diff options
Diffstat (limited to 'drivers/dma')
| -rw-r--r-- | drivers/dma/Kconfig | 34 | ||||
| -rw-r--r-- | drivers/dma/Makefile | 5 | ||||
| -rw-r--r-- | drivers/dma/caam_dma.c | 463 | ||||
| -rw-r--r-- | drivers/dma/fsl-dpaa2-qdma/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/dma/fsl-dpaa2-qdma/Makefile | 3 | ||||
| -rw-r--r-- | drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 825 | ||||
| -rw-r--r-- | drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 153 | ||||
| -rw-r--r-- | drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 366 | ||||
| -rw-r--r-- | drivers/dma/fsl-dpaa2-qdma/dpdmai.h | 177 | ||||
| -rw-r--r-- | drivers/dma/fsl-edma-common.c | 16 | ||||
| -rw-r--r-- | drivers/dma/fsl-edma-common.h | 3 | ||||
| -rw-r--r-- | drivers/dma/fsl-edma-v3.c | 1151 | ||||
| -rw-r--r-- | drivers/dma/fsl-edma.c | 9 | ||||
| -rw-r--r-- | drivers/dma/imx-sdma.c | 710 | ||||
| -rw-r--r-- | drivers/dma/mxs-dma.c | 161 | ||||
| -rw-r--r-- | drivers/dma/pxp/Kconfig | 22 | ||||
| -rw-r--r-- | drivers/dma/pxp/Makefile | 3 | ||||
| -rw-r--r-- | drivers/dma/pxp/pxp_device.c | 897 | ||||
| -rw-r--r-- | drivers/dma/pxp/pxp_dma_v2.c | 1849 | ||||
| -rw-r--r-- | drivers/dma/pxp/pxp_dma_v3.c | 8153 | ||||
| -rw-r--r-- | drivers/dma/pxp/reg_bitfields.h | 266 | ||||
| -rw-r--r-- | drivers/dma/pxp/regs-pxp_v2.h | 1139 | ||||
| -rw-r--r-- | drivers/dma/pxp/regs-pxp_v3.h | 26939 |
23 files changed, 43185 insertions, 168 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 7af874b69ffb..5be6f69d0f47 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -131,6 +131,24 @@ config COH901318 help Enable support for ST-Ericsson COH 901 318 DMA. +config CRYPTO_DEV_FSL_CAAM_DMA + tristate "CAAM DMA engine support" + depends on CRYPTO_DEV_FSL_CAAM_JR + default n + select DMA_ENGINE + select ASYNC_CORE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Selecting this will offload the DMA operations for users of + the scatter gather memcopy API to the CAAM via job rings. The + CAAM is a hardware module that provides hardware acceleration to + cryptographic operations. It has a built-in DMA controller that can + be programmed to read/write cryptographic data. This module defines + a DMA driver that uses the DMA capabilities of the CAAM. + + To compile this as a module, choose M here: the module + will be called caam_dma. + config DMA_BCM2835 tristate "BCM2835 DMA engine support" depends on ARCH_BCM2835 @@ -227,6 +245,17 @@ config FSL_QDMA or dequeuing DMA jobs from, different work queues. This module can be found on NXP Layerscape SoCs. The qdma driver only work on SoCs with a DPAA hardware block. +config FSL_EDMA_V3 + tristate "Freescale eDMA v3 engine support" + depends on OF + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support the Freescale eDMA v3 engine with programmable channel. + This driver is based on FSL_EDMA but big changes come such as + different interrupt for different channel, different register + scope for different channel. + This module can be found on Freescale i.MX8QM. config FSL_RAID tristate "Freescale RAID engine Support" @@ -409,6 +438,8 @@ config MXS_DMA Support the MXS DMA engine. This engine including APBH-DMA and APBX-DMA is integrated into some Freescale chips. +source "drivers/dma/pxp/Kconfig" + config MX3_IPU bool "MX3x Image Processing Unit support" depends on ARCH_MXC @@ -651,7 +682,6 @@ config ZX_DMA help Support the DMA engine for ZTE ZX family platform devices. - # driver files source "drivers/dma/bestcomm/Kconfig" @@ -669,6 +699,8 @@ source "drivers/dma/sh/Kconfig" source "drivers/dma/ti/Kconfig" +source "drivers/dma/fsl-dpaa2-qdma/Kconfig" + # clients comment "DMA Clients" depends on DMA_ENGINE diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f5ce8665e944..6c977c171706 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DW_EDMA) += dw-edma/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o +obj-$(CONFIG_FSL_EDMA_V3) += fsl-edma-v3.o obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o @@ -59,6 +60,8 @@ obj-$(CONFIG_PCH_DMA) += pch_dma.o obj-$(CONFIG_PL330_DMA) += pl330.o obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ obj-$(CONFIG_PXA_DMA) += pxa_dma.o +obj-$(CONFIG_MXC_PXP_V2) += pxp/ +obj-$(CONFIG_MXC_PXP_V3) += pxp/ obj-$(CONFIG_RENESAS_DMA) += sh/ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o @@ -75,6 +78,8 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o obj-$(CONFIG_XGENE_DMA) += xgene-dma.o obj-$(CONFIG_ZX_DMA) += zx_dma.o obj-$(CONFIG_ST_FDMA) += st_fdma.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_DMA) += caam_dma.o +obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/ obj-y += mediatek/ obj-y += qcom/ diff --git a/drivers/dma/caam_dma.c b/drivers/dma/caam_dma.c new file mode 100644 index 000000000000..2cd47c9b3ec5 --- /dev/null +++ b/drivers/dma/caam_dma.c @@ -0,0 +1,463 @@ +/* + * caam support for SG DMA + * + * Copyright 2016 Freescale Semiconductor, Inc + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/dma-mapping.h> +#include <linux/dmaengine.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "dmaengine.h" + +#include "../crypto/caam/regs.h" +#include "../crypto/caam/jr.h" +#include "../crypto/caam/error.h" +#include "../crypto/caam/desc_constr.h" + +#define DESC_DMA_MEMCPY_LEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN_MIN) / \ + CAAM_CMD_SZ) + +/* + * This is max chunk size of a DMA transfer. If a buffer is larger than this + * value it is internally broken into chunks of max CAAM_DMA_CHUNK_SIZE bytes + * and for each chunk a DMA transfer request is issued. + * This value is the largest number on 16 bits that is a multiple of 256 bytes + * (the largest configurable CAAM DMA burst size). + */ +#define CAAM_DMA_CHUNK_SIZE 65280 + +struct caam_dma_sh_desc { + u32 desc[DESC_DMA_MEMCPY_LEN] ____cacheline_aligned; + dma_addr_t desc_dma; +}; + +/* caam dma extended descriptor */ +struct caam_dma_edesc { + struct dma_async_tx_descriptor async_tx; + struct list_head node; + struct caam_dma_ctx *ctx; + dma_addr_t src_dma; + dma_addr_t dst_dma; + unsigned int src_len; + unsigned int dst_len; + u32 jd[] ____cacheline_aligned; +}; + +/* + * caam_dma_ctx - per jr/channel context + * @chan: dma channel used by async_tx API + * @node: list_head used to attach to the global dma_ctx_list + * @jrdev: Job Ring device + * @pending_q: queue of pending (submitted, but not enqueued) jobs + * @done_not_acked: jobs that have been completed by jr, but maybe not acked + * @edesc_lock: protects extended descriptor + */ +struct caam_dma_ctx { + struct dma_chan chan; + struct list_head node; + struct device *jrdev; + struct list_head pending_q; + struct list_head done_not_acked; + spinlock_t edesc_lock; +}; + +static struct dma_device *dma_dev; +static struct caam_dma_sh_desc *dma_sh_desc; +static LIST_HEAD(dma_ctx_list); + +static dma_cookie_t caam_dma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct caam_dma_edesc *edesc = NULL; + struct caam_dma_ctx *ctx = NULL; + dma_cookie_t cookie; + + edesc = container_of(tx, struct caam_dma_edesc, async_tx); + ctx = container_of(tx->chan, struct caam_dma_ctx, chan); + + spin_lock_bh(&ctx->edesc_lock); + + cookie = dma_cookie_assign(tx); + list_add_tail(&edesc->node, &ctx->pending_q); + + spin_unlock_bh(&ctx->edesc_lock); + + return cookie; +} + +static void caam_jr_chan_free_edesc(struct caam_dma_edesc *edesc) +{ + struct caam_dma_ctx *ctx = edesc->ctx; + struct caam_dma_edesc *_edesc = NULL; + + spin_lock_bh(&ctx->edesc_lock); + + list_add_tail(&edesc->node, &ctx->done_not_acked); + list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) { + if (async_tx_test_ack(&edesc->async_tx)) { + list_del(&edesc->node); + kfree(edesc); + } + } + + spin_unlock_bh(&ctx->edesc_lock); +} + +static void caam_dma_done(struct device *dev, u32 *hwdesc, u32 err, + void *context) +{ + struct caam_dma_edesc *edesc = context; + struct caam_dma_ctx *ctx = edesc->ctx; + dma_async_tx_callback callback; + void *callback_param; + + if (err) + caam_jr_strstatus(ctx->jrdev, err); + + dma_run_dependencies(&edesc->async_tx); + + spin_lock_bh(&ctx->edesc_lock); + dma_cookie_complete(&edesc->async_tx); + spin_unlock_bh(&ctx->edesc_lock); + + callback = edesc->async_tx.callback; + callback_param = edesc->async_tx.callback_param; + + dma_descriptor_unmap(&edesc->async_tx); + + caam_jr_chan_free_edesc(edesc); + + if (callback) + callback(callback_param); +} + +static void caam_dma_memcpy_init_job_desc(struct caam_dma_edesc *edesc) +{ + u32 *jd = edesc->jd; + u32 *sh_desc = dma_sh_desc->desc; + dma_addr_t desc_dma = dma_sh_desc->desc_dma; + + /* init the job descriptor */ + init_job_desc_shared(jd, desc_dma, desc_len(sh_desc), HDR_REVERSE); + + /* set SEQIN PTR */ + append_seq_in_ptr(jd, edesc->src_dma, edesc->src_len, 0); + + /* set SEQOUT PTR */ + append_seq_out_ptr(jd, edesc->dst_dma, edesc->dst_len, 0); + + print_hex_dump_debug("caam dma desc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, jd, desc_bytes(jd), 1); +} + +static struct dma_async_tx_descriptor * +caam_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct caam_dma_edesc *edesc; + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + + edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN, GFP_DMA | GFP_NOWAIT); + if (!edesc) + return ERR_PTR(-ENOMEM); + + dma_async_tx_descriptor_init(&edesc->async_tx, chan); + edesc->async_tx.tx_submit = caam_dma_tx_submit; + edesc->async_tx.flags = flags; + edesc->async_tx.cookie = -EBUSY; + + edesc->src_dma = src; + edesc->src_len = len; + edesc->dst_dma = dst; + edesc->dst_len = len; + edesc->ctx = ctx; + + caam_dma_memcpy_init_job_desc(edesc); + + return &edesc->async_tx; +} + +/* This function can be called in an interrupt context */ +static void caam_dma_issue_pending(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + struct caam_dma_edesc *edesc, *_edesc; + + spin_lock_bh(&ctx->edesc_lock); + list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) { + int ret = caam_jr_enqueue(ctx->jrdev, edesc->jd, + caam_dma_done, edesc); + if (ret != -EINPROGRESS) + break; + list_del(&edesc->node); + } + spin_unlock_bh(&ctx->edesc_lock); +} + +static void caam_dma_free_chan_resources(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + struct caam_dma_edesc *edesc, *_edesc; + + spin_lock_bh(&ctx->edesc_lock); + list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) { + list_del(&edesc->node); + kfree(edesc); + } + list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) { + list_del(&edesc->node); + kfree(edesc); + } + spin_unlock_bh(&ctx->edesc_lock); +} + +static int caam_dma_jr_chan_bind(void) +{ + struct device *jrdev; + struct caam_dma_ctx *ctx; + int bonds = 0; + int i; + + for (i = 0; i < caam_jr_driver_probed(); i++) { + jrdev = caam_jridx_alloc(i); + if (IS_ERR(jrdev)) { + pr_err("job ring device %d allocation failed\n", i); + continue; + } + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + caam_jr_free(jrdev); + continue; + } + + ctx->chan.device = dma_dev; + ctx->chan.private = ctx; + + ctx->jrdev = jrdev; + + INIT_LIST_HEAD(&ctx->pending_q); + INIT_LIST_HEAD(&ctx->done_not_acked); + INIT_LIST_HEAD(&ctx->node); + spin_lock_init(&ctx->edesc_lock); + + dma_cookie_init(&ctx->chan); + + /* add the context of this channel to the context list */ + list_add_tail(&ctx->node, &dma_ctx_list); + + /* add this channel to the device chan list */ + list_add_tail(&ctx->chan.device_node, &dma_dev->channels); + + bonds++; + } + + return bonds; +} + +static inline void caam_jr_dma_free(struct dma_chan *chan) +{ + struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx, + chan); + + list_del(&ctx->node); + list_del(&chan->device_node); + caam_jr_free(ctx->jrdev); + kfree(ctx); +} + +static void set_caam_dma_desc(u32 *desc) +{ + u32 *jmp_cmd; + + /* dma shared descriptor */ + init_sh_desc(desc, HDR_SHARE_NEVER | (1 << HDR_START_IDX_SHIFT)); + + /* REG1 = CAAM_DMA_CHUNK_SIZE */ + append_math_add_imm_u32(desc, REG1, ZERO, IMM, CAAM_DMA_CHUNK_SIZE); + + /* REG0 = SEQINLEN - CAAM_DMA_CHUNK_SIZE */ + append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, CAAM_DMA_CHUNK_SIZE); + + /* + * if (REG0 > 0) + * jmp to LABEL1 + */ + jmp_cmd = append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N | + JUMP_COND_MATH_Z); + + /* REG1 = SEQINLEN */ + append_math_sub(desc, REG1, SEQINLEN, ZERO, CAAM_CMD_SZ); + + /* LABEL1 */ + set_jump_tgt_here(desc, jmp_cmd); + + /* VARSEQINLEN = REG1 */ + append_math_add(desc, VARSEQINLEN, REG1, ZERO, CAAM_CMD_SZ); + + /* VARSEQOUTLEN = REG1 */ + append_math_add(desc, VARSEQOUTLEN, REG1, ZERO, CAAM_CMD_SZ); + + /* do FIFO STORE */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_METADATA | LDST_VLF); + + /* do FIFO LOAD */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | + FIFOLD_TYPE_IFIFO | LDST_VLF); + + /* + * if (REG0 > 0) + * jmp 0xF8 (after shared desc header) + */ + append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N | + JUMP_COND_MATH_Z | 0xF8); + + print_hex_dump_debug("caam dma shdesc@" __stringify(__LINE__) ": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), + 1); +} + +static int caam_dma_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *ctrldev = dev->parent; + struct dma_chan *chan, *_chan; + u32 *sh_desc; + int err = -ENOMEM; + int bonds; + + if (!caam_jr_driver_probed()) { + dev_info(dev, "Defer probing after JR driver probing\n"); + return -EPROBE_DEFER; + } + + dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL); + if (!dma_dev) + return -ENOMEM; + + dma_sh_desc = kzalloc(sizeof(*dma_sh_desc), GFP_KERNEL | GFP_DMA); + if (!dma_sh_desc) + goto desc_err; + + sh_desc = dma_sh_desc->desc; + set_caam_dma_desc(sh_desc); + dma_sh_desc->desc_dma = dma_map_single(ctrldev, sh_desc, + desc_bytes(sh_desc), + DMA_TO_DEVICE); + if (dma_mapping_error(ctrldev, dma_sh_desc->desc_dma)) { + dev_err(dev, "unable to map dma descriptor\n"); + goto map_err; + } + + INIT_LIST_HEAD(&dma_dev->channels); + + bonds = caam_dma_jr_chan_bind(); + if (!bonds) { + err = -ENODEV; + goto jr_bind_err; + } + + dma_dev->dev = dev; + dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; + dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); + dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask); + dma_dev->device_tx_status = dma_cookie_status; + dma_dev->device_issue_pending = caam_dma_issue_pending; + dma_dev->device_prep_dma_memcpy = caam_dma_prep_memcpy; + dma_dev->device_free_chan_resources = caam_dma_free_chan_resources; + + err = dma_async_device_register(dma_dev); + if (err) { + dev_err(dev, "Failed to register CAAM DMA engine\n"); + goto jr_bind_err; + } + + dev_info(dev, "caam dma support with %d job rings\n", bonds); + + return err; + +jr_bind_err: + list_for_each_entry_safe(chan, _chan, &dma_dev->channels, device_node) + caam_jr_dma_free(chan); + + dma_unmap_single(ctrldev, dma_sh_desc->desc_dma, desc_bytes(sh_desc), + DMA_TO_DEVICE); +map_err: + kfree(dma_sh_desc); +desc_err: + kfree(dma_dev); + return err; +} + +static int caam_dma_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *ctrldev = dev->parent; + struct caam_dma_ctx *ctx, *_ctx; + + dma_async_device_unregister(dma_dev); + + list_for_each_entry_safe(ctx, _ctx, &dma_ctx_list, node) { + list_del(&ctx->node); + caam_jr_free(ctx->jrdev); + kfree(ctx); + } + + dma_unmap_single(ctrldev, dma_sh_desc->desc_dma, + desc_bytes(dma_sh_desc->desc), DMA_TO_DEVICE); + + kfree(dma_sh_desc); + kfree(dma_dev); + + dev_info(dev, "caam dma support disabled\n"); + return 0; +} + +static struct platform_driver caam_dma_driver = { + .driver = { + .name = "caam-dma", + }, + .probe = caam_dma_probe, + .remove = caam_dma_remove, +}; +module_platform_driver(caam_dma_driver); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("NXP CAAM support for DMA engine"); +MODULE_AUTHOR("NXP Semiconductors"); +MODULE_ALIAS("platform:caam-dma"); diff --git a/drivers/dma/fsl-dpaa2-qdma/Kconfig b/drivers/dma/fsl-dpaa2-qdma/Kconfig new file mode 100644 index 000000000000..258ed6be934d --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/Kconfig @@ -0,0 +1,9 @@ +menuconfig FSL_DPAA2_QDMA + tristate "NXP DPAA2 QDMA" + depends on ARM64 + depends on FSL_MC_BUS && FSL_MC_DPIO + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + NXP Data Path Acceleration Architecture 2 QDMA driver, + using the NXP MC bus driver. diff --git a/drivers/dma/fsl-dpaa2-qdma/Makefile b/drivers/dma/fsl-dpaa2-qdma/Makefile new file mode 100644 index 000000000000..c1d0226f2bd7 --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile for the NXP DPAA2 qDMA controllers +obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c new file mode 100644 index 000000000000..c70a7965f140 --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright 2019 NXP + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/dmapool.h> +#include <linux/of_irq.h> +#include <linux/iommu.h> +#include <linux/sys_soc.h> +#include <linux/fsl/mc.h> +#include <soc/fsl/dpaa2-io.h> + +#include "../virt-dma.h" +#include "dpdmai.h" +#include "dpaa2-qdma.h" + +static bool smmu_disable = true; + +static struct dpaa2_qdma_chan *to_dpaa2_qdma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct dpaa2_qdma_chan, vchan.chan); +} + +static struct dpaa2_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd) +{ + return container_of(vd, struct dpaa2_qdma_comp, vdesc); +} + +static int dpaa2_qdma_alloc_chan_resources(struct dma_chan *chan) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma; + struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev; + + dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev, + sizeof(struct dpaa2_fd), + sizeof(struct dpaa2_fd), 0); + if (!dpaa2_chan->fd_pool) + goto err; + + dpaa2_chan->fl_pool = dma_pool_create("fl_pool", dev, + sizeof(struct dpaa2_fl_entry), + sizeof(struct dpaa2_fl_entry), 0); + if (!dpaa2_chan->fl_pool) + goto err_fd; + + dpaa2_chan->sdd_pool = + dma_pool_create("sdd_pool", dev, + sizeof(struct dpaa2_qdma_sd_d), + sizeof(struct dpaa2_qdma_sd_d), 0); + if (!dpaa2_chan->sdd_pool) + goto err_fl; + + return dpaa2_qdma->desc_allocated++; +err_fl: + dma_pool_destroy(dpaa2_chan->fl_pool); +err_fd: + dma_pool_destroy(dpaa2_chan->fd_pool); +err: + return -ENOMEM; +} + +static void dpaa2_qdma_free_chan_resources(struct dma_chan *chan) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma; + unsigned long flags; + + LIST_HEAD(head); + + spin_lock_irqsave(&dpaa2_chan->vchan.lock, flags); + vchan_get_all_descriptors(&dpaa2_chan->vchan, &head); + spin_unlock_irqrestore(&dpaa2_chan->vchan.lock, flags); + + vchan_dma_desc_free_list(&dpaa2_chan->vchan, &head); + + dpaa2_dpdmai_free_comp(dpaa2_chan, &dpaa2_chan->comp_used); + dpaa2_dpdmai_free_comp(dpaa2_chan, &dpaa2_chan->comp_free); + + dma_pool_destroy(dpaa2_chan->fd_pool); + dma_pool_destroy(dpaa2_chan->fl_pool); + dma_pool_destroy(dpaa2_chan->sdd_pool); + dpaa2_qdma->desc_allocated--; +} + +/* + * Request a command descriptor for enqueue. + */ +static struct dpaa2_qdma_comp * +dpaa2_qdma_request_desc(struct dpaa2_qdma_chan *dpaa2_chan) +{ + struct dpaa2_qdma_priv *qdma_priv = dpaa2_chan->qdma->priv; + struct device *dev = &qdma_priv->dpdmai_dev->dev; + struct dpaa2_qdma_comp *comp_temp = NULL; + unsigned long flags; + + spin_lock_irqsave(&dpaa2_chan->queue_lock, flags); + if (list_empty(&dpaa2_chan->comp_free)) { + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags); + comp_temp = kzalloc(sizeof(*comp_temp), GFP_NOWAIT); + if (!comp_temp) + goto err; + comp_temp->fd_virt_addr = + dma_pool_alloc(dpaa2_chan->fd_pool, GFP_NOWAIT, + &comp_temp->fd_bus_addr); + if (!comp_temp->fd_virt_addr) + goto err_comp; + + comp_temp->fl_virt_addr = + dma_pool_alloc(dpaa2_chan->fl_pool, GFP_NOWAIT, + &comp_temp->fl_bus_addr); + if (!comp_temp->fl_virt_addr) + goto err_fd_virt; + + comp_temp->desc_virt_addr = + dma_pool_alloc(dpaa2_chan->sdd_pool, GFP_NOWAIT, + &comp_temp->desc_bus_addr); + if (!comp_temp->desc_virt_addr) + goto err_fl_virt; + + comp_temp->qchan = dpaa2_chan; + return comp_temp; + } + + comp_temp = list_first_entry(&dpaa2_chan->comp_free, + struct dpaa2_qdma_comp, list); + list_del(&comp_temp->list); + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags); + + comp_temp->qchan = dpaa2_chan; + + return comp_temp; + +err_fl_virt: + dma_pool_free(dpaa2_chan->fl_pool, + comp_temp->fl_virt_addr, + comp_temp->fl_bus_addr); +err_fd_virt: + dma_pool_free(dpaa2_chan->fd_pool, + comp_temp->fd_virt_addr, + comp_temp->fd_bus_addr); +err_comp: + kfree(comp_temp); +err: + dev_err(dev, "Failed to request descriptor\n"); + return NULL; +} + +static void +dpaa2_qdma_populate_fd(u32 format, struct dpaa2_qdma_comp *dpaa2_comp) +{ + struct dpaa2_fd *fd; + + fd = dpaa2_comp->fd_virt_addr; + memset(fd, 0, sizeof(struct dpaa2_fd)); + + /* fd populated */ + dpaa2_fd_set_addr(fd, dpaa2_comp->fl_bus_addr); + + /* + * Bypass memory translation, Frame list format, short length disable + * we need to disable BMT if fsl-mc use iova addr + */ + if (smmu_disable) + dpaa2_fd_set_bpid(fd, QMAN_FD_BMT_ENABLE); + dpaa2_fd_set_format(fd, QMAN_FD_FMT_ENABLE | QMAN_FD_SL_DISABLE); + + dpaa2_fd_set_frc(fd, format | QDMA_SER_CTX); +} + +/* first frame list for descriptor buffer */ +static void +dpaa2_qdma_populate_first_framel(struct dpaa2_fl_entry *f_list, + struct dpaa2_qdma_comp *dpaa2_comp, + bool wrt_changed) +{ + struct dpaa2_qdma_sd_d *sdd; + + sdd = dpaa2_comp->desc_virt_addr; + memset(sdd, 0, 2 * (sizeof(*sdd))); + + /* source descriptor CMD */ + sdd->cmd = cpu_to_le32(QDMA_SD_CMD_RDTTYPE_COHERENT); + sdd++; + + /* dest descriptor CMD */ + if (wrt_changed) + sdd->cmd = cpu_to_le32(LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT); + else + sdd->cmd = cpu_to_le32(QDMA_DD_CMD_WRTTYPE_COHERENT); + + memset(f_list, 0, sizeof(struct dpaa2_fl_entry)); + + /* first frame list to source descriptor */ + dpaa2_fl_set_addr(f_list, dpaa2_comp->desc_bus_addr); + dpaa2_fl_set_len(f_list, 0x20); + dpaa2_fl_set_format(f_list, QDMA_FL_FMT_SBF | QDMA_FL_SL_LONG); + + /* bypass memory translation */ + if (smmu_disable) + f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); +} + +/* source and destination frame list */ +static void +dpaa2_qdma_populate_frames(struct dpaa2_fl_entry *f_list, + dma_addr_t dst, dma_addr_t src, + size_t len, uint8_t fmt) +{ + /* source frame list to source buffer */ + memset(f_list, 0, sizeof(struct dpaa2_fl_entry)); + + dpaa2_fl_set_addr(f_list, src); + dpaa2_fl_set_len(f_list, len); + + /* single buffer frame or scatter gather frame */ + dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG)); + + /* bypass memory translation */ + if (smmu_disable) + f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); + + f_list++; + + /* destination frame list to destination buffer */ + memset(f_list, 0, sizeof(struct dpaa2_fl_entry)); + + dpaa2_fl_set_addr(f_list, dst); + dpaa2_fl_set_len(f_list, len); + dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG)); + /* single buffer frame or scatter gather frame */ + dpaa2_fl_set_final(f_list, QDMA_FL_F); + /* bypass memory translation */ + if (smmu_disable) + f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); +} + +static struct dma_async_tx_descriptor +*dpaa2_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, + dma_addr_t src, size_t len, ulong flags) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_comp *dpaa2_comp; + struct dpaa2_fl_entry *f_list; + bool wrt_changed; + + dpaa2_qdma = dpaa2_chan->qdma; + dpaa2_comp = dpaa2_qdma_request_desc(dpaa2_chan); + if (!dpaa2_comp) + return NULL; + + wrt_changed = (bool)dpaa2_qdma->qdma_wrtype_fixup; + + /* populate Frame descriptor */ + dpaa2_qdma_populate_fd(QDMA_FD_LONG_FORMAT, dpaa2_comp); + + f_list = dpaa2_comp->fl_virt_addr; + + /* first frame list for descriptor buffer (logn format) */ + dpaa2_qdma_populate_first_framel(f_list, dpaa2_comp, wrt_changed); + + f_list++; + + dpaa2_qdma_populate_frames(f_list, dst, src, len, QDMA_FL_FMT_SBF); + + return vchan_tx_prep(&dpaa2_chan->vchan, &dpaa2_comp->vdesc, flags); +} + +static void dpaa2_qdma_issue_pending(struct dma_chan *chan) +{ + struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan); + struct dpaa2_qdma_comp *dpaa2_comp; + struct virt_dma_desc *vdesc; + struct dpaa2_fd *fd; + unsigned long flags; + int err; + + spin_lock_irqsave(&dpaa2_chan->queue_lock, flags); + spin_lock(&dpaa2_chan->vchan.lock); + if (vchan_issue_pending(&dpaa2_chan->vchan)) { + vdesc = vchan_next_desc(&dpaa2_chan->vchan); + if (!vdesc) + goto err_enqueue; + dpaa2_comp = to_fsl_qdma_comp(vdesc); + + fd = dpaa2_comp->fd_virt_addr; + + list_del(&vdesc->node); + list_add_tail(&dpaa2_comp->list, &dpaa2_chan->comp_used); + + err = dpaa2_io_service_enqueue_fq(NULL, dpaa2_chan->fqid, fd); + if (err) { + list_del(&dpaa2_comp->list); + list_add_tail(&dpaa2_comp->list, + &dpaa2_chan->comp_free); + } + } +err_enqueue: + spin_unlock(&dpaa2_chan->vchan.lock); + spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags); +} + +static int __cold dpaa2_qdma_setup(struct fsl_mc_device *ls_dev) +{ + struct dpaa2_qdma_priv_per_prio *ppriv; + struct device *dev = &ls_dev->dev; + struct dpaa2_qdma_priv *priv; + u8 prio_def = DPDMAI_PRIO_NUM; + int err = -EINVAL; + int i; + + priv = dev_get_drvdata(dev); + + priv->dev = dev; + priv->dpqdma_id = ls_dev->obj_desc.id; + + /* Get the handle for the DPDMAI this interface is associate with */ + err = dpdmai_open(priv->mc_io, 0, priv->dpqdma_id, &ls_dev->mc_handle); + if (err) { + dev_err(dev, "dpdmai_open() failed\n"); + return err; + } + + dev_dbg(dev, "Opened dpdmai object successfully\n"); + + err = dpdmai_get_attributes(priv->mc_io, 0, ls_dev->mc_handle, + &priv->dpdmai_attr); + if (err) { + dev_err(dev, "dpdmai_get_attributes() failed\n"); + goto exit; + } + + if (priv->dpdmai_attr.version.major > DPDMAI_VER_MAJOR) { + dev_err(dev, "DPDMAI major version mismatch\n" + "Found %u.%u, supported version is %u.%u\n", + priv->dpdmai_attr.version.major, + priv->dpdmai_attr.version.minor, + DPDMAI_VER_MAJOR, DPDMAI_VER_MINOR); + goto exit; + } + + if (priv->dpdmai_attr.version.minor > DPDMAI_VER_MINOR) { + dev_err(dev, "DPDMAI minor version mismatch\n" + "Found %u.%u, supported version is %u.%u\n", + priv->dpdmai_attr.version.major, + priv->dpdmai_attr.version.minor, + DPDMAI_VER_MAJOR, DPDMAI_VER_MINOR); + goto exit; + } + + priv->num_pairs = min(priv->dpdmai_attr.num_of_priorities, prio_def); + ppriv = kcalloc(priv->num_pairs, sizeof(*ppriv), GFP_KERNEL); + if (!ppriv) { + err = -ENOMEM; + goto exit; + } + priv->ppriv = ppriv; + + for (i = 0; i < priv->num_pairs; i++) { + err = dpdmai_get_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, + i, &priv->rx_queue_attr[i]); + if (err) { + dev_err(dev, "dpdmai_get_rx_queue() failed\n"); + goto exit; + } + ppriv->rsp_fqid = priv->rx_queue_attr[i].fqid; + + err = dpdmai_get_tx_queue(priv->mc_io, 0, ls_dev->mc_handle, + i, &priv->tx_fqid[i]); + if (err) { + dev_err(dev, "dpdmai_get_tx_queue() failed\n"); + goto exit; + } + ppriv->req_fqid = priv->tx_fqid[i]; + ppriv->prio = i; + ppriv->priv = priv; + ppriv++; + } + + return 0; +exit: + dpdmai_close(priv->mc_io, 0, ls_dev->mc_handle); + return err; +} + +static void dpaa2_qdma_fqdan_cb(struct dpaa2_io_notification_ctx *ctx) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = container_of(ctx, + struct dpaa2_qdma_priv_per_prio, nctx); + struct dpaa2_qdma_comp *dpaa2_comp, *_comp_tmp; + struct dpaa2_qdma_priv *priv = ppriv->priv; + u32 n_chans = priv->dpaa2_qdma->n_chans; + struct dpaa2_qdma_chan *qchan; + const struct dpaa2_fd *fd_eq; + const struct dpaa2_fd *fd; + struct dpaa2_dq *dq; + int is_last = 0; + int found; + u8 status; + int err; + int i; + + do { + err = dpaa2_io_service_pull_fq(NULL, ppriv->rsp_fqid, + ppriv->store); + } while (err); + + while (!is_last) { + do { + dq = dpaa2_io_store_next(ppriv->store, &is_last); + } while (!is_last && !dq); + if (!dq) { + dev_err(priv->dev, "FQID returned no valid frames!\n"); + continue; + } + + /* obtain FD and process the error */ + fd = dpaa2_dq_fd(dq); + + status = dpaa2_fd_get_ctrl(fd) & 0xff; + if (status) + dev_err(priv->dev, "FD error occurred\n"); + found = 0; + for (i = 0; i < n_chans; i++) { + qchan = &priv->dpaa2_qdma->chans[i]; + spin_lock(&qchan->queue_lock); + if (list_empty(&qchan->comp_used)) { + spin_unlock(&qchan->queue_lock); + continue; + } + list_for_each_entry_safe(dpaa2_comp, _comp_tmp, + &qchan->comp_used, list) { + fd_eq = dpaa2_comp->fd_virt_addr; + + if (le64_to_cpu(fd_eq->simple.addr) == + le64_to_cpu(fd->simple.addr)) { + spin_lock(&qchan->vchan.lock); + vchan_cookie_complete(& + dpaa2_comp->vdesc); + spin_unlock(&qchan->vchan.lock); + found = 1; + break; + } + } + spin_unlock(&qchan->queue_lock); + if (found) + break; + } + } + + dpaa2_io_service_rearm(NULL, ctx); +} + +static int __cold dpaa2_qdma_dpio_setup(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv; + struct device *dev = priv->dev; + int err = -EINVAL; + int i, num; + + num = priv->num_pairs; + ppriv = priv->ppriv; + for (i = 0; i < num; i++) { + ppriv->nctx.is_cdan = 0; + ppriv->nctx.desired_cpu = DPAA2_IO_ANY_CPU; + ppriv->nctx.id = ppriv->rsp_fqid; + ppriv->nctx.cb = dpaa2_qdma_fqdan_cb; + err = dpaa2_io_service_register(NULL, &ppriv->nctx, dev); + if (err) { + dev_err(dev, "Notification register failed\n"); + goto err_service; + } + + ppriv->store = + dpaa2_io_store_create(DPAA2_QDMA_STORE_SIZE, dev); + if (!ppriv->store) { + dev_err(dev, "dpaa2_io_store_create() failed\n"); + goto err_store; + } + + ppriv++; + } + return 0; + +err_store: + dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev); +err_service: + ppriv--; + while (ppriv >= priv->ppriv) { + dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev); + dpaa2_io_store_destroy(ppriv->store); + ppriv--; + } + return err; +} + +static void dpaa2_dpmai_store_free(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = priv->ppriv; + int i; + + for (i = 0; i < priv->num_pairs; i++) { + dpaa2_io_store_destroy(ppriv->store); + ppriv++; + } +} + +static void dpaa2_dpdmai_dpio_free(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = priv->ppriv; + struct device *dev = priv->dev; + int i; + + for (i = 0; i < priv->num_pairs; i++) { + dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev); + ppriv++; + } +} + +static int __cold dpaa2_dpdmai_bind(struct dpaa2_qdma_priv *priv) +{ + struct dpdmai_rx_queue_cfg rx_queue_cfg; + struct dpaa2_qdma_priv_per_prio *ppriv; + struct device *dev = priv->dev; + struct fsl_mc_device *ls_dev; + int i, num; + int err; + + ls_dev = to_fsl_mc_device(dev); + num = priv->num_pairs; + ppriv = priv->ppriv; + for (i = 0; i < num; i++) { + rx_queue_cfg.options = DPDMAI_QUEUE_OPT_USER_CTX | + DPDMAI_QUEUE_OPT_DEST; + rx_queue_cfg.user_ctx = ppriv->nctx.qman64; + rx_queue_cfg.dest_cfg.dest_type = DPDMAI_DEST_DPIO; + rx_queue_cfg.dest_cfg.dest_id = ppriv->nctx.dpio_id; + rx_queue_cfg.dest_cfg.priority = ppriv->prio; + err = dpdmai_set_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, + rx_queue_cfg.dest_cfg.priority, + &rx_queue_cfg); + if (err) { + dev_err(dev, "dpdmai_set_rx_queue() failed\n"); + return err; + } + + ppriv++; + } + + return 0; +} + +static int __cold dpaa2_dpdmai_dpio_unbind(struct dpaa2_qdma_priv *priv) +{ + struct dpaa2_qdma_priv_per_prio *ppriv = priv->ppriv; + struct device *dev = priv->dev; + struct fsl_mc_device *ls_dev; + int err = 0; + int i; + + ls_dev = to_fsl_mc_device(dev); + + for (i = 0; i < priv->num_pairs; i++) { + ppriv->nctx.qman64 = 0; + ppriv->nctx.dpio_id = 0; + ppriv++; + } + + err = dpdmai_reset(priv->mc_io, 0, ls_dev->mc_handle); + if (err) + dev_err(dev, "dpdmai_reset() failed\n"); + + return err; +} + +static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan, + struct list_head *head) +{ + struct dpaa2_qdma_comp *comp_tmp, *_comp_tmp; + unsigned long flags; + + list_for_each_entry_safe(comp_tmp, _comp_tmp, + head, list) { + spin_lock_irqsave(&qchan->queue_lock, flags); + list_del(&comp_tmp->list); + spin_unlock_irqrestore(&qchan->queue_lock, flags); + dma_pool_free(qchan->fd_pool, + comp_tmp->fd_virt_addr, + comp_tmp->fd_bus_addr); + dma_pool_free(qchan->fl_pool, + comp_tmp->fl_virt_addr, + comp_tmp->fl_bus_addr); + dma_pool_free(qchan->sdd_pool, + comp_tmp->desc_virt_addr, + comp_tmp->desc_bus_addr); + kfree(comp_tmp); + } +} + +static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma) +{ + struct dpaa2_qdma_chan *qchan; + int num, i; + + num = dpaa2_qdma->n_chans; + for (i = 0; i < num; i++) { + qchan = &dpaa2_qdma->chans[i]; + dpaa2_dpdmai_free_comp(qchan, &qchan->comp_used); + dpaa2_dpdmai_free_comp(qchan, &qchan->comp_free); + dma_pool_destroy(qchan->fd_pool); + dma_pool_destroy(qchan->fl_pool); + dma_pool_destroy(qchan->sdd_pool); + } +} + +static void dpaa2_qdma_free_desc(struct virt_dma_desc *vdesc) +{ + struct dpaa2_qdma_comp *dpaa2_comp; + struct dpaa2_qdma_chan *qchan; + unsigned long flags; + + dpaa2_comp = to_fsl_qdma_comp(vdesc); + qchan = dpaa2_comp->qchan; + spin_lock_irqsave(&qchan->queue_lock, flags); + list_del(&dpaa2_comp->list); + list_add_tail(&dpaa2_comp->list, &qchan->comp_free); + spin_unlock_irqrestore(&qchan->queue_lock, flags); +} + +static int dpaa2_dpdmai_init_channels(struct dpaa2_qdma_engine *dpaa2_qdma) +{ + struct dpaa2_qdma_priv *priv = dpaa2_qdma->priv; + struct dpaa2_qdma_chan *dpaa2_chan; + int num = priv->num_pairs; + int i; + + INIT_LIST_HEAD(&dpaa2_qdma->dma_dev.channels); + for (i = 0; i < dpaa2_qdma->n_chans; i++) { + dpaa2_chan = &dpaa2_qdma->chans[i]; + dpaa2_chan->qdma = dpaa2_qdma; + dpaa2_chan->fqid = priv->tx_fqid[i % num]; + dpaa2_chan->vchan.desc_free = dpaa2_qdma_free_desc; + vchan_init(&dpaa2_chan->vchan, &dpaa2_qdma->dma_dev); + spin_lock_init(&dpaa2_chan->queue_lock); + INIT_LIST_HEAD(&dpaa2_chan->comp_used); + INIT_LIST_HEAD(&dpaa2_chan->comp_free); + } + return 0; +} + +static int dpaa2_qdma_probe(struct fsl_mc_device *dpdmai_dev) +{ + struct device *dev = &dpdmai_dev->dev; + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_priv *priv; + int err; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + dev_set_drvdata(dev, priv); + priv->dpdmai_dev = dpdmai_dev; + + priv->iommu_domain = iommu_get_domain_for_dev(dev); + if (priv->iommu_domain) + smmu_disable = false; + + /* obtain a MC portal */ + err = fsl_mc_portal_allocate(dpdmai_dev, 0, &priv->mc_io); + if (err) { + if (err == -ENXIO) + err = -EPROBE_DEFER; + else + dev_err(dev, "MC portal allocation failed\n"); + goto err_mcportal; + } + + /* DPDMAI initialization */ + err = dpaa2_qdma_setup(dpdmai_dev); + if (err) { + dev_err(dev, "dpaa2_dpdmai_setup() failed\n"); + goto err_dpdmai_setup; + } + + /* DPIO */ + err = dpaa2_qdma_dpio_setup(priv); + if (err) { + dev_err(dev, "dpaa2_dpdmai_dpio_setup() failed\n"); + goto err_dpio_setup; + } + + /* DPDMAI binding to DPIO */ + err = dpaa2_dpdmai_bind(priv); + if (err) { + dev_err(dev, "dpaa2_dpdmai_bind() failed\n"); + goto err_bind; + } + + /* DPDMAI enable */ + err = dpdmai_enable(priv->mc_io, 0, dpdmai_dev->mc_handle); + if (err) { + dev_err(dev, "dpdmai_enable() faile\n"); + goto err_enable; + } + + dpaa2_qdma = kzalloc(sizeof(*dpaa2_qdma), GFP_KERNEL); + if (!dpaa2_qdma) { + err = -ENOMEM; + goto err_eng; + } + + priv->dpaa2_qdma = dpaa2_qdma; + dpaa2_qdma->priv = priv; + + dpaa2_qdma->desc_allocated = 0; + dpaa2_qdma->n_chans = NUM_CH; + + dpaa2_dpdmai_init_channels(dpaa2_qdma); + + if (soc_device_match(soc_fixup_tuning)) + dpaa2_qdma->qdma_wrtype_fixup = true; + else + dpaa2_qdma->qdma_wrtype_fixup = false; + + dma_cap_set(DMA_PRIVATE, dpaa2_qdma->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, dpaa2_qdma->dma_dev.cap_mask); + dma_cap_set(DMA_MEMCPY, dpaa2_qdma->dma_dev.cap_mask); + + dpaa2_qdma->dma_dev.dev = dev; + dpaa2_qdma->dma_dev.device_alloc_chan_resources = + dpaa2_qdma_alloc_chan_resources; + dpaa2_qdma->dma_dev.device_free_chan_resources = + dpaa2_qdma_free_chan_resources; + dpaa2_qdma->dma_dev.device_tx_status = dma_cookie_status; + dpaa2_qdma->dma_dev.device_prep_dma_memcpy = dpaa2_qdma_prep_memcpy; + dpaa2_qdma->dma_dev.device_issue_pending = dpaa2_qdma_issue_pending; + + err = dma_async_device_register(&dpaa2_qdma->dma_dev); + if (err) { + dev_err(dev, "Can't register NXP QDMA engine.\n"); + goto err_dpaa2_qdma; + } + + return 0; + +err_dpaa2_qdma: + kfree(dpaa2_qdma); +err_eng: + dpdmai_disable(priv->mc_io, 0, dpdmai_dev->mc_handle); +err_enable: + dpaa2_dpdmai_dpio_unbind(priv); +err_bind: + dpaa2_dpmai_store_free(priv); + dpaa2_dpdmai_dpio_free(priv); +err_dpio_setup: + kfree(priv->ppriv); + dpdmai_close(priv->mc_io, 0, dpdmai_dev->mc_handle); +err_dpdmai_setup: + fsl_mc_portal_free(priv->mc_io); +err_mcportal: + kfree(priv); + dev_set_drvdata(dev, NULL); + return err; +} + +static int dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) +{ + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_priv *priv; + struct device *dev; + + dev = &ls_dev->dev; + priv = dev_get_drvdata(dev); + dpaa2_qdma = priv->dpaa2_qdma; + + dpdmai_disable(priv->mc_io, 0, ls_dev->mc_handle); + dpaa2_dpdmai_dpio_unbind(priv); + dpaa2_dpmai_store_free(priv); + dpaa2_dpdmai_dpio_free(priv); + dpdmai_close(priv->mc_io, 0, ls_dev->mc_handle); + fsl_mc_portal_free(priv->mc_io); + dev_set_drvdata(dev, NULL); + dpaa2_dpdmai_free_channels(dpaa2_qdma); + + dma_async_device_unregister(&dpaa2_qdma->dma_dev); + kfree(priv); + kfree(dpaa2_qdma); + + return 0; +} + +static const struct fsl_mc_device_id dpaa2_qdma_id_table[] = { + { + .vendor = FSL_MC_VENDOR_FREESCALE, + .obj_type = "dpdmai", + }, + { .vendor = 0x0 } +}; + +static struct fsl_mc_driver dpaa2_qdma_driver = { + .driver = { + .name = "dpaa2-qdma", + .owner = THIS_MODULE, + }, + .probe = dpaa2_qdma_probe, + .remove = dpaa2_qdma_remove, + .match_id_table = dpaa2_qdma_id_table +}; + +static int __init dpaa2_qdma_driver_init(void) +{ + return fsl_mc_driver_register(&(dpaa2_qdma_driver)); +} +late_initcall(dpaa2_qdma_driver_init); + +static void __exit fsl_qdma_exit(void) +{ + fsl_mc_driver_unregister(&(dpaa2_qdma_driver)); +} +module_exit(fsl_qdma_exit); + +MODULE_ALIAS("platform:fsl-dpaa2-qdma"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("NXP Layerscape DPAA2 qDMA engine driver"); diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h new file mode 100644 index 000000000000..7d571849c569 --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2019 NXP */ + +#ifndef __DPAA2_QDMA_H +#define __DPAA2_QDMA_H + +#define DPAA2_QDMA_STORE_SIZE 16 +#define NUM_CH 8 + +struct dpaa2_qdma_sd_d { + u32 rsv:32; + union { + struct { + u32 ssd:12; /* souce stride distance */ + u32 sss:12; /* souce stride size */ + u32 rsv1:8; + } sdf; + struct { + u32 dsd:12; /* Destination stride distance */ + u32 dss:12; /* Destination stride size */ + u32 rsv2:8; + } ddf; + } df; + u32 rbpcmd; /* Route-by-port command */ + u32 cmd; +} __attribute__((__packed__)); + +/* Source descriptor command read transaction type for RBP=0: */ +/* coherent copy of cacheable memory */ +#define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28) +/* Destination descriptor command write transaction type for RBP=0: */ +/* coherent copy of cacheable memory */ +#define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28) +#define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28) + +#define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */ +#define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */ +#define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */ +#define QMAN_FD_SL_DISABLE (0) /* short lengthe disabled */ +#define QMAN_FD_SL_ENABLE BIT(14) /* short lengthe enabled */ + +#define QDMA_FINAL_BIT_DISABLE (0) /* final bit disable */ +#define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */ + +#define QDMA_FD_SHORT_FORMAT BIT(11) /* short format */ +#define QDMA_FD_LONG_FORMAT (0) /* long format */ +#define QDMA_SER_DISABLE (8) /* no notification */ +#define QDMA_SER_CTX BIT(8) /* notification by FQD_CTX[fqid] */ +#define QDMA_SER_DEST (2 << 8) /* notification by destination desc */ +#define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */ +#define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */ + +#define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */ +#define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */ +/* Flow Context: 49bit physical address */ +#define QMAN_FD_CBMT_ENABLE BIT(15) +#define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */ +#define QMAN_FD_SC_DISABLE (0) /* stashing control */ + +#define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */ +#define QDMA_FL_FMT_SGE (0x2) /* Scatter gather frame */ +#define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */ +#define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */ +#define QDMA_FL_SL_LONG (0x0)/* long length */ +#define QDMA_FL_SL_SHORT (0x1) /* short length */ +#define QDMA_FL_F (0x1)/* last frame list bit */ + +/*Description of Frame list table structure*/ +struct dpaa2_qdma_chan { + struct dpaa2_qdma_engine *qdma; + struct virt_dma_chan vchan; + struct virt_dma_desc vdesc; + enum dma_status status; + u32 fqid; + + /* spinlock used by dpaa2 qdma driver */ + spinlock_t queue_lock; + struct dma_pool *fd_pool; + struct dma_pool *fl_pool; + struct dma_pool *sdd_pool; + + struct list_head comp_used; + struct list_head comp_free; + +}; + +struct dpaa2_qdma_comp { + dma_addr_t fd_bus_addr; + dma_addr_t fl_bus_addr; + dma_addr_t desc_bus_addr; + struct dpaa2_fd *fd_virt_addr; + struct dpaa2_fl_entry *fl_virt_addr; + struct dpaa2_qdma_sd_d *desc_virt_addr; + struct dpaa2_qdma_chan *qchan; + struct virt_dma_desc vdesc; + struct list_head list; +}; + +struct dpaa2_qdma_engine { + struct dma_device dma_dev; + u32 n_chans; + struct dpaa2_qdma_chan chans[NUM_CH]; + int qdma_wrtype_fixup; + int desc_allocated; + + struct dpaa2_qdma_priv *priv; +}; + +/* + * dpaa2_qdma_priv - driver private data + */ +struct dpaa2_qdma_priv { + int dpqdma_id; + + struct iommu_domain *iommu_domain; + struct dpdmai_attr dpdmai_attr; + struct device *dev; + struct fsl_mc_io *mc_io; + struct fsl_mc_device *dpdmai_dev; + u8 num_pairs; + + struct dpaa2_qdma_engine *dpaa2_qdma; + struct dpaa2_qdma_priv_per_prio *ppriv; + + struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM]; + u32 tx_fqid[DPDMAI_PRIO_NUM]; +}; + +struct dpaa2_qdma_priv_per_prio { + int req_fqid; + int rsp_fqid; + int prio; + + struct dpaa2_io_store *store; + struct dpaa2_io_notification_ctx nctx; + + struct dpaa2_qdma_priv *priv; +}; + +static struct soc_device_attribute soc_fixup_tuning[] = { + { .family = "QorIQ LX2160A"}, + { }, +}; + +/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */ +#define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \ + sizeof(struct dpaa2_fl_entry) * 3 + \ + sizeof(struct dpaa2_qdma_sd_d) * 2) + +static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma); +static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan, + struct list_head *head); +#endif /* __DPAA2_QDMA_H */ diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.c b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c new file mode 100644 index 000000000000..fbc2b2f39bec --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright 2019 NXP + +#include <linux/types.h> +#include <linux/io.h> +#include <linux/fsl/mc.h> +#include "dpdmai.h" + +struct dpdmai_rsp_get_attributes { + __le32 id; + u8 num_of_priorities; + u8 pad0[3]; + __le16 major; + __le16 minor; +}; + +struct dpdmai_cmd_queue { + __le32 dest_id; + u8 priority; + u8 queue; + u8 dest_type; + u8 pad; + __le64 user_ctx; + union { + __le32 options; + __le32 fqid; + }; +}; + +struct dpdmai_rsp_get_tx_queue { + __le64 pad; + __le32 fqid; +}; + +#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ + ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) + +/* cmd, param, offset, width, type, arg_name */ +#define DPDMAI_CMD_CREATE(_cmd, _cfg) \ +do { \ + typeof(_cmd) (cmd) = (_cmd); \ + typeof(_cfg) (cfg) = (_cfg); \ + MC_CMD_OP(cmd, 0, 8, 8, u8, (cfg)->priorities[0]);\ + MC_CMD_OP(cmd, 0, 16, 8, u8, (cfg)->priorities[1]);\ +} while (0) + +static inline u64 mc_enc(int lsoffset, int width, u64 val) +{ + return (val & MAKE_UMASK64(width)) << lsoffset; +} + +/** + * dpdmai_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpdmai_id: DPDMAI unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpdmai_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags, + int dpdmai_id, u16 *token) +{ + struct fsl_mc_command cmd = { 0 }; + __le64 *cmd_dpdmai_id; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN, + cmd_flags, 0); + + cmd_dpdmai_id = cmd.params; + *cmd_dpdmai_id = cpu_to_le32(dpdmai_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return 0; +} + +/** + * dpdmai_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_create() - Create the DPDMAI object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPDMAI object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpdmai_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_create(struct fsl_mc_io *mc_io, u32 cmd_flags, + const struct dpdmai_cfg *cfg, u16 *token) +{ + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CREATE, + cmd_flags, 0); + DPDMAI_CMD_CREATE(cmd, cfg); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return 0; +} + +/** + * dpdmai_enable() - Enable the DPDMAI, allow sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_ENABLE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_disable() - Disable the DPDMAI, stop sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DISABLE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_reset() - Reset the DPDMAI, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) +{ + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_RESET, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_get_attributes() - Retrieve DPDMAI attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, struct dpdmai_attr *attr) +{ + struct dpdmai_rsp_get_attributes *rsp_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_ATTR, + cmd_flags, token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpdmai_rsp_get_attributes *)cmd.params; + attr->id = le32_to_cpu(rsp_params->id); + attr->version.major = le16_to_cpu(rsp_params->major); + attr->version.minor = le16_to_cpu(rsp_params->minor); + attr->num_of_priorities = rsp_params->num_of_priorities; + + return 0; +} + +/** + * dpdmai_set_rx_queue() - Set Rx queue configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @priority: Select the queue relative to number of + * priorities configured at DPDMAI creation + * @cfg: Rx queue configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, const struct dpdmai_rx_queue_cfg *cfg) +{ + struct dpdmai_cmd_queue *cmd_params; + struct fsl_mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_RX_QUEUE, + cmd_flags, token); + + cmd_params = (struct dpdmai_cmd_queue *)cmd.params; + cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id); + cmd_params->priority = cfg->dest_cfg.priority; + cmd_params->queue = priority; + cmd_params->dest_type = cfg->dest_cfg.dest_type; + cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx); + cmd_params->options = cpu_to_le32(cfg->options); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpdmai_get_rx_queue() - Retrieve Rx queue attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @priority: Select the queue relative to number of + * priorities configured at DPDMAI creation + * @attr: Returned Rx queue attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, struct dpdmai_rx_queue_attr *attr) +{ + struct dpdmai_cmd_queue *cmd_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_RX_QUEUE, + cmd_flags, token); + + cmd_params = (struct dpdmai_cmd_queue *)cmd.params; + cmd_params->queue = priority; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + attr->dest_cfg.dest_id = le32_to_cpu(cmd_params->dest_id); + attr->dest_cfg.priority = cmd_params->priority; + attr->dest_cfg.dest_type = cmd_params->dest_type; + attr->user_ctx = le64_to_cpu(cmd_params->user_ctx); + attr->fqid = le32_to_cpu(cmd_params->fqid); + + return 0; +} + +/** + * dpdmai_get_tx_queue() - Retrieve Tx queue attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPDMAI object + * @priority: Select the queue relative to number of + * priorities configured at DPDMAI creation + * @fqid: Returned Tx queue + * + * Return: '0' on Success; Error code otherwise. + */ +int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 priority, u32 *fqid) +{ + struct dpdmai_rsp_get_tx_queue *rsp_params; + struct dpdmai_cmd_queue *cmd_params; + struct fsl_mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_TX_QUEUE, + cmd_flags, token); + + cmd_params = (struct dpdmai_cmd_queue *)cmd.params; + cmd_params->queue = priority; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + + rsp_params = (struct dpdmai_rsp_get_tx_queue *)cmd.params; + *fqid = le32_to_cpu(rsp_params->fqid); + + return 0; +} diff --git a/drivers/dma/fsl-dpaa2-qdma/dpdmai.h b/drivers/dma/fsl-dpaa2-qdma/dpdmai.h new file mode 100644 index 000000000000..6d785093da8e --- /dev/null +++ b/drivers/dma/fsl-dpaa2-qdma/dpdmai.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2019 NXP */ + +#ifndef __FSL_DPDMAI_H +#define __FSL_DPDMAI_H + +/* DPDMAI Version */ +#define DPDMAI_VER_MAJOR 2 +#define DPDMAI_VER_MINOR 2 + +#define DPDMAI_CMD_BASE_VERSION 0 +#define DPDMAI_CMD_ID_OFFSET 4 + +#define DPDMAI_CMDID_FORMAT(x) (((x) << DPDMAI_CMD_ID_OFFSET) | \ + DPDMAI_CMD_BASE_VERSION) + +/* Command IDs */ +#define DPDMAI_CMDID_CLOSE DPDMAI_CMDID_FORMAT(0x800) +#define DPDMAI_CMDID_OPEN DPDMAI_CMDID_FORMAT(0x80E) +#define DPDMAI_CMDID_CREATE DPDMAI_CMDID_FORMAT(0x90E) + +#define DPDMAI_CMDID_ENABLE DPDMAI_CMDID_FORMAT(0x002) +#define DPDMAI_CMDID_DISABLE DPDMAI_CMDID_FORMAT(0x003) +#define DPDMAI_CMDID_GET_ATTR DPDMAI_CMDID_FORMAT(0x004) +#define DPDMAI_CMDID_RESET DPDMAI_CMDID_FORMAT(0x005) +#define DPDMAI_CMDID_IS_ENABLED DPDMAI_CMDID_FORMAT(0x006) + +#define DPDMAI_CMDID_SET_IRQ DPDMAI_CMDID_FORMAT(0x010) +#define DPDMAI_CMDID_GET_IRQ DPDMAI_CMDID_FORMAT(0x011) +#define DPDMAI_CMDID_SET_IRQ_ENABLE DPDMAI_CMDID_FORMAT(0x012) +#define DPDMAI_CMDID_GET_IRQ_ENABLE DPDMAI_CMDID_FORMAT(0x013) +#define DPDMAI_CMDID_SET_IRQ_MASK DPDMAI_CMDID_FORMAT(0x014) +#define DPDMAI_CMDID_GET_IRQ_MASK DPDMAI_CMDID_FORMAT(0x015) +#define DPDMAI_CMDID_GET_IRQ_STATUS DPDMAI_CMDID_FORMAT(0x016) +#define DPDMAI_CMDID_CLEAR_IRQ_STATUS DPDMAI_CMDID_FORMAT(0x017) + +#define DPDMAI_CMDID_SET_RX_QUEUE DPDMAI_CMDID_FORMAT(0x1A0) +#define DPDMAI_CMDID_GET_RX_QUEUE DPDMAI_CMDID_FORMAT(0x1A1) +#define DPDMAI_CMDID_GET_TX_QUEUE DPDMAI_CMDID_FORMAT(0x1A2) + +#define MC_CMD_HDR_TOKEN_O 32 /* Token field offset */ +#define MC_CMD_HDR_TOKEN_S 16 /* Token field size */ + +#define MAKE_UMASK64(_width) \ + ((u64)((_width) < 64 ? ((u64)1 << (_width)) - 1 : (u64)-1)) + +/* Data Path DMA Interface API + * Contains initialization APIs and runtime control APIs for DPDMAI + */ + +/** + * Maximum number of Tx/Rx priorities per DPDMAI object + */ +#define DPDMAI_PRIO_NUM 2 + +/* DPDMAI queue modification options */ + +/** + * Select to modify the user's context associated with the queue + */ +#define DPDMAI_QUEUE_OPT_USER_CTX 0x1 + +/** + * Select to modify the queue's destination + */ +#define DPDMAI_QUEUE_OPT_DEST 0x2 + +/** + * struct dpdmai_cfg - Structure representing DPDMAI configuration + * @priorities: Priorities for the DMA hardware processing; valid priorities are + * configured with values 1-8; the entry following last valid entry + * should be configured with 0 + */ +struct dpdmai_cfg { + u8 priorities[DPDMAI_PRIO_NUM]; +}; + +/** + * struct dpdmai_attr - Structure representing DPDMAI attributes + * @id: DPDMAI object ID + * @version: DPDMAI version + * @num_of_priorities: number of priorities + */ +struct dpdmai_attr { + int id; + /** + * struct version - DPDMAI version + * @major: DPDMAI major version + * @minor: DPDMAI minor version + */ + struct { + u16 major; + u16 minor; + } version; + u8 num_of_priorities; +}; + +/** + * enum dpdmai_dest - DPDMAI destination types + * @DPDMAI_DEST_NONE: Unassigned destination; The queue is set in parked mode + * and does not generate FQDAN notifications; user is expected to dequeue + * from the queue based on polling or other user-defined method + * @DPDMAI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN + * notifications to the specified DPIO; user is expected to dequeue + * from the queue only after notification is received + * @DPDMAI_DEST_DPCON: The queue is set in schedule mode and does not generate + * FQDAN notifications, but is connected to the specified DPCON object; + * user is expected to dequeue from the DPCON channel + */ +enum dpdmai_dest { + DPDMAI_DEST_NONE = 0, + DPDMAI_DEST_DPIO = 1, + DPDMAI_DEST_DPCON = 2 +}; + +/** + * struct dpdmai_dest_cfg - Structure representing DPDMAI destination parameters + * @dest_type: Destination type + * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type + * @priority: Priority selection within the DPIO or DPCON channel; valid values + * are 0-1 or 0-7, depending on the number of priorities in that + * channel; not relevant for 'DPDMAI_DEST_NONE' option + */ +struct dpdmai_dest_cfg { + enum dpdmai_dest dest_type; + int dest_id; + u8 priority; +}; + +/** + * struct dpdmai_rx_queue_cfg - DPDMAI RX queue configuration + * @options: Flags representing the suggested modifications to the queue; + * Use any combination of 'DPDMAI_QUEUE_OPT_<X>' flags + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame; + * valid only if 'DPDMAI_QUEUE_OPT_USER_CTX' is contained in 'options' + * @dest_cfg: Queue destination parameters; + * valid only if 'DPDMAI_QUEUE_OPT_DEST' is contained in 'options' + */ +struct dpdmai_rx_queue_cfg { + struct dpdmai_dest_cfg dest_cfg; + u32 options; + u64 user_ctx; + +}; + +/** + * struct dpdmai_rx_queue_attr - Structure representing attributes of Rx queues + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame + * @dest_cfg: Queue destination configuration + * @fqid: Virtual FQID value to be used for dequeue operations + */ +struct dpdmai_rx_queue_attr { + struct dpdmai_dest_cfg dest_cfg; + u64 user_ctx; + u32 fqid; +}; + +int dpdmai_open(struct fsl_mc_io *mc_io, u32 cmd_flags, + int dpdmai_id, u16 *token); +int dpdmai_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_create(struct fsl_mc_io *mc_io, u32 cmd_flags, + const struct dpdmai_cfg *cfg, u16 *token); +int dpdmai_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpdmai_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, struct dpdmai_attr *attr); +int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, const struct dpdmai_rx_queue_cfg *cfg); +int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 priority, struct dpdmai_rx_queue_attr *attr); +int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 token, u8 priority, u32 *fqid); + +#endif /* __FSL_DPDMAI_H */ diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index d6010486ee50..4a13e158065a 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -109,10 +109,15 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, u32 ch = fsl_chan->vchan.chan.chan_id; void __iomem *muxaddr; unsigned int chans_per_mux, ch_off; + int endian_diff[4] = {3, 1, -1, -3}; u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; + + if (fsl_chan->edma->drvdata->mux_swap) + ch_off += endian_diff[ch_off % 4]; + muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; slot = EDMAMUX_CHCFG_SOURCE(slot); @@ -305,6 +310,11 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, return len; } +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan) +{ + fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true); +} + enum dma_status fsl_edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { @@ -314,8 +324,12 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan, unsigned long flags; status = dma_cookie_status(chan, cookie, txstate); - if (status == DMA_COMPLETE) + if (status == DMA_COMPLETE) { + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + txstate->residue = fsl_chan->chn_real_count; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return status; + } if (!txstate) return fsl_chan->status; diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 6ff7063a8a2f..b254dc656980 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -126,6 +126,7 @@ struct fsl_edma_chan { u32 dma_dev_size; enum dma_data_direction dma_dir; char chan_name[16]; + u32 chn_real_count; }; struct fsl_edma_desc { @@ -147,6 +148,7 @@ struct fsl_edma_drvdata { enum edma_version version; u32 dmamuxs; bool has_dmaclk; + bool mux_swap; int (*setup_irq)(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma); }; @@ -229,6 +231,7 @@ int fsl_edma_pause(struct dma_chan *chan); int fsl_edma_resume(struct dma_chan *chan); int fsl_edma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg); +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan); enum dma_status fsl_edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate); struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( diff --git a/drivers/dma/fsl-edma-v3.c b/drivers/dma/fsl-edma-v3.c new file mode 100644 index 000000000000..7204124a0742 --- /dev/null +++ b/drivers/dma/fsl-edma-v3.c @@ -0,0 +1,1151 @@ +/* + * drivers/dma/fsl-edma3-v3.c + * + * Copyright 2017-2018 NXP . + * + * Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c + * but changed to meet the IP change on i.MX8QM: every dma channel is specific + * to hardware. For example, channel 14 for LPUART1 receive request and channel + * 13 for transmit requesst. The eDMA block can be found on i.MX8QM + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/dmapool.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_dma.h> +#include <linux/pm_runtime.h> +#include <linux/pm_domain.h> + +#include "virt-dma.h" + +#define EDMA_CH_CSR 0x00 +#define EDMA_CH_ES 0x04 +#define EDMA_CH_INT 0x08 +#define EDMA_CH_SBR 0x0C +#define EDMA_CH_PRI 0x10 +#define EDMA_TCD_SADDR 0x20 +#define EDMA_TCD_SOFF 0x24 +#define EDMA_TCD_ATTR 0x26 +#define EDMA_TCD_NBYTES 0x28 +#define EDMA_TCD_SLAST 0x2C +#define EDMA_TCD_DADDR 0x30 +#define EDMA_TCD_DOFF 0x34 +#define EDMA_TCD_CITER_ELINK 0x36 +#define EDMA_TCD_CITER 0x36 +#define EDMA_TCD_DLAST_SGA 0x38 +#define EDMA_TCD_CSR 0x3C +#define EDMA_TCD_BITER_ELINK 0x3E +#define EDMA_TCD_BITER 0x3E + +#define EDMA_CH_SBR_RD BIT(22) +#define EDMA_CH_SBR_WR BIT(21) +#define EDMA_CH_CSR_ERQ BIT(0) +#define EDMA_CH_CSR_EARQ BIT(1) +#define EDMA_CH_CSR_EEI BIT(2) +#define EDMA_CH_CSR_DONE BIT(30) +#define EDMA_CH_CSR_ACTIVE BIT(31) + +#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) +#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) +#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) +#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) +#define EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) +#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) +#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) +#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) +#define EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) +#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) +#define EDMA_TCD_ATTR_SSIZE_64BYTE (0x0600) +#define EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) +#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) +#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) +#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) +#define EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) +#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) +#define EDMA_TCD_ATTR_DSIZE_64BYTE (0x0006) + +#define EDMA_TCD_SOFF_SOFF(x) (x) +#define EDMA_TCD_NBYTES_NBYTES(x) (x) +#define EDMA_TCD_NBYTES_MLOFF(x) (x << 10) +#define EDMA_TCD_NBYTES_DMLOE (1 << 30) +#define EDMA_TCD_NBYTES_SMLOE (1 << 31) +#define EDMA_TCD_SLAST_SLAST(x) (x) +#define EDMA_TCD_DADDR_DADDR(x) (x) +#define EDMA_TCD_CITER_CITER(x) ((x) & 0x7FFF) +#define EDMA_TCD_DOFF_DOFF(x) (x) +#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) +#define EDMA_TCD_BITER_BITER(x) ((x) & 0x7FFF) + +#define EDMA_TCD_CSR_START BIT(0) +#define EDMA_TCD_CSR_INT_MAJOR BIT(1) +#define EDMA_TCD_CSR_INT_HALF BIT(2) +#define EDMA_TCD_CSR_D_REQ BIT(3) +#define EDMA_TCD_CSR_E_SG BIT(4) +#define EDMA_TCD_CSR_E_LINK BIT(5) +#define EDMA_TCD_CSR_ACTIVE BIT(6) +#define EDMA_TCD_CSR_DONE BIT(7) + +#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)) + +#define ARGS_RX BIT(0) +#define ARGS_REMOTE BIT(1) +#define ARGS_DFIFO BIT(2) + +/* channel name template define in dts */ +#define CHAN_PREFIX "edma0-chan" +#define CHAN_POSFIX "-tx" + +enum fsl_edma3_pm_state { + RUNNING = 0, + SUSPENDED, +}; + +struct fsl_edma3_hw_tcd { + __le32 saddr; + __le16 soff; + __le16 attr; + __le32 nbytes; + __le32 slast; + __le32 daddr; + __le16 doff; + __le16 citer; + __le32 dlast_sga; + __le16 csr; + __le16 biter; +}; + +struct fsl_edma3_sw_tcd { + dma_addr_t ptcd; + struct fsl_edma3_hw_tcd *vtcd; +}; + +struct fsl_edma3_slave_config { + enum dma_transfer_direction dir; + enum dma_slave_buswidth addr_width; + u32 dev_addr; + u32 dev2_addr; /* source addr for dev2dev */ + u32 burst; + u32 attr; +}; + +struct fsl_edma3_chan { + struct virt_dma_chan vchan; + enum dma_status status; + enum fsl_edma3_pm_state pm_state; + bool idle; + bool used; + struct fsl_edma3_engine *edma3; + struct fsl_edma3_desc *edesc; + struct fsl_edma3_slave_config fsc; + void __iomem *membase; + int txirq; + int hw_chanid; + int priority; + int is_rxchan; + int is_remote; + int is_dfifo; + struct dma_pool *tcd_pool; + u32 chn_real_count; + char txirq_name[32]; + struct platform_device *pdev; + struct device *dev; +}; + +struct fsl_edma3_desc { + struct virt_dma_desc vdesc; + struct fsl_edma3_chan *echan; + bool iscyclic; + unsigned int n_tcds; + struct fsl_edma3_sw_tcd tcd[]; +}; + +struct fsl_edma3_reg_save { + u32 csr; + u32 sbr; +}; + +struct fsl_edma3_engine { + struct dma_device dma_dev; + unsigned long irqflag; + struct mutex fsl_edma3_mutex; + u32 n_chans; + int errirq; + #define MAX_CHAN_NUM 32 + struct fsl_edma3_reg_save edma_regs[MAX_CHAN_NUM]; + bool swap; /* remote/local swapped on Audio edma */ + struct fsl_edma3_chan chans[]; +}; + +static struct fsl_edma3_chan *to_fsl_edma3_chan(struct dma_chan *chan) +{ + return container_of(chan, struct fsl_edma3_chan, vchan.chan); +} + +static struct fsl_edma3_desc *to_fsl_edma3_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct fsl_edma3_desc, vdesc); +} + +static void fsl_edma3_enable_request(struct fsl_edma3_chan *fsl_chan) +{ + void __iomem *addr = fsl_chan->membase; + u32 val; + + val = readl(addr + EDMA_CH_SBR); + /* Remote/local swapped wrongly on iMX8 QM Audio edma */ + if (fsl_chan->edma3->swap) { + if (!fsl_chan->is_rxchan) + val |= EDMA_CH_SBR_RD; + else + val |= EDMA_CH_SBR_WR; + } else { + if (fsl_chan->is_rxchan) + val |= EDMA_CH_SBR_RD; + else + val |= EDMA_CH_SBR_WR; + } + + if (fsl_chan->is_remote) + val &= ~(EDMA_CH_SBR_RD | EDMA_CH_SBR_WR); + + writel(val, addr + EDMA_CH_SBR); + + val = readl(addr + EDMA_CH_CSR); + + val |= EDMA_CH_CSR_ERQ; + writel(val, addr + EDMA_CH_CSR); + + fsl_chan->used = true; +} + +static void fsl_edma3_disable_request(struct fsl_edma3_chan *fsl_chan) +{ + void __iomem *addr = fsl_chan->membase; + u32 val = readl(addr + EDMA_CH_CSR); + + val &= ~EDMA_CH_CSR_ERQ; + writel(val, addr + EDMA_CH_CSR); +} + +static unsigned int fsl_edma3_get_tcd_attr(enum dma_slave_buswidth addr_width) +{ + switch (addr_width) { + case 1: + return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT; + case 2: + return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT; + case 4: + return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; + case 8: + return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT; + case 16: + return EDMA_TCD_ATTR_SSIZE_16BYTE | EDMA_TCD_ATTR_DSIZE_16BYTE; + case 32: + return EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE; + case 64: + return EDMA_TCD_ATTR_SSIZE_64BYTE | EDMA_TCD_ATTR_DSIZE_64BYTE; + default: + return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT; + } +} + +static void fsl_edma3_free_desc(struct virt_dma_desc *vdesc) +{ + struct fsl_edma3_desc *fsl_desc; + int i; + + fsl_desc = to_fsl_edma3_desc(vdesc); + for (i = 0; i < fsl_desc->n_tcds; i++) + dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd, + fsl_desc->tcd[i].ptcd); + kfree(fsl_desc); +} + +static int fsl_edma3_terminate_all(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma3_disable_request(fsl_chan); + fsl_chan->edesc = NULL; + fsl_chan->idle = true; + fsl_chan->used = false; + fsl_chan->vchan.cyclic = NULL; + vchan_get_all_descriptors(&fsl_chan->vchan, &head); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + vchan_dma_desc_free_list(&fsl_chan->vchan, &head); + return 0; +} + +static int fsl_edma3_pause(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + if (fsl_chan->edesc) { + fsl_edma3_disable_request(fsl_chan); + fsl_chan->status = DMA_PAUSED; + fsl_chan->idle = true; + } + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + return 0; +} + +static int fsl_edma3_resume(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + if (fsl_chan->edesc) { + fsl_edma3_enable_request(fsl_chan); + fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; + } + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + return 0; +} + +static int fsl_edma3_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + + fsl_chan->fsc.dir = cfg->direction; + if (cfg->direction == DMA_DEV_TO_MEM) { + fsl_chan->fsc.dev_addr = cfg->src_addr; + fsl_chan->fsc.addr_width = cfg->src_addr_width; + fsl_chan->fsc.burst = cfg->src_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->src_addr_width); + } else if (cfg->direction == DMA_MEM_TO_DEV) { + fsl_chan->fsc.dev_addr = cfg->dst_addr; + fsl_chan->fsc.addr_width = cfg->dst_addr_width; + fsl_chan->fsc.burst = cfg->dst_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->dst_addr_width); + } else if (cfg->direction == DMA_DEV_TO_DEV) { + fsl_chan->fsc.dev2_addr = cfg->src_addr; + fsl_chan->fsc.dev_addr = cfg->dst_addr; + fsl_chan->fsc.addr_width = cfg->dst_addr_width; + fsl_chan->fsc.burst = cfg->dst_maxburst; + fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr + (cfg->dst_addr_width); + } else { + return -EINVAL; + } + return 0; +} + +static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, + struct virt_dma_desc *vdesc, bool in_progress) +{ + struct fsl_edma3_desc *edesc = fsl_chan->edesc; + void __iomem *addr = fsl_chan->membase; + enum dma_transfer_direction dir = fsl_chan->fsc.dir; + dma_addr_t cur_addr, dma_addr; + size_t len, size; + int i; + + /* calculate the total size in this desc */ + for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) + len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes) + * le16_to_cpu(edesc->tcd[i].vtcd->biter); + + if (!in_progress) + return len; + + if (dir == DMA_MEM_TO_DEV) + cur_addr = readl(addr + EDMA_TCD_SADDR); + else + cur_addr = readl(addr + EDMA_TCD_DADDR); + + /* figure out the finished and calculate the residue */ + for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { + size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes) + * le16_to_cpu(edesc->tcd[i].vtcd->biter); + if (dir == DMA_MEM_TO_DEV) + dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); + else + dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); + + len -= size; + if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { + len += dma_addr + size - cur_addr; + break; + } + } + + return len; +} + +static enum dma_status fsl_edma3_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *txstate) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct virt_dma_desc *vdesc; + enum dma_status status; + unsigned long flags; + + status = dma_cookie_status(chan, cookie, txstate); + if (status == DMA_COMPLETE) { + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + txstate->residue = fsl_chan->chn_real_count; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + return status; + } + + if (!txstate) + return fsl_chan->status; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + vdesc = vchan_find_desc(&fsl_chan->vchan, cookie); + if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie) + txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, + true); + else if (fsl_chan->edesc && vdesc) + txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc, + false); + else + txstate->residue = 0; + + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + return fsl_chan->status; +} + +static void fsl_edma3_set_tcd_regs(struct fsl_edma3_chan *fsl_chan, + struct fsl_edma3_hw_tcd *tcd) +{ + void __iomem *addr = fsl_chan->membase; + /* + * TCD parameters are stored in struct fsl_edma3_hw_tcd in little + * endian format. However, we need to load the TCD registers in + * big- or little-endian obeying the eDMA engine model endian. + */ + writew(0, addr + EDMA_TCD_CSR); + writel(le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR); + writel(le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR); + + writew(le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR); + writew(le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF); + + writel(le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES); + writel(le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST); + + writew(le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER); + writew(le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER); + writew(le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF); + + writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA); + + /* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */ + writel(readl(addr + EDMA_CH_CSR), addr + EDMA_CH_CSR); + + writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR); +} + +static inline +void fsl_edma3_fill_tcd(struct fsl_edma3_chan *fsl_chan, + struct fsl_edma3_hw_tcd *tcd, u32 src, u32 dst, + u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, + u16 biter, u16 doff, u32 dlast_sga, bool major_int, + bool disable_req, bool enable_sg) +{ + u16 csr = 0; + + /* + * eDMA hardware SGs require the TCDs to be stored in little + * endian format irrespective of the register endian model. + * So we put the value in little endian in memory, waiting + * for fsl_edma3_set_tcd_regs doing the swap. + */ + tcd->saddr = cpu_to_le32(src); + tcd->daddr = cpu_to_le32(dst); + + tcd->attr = cpu_to_le16(attr); + + tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff)); + + if (fsl_chan->is_dfifo) { + /* set mloff as -8 */ + nbytes |= EDMA_TCD_NBYTES_MLOFF(-8); + /* enable DMLOE/SMLOE */ + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + nbytes |= EDMA_TCD_NBYTES_DMLOE; + nbytes &= ~EDMA_TCD_NBYTES_SMLOE; + } else { + nbytes |= EDMA_TCD_NBYTES_SMLOE; + nbytes &= ~EDMA_TCD_NBYTES_DMLOE; + } + } + + tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes)); + tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast)); + + tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); + tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff)); + + tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga)); + + tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); + if (major_int) + csr |= EDMA_TCD_CSR_INT_MAJOR; + + if (disable_req) + csr |= EDMA_TCD_CSR_D_REQ; + + if (enable_sg) + csr |= EDMA_TCD_CSR_E_SG; + + if (fsl_chan->is_rxchan) + csr |= EDMA_TCD_CSR_ACTIVE; + + tcd->csr = cpu_to_le16(csr); +} + +static struct fsl_edma3_desc *fsl_edma3_alloc_desc(struct fsl_edma3_chan + *fsl_chan, int sg_len) +{ + struct fsl_edma3_desc *fsl_desc; + int i; + + fsl_desc = kzalloc(sizeof(*fsl_desc) + sizeof(struct fsl_edma3_sw_tcd) + * sg_len, GFP_ATOMIC); + if (!fsl_desc) + return NULL; + + fsl_desc->echan = fsl_chan; + fsl_desc->n_tcds = sg_len; + for (i = 0; i < sg_len; i++) { + fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool, + GFP_ATOMIC, &fsl_desc->tcd[i].ptcd); + if (!fsl_desc->tcd[i].vtcd) + goto err; + } + return fsl_desc; + +err: + while (--i >= 0) + dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd, + fsl_desc->tcd[i].ptcd); + kfree(fsl_desc); + return NULL; +} + +static struct dma_async_tx_descriptor *fsl_edma3_prep_dma_cyclic( + struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct fsl_edma3_desc *fsl_desc; + dma_addr_t dma_buf_next; + int sg_len, i; + u32 src_addr, dst_addr, last_sg, nbytes; + u16 soff, doff, iter; + bool major_int = true; + + sg_len = buf_len / period_len; + fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = true; + + dma_buf_next = dma_addr; + nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; + iter = period_len / nbytes; + + for (i = 0; i < sg_len; i++) { + if (dma_buf_next >= dma_addr + buf_len) + dma_buf_next = dma_addr; + + /* get next sg's physical address */ + last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; + + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + src_addr = dma_buf_next; + dst_addr = fsl_chan->fsc.dev_addr; + soff = fsl_chan->fsc.addr_width; + if (fsl_chan->is_dfifo) + doff = 4; + else + doff = 0; + } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { + src_addr = fsl_chan->fsc.dev_addr; + dst_addr = dma_buf_next; + if (fsl_chan->is_dfifo) + soff = 4; + else + soff = 0; + doff = fsl_chan->fsc.addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->fsc.dev2_addr; + dst_addr = fsl_chan->fsc.dev_addr; + soff = 0; + doff = 0; + major_int = false; + } + + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->fsc.attr, soff, nbytes, 0, + iter, iter, doff, last_sg, major_int, false, true); + dma_buf_next += period_len; + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + +static struct dma_async_tx_descriptor *fsl_edma3_prep_slave_sg( + struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct fsl_edma3_desc *fsl_desc; + struct scatterlist *sg; + u32 src_addr, dst_addr, last_sg, nbytes; + u16 soff, doff, iter; + int i; + + if (!is_slave_direction(fsl_chan->fsc.dir)) + return NULL; + + fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic = false; + + nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst; + for_each_sg(sgl, sg, sg_len, i) { + /* get next sg's physical address */ + last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; + + if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) { + src_addr = sg_dma_address(sg); + dst_addr = fsl_chan->fsc.dev_addr; + soff = fsl_chan->fsc.addr_width; + doff = 0; + } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) { + src_addr = fsl_chan->fsc.dev_addr; + dst_addr = sg_dma_address(sg); + soff = 0; + doff = fsl_chan->fsc.addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr = fsl_chan->fsc.dev2_addr; + dst_addr = fsl_chan->fsc.dev_addr; + soff = 0; + doff = 0; + } + + iter = sg_dma_len(sg) / nbytes; + if (i < sg_len - 1) { + last_sg = fsl_desc->tcd[(i + 1)].ptcd; + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, + src_addr, dst_addr, fsl_chan->fsc.attr, + soff, nbytes, 0, iter, iter, doff, + last_sg, false, false, true); + } else { + last_sg = 0; + fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, + src_addr, dst_addr, fsl_chan->fsc.attr, + soff, nbytes, 0, iter, iter, doff, + last_sg, true, true, false); + } + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); +} + +static void fsl_edma3_xfer_desc(struct fsl_edma3_chan *fsl_chan) +{ + struct virt_dma_desc *vdesc; + + vdesc = vchan_next_desc(&fsl_chan->vchan); + if (!vdesc) + return; + fsl_chan->edesc = to_fsl_edma3_desc(vdesc); + fsl_edma3_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); + fsl_edma3_enable_request(fsl_chan); + fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; +} + +static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan, + struct virt_dma_desc *vdesc, bool in_progress); + +static void fsl_edma3_get_realcnt(struct fsl_edma3_chan *fsl_chan) +{ + fsl_chan->chn_real_count = fsl_edma3_desc_residue(fsl_chan, NULL, true); +} + +static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) +{ + struct fsl_edma3_chan *fsl_chan = dev_id; + unsigned int intr; + void __iomem *base_addr; + + spin_lock(&fsl_chan->vchan.lock); + + /* Ignore this interrupt since channel has been freeed with power off */ + if (!fsl_chan->edesc && !fsl_chan->tcd_pool) + goto irq_handled; + + base_addr = fsl_chan->membase; + + intr = readl(base_addr + EDMA_CH_INT); + if (!intr) + goto irq_handled; + + writel(1, base_addr + EDMA_CH_INT); + + /* Ignore this interrupt since channel has been disabled already */ + if (!fsl_chan->edesc) + goto irq_handled; + + if (!fsl_chan->edesc->iscyclic) { + fsl_edma3_get_realcnt(fsl_chan); + list_del(&fsl_chan->edesc->vdesc.node); + vchan_cookie_complete(&fsl_chan->edesc->vdesc); + fsl_chan->edesc = NULL; + fsl_chan->status = DMA_COMPLETE; + fsl_chan->idle = true; + } else { + vchan_cyclic_callback(&fsl_chan->edesc->vdesc); + } + + if (!fsl_chan->edesc) + fsl_edma3_xfer_desc(fsl_chan); +irq_handled: + spin_unlock(&fsl_chan->vchan.lock); + + return IRQ_HANDLED; +} + +static void fsl_edma3_issue_pending(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + + if (unlikely(fsl_chan->pm_state != RUNNING)) { + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + /* cannot submit due to suspend */ + return; + } + + if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) + fsl_edma3_xfer_desc(fsl_chan); + + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); +} + +static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct fsl_edma3_engine *fsl_edma3 = ofdma->of_dma_data; + struct dma_chan *chan, *_chan; + struct fsl_edma3_chan *fsl_chan; + + if (dma_spec->args_count != 3) + return NULL; + + mutex_lock(&fsl_edma3->fsl_edma3_mutex); + list_for_each_entry_safe(chan, _chan, &fsl_edma3->dma_dev.channels, + device_node) { + if (chan->client_count) + continue; + + fsl_chan = to_fsl_edma3_chan(chan); + if (fsl_chan->hw_chanid == dma_spec->args[0]) { + chan = dma_get_slave_channel(chan); + chan->device->privatecnt++; + fsl_chan->priority = dma_spec->args[1]; + fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; + fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; + fsl_chan->is_dfifo = dma_spec->args[2] & ARGS_DFIFO; + mutex_unlock(&fsl_edma3->fsl_edma3_mutex); + return chan; + } + } + mutex_unlock(&fsl_edma3->fsl_edma3_mutex); + return NULL; +} + +static int fsl_edma3_alloc_chan_resources(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + struct platform_device *pdev = fsl_chan->pdev; + int ret; + + fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, + sizeof(struct fsl_edma3_hw_tcd), + 32, 0); + pm_runtime_get_sync(fsl_chan->dev); + /* clear meaningless pending irq anyway */ + if (readl(fsl_chan->membase + EDMA_CH_INT)) + writel(1, fsl_chan->membase + EDMA_CH_INT); + + ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, + fsl_edma3_tx_handler, fsl_chan->edma3->irqflag, + fsl_chan->txirq_name, fsl_chan); + if (ret) { + dev_err(&pdev->dev, "Can't register %s IRQ.\n", + fsl_chan->txirq_name); + return ret; + } + + return 0; +} + +static void fsl_edma3_free_chan_resources(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + devm_free_irq(&fsl_chan->pdev->dev, fsl_chan->txirq, fsl_chan); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma3_disable_request(fsl_chan); + fsl_chan->edesc = NULL; + vchan_get_all_descriptors(&fsl_chan->vchan, &head); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + vchan_dma_desc_free_list(&fsl_chan->vchan, &head); + dma_pool_destroy(fsl_chan->tcd_pool); + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_chan->tcd_pool = NULL; + fsl_chan->used = false; + /* Clear interrupt before power off */ + if (readl(fsl_chan->membase + EDMA_CH_INT)) + writel(1, fsl_chan->membase + EDMA_CH_INT); + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + + pm_runtime_put_sync(fsl_chan->dev); +} + +static void fsl_edma3_synchronize(struct dma_chan *chan) +{ + struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan); + + vchan_synchronize(&fsl_chan->vchan); +} + +static struct device *fsl_edma3_attach_pd(struct device *dev, + struct device_node *np, int index) +{ + const char *domn = "edma0-chan01"; + struct device *pd_chan; + struct device_link *link; + int ret; + + ret = of_property_read_string_index(np, "power-domain-names", index, + &domn); + if (ret) { + dev_err(dev, "parse power-domain-names error.(%d)\n", ret); + return NULL; + } + + pd_chan = dev_pm_domain_attach_by_name(dev, domn); + if (!pd_chan) + return NULL; + + link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(link)) { + dev_err(dev, "Failed to add device_link to %s: %ld\n", domn, + PTR_ERR(link)); + return NULL; + } + + return pd_chan; +} + +static int fsl_edma3_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct fsl_edma3_engine *fsl_edma3; + struct fsl_edma3_chan *fsl_chan; + struct resource *res; + int len, chans; + int ret, i; + + ret = of_property_read_u32(np, "dma-channels", &chans); + if (ret) { + dev_err(&pdev->dev, "Can't get dma-channels.\n"); + return ret; + } + + len = sizeof(*fsl_edma3) + sizeof(*fsl_chan) * chans; + fsl_edma3 = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!fsl_edma3) + return -ENOMEM; + + /* Audio edma rx/tx channel shared interrupt */ + if (of_property_read_bool(np, "shared-interrupt")) + fsl_edma3->irqflag = IRQF_SHARED; + + fsl_edma3->swap = of_device_is_compatible(np, "fsl,imx8qm-adma"); + fsl_edma3->n_chans = chans; + + INIT_LIST_HEAD(&fsl_edma3->dma_dev.channels); + for (i = 0; i < fsl_edma3->n_chans; i++) { + struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; + const char *txirq_name; + char chanid[3], id_len = 0; + char *p = chanid; + unsigned long val; + + fsl_chan->edma3 = fsl_edma3; + fsl_chan->pdev = pdev; + fsl_chan->pm_state = RUNNING; + fsl_chan->idle = true; + /* Get per channel membase */ + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + fsl_chan->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(fsl_chan->membase)) + return PTR_ERR(fsl_chan->membase); + + /* Get the hardware chanel id by the channel membase + * channel0:0x10000, channel1:0x20000... total 32 channels + */ + fsl_chan->hw_chanid = (res->start >> 16) & 0x1f; + + ret = of_property_read_string_index(np, "interrupt-names", i, + &txirq_name); + if (ret) { + dev_err(&pdev->dev, "read interrupt-names fail.\n"); + return ret; + } + /* Get channel id length from dts, one-digit or double-digit */ + id_len = strlen(txirq_name) - strlen(CHAN_PREFIX) - + strlen(CHAN_POSFIX); + if (id_len > 2) { + dev_err(&pdev->dev, "%s is edmaX-chanX-tx in dts?\n", + res->name); + return -EINVAL; + } + /* Grab channel id from txirq_name */ + strncpy(p, txirq_name + strlen(CHAN_PREFIX), id_len); + *(p + id_len) = '\0'; + + /* check if the channel id match well with hw_chanid */ + ret = kstrtoul(chanid, 0, &val); + if (ret || val != fsl_chan->hw_chanid) { + dev_err(&pdev->dev, "%s,wrong id?\n", txirq_name); + return -EINVAL; + } + + /* request channel irq */ + fsl_chan->txirq = platform_get_irq_byname(pdev, txirq_name); + if (fsl_chan->txirq < 0) { + dev_err(&pdev->dev, "Can't get %s irq.\n", txirq_name); + return fsl_chan->txirq; + } + + memcpy(fsl_chan->txirq_name, txirq_name, strlen(txirq_name)); + + fsl_chan->vchan.desc_free = fsl_edma3_free_desc; + vchan_init(&fsl_chan->vchan, &fsl_edma3->dma_dev); + fsl_chan->used = false; + } + + mutex_init(&fsl_edma3->fsl_edma3_mutex); + + dma_cap_set(DMA_PRIVATE, fsl_edma3->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, fsl_edma3->dma_dev.cap_mask); + dma_cap_set(DMA_CYCLIC, fsl_edma3->dma_dev.cap_mask); + + fsl_edma3->dma_dev.dev = &pdev->dev; + fsl_edma3->dma_dev.device_alloc_chan_resources + = fsl_edma3_alloc_chan_resources; + fsl_edma3->dma_dev.device_free_chan_resources + = fsl_edma3_free_chan_resources; + fsl_edma3->dma_dev.device_tx_status = fsl_edma3_tx_status; + fsl_edma3->dma_dev.device_prep_slave_sg = fsl_edma3_prep_slave_sg; + fsl_edma3->dma_dev.device_prep_dma_cyclic = fsl_edma3_prep_dma_cyclic; + fsl_edma3->dma_dev.device_config = fsl_edma3_slave_config; + fsl_edma3->dma_dev.device_pause = fsl_edma3_pause; + fsl_edma3->dma_dev.device_resume = fsl_edma3_resume; + fsl_edma3->dma_dev.device_terminate_all = fsl_edma3_terminate_all; + fsl_edma3->dma_dev.device_issue_pending = fsl_edma3_issue_pending; + fsl_edma3->dma_dev.device_synchronize = fsl_edma3_synchronize; + + fsl_edma3->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; + fsl_edma3->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; + fsl_edma3->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | + BIT(DMA_MEM_TO_DEV) | + BIT(DMA_DEV_TO_DEV); + + platform_set_drvdata(pdev, fsl_edma3); + + ret = dma_async_device_register(&fsl_edma3->dma_dev); + if (ret) { + dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n"); + return ret; + } + /* Attach power domains from dts for each dma chanel device */ + for (i = 0; i < fsl_edma3->n_chans; i++) { + struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i]; + struct device *dev; + + dev = fsl_edma3_attach_pd(&pdev->dev, np, i); + if (!dev) { + dev_err(dev, "edma channel attach failed.\n"); + return -EINVAL; + } + + fsl_chan->dev = dev; + /* clear meaningless pending irq anyway */ + writel(1, fsl_chan->membase + EDMA_CH_INT); + pm_runtime_put_sync(dev); + } + + ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma3); + if (ret) { + dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma.\n"); + dma_async_device_unregister(&fsl_edma3->dma_dev); + return ret; + } + + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static int fsl_edma3_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct fsl_edma3_engine *fsl_edma3 = platform_get_drvdata(pdev); + + of_dma_controller_free(np); + dma_async_device_unregister(&fsl_edma3->dma_dev); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int fsl_edma3_suspend_late(struct device *dev) +{ + struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma3_chan *fsl_chan; + unsigned long flags; + void __iomem *addr; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + addr = fsl_chan->membase; + + if (!fsl_chan->used) + continue; + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + fsl_edma->edma_regs[i].csr = readl(addr + EDMA_CH_CSR); + fsl_edma->edma_regs[i].sbr = readl(addr + EDMA_CH_SBR); + /* Make sure chan is idle or will force disable. */ + if (unlikely(!fsl_chan->idle)) { + dev_warn(dev, "WARN: There is non-idle channel."); + fsl_edma3_disable_request(fsl_chan); + } + fsl_chan->pm_state = SUSPENDED; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + } + + return 0; +} + +static int fsl_edma3_resume_early(struct device *dev) +{ + struct fsl_edma3_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma3_chan *fsl_chan; + void __iomem *addr; + unsigned long flags; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + addr = fsl_chan->membase; + + if (!fsl_chan->used) + continue; + + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + writel(fsl_edma->edma_regs[i].csr, addr + EDMA_CH_CSR); + writel(fsl_edma->edma_regs[i].sbr, addr + EDMA_CH_SBR); + /* restore tcd if this channel not terminated before suspend */ + if (fsl_chan->edesc) + fsl_edma3_set_tcd_regs(fsl_chan, + fsl_chan->edesc->tcd[0].vtcd); + fsl_chan->pm_state = RUNNING; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + } + + return 0; +} +#endif + +static const struct dev_pm_ops fsl_edma3_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(fsl_edma3_suspend_late, + fsl_edma3_resume_early) +}; + +static const struct of_device_id fsl_edma3_dt_ids[] = { + { .compatible = "fsl,imx8qm-edma", }, + { .compatible = "fsl,imx8qm-adma", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_edma3_dt_ids); + +static struct platform_driver fsl_edma3_driver = { + .driver = { + .name = "fsl-edma-v3", + .of_match_table = fsl_edma3_dt_ids, + .pm = &fsl_edma3_pm_ops, + }, + .probe = fsl_edma3_probe, + .remove = fsl_edma3_remove, +}; + +static int __init fsl_edma3_init(void) +{ + return platform_driver_register(&fsl_edma3_driver); +} +fs_initcall(fsl_edma3_init); + +static void __exit fsl_edma3_exit(void) +{ + platform_driver_unregister(&fsl_edma3_driver); +} +module_exit(fsl_edma3_exit); + +MODULE_ALIAS("platform:fsl-edma3"); +MODULE_DESCRIPTION("Freescale eDMA-V3 engine driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index 6760ae4b2956..5d2f22744923 100644 --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c @@ -53,6 +53,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) } if (!fsl_chan->edesc->iscyclic) { + fsl_edma_get_realcnt(fsl_chan); list_del(&fsl_chan->edesc->vdesc.node); vchan_cookie_complete(&fsl_chan->edesc->vdesc); fsl_chan->edesc = NULL; @@ -240,6 +241,13 @@ static struct fsl_edma_drvdata vf610_data = { .setup_irq = fsl_edma_irq_init, }; +static struct fsl_edma_drvdata ls1028a_data = { + .version = v1, + .dmamuxs = DMAMUX_NR, + .mux_swap = true, + .setup_irq = fsl_edma_irq_init, +}; + static struct fsl_edma_drvdata imx7ulp_data = { .version = v3, .dmamuxs = 1, @@ -249,6 +257,7 @@ static struct fsl_edma_drvdata imx7ulp_data = { static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,vf610-edma", .data = &vf610_data}, + { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, { /* sentinel */ } }; diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 67736c801f3c..09ae4282ad56 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -8,7 +8,8 @@ // // Based on code from Freescale: // -// Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. +// Copyright 2004-2016 Freescale Semiconductor, Inc. All Rights Reserved. +// Copyright 2018 NXP. #include <linux/init.h> #include <linux/iopoll.h> @@ -23,10 +24,12 @@ #include <linux/semaphore.h> #include <linux/spinlock.h> #include <linux/device.h> +#include <linux/genalloc.h> #include <linux/dma-mapping.h> #include <linux/firmware.h> #include <linux/slab.h> #include <linux/platform_device.h> +#include <linux/pm_runtime.h> #include <linux/dmaengine.h> #include <linux/of.h> #include <linux/of_address.h> @@ -74,6 +77,9 @@ #define SDMA_CHNENBL0_IMX35 0x200 #define SDMA_CHNENBL0_IMX31 0x080 #define SDMA_CHNPRI_0 0x100 +#define SDMA_DONE0_CONFIG 0x1000 +#define SDMA_DONE0_CONFIG_DONE_SEL 0x7 +#define SDMA_DONE0_CONFIG_DONE_DIS 0x6 /* * Buffer descriptor status values. @@ -168,6 +174,8 @@ #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) #define SDMA_WATERMARK_LEVEL_SP BIT(11) #define SDMA_WATERMARK_LEVEL_DP BIT(12) +#define SDMA_WATERMARK_LEVEL_SD BIT(13) +#define SDMA_WATERMARK_LEVEL_DD BIT(14) #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) #define SDMA_WATERMARK_LEVEL_LWE BIT(28) #define SDMA_WATERMARK_LEVEL_HWE BIT(29) @@ -175,12 +183,17 @@ #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ BIT(DMA_MEM_TO_DEV) | \ BIT(DMA_DEV_TO_DEV)) +#define SDMA_WATERMARK_LEVEL_FIFOS_OFF 12 +#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23) +#define SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF 24 + /* * Mode/Count of data node descriptors - IPCv2 */ @@ -360,6 +373,7 @@ struct sdma_desc { struct sdma_channel { struct virt_dma_chan vc; struct sdma_desc *desc; + struct list_head terminated_node; struct sdma_engine *sdma; unsigned int channel; enum dma_transfer_direction direction; @@ -377,9 +391,14 @@ struct sdma_channel { unsigned long watermark_level; u32 shp_addr, per_addr; enum dma_status status; - bool context_loaded; struct imx_dma_data data; struct work_struct terminate_worker; + bool is_ram_script; + bool src_dualfifo; + bool dst_dualfifo; + unsigned int fifo_num; + bool sw_done; + u32 sw_done_sel; }; #define IMX_DMA_SG_LOOP BIT(0) @@ -389,6 +408,15 @@ struct sdma_channel { #define MXC_SDMA_MIN_PRIORITY 1 #define MXC_SDMA_MAX_PRIORITY 7 +/* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are reserved and + * can't be accessed. Skip these register touch in suspend/resume. Also below + * two macros are only used on i.mx6sx. + */ +#define MXC_SDMA_RESERVED_REG (SDMA_CHNPRI_0 - SDMA_XTRIG_CONF2 - 4) +#define MXC_SDMA_SAVED_REG_NUM (((SDMA_CHNENBL0_IMX35 + 4 * 48) - \ + MXC_SDMA_RESERVED_REG) / 4) + #define SDMA_FIRMWARE_MAGIC 0x414d4453 /** @@ -420,6 +448,15 @@ struct sdma_driver_data { int num_events; struct sdma_script_start_addrs *script_addrs; bool check_ratio; + /* + * ecspi ERR009165 fixed should be done in sdma script + * and it be fixed in soc from i.mx6ul. + * please get more information from below link: + * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf + */ + bool ecspi_fixed; + bool has_done0; + bool pm_runtime; }; struct sdma_engine { @@ -427,9 +464,14 @@ struct sdma_engine { struct device_dma_parameters dma_parms; struct sdma_channel channel[MAX_DMA_CHANNELS]; struct sdma_channel_control *channel_control; + u32 save_regs[MXC_SDMA_SAVED_REG_NUM]; + u32 save_done0_regs[2]; + const char *fw_name; void __iomem *regs; struct sdma_context_data *context; dma_addr_t context_phys; + dma_addr_t ccb_phys; + bool is_on; struct dma_device dma_device; struct clk *clk_ipg; struct clk *clk_ahb; @@ -444,12 +486,21 @@ struct sdma_engine { struct sdma_buffer_descriptor *bd0; /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ bool clk_ratio; + struct gen_pool *iram_pool; + bool fw_loaded; + u32 fw_fail; + unsigned short ram_code_start; }; static int sdma_config_write(struct dma_chan *chan, struct dma_slave_config *dmaengine_cfg, enum dma_transfer_direction direction); +static int sdma_get_firmware(struct sdma_engine *sdma, + const char *fw_name); +static int sdma_get_firmware_wait(struct sdma_engine *sdma, + const char *fw_name); + static struct sdma_driver_data sdma_imx31 = { .chnenbl0 = SDMA_CHNENBL0_IMX31, .num_events = 32, @@ -540,6 +591,31 @@ static struct sdma_driver_data sdma_imx6q = { .script_addrs = &sdma_script_imx6q, }; +static struct sdma_script_start_addrs sdma_script_imx6sx = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1032, + .mcu_2_shp_addr = 960, + .app_2_mcu_addr = 683, + .shp_2_mcu_addr = 891, + .spdif_2_mcu_addr = 1100, + .mcu_2_spdif_addr = 1134, +}; + +static struct sdma_driver_data sdma_imx6sx = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx6sx, +}; + +static struct sdma_driver_data sdma_imx6ul = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx6sx, + .ecspi_fixed = true, +}; + static struct sdma_script_start_addrs sdma_script_imx7d = { .ap_2_ap_addr = 644, .uart_2_mcu_addr = 819, @@ -563,6 +639,17 @@ static struct sdma_driver_data sdma_imx8mq = { .num_events = 48, .script_addrs = &sdma_script_imx7d, .check_ratio = 1, + .ecspi_fixed = true, +}; + +static struct sdma_driver_data sdma_imx8mp = { + .chnenbl0 = SDMA_CHNENBL0_IMX35, + .num_events = 48, + .script_addrs = &sdma_script_imx7d, + .check_ratio = 1, + .ecspi_fixed = true, + .has_done0 = true, + .pm_runtime = true, }; static const struct platform_device_id sdma_devtypes[] = { @@ -585,12 +672,21 @@ static const struct platform_device_id sdma_devtypes[] = { .name = "imx6q-sdma", .driver_data = (unsigned long)&sdma_imx6q, }, { + .name = "imx6sx-sdma", + .driver_data = (unsigned long)&sdma_imx6sx, + }, { .name = "imx7d-sdma", .driver_data = (unsigned long)&sdma_imx7d, }, { + .name = "imx6ul-sdma", + .driver_data = (unsigned long)&sdma_imx6ul, + }, { .name = "imx8mq-sdma", .driver_data = (unsigned long)&sdma_imx8mq, }, { + .name = "imx8mp-sdma", + .driver_data = (unsigned long)&sdma_imx8mp, + }, { /* sentinel */ } }; @@ -603,8 +699,11 @@ static const struct of_device_id sdma_dt_ids[] = { { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, + { .compatible = "fsl,imx6sx-sdma", .data = &sdma_imx6sx, }, { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, + { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, }, { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, }, + { .compatible = "fsl,imx8mp-sdma", .data = &sdma_imx8mp, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sdma_dt_ids); @@ -695,10 +794,13 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, int ret; unsigned long flags; - buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); - if (!buf_virt) { + if (sdma->iram_pool) + buf_virt = gen_pool_dma_alloc(sdma->iram_pool, size, &buf_phys); + else + buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, + GFP_KERNEL); + if (!buf_virt) return -ENOMEM; - } spin_lock_irqsave(&sdma->channel_0_lock, flags); @@ -714,7 +816,10 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)buf_virt, size); + else + dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); return ret; } @@ -729,6 +834,21 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) val = readl_relaxed(sdma->regs + chnenbl); __set_bit(channel, &val); writel_relaxed(val, sdma->regs + chnenbl); + + /* Set SDMA_DONEx_CONFIG is sw_done enabled */ + if (sdmac->sw_done) { + u32 offset = SDMA_DONE0_CONFIG + sdmac->sw_done_sel / 4; + u32 done_sel = SDMA_DONE0_CONFIG_DONE_SEL + + ((sdmac->sw_done_sel % 4) << 3); + u32 sw_done_dis = SDMA_DONE0_CONFIG_DONE_DIS + + ((sdmac->sw_done_sel % 4) << 3); + + val = readl_relaxed(sdma->regs + offset); + __set_bit(done_sel, &val); + __clear_bit(sw_done_dis, &val); + writel_relaxed(val, sdma->regs + offset); + } + } static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) @@ -852,6 +972,9 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) struct sdma_engine *sdma = dev_id; unsigned long stat; + clk_enable(sdma->clk_ipg); + clk_enable(sdma->clk_ahb); + stat = readl_relaxed(sdma->regs + SDMA_H_INTR); writel_relaxed(stat, sdma->regs + SDMA_H_INTR); /* channel 0 is special and not handled here, see run_channel0() */ @@ -866,7 +989,10 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) desc = sdmac->desc; if (desc) { if (sdmac->flags & IMX_DMA_SG_LOOP) { - sdma_update_channel_loop(sdmac); + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + sdma_update_channel_loop(sdmac); + else + vchan_cyclic_callback(&desc->vd); } else { mxc_sdma_handle_channel_normal(sdmac); vchan_cookie_complete(&desc->vd); @@ -878,6 +1004,9 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) __clear_bit(channel, &stat); } + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + return IRQ_HANDLED; } @@ -925,6 +1054,10 @@ static void sdma_get_pc(struct sdma_channel *sdmac, emi_2_per = sdma->script_addrs->mcu_2_ata_addr; break; case IMX_DMATYPE_CSPI: + per_2_emi = sdma->script_addrs->app_2_mcu_addr; + emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; + sdmac->is_ram_script = true; + break; case IMX_DMATYPE_EXT: case IMX_DMATYPE_SSI: case IMX_DMATYPE_SAI: @@ -934,6 +1067,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac, case IMX_DMATYPE_SSI_DUAL: per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; + sdmac->is_ram_script = true; break; case IMX_DMATYPE_SSI_SP: case IMX_DMATYPE_MMC: @@ -948,11 +1082,13 @@ static void sdma_get_pc(struct sdma_channel *sdmac, per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; per_2_per = sdma->script_addrs->per_2_per_addr; + sdmac->is_ram_script = true; break; case IMX_DMATYPE_ASRC_SP: per_2_emi = sdma->script_addrs->shp_2_mcu_addr; emi_2_per = sdma->script_addrs->mcu_2_shp_addr; per_2_per = sdma->script_addrs->per_2_per_addr; + sdmac->is_ram_script = true; break; case IMX_DMATYPE_MSHC: per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; @@ -968,6 +1104,14 @@ static void sdma_get_pc(struct sdma_channel *sdmac, case IMX_DMATYPE_IPU_MEMORY: emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; break; + case IMX_DMATYPE_HDMI: + emi_2_per = sdma->script_addrs->hdmi_dma_addr; + sdmac->is_ram_script = true; + break; + case IMX_DMATYPE_MULTI_SAI: + per_2_emi = sdma->script_addrs->sai_2_mcu_addr; + emi_2_per = sdma->script_addrs->mcu_2_sai_addr; + sdmac->is_ram_script = true; default: break; } @@ -988,9 +1132,6 @@ static int sdma_load_context(struct sdma_channel *sdmac) int ret; unsigned long flags; - if (sdmac->context_loaded) - return 0; - if (sdmac->direction == DMA_DEV_TO_MEM) load_address = sdmac->pc_from_device; else if (sdmac->direction == DMA_DEV_TO_DEV) @@ -1018,11 +1159,16 @@ static int sdma_load_context(struct sdma_channel *sdmac) /* Send by context the event mask,base address for peripheral * and watermark level */ - context->gReg[0] = sdmac->event_mask[1]; - context->gReg[1] = sdmac->event_mask[0]; - context->gReg[2] = sdmac->per_addr; - context->gReg[6] = sdmac->shp_addr; - context->gReg[7] = sdmac->watermark_level; + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + context->gReg[4] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + } else { + context->gReg[0] = sdmac->event_mask[1]; + context->gReg[1] = sdmac->event_mask[0]; + context->gReg[2] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + context->gReg[7] = sdmac->watermark_level; + } bd0->mode.command = C0_SETDM; bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; @@ -1033,7 +1179,30 @@ static int sdma_load_context(struct sdma_channel *sdmac) spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - sdmac->context_loaded = true; + return ret; +} + +static int sdma_save_restore_context(struct sdma_engine *sdma, bool save) +{ + struct sdma_context_data *context = sdma->context; + struct sdma_buffer_descriptor *bd0 = sdma->bd0; + unsigned long flags; + int ret; + + spin_lock_irqsave(&sdma->channel_0_lock, flags); + + if (save) + bd0->mode.command = C0_GETDM; + else + bd0->mode.command = C0_SETDM; + + bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; + bd0->mode.count = MAX_DMA_CHANNELS * sizeof(*context) / 4; + bd0->buffer_addr = sdma->context_phys; + bd0->ext_buffer_addr = 2048; + ret = sdma_run_channel0(sdma); + + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); return ret; } @@ -1058,9 +1227,6 @@ static void sdma_channel_terminate_work(struct work_struct *work) { struct sdma_channel *sdmac = container_of(work, struct sdma_channel, terminate_worker); - unsigned long flags; - LIST_HEAD(head); - /* * According to NXP R&D team a delay of one BD SDMA cost time * (maximum is 1ms) should be added after disable of the channel @@ -1069,22 +1235,25 @@ static void sdma_channel_terminate_work(struct work_struct *work) */ usleep_range(1000, 2000); - spin_lock_irqsave(&sdmac->vc.lock, flags); - vchan_get_all_descriptors(&sdmac->vc, &head); - sdmac->desc = NULL; - spin_unlock_irqrestore(&sdmac->vc.lock, flags); - vchan_dma_desc_free_list(&sdmac->vc, &head); - sdmac->context_loaded = false; + vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated_node); } static int sdma_disable_channel_async(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); + unsigned long flags; sdma_disable_channel(chan); - if (sdmac->desc) + spin_lock_irqsave(&sdmac->vc.lock, flags); + if (sdmac->desc) { + vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated_node); + sdmac->desc = NULL; + spin_unlock_irqrestore(&sdmac->vc.lock, flags); schedule_work(&sdmac->terminate_worker); + return 0; + } + spin_unlock_irqrestore(&sdmac->vc.lock, flags); return 0; } @@ -1136,12 +1305,36 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; + + if (sdmac->src_dualfifo) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD; + if (sdmac->dst_dualfifo) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD; +} + +static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac) +{ + sdmac->watermark_level &= ~(0xFF << SDMA_WATERMARK_LEVEL_FIFOS_OFF | + SDMA_WATERMARK_LEVEL_SW_DONE | + 0xf << SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF); + + if (sdmac->sw_done) + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE | + sdmac->sw_done_sel << + SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF; + + /* For fifo_num + * bit 12-15 is the fifo number; + * bit 16-19 is the fifo offset, + * so here only need to shift left fifo_num 12 bit for watermake_level + */ + sdmac->watermark_level |= sdmac->fifo_num<< + SDMA_WATERMARK_LEVEL_FIFOS_OFF; } static int sdma_config_channel(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); - int ret; sdma_disable_channel(chan); @@ -1171,8 +1364,21 @@ static int sdma_config_channel(struct dma_chan *chan) if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || sdmac->peripheral_type == IMX_DMATYPE_ASRC) sdma_set_watermarklevel_for_p2p(sdmac); - } else + } else { + /* + * ERR009165 fixed from i.mx6ul, no errata need, + * set bit31 to let sdma script skip the errata. + */ + if (sdmac->peripheral_type == IMX_DMATYPE_CSPI && + sdmac->direction == DMA_MEM_TO_DEV && + sdmac->sdma->drvdata->ecspi_fixed) + __set_bit(31, &sdmac->watermark_level); + else if (sdmac->peripheral_type == + IMX_DMATYPE_MULTI_SAI) + sdma_set_watermarklevel_for_sais(sdmac); + __set_bit(sdmac->event_id0, sdmac->event_mask); + } /* Address */ sdmac->shp_addr = sdmac->per_address; @@ -1181,9 +1387,7 @@ static int sdma_config_channel(struct dma_chan *chan) sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ } - ret = sdma_load_context(sdmac); - - return ret; + return 0; } static int sdma_set_channel_priority(struct sdma_channel *sdmac, @@ -1206,8 +1410,12 @@ static int sdma_request_channel0(struct sdma_engine *sdma) { int ret = -EBUSY; - sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, - GFP_NOWAIT); + if (sdma->iram_pool) + sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, + &sdma->bd0_phys); + else + sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, + &sdma->bd0_phys, GFP_NOWAIT); if (!sdma->bd0) { ret = -ENOMEM; goto out; @@ -1227,10 +1435,15 @@ out: static int sdma_alloc_bd(struct sdma_desc *desc) { u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + struct sdma_engine *sdma = desc->sdmac->sdma; int ret = 0; - desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, - &desc->bd_phys, GFP_NOWAIT); + if (sdma->iram_pool) + desc->bd = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, + &desc->bd_phys); + else + desc->bd = dma_alloc_coherent(sdma->dev, bd_size, + &desc->bd_phys, GFP_NOWAIT); if (!desc->bd) { ret = -ENOMEM; goto out; @@ -1242,9 +1455,14 @@ out: static void sdma_free_bd(struct sdma_desc *desc) { u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); + struct sdma_engine *sdma = desc->sdmac->sdma; - dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, - desc->bd_phys); + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)desc->bd, + PAGE_SIZE); + else + dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, + desc->bd_phys); } static void sdma_desc_free(struct virt_dma_desc *vd) @@ -1255,6 +1473,90 @@ static void sdma_desc_free(struct virt_dma_desc *vd) kfree(desc); } +static int sdma_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + + sdma->fw_loaded = false; + sdma->is_on = false; + + clk_disable(sdma->clk_ipg); + clk_disable(sdma->clk_ahb); + + /* free channel0 bd */ + if (sdma->iram_pool) + gen_pool_free(sdma->iram_pool, (unsigned long)sdma->bd0, + PAGE_SIZE); + else + dma_free_coherent(sdma->dev, PAGE_SIZE, sdma->bd0, + sdma->bd0_phys); + + return 0; +} + +static int sdma_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret; + + ret = clk_enable(sdma->clk_ipg); + if (ret) + return ret; + ret = clk_enable(sdma->clk_ahb); + if (ret) + goto disable_clk_ipg; + + /* Be sure SDMA has not started yet */ + writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); + + /* disable all channels */ + for (i = 0; i < sdma->drvdata->num_events; i++) + writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); + + /* All channels have priority 0 */ + for (i = 0; i < MAX_DMA_CHANNELS; i++) + writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); + + ret = sdma_request_channel0(sdma); + if (ret) + return ret; + + sdma_config_ownership(&sdma->channel[0], false, true, false); + + /* Set Command Channel (Channel Zero) */ + writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); + + /* Set bits of CONFIG register but with static context switching */ + if (sdma->clk_ratio) + writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); + + writel_relaxed(sdma->ccb_phys, sdma->regs + SDMA_H_C0PTR); + + /* Initializes channel's priorities */ + sdma_set_channel_priority(&sdma->channel[0], 7); + + if (sdma->drvdata->pm_runtime) + ret = sdma_get_firmware_wait(sdma, sdma->fw_name); + else + ret = sdma_get_firmware(sdma, sdma->fw_name); + if (ret) + dev_warn(sdma->dev, "failed to get firmware.\n"); + + sdma->is_on = true; + + return 0; + +disable_clk_ipg: + clk_disable(sdma->clk_ipg); + dev_err(sdma->dev, "initialisation failed with %d\n", ret); + + return ret; +} + static int sdma_alloc_chan_resources(struct dma_chan *chan) { struct sdma_channel *sdmac = to_sdma_chan(chan); @@ -1298,25 +1600,21 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan) sdmac->peripheral_type = data->peripheral_type; sdmac->event_id0 = data->dma_request; sdmac->event_id1 = data->dma_request2; + sdmac->src_dualfifo = data->src_dualfifo; + sdmac->dst_dualfifo = data->dst_dualfifo; + /* Get software done selector if sw_done enabled */ + if (data->done_sel & BIT(31)) { + sdmac->sw_done = true; + sdmac->sw_done_sel = (data->done_sel >> 8) & 0xff; + } - ret = clk_enable(sdmac->sdma->clk_ipg); - if (ret) - return ret; - ret = clk_enable(sdmac->sdma->clk_ahb); - if (ret) - goto disable_clk_ipg; + pm_runtime_get_sync(sdmac->sdma->dev); ret = sdma_set_channel_priority(sdmac, prio); if (ret) - goto disable_clk_ahb; + return ret; return 0; - -disable_clk_ahb: - clk_disable(sdmac->sdma->clk_ahb); -disable_clk_ipg: - clk_disable(sdmac->sdma->clk_ipg); - return ret; } static void sdma_free_chan_resources(struct dma_chan *chan) @@ -1328,19 +1626,17 @@ static void sdma_free_chan_resources(struct dma_chan *chan) sdma_channel_synchronize(chan); - if (sdmac->event_id0 >= 0) - sdma_event_disable(sdmac, sdmac->event_id0); + sdma_event_disable(sdmac, sdmac->event_id0); + if (sdmac->event_id1) sdma_event_disable(sdmac, sdmac->event_id1); sdmac->event_id0 = 0; sdmac->event_id1 = 0; - sdmac->context_loaded = false; sdma_set_channel_priority(sdmac, 0); - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); + pm_runtime_put_sync(sdma->dev); } static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, @@ -1348,6 +1644,11 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, { struct sdma_desc *desc; + if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { + dev_err(sdmac->sdma->dev, "sdma firmware not ready!\n"); + goto err_out; + } + desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); if (!desc) goto err_out; @@ -1363,7 +1664,7 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, desc->sdmac = sdmac; desc->num_bd = bds; - if (sdma_alloc_bd(desc)) + if (bds && sdma_alloc_bd(desc)) goto err_desc_out; /* No slave_config called in MEMCPY case, so do here */ @@ -1484,6 +1785,9 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg( if (count & 3 || sg->dma_address & 3) goto err_bd_out; break; + case DMA_SLAVE_BUSWIDTH_3_BYTES: + bd->mode.command = 3; + break; case DMA_SLAVE_BUSWIDTH_2_BYTES: bd->mode.command = 2; if (count & 1 || sg->dma_address & 1) @@ -1528,13 +1832,16 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( { struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; - int num_periods = buf_len / period_len; + int num_periods = 0; int channel = sdmac->channel; int i = 0, buf = 0; struct sdma_desc *desc; dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + num_periods = buf_len / period_len; + sdma_config_write(chan, &sdmac->slave_config, direction); desc = sdma_transfer_init(sdmac, direction, num_periods); @@ -1551,6 +1858,9 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( goto err_bd_out; } + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); + while (buf < buf_len) { struct sdma_buffer_descriptor *bd = &desc->bd[i]; int param; @@ -1598,11 +1908,15 @@ static int sdma_config_write(struct dma_chan *chan, { struct sdma_channel *sdmac = to_sdma_chan(chan); + sdmac->watermark_level = 0; + sdmac->is_ram_script = false; + if (direction == DMA_DEV_TO_MEM) { sdmac->per_address = dmaengine_cfg->src_addr; sdmac->watermark_level = dmaengine_cfg->src_maxburst * dmaengine_cfg->src_addr_width; sdmac->word_size = dmaengine_cfg->src_addr_width; + sdmac->fifo_num = dmaengine_cfg->src_fifo_num; } else if (direction == DMA_DEV_TO_DEV) { sdmac->per_address2 = dmaengine_cfg->src_addr; sdmac->per_address = dmaengine_cfg->dst_addr; @@ -1611,11 +1925,16 @@ static int sdma_config_write(struct dma_chan *chan, sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & SDMA_WATERMARK_LEVEL_HWML; sdmac->word_size = dmaengine_cfg->dst_addr_width; + } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + sdmac->per_address = dmaengine_cfg->dst_addr; + sdmac->per_address2 = dmaengine_cfg->src_addr; + sdmac->watermark_level = 0; } else { sdmac->per_address = dmaengine_cfg->dst_addr; sdmac->watermark_level = dmaengine_cfg->dst_maxburst * dmaengine_cfg->dst_addr_width; sdmac->word_size = dmaengine_cfg->dst_addr_width; + sdmac->fifo_num = dmaengine_cfg->dst_fifo_num; } sdmac->direction = direction; return sdma_config_channel(chan); @@ -1629,11 +1948,9 @@ static int sdma_config(struct dma_chan *chan, memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); /* Set ENBLn earlier to make sure dma request triggered after that */ - if (sdmac->event_id0 >= 0) { - if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) - return -EINVAL; - sdma_event_enable(sdmac, sdmac->event_id0); - } + if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) + return -EINVAL; + sdma_event_enable(sdmac, sdmac->event_id0); if (sdmac->event_id1) { if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) @@ -1694,8 +2011,8 @@ static void sdma_issue_pending(struct dma_chan *chan) #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46 static void sdma_add_scripts(struct sdma_engine *sdma, const struct sdma_script_start_addrs *addr) @@ -1729,12 +2046,21 @@ static void sdma_load_firmware(const struct firmware *fw, void *context) unsigned short *ram_code; if (!fw) { - dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); - /* In this case we just use the ROM firmware. */ + /* Load firmware once more time if timeout */ + if (sdma->fw_fail) + dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); + else { + request_firmware_nowait(THIS_MODULE, + FW_ACTION_HOTPLUG, sdma->fw_name, + sdma->dev, GFP_KERNEL, sdma, + sdma_load_firmware); + sdma->fw_fail++; + } + return; } - if (fw->size < sizeof(*header)) + if (fw->size < sizeof(*header) || sdma->fw_loaded) goto err_firmware; header = (struct sdma_firmware_header *)fw->data; @@ -1763,19 +2089,18 @@ static void sdma_load_firmware(const struct firmware *fw, void *context) addr = (void *)header + header->script_addrs_start; ram_code = (void *)header + header->ram_code_start; + sdma->ram_code_start = header->ram_code_start; - clk_enable(sdma->clk_ipg); - clk_enable(sdma->clk_ahb); /* download the RAM image for SDMA */ sdma_load_script(sdma, ram_code, header->ram_code_size, addr->ram_code_start_addr); - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); sdma_add_scripts(sdma, addr); - dev_info(sdma->dev, "loaded firmware %d.%d\n", + sdma->fw_loaded = true; + + dev_info_once(sdma->dev, "loaded firmware %d.%d\n", header->version_major, header->version_minor); @@ -1861,79 +2186,51 @@ static int sdma_get_firmware(struct sdma_engine *sdma, return ret; } -static int sdma_init(struct sdma_engine *sdma) +static int sdma_get_firmware_wait(struct sdma_engine *sdma, + const char *fw_name) { - int i, ret; - dma_addr_t ccb_phys; + const struct firmware *fw = NULL; + int ret; - ret = clk_enable(sdma->clk_ipg); - if (ret) + ret = request_firmware(&fw, fw_name, sdma->dev); + if (ret < 0 || !fw) { + dev_err(sdma->dev, "unable to find firmware\n"); return ret; - ret = clk_enable(sdma->clk_ahb); - if (ret) - goto disable_clk_ipg; + } + + sdma_load_firmware(fw, (void *)sdma); + + return 0; +} + +static int sdma_init_sw(struct sdma_engine *sdma) +{ + int ret, ccbsize; if (sdma->drvdata->check_ratio && (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) sdma->clk_ratio = 1; - /* Be sure SDMA has not started yet */ - writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); - - sdma->channel_control = dma_alloc_coherent(sdma->dev, - MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + - sizeof(struct sdma_context_data), - &ccb_phys, GFP_KERNEL); + ccbsize = MAX_DMA_CHANNELS * (sizeof(struct sdma_channel_control) + + sizeof(struct sdma_context_data)); + if (sdma->iram_pool) + sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, + ccbsize, &sdma->ccb_phys); + else + sdma->channel_control = dma_alloc_coherent(sdma->dev, ccbsize, + &sdma->ccb_phys, GFP_KERNEL); if (!sdma->channel_control) { ret = -ENOMEM; - goto err_dma_alloc; + return ret; } sdma->context = (void *)sdma->channel_control + MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); - sdma->context_phys = ccb_phys + + sdma->context_phys = sdma->ccb_phys + MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); - /* disable all channels */ - for (i = 0; i < sdma->drvdata->num_events; i++) - writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); - - /* All channels have priority 0 */ - for (i = 0; i < MAX_DMA_CHANNELS; i++) - writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); - - ret = sdma_request_channel0(sdma); - if (ret) - goto err_dma_alloc; - - sdma_config_ownership(&sdma->channel[0], false, true, false); - - /* Set Command Channel (Channel Zero) */ - writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); - - /* Set bits of CONFIG register but with static context switching */ - if (sdma->clk_ratio) - writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); - else - writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); - - writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); - - /* Initializes channel's priorities */ - sdma_set_channel_priority(&sdma->channel[0], 7); - - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); - return 0; - -err_dma_alloc: - clk_disable(sdma->clk_ahb); -disable_clk_ipg: - clk_disable(sdma->clk_ipg); - dev_err(sdma->dev, "initialisation failed with %d\n", ret); - return ret; } static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) @@ -1960,9 +2257,14 @@ static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, if (dma_spec->args_count != 3) return NULL; + memset(&data, 0, sizeof(data)); + data.dma_request = dma_spec->args[0]; data.peripheral_type = dma_spec->args[1]; - data.priority = dma_spec->args[2]; + /* Get sw_done setting if sw_done enabled */ + if (dma_spec->args[2] & BIT(31)) + data.done_sel = dma_spec->args[2]; + data.priority = dma_spec->args[2] & 0xff; /* * init dma_request2 to zero, which is not used by the dts. * For P2P, dma_request2 is init from dma_request_channel(), @@ -2072,6 +2374,7 @@ static int sdma_probe(struct platform_device *pdev) sdmac->channel = i; sdmac->vc.desc_free = sdma_desc_free; + INIT_LIST_HEAD(&sdmac->terminated_node); INIT_WORK(&sdmac->terminate_worker, sdma_channel_terminate_work); /* @@ -2083,7 +2386,7 @@ static int sdma_probe(struct platform_device *pdev) vchan_init(&sdmac->vc, &sdma->dma_device); } - ret = sdma_init(sdma); + ret = sdma_init_sw(sdma); if (ret) goto err_init; @@ -2138,18 +2441,14 @@ static int sdma_probe(struct platform_device *pdev) sdma->spba_end_addr = spba_res.end; } of_node_put(spba_bus); + + sdma->iram_pool = of_gen_pool_get(np, "iram", 0); + if (sdma->iram_pool) + dev_info(&pdev->dev, "alloc bd from iram. \n"); } - /* - * Kick off firmware loading as the very last step: - * attempt to load firmware only if we're not on the error path, because - * the firmware callback requires a fully functional and allocated sdma - * instance. - */ if (pdata) { - ret = sdma_get_firmware(sdma, pdata->fw_name); - if (ret) - dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); + sdma->fw_name = pdata->fw_name; } else { /* * Because that device tree does not encode ROM script address, @@ -2158,15 +2457,16 @@ static int sdma_probe(struct platform_device *pdev) */ ret = of_property_read_string(np, "fsl,sdma-ram-script-name", &fw_name); - if (ret) { + if (ret) dev_warn(&pdev->dev, "failed to get firmware name\n"); - } else { - ret = sdma_get_firmware(sdma, fw_name); - if (ret) - dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); - } + else + sdma->fw_name = fw_name; } + pm_runtime_enable(&pdev->dev); + if (!sdma->drvdata->pm_runtime) + pm_runtime_get_sync(&pdev->dev); + return 0; err_register: @@ -2188,6 +2488,7 @@ static int sdma_remove(struct platform_device *pdev) devm_free_irq(&pdev->dev, sdma->irq, sdma); dma_async_device_unregister(&sdma->dma_device); kfree(sdma->script_addrs); + pm_runtime_put_sync_suspend(sdma->dev); clk_unprepare(sdma->clk_ahb); clk_unprepare(sdma->clk_ipg); /* Kill the tasklet */ @@ -2202,10 +2503,131 @@ static int sdma_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM_SLEEP +static int sdma_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + int i, ret = 0; + + /* Do nothing if not i.MX6SX or i.MX7D, i.MX8MP */ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) + return 0; + + if (!sdma->is_on) + return 0; + + ret = sdma_save_restore_context(sdma, true); + if (ret) { + dev_err(sdma->dev, "save context error!\n"); + return ret; + } + + /* save regs */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + sdma->save_regs[i] = readl_relaxed(sdma->regs + + MXC_SDMA_RESERVED_REG + + 4 * i); + else + sdma->save_regs[i] = readl_relaxed(sdma->regs + 4 * i); + } + + if (sdma->drvdata->has_done0) { + for (i = 0; i < 2; i++) + sdma->save_done0_regs[i] = + readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG + 4 * i); + } + + return 0; +} + +static int sdma_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct sdma_engine *sdma = platform_get_drvdata(pdev); + unsigned long timeout = jiffies + msecs_to_jiffies(2); + int i, ret; + + /* Do nothing if not i.MX6SX or i.MX7D, i.MX8MP*/ + if (sdma->drvdata != &sdma_imx6sx && sdma->drvdata != &sdma_imx7d + && sdma->drvdata != &sdma_imx6ul && sdma->drvdata != &sdma_imx8mp) + return 0; + + if (!sdma->is_on) + return 0; + + /* Do nothing if mega/fast mix not turned off */ + if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) + return 0; + + /* Firmware was lost, mark as "not ready" */ + sdma->fw_loaded = false; + + /* restore regs and load firmware */ + for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) { + /* + * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are + * reserved and can't be touched. Skip these regs. + */ + if (i > SDMA_XTRIG_CONF2 / 4) + writel_relaxed(sdma->save_regs[i], sdma->regs + + MXC_SDMA_RESERVED_REG + 4 * i); + /* set static context switch mode before channel0 running */ + else if (i == SDMA_H_CONFIG / 4) + writel_relaxed(sdma->save_regs[i] & ~SDMA_H_CONFIG_CSM, + sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(sdma->save_regs[i], sdma->regs + 4 * i); + } + + /* restore SDMA_DONEx_CONFIG */ + if (sdma->drvdata->has_done0) { + for (i = 0; i < 2; i++) + writel_relaxed(sdma->save_done0_regs[i], + sdma->regs + SDMA_DONE0_CONFIG + 4 * i); + } + + /* prepare priority for channel0 to start */ + sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); + + ret = sdma_get_firmware(sdma, sdma->fw_name); + if (ret) { + dev_warn(&pdev->dev, "failed to get firmware\n"); + return ret; + } + /* wait firmware loaded */ + do { + if (time_after(jiffies, timeout)) { + dev_warn(&pdev->dev, "failed to load firmware\n"); + break; + } + usleep_range(50, 500); + } while (!sdma->fw_loaded); + + ret = sdma_save_restore_context(sdma, false); + if (ret) + dev_err(sdma->dev, "restore context error!\n"); + + return ret; +} +#endif + +static const struct dev_pm_ops sdma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(sdma_suspend, sdma_resume) + SET_RUNTIME_PM_OPS(sdma_runtime_suspend, sdma_runtime_resume, NULL) +}; + static struct platform_driver sdma_driver = { .driver = { .name = "imx-sdma", .of_match_table = sdma_dt_ids, + .pm = &sdma_pm_ops, }, .id_table = sdma_devtypes, .remove = sdma_remove, diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c index 3039bba0e4d5..9e3027114f59 100644 --- a/drivers/dma/mxs-dma.c +++ b/drivers/dma/mxs-dma.c @@ -25,6 +25,8 @@ #include <linux/of_dma.h> #include <linux/list.h> #include <linux/dma/mxs-dma.h> +#include <linux/pm_runtime.h> +#include <linux/dmapool.h> #include <asm/irq.h> @@ -39,6 +41,8 @@ #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH) #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA) +#define MXS_DMA_RPM_TIMEOUT 50 /* ms */ + #define HW_APBHX_CTRL0 0x000 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28) @@ -118,6 +122,7 @@ struct mxs_dma_chan { enum dma_status status; unsigned int flags; bool reset; + struct dma_pool *ccw_pool; #define MXS_DMA_SG_LOOP (1 << 0) #define MXS_DMA_USE_SEMAPHORE (1 << 1) }; @@ -416,11 +421,13 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) { struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + struct device *dev = &mxs_dma->pdev->dev; int ret; - mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, - CCW_BLOCK_SIZE, - &mxs_chan->ccw_phys, GFP_KERNEL); + mxs_chan->ccw = dma_pool_zalloc(mxs_chan->ccw_pool, + GFP_ATOMIC, + &mxs_chan->ccw_phys); + if (!mxs_chan->ccw) { ret = -ENOMEM; goto err_alloc; @@ -431,9 +438,11 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) if (ret) goto err_irq; - ret = clk_prepare_enable(mxs_dma->clk); - if (ret) + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable clock\n"); goto err_clk; + } mxs_dma_reset_chan(chan); @@ -448,8 +457,8 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan) err_clk: free_irq(mxs_chan->chan_irq, mxs_dma); err_irq: - dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, - mxs_chan->ccw, mxs_chan->ccw_phys); + dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, + mxs_chan->ccw_phys); err_alloc: return ret; } @@ -458,15 +467,18 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan) { struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; + struct device *dev = &mxs_dma->pdev->dev; mxs_dma_disable_chan(chan); free_irq(mxs_chan->chan_irq, mxs_dma); - dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE, - mxs_chan->ccw, mxs_chan->ccw_phys); + dma_pool_free(mxs_chan->ccw_pool, mxs_chan->ccw, + mxs_chan->ccw_phys); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); - clk_disable_unprepare(mxs_dma->clk); } /* @@ -689,14 +701,32 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan, return mxs_chan->status; } -static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) +static int mxs_dma_init_rpm(struct mxs_dma_engine *mxs_dma) +{ + struct device *dev = &mxs_dma->pdev->dev; + + pm_runtime_enable(dev); + pm_runtime_set_autosuspend_delay(dev, MXS_DMA_RPM_TIMEOUT); + pm_runtime_use_autosuspend(dev); + + return 0; +} + +static int mxs_dma_init(struct mxs_dma_engine *mxs_dma) { + struct device *dev = &mxs_dma->pdev->dev; int ret; - ret = clk_prepare_enable(mxs_dma->clk); + ret = mxs_dma_init_rpm(mxs_dma); if (ret) return ret; + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + ret = stmp_reset_block(mxs_dma->base); if (ret) goto err_out; @@ -714,7 +744,8 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); err_out: - clk_disable_unprepare(mxs_dma->clk); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return ret; } @@ -729,6 +760,12 @@ static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; int chan_irq; + if (strcmp(chan->device->dev->driver->name, "mxs-dma")) + return false; + + if (!mxs_dma) + return false; + if (chan->chan_id != param->chan_id) return false; @@ -760,7 +797,7 @@ static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec, ofdma->of_node); } -static int __init mxs_dma_probe(struct platform_device *pdev) +static int mxs_dma_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; const struct platform_device_id *id_entry; @@ -768,6 +805,7 @@ static int __init mxs_dma_probe(struct platform_device *pdev) const struct mxs_dma_type *dma_type; struct mxs_dma_engine *mxs_dma; struct resource *iores; + struct dma_pool *ccw_pool; int ret, i; mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); @@ -815,19 +853,31 @@ static int __init mxs_dma_probe(struct platform_device *pdev) tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet, (unsigned long) mxs_chan); - /* Add the channel to mxs_chan list */ list_add_tail(&mxs_chan->chan.device_node, &mxs_dma->dma_device.channels); } + platform_set_drvdata(pdev, mxs_dma); + mxs_dma->pdev = pdev; + ret = mxs_dma_init(mxs_dma); if (ret) return ret; - mxs_dma->pdev = pdev; mxs_dma->dma_device.dev = &pdev->dev; + /* create the dma pool */ + ccw_pool = dma_pool_create("ccw_pool", + mxs_dma->dma_device.dev, + CCW_BLOCK_SIZE, 32, 0); + + for (i = 0; i < MXS_DMA_CHANNELS; i++) { + struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; + + mxs_chan->ccw_pool = ccw_pool; + } + /* mxs_dma gets 65535 bytes maximum sg size */ mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms; dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); @@ -863,16 +913,83 @@ static int __init mxs_dma_probe(struct platform_device *pdev) return 0; } +static int mxs_dma_remove(struct platform_device *pdev) +{ + struct mxs_dma_engine *mxs_dma = platform_get_drvdata(pdev); + int i; + + dma_async_device_unregister(&mxs_dma->dma_device); + dma_pool_destroy(mxs_dma->mxs_chans[0].ccw_pool); + + for (i = 0; i < MXS_DMA_CHANNELS; i++) { + struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i]; + + tasklet_kill(&mxs_chan->tasklet); + mxs_chan->ccw_pool = NULL; + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int mxs_dma_pm_suspend(struct device *dev) +{ + int ret; + + ret = pm_runtime_force_suspend(dev); + + return ret; +} + +static int mxs_dma_pm_resume(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + int ret; + + ret = mxs_dma_init(mxs_dma); + if (ret) + return ret; + + return 0; +} +#endif + +int mxs_dma_runtime_suspend(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + + clk_disable_unprepare(mxs_dma->clk); + + return 0; +} + +int mxs_dma_runtime_resume(struct device *dev) +{ + struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(mxs_dma->clk); + if (ret) { + dev_err(&mxs_dma->pdev->dev, "failed to enable the clock\n"); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops mxs_dma_pm_ops = { + SET_RUNTIME_PM_OPS(mxs_dma_runtime_suspend, mxs_dma_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(mxs_dma_pm_suspend, mxs_dma_pm_resume) +}; + static struct platform_driver mxs_dma_driver = { .driver = { .name = "mxs-dma", + .pm = &mxs_dma_pm_ops, .of_match_table = mxs_dma_dt_ids, }, .id_table = mxs_dma_ids, + .remove = mxs_dma_remove, + .probe = mxs_dma_probe, }; - -static int __init mxs_dma_module_init(void) -{ - return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe); -} -subsys_initcall(mxs_dma_module_init); +module_platform_driver(mxs_dma_driver); diff --git a/drivers/dma/pxp/Kconfig b/drivers/dma/pxp/Kconfig new file mode 100644 index 000000000000..76717f7d78e1 --- /dev/null +++ b/drivers/dma/pxp/Kconfig @@ -0,0 +1,22 @@ +config MXC_PXP_V2 + bool "MXC PxP V2 support" + depends on ARM + select DMA_ENGINE + help + Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite. + If unsure, select N. + +config MXC_PXP_V3 + bool "MXC PxP V3 support" + depends on ARM + select DMA_ENGINE + help + Support the PxP V3(Pixel Pipeline) on i.MX7D. The PxP V3 supports + more functions than PxP V2, dithering, reagl/-D and etc. + If unsure, select N. + +config MXC_PXP_CLIENT_DEVICE + bool "MXC PxP Client Device" + default y + depends on MXC_PXP_V2 || MXC_PXP_V3 + diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile new file mode 100644 index 000000000000..42e4ace02fbd --- /dev/null +++ b/drivers/dma/pxp/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o +obj-$(CONFIG_MXC_PXP_V3) += pxp_dma_v3.o +obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c new file mode 100644 index 000000000000..2504adf1ae4a --- /dev/null +++ b/drivers/dma/pxp/pxp_device.c @@ -0,0 +1,897 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/fs.h> +#include <linux/slab.h> +#include <linux/uaccess.h> +#include <linux/delay.h> +#include <linux/dmaengine.h> +#include <linux/dma-mapping.h> +#include <linux/sched.h> +#include <linux/module.h> +#include <linux/pxp_device.h> +#include <linux/atomic.h> +#include <linux/platform_data/dma-imx.h> + +#define BUFFER_HASH_ORDER 4 + +static struct pxp_buffer_hash bufhash; +static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL]; +static int major; +static struct class *pxp_class; +static struct device *pxp_dev; + +static int pxp_ht_create(struct pxp_buffer_hash *hash, int order) +{ + unsigned long i; + unsigned long table_size; + + table_size = 1U << order; + + hash->order = order; + hash->hash_table = kmalloc(sizeof(*hash->hash_table) * table_size, GFP_KERNEL); + + if (!hash->hash_table) { + pr_err("%s: Out of memory for hash table\n", __func__); + return -ENOMEM; + } + + for (i = 0; i < table_size; i++) + INIT_HLIST_HEAD(&hash->hash_table[i]); + + return 0; +} + +static int pxp_ht_insert_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *new) +{ + unsigned long hashkey; + struct hlist_head *h_list; + + hashkey = hash_long(new->offset >> PAGE_SHIFT, hash->order); + h_list = &hash->hash_table[hashkey]; + + spin_lock(&hash->hash_lock); + hlist_add_head_rcu(&new->item, h_list); + spin_unlock(&hash->hash_lock); + + return 0; +} + +static int pxp_ht_remove_item(struct pxp_buffer_hash *hash, + struct pxp_buf_obj *obj) +{ + spin_lock(&hash->hash_lock); + hlist_del_init_rcu(&obj->item); + spin_unlock(&hash->hash_lock); + return 0; +} + +static struct hlist_node *pxp_ht_find_key(struct pxp_buffer_hash *hash, + unsigned long key) +{ + struct pxp_buf_obj *entry; + struct hlist_head *h_list; + unsigned long hashkey; + + hashkey = hash_long(key, hash->order); + h_list = &hash->hash_table[hashkey]; + + hlist_for_each_entry_rcu(entry, h_list, item) { + if (entry->offset >> PAGE_SHIFT == key) + return &entry->item; + } + + return NULL; +} + +static void pxp_ht_destroy(struct pxp_buffer_hash *hash) +{ + kfree(hash->hash_table); + hash->hash_table = NULL; +} + +static int pxp_buffer_handle_create(struct pxp_file *file_priv, + struct pxp_buf_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->buffer_lock); + + ret = idr_alloc(&file_priv->buffer_idr, obj, 1, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->buffer_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_buf_obj * +pxp_buffer_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return NULL; + } + + spin_unlock(&file_priv->buffer_lock); + + return obj; +} + +static int pxp_buffer_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_buf_obj *obj; + + spin_lock(&file_priv->buffer_lock); + + obj = idr_find(&file_priv->buffer_idr, handle); + if (!obj) { + spin_unlock(&file_priv->buffer_lock); + return -EINVAL; + } + + idr_remove(&file_priv->buffer_idr, handle); + spin_unlock(&file_priv->buffer_lock); + + return 0; +} + +static int pxp_channel_handle_create(struct pxp_file *file_priv, + struct pxp_chan_obj *obj, + uint32_t *handlep) +{ + int ret; + + idr_preload(GFP_KERNEL); + spin_lock(&file_priv->channel_lock); + + ret = idr_alloc(&file_priv->channel_idr, obj, 0, 0, GFP_NOWAIT); + + spin_unlock(&file_priv->channel_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handlep = ret; + + return 0; +} + +static struct pxp_chan_obj * +pxp_channel_object_lookup(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return NULL; + } + + spin_unlock(&file_priv->channel_lock); + + return obj; +} + +static int pxp_channel_handle_delete(struct pxp_file *file_priv, + uint32_t handle) +{ + struct pxp_chan_obj *obj; + + spin_lock(&file_priv->channel_lock); + + obj = idr_find(&file_priv->channel_idr, handle); + if (!obj) { + spin_unlock(&file_priv->channel_lock); + return -EINVAL; + } + + idr_remove(&file_priv->channel_idr, handle); + spin_unlock(&file_priv->channel_lock); + + return 0; +} + +static int pxp_alloc_dma_buffer(struct pxp_buf_obj *obj) +{ + obj->virtual = dma_alloc_coherent(pxp_dev, PAGE_ALIGN(obj->size), + (dma_addr_t *) (&obj->offset), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc phys_addr = 0x%lx\n", obj->offset); + + if (obj->virtual == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + + return 0; +} + +static void pxp_free_dma_buffer(struct pxp_buf_obj *obj) +{ + if (obj->virtual != NULL) { + dma_free_coherent(pxp_dev, PAGE_ALIGN(obj->size), + obj->virtual, (dma_addr_t)obj->offset); + } +} + +static int +pxp_buffer_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_buf_obj *obj = ptr; + int ret; + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret < 0) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + return 0; +} + +static int +pxp_channel_object_free(int id, void *ptr, void *data) +{ + struct pxp_file *file_priv = data; + struct pxp_chan_obj *obj = ptr; + int chan_id; + + chan_id = obj->chan->chan_id; + wait_event(irq_info[chan_id].waitq, + atomic_read(&irq_info[chan_id].irq_pending) == 0); + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + return 0; +} + +static void pxp_free_buffers(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->buffer_idr, + &pxp_buffer_object_free, file_priv); + idr_destroy(&file_priv->buffer_idr); +} + +static void pxp_free_channels(struct pxp_file *file_priv) +{ + idr_for_each(&file_priv->channel_idr, + &pxp_channel_object_free, file_priv); + idr_destroy(&file_priv->channel_idr); +} + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + int chan_id = pxp_chan->dma_chan.chan_id; + + pr_debug("DMA Done ISR, chan_id %d\n", chan_id); + + atomic_dec(&irq_info[chan_id].irq_pending); + irq_info[chan_id].hist_status = tx_desc->hist_status; + + wake_up(&(irq_info[chan_id].waitq)); +} + +static int pxp_ioc_config_chan(struct pxp_file *priv, unsigned long arg) +{ + struct scatterlist *sg; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_config_data *pxp_conf; + dma_cookie_t cookie; + int handle, chan_id; + struct dma_chan *chan; + struct pxp_chan_obj *obj; + int i = 0, j = 0, k = 0, m = 0, length, ret, sg_len; + + pxp_conf = kzalloc(sizeof(*pxp_conf), GFP_KERNEL); + if (!pxp_conf) + return -ENOMEM; + + ret = copy_from_user(pxp_conf, + (struct pxp_config_data *)arg, + sizeof(struct pxp_config_data)); + if (ret) { + kfree(pxp_conf); + return -EFAULT; + } + + handle = pxp_conf->handle; + obj = pxp_channel_object_lookup(priv, handle); + if (!obj) { + kfree(pxp_conf); + return -EINVAL; + } + chan = obj->chan; + chan_id = chan->chan_id; + + sg_len = 3; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) + sg_len += 4; + if (pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) + sg_len += 4; + + sg = kmalloc(sizeof(*sg) * sg_len, GFP_KERNEL); + if (!sg) { + kfree(pxp_conf); + return -ENOMEM; + } + + sg_init_table(sg, sg_len); + + txd = chan->device->device_prep_slave_sg(chan, + sg, sg_len, + DMA_TO_DEVICE, + DMA_PREP_INTERRUPT, + NULL); + if (!txd) { + pr_err("Error preparing a DMA transaction descriptor.\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + desc = to_tx_desc(txd); + + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) { /* S0 */ + memcpy(&desc->proc_data, + &pxp_conf->proc_data, + sizeof(struct pxp_proc_data)); + memcpy(&desc->layer_param.s0_param, + &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 1) { /* Output */ + memcpy(&desc->layer_param.out_param, + &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if (i == 2) { + /* OverLay */ + memcpy(&desc->layer_param.ol_param, + &pxp_conf->ol_param, + sizeof(struct pxp_layer_param)); + desc = desc->next; + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_A) && (j < 4)) { + for (j = 0; j < 4; j++) { + if (j == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH0; + } else if (j == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_FETCH1; + } else if (j == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE0; + } else if (j == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_a_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_A_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_WFE_B) && (m < 4)) { + for (m = 0; m < 4; m++) { + if (m == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH0; + } else if (m == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_FETCH1; + } else if (m == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE0; + } else if (m == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->wfe_b_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_WFE_B_STORE1; + } + + desc = desc->next; + } + + i += 4; + + } else if ((pxp_conf->proc_data.engine_enable & PXP_ENABLE_DITHER) && (k < 4)) { + for (k = 0; k < 4; k++) { + if (k == 0) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH0; + } else if (k == 1) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_fetch_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_FETCH1; + } else if (k == 2) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[0], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE0; + } else if (k == 3) { + memcpy(&desc->layer_param.processing_param, + &pxp_conf->dither_store_param[1], + sizeof(struct pxp_layer_param)); + desc->layer_param.processing_param.flag = PXP_BUF_FLAG_DITHER_STORE1; + } + + desc = desc->next; + } + + i += 4; + } + } + + cookie = txd->tx_submit(txd); + if (cookie < 0) { + pr_err("Error tx_submit\n"); + kfree(pxp_conf); + kfree(sg); + return -EIO; + } + + atomic_inc(&irq_info[chan_id].irq_pending); + + kfree(pxp_conf); + kfree(sg); + + return 0; +} + +static int pxp_device_open(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + filp->private_data = priv; + priv->filp = filp; + + idr_init(&priv->buffer_idr); + spin_lock_init(&priv->buffer_lock); + + idr_init(&priv->channel_idr); + spin_lock_init(&priv->channel_lock); + + return 0; +} + +static int pxp_device_release(struct inode *inode, struct file *filp) +{ + struct pxp_file *priv = filp->private_data; + + if (priv) { + pxp_free_channels(priv); + pxp_free_buffers(priv); + kfree(priv); + filp->private_data = NULL; + } + + return 0; +} + +static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma) +{ + int request_size; + struct hlist_node *node; + struct pxp_buf_obj *obj; + + request_size = vma->vm_end - vma->vm_start; + + pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff), + request_size); + + node = pxp_ht_find_key(&bufhash, vma->vm_pgoff); + if (!node) + return -EINVAL; + + obj = list_entry(node, struct pxp_buf_obj, item); + if (obj->offset + (obj->size >> PAGE_SHIFT) < + (vma->vm_pgoff + vma_pages(vma))) + return -ENOMEM; + + switch (obj->mem_type) { + case MEMORY_TYPE_UNCACHED: + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + break; + case MEMORY_TYPE_WC: + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + break; + case MEMORY_TYPE_CACHED: + break; + default: + pr_err("%s: invalid memory type!\n", __func__); + return -EINVAL; + } + + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + request_size, vma->vm_page_prot) ? -EAGAIN : 0; +} + +static bool chan_filter(struct dma_chan *chan, void *arg) +{ + if (imx_dma_is_pxp(chan)) + return true; + else + return false; +} + +static long pxp_device_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + struct pxp_file *file_priv = filp->private_data; + + switch (cmd) { + case PXP_IOC_GET_CHAN: + { + int ret; + struct dma_chan *chan = NULL; + dma_cap_mask_t mask; + struct pxp_chan_obj *obj = NULL; + + pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__); + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + + chan = dma_request_channel(mask, chan_filter, NULL); + if (!chan) { + pr_err("Unsccessfully received channel!\n"); + return -EBUSY; + } + + pr_debug("Successfully received channel." + "chan_id %d\n", chan->chan_id); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) { + dma_release_channel(chan); + return -ENOMEM; + } + obj->chan = chan; + + ret = pxp_channel_handle_create(file_priv, obj, + &obj->handle); + if (ret) { + dma_release_channel(chan); + kfree(obj); + return ret; + } + + init_waitqueue_head(&(irq_info[chan->chan_id].waitq)); + if (put_user(obj->handle, (u32 __user *) arg)) { + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(chan); + kfree(obj); + return -EFAULT; + } + + break; + } + case PXP_IOC_PUT_CHAN: + { + int handle; + struct pxp_chan_obj *obj; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + pr_debug("%d release handle %d\n", __LINE__, handle); + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + pxp_channel_handle_delete(file_priv, obj->handle); + dma_release_channel(obj->chan); + kfree(obj); + + break; + } + case PXP_IOC_CONFIG_CHAN: + { + int ret; + + ret = pxp_ioc_config_chan(file_priv, arg); + if (ret) + return ret; + + break; + } + case PXP_IOC_START_CHAN: + { + int handle; + struct pxp_chan_obj *obj = NULL; + + if (get_user(handle, (u32 __user *) arg)) + return -EFAULT; + + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + + dma_async_issue_pending(obj->chan); + + break; + } + case PXP_IOC_GET_PHYMEM: + { + struct pxp_mem_desc buffer; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&buffer, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EFAULT; + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + buffer.size); + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + obj->size = buffer.size; + obj->mem_type = buffer.mtype; + + ret = pxp_alloc_dma_buffer(obj); + if (ret == -1) { + printk(KERN_ERR + "Physical memory allocation error!\n"); + kfree(obj); + return ret; + } + + ret = pxp_buffer_handle_create(file_priv, obj, &obj->handle); + if (ret) { + pxp_free_dma_buffer(obj); + kfree(obj); + return ret; + } + buffer.handle = obj->handle; + buffer.phys_addr = obj->offset; + + ret = copy_to_user((void __user *)arg, &buffer, + sizeof(struct pxp_mem_desc)); + if (ret) { + pxp_buffer_handle_delete(file_priv, buffer.handle); + pxp_free_dma_buffer(obj); + kfree(obj); + return -EFAULT; + } + + pxp_ht_insert_item(&bufhash, obj); + + break; + } + case PXP_IOC_PUT_PHYMEM: + { + struct pxp_mem_desc pxp_mem; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&pxp_mem, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EACCES; + + obj = pxp_buffer_object_lookup(file_priv, pxp_mem.handle); + if (!obj) + return -EINVAL; + + ret = pxp_buffer_handle_delete(file_priv, obj->handle); + if (ret) + return ret; + + pxp_ht_remove_item(&bufhash, obj); + pxp_free_dma_buffer(obj); + kfree(obj); + + break; + } + case PXP_IOC_FLUSH_PHYMEM: + { + int ret; + struct pxp_mem_flush flush; + struct pxp_buf_obj *obj; + + ret = copy_from_user(&flush, + (struct pxp_mem_flush *)arg, + sizeof(struct pxp_mem_flush)); + if (ret) + return -EACCES; + + obj = pxp_buffer_object_lookup(file_priv, flush.handle); + if (!obj) + return -EINVAL; + + switch (flush.type) { + case CACHE_CLEAN: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_TO_DEVICE); + break; + case CACHE_INVALIDATE: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + case CACHE_FLUSH: + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_TO_DEVICE); + dma_sync_single_for_device(NULL, obj->offset, + obj->size, DMA_FROM_DEVICE); + break; + default: + pr_err("%s: invalid cache flush type\n", __func__); + return -EINVAL; + } + + break; + } + case PXP_IOC_WAIT4CMPLT: + { + struct pxp_chan_handle chan_handle; + int ret, chan_id, handle; + struct pxp_chan_obj *obj = NULL; + + ret = copy_from_user(&chan_handle, + (struct pxp_chan_handle *)arg, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + + handle = chan_handle.handle; + obj = pxp_channel_object_lookup(file_priv, handle); + if (!obj) + return -EINVAL; + chan_id = obj->chan->chan_id; + + ret = wait_event_interruptible + (irq_info[chan_id].waitq, + (atomic_read(&irq_info[chan_id].irq_pending) == 0)); + if (ret < 0) + return -ERESTARTSYS; + + chan_handle.hist_status = irq_info[chan_id].hist_status; + ret = copy_to_user((struct pxp_chan_handle *)arg, + &chan_handle, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + break; + } + default: + break; + } + + return 0; +} + +static const struct file_operations pxp_device_fops = { + .open = pxp_device_open, + .release = pxp_device_release, + .unlocked_ioctl = pxp_device_ioctl, + .mmap = pxp_device_mmap, +}; + +int register_pxp_device(void) +{ + int ret; + + if (!major) { + major = register_chrdev(0, "pxp_device", &pxp_device_fops); + if (major < 0) { + printk(KERN_ERR "Unable to register pxp device\n"); + ret = major; + goto register_cdev_fail; + } + + pxp_class = class_create(THIS_MODULE, "pxp_device"); + if (IS_ERR(pxp_class)) { + ret = PTR_ERR(pxp_class); + goto pxp_class_fail; + } + + pxp_dev = device_create(pxp_class, NULL, MKDEV(major, 0), + NULL, "pxp_device"); + if (IS_ERR(pxp_dev)) { + ret = PTR_ERR(pxp_dev); + goto dev_create_fail; + } + pxp_dev->dma_mask = kmalloc(sizeof(*pxp_dev->dma_mask), + GFP_KERNEL); + *pxp_dev->dma_mask = DMA_BIT_MASK(32); + pxp_dev->coherent_dma_mask = DMA_BIT_MASK(32); + } + + ret = pxp_ht_create(&bufhash, BUFFER_HASH_ORDER); + if (ret) { + goto ht_create_fail; + } + spin_lock_init(&(bufhash.hash_lock)); + + pr_debug("PxP_Device registered Successfully\n"); + return 0; + +ht_create_fail: + device_destroy(pxp_class, MKDEV(major, 0)); +dev_create_fail: + class_destroy(pxp_class); +pxp_class_fail: + unregister_chrdev(major, "pxp_device"); +register_cdev_fail: + return ret; +} + +void unregister_pxp_device(void) +{ + pxp_ht_destroy(&bufhash); + if (major) { + device_destroy(pxp_class, MKDEV(major, 0)); + class_destroy(pxp_class); + unregister_chrdev(major, "pxp_device"); + major = 0; + } +} diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c new file mode 100644 index 000000000000..7b83dedc629b --- /dev/null +++ b/drivers/dma/pxp/pxp_dma_v2.c @@ -0,0 +1,1849 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/dmaengine.h> +#include <linux/freezer.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/kthread.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/pxp_dma.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/timer.h> +#include <linux/vmalloc.h> +#include <linux/workqueue.h> + +#include "regs-pxp_v2.h" + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; + +struct pxp_dma { + struct dma_device dma; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *clk; + struct clk *clk_disp_axi; /* may exist on some SoC for gating */ + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); + dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF)); + dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); + dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); + dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); + dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CTRL)); + dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BUF)); + dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_UBUF)); + dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_VBUF)); + dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_PITCH)); + dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND)); + dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_SCALE)); + dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CTRL)); + dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_BUF)); + dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_PITCH)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); + dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_DATA)); + dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); + dev_dbg(pxp->dev, "PXP_CFA 0x%x", + __raw_readl(pxp->base + HW_PXP_CFA)); + dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST_CTRL)); + dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST2_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST4_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3)); + dev_dbg(pxp->dev, "PXP_POWER 0x%x", + __raw_readl(pxp->base + HW_PXP_POWER)); + dev_dbg(pxp->dev, "PXP_NEXT 0x%x", + __raw_readl(pxp->base + HW_PXP_NEXT)); + dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); + dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUG)); + dev_dbg(pxp->dev, "PXP_VERSION 0x%x", + __raw_readl(pxp->base + HW_PXP_VERSION)); +} + +static bool is_yuv(u32 pix_fmt) +{ + switch (pix_fmt) { + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_Y41P: + case PXP_PIX_FMT_VUY444: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YVU410P: + case PXP_PIX_FMT_YUV410P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV420P2: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV422P: + return true; + default: + return false; + } +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_set_ctrl(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 ctrl; + u32 fmt_ctrl; + int need_swap = 0; /* to support YUYV and YVYU formats */ + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + need_swap = 1; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap); + __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL_SET); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_BGRA32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl); + __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL); + + ctrl = 0; + if (proc_data->scaling) + ; + if (proc_data->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (proc_data->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (proc_data->rotate) + ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90); + + /* In default, the block size is set to 8x8 + * But block size can be set to 16x16 due to + * blocksize variable modification + */ + ctrl |= block_size << 23; + + __raw_writel(ctrl, pxp->base + HW_PXP_CTRL); +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET); + __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static void pxp_set_outbuf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF); + + if ((out_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (out_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + dma_addr_t Y, U; + + Y = out_params->paddr; + U = Y + (out_params->width * out_params->height); + + __raw_writel(U, pxp->base + HW_PXP_OUT_BUF2); + } + + if (proc_data->rotate == 90 || proc_data->rotate == 270) + __raw_writel(BF_PXP_OUT_LRC_X(out_params->height - 1) | + BF_PXP_OUT_LRC_Y(out_params->width - 1), + pxp->base + HW_PXP_OUT_LRC); + else + __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) | + BF_PXP_OUT_LRC_Y(out_params->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24) { + __raw_writel(out_params->stride * 3, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_BGRA32 || + out_params->pixel_fmt == PXP_PIX_FMT_XRGB32) { + __raw_writel(out_params->stride << 2, + pxp->base + HW_PXP_OUT_PITCH); + } else if ((out_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (out_params->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_UYVY || + (out_params->pixel_fmt == PXP_PIX_FMT_VYUY)) { + __raw_writel(out_params->stride << 1, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GREY || + out_params->pixel_fmt == PXP_PIX_FMT_NV12 || + out_params->pixel_fmt == PXP_PIX_FMT_NV21 || + out_params->pixel_fmt == PXP_PIX_FMT_NV16 || + out_params->pixel_fmt == PXP_PIX_FMT_NV61) { + __raw_writel(out_params->stride, + pxp->base + HW_PXP_OUT_PITCH); + } else if (out_params->pixel_fmt == PXP_PIX_FMT_GY04) { + __raw_writel(out_params->stride >> 1, + pxp->base + HW_PXP_OUT_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_OUT_PITCH); + } + + /* set global alpha if necessary */ + if (out_params->global_alpha_enable) { + __raw_writel(out_params->global_alpha << 24, + pxp->base + HW_PXP_OUT_CTRL_SET); + __raw_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, + pxp->base + HW_PXP_OUT_CTRL_SET); + } +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH); + } else { + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYLOW); + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_PS_CLRKEYHIGH); + } +} + +static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_AS_CLRKEYHIGH); + } else { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH); + } +} + +static void pxp_set_oln(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + dma_addr_t phys_addr = olparams_data->paddr; + u32 pitch = olparams_data->stride ? olparams_data->stride : + olparams_data->width; + + __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF); + + /* Fixme */ + if (olparams_data->width == 0 && olparams_data->height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC); + } else { + __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC); + __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) | + BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1), + pxp->base + HW_PXP_OUT_AS_LRC); + } + + if ((olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32)) { + __raw_writel(pitch << 2, + pxp->base + HW_PXP_AS_PITCH); + } else if ((olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) || + (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555)) { + __raw_writel(pitch << 1, + pxp->base + HW_PXP_AS_PITCH); + } else { + __raw_writel(0, pxp->base + HW_PXP_AS_PITCH); + } +} + +static void pxp_set_olparam(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + u32 olparam; + + olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha); + if (olparams_data->pixel_fmt == PXP_PIX_FMT_XRGB32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__ARGB8888); + if (!olparams_data->combine_enable) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + olparam |= 0x3 << 16; + } + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565); + } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB555) { + olparam |= + BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB555); + } + + if (olparams_data->global_alpha_enable) { + if (olparams_data->global_override) { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Override); + } else { + olparam |= + BF_PXP_AS_CTRL_ALPHA_CTRL + (BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply); + } + if (olparams_data->alpha_invert) + olparam |= BM_PXP_AS_CTRL_ALPHA_INVERT; + } + if (olparams_data->color_key_enable) + olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY; + + __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL); +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + u32 s0param_ulc, s0param_lrc; + + /* contains the coordinate for the PS in the OUTPUT buffer. */ + if ((pxp_conf->s0_param).width == 0 && + (pxp_conf->s0_param).height == 0) { + __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(0x0, pxp->base + HW_PXP_OUT_PS_LRC); + } else { + switch (proc_data->rotate) { + case 0: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 90: + s0param_ulc = BF_PXP_OUT_PS_ULC_Y(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_X(proc_data->drect.top); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + case 180: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->width - (proc_data->drect.left + proc_data->drect.width)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1); + break; + case 270: + s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->height - (proc_data->drect.top + proc_data->drect.height)); + s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.left); + s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1); + s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1); + break; + default: + return; + } + __raw_writel(s0param_ulc, pxp->base + HW_PXP_OUT_PS_ULC); + __raw_writel(s0param_lrc, pxp->base + HW_PXP_OUT_PS_LRC); + } + + /* Since user apps always pass the rotated drect + * to this driver, we need to first swap the width + * and height which is used to calculate the scale + * factors later. + */ + if (proc_data->rotate == 90 || proc_data->rotate == 270) { + int temp; + temp = proc_data->drect.width; + proc_data->drect.width = proc_data->drect.height; + proc_data->drect.height = temp; + } +} + +/* crop behavior is re-designed in h/w. */ +static void pxp_set_s0crop(struct pxps *pxp) +{ + /* + * place-holder, it's implemented in other functions in this driver. + * Refer to "Clipping source images" section in RM for detail. + */ +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + u32 decx, decy, xdec = 0, ydec = 0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + proc_data->scaling = 1; + + if (!proc_data->drect.width || !proc_data->drect.height) { + pr_err("Invalid drect width and height passed in\n"); + return -EINVAL; + } + + decx = proc_data->srect.width / proc_data->drect.width; + decy = proc_data->srect.height / proc_data->drect.height; + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + xdec = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + xdec = 2; + } else if (decx >= 8) { + decx = 8; + xdec = 3; + } + xscale = proc_data->srect.width * 0x1000 / + (proc_data->drect.width * decx); + } else { + if (!is_yuv(s0_params->pixel_fmt) || + (is_yuv(s0_params->pixel_fmt) == + is_yuv(out_params->pixel_fmt)) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) || + (s0_params->pixel_fmt == PXP_PIX_FMT_VUY444)) { + if ((proc_data->srect.width > 1) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 1) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } else { + if ((proc_data->srect.width > 2) && + (proc_data->drect.width > 1)) + xscale = (proc_data->srect.width - 2) * 0x1000 / + (proc_data->drect.width - 1); + else + xscale = proc_data->srect.width * 0x1000 / + proc_data->drect.width; + } + } + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ydec = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ydec = 2; + } else if (decy >= 8) { + decy = 8; + ydec = 3; + } + yscale = proc_data->srect.height * 0x1000 / + (proc_data->drect.height * decy); + } else { + if ((proc_data->srect.height > 1) && + (proc_data->drect.height > 1)) + yscale = (proc_data->srect.height - 1) * 0x1000 / + (proc_data->drect.height - 1); + else + yscale = proc_data->srect.height * 0x1000 / + proc_data->drect.height; + } + + __raw_writel((xdec << 10) | (ydec << 8), pxp->base + HW_PXP_PS_CTRL); + + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) | + BF_PXP_PS_SCALE_XSCALE(xscale); + __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE); + + pxp_set_ctrl(pxp); + + return ret; +} + +static void pxp_set_bg(struct pxps *pxp) +{ + __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND); +} + +static void pxp_set_lut(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + int lut_op = pxp_conf->proc_data.lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = pxp_conf->proc_data.lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && pxp_conf->proc_data.lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp->lut_state = lut_op; +} + +static void pxp_set_csc(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + bool input_is_YUV = is_yuv(s0_params->pixel_fmt); + bool output_is_YUV = is_yuv(out_params->pixel_fmt); + + if (input_is_YUV && output_is_YUV) { + /* + * Input = YUV, Output = YUV + * No CSC unless we need to do combining + */ + if (ol_params->combine_enable) { + /* Must convert to RGB for combining with RGB overlay */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* Input & Output both YUV, so bypass both CSCs */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + } else if (input_is_YUV && !output_is_YUV) { + /* + * Input = YUV, Output = RGB + * Use CSC1 to convert to RGB + */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0); + __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1); + __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } else if (!input_is_YUV && output_is_YUV) { + /* + * Input = RGB, Output = YUV + * Use CSC2 to convert to YUV + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5); + } else { + /* + * Input = RGB, Output = RGB + * Input & Output both RGB, so bypass both CSCs + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL); + } + + /* YCrCb colorspace */ + /* Not sure when we use this...no YCrCb formats are defined for PxP */ + /* + __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); + */ + +} + +static void pxp_set_s0buf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + dma_addr_t Y, U, V; + dma_addr_t Y1, U1, V1; + u32 offset, bpp = 1; + u32 pitch = s0_params->stride ? s0_params->stride : + s0_params->width; + + Y = s0_params->paddr; + + if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + bpp = 2; + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32) + bpp = 4; + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) * bpp; + /* clipping or cropping */ + Y1 = Y + offset; + __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF); + if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)) { + /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */ + int s = 2; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) + s = 1; + + offset = proc_data->srect.top * s0_params->width / 4 + + proc_data->srect.left / 2; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + V = U + ((s0_params->width * s0_params->height) >> s); + V1 = V + offset; + if (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) { + __raw_writel(V1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(U1, pxp->base + HW_PXP_PS_VBUF); + } else { + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF); + } + } else if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV12) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV21) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) { + int s = 2; + if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV16) || + (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) + s = 1; + + offset = (proc_data->srect.top * s0_params->width + + proc_data->srect.left) / s; + U = Y + (s0_params->width * s0_params->height); + U1 = U + offset; + + __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF); + } + + /* TODO: only support RGB565, Y8, Y4, YUV420 */ + if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P || + s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P || + s0_params->pixel_fmt == PXP_PIX_FMT_NV12 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV21 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV16 || + s0_params->pixel_fmt == PXP_PIX_FMT_NV61 || + s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) { + __raw_writel(pitch, pxp->base + HW_PXP_PS_PITCH); + } + else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) + __raw_writel(pitch >> 1, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_XRGB32 || + s0_params->pixel_fmt == PXP_PIX_FMT_VUY444) + __raw_writel(pitch << 2, + pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_UYVY || + s0_params->pixel_fmt == PXP_PIX_FMT_YUYV || + s0_params->pixel_fmt == PXP_PIX_FMT_VYUY || + s0_params->pixel_fmt == PXP_PIX_FMT_YVYU) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else if ((s0_params->pixel_fmt == PXP_PIX_FMT_RGB565) || + (s0_params->pixel_fmt == PXP_PIX_FMT_RGB555)) + __raw_writel(pitch << 1, + pxp->base + HW_PXP_PS_PITCH); + else + __raw_writel(0, pxp->base + HW_PXP_PS_PITCH); +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + /* Configure PxP regs */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + pxp_set_s0colorkey(pxp); + + pxp_set_oln(0, pxp); + pxp_set_olparam(0, pxp); + pxp_set_olcolorkey(0, pxp); + + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + pxp_set_s0buf(pxp); + pxp_set_outbuf(pxp); + + return 0; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + + if (pxp->clk_disp_axi) + clk_prepare_enable(pxp->clk_disp_axi); + clk_prepare_enable(pxp->clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + pxp->clk_stat = CLK_STAT_OFF; + pm_runtime_put_sync_suspend(pxp->dev); + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(struct timer_list *t) +{ + struct pxps *pxp = from_timer(pxp, t, clk_timer); + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + int i = 0; + + memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param) * 8); + memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + } + + i++; + } + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static void pxpdma_dostart_work(struct pxps *pxp) +{ + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + pxp_config(pxp, pxp_chan); + + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + + dump_pxp_reg(pxp); + + hist_status = + __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS; + + __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR); + + /* set the SFTRST bit to be 1 to reset + * the PXP block to its default state. + */ + pxp_soft_reset(pxp); + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx6dl-pxp-dma", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + pxpdma_dostart_work(pxp); + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + } + + return 0; +} + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + pxp->irq = irq; + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + + pxp->pdev = pdev; + + pxp->clk_disp_axi = devm_clk_get(&pdev->dev, "disp-axi"); + if (IS_ERR(pxp->clk_disp_axi)) + pxp->clk_disp_axi = NULL; + pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi"); + + err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0, + "pxp-dmaengine", pxp); + if (err) + goto exit; + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + goto exit; + } + + device_create_file(&pdev->dev, &dev_attr_block_size); + pxp_clk_enable(pxp); + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + INIT_WORK(&pxp->work, clkoff_callback); + timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + register_pxp_device(); + + pm_runtime_enable(pxp->dev); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->clk); + if (pxp->clk_disp_axi) + clk_disable_unprepare(pxp->clk_disp_axi); + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +module_platform_driver(pxp_driver); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/pxp_dma_v3.c b/drivers/dma/pxp/pxp_dma_v3.c new file mode 100644 index 000000000000..0b6afe03c1fa --- /dev/null +++ b/drivers/dma/pxp/pxp_dma_v3.c @@ -0,0 +1,8153 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * + * Copyright 2017-2019 NXP + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include <linux/dma-mapping.h> +#include <linux/freezer.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/kthread.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/dmaengine.h> +#include <linux/pxp_dma.h> +#include <linux/timer.h> +#include <linux/clk.h> +#include <linux/workqueue.h> +#include <linux/sched.h> +#include <linux/of.h> + +#include "regs-pxp_v3.h" +#include "reg_bitfields.h" + +#ifdef CONFIG_MXC_FPGA_M4_TEST +#include "cm4_image.c" +#define FPGA_TCML_ADDR 0x0C7F8000 +#define PINCTRL 0x0C018000 +#define PIN_DOUT 0x700 +void __iomem *fpga_tcml_base; +void __iomem *pinctrl_base; +#endif + + +#define PXP_FILL_TIMEOUT 3000 +#define busy_wait(cond) \ + ({ \ + unsigned long end_jiffies = jiffies + \ + msecs_to_jiffies(PXP_FILL_TIMEOUT); \ + bool succeeded = false; \ + do { \ + if (cond) { \ + succeeded = true; \ + break; \ + } \ + cpu_relax(); \ + } while (time_after(end_jiffies, jiffies)); \ + succeeded; \ + }) + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +#define CONFIG_FB_MXC_EINK_FPGA + +/* define all the pxp 2d nodes */ +#define PXP_2D_PS 0 +#define PXP_2D_AS 1 +#define PXP_2D_INPUT_FETCH0 2 +#define PXP_2D_INPUT_FETCH1 3 +#define PXP_2D_CSC1 4 +#define PXP_2D_ROTATION1 5 +#define PXP_2D_ALPHA0_S0 6 +#define PXP_2D_ALPHA0_S1 7 +#define PXP_2D_ALPHA1_S0 8 +#define PXP_2D_ALPHA1_S1 9 +#define PXP_2D_CSC2 10 +#define PXP_2D_LUT 11 +#define PXP_2D_ROTATION0 12 +#define PXP_2D_OUT 13 +#define PXP_2D_INPUT_STORE0 14 +#define PXP_2D_INPUT_STORE1 15 +#define PXP_2D_NUM 16 + +#define PXP_2D_ALPHA0_S0_S1 0xaa +#define PXP_2D_ALPHA1_S0_S1 0xbb + +#define PXP_2D_MUX_BASE 50 +#define PXP_2D_MUX_MUX0 (PXP_2D_MUX_BASE + 0) +#define PXP_2D_MUX_MUX1 (PXP_2D_MUX_BASE + 1) +#define PXP_2D_MUX_MUX2 (PXP_2D_MUX_BASE + 2) +#define PXP_2D_MUX_MUX3 (PXP_2D_MUX_BASE + 3) +#define PXP_2D_MUX_MUX4 (PXP_2D_MUX_BASE + 4) +#define PXP_2D_MUX_MUX5 (PXP_2D_MUX_BASE + 5) +#define PXP_2D_MUX_MUX6 (PXP_2D_MUX_BASE + 6) +#define PXP_2D_MUX_MUX7 (PXP_2D_MUX_BASE + 7) +#define PXP_2D_MUX_MUX8 (PXP_2D_MUX_BASE + 8) +#define PXP_2D_MUX_MUX9 (PXP_2D_MUX_BASE + 9) +#define PXP_2D_MUX_MUX10 (PXP_2D_MUX_BASE + 10) +#define PXP_2D_MUX_MUX11 (PXP_2D_MUX_BASE + 11) +#define PXP_2D_MUX_MUX12 (PXP_2D_MUX_BASE + 12) +#define PXP_2D_MUX_MUX13 (PXP_2D_MUX_BASE + 13) +#define PXP_2D_MUX_MUX14 (PXP_2D_MUX_BASE + 14) +#define PXP_2D_MUX_MUX15 (PXP_2D_MUX_BASE + 15) + +/* define pxp 2d node types */ +#define PXP_2D_TYPE_INPUT 1 +#define PXP_2D_TYPE_ALU 2 +#define PXP_2D_TYPE_OUTPUT 3 + +#define DISTANCE_INFINITY 0xffff +#define NO_PATH_NODE 0xffffffff + +#define PXP_MAX_INPUT_NUM 2 +#define PXP_MAX_OUTPUT_NUM 2 + +#define FETCH_NOOP 0x01 +#define FETCH_EXPAND 0x02 +#define FETCH_SHIFT 0x04 + +#define STORE_NOOP 0x01 +#define STORE_SHIFT 0x02 +#define STORE_SHRINK 0x04 + +#define NEED_YUV_SWAP 0x02 + +#define IN_NEED_COMPOSITE (0x01 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_CSC (0x02 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_SCALE (0x04 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_ROTATE_FLIP (0x08 | IN_NEED_FMT_UNIFIED) +#define IN_NEED_FMT_UNIFIED 0x10 +#define IN_NEED_SHIFT 0x20 +#define IN_NEED_LUT (0x40 | IN_NEED_UNIFIED) + +#define OUT_NEED_SHRINK 0x100 +#define OUT_NEED_SHIFT 0x200 + +#define PXP_ROTATE_0 0 +#define PXP_ROTATE_90 1 +#define PXP_ROTATE_180 2 +#define PXP_ROTATE_270 3 + +#define PXP_H_FLIP 1 +#define PXP_V_FLIP 2 + +#define PXP_OP_TYPE_2D 0x001 +#define PXP_OP_TYPE_DITHER 0x002 +#define PXP_OP_TYPE_WFE_A 0x004 +#define PXP_OP_TYPE_WFE_B 0x008 + +/* define store engine output mode */ +#define STORE_MODE_NORMAL 1 +#define STORE_MODE_BYPASS 2 +#define STORE_MODE_DUAL 3 +#define STORE_MODE_HANDSHAKE 4 + +/* define fetch engine input mode */ +#define FETCH_MODE_NORMAL 1 +#define FETCH_MODE_BYPASS 2 +#define FETCH_MODE_HANDSHAKE 3 + +#define COMMON_FMT_BPP 32 + +#define R_COMP 0 +#define G_COMP 1 +#define B_COMP 2 +#define A_COMP 3 + +#define Y_COMP 0 +#define U_COMP 1 +#define V_COMP 2 +#define Y1_COMP 4 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; +static unsigned int block_size; +static struct kmem_cache *tx_desc_cache; +static struct kmem_cache *edge_node_cache; +static struct pxp_collision_info col_info; +static bool v3p_flag; +static int alpha_blending_version; +static bool pxp_legacy; + +struct pxp_dma { + struct dma_device dma; +}; + +enum pxp_alpha_blending_version { + PXP_ALPHA_BLENDING_NONE = 0x0, + PXP_ALPHA_BLENDING_V1 = 0x1, + PXP_ALPHA_BLENDING_V2 = 0x2, +}; + +struct pxp_alpha_global { + unsigned int color_key_enable; + bool combine_enable; + bool global_alpha_enable; + bool global_override; + bool alpha_invert; + bool local_alpha_enable; + unsigned char global_alpha; + int comp_mask; +}; + +struct rectangle { + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; +}; + +struct pxp_alpha_info { + uint8_t alpha_mode; + uint8_t rop_type; + + struct pxp_alpha s0_alpha; + struct pxp_alpha s1_alpha; +}; + +struct pxp_op_info{ + uint16_t op_type; + uint16_t rotation; + uint8_t flip; + uint8_t fill_en; + uint32_t fill_data; + uint8_t alpha_blending; + struct pxp_alpha_info alpha_info; + + /* Dithering specific data */ + uint32_t dither_mode; + uint32_t quant_bit; + + /* + * partial: + * 0 - full update + * 1 - partial update + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * lut: + * valid value 0-63 + * set to the lut used for next update + */ + bool partial_update; + bool alpha_en; + bool lut_update; + bool reagl_en; /* enable reagl/-d */ + bool reagl_d_en; /* enable reagl or reagl-d */ + bool detection_only; + int lut; + uint32_t lut_status_1; + uint32_t lut_status_2; +}; + +struct pxp_pixmap { + uint8_t channel_id; + uint8_t bpp; + int32_t pitch; + uint16_t width; + uint16_t height; + struct rectangle crop; + uint32_t rotate; + uint8_t flip; + uint32_t format; /* fourcc pixmap format */ + uint32_t flags; + bool valid; + dma_addr_t paddr; + struct pxp_alpha_global g_alpha; +}; + +struct pxp_task_info { + uint8_t input_num; + uint8_t output_num; + struct pxp_pixmap input[PXP_MAX_INPUT_NUM]; + struct pxp_pixmap output[PXP_MAX_OUTPUT_NUM]; + struct pxp_op_info op_info; + uint32_t pxp_2d_flags; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *ipg_clk; + struct clk *axi_clk; + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + struct work_struct work; + + const struct pxp_devdata *devdata; + struct pxp_task_info task; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; + + /* for pxp config dispatch asynchronously*/ + struct task_struct *dispatch; + wait_queue_head_t thread_waitq; + struct completion complete; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define to_pxp_task_info(op) container_of((op), struct pxp_task_info, op_info) +#define to_pxp_from_task(task) container_of((task), struct pxps, task) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +static uint8_t active_bpp(uint8_t bpp) +{ + switch(bpp) { + case 8: + return 0x0; + case 16: + return 0x1; + case 32: + return 0x2; + case 64: + return 0x3; + default: + return 0xff; + } +} + +static uint8_t rotate_map(uint32_t degree) +{ + switch (degree) { + case 0: + return PXP_ROTATE_0; + case 90: + return PXP_ROTATE_90; + case 180: + return PXP_ROTATE_180; + case 270: + return PXP_ROTATE_270; + default: + return 0; + } +} + +static uint8_t expand_format(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + return 0x0; + case PXP_PIX_FMT_RGB555: + return 0x1; + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + return 0x5; + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + return 0x6; + case PXP_PIX_FMT_NV16: + return 0x7; + default: + return 0xff; + } +} + +struct color_component { + uint8_t id; + uint8_t offset; + uint8_t length; + uint8_t mask; +}; + +struct color { + uint32_t format; + struct color_component comp[4]; +}; + +struct color rgb_colors[] = { + { + .format = PXP_PIX_FMT_RGB565, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR565, + .comp = { + { .id = R_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 6, .mask = 0x3f, }, + { .id = B_COMP, .offset = 11, .length = 6, .mask = 0x3f, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGB555, + .comp = { + { .id = B_COMP, .offset = 0, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 5, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 10, .length = 5, .mask = 0x1f, }, + { .id = A_COMP, .offset = 15, .length = 1, .mask = 0x1, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA555, + .comp = { + { .id = A_COMP, .offset = 0, .length = 1, .mask = 0x1, }, + { .id = B_COMP, .offset = 1, .length = 5, .mask = 0x1f, }, + { .id = G_COMP, .offset = 6, .length = 5, .mask = 0x1f, }, + { .id = R_COMP, .offset = 11, .length = 5, .mask = 0x1f, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB444, + .comp = { + { .id = B_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = A_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA444, + .comp = { + { .id = A_COMP, .offset = 0, .length = 4, .mask = 0xf, }, + { .id = B_COMP, .offset = 4, .length = 4, .mask = 0xf, }, + { .id = G_COMP, .offset = 8, .length = 4, .mask = 0xf, }, + { .id = R_COMP, .offset = 12, .length = 4, .mask = 0xf, }, + }, + }, { + .format = PXP_PIX_FMT_RGB24, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_BGR24, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 0, .length = 0, .mask = 0x0, }, + }, + }, { + .format = PXP_PIX_FMT_XRGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_XBGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRX32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ARGB32, + .comp = { + { .id = B_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_ABGR32, + .comp = { + { .id = R_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_RGBA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_BGRA32, + .comp = { + { .id = A_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = R_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = G_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = B_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* only one plane yuv formats */ +struct color yuv_colors[] = { + { + .format = PXP_PIX_FMT_GREY, + .comp = { + { .id = Y_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 0, .mask = 0x00, }, + { .id = V_COMP, .offset = 16, .length = 0, .mask = 0x00, }, + { .id = A_COMP, .offset = 24, .length = 0, .mask = 0x00, }, + }, + }, { + .format = PXP_PIX_FMT_YUYV, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_UYVY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVYU, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = Y1_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_VYUY, + .comp = { + { .id = Y1_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YUV444, + .comp = { + { .id = V_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = U_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, { + .format = PXP_PIX_FMT_YVU444, + .comp = { + { .id = U_COMP, .offset = 0, .length = 8, .mask = 0xff, }, + { .id = V_COMP, .offset = 8, .length = 8, .mask = 0xff, }, + { .id = Y_COMP, .offset = 16, .length = 8, .mask = 0xff, }, + { .id = A_COMP, .offset = 24, .length = 8, .mask = 0xff, }, + }, + }, +}; + +/* 4 to 1 mux */ +struct mux { + uint32_t id; + uint8_t mux_inputs[4]; + uint8_t mux_outputs[2]; +}; + +/* Adjacent list structure */ +struct edge_node { + uint32_t adjvex; + uint32_t prev_vnode; + struct edge_node *next; + uint32_t mux_used; + struct mux_config muxes; +}; + +struct vetex_node { + uint8_t type; + struct edge_node *first; +}; + +struct path_node { + struct list_head node; + uint32_t id; + uint32_t distance; + uint32_t prev_node; +}; + +static struct vetex_node adj_list[PXP_2D_NUM]; +static struct path_node path_table[PXP_2D_NUM][PXP_2D_NUM]; + +static bool adj_array_v3[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0}, /* 2 */ + {0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + + +static struct mux muxes_v3[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_INPUT_FETCH0, PXP_2D_INPUT_FETCH1, 0xff}, + .mux_outputs = {PXP_2D_ROTATION1, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S1, PXP_2D_MUX_MUX5}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {PXP_2D_INPUT_FETCH1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA1_S0, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {PXP_2D_MUX_MUX1, PXP_2D_ALPHA1_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX7, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {PXP_2D_ALPHA1_S0_S1, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_CSC2, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {PXP_2D_MUX_MUX5, PXP_2D_CSC2, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX10}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {PXP_2D_MUX_MUX7, PXP_2D_LUT, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX15}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_MUX_MUX14}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_MUX_MUX10, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ROTATION0, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {PXP_2D_INPUT_FETCH1, 0xff, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE1, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {PXP_2D_INPUT_FETCH0, PXP_2D_MUX_MUX10, 0xff, 0xff}, + .mux_outputs = {PXP_2D_INPUT_STORE0, 0xff}, + }, +}; + +static bool adj_array_v3p[PXP_2D_NUM][PXP_2D_NUM] = { + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ + {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 0 */ + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, /* 1 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 2 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 3 */ + {0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 4 */ + {0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 5 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 6 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0}, /* 7 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 8 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 9 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0}, /* 10 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0}, /* 11 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0}, /* 12 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 13 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 14 */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* 15 */ +}; + +static struct mux muxes_v3p[16] = { + { + /* mux0 */ + .id = 0, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux1 */ + .id = 1, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux2 */ + .id = 2, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux3 */ + .id = 3, + .mux_inputs = {PXP_2D_CSC1, PXP_2D_ROTATION1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_ALPHA0_S0, 0xff}, + }, { + /* mux4 is not used in ULT1 */ + .id = 4, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux5 */ + .id = 5, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux6 */ + .id = 6, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux7 */ + .id = 7, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux8 */ + .id = 8, + .mux_inputs = {PXP_2D_CSC2, PXP_2D_ALPHA0_S0_S1, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX9, PXP_2D_MUX_MUX11}, + }, { + /* mux9 */ + .id = 9, + .mux_inputs = {0xff, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_LUT, 0xff}, + }, { + /* mux10 */ + .id = 10, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux11 */ + .id = 11, + .mux_inputs = {PXP_2D_LUT, PXP_2D_MUX_MUX8, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX12, PXP_2D_ROTATION0}, + }, { + /* mux12 */ + .id = 12, + .mux_inputs = {PXP_2D_ROTATION0, PXP_2D_MUX_MUX11, 0xff, 0xff}, + .mux_outputs = {PXP_2D_MUX_MUX14, 0xff}, + }, { + /* mux13 */ + .id = 13, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, { + /* mux14 */ + .id = 14, + .mux_inputs = {0xff, PXP_2D_MUX_MUX12, 0xff, 0xff}, + .mux_outputs = {PXP_2D_OUT, 0xff}, + }, { + /* mux15 */ + .id = 15, + .mux_inputs = {0xff, 0xff, 0xff, 0xff}, + .mux_outputs = {0xff, 0xff}, + }, +}; + +static void __iomem *pxp_reg_base; + +#define pxp_writel(val, reg) writel(val, pxp_reg_base + (reg)) + +static __attribute__((aligned (1024*4))) unsigned int active_matrix_data_8x8[64]={ + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004, + 0x06050100, 0x04030207, 0x06050100, 0x04030207, + 0x00040302, 0x07060501, 0x00040302, 0x07060501, + 0x02070605, 0x01000403, 0x02070605, 0x01000403, + 0x05010004, 0x03020706, 0x05010004, 0x03020706, + 0x04030207, 0x06050100, 0x04030207, 0x06050100, + 0x07060501, 0x00040302, 0x07060501, 0x00040302, + 0x01000403, 0x02070605, 0x01000403, 0x02070605, + 0x03020706, 0x05010004, 0x03020706, 0x05010004 + }; + +static __attribute__((aligned (1024*4))) unsigned int bit1_dither_data_8x8[64] = { + + 1, 49*2, 13*2, 61*2, 4*2, 52*2, 16*2, 64*2, + 33*2, 17*2, 45*2, 29*2, 36*2, 20*2, 48*2, 32*2, + 9*2, 57*2, 5*2, 53*2, 12*2, 60*2, 8*2, 56*2, + 41*2, 25*2, 37*2, 21*2, 44*2, 28*2, 40*2, 24*2, + 3*2, 51*2, 15*2, 63*2, 2*2, 50*2, 14*2, 62*2, + 35*2, 19*2, 47*2, 31*2, 34*2, 18*2, 46*2, 30*2, + 11*2, 59*2, 7*2, 55*2, 10*2, 58*2, 6*2, 54*2, + 43*2, 27*2, 39*2, 23*2, 42*2, 26*2, 38*2, 22*2 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit2_dither_data_8x8[64] = { + + 1, 49, 13, 61, 4, 52, 16, 64, + 33, 17, 45, 29, 36, 20, 48, 32, + 9, 57, 5, 53, 12, 60, 8, 56, + 41, 25, 37, 21, 44, 28, 40, 24, + 3, 51, 15, 63, 2, 50, 14, 62, + 35, 19, 47, 31, 34, 18, 46, 30, + 11, 59, 7, 55, 10, 58, 6, 54, + 43, 27, 39, 23, 42, 26, 38, 22 +}; + +static __attribute__((aligned (1024*4))) unsigned int bit4_dither_data_8x8[64] = { + + 1, 49/4, 13/4, 61/4, 4/4, 52/4, 16/4, 64/4, + 33/4, 17/4, 45/4, 29/4, 36/4, 20/4, 48/4, 32/4, + 9/4, 57/4, 5/4, 53/4, 12/4, 60/4, 8/4, 56/4, + 41/4, 25/4, 37/4, 21/4, 44/4, 28/4, 40/4, 24/4, + 3/4, 51/4, 15/4, 63/4, 2/4, 50/4, 14/4, 62/4, + 35/4, 19/4, 47/4, 31/4, 34/4, 18/4, 46/4, 30/4, + 11/4, 59/4, 7/4, 55/4, 10/4, 58/4, 6/4, 54/4, + 43/4, 27/4, 39/4, 23/4, 42/4, 26/4, 38/4, 22/4 +}; + +static void pxp_dithering_configure(struct pxps *pxp); +static void pxp_dithering_configure_v3p(struct pxps *pxp); +static void pxp_dithering_process(struct pxps *pxp); +static void pxp_wfe_a_process(struct pxps *pxp); +static void pxp_wfe_a_process_v3p(struct pxps *pxp); +static void pxp_wfe_a_configure(struct pxps *pxp); +static void pxp_wfe_a_configure_v3p(struct pxps *pxp); +static void pxp_wfe_b_process(struct pxps *pxp); +static void pxp_wfe_b_configure(struct pxps *pxp); +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut); +static void pxp_lut_status_clr(unsigned int lut); +static void pxp_lut_status_clr_v3p(unsigned int lut); +static void pxp_start2(struct pxps *pxp); +static void pxp_data_path_config_v3p(struct pxps *pxp); +static void pxp_soft_reset(struct pxps *pxp); +static void pxp_collision_detection_disable(struct pxps *pxp); +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status); +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info); +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status); +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height); +static void pxp_histogram_disable(struct pxps *pxp); +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set); +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set); +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status); +static void pxp_set_colorkey(struct pxps *pxp); + +enum { + DITHER0_LUT = 0x0, /* Select the LUT memory for access */ + DITHER0_ERR0 = 0x1, /* Select the ERR0 memory for access */ + DITHER0_ERR1 = 0x2, /* Select the ERR1 memory for access */ + DITHER1_LUT = 0x3, /* Select the LUT memory for access */ + DITHER2_LUT = 0x4, /* Select the LUT memory for access */ + ALU_A = 0x5, /* Select the ALU instr memory for access */ + ALU_B = 0x6, /* Select the ALU instr memory for access */ + WFE_A = 0x7, /* Select the WFE_A instr memory for access */ + WFE_B = 0x8, /* Select the WFE_B instr memory for access */ + RESERVED = 0x15, +}; + +enum pxp_devtype { + PXP_V3, + PXP_V3P, /* minor changes over V3, use WFE_B to replace WFE_A */ +}; + +#define pxp_is_v3(pxp) (pxp->devdata->version == 30) +#define pxp_is_v3p(pxp) (pxp->devdata->version == 31) + +struct pxp_devdata { + void (*pxp_wfe_a_configure)(struct pxps *pxp); + void (*pxp_wfe_a_process)(struct pxps *pxp); + void (*pxp_lut_status_set)(struct pxps *pxp, unsigned int lut); + void (*pxp_lut_status_clr)(unsigned int lut); + void (*pxp_dithering_configure)(struct pxps *pxp); + void (*pxp_lut_cleanup_multiple)(struct pxps *pxp, u64 lut, bool set); + void (*pxp_data_path_config)(struct pxps *pxp); + unsigned int version; +}; + +static const struct pxp_devdata pxp_devdata[] = { + [PXP_V3] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure, + .pxp_wfe_a_process = pxp_wfe_a_process, + .pxp_lut_status_set = pxp_lut_status_set, + .pxp_lut_status_clr = pxp_lut_status_clr, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple, + .pxp_dithering_configure = pxp_dithering_configure, + .pxp_data_path_config = NULL, + .version = 30, + }, + [PXP_V3P] = { + .pxp_wfe_a_configure = pxp_wfe_a_configure_v3p, + .pxp_wfe_a_process = pxp_wfe_a_process_v3p, + .pxp_lut_status_set = pxp_lut_status_set_v3p, + .pxp_lut_status_clr = pxp_lut_status_clr_v3p, + .pxp_lut_cleanup_multiple = pxp_lut_cleanup_multiple_v3p, + .pxp_dithering_configure = pxp_dithering_configure_v3p, + .pxp_data_path_config = pxp_data_path_config_v3p, + .version = 31, + }, +}; + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_CTRL)); + dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF)); + dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_BUF2)); + dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PITCH)); + dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC)); + dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x", + __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC)); + dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CTRL)); + dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BUF)); + dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_UBUF)); + dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_VBUF)); + dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_PITCH)); + dev_dbg(pxp->dev, "PXP_PS_BACKGROUND_0 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND_0)); + dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_SCALE)); + dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_OFFSET)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW_0 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW_0)); + dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH_0)); + dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CTRL)); + dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_BUF)); + dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_PITCH)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW_0)); + dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x", + __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH_0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC1_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2_COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_ADDR)); + dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_DATA)); + dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM)); + dev_dbg(pxp->dev, "PXP_CFA 0x%x", + __raw_readl(pxp->base + HW_PXP_CFA)); + dev_dbg(pxp->dev, "PXP_ALPHA_A_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_ALPHA_A_CTRL)); + dev_dbg(pxp->dev, "PXP_ALPHA_B_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_ALPHA_B_CTRL)); + dev_dbg(pxp->dev, "PXP_POWER_REG0 0x%x", + __raw_readl(pxp->base + HW_PXP_POWER_REG0)); + dev_dbg(pxp->dev, "PXP_NEXT 0x%x", + __raw_readl(pxp->base + HW_PXP_NEXT)); + dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUGCTRL)); + dev_dbg(pxp->dev, "PXP_DEBUG 0x%x", + __raw_readl(pxp->base + HW_PXP_DEBUG)); + dev_dbg(pxp->dev, "PXP_VERSION 0x%x", + __raw_readl(pxp->base + HW_PXP_VERSION)); +} + +static void dump_pxp_reg2(struct pxps *pxp) +{ +#ifdef DEBUG + int i = 0; + + for (i=0; i< ((0x33C0/0x10) + 1);i++) { + printk("0x%08x: 0x%08x\n", 0x10*i, __raw_readl(pxp->base + 0x10*i)); + } +#endif +} + +static void print_param(struct pxp_layer_param *p, char *s) +{ + pr_debug("%s: t/l/w/h/s %d/%d/%d/%d/%d, addr %x\n", s, + p->top, p->left, p->width, p->height, p->stride, p->paddr); +} + +/* when it is, return yuv plane number */ +static uint8_t is_yuv(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_VUY444: + return 1; + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + return 2; + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_YVU422P: + return 3; + default: + return 0; + } +} + +static u32 get_bpp_from_fmt(u32 pix_fmt) +{ + unsigned int bpp = 0; + + switch (pix_fmt) { + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YVU422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + bpp = 8; + break; + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + bpp = 16; + break; + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_BGR24: + bpp = 24; + break; + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_VUY444: + bpp = 32; + break; + default: + pr_err("%s: pix_fmt unsupport yet: 0x%x\n", __func__, pix_fmt); + break; + } + + return bpp; +} + +static uint32_t pxp_parse_ps_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YVU420P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_VUY444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_YVYU: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422; + break; + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGBA888; + break; + default: + pr_debug("PS doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void pxp_set_colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_PS_CLRKEYHIGH_0); + } else { + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYLOW_0); + pxp_writel(s0_params->color_key, HW_PXP_PS_CLRKEYHIGH_0); + } + + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(ol_params->color_key, HW_PXP_AS_CLRKEYHIGH_0); + } else { + /* disable color key */ + pxp_writel(0xFFFFFF, HW_PXP_AS_CLRKEYLOW_0); + pxp_writel(0, HW_PXP_AS_CLRKEYHIGH_0); + } +} + +static uint32_t pxp_parse_as_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_RGBA32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_ARGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB1555; + break; + case PXP_PIX_FMT_ARGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__ARGB4444; + break; + case PXP_PIX_FMT_RGBA555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA5551; + break; + case PXP_PIX_FMT_RGBA444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGBA4444; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_RGB444: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB444; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_AS_CTRL_FORMAT__RGB565; + break; + default: + pr_debug("AS doesn't support this format\n"); + fmt_ctrl = 0xf; + break; + } + + return fmt_ctrl; +} + +static uint32_t pxp_parse_out_fmt(uint32_t format) +{ + uint32_t fmt_ctrl; + + switch (format) { + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888; + break; + case PXP_PIX_FMT_XRGB32: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; + break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; + case PXP_PIX_FMT_UYVY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422; + break; + case PXP_PIX_FMT_VYUY: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422; + break; + case PXP_PIX_FMT_NV12: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_NV21: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420; + break; + case PXP_PIX_FMT_NV16: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_NV61: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422; + break; + default: + pr_debug("OUT doesn't support this format\n"); + fmt_ctrl = 0; + } + + return fmt_ctrl; +} + +static void set_mux(struct mux_config *path_ctrl) +{ + struct mux_config *mux = path_ctrl; + + *(uint32_t *)path_ctrl = 0xFFFFFFFF; + + mux->mux0_sel = 0; + mux->mux3_sel = 1; + mux->mux6_sel = 1; + mux->mux8_sel = 0; + mux->mux9_sel = 1; + mux->mux11_sel = 0; + mux->mux12_sel = 1; + mux->mux14_sel = 0; +} + +static void set_mux_val(struct mux_config *muxes, + uint32_t mux_id, + uint32_t mux_val) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + muxes->mux0_sel = mux_val; + break; + case 1: + muxes->mux1_sel = mux_val; + break; + case 2: + muxes->mux2_sel = mux_val; + break; + case 3: + muxes->mux3_sel = mux_val; + break; + case 4: + muxes->mux4_sel = mux_val; + break; + case 5: + muxes->mux5_sel = mux_val; + break; + case 6: + muxes->mux6_sel = mux_val; + break; + case 7: + muxes->mux7_sel = mux_val; + break; + case 8: + muxes->mux8_sel = mux_val; + break; + case 9: + muxes->mux9_sel = mux_val; + break; + case 10: + muxes->mux10_sel = mux_val; + break; + case 11: + muxes->mux11_sel = mux_val; + break; + case 12: + muxes->mux12_sel = mux_val; + break; + case 13: + muxes->mux13_sel = mux_val; + break; + case 14: + muxes->mux14_sel = mux_val; + break; + case 15: + muxes->mux15_sel = mux_val; + break; + default: + break; + } +} + +static uint32_t get_mux_val(struct mux_config *muxes, + uint32_t mux_id) +{ + BUG_ON(!muxes); + BUG_ON(mux_id > 15); + + switch (mux_id) { + case 0: + return muxes->mux0_sel; + case 1: + return muxes->mux1_sel; + case 2: + return muxes->mux2_sel; + case 3: + return muxes->mux3_sel; + case 4: + return muxes->mux4_sel; + case 5: + return muxes->mux5_sel; + case 6: + return muxes->mux6_sel; + case 7: + return muxes->mux7_sel; + case 8: + return muxes->mux8_sel; + case 9: + return muxes->mux9_sel; + case 10: + return muxes->mux10_sel; + case 11: + return muxes->mux11_sel; + case 12: + return muxes->mux12_sel; + case 13: + return muxes->mux13_sel; + case 14: + return muxes->mux14_sel; + case 15: + return muxes->mux15_sel; + default: + return -EINVAL; + } +} + +static uint32_t pxp_store_ctrl_config(struct pxp_pixmap *out, uint8_t mode, + uint8_t fill_en, uint8_t combine_2ch) +{ + struct store_ctrl ctrl; + uint8_t output_active_bpp; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (combine_2ch) { + ctrl.combine_2channel = 1; + if (out) { + output_active_bpp = active_bpp(out->bpp); + ctrl.pack_in_sel = (output_active_bpp < 0x3) ? 1 : 0; + ctrl.store_memory_en = 1; + } + } else { + if (fill_en) { + ctrl.fill_data_en = 1; + ctrl.wr_num_bytes = 2; + } + ctrl.store_memory_en = 1; + } + + if (out->rotate || out->flip) + ctrl.block_en = 1; + + ctrl.ch_en = 1; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_store_size_config(struct pxp_pixmap *out) +{ + struct store_size size; + + memset((void*)&size, 0x0, sizeof(size)); + + size.out_height = out->height - 1; + size.out_width = out->width - 1; + + return *(uint32_t *)&size; +} + +static uint32_t pxp_store_pitch_config(struct pxp_pixmap *out0, + struct pxp_pixmap *out1) +{ + struct store_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + pitch.ch0_out_pitch = out0->pitch; + pitch.ch1_out_pitch = out1 ? out1->pitch : 0; + + return *(uint32_t *)&pitch; +} + +static struct color *pxp_find_rgb_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(rgb_colors) / sizeof(struct color); i++) { + if (rgb_colors[i].format == format) + return &rgb_colors[i]; + } + + return NULL; +} + +static struct color_component *pxp_find_comp(struct color *color, uint8_t id) +{ + int i; + + for (i = 0; i < 4; i++) { + if (id == color->comp[i].id) + return &color->comp[i]; + } + + return NULL; +} + +static struct color *pxp_find_yuv_color(uint32_t format) +{ + int i; + + for (i = 0; i < sizeof(yuv_colors) / sizeof(struct color); i++) { + if (yuv_colors[i].format == format) + return &yuv_colors[i]; + } + + return NULL; +} + +static uint64_t pxp_store_d_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct store_d_mask *d_mask) +{ + int i, shift_width, shift_flag, drop = 0; + struct store_d_shift d_shift; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + BUG_ON((in_fmt == out_fmt)); + memset((void*)&d_shift, 0x0, sizeof(d_shift)); + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for (i = 0; i < 4; i++) { + input_comp = &input_color->comp[i]; + if (!input_comp->length) + continue; + + output_comp = pxp_find_comp(output_color, input_comp->id); + if (!output_comp->length) + continue; + + /* only rgb format can drop color bits */ + if (input_comp->length > output_comp->length) { + drop = input_comp->length - output_comp->length; + input_comp->offset += drop; + } + d_mask[i].d_mask_l = output_comp->mask << input_comp->offset; + + shift_width = input_comp->offset - output_comp->offset; + if (shift_width > 0) + shift_flag = 0; /* right shift */ + else if (shift_width < 0) { + shift_flag = 1; /* left shift */ + shift_width = -shift_width; + } else + shift_width = shift_flag = 0; /* no shift require */ + + switch (i) { + case 0: + d_shift.d_shift_width0 = shift_width; + d_shift.d_shift_flag0 = shift_flag; + break; + case 1: + d_shift.d_shift_width1 = shift_width; + d_shift.d_shift_flag1 = shift_flag; + break; + case 2: + d_shift.d_shift_width2 = shift_width; + d_shift.d_shift_flag2 = shift_flag; + break; + case 3: + d_shift.d_shift_width3 = shift_width; + d_shift.d_shift_flag3 = shift_flag; + break; + default: + printk(KERN_ERR "unsupport d shift\n"); + break; + } + + input_comp->offset -= drop; + } + + return *(uint64_t *)&d_shift; +} + +static uint32_t pxp_store_shift_ctrl_config(struct pxp_pixmap *out, + uint8_t shift_bypass) +{ + struct store_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.output_active_bpp = active_bpp(out->bpp); + /* Not general data */ + if (!shift_bypass) { + switch(out->format) { + case PXP_PIX_FMT_YUYV: + shift_bypass = 1; + /* fall through */ + case PXP_PIX_FMT_YVYU: + shift_ctrl.out_yuv422_1p_en = 1; + break; + case PXP_PIX_FMT_NV16: + shift_bypass = 1; + /* fall through */ + case PXP_PIX_FMT_NV61: + shift_ctrl.out_yuv422_2p_en = 1; + break; + default: + break; + } + } + shift_ctrl.shift_bypass = shift_bypass; + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_ctrl_config(struct pxp_pixmap *in, + uint8_t mode) +{ + struct fetch_ctrl ctrl; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + if (mode == FETCH_MODE_NORMAL) + ctrl.bypass_pixel_en = 0; + + if (in->flip == PXP_H_FLIP) + ctrl.hflip = 1; + else if (in->flip == PXP_V_FLIP) + ctrl.vflip = 1; + + ctrl.rotation_angle = rotate_map(in->rotate); + + if (in->rotate || in->flip) + ctrl.block_en = 1; + + ctrl.ch_en = 1; + + return *(uint32_t *)&ctrl; +} + +static uint32_t pxp_fetch_active_size_ulc(struct pxp_pixmap *in) +{ + struct fetch_active_size_ulc size_ulc; + + memset((void*)&size_ulc, 0x0, sizeof(size_ulc)); + + size_ulc.active_size_ulc_x = 0; + size_ulc.active_size_ulc_y = 0; + + return *(uint32_t *)&size_ulc; +} + +static uint32_t pxp_fetch_active_size_lrc(struct pxp_pixmap *in) +{ + struct fetch_active_size_lrc size_lrc; + + memset((void*)&size_lrc, 0x0, sizeof(size_lrc)); + + size_lrc.active_size_lrc_x = in->crop.width - 1; + size_lrc.active_size_lrc_y = in->crop.height - 1; + + return *(uint32_t *)&size_lrc; +} + +static uint32_t pxp_fetch_pitch_config(struct pxp_pixmap *in0, + struct pxp_pixmap *in1) +{ + struct fetch_pitch pitch; + + memset((void*)&pitch, 0x0, sizeof(pitch)); + + if (in0) + pitch.ch0_input_pitch = in0->pitch; + if (in1) + pitch.ch1_input_pitch = in1->pitch; + + return *(uint32_t *)&pitch; +} + +static uint32_t pxp_fetch_shift_ctrl_config(struct pxp_pixmap *in, + uint8_t shift_bypass, + uint8_t need_expand) +{ + uint8_t input_expand_format; + struct fetch_shift_ctrl shift_ctrl; + + memset((void*)&shift_ctrl, 0x0, sizeof(shift_ctrl)); + + shift_ctrl.input_active_bpp = active_bpp(in->bpp); + shift_ctrl.shift_bypass = shift_bypass; + + if (in->bpp == 32) + need_expand = 0; + + if (need_expand) { + input_expand_format = expand_format(in->format); + + if (input_expand_format <= 0x7) { + shift_ctrl.expand_en = 1; + shift_ctrl.expand_format = input_expand_format; + } + } + + return *(uint32_t *)&shift_ctrl; +} + +static uint32_t pxp_fetch_shift_calc(uint32_t in_fmt, uint32_t out_fmt, + struct fetch_shift_width *shift_width) +{ + int i; + struct fetch_shift_offset shift_offset; + struct color *input_color, *output_color; + struct color_component *input_comp, *output_comp; + + memset((void*)&shift_offset, 0x0, sizeof(shift_offset)); + memset((void*)shift_width, 0x0, sizeof(*shift_width)); + + if (!is_yuv(in_fmt)) { + input_color = pxp_find_rgb_color(in_fmt); + output_color = pxp_find_rgb_color(out_fmt); + } else { + input_color = pxp_find_yuv_color(in_fmt); + output_color = pxp_find_yuv_color(out_fmt); + } + + for(i = 0; i < 4; i++) { + output_comp = &output_color->comp[i]; + if (!output_comp->length) + continue; + + input_comp = pxp_find_comp(input_color, output_comp->id); + switch (i) { + case 0: + shift_offset.offset0 = input_comp->offset; + shift_width->width0 = input_comp->length; + break; + case 1: + shift_offset.offset1 = input_comp->offset; + shift_width->width1 = input_comp->length; + break; + case 2: + shift_offset.offset2 = input_comp->offset; + shift_width->width2 = input_comp->length; + break; + case 3: + shift_offset.offset3 = input_comp->offset; + shift_width->width3 = input_comp->length; + break; + } + } + + return *(uint32_t *)&shift_offset; +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE | + BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT | + BM_PXP_CTRL_ENABLE_PS_AS_OUT | BM_PXP_CTRL_ENABLE_ROTATE0, + pxp->base + HW_PXP_CTRL_SET); + dump_pxp_reg(pxp); + + return 0; +} + +static bool fmt_ps_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_XRGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_XRGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VUY444: + /* need word byte swap */ + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_VYUY: + /* need word byte swap */ + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + case PXP_PIX_FMT_YUV422P: + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_YVU420P: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + return true; + default: + return false; + } +} + +static bool fmt_as_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGBA555: + case PXP_PIX_FMT_RGBA444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + return true; + default: + return false; + } +} + +static bool fmt_out_support(uint32_t format) +{ + switch (format) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_RGB24: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_YUV444: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_VYUY: + case PXP_PIX_FMT_GREY: + case PXP_PIX_FMT_GY04: + case PXP_PIX_FMT_NV16: + case PXP_PIX_FMT_NV12: + case PXP_PIX_FMT_NV61: + case PXP_PIX_FMT_NV21: + return true; + default: + return false; + } +} + +/* common means 'ARGB32/XRGB32/YUV444' */ +static uint8_t fmt_fetch_to_common(uint32_t in) +{ + switch (in) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return FETCH_NOOP; + + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_UYVY: + case PXP_PIX_FMT_NV16: + return FETCH_EXPAND; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + return FETCH_SHIFT; + + case PXP_PIX_FMT_BGR565: + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_VYUY: + return FETCH_EXPAND | FETCH_SHIFT; + + default: + return 0; + } +} + +static uint8_t fmt_store_from_common(uint32_t out) +{ + switch (out) { + case PXP_PIX_FMT_ARGB32: + case PXP_PIX_FMT_XRGB32: + case PXP_PIX_FMT_YUV444: + return STORE_NOOP; + + case PXP_PIX_FMT_YUYV: + case PXP_PIX_FMT_NV16: + return STORE_SHRINK; + + case PXP_PIX_FMT_RGBA32: + case PXP_PIX_FMT_RGBX32: + case PXP_PIX_FMT_BGRA32: + case PXP_PIX_FMT_BGRX32: + case PXP_PIX_FMT_ABGR32: + case PXP_PIX_FMT_XBGR32: + case PXP_PIX_FMT_YVU444: + case PXP_PIX_FMT_RGB565: + case PXP_PIX_FMT_RGB555: + case PXP_PIX_FMT_ARGB555: + case PXP_PIX_FMT_RGB444: + case PXP_PIX_FMT_ARGB444: + case PXP_PIX_FMT_GREY: + return STORE_SHIFT; + + case PXP_PIX_FMT_YVYU: + case PXP_PIX_FMT_NV61: + return STORE_SHIFT | STORE_SHRINK; + + default: + return 0; + } +} + +static void filter_possible_inputs(struct pxp_pixmap *input, + uint32_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + if (!fmt_ps_support(input->format)) + clear = PXP_2D_PS; + break; + case PXP_2D_AS: + if (!fmt_as_support(input->format)) + clear = PXP_2D_AS; + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((is_yuv(input->format) == 3)) { + clear = position; + break; + } + if ((input->flags & IN_NEED_FMT_UNIFIED) || + is_yuv(input->format) == 2) + if (!fmt_fetch_to_common(input->format)) + clear = position; + break; + default: + pr_err("invalid input node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +static void filter_possible_outputs(struct pxp_pixmap *output, + uint32_t *possible) +{ + uint8_t clear = 0xff; + uint8_t position = 0; + + do { + position = find_next_bit((unsigned long *)possible, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_OUT: + if (!fmt_out_support(output->format)) + clear = PXP_2D_OUT; + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + if (output->flags) { + if (!fmt_store_from_common(output->format)) + clear = position; + } + break; + default: + pr_err("invalid output node: %d\n", position); + clear = position; + break; + } + + if (clear != 0xff) { + clear_bit(clear, (unsigned long*)possible); + clear = 0xff; + } + + position++; + } while (1); +} + +static uint32_t calc_shortest_path(uint32_t *nodes_used) +{ + uint32_t distance = 0; + uint32_t from = 0, to = 0, bypass, end; + + do { + from = find_next_bit((unsigned long *)nodes_used, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + if (path_table[to][from].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[to][from].distance; + /* backtrace */ + end = from; + while (1) { + bypass = path_table[to][end].prev_node; + if (bypass == to) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + } + + to = find_next_bit((unsigned long *)nodes_used, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + if (path_table[from][to].distance == DISTANCE_INFINITY) + return DISTANCE_INFINITY; + + distance += path_table[from][to].distance; + /* backtrace */ + end = to; + while (1) { + bypass = path_table[from][end].prev_node; + if (bypass == from) + break; + set_bit(bypass, (unsigned long*)nodes_used); + end = bypass; + } + + from = to + 1; + } while (1); + + return distance; +} + +static uint32_t find_best_path(uint32_t inputs, + uint32_t outputs, + struct pxp_pixmap *in, + uint32_t *nodes_used) +{ + uint32_t outs; + uint32_t nodes_add, best_nodes_used = 0; + uint8_t in_pos = 0, out_pos = 0; + uint32_t nodes_in_path, best_nodes_in_path = 0; + uint32_t best_distance = DISTANCE_INFINITY, distance; + + do { + outs = outputs; + in_pos = find_next_bit((unsigned long *)&inputs, 32, in_pos); + if (in_pos >= sizeof(uint32_t) * 8) + break; + nodes_add = 0; + set_bit(in_pos, (unsigned long *)&nodes_add); + + switch (in_pos) { + case PXP_2D_PS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) { + if (is_yuv(in->format)) + set_bit(PXP_2D_CSC1, + (unsigned long *)&nodes_add); + else + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + } + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_AS: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_INPUT_STORE0, (unsigned long *)&outs); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + if ((in->flags & IN_NEED_CSC) == IN_NEED_CSC) + set_bit(PXP_2D_CSC2, + (unsigned long *)&nodes_add); + clear_bit(PXP_2D_OUT, (unsigned long *)&outs); + if ((in->flags & IN_NEED_ROTATE_FLIP) == IN_NEED_ROTATE_FLIP) + set_bit(PXP_2D_ROTATION1, + (unsigned long *)&nodes_add); + break; + default: + /* alph0_s0/s1, alpha1_s0/s1 */ + break; + } + + nodes_add |= *nodes_used; + + do { + out_pos = find_next_bit((unsigned long *)&outs, 32, out_pos); + if (out_pos >= sizeof(uint32_t) * 8) + break; + set_bit(out_pos, (unsigned long *)&nodes_add); + + switch(out_pos) { + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S0: + case PXP_2D_ALPHA1_S1: + clear_bit(PXP_2D_CSC2, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_add); + clear_bit(PXP_2D_LUT, (unsigned long *)&nodes_add); + break; + default: + break; + } + + nodes_in_path = nodes_add; + distance = calc_shortest_path(&nodes_in_path); + if (best_distance > distance) { + best_distance = distance; + best_nodes_used = nodes_add; + best_nodes_in_path = nodes_in_path; + } + pr_debug("%s: out_pos = %d, nodes_in_path = 0x%x, nodes_add = 0x%x, distance = 0x%x\n", + __func__, out_pos, nodes_in_path, nodes_add, distance); + + clear_bit(out_pos, (unsigned long *)&nodes_add); + + out_pos++; + } while (1); + + in_pos++; + } while (1); + + *nodes_used = best_nodes_used; + + return best_nodes_in_path; +} + +static uint32_t ps_calc_scaling(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct ps_ctrl *ctrl) +{ + struct ps_scale scale; + uint32_t decx, decy; + + memset((void*)&scale, 0x0, sizeof(scale)); + + if (!output->crop.width || !output->crop.height) { + pr_err("Invalid drect width and height passed in\n"); + return 0; + } + + if ((input->rotate == 90) || (input->rotate == 270)) + swap(output->crop.width, output->crop.height); + + decx = input->crop.width / output->crop.width; + decy = input->crop.height / output->crop.height; + + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + ctrl->decx = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + ctrl->decx = 2; + } else if (decx >= 8) { + decx = 8; + ctrl->decx = 3; + } + scale.xscale = input->crop.width * 0x1000 / + (output->crop.width * decx); + + /* A factor greater than 2 is not supported + * with the bilinear filter, so correct it in + * driver + */ + if (((scale.xscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { + scale.xscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); + scale.xscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); + pr_warn("%s: scale.xscale is larger than 2, forcing to 2" + "input w/h=(%d,%d), output w/h=(%d, %d)\n", + __func__, input->crop.width, input->crop.height, + output->crop.width, output->crop.height); + } + } else { + if (!is_yuv(input->format) || + (is_yuv(input->format) == is_yuv(output->format)) || + (input->format == PXP_PIX_FMT_GREY) || + (input->format == PXP_PIX_FMT_GY04) || + (input->format == PXP_PIX_FMT_VUY444)) { + if ((input->crop.width > 1) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 1) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } else { + if ((input->crop.width > 2) && + (output->crop.width > 1)) + scale.xscale = (input->crop.width - 2) * 0x1000 / + (output->crop.width - 1); + else + scale.xscale = input->crop.width * 0x1000 / + output->crop.width; + } + } + + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ctrl->decy = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ctrl->decy = 2; + } else if (decy >= 8) { + decy = 8; + ctrl->decy = 3; + } + scale.yscale = input->crop.height * 0x1000 / + (output->crop.height * decy); + + /* A factor greater than 2 is not supported + * with the bilinear filter, so correct it in + * driver + */ + if (((scale.yscale >> BP_PXP_PS_SCALE_OFFSET) & 0x3) > 2) { + scale.yscale &= (~(0x3 << BP_PXP_PS_SCALE_OFFSET)); + scale.yscale |= (0x2 << BP_PXP_PS_SCALE_OFFSET); + pr_warn("%s: scale.yscale is larger than 2, forcing to 2" + "input w/h=(%d,%d), output w/h=(%d, %d)\n", + __func__, input->crop.width, input->crop.height, + output->crop.width, output->crop.height); + } + } else { + if ((input->crop.height > 1) && (output->crop.height > 1)) + scale.yscale = (input->crop.height - 1) * 0x1000 / + (output->crop.height - 1); + else + scale.yscale = input->crop.height * 0x1000 / + output->crop.height; + } + + return *(uint32_t *)&scale; +} + +static int pxp_ps_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset, U, V; + struct ps_ctrl ctrl; + struct coordinate out_ps_ulc, out_ps_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_ps_fmt(input->format); + + switch (output->rotate) { + case 0: + out_ps_ulc.x = output->crop.x; + out_ps_ulc.y = output->crop.y; + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 90: + out_ps_ulc.x = output->crop.y; + out_ps_ulc.y = output->width - (output->crop.x + output->crop.width); + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + case 180: + out_ps_ulc.x = output->width - (output->crop.x + output->crop.width); + out_ps_ulc.y = output->height - (output->crop.y + output->crop.height); + out_ps_lrc.x = out_ps_ulc.x + output->crop.width - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.height - 1; + break; + case 270: + out_ps_ulc.x = output->height - (output->crop.y + output->crop.height); + out_ps_ulc.y = output->crop.x; + out_ps_lrc.x = out_ps_ulc.x + output->crop.height - 1; + out_ps_lrc.y = out_ps_ulc.y + output->crop.width - 1; + break; + default: + pr_err("PxP only support rotate 0 90 180 270\n"); + return -EINVAL; + break; + } + + if ((input->format == PXP_PIX_FMT_YUYV) || + (input->format == PXP_PIX_FMT_YVYU)) + ctrl.wb_swap = 1; + + pxp_writel(ps_calc_scaling(input, output, &ctrl), + HW_PXP_PS_SCALE); + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_PS_CTRL); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + + pxp_writel(input->paddr + offset, HW_PXP_PS_BUF); + + switch (is_yuv(input->format)) { + case 0: /* RGB */ + case 1: /* 1 Plane YUV */ + break; + case 2: /* NV16,NV61,NV12,NV21 */ + if ((input->format == PXP_PIX_FMT_NV16) || + (input->format == PXP_PIX_FMT_NV61)) { + U = input->paddr + input->width * input->height; + pxp_writel(U + offset, HW_PXP_PS_UBUF); + } + else { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); + } + break; + case 3: /* YUV422P, YUV420P */ + if (input->format == PXP_PIX_FMT_YUV422P) { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 1), HW_PXP_PS_UBUF); + V = U + (input->width * input->height >> 1); + pxp_writel(V + (offset >> 1), HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YUV420P) { + U = input->paddr + input->width * input->height; + pxp_writel(U + (offset >> 2), HW_PXP_PS_UBUF); + V = U + (input->width * input->height >> 2); + pxp_writel(V + (offset >> 2), HW_PXP_PS_VBUF); + } else if (input->format == PXP_PIX_FMT_YVU420P) { + U = input->paddr + input->width * input->height; + V = U + (input->width * input->height >> 2); + pxp_writel(U + (offset >> 2), HW_PXP_PS_VBUF); + pxp_writel(V + (offset >> 2), HW_PXP_PS_UBUF); + } + + break; + default: + break; + } + + pxp_writel(input->pitch, HW_PXP_PS_PITCH); + pxp_writel(*(uint32_t *)&out_ps_ulc, HW_PXP_OUT_PS_ULC); + pxp_writel(*(uint32_t *)&out_ps_lrc, HW_PXP_OUT_PS_LRC); + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_as_config(struct pxp_pixmap *input, + struct pxp_pixmap *output) +{ + uint32_t offset; + struct as_ctrl ctrl; + struct coordinate out_as_ulc, out_as_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_as_fmt(input->format); + + if (alpha_blending_version == PXP_ALPHA_BLENDING_V1) { + if (input->format == PXP_PIX_FMT_BGRA32) { + if (!input->g_alpha.combine_enable) { + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs; + ctrl.rop = 0x3; + } + } + + if (input->g_alpha.global_alpha_enable) { + if (input->g_alpha.global_override) + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Override; + else + ctrl.alpha_ctrl = BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply; + + if (input->g_alpha.alpha_invert) + ctrl.alpha0_invert = 0x1; + } + + if (input->g_alpha.color_key_enable) { + ctrl.enable_colorkey = 1; + } + + ctrl.alpha = input->g_alpha.global_alpha; + } + + out_as_ulc.x = out_as_ulc.y = 0; + if (input->g_alpha.combine_enable) { + out_as_lrc.x = input->width - 1; + out_as_lrc.y = input->height - 1; + } else { + out_as_lrc.x = output->crop.width - 1; + out_as_lrc.y = output->crop.height - 1; + } + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + pxp_writel(input->paddr + offset, HW_PXP_AS_BUF); + + pxp_writel(input->pitch, HW_PXP_AS_PITCH); + pxp_writel(*(uint32_t *)&out_as_ulc, HW_PXP_OUT_AS_ULC); + pxp_writel(*(uint32_t *)&out_as_lrc, HW_PXP_OUT_AS_LRC); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_AS_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static uint32_t pxp_fetch_size_config(struct pxp_pixmap *input) +{ + struct fetch_size total_size; + + memset((void*)&total_size, 0x0, sizeof(total_size)); + + total_size.input_total_width = input->width - 1; + total_size.input_total_height = input->height - 1; + + return *(uint32_t *)&total_size; +} + +static int pxp_fetch_config(struct pxp_pixmap *input, + uint32_t fetch_index) +{ + uint8_t shift_bypass = 1, expand_en = 0; + uint32_t flags, pitch = 0, offset, UV = 0; + uint32_t in_fmt, out_fmt; + uint32_t size_ulc, size_lrc; + uint32_t fetch_ctrl, total_size; + uint32_t shift_ctrl, shift_offset = 0; + struct fetch_shift_width shift_width; + + memset((unsigned int *)&shift_width, 0x0, sizeof(shift_width)); + fetch_ctrl = pxp_fetch_ctrl_config(input, FETCH_MODE_NORMAL); + size_ulc = pxp_fetch_active_size_ulc(input); + size_lrc = pxp_fetch_active_size_lrc(input); + total_size = pxp_fetch_size_config(input); + + if (input->flags) { + flags = fmt_fetch_to_common(input->format); + shift_bypass = (flags & FETCH_SHIFT) ? 0 : 1; + expand_en = (flags & FETCH_EXPAND) ? 1 : 0; + + if (!shift_bypass) { + if (expand_en) { + if (is_yuv(input->format)) { + in_fmt = PXP_PIX_FMT_YVU444; + out_fmt = PXP_PIX_FMT_YUV444; + } else { + in_fmt = PXP_PIX_FMT_ABGR32; + out_fmt = PXP_PIX_FMT_ARGB32; + } + } else { + in_fmt = input->format; + out_fmt = is_yuv(input->format) ? + PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + } + + shift_offset = pxp_fetch_shift_calc(in_fmt, out_fmt, + &shift_width); + } + } + shift_ctrl = pxp_fetch_shift_ctrl_config(input, shift_bypass, expand_en); + + offset = input->crop.y * input->pitch + + input->crop.x * (input->bpp >> 3); + if (is_yuv(input->format) == 2) + UV = input->paddr + input->width * input->height; + + switch (fetch_index) { + case PXP_2D_INPUT_FETCH0: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(input, NULL); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH0); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH0); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0); + break; + case PXP_2D_INPUT_FETCH1: + pitch = __raw_readl(pxp_reg_base + HW_PXP_INPUT_FETCH_PITCH); + pitch |= pxp_fetch_pitch_config(NULL, input); + pxp_writel(fetch_ctrl, HW_PXP_INPUT_FETCH_CTRL_CH1); + pxp_writel(size_ulc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1); + pxp_writel(size_lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1); + pxp_writel(total_size, HW_PXP_INPUT_FETCH_SIZE_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + pxp_writel(input->paddr + offset, HW_PXP_INPUT_FETCH_ADDR_0_CH1); + if (UV) + pxp_writel(UV + offset, HW_PXP_INPUT_FETCH_ADDR_1_CH1); + pxp_writel(shift_ctrl, HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1); + if (shift_offset) + pxp_writel(*(uint32_t *)&shift_offset, HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1); + pxp_writel(*(uint32_t *)&shift_width, HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1); + break; + default: + break; + } + + pxp_writel(pitch, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc1_config(struct pxp_pixmap *input, + bool is_ycbcr) +{ + BUG_ON(!is_yuv(input->format)); + + if (!is_ycbcr) { + /* YUV -> RGB */ + pxp_writel(0x04030000, HW_PXP_CSC1_COEF0); + pxp_writel(0x01230208, HW_PXP_CSC1_COEF1); + pxp_writel(0x076b079c, HW_PXP_CSC1_COEF2); + + return 0; + } + + /* YCbCr -> RGB */ + pxp_writel(0x84ab01f0, HW_PXP_CSC1_COEF0); + pxp_writel(0x01980204, HW_PXP_CSC1_COEF1); + pxp_writel(0x0730079c, HW_PXP_CSC1_COEF2); + + return 0; +} + +static int pxp_rotation1_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP1(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP1(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE1(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE1(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_rotation0_config(struct pxp_pixmap *input) +{ + uint8_t rotate; + + if (input->flip == PXP_H_FLIP) + pxp_writel(BF_PXP_CTRL_HFLIP0(1), HW_PXP_CTRL_SET); + else if (input->flip == PXP_V_FLIP) + pxp_writel(BF_PXP_CTRL_VFLIP0(1), HW_PXP_CTRL_SET); + + rotate = rotate_map(input->rotate); + pxp_writel(BF_PXP_CTRL_ROTATE0(rotate), HW_PXP_CTRL_SET); + + pxp_writel(BF_PXP_CTRL_ENABLE_ROTATE0(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_csc2_config(struct pxp_pixmap *output) +{ + if (is_yuv(output->format)) { + /* RGB -> YUV */ + pxp_writel(0x4, HW_PXP_CSC2_CTRL); + pxp_writel(0x0096004D, HW_PXP_CSC2_COEF0); + pxp_writel(0x05DA001D, HW_PXP_CSC2_COEF1); + pxp_writel(0x007005B6, HW_PXP_CSC2_COEF2); + pxp_writel(0x057C009E, HW_PXP_CSC2_COEF3); + pxp_writel(0x000005E6, HW_PXP_CSC2_COEF4); + pxp_writel(0x00000000, HW_PXP_CSC2_COEF5); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_CSC2(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_out_config(struct pxp_pixmap *output) +{ + uint32_t offset, UV; + struct out_ctrl ctrl; + struct coordinate out_lrc; + + memset((void*)&ctrl, 0x0, sizeof(ctrl)); + + ctrl.format = pxp_parse_out_fmt(output->format); + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + + pxp_writel(*(uint32_t *)&ctrl, HW_PXP_OUT_CTRL); + + pxp_writel(output->paddr, HW_PXP_OUT_BUF); + if (is_yuv(output->format) == 2) { + UV = output->paddr + output->width * output->height; + if ((output->format == PXP_PIX_FMT_NV16) || + (output->format == PXP_PIX_FMT_NV61)) + pxp_writel(UV + offset, HW_PXP_OUT_BUF2); + else + pxp_writel(UV + (offset >> 1), HW_PXP_OUT_BUF2); + } + + if (output->rotate == 90 || output->rotate == 270) { + out_lrc.y = output->width - 1; + out_lrc.x = output->height - 1; + } else { + out_lrc.x = output->width - 1; + out_lrc.y = output->height - 1; + } + + pxp_writel(*(uint32_t *)&out_lrc, HW_PXP_OUT_LRC); + + pxp_writel(output->pitch, HW_PXP_OUT_PITCH); + + /* set global alpha if necessary */ + if (output->g_alpha.global_alpha_enable) { + pxp_writel(output->g_alpha.global_alpha << 24, HW_PXP_OUT_CTRL_SET); + pxp_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT, HW_PXP_OUT_CTRL_SET); + } + + pxp_writel(BF_PXP_CTRL_ENABLE_PS_AS_OUT(1) | + BF_PXP_CTRL_IRQ_ENABLE(1), + HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_store_config(struct pxp_pixmap *output, + struct pxp_op_info *op) +{ + uint8_t combine_2ch, flags; + uint32_t in_fmt, out_fmt, offset, UV = 0; + uint64_t d_shift = 0; + struct store_d_mask d_mask[8]; + uint32_t store_ctrl, store_size, store_pitch, shift_ctrl; + + memset((void*)d_mask, 0x0, sizeof(*d_mask) * 8); + combine_2ch = (output->bpp == 64) ? 1 : 0; + store_ctrl = pxp_store_ctrl_config(output, STORE_MODE_NORMAL, + op->fill_en, combine_2ch); + store_size = pxp_store_size_config(output); + store_pitch = pxp_store_pitch_config(output, NULL); + + pxp_writel(store_ctrl, HW_PXP_INPUT_STORE_CTRL_CH0); + + if (output->flags) { + flags = fmt_store_from_common(output->format); + if (flags == STORE_NOOP) + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + else if (flags & STORE_SHIFT) { + in_fmt = is_yuv(output->format) ? PXP_PIX_FMT_YUV444 : + PXP_PIX_FMT_ARGB32; + out_fmt = (flags & STORE_SHRINK) ? PXP_PIX_FMT_YVU444 : + output->format; + d_shift = pxp_store_d_shift_calc(in_fmt, out_fmt, d_mask); + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 0); + + if (flags & STORE_SHIFT) { + pxp_writel((uint32_t)d_shift, HW_PXP_INPUT_STORE_D_SHIFT_L_CH0); + /* TODO use only 4 masks */ + pxp_writel(d_mask[0].d_mask_l, HW_PXP_INPUT_STORE_D_MASK0_L_CH0); + pxp_writel(d_mask[0].d_mask_h, HW_PXP_INPUT_STORE_D_MASK0_H_CH0); + pxp_writel(d_mask[1].d_mask_l, HW_PXP_INPUT_STORE_D_MASK1_L_CH0); + pxp_writel(d_mask[1].d_mask_h, HW_PXP_INPUT_STORE_D_MASK1_H_CH0); + pxp_writel(d_mask[2].d_mask_l, HW_PXP_INPUT_STORE_D_MASK2_L_CH0); + pxp_writel(d_mask[2].d_mask_h, HW_PXP_INPUT_STORE_D_MASK2_H_CH0); + pxp_writel(d_mask[3].d_mask_l, HW_PXP_INPUT_STORE_D_MASK3_L_CH0); + pxp_writel(d_mask[3].d_mask_h, HW_PXP_INPUT_STORE_D_MASK3_H_CH0); + } + } else + shift_ctrl = pxp_store_shift_ctrl_config(output, 1); + + pxp_writel(shift_ctrl, HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0); + pxp_writel(store_size, HW_PXP_INPUT_STORE_SIZE_CH0); + pxp_writel(store_pitch, HW_PXP_INPUT_STORE_PITCH); + if (op->fill_en) { + uint32_t lrc; + + lrc = (output->width - 1) | ((output->height - 1) << 16); + pxp_writel(op->fill_data, HW_PXP_INPUT_STORE_FILL_DATA_CH0); + + pxp_writel(0x1, HW_PXP_INPUT_FETCH_CTRL_CH0); + pxp_writel(0, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0); + pxp_writel(lrc, HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0); + } + + offset = output->crop.y * output->pitch + + output->crop.x * (output->bpp >> 3); + if (is_yuv(output->format == 2)) { + UV = output->paddr + output->width * output->height; + pxp_writel(UV + offset, HW_PXP_INPUT_STORE_ADDR_1_CH0); + } + pxp_writel(output->paddr + offset, HW_PXP_INPUT_STORE_ADDR_0_CH0); + + pxp_writel(BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(1), HW_PXP_CTRL_SET); + + return 0; +} + +static int pxp_alpha_config(struct pxp_op_info *op, + uint8_t alpha_node) +{ + uint32_t as_ctrl; + struct pxp_alpha_ctrl alpha_ctrl; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_alpha *s0_alpha, *s1_alpha; + + memset((void*)&alpha_ctrl, 0x0, sizeof(alpha_ctrl)); + + if (alpha_blending_version != PXP_ALPHA_BLENDING_V1) { + if (alpha->alpha_mode == ALPHA_MODE_ROP) { + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + as_ctrl = __raw_readl(pxp_reg_base + HW_PXP_AS_CTRL); + as_ctrl |= BF_PXP_AS_CTRL_ALPHA_CTRL(BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs); + as_ctrl |= BF_PXP_AS_CTRL_ROP(alpha->rop_type); + pxp_writel(as_ctrl, HW_PXP_AS_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE | + BF_PXP_ALPHA_B_CTRL_1_ROP(alpha->rop_type), + HW_PXP_ALPHA_B_CTRL_1); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + + return 0; + } + + s0_alpha = &alpha->s0_alpha; + s1_alpha = &alpha->s1_alpha; + + alpha_ctrl.poter_duff_enable = 1; + + alpha_ctrl.s0_s1_factor_mode = s1_alpha->factor_mode; + alpha_ctrl.s0_global_alpha_mode = s0_alpha->global_alpha_mode; + alpha_ctrl.s0_alpha_mode = s0_alpha->alpha_mode; + alpha_ctrl.s0_color_mode = s0_alpha->color_mode; + + alpha_ctrl.s1_s0_factor_mode = s0_alpha->factor_mode; + alpha_ctrl.s1_global_alpha_mode = s1_alpha->global_alpha_mode; + alpha_ctrl.s1_alpha_mode = s1_alpha->alpha_mode; + alpha_ctrl.s1_color_mode = s1_alpha->color_mode; + + alpha_ctrl.s0_global_alpha = s0_alpha->global_alpha_value; + alpha_ctrl.s1_global_alpha = s1_alpha->global_alpha_value; + + switch (alpha_node) { + case PXP_2D_ALPHA0_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_A_CTRL); + break; + case PXP_2D_ALPHA1_S0: + pxp_writel(*(uint32_t *)&alpha_ctrl, HW_PXP_ALPHA_B_CTRL); + pxp_writel(BF_PXP_CTRL_ENABLE_ALPHA_B(1), HW_PXP_CTRL_SET); + break; + default: + break; + } + } + + return 0; +} + +static void pxp_lut_config(struct pxp_op_info *op) +{ + struct pxp_task_info *task = to_pxp_task_info(op); + struct pxps *pxp = to_pxp_from_task(task); + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + int lut_op = proc_data->lut_transform; + u32 reg_val; + int i; + bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false; + u8 *cmap = proc_data->lut_map; + u32 entry_src; + u32 pix_val; + u8 entry[4]; + + /* + * If LUT already configured as needed, return... + * Unless CMAP is needed and it has been updated. + */ + if ((pxp->lut_state == lut_op) && + !(use_cmap && proc_data->lut_map_updated)) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0xFF : 0x00; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_INVERT) != 0) { + /* Fill out LUT table with 8-bit inverted values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = ~entry_src & 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) { + entry_src = use_cmap ? + cmap[pix_val + i] : pix_val + i; + entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF; + } + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } else if (use_cmap) { + /* Fill out LUT table using colormap values */ + + /* clear bypass bit, set lookup mode & out mode */ + __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE + (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) | + BF_PXP_LUT_CTRL_OUT_MODE + (BV_PXP_LUT_CTRL_OUT_MODE__Y8), + pxp->base + HW_PXP_LUT_CTRL); + + /* Initialize LUT address to 0 and set NUM_BYTES to 0 */ + __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR); + + /* LUT address pointer auto-increments after each data write */ + for (pix_val = 0; pix_val < 256; pix_val += 4) { + for (i = 0; i < 4; i++) + entry[i] = cmap[pix_val + i]; + reg_val = (entry[3] << 24) | (entry[2] << 16) | + (entry[1] << 8) | entry[0]; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA); + } + } + + pxp_writel(BM_PXP_CTRL_ENABLE_ROTATE1 | BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_CSC2 | BM_PXP_CTRL_ENABLE_LUT, + HW_PXP_CTRL_SET); + + pxp->lut_state = lut_op; +} + +static int pxp_2d_task_config(struct pxp_pixmap *input, + struct pxp_pixmap *output, + struct pxp_op_info *op, + uint32_t nodes_used) +{ + uint8_t position = 0; + + + do { + position = find_next_bit((unsigned long *)&nodes_used, 32, position); + if (position >= sizeof(uint32_t) * 8) + break; + + switch (position) { + case PXP_2D_PS: + pxp_ps_config(input, output); + break; + case PXP_2D_AS: + pxp_as_config(input, output); + break; + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + pxp_fetch_config(input, position); + break; + case PXP_2D_CSC1: + pxp_csc1_config(input, true); + break; + case PXP_2D_ROTATION1: + pxp_rotation1_config(input); + break; + case PXP_2D_ALPHA0_S0: + case PXP_2D_ALPHA1_S0: + pxp_alpha_config(op, position); + break; + case PXP_2D_ALPHA0_S1: + case PXP_2D_ALPHA1_S1: + break; + case PXP_2D_CSC2: + pxp_csc2_config(output); + break; + case PXP_2D_LUT: + pxp_lut_config(op); + break; + case PXP_2D_ROTATION0: + pxp_rotation0_config(input); + break; + case PXP_2D_OUT: + pxp_out_config(output); + break; + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + pxp_store_config(output, op); + break; + default: + break; + } + + position++; + } while (1); + + return 0; +} + +static void mux_config_helper(struct mux_config *path_ctrl, + struct edge_node *enode) +{ + uint32_t mux_val, mux_pos = 0; + + if (enode->mux_used) { + do { + mux_pos = find_next_bit((unsigned long *)&enode->mux_used, + 32, mux_pos); + if (mux_pos >= 16) + break; + + mux_val = get_mux_val(&enode->muxes, mux_pos); + pr_debug("%s: mux_pos = %d, mux_val = %d\n", + __func__, mux_pos, mux_val); + set_mux_val(path_ctrl, mux_pos, mux_val); + + mux_pos++; + } while (1); + } +} + +static void pxp_2d_calc_mux(uint32_t nodes, struct mux_config *path_ctrl) +{ + struct edge_node *enode; + uint8_t from = 0, to = 0; + + do { + from = find_next_bit((unsigned long *)&nodes, 32, from); + if (from >= sizeof(uint32_t) * 8) + break; + + if (to != 0) { + enode = adj_list[to].first; + while (enode) { + if (enode->adjvex == from) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + } + + to = find_next_bit((unsigned long *)&nodes, 32, from + 1); + if (to >= sizeof(uint32_t) * 8) + break; + + enode = adj_list[from].first; + while (enode) { + if (enode->adjvex == to) { + mux_config_helper(path_ctrl, enode); + break; + } + enode = enode->next; + } + + from = to + 1; + } while (1); +} + +static int pxp_2d_op_handler(struct pxps *pxp) +{ + struct mux_config path_ctrl0; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_pixmap *input, *output, *input_s0, *input_s1; + uint32_t possible_inputs, possible_outputs; + uint32_t possible_inputs_s0, possible_inputs_s1; + uint32_t inputs_filter_s0, inputs_filter_s1; + uint32_t nodes_used = 0, nodes_in_path; + uint32_t partial_nodes_used = 0; + uint32_t nodes_used_s0 = 0, nodes_used_s1 = 0; + uint32_t nodes_in_path_s0, nodes_in_path_s1; + uint32_t val; + + output = &task->output[0]; + if (!output->pitch) + return -EINVAL; + + *(unsigned int*)&path_ctrl0 = 0xffffffff; + +reparse: + switch (task->input_num) { + case 0: + /* Fill operation: use input store engine */ + if (is_yuv(output->format) > 1) + return -EINVAL; + + if (output->bpp > 32) + return -EINVAL; + + nodes_used = 1 << PXP_2D_INPUT_STORE0; + pxp_2d_task_config(NULL, output, op, nodes_used); + break; + case 1: + /* No Composite */ + possible_inputs = (1 << PXP_2D_PS) | + (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + input = &task->input[0]; + if (!input->pitch) + return -EINVAL; + + if (input->rotate || input->flip) { + input->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input->rotate; + output->flip = input->flip; + } + + if (!is_yuv(input->format) != !is_yuv(output->format)) + input->flags |= IN_NEED_CSC; + else if (input->format != output->format) + input->flags |= IN_NEED_FMT_UNIFIED; + + if ((input->rotate == 90) || (input->rotate == 270)) { + if ((input->crop.width != output->crop.height) || + (input->crop.height != output->crop.width)) + input->flags |= IN_NEED_SCALE; + } else { + if ((input->crop.width != output->crop.width) || + (input->crop.height != output->crop.height)) + input->flags |= IN_NEED_SCALE; + } + + if (input->flags) { + /* only ps has scaling function */ + if ((input->flags & IN_NEED_SCALE) == IN_NEED_SCALE) + possible_inputs = 1 << PXP_2D_PS; + output->flags |= (output->bpp < 32) ? OUT_NEED_SHRINK : + OUT_NEED_SHIFT; + } + + filter_possible_inputs(input, &possible_inputs); + filter_possible_outputs(output, &possible_outputs); + + if (!possible_inputs || !possible_outputs) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + if (proc_data->lut_transform) + nodes_used |= (1 << PXP_2D_LUT); + + nodes_in_path = find_best_path(possible_inputs, + possible_outputs, + input, &nodes_used); + + if (nodes_in_path & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path); + } + + if (nodes_used & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used); + } + + pr_debug("%s: nodes_in_path = 0x%x, nodes_used = 0x%x\n", + __func__, nodes_in_path, nodes_used); + if (!nodes_used) { + dev_err(&pxp->pdev->dev, "unsupport 2d operation\n"); + return -EINVAL; + } + + /* If use input fetch0, should use + * alpha b instead of alpha a */ + if (nodes_in_path & (1 << PXP_2D_ALPHA0_S0)) { + if (nodes_in_path & (1 << PXP_2D_INPUT_FETCH0)) { + clear_bit(PXP_2D_ALPHA0_S0, + (unsigned long *)&nodes_in_path); + set_bit(PXP_2D_ALPHA1_S1, + (unsigned long *)&nodes_in_path); + } + } + + /* In this case input read in + * by input fetch engine + */ + if ((nodes_in_path & (1 << PXP_2D_ALPHA1_S1)) || + (nodes_in_path & (1 << PXP_2D_ALPHA1_S0))) { + memcpy(&task->input[1], input, sizeof(*input)); + if (input->rotate == 90 || input->rotate == 270) { + uint32_t temp; + + input = &task->input[1]; + input->rotate = 0; + input->flags = 0; + temp = input->width; + input->width = input->height; + input->height = temp; + input->pitch = input->width * (input->bpp >> 3); + temp = input->crop.width; + input->crop.width = input->crop.height; + input->crop.height = temp; + } + + op->alpha_info.alpha_mode = ALPHA_MODE_ROP; + /* s0 AND s1 */ + op->alpha_info.rop_type = 0x0; + task->input_num = 2; + goto reparse; + } + + pxp_2d_calc_mux(nodes_in_path, &path_ctrl0); + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_2d_task_config(input, output, op, nodes_used); + + if (is_yuv(input->format) && is_yuv(output->format)) { + val = readl(pxp_reg_base + HW_PXP_CSC1_COEF0); + val |= (BF_PXP_CSC1_COEF0_YCBCR_MODE(1) | + BF_PXP_CSC1_COEF0_BYPASS(1)); + pxp_writel(val, HW_PXP_CSC1_COEF0); + } + break; + case 2: + /* Composite */ + input_s0 = &task->input[0]; + input_s1 = &task->input[1]; + if (!input_s0->pitch || !input_s1->pitch) + return -EINVAL; + + possible_inputs_s0 = (1 << PXP_2D_PS) | + (1 << PXP_2D_INPUT_FETCH0) | + (1 << PXP_2D_INPUT_FETCH1); + possible_inputs_s1 = (1 << PXP_2D_AS) | + (1 << PXP_2D_INPUT_FETCH0); + possible_outputs = (1 << PXP_2D_OUT) | + (1 << PXP_2D_INPUT_STORE0); + + if (input_s0->rotate || input_s0->flip) { + input_s0->flags |= IN_NEED_ROTATE_FLIP; + output->rotate = input_s0->rotate; + output->flip = input_s0->flip; + } + if (input_s1->rotate || input_s1->flip) { + input_s1->flags |= IN_NEED_ROTATE_FLIP; + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + } + + if (is_yuv(input_s0->format) && is_yuv(input_s1->format)) + return -EINVAL; + + if (is_yuv(input_s0->format)){ + /* need do yuv -> rgb conversion by csc1 */ + possible_inputs_s0 = 1 << PXP_2D_PS; + input_s0->flags |= IN_NEED_CSC; + } else if (is_yuv(input_s1->format)) { + possible_inputs_s1 = 1 << PXP_2D_PS; + input_s1->flags |= IN_NEED_CSC; + } + + filter_possible_inputs(input_s0, &possible_inputs_s0); + filter_possible_inputs(input_s1, &possible_inputs_s1); + + if (!possible_inputs_s0 || !possible_inputs_s0) + return -EINVAL; + + filter_possible_outputs(output, &possible_outputs); + if (!possible_outputs) + return -EINVAL; + + pr_debug("%s: poss_s0 = 0x%x, poss_s1 = 0x%x, poss_out = 0x%x\n", + __func__, possible_inputs_s0, possible_inputs_s1, possible_outputs); + + inputs_filter_s0 = possible_inputs_s0; + inputs_filter_s1 = possible_inputs_s1; + + /* Using alpha0, possible cases: + * 1. PS --> S0, AS --> S1; + */ + if (possible_inputs_s1 & (1 << PXP_2D_AS)) { + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH1, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + goto alpha1; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA0_S0, + input_s0, + &partial_nodes_used); + if (!nodes_in_path_s0) + goto alpha1; + + nodes_used_s0 |= partial_nodes_used; + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA0_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + if (!(nodes_in_path_s0 & possible_outputs)) + goto alpha1; + nodes_used_s0 |= partial_nodes_used; + + possible_inputs_s1 = (1 << PXP_2D_AS); + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA0_S1, + input_s1, + &nodes_used_s1); + if (!nodes_in_path_s1) + goto alpha1; + + goto config; + } +alpha1: + partial_nodes_used = 0; + possible_inputs_s0 = inputs_filter_s0; + possible_inputs_s1 = inputs_filter_s1; + + /* Using alpha1, possible cases: + * 1. FETCH1 --> S0, FETCH0 --> S1; + */ + clear_bit(PXP_2D_PS, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_INPUT_FETCH0, + (unsigned long *)&possible_inputs_s0); + clear_bit(PXP_2D_OUT, + (unsigned long *)&possible_outputs); + + if (!possible_inputs_s0 || !possible_outputs) + return -EINVAL; + + nodes_in_path_s0 = find_best_path(possible_inputs_s0, + 1 << PXP_2D_ALPHA1_S0, + input_s0, + &partial_nodes_used); + pr_debug("%s: nodes_in_path_s0 = 0x%x\n", __func__, nodes_in_path_s0); + BUG_ON(!nodes_in_path_s0); + + nodes_used_s0 |= partial_nodes_used; + if ((nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH0)) || + (nodes_used_s0 & (1 << PXP_2D_INPUT_FETCH1))) + clear_bit(PXP_2D_OUT, (unsigned long *)&possible_outputs); + else + clear_bit(PXP_2D_INPUT_STORE0, + (unsigned long *)&possible_outputs); + partial_nodes_used = 0; + + if (is_yuv(output->format)) + set_bit(PXP_2D_CSC2, + (unsigned long *)&partial_nodes_used); + if (output->rotate || output->flip) + set_bit(PXP_2D_ROTATION0, + (unsigned long *)&partial_nodes_used); + + nodes_in_path_s0 |= find_best_path(1 << PXP_2D_ALPHA1_S0, + possible_outputs, + input_s0, + &partial_nodes_used); + BUG_ON(!(nodes_in_path_s0 & possible_outputs)); + nodes_used_s0 |= partial_nodes_used; + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x\n", + __func__, nodes_in_path_s0, nodes_used_s0); + + clear_bit(PXP_2D_AS, + (unsigned long *)&possible_inputs_s1); + BUG_ON(!possible_inputs_s1); + + nodes_in_path_s1 = find_best_path(possible_inputs_s1, + 1 << PXP_2D_ALPHA1_S1, + input_s1, + &nodes_used_s1); + pr_debug("%s: poss_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, possible_inputs_s1, nodes_used_s1); + BUG_ON(!nodes_in_path_s1); + /* To workaround an IC bug */ + path_ctrl0.mux4_sel = 0x0; +config: + if (nodes_in_path_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_in_path_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_in_path_s0); + } + + pr_debug("%s: nodes_in_path_s0 = 0x%x, nodes_used_s0 = 0x%x, nodes_in_path_s1 = 0x%x, nodes_used_s1 = 0x%x\n", + __func__, nodes_in_path_s0, nodes_used_s0, nodes_in_path_s1, nodes_used_s1); + pxp_2d_calc_mux(nodes_in_path_s0, &path_ctrl0); + pxp_2d_calc_mux(nodes_in_path_s1, &path_ctrl0); + + pr_debug("%s: s0 paddr = 0x%x, s1 paddr = 0x%x, out paddr = 0x%x\n", + __func__, input_s0->paddr, input_s1->paddr, output->paddr); + + if (nodes_used_s0 & (1 << PXP_2D_ROTATION1)) { + clear_bit(PXP_2D_ROTATION1, (unsigned long *)&nodes_used_s0); + set_bit(PXP_2D_ROTATION0, (unsigned long *)&nodes_used_s0); + } + + pxp_2d_task_config(input_s0, output, op, nodes_used_s0); + pxp_2d_task_config(input_s1, output, op, nodes_used_s1); + break; + default: + break; + } + + __raw_writel(proc_data->bgcolor, + pxp->base + HW_PXP_PS_BACKGROUND_0); + pxp_set_colorkey(pxp); + + if (proc_data->lut_transform && pxp_is_v3(pxp)) + set_mux(&path_ctrl0); + + pr_debug("%s: path_ctrl0 = 0x%x\n", + __func__, *(uint32_t *)&path_ctrl0); + pxp_writel(*(uint32_t *)&path_ctrl0, HW_PXP_DATA_PATH_CTRL0); + + return 0; +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + int ret = 0; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf_data->proc_data; + + switch (op->op_type) { + case PXP_OP_TYPE_2D: + pxp_writel(0xffffffff, HW_PXP_OUT_AS_ULC); + pxp_writel(0x0, HW_PXP_OUT_AS_LRC); + pxp_writel(0xffffffff, HW_PXP_OUT_PS_ULC); + pxp_writel(0x0, HW_PXP_OUT_PS_LRC); + pxp_writel(0x0, HW_PXP_INPUT_FETCH_PITCH); + pxp_writel(0x40000000, HW_PXP_CSC1_COEF0); + ret = pxp_2d_op_handler(pxp); + break; + case PXP_OP_TYPE_DITHER: + pxp_dithering_process(pxp); + if (pxp_is_v3p(pxp)) { + __raw_writel( + BM_PXP_CTRL_ENABLE | + BM_PXP_CTRL_ENABLE_DITHER | + BM_PXP_CTRL_ENABLE_CSC2 | + BM_PXP_CTRL_ENABLE_LUT | + BM_PXP_CTRL_ENABLE_ROTATE0 | + BM_PXP_CTRL_ENABLE_PS_AS_OUT, + pxp->base + HW_PXP_CTRL_SET); + return 0; + } + break; + case PXP_OP_TYPE_WFE_A: + pxp_luts_deactivate(pxp, proc_data->lut_sels); + + if (proc_data->lut_cleanup == 0) { + /* We should enable histogram in standard mode + * in wfe_a processing for waveform mode selection + */ + pxp_histogram_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + + pxp_luts_activate(pxp, (u64)proc_data->lut_status_1 | + ((u64)proc_data->lut_status_2 << 32)); + + /* collision detection should be always enable in standard mode */ + pxp_collision_detection_enable(pxp, pxp_conf_data->wfe_a_fetch_param[0].width, + pxp_conf_data->wfe_a_fetch_param[0].height); + } + + if (pxp->devdata && pxp->devdata->pxp_wfe_a_configure) + pxp->devdata->pxp_wfe_a_configure(pxp); + if (pxp->devdata && pxp->devdata->pxp_wfe_a_process) + pxp->devdata->pxp_wfe_a_process(pxp); + break; + case PXP_OP_TYPE_WFE_B: + pxp_wfe_b_configure(pxp); + pxp_wfe_b_process(pxp); + break; + default: + /* Unsupport */ + ret = -EINVAL; + pr_err("Invalid pxp operation type passed\n"); + break; + } + + return ret; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + pm_runtime_get_sync(pxp->dev); + + clk_prepare_enable(pxp->ipg_clk); + clk_prepare_enable(pxp->axi_clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + unsigned long flags; + + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) { + spin_unlock_irqrestore(&pxp->lock, flags); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pxp->clk_stat = CLK_STAT_OFF; + } else + spin_unlock_irqrestore(&pxp->lock, flags); + + pm_runtime_put_sync_suspend(pxp->dev); + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(struct timer_list *t) +{ + struct pxps *pxp = from_timer(pxp, t, clk_timer); + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +static int convert_param_to_pixmap(struct pxp_pixmap *pixmap, + struct pxp_layer_param *param) +{ + if (!param->width || !param->height) + return -EINVAL; + + pixmap->width = param->width; + pixmap->height = param->height; + pixmap->format = param->pixel_fmt; + pixmap->paddr = param->paddr; + pixmap->bpp = get_bpp_from_fmt(pixmap->format); + + if (pxp_legacy) { + pixmap->pitch = (param->stride) ? (param->stride * pixmap->bpp >> 3) : + (param->width * pixmap->bpp >> 3); + } else { + if (!param->stride || (param->stride == param->width)) + pixmap->pitch = param->width * pixmap->bpp >> 3; + else + pixmap->pitch = param->stride; + } + + pixmap->crop.x = param->crop.left; + pixmap->crop.y = param->crop.top; + pixmap->crop.width = param->crop.width; + pixmap->crop.height = param->crop.height; + + pixmap->g_alpha.color_key_enable = param->color_key_enable; + pixmap->g_alpha.combine_enable = param->combine_enable; + pixmap->g_alpha.global_alpha_enable = param->global_alpha_enable; + pixmap->g_alpha.global_override = param->global_override; + pixmap->g_alpha.global_alpha = param->global_alpha; + pixmap->g_alpha.alpha_invert = param->alpha_invert; + pixmap->g_alpha.local_alpha_enable = param->local_alpha_enable; + pixmap->g_alpha.comp_mask = param->comp_mask; + + return 0; +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + struct pxp_task_info *task = &pxp->task; + struct pxp_op_info *op = &task->op_info; + struct pxp_alpha_info *alpha = &op->alpha_info; + struct pxp_layer_param *param = NULL; + struct pxp_pixmap *input, *output; + int i = 0, ret; + bool combine_enable = false; + int delta_x, delta_y; + + memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param)); + memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param)); + memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data)); + + memset(task, 0, sizeof(*task)); + /* S0 */ + desc = list_first_entry(&head, struct pxp_tx_desc, list); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + if (proc_data->combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V2; + else + alpha_blending_version = PXP_ALPHA_BLENDING_NONE; + + pxp_legacy = (proc_data->pxp_legacy) ? true : false; + + param = &pxp->pxp_conf_state.s0_param; + if (param->pixel_fmt == PXP_PIX_FMT_YUV420P || + param->pixel_fmt == PXP_PIX_FMT_YVU420P) { + delta_x = proc_data->srect.left - ALIGN_DOWN(proc_data->srect.left, 2); + delta_y = proc_data->srect.top - ALIGN_DOWN(proc_data->srect.top, 2); + + proc_data->srect.left = ALIGN_DOWN(proc_data->srect.left, 2); + proc_data->srect.top = ALIGN_DOWN(proc_data->srect.top, 2); + + proc_data->srect.width = proc_data->srect.width + delta_x; + proc_data->srect.height = proc_data->srect.height + delta_y; + } + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + if (pxp->pxp_conf_state.ol_param[i - 1].width != 0 && + pxp->pxp_conf_state.ol_param[i - 1].height != 0) { + if (pxp->pxp_conf_state.ol_param[i - 1].combine_enable) + alpha_blending_version = PXP_ALPHA_BLENDING_V1; + } + } + + if (proc_data->engine_enable & PXP_ENABLE_DITHER) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH0) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_FETCH1) + memcpy(&pxp->pxp_conf_state.dither_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE0) + memcpy(&pxp->pxp_conf_state.dither_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_DITHER_STORE1) + memcpy(&pxp->pxp_conf_state.dither_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_DITHER; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_A) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_a_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_A_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_a_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_A; + } + + if (proc_data->engine_enable & PXP_ENABLE_WFE_B) { + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH0) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_FETCH1) + memcpy(&pxp->pxp_conf_state.wfe_b_fetch_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE0) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[0], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + if (child->layer_param.processing_param.flag & PXP_BUF_FLAG_WFE_B_STORE1) + memcpy(&pxp->pxp_conf_state.wfe_b_store_param[1], + &child->layer_param.processing_param, + sizeof(struct pxp_layer_param)); + op->op_type = PXP_OP_TYPE_WFE_B; + } + + i++; + } + + if (!op->op_type) { + op->op_type = PXP_OP_TYPE_2D; + + if ((alpha_blending_version == PXP_ALPHA_BLENDING_V1) || + (alpha_blending_version == PXP_ALPHA_BLENDING_V2)) + combine_enable = true; + + if (combine_enable) + task->input_num = 2; + else if (proc_data->fill_en) + task->input_num = 0; + else + task->input_num = 1; + + output = &task->output[0]; + switch (task->input_num) { + case 0: + op->fill_en = 1; + op->fill_data = proc_data->bgcolor; + break; + case 1: + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + if (ret < 0) { + param = &pxp->pxp_conf_state.ol_param[0]; + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + } else { + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + } + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + break; + case 2: + /* s0 */ + param = &pxp->pxp_conf_state.s0_param; + input = &task->input[0]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + input->crop.x = proc_data->srect.left; + input->crop.y = proc_data->srect.top; + input->crop.width = proc_data->srect.width; + input->crop.height = proc_data->srect.height; + alpha->s0_alpha = param->alpha; + + input->rotate = proc_data->rotate; + input->flip = (proc_data->hflip) ? PXP_H_FLIP : + (proc_data->vflip) ? PXP_V_FLIP : 0; + + /* overlay */ + param = &pxp->pxp_conf_state.ol_param[0]; + input = &task->input[1]; + + ret = convert_param_to_pixmap(input, param); + BUG_ON(ret < 0); + alpha->s1_alpha = param->alpha; + alpha->alpha_mode = proc_data->alpha_mode; + break; + } + + param = &pxp->pxp_conf_state.out_param; + ret = convert_param_to_pixmap(output, param); + BUG_ON(ret < 0); + + output->crop.x = proc_data->drect.left; + output->crop.y = proc_data->drect.top; + output->crop.width = proc_data->drect.width; + output->crop.height = proc_data->drect.height; + } + + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d S0 crop (top, left)=(%d, %d), (width, height)=(%d, %d)\n", + __func__, __LINE__, + pxp->pxp_conf_state.s0_param.crop.top, + pxp->pxp_conf_state.s0_param.crop.left, + pxp->pxp_conf_state.s0_param.crop.width, + pxp->pxp_conf_state.s0_param.crop.height); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static int pxpdma_dostart_work(struct pxps *pxp) +{ + int ret; + struct pxp_channel *pxp_chan = NULL; + unsigned long flags; + dma_async_tx_callback callback; + void *callback_param; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *child, *_child; + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + + spin_lock_irqsave(&pxp->lock, flags); + + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + __pxpdma_dostart(pxp_chan); + + /* Configure PxP */ + ret = pxp_config(pxp, pxp_chan); + if (ret) { + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + callback(callback_param); + + /* Unsupport operation */ + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + spin_unlock_irqrestore(&pxp->lock, flags); + return -EINVAL; + } + + if (proc_data->working_mode & PXP_MODE_STANDARD) { + if(!pxp_is_v3p(pxp) || !(proc_data->engine_enable & PXP_ENABLE_DITHER)) + pxp_start2(pxp); + } else + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return 0; +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp) +{ + unsigned long flags; + struct pxp_tx_desc *desc = NULL; + + do { + desc = pxpdma_first_queued(pxp_chan); + spin_lock_irqsave(&pxp->lock, flags); + list_move_tail(&desc->list, &head); + spin_unlock_irqrestore(&pxp->lock, flags); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock(&pxp_chan->lock); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock(&pxp_chan->lock); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + return cookie; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + INIT_LIST_HEAD(&pxp_chan->queue); + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child, *_child; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + int pxp_irq_status = 0; + + dump_pxp_reg(pxp); + + if (__raw_readl(pxp->base + HW_PXP_STAT) & BM_PXP_STAT_IRQ0) + __raw_writel(BM_PXP_STAT_IRQ0, pxp->base + HW_PXP_STAT_CLR); + else { + int irq_clr = 0; + + pxp_irq_status = __raw_readl(pxp->base + HW_PXP_IRQ); + BUG_ON(!pxp_irq_status); + + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_CH1_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_FIRST_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_FIRST_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ; + + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH0_STORE_IRQ; + if (pxp_irq_status & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) + irq_clr |= BM_PXP_IRQ_DITHER_CH1_STORE_IRQ; + /*XXX other irqs status clear should be added below */ + + __raw_writel(irq_clr, pxp->base + HW_PXP_IRQ_CLR); + + pxp_writel(BM_PXP_CTRL_ENABLE, HW_PXP_CTRL_CLR); + } + pxp_collision_status_report(pxp, &col_info); + pxp_histogram_status_report(pxp, &hist_status); + /*XXX before a new update operation, we should + * always clear all the collision information + */ + pxp_collision_detection_disable(pxp); + pxp_histogram_disable(pxp); + + pxp_writel(0x0, HW_PXP_CTRL); + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + spin_lock_irqsave(&pxp->lock, flags); + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = list_entry(head.next, struct pxp_tx_desc, list); + pxp_chan = to_pxp_channel(desc->txd.chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_for_each_entry_safe(child, _child, &desc->tx_list, list) { + list_del_init(&child->list); + kmem_cache_free(tx_desc_cache, (void *)child); + } + list_del_init(&desc->list); + kmem_cache_free(tx_desc_cache, (void *)desc); + + complete(&pxp->complete); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* allocate/free dma tx descriptor dynamically*/ +static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc = NULL; + struct dma_async_tx_descriptor *txd = NULL; + + desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return NULL; + + INIT_LIST_HEAD(&desc->list); + INIT_LIST_HEAD(&desc->tx_list); + txd = &desc->txd; + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + return desc; +} + + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum + dma_transfer_direction + direction, + unsigned long tx_flags, + void *context) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *pos = NULL, *next = NULL; + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_alloc(pxp_chan); + if (!desc) { + dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n"); + + if (first) { + list_for_each_entry_safe(pos, next, &first->tx_list, list) { + list_del_init(&pos->list); + kmem_cache_free(tx_desc_cache, (void*)pos); + } + list_del_init(&first->list); + kmem_cache_free(tx_desc_cache, (void*)first); + } + + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + + spin_lock(&pxp_chan->lock); + + if (list_empty(&pxp_chan->queue)) { + spin_unlock(&pxp_chan->lock); + return; + } + + pxpdma_dequeue(pxp_chan, pxp); + pxp_chan->status = PXP_CHANNEL_READY; + + spin_unlock(&pxp_chan->lock); + + pxp_clk_enable(pxp); + wake_up_interruptible(&pxp->thread_waitq); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_device_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + __pxp_terminate_all(chan); + spin_unlock(&pxp_chan->lock); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + spin_lock(&pxp_chan->lock); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + spin_unlock(&pxp_chan->lock); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_COMPLETE; +} + +static void pxp_data_path_config_v3p(struct pxps *pxp) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)| + BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)| + BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0), + pxp->base + HW_PXP_DATA_PATH_CTRL0); + + /* + * MUX17: HIST_B as histogram: 0: output buffer, 1: wfe_store + * MUX16: HIST_A as collision: 0: output buffer, 1: wfe_store + */ + if (pxp_is_v3(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1)| + BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1); + __raw_writel(val, pxp->base + HW_PXP_DATA_PATH_CTRL1); +} + +static void pxp_soft_reset(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET); + while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE)) + dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__); + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR); + __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR); +} + +static void pxp_sram_init(struct pxps *pxp, u32 select, + u32 buffer_addr, u32 length) +{ + u32 i; + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(1), + pxp->base + HW_PXP_INIT_MEM_CTRL); + + if ((select == WFE_A) || (select == WFE_B)) { + for (i = 0; i < length / 2; i++) { + __raw_writel(*(((u32*)buffer_addr) + 2 * i + 1), + pxp->base + HW_PXP_INIT_MEM_DATA_HIGH); + + __raw_writel(*(((u32*)buffer_addr) + 2 * i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } else { + for (i = 0; i < length; i++) { + __raw_writel(*(((u32*) buffer_addr) + i), + pxp->base + HW_PXP_INIT_MEM_DATA); + } + } + + __raw_writel( + BF_PXP_INIT_MEM_CTRL_ADDR(0) | + BF_PXP_INIT_MEM_CTRL_SELECT(select) | + BF_PXP_INIT_MEM_CTRL_START(0), + pxp->base + HW_PXP_INIT_MEM_CTRL); +} + +/* + * wfe a configuration + * configure wfe a engine for waveform processing + * including its fetch and store module + */ +static void pxp_wfe_a_configure(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(8) | + BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(1) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(10) | + BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(15), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(4) | + BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFA_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFA_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_A_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_A_STORE_D_MASK4_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_H_CH0); + + + __raw_writel( + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_A_STORE_F_MASK_L_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_A_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_A_PARAM_PARAM0(0) | + BF_PXP_ALU_A_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_A_PARAM); + + __raw_writel(BF_PXP_ALU_A_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_A_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_A_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_A_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_A_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_A_CTRL_BYPASS (1) | + BF_PXP_ALU_A_CTRL_ENABLE (1) | + BF_PXP_ALU_A_CTRL_START (0) | + BF_PXP_ALU_A_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_A_CTRL); + + /* WFE A */ + __raw_writel(0x3F3F0303, pxp->base + HW_PXP_WFE_A_STAGE1_MUX0); + __raw_writel(0x0C00000C, pxp->base + HW_PXP_WFE_A_STAGE1_MUX1); + __raw_writel(0x01040000, pxp->base + HW_PXP_WFE_A_STAGE1_MUX2); + __raw_writel(0x0A0A0904, pxp->base + HW_PXP_WFE_A_STAGE1_MUX3); + __raw_writel(0x00000B0B, pxp->base + HW_PXP_WFE_A_STAGE1_MUX4); + + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX0); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX1); + __raw_writel(0x280E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX2); + __raw_writel(0x00011800, pxp->base + HW_PXP_WFE_A_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX4); + __raw_writel(0x1800280E, pxp->base + HW_PXP_WFE_A_STAGE2_MUX5); + __raw_writel(0x00280E01, pxp->base + HW_PXP_WFE_A_STAGE2_MUX6); + __raw_writel(0x1A0E0118, pxp->base + HW_PXP_WFE_A_STAGE2_MUX7); + __raw_writel(0x1B012911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX8); + __raw_writel(0x00002911, pxp->base + HW_PXP_WFE_A_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STAGE2_MUX12); + + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_A_STAGE3_MUX0); + __raw_writel(0x3F3F3F08, pxp->base + HW_PXP_WFE_A_STAGE3_MUX1); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_A_STAGE3_MUX2); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_A_STAGE3_MUX3); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f030100, pxp->base + HW_PXP_WFE_A_STAGE2_5X6_ADDR_0); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_A_STG2_5X1_OUT3); + __raw_writel(0x071F1F1F, pxp->base + HW_PXP_WFE_A_STG2_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT3_7); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_3); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_4); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_5); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_6); + __raw_writel(0X0F0F0F0F, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG2_5X6_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +static void pxp_wfe_a_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + /* FETCH */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(3), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(4) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel(1, pxp->base + HW_PXP_WFB_ARRAY_REG2); + + /* STORE */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(8)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xf), /* fetch CP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00), /* fetch NP */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x00000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000), /* fetch LUT */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK3_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xf), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(0x0), /* fetch Y4 */ + pxp->base + HW_PXP_WFE_B_STORE_D_MASK4_L_CH0); + + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK5_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK6_L_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_H_CH0); + __raw_writel(0x0, pxp->base + HW_PXP_WFE_B_STORE_D_MASK7_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32+6)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x1) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0x2) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0x4) | + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0x8), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0x0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0x0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel(BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE A */ + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000003, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x04000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x0A090401, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x000B0B0A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x290C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00021901, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1901290C, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x01290C02, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x1B0C0219, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x1C022A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x02002A0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x2a123a1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x00000013, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x3b202c1d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x003b202d, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x03020100, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x001F1F1F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3f232120, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0x04050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0x04040404, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0x05080808, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0x05050505, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_0); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_1); + __raw_writel(0x070C0C0C, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_2); + __raw_writel(0x07070707, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_3); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_4); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_5); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_6); + __raw_writel(0x0F0F0F0F, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT3_7); + + __raw_writel(0x070F1F1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0x00000700, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0x00007000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel(0x0000A000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT2_7); + + __raw_writel(0x000000C0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT3_7); + + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, + proc_data->lut_sels, 1); +} + +/* + * wfe a processing + * use wfe a to process an update + * x,y,width,height: + * coordinate and size of the update region + * wb: + * working buffer, 16bpp + * upd: + * update buffer, in Y4 with or without alpha, 8bpp + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * y4c: + * y4c buffer, {Y4[3:0],3'b000,collision}, 8bpp + * lut: + * valid value 0-63 + * set to the lut used for next update + * partial: + * 0 - full update + * 1 - partial update + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + */ +static void pxp_wfe_a_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFA_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFA_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFA_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFA_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFA_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFA_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_A_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_A_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_A_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_A_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_A_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_A_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_A_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_A_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_A_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_A_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_A_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_A_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_A_CTRL_ENABLE(1) | + BF_PXP_WFE_A_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_A_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFA_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); +} + +static void pxp_wfe_a_process_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_a_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_a_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_a_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_a_store_param[1]; + int v; + + if (fetch_ch0->width != fetch_ch1->width || + fetch_ch0->height != fetch_ch1->height) { + dev_err(pxp->dev, "width/height should be same for two fetch " + "channels\n"); + } + + print_param(fetch_ch0, "wfe_a fetch_ch0"); + print_param(fetch_ch1, "wfe_a fetch_ch1"); + print_param(store_ch0, "wfe_a store_ch0"); + print_param(store_ch1, "wfe_a store_ch1"); + + /* Fetch */ + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height - 1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel(fetch_ch1->stride * 2, pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel(BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height - 1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width - 1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + /* Store */ + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + + __raw_writel(BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0( + store_ch1->paddr + (store_ch1->left + store_ch1->top * + store_ch1->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel(BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + /* Here it should be fetch_ch1 */ + __raw_writel(BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch1->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch1->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel((proc_data->lut & 0x000000FF) | 0x00000F00, + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + __raw_writel((proc_data->partial_update | (proc_data->reagl_en << 1)), + pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); + + if (proc_data->alpha_en) { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } else { + __raw_writel(BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(2) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(0), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + } + + /* disable CH1 when only doing detection */ + v = __raw_readl(pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + if (proc_data->detection_only) { + v &= ~BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + printk(KERN_EMERG "%s: detection only happens\n", __func__); + } else + v |= BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(1); + __raw_writel(v, pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); +} + +/* + * wfe b configuration + * + * configure wfe b engnine for reagl/-d waveform processing + */ +static void pxp_wfe_b_configure(struct pxps *pxp) +{ + /* Fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(10) | + BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(15), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(2) | + BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(0) | + BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(7), + pxp->base + HW_PXP_WFB_ARRAY_PIXEL7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG0_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG1_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG2_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG3_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG4_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG5_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG6_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG7_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(8) | + BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(8), + pxp->base + HW_PXP_WFB_ARRAY_FLAG8_MASK); + + __raw_writel( + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(0) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(1) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(9) | + BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(9), + pxp->base + HW_PXP_WFB_ARRAY_FLAG9_MASK); + + pxp_sram_init(pxp, WFE_B, (u32)active_matrix_data_8x8, 64); + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(1) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(1)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(0), + pxp->base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel(BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xff), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel(BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(2)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(6)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(0)| + BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_H_CH0); + + /* ALU */ + __raw_writel(BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(0), + pxp->base + HW_PXP_ALU_B_INST_ENTRY); + + __raw_writel(BF_PXP_ALU_B_PARAM_PARAM0(0) | + BF_PXP_ALU_B_PARAM_PARAM1(0), + pxp->base + HW_PXP_ALU_B_PARAM); + + __raw_writel(BF_PXP_ALU_B_CONFIG_BUF_ADDR(0), + pxp->base + HW_PXP_ALU_B_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_CONFIG_MODE(0) | + BF_PXP_ALU_B_LUT_CONFIG_EN(0), + pxp->base + HW_PXP_ALU_B_LUT_CONFIG); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA0); + + __raw_writel(BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(0), + pxp->base + HW_PXP_ALU_B_LUT_DATA1); + + __raw_writel( + BF_PXP_ALU_B_CTRL_BYPASS (1) | + BF_PXP_ALU_B_CTRL_ENABLE (1) | + BF_PXP_ALU_B_CTRL_START (0) | + BF_PXP_ALU_B_CTRL_SW_RESET (0), + pxp->base + HW_PXP_ALU_B_CTRL); + + /* WFE */ + __raw_writel(0x00000402, pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + __raw_writel(0x02040608, pxp->base + HW_PXP_WFE_B_STAGE1_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX4); + __raw_writel(0x03000000, pxp->base + HW_PXP_WFE_B_STAGE1_MUX5); + __raw_writel(0x050A040A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX6); + __raw_writel(0x070A060A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX7); + __raw_writel(0x0000000A, pxp->base + HW_PXP_WFE_B_STAGE1_MUX8); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX0); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX1); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX2); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX4); + __raw_writel(0x1C1E2022, pxp->base + HW_PXP_WFE_B_STAGE2_MUX5); + __raw_writel(0x1215181A, pxp->base + HW_PXP_WFE_B_STAGE2_MUX6); + __raw_writel(0x00000C0F, pxp->base + HW_PXP_WFE_B_STAGE2_MUX7); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX8); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX9); + __raw_writel(0x01000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX10); + __raw_writel(0x000C010B, pxp->base + HW_PXP_WFE_B_STAGE2_MUX11); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE2_MUX12); + + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX0); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX1); + __raw_writel(0x09000C01, pxp->base + HW_PXP_WFE_B_STAGE3_MUX2); + __raw_writel(0x003A2A1D, pxp->base + HW_PXP_WFE_B_STAGE3_MUX3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STAGE3_MUX7); + __raw_writel(0x07060504, pxp->base + HW_PXP_WFE_B_STAGE3_MUX8); + __raw_writel(0x00000008, pxp->base + HW_PXP_WFE_B_STAGE3_MUX9); + __raw_writel(0x00001211, pxp->base + HW_PXP_WFE_B_STAGE3_MUX10); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT0_7); + + __raw_writel(0x02010100, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_0); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_1); + __raw_writel(0x03020201, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_2); + __raw_writel(0x04030302, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_3); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_4); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_5); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_6); + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X8_OUT1_7); + + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STAGE1_5X8_MASKS_0); + + __raw_writel(0x00000000, pxp->base + HW_PXP_WFE_B_STG1_5X1_OUT0); + __raw_writel(0x0000000F, pxp->base + HW_PXP_WFE_B_STG1_5X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT2_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT3_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT4_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_MASKS_0); + __raw_writel(0x3F3F3F3F, pxp->base + HW_PXP_WFE_B_STAGE2_5X6_ADDR_0); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X6_OUT1_7); + + __raw_writel(0x00008000, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT0); + __raw_writel(0x0000FFFE, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT2); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG2_5X1_OUT3); + __raw_writel(0x00000F0F, pxp->base + HW_PXP_WFE_B_STG2_5X1_MASKS); + + __raw_writel(0x00007F7F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_MASKS); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_0); + __raw_writel(0x00FF00FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_2); + __raw_writel(0x000000FF, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT0_7); + + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_0); + __raw_writel(0xFF3FFF3F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_1); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_2); + __raw_writel(0xFFFFFF1F, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_3); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_4); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_5); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_6); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG3_F8X1_OUT1_7); + + __raw_writel( + BF_PXP_WFE_B_CTRL_ENABLE(1) | + BF_PXP_WFE_B_CTRL_SW_RESET(1), + pxp->base + HW_PXP_WFE_B_CTRL); +} + +/* wfe b processing + * use wfe b to process an update + * call this function only after pxp_wfe_a_processing + * x,y,width,height: + * coordinate and size of the update region + * twb: + * temp working buffer, 16bpp + * only used when reagl_en is 1 + * wb: + * working buffer, 16bpp + * lut: + * lut buffer, 8bpp + * lut_update: + * 0 - wfe_b is used for reagl/reagl-d operation + * 1 - wfe_b is used for lut update operation + * reagl_d_en: + * 0 - use reagl waveform algorithm + * 1 - use reagl/-d waveform algorithm + */ +static void pxp_wfe_b_process(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &config_data->proc_data; + struct pxp_layer_param *fetch_ch0 = &config_data->wfe_b_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->wfe_b_fetch_param[1]; + struct pxp_layer_param *store_ch0 = &config_data->wfe_b_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->wfe_b_store_param[1]; + static int comp_mask; + /* Fetch */ + + print_param(fetch_ch0, "wfe_b fetch_ch0"); + print_param(fetch_ch1, "wfe_b fetch_ch1"); + print_param(store_ch0, "wfe_b store_ch0"); + print_param(store_ch1, "wfe_b store_ch1"); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF1_ADDR); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(fetch_ch0->top) | + BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(fetch_ch0->left), + pxp->base + HW_PXP_WFB_FETCH_BUF1_CORD); + + __raw_writel(fetch_ch0->stride, + pxp->base + HW_PXP_WFB_FETCH_BUF1_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(fetch_ch0->height-1) | + BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(fetch_ch0->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF1_SIZE); + + __raw_writel(fetch_ch1->paddr, pxp->base + HW_PXP_WFB_FETCH_BUF2_ADDR); + + __raw_writel(fetch_ch1->stride * 2, + pxp->base + HW_PXP_WFB_FETCH_BUF2_PITCH); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(fetch_ch1->top) | + BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(fetch_ch1->left), + pxp->base + HW_PXP_WFB_FETCH_BUF2_CORD); + + __raw_writel( + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(fetch_ch1->height-1) | + BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(fetch_ch1->width-1), + pxp->base + HW_PXP_WFB_FETCH_BUF2_SIZE); + + if (!proc_data->lut_update) { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } + +#ifdef CONFIG_REAGLD_ALGO_CHECK + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((fetch_ch0->comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); +#else + __raw_writel( + (__raw_readl(pxp->base + HW_PXP_WFE_B_SW_DATA_REGS) & 0x0000FFFF) | ((comp_mask&0x000000FF)<<16), + pxp->base + HW_PXP_WFE_B_SW_DATA_REGS); + + /* comp_mask only need to be updated upon REAGL-D, 0,1,...7, 0,1,... */ + if (proc_data->reagl_d_en) { + comp_mask++; + if (comp_mask>7) + comp_mask = 0; + } +#endif + + /* Store */ + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height-1), + pxp->base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride * 2)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride * 2), + pxp->base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr + + (store_ch0->left + store_ch0->top * store_ch0->stride) * 2), + pxp->base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + if (proc_data->lut_update) { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x3f0000), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(0x30)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(4)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } else { + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x3f00), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x0), + pxp->base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(3)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(0)| + BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_MASK_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(8)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(0), + pxp->base + HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0); + } + + /* ALU */ + __raw_writel( + BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(fetch_ch0->width) | + BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_ALU_B_BUF_SIZE); + + /* WFE */ + __raw_writel( + BF_PXP_WFE_B_DIMENSIONS_WIDTH(fetch_ch0->width) | + BF_PXP_WFE_B_DIMENSIONS_HEIGHT(fetch_ch0->height), + pxp->base + HW_PXP_WFE_B_DIMENSIONS); + + __raw_writel( /*TODO check*/ + BF_PXP_WFE_B_OFFSET_X_OFFSET(fetch_ch0->left) | + BF_PXP_WFE_B_OFFSET_Y_OFFSET(fetch_ch0->top), + pxp->base + HW_PXP_WFE_B_OFFSET); + + __raw_writel(proc_data->reagl_d_en, pxp->base + HW_PXP_WFE_B_SW_FLAG_REGS); +} + +void pxp_fill( + u32 bpp, + u32 value, + u32 width, + u32 height, + u32 output_buffer, + u32 output_pitch) +{ + u32 active_bpp; + u32 pitch; + + if (bpp == 8) { + active_bpp = 0; + pitch = output_pitch; + } else if(bpp == 16) { + active_bpp = 1; + pitch = output_pitch * 2; + } else { + active_bpp = 2; + pitch = output_pitch * 4; + } + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp_reg_base + HW_PXP_WFE_B_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(width-1)| + BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(height-1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(pitch)| + BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(pitch), + pxp_reg_base + HW_PXP_WFE_B_STORE_PITCH); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(active_bpp)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(output_buffer), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(value), + pxp_reg_base + HW_PXP_WFE_B_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(0x00000000), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_H_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(0x000000ff), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_MASK2_L_CH0); + + __raw_writel( + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(40)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp_reg_base + HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (1) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (1) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp_reg_base + HW_PXP_CTRL2); + + if (busy_wait(BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ & + __raw_readl(pxp_reg_base + HW_PXP_IRQ)) == false) + printk("%s: wait for completion timeout\n", __func__); +} +EXPORT_SYMBOL(pxp_fill); + +static void pxp_lut_cleanup_multiple(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->lut_cleanup == 1) { + if (set) { + __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0 + 0x4); + __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1 + 0x4); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT1_1); + } + } +} + +static void pxp_lut_cleanup_multiple_v3p(struct pxps *pxp, u64 lut, bool set) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->lut_cleanup == 1) { + if (set) { + __raw_writel((u32)lut, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0 + 0x4); + __raw_writel((u32)(lut>>32), pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1 + 0x4); + } else { + pxp_luts_deactivate(pxp, lut); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_0); + __raw_writel(0, pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT1_1); + } + } +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +void m4_process(void) +{ + __raw_writel(0x7, pinctrl_base + PIN_DOUT); /* M4 Start */ + + while (!(__raw_readl(pxp_reg_base + HW_PXP_HANDSHAKE_CPU_STORE) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY)); + + __raw_writel(0x3, pinctrl_base + PIN_DOUT); /* M4 Stop */ + + +} +#else +void m4_process(void) {} +#endif +EXPORT_SYMBOL(m4_process); + +static void pxp_lut_status_set(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_set_v3p(struct pxps *pxp, unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) | (1 << lut), + pxp->base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +static void pxp_luts_activate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_set) + pxp->devdata->pxp_lut_status_set(pxp, i); + } +} + +static void pxp_lut_status_clr(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_A_STG1_8X1_OUT0_1); + } +} + +static void pxp_lut_status_clr_v3p(unsigned int lut) +{ + if(lut<32) + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_0); + else + { + lut = lut -32; + __raw_writel( + __raw_readl(pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1) & (~(1 << lut)), + pxp_reg_base + HW_PXP_WFE_B_STG1_8X1_OUT0_1); + } +} + +/* this function should be called in the epdc + * driver explicitly when some epdc lut becomes + * idle. So it should be exported. + */ +static void pxp_luts_deactivate(struct pxps *pxp, u64 lut_status) +{ + int i = 0; + + if (!lut_status) + return; + + for (i = 0; i < 64; i++) { + if (lut_status & (1ULL << i)) + if (pxp->devdata && pxp->devdata->pxp_lut_status_clr) + pxp->devdata->pxp_lut_status_clr(i); + } +} + +/* use histogram_B engine to calculate histogram status */ +static void pxp_histogram_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_HIST_B_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_B_BUF_SIZE_WIDTH(width), + pxp->base + HW_PXP_HIST_B_BUF_SIZE); + + if (pxp_is_v3(pxp)) + val = 64; + else if (pxp_is_v3p(pxp)) + val = 64 + 4; + + __raw_writel( + BF_PXP_HIST_B_MASK_MASK_EN(1)| + BF_PXP_HIST_B_MASK_MASK_MODE(0)| + BF_PXP_HIST_B_MASK_MASK_OFFSET(val)| + BF_PXP_HIST_B_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_B_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_B_MASK_MASK_VALUE1(0), + pxp->base + HW_PXP_HIST_B_MASK); + + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(8)| + BF_PXP_HIST_B_CTRL_CLEAR(0)| + BF_PXP_HIST_B_CTRL_ENABLE(1), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +static void pxp_histogram_status_report(struct pxps *pxp, u32 *hist_status) +{ + BUG_ON(!hist_status); + + *hist_status = (__raw_readl(pxp->base + HW_PXP_HIST_B_CTRL) & BM_PXP_HIST_B_CTRL_STATUS) + >> BP_PXP_HIST_B_CTRL_STATUS; + dev_dbg(pxp->dev, "%d pixels are used to calculate histogram status %d\n", + __raw_readl(pxp->base + HW_PXP_HIST_B_TOTAL_PIXEL), *hist_status); +} + +static void pxp_histogram_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(3)| + BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(4)| + BF_PXP_HIST_B_CTRL_CLEAR(1)| + BF_PXP_HIST_B_CTRL_ENABLE(0), + pxp->base + HW_PXP_HIST_B_CTRL); +} + +/* the collision detection function will be + * called by epdc driver when required + */ +static void pxp_collision_detection_enable(struct pxps *pxp, + unsigned int width, + unsigned int height) +{ + u32 val = 0; + + __raw_writel( + BF_PXP_HIST_A_BUF_SIZE_HEIGHT(height)| + BF_PXP_HIST_A_BUF_SIZE_WIDTH(width), + pxp_reg_base + HW_PXP_HIST_A_BUF_SIZE); + + if (pxp_is_v3(pxp)) + val = 65; + else if (pxp_is_v3p(pxp)) + val = 65 + 4; + + __raw_writel( + BF_PXP_HIST_A_MASK_MASK_EN(1)| + BF_PXP_HIST_A_MASK_MASK_MODE(0)| + BF_PXP_HIST_A_MASK_MASK_OFFSET(val)| + BF_PXP_HIST_A_MASK_MASK_WIDTH(0)| + BF_PXP_HIST_A_MASK_MASK_VALUE0(1) | + BF_PXP_HIST_A_MASK_MASK_VALUE1(0), + pxp_reg_base + HW_PXP_HIST_A_MASK); + + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(0)| + BF_PXP_HIST_A_CTRL_ENABLE(1), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +static void pxp_collision_detection_disable(struct pxps *pxp) +{ + __raw_writel( + BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(6)| + BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(24)| + BF_PXP_HIST_A_CTRL_CLEAR(1)| + BF_PXP_HIST_A_CTRL_ENABLE(0), + pxp_reg_base + HW_PXP_HIST_A_CTRL); +} + +/* this function can be called in the epdc callback + * function in the pxp_irq() to let the epdc know + * the collision information for the previous working + * buffer update. + */ +static bool pxp_collision_status_report(struct pxps *pxp, struct pxp_collision_info *info) +{ + unsigned int count; + + BUG_ON(!info); + memset(info, 0x0, sizeof(*info)); + + info->pixel_cnt = count = __raw_readl(pxp->base + HW_PXP_HIST_A_TOTAL_PIXEL); + if (!count) + return false; + + dev_dbg(pxp->dev, "%s: pixel_cnt = %d\n", __func__, info->pixel_cnt); + info->rect_min_x = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_x = %d\n", __func__, info->rect_min_x); + info->rect_max_x = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_X) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_x = %d\n", __func__, info->rect_max_x); + info->rect_min_y = __raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_min_y = %d\n", __func__, info->rect_min_y); + info->rect_max_y = (__raw_readl(pxp->base + HW_PXP_HIST_A_ACTIVE_AREA_Y) >> 16) & 0xffff; + dev_dbg(pxp->dev, "%s: rect_max_y = %d\n", __func__, info->rect_max_y); + + info->victim_luts[0] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT0); + dev_dbg(pxp->dev, "%s: victim_luts[0] = 0x%x\n", __func__, info->victim_luts[0]); + info->victim_luts[1] = __raw_readl(pxp->base + HW_PXP_HIST_A_RAW_STAT1); + dev_dbg(pxp->dev, "%s: victim_luts[1] = 0x%x\n", __func__, info->victim_luts[1]); + + return true; +} + +void pxp_get_collision_info(struct pxp_collision_info *info) +{ + BUG_ON(!info); + + memcpy(info, &col_info, sizeof(struct pxp_collision_info)); +} +EXPORT_SYMBOL(pxp_get_collision_info); + +static void dither_prefetch_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *fetch_ch1 = &config_data->dither_fetch_param[1]; + + print_param(fetch_ch0, "dither fetch_ch0"); + print_param(fetch_ch1, "dither fetch_ch1"); + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(2) | + BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(0) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(0), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1); + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(fetch_ch0->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(fetch_ch0->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(fetch_ch1->width - 1) | + BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(fetch_ch1->height - 1), + pxp->base + HW_PXP_DITHER_FETCH_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(fetch_ch0->stride) | + BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(fetch_ch1->stride), + pxp->base + HW_PXP_DITHER_FETCH_PITCH); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(0) | + BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(0) | + BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(0), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(7) | + BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(7), + pxp->base + HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(fetch_ch0->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(fetch_ch1->paddr), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_FETCH_ADDR_1_CH1); +} + +static void dither_store_config(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + struct pxp_layer_param *store_ch1 = &config_data->dither_store_param[1]; + + print_param(store_ch0, "dither store_ch0"); + print_param(store_ch1, "dither store_ch1"); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(32), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(store_ch1->width - 1) | + BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(store_ch1->height - 1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(store_ch0->stride) | + BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(store_ch1->stride), + pxp->base + HW_PXP_DITHER_STORE_PITCH); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(1), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(0)| + BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(0), + pxp->base + HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(store_ch0->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(store_ch1->paddr), + pxp->base + HW_PXP_DITHER_STORE_ADDR_0_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(0), + pxp->base + HW_PXP_DITHER_STORE_ADDR_1_CH1); + + __raw_writel( + BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(0), + pxp->base + HW_PXP_DITHER_STORE_FILL_DATA_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(0xffffff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK0_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(0x0), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_H_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xff), + pxp->base + HW_PXP_DITHER_STORE_D_MASK1_L_CH0); + + __raw_writel( + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(0) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(32)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1) | + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(0)| + BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(0), + pxp->base + HW_PXP_DITHER_STORE_D_SHIFT_L_CH0); +} + +static void pxp_set_final_lut_data(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + + if (proc_data->quant_bit < 2) { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit1_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xf0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else if (proc_data->quant_bit < 4) { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit2_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x50), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0xa0) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xa0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xf0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } else { + pxp_sram_init(pxp, DITHER0_LUT, (u32)bit4_dither_data_8x8, 64); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(0x0) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(0x10) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(0x20) | + BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(0x30), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA0); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(0x40) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(0x50) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(0x60) | + BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(0x70), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA1); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(0x80) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(0x90) | + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(0xa0)| + BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(0xb0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA2); + + __raw_writel( + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(0xc0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(0xd0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(0xe0) | + BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(0xf0), + pxp->base + HW_PXP_DITHER_FINAL_LUT_DATA3); + } +} + +static void pxp_dithering_process(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 val = 0; + + if (pxp->devdata && pxp->devdata->pxp_dithering_configure) + pxp->devdata->pxp_dithering_configure(pxp); + + if (pxp_is_v3(pxp)) + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (0) | + BF_PXP_DITHER_CTRL_ENABLE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE2 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE1 (0) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + else if (pxp_is_v3p(pxp)) { + if (proc_data->dither_mode != 0 && + proc_data->dither_mode != 3) { + dev_err(pxp->dev, "Not supported dithering mode. " + "Forced to be Orderred mode!\n"); + proc_data->dither_mode = 3; + } + + val = BF_PXP_DITHER_CTRL_ENABLE0 (1) | + BF_PXP_DITHER_CTRL_ENABLE1 (1) | + BF_PXP_DITHER_CTRL_ENABLE2 (1) | + BF_PXP_DITHER_CTRL_DITHER_MODE2(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE1(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_DITHER_MODE0(proc_data->dither_mode) | + BF_PXP_DITHER_CTRL_LUT_MODE (0) | + BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE (1) | + BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE (1) | + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE (0) | + BF_PXP_DITHER_CTRL_BUSY2 (0) | + BF_PXP_DITHER_CTRL_BUSY1 (0) | + BF_PXP_DITHER_CTRL_BUSY0 (0); + } + __raw_writel(val, pxp->base + HW_PXP_DITHER_CTRL); + + switch(proc_data->dither_mode) { + case PXP_DITHER_PASS_THROUGH: + /* no more settings required */ + break; + case PXP_DITHER_FLOYD: + case PXP_DITHER_ATKINSON: + case PXP_DITHER_ORDERED: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(1) | + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + pxp_set_final_lut_data(pxp); + + break; + case PXP_DITHER_QUANT_ONLY: + if(!proc_data->quant_bit || proc_data->quant_bit > 7) { + dev_err(pxp->dev, "unsupported quantization bit number!\n"); + return; + } + __raw_writel( + BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(proc_data->quant_bit), + pxp->base + HW_PXP_DITHER_CTRL_SET); + break; + default: + /* unknown mode */ + dev_err(pxp->dev, "unknown dithering mode passed!\n"); + __raw_writel(0x0, pxp->base + HW_PXP_DITHER_CTRL); + return; + } +} + +static void pxp_dithering_configure(struct pxps *pxp) +{ + dither_prefetch_config(pxp); + dither_store_config(pxp); +} + +static void pxp_dithering_configure_v3p(struct pxps *pxp) +{ + struct pxp_config_data *config_data = &pxp->pxp_conf_state; + struct pxp_layer_param *fetch_ch0 = &config_data->dither_fetch_param[0]; + struct pxp_layer_param *store_ch0 = &config_data->dither_store_param[0]; + + __raw_writel(BF_PXP_CTRL_BLOCK_SIZE(BV_PXP_CTRL_BLOCK_SIZE__8X8) | + BF_PXP_CTRL_ROTATE0(BV_PXP_CTRL_ROTATE0__ROT_0) | + BM_PXP_CTRL_IRQ_ENABLE, + pxp->base + HW_PXP_CTRL); + + __raw_writel(BF_PXP_PS_CTRL_DECX(BV_PXP_PS_CTRL_DECX__DISABLE) | + BF_PXP_PS_CTRL_DECY(BV_PXP_PS_CTRL_DECY__DISABLE) | + BF_PXP_PS_CTRL_FORMAT(BV_PXP_PS_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_PS_CTRL); + + __raw_writel(BF_PXP_OUT_CTRL_FORMAT(BV_PXP_OUT_CTRL_FORMAT__Y8), + pxp->base + HW_PXP_OUT_CTRL); + + __raw_writel(BF_PXP_PS_SCALE_YSCALE(4096) | + BF_PXP_PS_SCALE_XSCALE(4096), + pxp->base + HW_PXP_PS_SCALE); + + __raw_writel(store_ch0->paddr, pxp->base + HW_PXP_OUT_BUF); + + __raw_writel(store_ch0->stride, pxp->base + HW_PXP_OUT_PITCH); + + __raw_writel(BF_PXP_OUT_LRC_X(store_ch0->width - 1) | + BF_PXP_OUT_LRC_Y(store_ch0->height - 1), + pxp->base + HW_PXP_OUT_LRC); + + __raw_writel(BF_PXP_OUT_AS_ULC_X(1) | + BF_PXP_OUT_AS_ULC_Y(1), + pxp->base + HW_PXP_OUT_AS_ULC); + + __raw_writel(BF_PXP_OUT_AS_LRC_X(0) | + BF_PXP_OUT_AS_LRC_Y(0), + pxp->base + HW_PXP_OUT_AS_LRC); + + __raw_writel(BF_PXP_OUT_PS_ULC_X(0) | + BF_PXP_OUT_PS_ULC_Y(0), + pxp->base + HW_PXP_OUT_PS_ULC); + + __raw_writel(BF_PXP_OUT_PS_LRC_X(fetch_ch0->width - 1) | + BF_PXP_OUT_PS_LRC_Y(fetch_ch0->height - 1), + pxp->base + HW_PXP_OUT_PS_LRC); + + __raw_writel(fetch_ch0->paddr, pxp->base + HW_PXP_PS_BUF); + + __raw_writel(fetch_ch0->stride, pxp->base + HW_PXP_PS_PITCH); + + __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0); + + __raw_writel(BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(store_ch0->width-1)| + BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(store_ch0->height-1), + pxp->base + HW_PXP_DITHER_STORE_SIZE_CH0); + + __raw_writel(BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1), + pxp->base + HW_PXP_DATA_PATH_CTRL0_CLR); +} + +static void pxp_start2(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + int dither_wfe_a_handshake = 0; + int wfe_a_b_handshake = 0; + int count = 0; + + int wfe_a_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_A) == PXP_ENABLE_WFE_A); + int wfe_b_enable = ((proc_data->engine_enable & PXP_ENABLE_WFE_B) == PXP_ENABLE_WFE_B); + int dither_enable = ((proc_data->engine_enable & PXP_ENABLE_DITHER) == PXP_ENABLE_DITHER); + int handshake = ((proc_data->engine_enable & PXP_ENABLE_HANDSHAKE) == PXP_ENABLE_HANDSHAKE); + int dither_bypass = ((proc_data->engine_enable & PXP_ENABLE_DITHER_BYPASS) == PXP_ENABLE_DITHER_BYPASS); + u32 val = 0; + + if (dither_enable) + count++; + if (wfe_a_enable) + count++; + if (wfe_b_enable) + count++; + + if (count == 0) + return; + if (handshake && (count == 1)) { + dev_warn(pxp->dev, "Warning: Can not use handshake mode when " + "only one sub-block is enabled!\n"); + handshake = 0; + } + + if (handshake && wfe_b_enable && (wfe_a_enable == 0)) { + dev_err(pxp->dev, "WFE_B only works when WFE_A is enabled!\n"); + return; + } + + if (handshake && dither_enable && wfe_a_enable) + dither_wfe_a_handshake = 1; + if (handshake && wfe_a_enable && wfe_b_enable) + wfe_a_b_handshake = 1; + + dev_dbg(pxp->dev, "handshake %d, dither_wfe_a_handshake %d, " + "wfe_a_b_handshake %d, dither_bypass %d\n", + handshake, + dither_wfe_a_handshake, + wfe_a_b_handshake, + dither_bypass); + + if (handshake) { + /* for handshake, we only enable the last completion INT */ + if (wfe_b_enable) + __raw_writel(0x8000, pxp->base + HW_PXP_IRQ_MASK); + else if (wfe_a_enable) + __raw_writel(0x4000, pxp->base + HW_PXP_IRQ_MASK); + + /* Dither fetch */ + __raw_writel( + BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(1) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(32) | + BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(0) | + BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_FETCH_CTRL_CH0); + + if (dither_bypass) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(2) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + + } else if (dither_wfe_a_handshake) { + /* Dither store */ + __raw_writel( + BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(1)| + BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(0)| + BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(32)| + BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(0) | + BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(0), + pxp->base + HW_PXP_DITHER_STORE_CTRL_CH0); + + /* WFE_A fetch */ + __raw_writel( + BF_PXP_WFA_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(1) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFA_FETCH_CTRL); + } + + if (wfe_a_b_handshake) { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + + /* WFE_B fetch */ + __raw_writel( + BF_PXP_WFB_FETCH_CTRL_BF1_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_EN(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(0) | + BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(1) | + BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(0), + pxp->base + HW_PXP_WFB_FETCH_CTRL); + } else { + /* WFE_A Store */ + __raw_writel( + BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(0)| + BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1)| + BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(16), + pxp->base + HW_PXP_WFE_A_STORE_CTRL_CH1); + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + /* trigger operation */ + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(1) | + BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(1) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0) | + BF_PXP_CTRL_BLOCK_SIZE(1) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(1) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + return; + } + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_A(wfe_a_enable) | + BF_PXP_CTRL_ENABLE_WFE_B(wfe_b_enable) | + BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(0) | + BF_PXP_CTRL_ENABLE_ALPHA_B(0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL_ENABLE_WFE_B(wfe_a_enable | + wfe_b_enable); + + __raw_writel( + BF_PXP_CTRL_ENABLE(1) | + BF_PXP_CTRL_IRQ_ENABLE(0) | + BF_PXP_CTRL_NEXT_IRQ_ENABLE(0) | + BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(0) | + BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(0) | + BF_PXP_CTRL_ROTATE0(0) | + BF_PXP_CTRL_HFLIP0(0) | + BF_PXP_CTRL_VFLIP0(0) | + BF_PXP_CTRL_ROTATE1(0) | + BF_PXP_CTRL_HFLIP1(0) | + BF_PXP_CTRL_VFLIP1(0) | + BF_PXP_CTRL_ENABLE_PS_AS_OUT(0) | + BF_PXP_CTRL_ENABLE_DITHER(dither_enable) | + BF_PXP_CTRL_BLOCK_SIZE(0) | + BF_PXP_CTRL_ENABLE_CSC2(0) | + BF_PXP_CTRL_ENABLE_LUT(0) | + BF_PXP_CTRL_ENABLE_ROTATE0(0) | + BF_PXP_CTRL_ENABLE_ROTATE1(0) | + BF_PXP_CTRL_EN_REPEAT(0) | + val, + pxp->base + HW_PXP_CTRL); + + if (pxp_is_v3(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_A (0) | + BF_PXP_CTRL2_ENABLE_WFE_B (0) | + BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE (0) | + BF_PXP_CTRL2_ENABLE_ALPHA_B (0); + else if (pxp_is_v3p(pxp)) + val = BF_PXP_CTRL2_ENABLE_WFE_B(0); + + __raw_writel( + BF_PXP_CTRL2_ENABLE (0) | + BF_PXP_CTRL2_ROTATE0 (0) | + BF_PXP_CTRL2_HFLIP0 (0) | + BF_PXP_CTRL2_VFLIP0 (0) | + BF_PXP_CTRL2_ROTATE1 (0) | + BF_PXP_CTRL2_HFLIP1 (0) | + BF_PXP_CTRL2_VFLIP1 (0) | + BF_PXP_CTRL2_ENABLE_DITHER (0) | + BF_PXP_CTRL2_BLOCK_SIZE (0) | + BF_PXP_CTRL2_ENABLE_CSC2 (0) | + BF_PXP_CTRL2_ENABLE_LUT (0) | + BF_PXP_CTRL2_ENABLE_ROTATE0 (0) | + BF_PXP_CTRL2_ENABLE_ROTATE1 (0), + pxp->base + HW_PXP_CTRL2); + + dump_pxp_reg2(pxp); +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_terminate_all = pxp_device_terminate_all; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static ssize_t block_size_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", block_size); +} + +static ssize_t block_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char **last = NULL; + + block_size = simple_strtoul(buf, last, 0); + if (block_size > 1) + block_size = 1; + + return count; +} +static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO, + block_size_show, block_size_store); + +static struct platform_device_id imx_pxpdma_devtype[] = { + { + .name = "imx7d-pxp-dma", + .driver_data = PXP_V3, + }, { + .name = "imx6ull-pxp-dma", + .driver_data = PXP_V3P, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, imx_pxpdma_devtype); + +static const struct of_device_id imx_pxpdma_dt_ids[] = { + { .compatible = "fsl,imx7d-pxp-dma", .data = &imx_pxpdma_devtype[0], }, + { .compatible = "fsl,imx6ull-pxp-dma", .data = &imx_pxpdma_devtype[1], }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids); + +static int has_pending_task(struct pxps *pxp, struct pxp_channel *task) +{ + int found; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + found = !list_empty(&head); + spin_unlock_irqrestore(&pxp->lock, flags); + + return found; +} + +static int pxp_dispatch_thread(void *argv) +{ + struct pxps *pxp = (struct pxps *)argv; + struct pxp_channel *pending = NULL; + unsigned long flags; + + set_freezable(); + + while (!kthread_should_stop()) { + int ret; + ret = wait_event_freezable(pxp->thread_waitq, + has_pending_task(pxp, pending) || + kthread_should_stop()); + if (ret < 0) + continue; + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&pxp->lock, flags); + pxp->pxp_ongoing = 1; + spin_unlock_irqrestore(&pxp->lock, flags); + init_completion(&pxp->complete); + ret = pxpdma_dostart_work(pxp); + if (ret) { + pxp->pxp_ongoing = 0; + continue; + } + ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ); + if (ret == 0) { + printk(KERN_EMERG "%s: task is timeout\n\n", __func__); + break; + } + if (pxp->devdata && pxp->devdata->pxp_lut_cleanup_multiple) + pxp->devdata->pxp_lut_cleanup_multiple(pxp, 0, 0); + } + + return 0; +} + +static int pxp_init_interrupt(struct platform_device *pdev) +{ + int legacy_irq, std_irq, err; + struct pxps *pxp = platform_get_drvdata(pdev); + + legacy_irq = platform_get_irq(pdev, 0); + if (legacy_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp legacy irq: %d\n", + legacy_irq); + return legacy_irq; + } + + std_irq = platform_get_irq(pdev, 1); + if (std_irq < 0) { + dev_err(&pdev->dev, "failed to get pxp standard irq: %d\n", + std_irq); + return std_irq; + } + + err = devm_request_irq(&pdev->dev, legacy_irq, pxp_irq, 0, + "pxp-dmaengine-legacy", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp legacy irq failed: %d\n", err); + return err; + } + + err = devm_request_irq(&pdev->dev, std_irq, pxp_irq, 0, + "pxp-dmaengine-std", pxp); + if (err) { + dev_err(&pdev->dev, "Request pxp standard irq failed: %d\n", + err); + return err; + } + + pxp->irq = legacy_irq; + + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + return 0; +} + +static int pxp_create_attrs(struct platform_device *pdev) +{ + int ret = 0; + + if ((ret = device_create_file(&pdev->dev, &dev_attr_clk_off_timeout))) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + return ret; + } + + if ((ret = device_create_file(&pdev->dev, &dev_attr_block_size))) { + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + + dev_err(&pdev->dev, + "Unable to create file from block_size\n"); + return ret; + } + + return 0; +} + +static void pxp_remove_attrs(struct platform_device *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + device_remove_file(&pdev->dev, &dev_attr_block_size); +} + +static void pxp_init_timer(struct pxps *pxp) +{ + INIT_WORK(&pxp->work, clkoff_callback); + + timer_setup(&pxp->clk_timer, pxp_clkoff_timer, 0); +} + +static bool is_mux_node(uint32_t node_id) +{ + if ((node_id < PXP_2D_MUX_MUX0) || + (node_id > PXP_2D_MUX_MUX15)) + return false; + + return true; +} + +static bool search_mux_chain(uint32_t mux_id, + struct edge_node *enode) +{ + bool found = false; + uint32_t i, j, next_mux = 0; + uint32_t output; + struct mux *muxes; + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 2; i++) { + output = muxes[mux_id].mux_outputs[i]; + if (output == 0xff) + break; + + if ((output == enode->adjvex)) { + /* found */ + found = true; + break; + } else if (is_mux_node(output)) { + next_mux = output - PXP_2D_MUX_BASE; + found = search_mux_chain(next_mux, enode); + + if (found) { + for (j = 0; j < 4; j++) { + if (muxes[next_mux].mux_inputs[j] == + (mux_id + PXP_2D_MUX_BASE)) + break; + } + + set_bit(next_mux, (unsigned long *)&enode->mux_used); + set_mux_val(&enode->muxes, next_mux, j); + break; + } + } + } + + return found; +} + +static void enode_mux_config(unsigned int vnode_id, + struct edge_node *enode) +{ + uint32_t i, j; + bool via_mux = false, need_search = false; + struct mux *muxes; + + BUG_ON(vnode_id >= PXP_2D_NUM); + BUG_ON(enode->adjvex >= PXP_2D_NUM); + + muxes = (v3p_flag) ? muxes_v3p : muxes_v3; + + for (i = 0; i < 16; i++) { + for (j = 0; j < 4; j++) { + if (muxes[i].mux_inputs[j] == 0xff) + break; + + if (muxes[i].mux_inputs[j] == vnode_id) + need_search = true; + else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA0_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA0_S0) || + (vnode_id == PXP_2D_ALPHA0_S1)) + need_search = true; + } else if (muxes[i].mux_inputs[j] == PXP_2D_ALPHA1_S0_S1) { + if ((vnode_id == PXP_2D_ALPHA1_S0) || + (vnode_id == PXP_2D_ALPHA1_S1)) + need_search = true; + } + + if (need_search) { + via_mux = search_mux_chain(i, enode); + need_search = false; + break; + } + } + + if (via_mux) { + set_bit(i, (unsigned long *)&enode->mux_used); + set_mux_val(&enode->muxes, i, j); + break; + } + } +} + +static int pxp_create_initial_graph(struct platform_device *pdev) +{ + int i, j, first; + static bool (*adj_array)[PXP_2D_NUM]; + struct edge_node *enode, *curr = NULL; + + adj_array = (v3p_flag) ? adj_array_v3p : adj_array_v3; + + for (i = 0; i < PXP_2D_NUM; i++) { + switch (i) { + case PXP_2D_PS: + case PXP_2D_AS: + case PXP_2D_INPUT_FETCH0: + case PXP_2D_INPUT_FETCH1: + adj_list[i].type = PXP_2D_TYPE_INPUT; + break; + case PXP_2D_OUT: + case PXP_2D_INPUT_STORE0: + case PXP_2D_INPUT_STORE1: + adj_list[i].type = PXP_2D_TYPE_OUTPUT; + break; + default: + adj_list[i].type = PXP_2D_TYPE_ALU; + break; + } + + first = -1; + + for (j = 0; j < PXP_2D_NUM; j++) { + if (adj_array[i][j]) { + enode = kmem_cache_alloc(edge_node_cache, + GFP_KERNEL | __GFP_ZERO); + if (!enode) { + dev_err(&pdev->dev, "allocate edge node failed\n"); + return -ENOMEM; + } + enode->adjvex = j; + enode->prev_vnode = i; + + if (unlikely(first == -1)) { + first = j; + adj_list[i].first = enode; + } else + curr->next = enode; + + curr = enode; + enode_mux_config(i, enode); + dev_dbg(&pdev->dev, "(%d -> %d): mux_used 0x%x, mux_config 0x%x\n\n", + i, j, enode->mux_used, *(unsigned int*)&enode->muxes); + } + } + } + + return 0; +} + +/* Calculate the shortest paths start via + * 'from' node to other nodes + */ +static void pxp_find_shortest_path(unsigned int from) +{ + int i; + struct edge_node *enode; + struct path_node *pnode, *adjnode; + struct list_head queue; + + INIT_LIST_HEAD(&queue); + list_add_tail(&path_table[from][from].node, &queue); + + while(!list_empty(&queue)) { + pnode = list_entry(queue.next, struct path_node, node); + enode = adj_list[pnode->id].first; + while (enode) { + adjnode = &path_table[from][enode->adjvex]; + + if (adjnode->distance == DISTANCE_INFINITY) { + adjnode->distance = pnode->distance + 1; + adjnode->prev_node = pnode->id; + list_add_tail(&adjnode->node, &queue); + } + + enode = enode->next; + } + list_del_init(&pnode->node); + } + + for (i = 0; i < PXP_2D_NUM; i++) + pr_debug("From %u: to %d (id = %d, distance = 0x%x, prev_node = %d\n", + from, i, path_table[from][i].id, path_table[from][i].distance, + path_table[from][i].prev_node); +} + +static int pxp_gen_shortest_paths(struct platform_device *pdev) +{ + int i, j; + + for (i = 0; i < PXP_2D_NUM; i++) { + for (j = 0; j < PXP_2D_NUM; j++) { + path_table[i][j].id = j; + path_table[i][j].distance = DISTANCE_INFINITY; + path_table[i][j].prev_node = NO_PATH_NODE; + INIT_LIST_HEAD(&path_table[i][j].node); + } + + path_table[i][i].distance = 0; + + pxp_find_shortest_path(i); + } + + return 0; +} + +#ifdef CONFIG_MXC_FPGA_M4_TEST +static void pxp_config_m4(struct platform_device *pdev) +{ + fpga_tcml_base = ioremap(FPGA_TCML_ADDR, SZ_32K); + if (fpga_tcml_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + pinctrl_base = ioremap(PINCTRL, SZ_4K); + if (pinctrl_base == NULL) { + dev_err(&pdev->dev, + "get fpga_tcml_base error.\n"); + goto exit; + } + + __raw_writel(0xC0000000, pinctrl_base + 0x08); + __raw_writel(0x3, pinctrl_base + PIN_DOUT); + int i; + + for (i = 0; i < 1024 * 32 / 4; i++) + *(((unsigned int *)(fpga_tcml_base)) + i) = cm4_image[i]; +} +#endif + +static int pxp_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id = + of_match_device(imx_pxpdma_dt_ids, &pdev->dev); + struct pxps *pxp; + struct resource *res; + int err = 0; + + if (of_id) + pdev->id_entry = of_id->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + pxp->base = devm_ioremap_resource(&pdev->dev, res); + if (pxp->base == NULL) { + dev_err(&pdev->dev, "Couldn't ioremap regs\n"); + err = -ENODEV; + goto exit; + } + pxp_reg_base = pxp->base; + + pxp->pdev = pdev; + pxp->devdata = &pxp_devdata[pdev->id_entry->driver_data]; + + v3p_flag = (pxp_is_v3p(pxp)) ? true : false; + + pxp->ipg_clk = devm_clk_get(&pdev->dev, "pxp_ipg"); + pxp->axi_clk = devm_clk_get(&pdev->dev, "pxp_axi"); + + if (IS_ERR(pxp->ipg_clk) || IS_ERR(pxp->axi_clk)) { + dev_err(&pdev->dev, "pxp clocks invalid\n"); + err = -EINVAL; + goto exit; + } + + pxp_soft_reset(pxp); + pxp_writel(0x0, HW_PXP_CTRL); + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto exit; + + pxp_clk_enable(pxp); + pxp_soft_reset(pxp); + + /* Initialize PXP Interrupt */ + err = pxp_init_interrupt(pdev); + if (err < 0) + goto exit; + + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + + dump_pxp_reg(pxp); + pxp_clk_disable(pxp); + + pxp_init_timer(pxp); + + init_waitqueue_head(&pxp->thread_waitq); + /* allocate a kernel thread to dispatch pxp conf */ + pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch"); + if (IS_ERR(pxp->dispatch)) { + err = PTR_ERR(pxp->dispatch); + goto exit; + } + tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!tx_desc_cache) { + err = -ENOMEM; + goto exit; + } + + edge_node_cache = kmem_cache_create("edge_node", sizeof(struct edge_node), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!edge_node_cache) { + err = -ENOMEM; + kmem_cache_destroy(tx_desc_cache); + goto exit; + } + + err = pxp_create_attrs(pdev); + if (err) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + if ((err = pxp_create_initial_graph(pdev))) { + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + goto exit; + } + + pxp_gen_shortest_paths(pdev); + +#ifdef CONFIG_MXC_FPGA_M4_TEST + pxp_config_m4(pdev); +#endif + register_pxp_device(); + pm_runtime_enable(pxp->dev); + +exit: + if (err) + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n"); + return err; +} + +static int pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + unregister_pxp_device(); + kmem_cache_destroy(tx_desc_cache); + kmem_cache_destroy(edge_node_cache); + kthread_stop(pxp->dispatch); + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + clk_disable_unprepare(pxp->ipg_clk); + clk_disable_unprepare(pxp->axi_clk); + pxp_remove_attrs(pdev); + dma_async_device_unregister(&(pxp->pxp_dma.dma)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pxp_suspend(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct device *dev) +{ + struct pxps *pxp = dev_get_drvdata(dev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + pxp_soft_reset(pxp); + if (pxp->devdata && pxp->devdata->pxp_data_path_config) + pxp->devdata->pxp_data_path_config(pxp); + /* enable all the possible irq raised by PXP */ + __raw_writel(0xffff, pxp->base + HW_PXP_IRQ_MASK); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +#ifdef CONFIG_PM +static int pxp_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high release.\n"); + + return 0; +} + +static int pxp_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pxp busfreq high request.\n"); + + return 0; +} +#else +#define pxp_runtime_suspend NULL +#define pxp_runtime_resume NULL +#endif + +static const struct dev_pm_ops pxp_pm_ops = { + SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume) +}; + +static struct platform_driver pxp_driver = { + .driver = { + .name = "imx-pxp-v3", + .of_match_table = of_match_ptr(imx_pxpdma_dt_ids), + .pm = &pxp_pm_ops, + }, + .probe = pxp_probe, + .remove = pxp_remove, +}; + +static int __init pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} +late_initcall(pxp_init); + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} +module_exit(pxp_exit); + + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/reg_bitfields.h b/drivers/dma/pxp/reg_bitfields.h new file mode 100644 index 000000000000..0acb83d8e4a7 --- /dev/null +++ b/drivers/dma/pxp/reg_bitfields.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef _REG_BITFIELDS_H +#define _REG_BITFIELDS_H +struct mux_config { + uint32_t mux0_sel : 2; + uint32_t mux1_sel : 2; + uint32_t mux2_sel : 2; + uint32_t mux3_sel : 2; + uint32_t mux4_sel : 2; + uint32_t mux5_sel : 2; + uint32_t mux6_sel : 2; + uint32_t mux7_sel : 2; + uint32_t mux8_sel : 2; + uint32_t mux9_sel : 2; + uint32_t mux10_sel : 2; + uint32_t mux11_sel : 2; + uint32_t mux12_sel : 2; + uint32_t mux13_sel : 2; + uint32_t mux14_sel : 2; + uint32_t mux15_sel : 2; +}; + +/* legacy engine registers */ +struct ps_ctrl { + uint32_t format : 6; + uint32_t wb_swap : 1; + uint32_t rsvd0 : 1; + uint32_t decy : 2; + uint32_t decx : 2; + uint32_t rsvd1 : 20; +}; + +struct ps_scale { + uint32_t xscale : 15; + uint32_t rsvd1 : 1; + uint32_t yscale : 15; + uint32_t rsvd2 : 1; +}; + +struct ps_offset { + uint32_t xoffset : 12; + uint32_t rsvd1 : 4; + uint32_t yoffset : 12; + uint32_t rsvd2 : 4; +}; + +struct as_ctrl { + uint32_t rsvd0 : 1; + uint32_t alpha_ctrl : 2; + uint32_t enable_colorkey : 1; + uint32_t format : 4; + uint32_t alpha : 8; + uint32_t rop : 4; + uint32_t alpha0_invert : 1; + uint32_t alpha1_invert : 1; + uint32_t rsvd1 : 10; +}; + +struct out_ctrl { + uint32_t format : 5; + uint32_t rsvd0 : 3; + uint32_t interlaced_output : 2; + uint32_t rsvd1 : 13; + uint32_t alpha_output : 1; + uint32_t alpha : 8; +}; + +struct coordinate { + uint32_t y : 14; + uint32_t rsvd0 : 2; + uint32_t x : 14; + uint32_t rsvd1 : 2; +}; + +struct pxp_alpha_ctrl { + uint32_t poter_duff_enable : 1; + uint32_t s0_s1_factor_mode : 2; + uint32_t s0_global_alpha_mode : 2; + uint32_t s0_alpha_mode : 1; + uint32_t s0_color_mode : 1; + uint32_t rsvd1 : 1; + uint32_t s1_s0_factor_mode : 2; + uint32_t s1_global_alpha_mode : 2; + uint32_t s1_alpha_mode : 1; + uint32_t s1_color_mode : 1; + uint32_t rsvd0 : 2; + uint32_t s0_global_alpha : 8; + uint32_t s1_global_alpha : 8; +}; + +/* store engine registers */ +struct store_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t array_en : 1; + uint32_t array_line_num : 2; + uint32_t rsvd3 : 1; + uint32_t store_bypass_en : 1; + uint32_t store_memory_en : 1; + uint32_t pack_in_sel : 1; + uint32_t fill_data_en : 1; + uint32_t rsvd2 : 4; + uint32_t wr_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t combine_2channel : 1; + uint32_t rsvd0 : 6; + uint32_t arbit_en : 1; +}; + +struct store_size { + uint32_t out_width : 16; + uint32_t out_height : 16; +}; + +struct store_pitch { + uint32_t ch0_out_pitch : 16; + uint32_t ch1_out_pitch : 16; +}; + +struct store_shift_ctrl { + uint32_t rsvd2 : 2; + uint32_t output_active_bpp : 2; + uint32_t out_yuv422_1p_en : 1; + uint32_t out_yuv422_2p_en : 1; + uint32_t rsvd1 : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 24; +}; + +struct store_d_shift { + uint64_t d_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t d_shift_flag0 : 1; + uint64_t d_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t d_shift_flag1 : 1; + uint64_t d_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t d_shift_flag2 : 1; + uint64_t d_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t d_shift_flag3 : 1; + + uint64_t d_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t d_shift_flag4 : 1; + uint64_t d_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t d_shift_flag5 : 1; + uint64_t d_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t d_shift_flag6 : 1; + uint64_t d_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t d_shift_flag7 : 1; +}; + +struct store_f_shift { + uint64_t f_shift_width0 : 6; + uint64_t rsvd3 : 1; + uint64_t f_shift_flag0 : 1; + uint64_t f_shift_width1 : 6; + uint64_t rsvd2 : 1; + uint64_t f_shift_flag1 : 1; + uint64_t f_shift_width2 : 6; + uint64_t rsvd1 : 1; + uint64_t f_shift_flag2 : 1; + uint64_t f_shift_width3 : 6; + uint64_t rsvd0 : 1; + uint64_t f_shift_flag3 : 1; + + uint64_t f_shift_width4 : 6; + uint64_t rsvd7 : 1; + uint64_t f_shift_flag4 : 1; + uint64_t f_shift_width5 : 6; + uint64_t rsvd6 : 1; + uint64_t f_shift_flag5 : 1; + uint64_t f_shift_width6 : 6; + uint64_t rsvd5 : 1; + uint64_t f_shift_flag6 : 1; + uint64_t f_shift_width7 : 6; + uint64_t rsvd4 : 1; + uint64_t f_shift_flag7 : 1; +}; + +struct store_d_mask { + uint64_t d_mask_l : 32; + uint64_t d_mask_h : 32; +}; + +/* fetch engine registers */ +struct fetch_ctrl { + uint32_t ch_en : 1; + uint32_t block_en : 1; + uint32_t block_16 : 1; + uint32_t handshake_en : 1; + uint32_t bypass_pixel_en : 1; + uint32_t high_byte : 1; + uint32_t rsvd4 : 3; + uint32_t hflip : 1; + uint32_t vflip : 1; + uint32_t rsvd3 : 1; + uint32_t rotation_angle : 2; + uint32_t rsvd2 : 2; + uint32_t rd_num_bytes : 2; + uint32_t rsvd1 : 6; + uint32_t handshake_scan_line_num : 2; + uint32_t rsvd0 : 5; + uint32_t arbit_en : 1; +}; + +struct fetch_active_size_ulc { + uint32_t active_size_ulc_x : 16; + uint32_t active_size_ulc_y : 16; +}; + +struct fetch_active_size_lrc { + uint32_t active_size_lrc_x : 16; + uint32_t active_size_lrc_y : 16; +}; + +struct fetch_size { + uint32_t input_total_width : 16; + uint32_t input_total_height : 16; +}; + +struct fetch_pitch { + uint32_t ch0_input_pitch : 16; + uint32_t ch1_input_pitch : 16; +}; + +struct fetch_shift_ctrl { + uint32_t input_active_bpp : 2; + uint32_t rsvd1 : 6; + uint32_t expand_format : 3; + uint32_t expand_en : 1; + uint32_t shift_bypass : 1; + uint32_t rsvd0 : 19; +}; + +struct fetch_shift_offset { + uint32_t offset0 : 5; + uint32_t rsvd3 : 3; + uint32_t offset1 : 5; + uint32_t rsvd2 : 3; + uint32_t offset2 : 5; + uint32_t rsvd1 : 3; + uint32_t offset3 : 5; + uint32_t rsvd0 : 3; +}; + +struct fetch_shift_width { + uint32_t width0 : 4; + uint32_t width1 : 4; + uint32_t width2 : 4; + uint32_t width3 : 4; + uint32_t rsvd0 : 16; +}; +#endif diff --git a/drivers/dma/pxp/regs-pxp_v2.h b/drivers/dma/pxp/regs-pxp_v2.h new file mode 100644 index 000000000000..0e2ef8933ed1 --- /dev/null +++ b/drivers/dma/pxp/regs-pxp_v2.h @@ -0,0 +1,1139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale PXP Register Definitions + * + * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.29 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BP_PXP_CTRL_RSVD3 26 +#define BM_PXP_CTRL_RSVD3 0x0C000000 +#define BF_PXP_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_CTRL_RSVD3) +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ROT_POS 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BP_PXP_CTRL_RSVD1 12 +#define BM_PXP_CTRL_RSVD1 0x001FF000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 5 +#define BM_PXP_CTRL_RSVD0 0x000000E0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010 +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 9 +#define BM_PXP_STAT_RSVD2 0x0000FE00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 9) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000001F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND (0x00000100) + +#define BP_PXP_PS_BACKGROUND_RSVD 24 +#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD) +#define BP_PXP_PS_BACKGROUND_COLOR 0 +#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 21 +#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000 +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_HIST_CTRL (0x00000290) + +#define BP_PXP_HIST_CTRL_RSVD 6 +#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0 +#define BF_PXP_HIST_CTRL_RSVD(v) \ + (((v) << 6) & BM_PXP_HIST_CTRL_RSVD) +#define BP_PXP_HIST_CTRL_PANEL_MODE 4 +#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030 +#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE) +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3 +#define BP_PXP_HIST_CTRL_STATUS 0 +#define BM_PXP_HIST_CTRL_STATUS 0x0000000F +#define BF_PXP_HIST_CTRL_STATUS(v) \ + (((v) << 0) & BM_PXP_HIST_CTRL_STATUS) + +#define HW_PXP_HIST2_PARAM (0x000002a0) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 13 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 5 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x000002b0) + +#define BP_PXP_HIST4_PARAM_RSVD3 29 +#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 21 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 13 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 5 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x000002c0) + +#define BP_PXP_HIST8_PARAM0_RSVD3 29 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 21 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 13 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 5 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x000002d0) + +#define BP_PXP_HIST8_PARAM1_RSVD7 29 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 21 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 13 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 5 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x000002e0) + +#define BP_PXP_HIST16_PARAM0_RSVD3 29 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 21 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 13 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 5 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x000002f0) + +#define BP_PXP_HIST16_PARAM1_RSVD7 29 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 21 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 13 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 5 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00000300) + +#define BP_PXP_HIST16_PARAM2_RSVD11 29 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 21 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 13 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 5 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00000310) + +#define BP_PXP_HIST16_PARAM3_RSVD15 29 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 21 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 13 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 5 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_POWER (0x00000320) + +#define BP_PXP_POWER_CTRL 12 +#define BM_PXP_POWER_CTRL 0xFFFFF000 +#define BF_PXP_POWER_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_CTRL) +#define BP_PXP_POWER_ROT_MEM_LP_STATE 9 +#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE) +#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/drivers/dma/pxp/regs-pxp_v3.h b/drivers/dma/pxp/regs-pxp_v3.h new file mode 100644 index 000000000000..2fef8e9a169a --- /dev/null +++ b/drivers/dma/pxp/regs-pxp_v3.h @@ -0,0 +1,26939 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale PXP Register Definitions + * + * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.77 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BF_PXP_CTRL_SFTRST(v) \ + (((v) << 31) & BM_PXP_CTRL_SFTRST) +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BF_PXP_CTRL_CLKGATE(v) \ + (((v) << 30) & BM_PXP_CTRL_CLKGATE) +#define BM_PXP_CTRL_RSVD4 0x20000000 +#define BF_PXP_CTRL_RSVD4(v) \ + (((v) << 29) & BM_PXP_CTRL_RSVD4) +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BF_PXP_CTRL_EN_REPEAT(v) \ + (((v) << 28) & BM_PXP_CTRL_EN_REPEAT) +#define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1) +#define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0) +#define BM_PXP_CTRL_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT) +#define BM_PXP_CTRL_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2) +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE) +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_RSVD1 0x00400000 +#define BF_PXP_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_CTRL_RSVD1) +#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B) +#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B) +#define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A) +#define BM_PXP_CTRL_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER) +#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000 +#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \ + (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT) +#define BM_PXP_CTRL_VFLIP1 0x00008000 +#define BF_PXP_CTRL_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL_VFLIP1) +#define BM_PXP_CTRL_HFLIP1 0x00004000 +#define BF_PXP_CTRL_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL_HFLIP1) +#define BP_PXP_CTRL_ROTATE1 12 +#define BM_PXP_CTRL_ROTATE1 0x00003000 +#define BF_PXP_CTRL_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL_ROTATE1) +#define BV_PXP_CTRL_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL_VFLIP0 0x00000800 +#define BF_PXP_CTRL_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL_VFLIP0) +#define BM_PXP_CTRL_HFLIP0 0x00000400 +#define BF_PXP_CTRL_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL_HFLIP0) +#define BP_PXP_CTRL_ROTATE0 8 +#define BM_PXP_CTRL_ROTATE0 0x00000300 +#define BF_PXP_CTRL_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE0) +#define BV_PXP_CTRL_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL_RSVD0 6 +#define BM_PXP_CTRL_RSVD0 0x000000C0 +#define BF_PXP_CTRL_RSVD0(v) \ + (((v) << 6) & BM_PXP_CTRL_RSVD0) +#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020 +#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \ + (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP) +#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010 +#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \ + (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE) +#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 +#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \ + (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE) +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \ + (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE) +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BF_PXP_CTRL_IRQ_ENABLE(v) \ + (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE) +#define BM_PXP_CTRL_ENABLE 0x00000001 +#define BF_PXP_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL_ENABLE) + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_AXI_ERROR_ID_1 12 +#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000 +#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \ + (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1) +#define BM_PXP_STAT_RSVD2 0x00000800 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 11) & BM_PXP_STAT_RSVD2) +#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400 +#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \ + (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1) +#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200 +#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \ + (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1) +#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 +#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \ + (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ) +#define BP_PXP_STAT_AXI_ERROR_ID_0 4 +#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BF_PXP_STAT_NEXT_IRQ(v) \ + (((v) << 3) & BM_PXP_STAT_NEXT_IRQ) +#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004 +#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \ + (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0) +#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002 +#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \ + (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0) +#define BM_PXP_STAT_IRQ0 0x00000001 +#define BF_PXP_STAT_IRQ0(v) \ + (((v) << 0) & BM_PXP_STAT_IRQ0) + +#define HW_PXP_OUT_CTRL (0x00000020) +#define HW_PXP_OUT_CTRL_SET (0x00000024) +#define HW_PXP_OUT_CTRL_CLR (0x00000028) +#define HW_PXP_OUT_CTRL_TOG (0x0000002c) + +#define BP_PXP_OUT_CTRL_ALPHA 24 +#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 +#define BF_PXP_OUT_CTRL_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) +#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 +#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \ + (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT) +#define BP_PXP_OUT_CTRL_RSVD1 10 +#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 +#define BF_PXP_OUT_CTRL_RSVD1(v) \ + (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) +#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 +#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 +#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_OUT_CTRL_RSVD0 5 +#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 +#define BF_PXP_OUT_CTRL_RSVD0(v) \ + (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) +#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B + +#define HW_PXP_OUT_BUF (0x00000030) + +#define BP_PXP_OUT_BUF_ADDR 0 +#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF_ADDR(v) (v) + +#define HW_PXP_OUT_BUF2 (0x00000040) + +#define BP_PXP_OUT_BUF2_ADDR 0 +#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUT_BUF2_ADDR(v) (v) + +#define HW_PXP_OUT_PITCH (0x00000050) + +#define BP_PXP_OUT_PITCH_RSVD 16 +#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_OUT_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) +#define BP_PXP_OUT_PITCH_PITCH 0 +#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF +#define BF_PXP_OUT_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) + +#define HW_PXP_OUT_LRC (0x00000060) + +#define BP_PXP_OUT_LRC_RSVD1 30 +#define BM_PXP_OUT_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) +#define BP_PXP_OUT_LRC_X 16 +#define BM_PXP_OUT_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_LRC_X) +#define BP_PXP_OUT_LRC_RSVD0 14 +#define BM_PXP_OUT_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) +#define BP_PXP_OUT_LRC_Y 0 +#define BM_PXP_OUT_LRC_Y 0x00003FFF +#define BF_PXP_OUT_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_LRC_Y) + +#define HW_PXP_OUT_PS_ULC (0x00000070) + +#define BP_PXP_OUT_PS_ULC_RSVD1 30 +#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) +#define BP_PXP_OUT_PS_ULC_X 16 +#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_ULC_X) +#define BP_PXP_OUT_PS_ULC_RSVD0 14 +#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) +#define BP_PXP_OUT_PS_ULC_Y 0 +#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_PS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) + +#define HW_PXP_OUT_PS_LRC (0x00000080) + +#define BP_PXP_OUT_PS_LRC_RSVD1 30 +#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_PS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) +#define BP_PXP_OUT_PS_LRC_X 16 +#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_PS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_PS_LRC_X) +#define BP_PXP_OUT_PS_LRC_RSVD0 14 +#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_PS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) +#define BP_PXP_OUT_PS_LRC_Y 0 +#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_PS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) + +#define HW_PXP_OUT_AS_ULC (0x00000090) + +#define BP_PXP_OUT_AS_ULC_RSVD1 30 +#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_ULC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) +#define BP_PXP_OUT_AS_ULC_X 16 +#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_ULC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_ULC_X) +#define BP_PXP_OUT_AS_ULC_RSVD0 14 +#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_ULC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) +#define BP_PXP_OUT_AS_ULC_Y 0 +#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF +#define BF_PXP_OUT_AS_ULC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) + +#define HW_PXP_OUT_AS_LRC (0x000000a0) + +#define BP_PXP_OUT_AS_LRC_RSVD1 30 +#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 +#define BF_PXP_OUT_AS_LRC_RSVD1(v) \ + (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) +#define BP_PXP_OUT_AS_LRC_X 16 +#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 +#define BF_PXP_OUT_AS_LRC_X(v) \ + (((v) << 16) & BM_PXP_OUT_AS_LRC_X) +#define BP_PXP_OUT_AS_LRC_RSVD0 14 +#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 +#define BF_PXP_OUT_AS_LRC_RSVD0(v) \ + (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) +#define BP_PXP_OUT_AS_LRC_Y 0 +#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF +#define BF_PXP_OUT_AS_LRC_Y(v) \ + (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) + +#define HW_PXP_PS_CTRL (0x000000b0) +#define HW_PXP_PS_CTRL_SET (0x000000b4) +#define HW_PXP_PS_CTRL_CLR (0x000000b8) +#define HW_PXP_PS_CTRL_TOG (0x000000bc) + +#define BP_PXP_PS_CTRL_RSVD1 12 +#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 +#define BF_PXP_PS_CTRL_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) +#define BP_PXP_PS_CTRL_DECX 10 +#define BM_PXP_PS_CTRL_DECX 0x00000C00 +#define BF_PXP_PS_CTRL_DECX(v) \ + (((v) << 10) & BM_PXP_PS_CTRL_DECX) +#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECX__DECX2 0x1 +#define BV_PXP_PS_CTRL_DECX__DECX4 0x2 +#define BV_PXP_PS_CTRL_DECX__DECX8 0x3 +#define BP_PXP_PS_CTRL_DECY 8 +#define BM_PXP_PS_CTRL_DECY 0x00000300 +#define BF_PXP_PS_CTRL_DECY(v) \ + (((v) << 8) & BM_PXP_PS_CTRL_DECY) +#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 +#define BV_PXP_PS_CTRL_DECY__DECY2 0x1 +#define BV_PXP_PS_CTRL_DECY__DECY4 0x2 +#define BV_PXP_PS_CTRL_DECY__DECY8 0x3 +#define BM_PXP_PS_CTRL_RSVD0 0x00000080 +#define BF_PXP_PS_CTRL_RSVD0(v) \ + (((v) << 7) & BM_PXP_PS_CTRL_RSVD0) +#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040 +#define BF_PXP_PS_CTRL_WB_SWAP(v) \ + (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000003F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 +#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 +#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 +#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 +#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A +#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B +#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E +#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F +#define BV_PXP_PS_CTRL_FORMAT__RGBA888 0x24 + +#define HW_PXP_PS_BUF (0x000000c0) + +#define BP_PXP_PS_BUF_ADDR 0 +#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_BUF_ADDR(v) (v) + +#define HW_PXP_PS_UBUF (0x000000d0) + +#define BP_PXP_PS_UBUF_ADDR 0 +#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_UBUF_ADDR(v) (v) + +#define HW_PXP_PS_VBUF (0x000000e0) + +#define BP_PXP_PS_VBUF_ADDR 0 +#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_PS_VBUF_ADDR(v) (v) + +#define HW_PXP_PS_PITCH (0x000000f0) + +#define BP_PXP_PS_PITCH_RSVD 16 +#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_PS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_PS_PITCH_RSVD) +#define BP_PXP_PS_PITCH_PITCH 0 +#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_PS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_PS_PITCH_PITCH) + +#define HW_PXP_PS_BACKGROUND_0 (0x00000100) + +#define BP_PXP_PS_BACKGROUND_0_RSVD 24 +#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD) +#define BP_PXP_PS_BACKGROUND_0_COLOR 0 +#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BF_PXP_PS_SCALE_RSVD2(v) \ + (((v) << 31) & BM_PXP_PS_SCALE_RSVD2) +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BF_PXP_PS_SCALE_RSVD1(v) \ + (((v) << 15) & BM_PXP_PS_SCALE_RSVD1) +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define BP_PXP_PS_SCALE_OFFSET 12 + +#define HW_PXP_PS_OFFSET (0x00000120) + +#define BP_PXP_PS_OFFSET_RSVD2 28 +#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 +#define BF_PXP_PS_OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) +#define BP_PXP_PS_OFFSET_YOFFSET 16 +#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_PS_OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) +#define BP_PXP_PS_OFFSET_RSVD1 12 +#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_PS_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) +#define BP_PXP_PS_OFFSET_XOFFSET 0 +#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_PS_OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) + +#define HW_PXP_PS_CLRKEYLOW_0 (0x00000130) + +#define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140) + +#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_AS_CTRL (0x00000150) + +#define BP_PXP_AS_CTRL_RSVD1 22 +#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000 +#define BF_PXP_AS_CTRL_RSVD1(v) \ + (((v) << 22) & BM_PXP_AS_CTRL_RSVD1) +#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000 +#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \ + (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT) +#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000 +#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \ + (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT) +#define BP_PXP_AS_CTRL_ROP 16 +#define BM_PXP_AS_CTRL_ROP 0x000F0000 +#define BF_PXP_AS_CTRL_ROP(v) \ + (((v) << 16) & BM_PXP_AS_CTRL_ROP) +#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 +#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 +#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 +#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 +#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 +#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 +#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 +#define BV_PXP_AS_CTRL_ROP__NOT 0x7 +#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 +#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 +#define BV_PXP_AS_CTRL_ROP__XORAS 0xA +#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB +#define BP_PXP_AS_CTRL_ALPHA 8 +#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 +#define BF_PXP_AS_CTRL_ALPHA(v) \ + (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) +#define BP_PXP_AS_CTRL_FORMAT 4 +#define BM_PXP_AS_CTRL_FORMAT 0x000000F0 +#define BF_PXP_AS_CTRL_FORMAT(v) \ + (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) +#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 +#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1 +#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 +#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 +#define BV_PXP_AS_CTRL_FORMAT__RGBA5551 0xA +#define BV_PXP_AS_CTRL_FORMAT__RGBA4444 0xB +#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE +#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 +#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \ + (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY) +#define BP_PXP_AS_CTRL_ALPHA_CTRL 1 +#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 +#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ + (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 +#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 +#define BM_PXP_AS_CTRL_RSVD0 0x00000001 +#define BF_PXP_AS_CTRL_RSVD0(v) \ + (((v) << 0) & BM_PXP_AS_CTRL_RSVD0) + +#define HW_PXP_AS_BUF (0x00000160) + +#define BP_PXP_AS_BUF_ADDR 0 +#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_AS_BUF_ADDR(v) (v) + +#define HW_PXP_AS_PITCH (0x00000170) + +#define BP_PXP_AS_PITCH_RSVD 16 +#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_AS_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_AS_PITCH_RSVD) +#define BP_PXP_AS_PITCH_PITCH 0 +#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF +#define BF_PXP_AS_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_AS_PITCH_PITCH) + +#define HW_PXP_AS_CLRKEYLOW_0 (0x00000180) + +#define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190) + +#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL) + +#define HW_PXP_CSC1_COEF0 (0x000001a0) + +#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 +#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \ + (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE) +#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 +#define BF_PXP_CSC1_COEF0_BYPASS(v) \ + (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS) +#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 +#define BF_PXP_CSC1_COEF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1) +#define BP_PXP_CSC1_COEF0_C0 18 +#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 +#define BF_PXP_CSC1_COEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSC1_COEF0_C0) +#define BP_PXP_CSC1_COEF0_UV_OFFSET 9 +#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) +#define BP_PXP_CSC1_COEF0_Y_OFFSET 0 +#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) + +#define HW_PXP_CSC1_COEF1 (0x000001b0) + +#define BP_PXP_CSC1_COEF1_RSVD1 27 +#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) +#define BP_PXP_CSC1_COEF1_C1 16 +#define BM_PXP_CSC1_COEF1_C1 0x07FF0000 +#define BF_PXP_CSC1_COEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF1_C1) +#define BP_PXP_CSC1_COEF1_RSVD0 11 +#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) +#define BP_PXP_CSC1_COEF1_C4 0 +#define BM_PXP_CSC1_COEF1_C4 0x000007FF +#define BF_PXP_CSC1_COEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF1_C4) + +#define HW_PXP_CSC1_COEF2 (0x000001c0) + +#define BP_PXP_CSC1_COEF2_RSVD1 27 +#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC1_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) +#define BP_PXP_CSC1_COEF2_C2 16 +#define BM_PXP_CSC1_COEF2_C2 0x07FF0000 +#define BF_PXP_CSC1_COEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSC1_COEF2_C2) +#define BP_PXP_CSC1_COEF2_RSVD0 11 +#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC1_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) +#define BP_PXP_CSC1_COEF2_C3 0 +#define BM_PXP_CSC1_COEF2_C3 0x000007FF +#define BF_PXP_CSC1_COEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSC1_COEF2_C3) + +#define HW_PXP_CSC2_CTRL (0x000001d0) + +#define BP_PXP_CSC2_CTRL_RSVD 3 +#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2_CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) +#define BP_PXP_CSC2_CTRL_CSC_MODE 1 +#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) +#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 +#define BF_PXP_CSC2_CTRL_BYPASS(v) \ + (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS) + +#define HW_PXP_CSC2_COEF0 (0x000001e0) + +#define BP_PXP_CSC2_COEF0_RSVD1 27 +#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) +#define BP_PXP_CSC2_COEF0_A2 16 +#define BM_PXP_CSC2_COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2_COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF0_A2) +#define BP_PXP_CSC2_COEF0_RSVD0 11 +#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) +#define BP_PXP_CSC2_COEF0_A1 0 +#define BM_PXP_CSC2_COEF0_A1 0x000007FF +#define BF_PXP_CSC2_COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF0_A1) + +#define HW_PXP_CSC2_COEF1 (0x000001f0) + +#define BP_PXP_CSC2_COEF1_RSVD1 27 +#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) +#define BP_PXP_CSC2_COEF1_B1 16 +#define BM_PXP_CSC2_COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2_COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF1_B1) +#define BP_PXP_CSC2_COEF1_RSVD0 11 +#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) +#define BP_PXP_CSC2_COEF1_A3 0 +#define BM_PXP_CSC2_COEF1_A3 0x000007FF +#define BF_PXP_CSC2_COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF1_A3) + +#define HW_PXP_CSC2_COEF2 (0x00000200) + +#define BP_PXP_CSC2_COEF2_RSVD1 27 +#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) +#define BP_PXP_CSC2_COEF2_B3 16 +#define BM_PXP_CSC2_COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2_COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF2_B3) +#define BP_PXP_CSC2_COEF2_RSVD0 11 +#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) +#define BP_PXP_CSC2_COEF2_B2 0 +#define BM_PXP_CSC2_COEF2_B2 0x000007FF +#define BF_PXP_CSC2_COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF2_B2) + +#define HW_PXP_CSC2_COEF3 (0x00000210) + +#define BP_PXP_CSC2_COEF3_RSVD1 27 +#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2_COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) +#define BP_PXP_CSC2_COEF3_C2 16 +#define BM_PXP_CSC2_COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2_COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF3_C2) +#define BP_PXP_CSC2_COEF3_RSVD0 11 +#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) +#define BP_PXP_CSC2_COEF3_C1 0 +#define BM_PXP_CSC2_COEF3_C1 0x000007FF +#define BF_PXP_CSC2_COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF3_C1) + +#define HW_PXP_CSC2_COEF4 (0x00000220) + +#define BP_PXP_CSC2_COEF4_RSVD1 25 +#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) +#define BP_PXP_CSC2_COEF4_D1 16 +#define BM_PXP_CSC2_COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2_COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF4_D1) +#define BP_PXP_CSC2_COEF4_RSVD0 11 +#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2_COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) +#define BP_PXP_CSC2_COEF4_C3 0 +#define BM_PXP_CSC2_COEF4_C3 0x000007FF +#define BF_PXP_CSC2_COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF4_C3) + +#define HW_PXP_CSC2_COEF5 (0x00000230) + +#define BP_PXP_CSC2_COEF5_RSVD1 25 +#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2_COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) +#define BP_PXP_CSC2_COEF5_D3 16 +#define BM_PXP_CSC2_COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2_COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2_COEF5_D3) +#define BP_PXP_CSC2_COEF5_RSVD0 9 +#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2_COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) +#define BP_PXP_CSC2_COEF5_D2 0 +#define BM_PXP_CSC2_COEF5_D2 0x000001FF +#define BF_PXP_CSC2_COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2_COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000240) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BF_PXP_LUT_CTRL_BYPASS(v) \ + (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS) +#define BP_PXP_LUT_CTRL_RSVD3 26 +#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 +#define BF_PXP_LUT_CTRL_RSVD3(v) \ + (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) +#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 +#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 +#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ + (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 +#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 +#define BP_PXP_LUT_CTRL_RSVD2 18 +#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 +#define BF_PXP_LUT_CTRL_RSVD2(v) \ + (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) +#define BP_PXP_LUT_CTRL_OUT_MODE 16 +#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 +#define BF_PXP_LUT_CTRL_OUT_MODE(v) \ + (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) +#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 +#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 +#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 +#define BP_PXP_LUT_CTRL_RSVD1 11 +#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 +#define BF_PXP_LUT_CTRL_RSVD1(v) \ + (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) +#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 +#define BF_PXP_LUT_CTRL_SEL_8KB(v) \ + (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB) +#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 +#define BF_PXP_LUT_CTRL_LRU_UPD(v) \ + (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD) +#define BM_PXP_LUT_CTRL_INVALID 0x00000100 +#define BF_PXP_LUT_CTRL_INVALID(v) \ + (((v) << 8) & BM_PXP_LUT_CTRL_INVALID) +#define BP_PXP_LUT_CTRL_RSVD0 1 +#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE +#define BF_PXP_LUT_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) +#define BM_PXP_LUT_CTRL_DMA_START 0x00000001 +#define BF_PXP_LUT_CTRL_DMA_START(v) \ + (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START) + +#define HW_PXP_LUT_ADDR (0x00000250) + +#define BM_PXP_LUT_ADDR_RSVD2 0x80000000 +#define BF_PXP_LUT_ADDR_RSVD2(v) \ + (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2) +#define BP_PXP_LUT_ADDR_NUM_BYTES 16 +#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 +#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) +#define BP_PXP_LUT_ADDR_RSVD1 14 +#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 +#define BF_PXP_LUT_ADDR_RSVD1(v) \ + (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) +#define BP_PXP_LUT_ADDR_ADDR 0 +#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF +#define BF_PXP_LUT_ADDR_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) + +#define HW_PXP_LUT_DATA (0x00000260) + +#define BP_PXP_LUT_DATA_DATA 0 +#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF +#define BF_PXP_LUT_DATA_DATA(v) (v) + +#define HW_PXP_LUT_EXTMEM (0x00000270) + +#define BP_PXP_LUT_EXTMEM_ADDR 0 +#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF +#define BF_PXP_LUT_EXTMEM_ADDR(v) (v) + +#define HW_PXP_CFA (0x00000280) + +#define BP_PXP_CFA_DATA 0 +#define BM_PXP_CFA_DATA 0xFFFFFFFF +#define BF_PXP_CFA_DATA(v) (v) + +#define HW_PXP_ALPHA_A_CTRL (0x00000290) + +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_A_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0) +#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0 +#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1) +#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL (0x000002a0) + +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \ + (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \ + (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA) +#define BP_PXP_ALPHA_B_CTRL_RSVD0 14 +#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000 +#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \ + (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0) +#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000 +#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \ + (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000 +#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \ + (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10 +#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 +#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ + (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8 +#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300 +#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080 +#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \ + (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040 +#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \ + (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1 +#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020 +#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \ + (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1 +#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3 +#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 +#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ + (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 +#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 1 +#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006 +#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE) +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2 +#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3 +#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE) +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0 +#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1 + +#define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0) + +#define BP_PXP_ALPHA_B_CTRL_1_RSVD0 8 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00 +#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \ + (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0) +#define BP_PXP_ALPHA_B_CTRL_1_ROP 4 +#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0 +#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \ + (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP) +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9 +#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA +#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB +#define BP_PXP_ALPHA_B_CTRL_1_RSVD1 2 +#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C +#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \ + (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1) +#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002 +#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \ + (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE) +#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001 +#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE) + +#define HW_PXP_PS_BACKGROUND_1 (0x000002c0) + +#define BP_PXP_PS_BACKGROUND_1_RSVD 24 +#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000 +#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \ + (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD) +#define BP_PXP_PS_BACKGROUND_1_COLOR 0 +#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF +#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \ + (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR) + +#define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0) + +#define BP_PXP_PS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0) + +#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0) + +#define BP_PXP_AS_CLRKEYLOW_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1) +#define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL) + +#define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300) + +#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 24 +#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000 +#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \ + (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1) +#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0 +#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF +#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \ + (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL) + +#define HW_PXP_CTRL2 (0x00000310) +#define HW_PXP_CTRL2_SET (0x00000314) +#define HW_PXP_CTRL2_CLR (0x00000318) +#define HW_PXP_CTRL2_TOG (0x0000031c) + +#define BP_PXP_CTRL2_RSVD3 28 +#define BM_PXP_CTRL2_RSVD3 0xF0000000 +#define BF_PXP_CTRL2_RSVD3(v) \ + (((v) << 28) & BM_PXP_CTRL2_RSVD3) +#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \ + (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1) +#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000 +#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \ + (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0) +#define BM_PXP_CTRL2_ENABLE_LUT 0x02000000 +#define BF_PXP_CTRL2_ENABLE_LUT(v) \ + (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT) +#define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000 +#define BF_PXP_CTRL2_ENABLE_CSC2(v) \ + (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2) +#define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000 +#define BF_PXP_CTRL2_BLOCK_SIZE(v) \ + (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE) +#define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL2_RSVD2 0x00400000 +#define BF_PXP_CTRL2_RSVD2(v) \ + (((v) << 22) & BM_PXP_CTRL2_RSVD2) +#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000 +#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \ + (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B) +#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000 +#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \ + (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE) +#define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000 +#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \ + (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B) +#define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000 +#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \ + (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A) +#define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000 +#define BF_PXP_CTRL2_ENABLE_DITHER(v) \ + (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER) +#define BM_PXP_CTRL2_RSVD1 0x00010000 +#define BF_PXP_CTRL2_RSVD1(v) \ + (((v) << 16) & BM_PXP_CTRL2_RSVD1) +#define BM_PXP_CTRL2_VFLIP1 0x00008000 +#define BF_PXP_CTRL2_VFLIP1(v) \ + (((v) << 15) & BM_PXP_CTRL2_VFLIP1) +#define BM_PXP_CTRL2_HFLIP1 0x00004000 +#define BF_PXP_CTRL2_HFLIP1(v) \ + (((v) << 14) & BM_PXP_CTRL2_HFLIP1) +#define BP_PXP_CTRL2_ROTATE1 12 +#define BM_PXP_CTRL2_ROTATE1 0x00003000 +#define BF_PXP_CTRL2_ROTATE1(v) \ + (((v) << 12) & BM_PXP_CTRL2_ROTATE1) +#define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3 +#define BM_PXP_CTRL2_VFLIP0 0x00000800 +#define BF_PXP_CTRL2_VFLIP0(v) \ + (((v) << 11) & BM_PXP_CTRL2_VFLIP0) +#define BM_PXP_CTRL2_HFLIP0 0x00000400 +#define BF_PXP_CTRL2_HFLIP0(v) \ + (((v) << 10) & BM_PXP_CTRL2_HFLIP0) +#define BP_PXP_CTRL2_ROTATE0 8 +#define BM_PXP_CTRL2_ROTATE0 0x00000300 +#define BF_PXP_CTRL2_ROTATE0(v) \ + (((v) << 8) & BM_PXP_CTRL2_ROTATE0) +#define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0 +#define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1 +#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2 +#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3 +#define BP_PXP_CTRL2_RSVD0 1 +#define BM_PXP_CTRL2_RSVD0 0x000000FE +#define BF_PXP_CTRL2_RSVD0(v) \ + (((v) << 1) & BM_PXP_CTRL2_RSVD0) +#define BM_PXP_CTRL2_ENABLE 0x00000001 +#define BF_PXP_CTRL2_ENABLE(v) \ + (((v) << 0) & BM_PXP_CTRL2_ENABLE) + +#define HW_PXP_POWER_REG0 (0x00000320) + +#define BP_PXP_POWER_REG0_CTRL 12 +#define BM_PXP_POWER_REG0_CTRL 0xFFFFF000 +#define BF_PXP_POWER_REG0_CTRL(v) \ + (((v) << 12) & BM_PXP_POWER_REG0_CTRL) +#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE) +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 6 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \ + (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 3 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \ + (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4 +#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0 +#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007 +#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \ + (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0) +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2 +#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4 + +#define HW_PXP_POWER_REG1 (0x00000330) + +#define BP_PXP_POWER_REG1_RSVD0 24 +#define BM_PXP_POWER_REG1_RSVD0 0xFF000000 +#define BF_PXP_POWER_REG1_RSVD0(v) \ + (((v) << 24) & BM_PXP_POWER_REG1_RSVD0) +#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 21 +#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000 +#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \ + (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 18 +#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000 +#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \ + (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 15 +#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000 +#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \ + (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 12 +#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000 +#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \ + (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 9 +#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00 +#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \ + (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 6 +#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0 +#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \ + (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 3 +#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038 +#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \ + (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4 +#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0 +#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007 +#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \ + (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE) +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2 +#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4 + +#define HW_PXP_DATA_PATH_CTRL0 (0x00000340) +#define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344) +#define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348) +#define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c) + +#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 30 +#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \ + (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 28 +#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \ + (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 26 +#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \ + (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 24 +#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000 +#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \ + (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 22 +#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000 +#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \ + (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 20 +#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000 +#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \ + (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 18 +#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000 +#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \ + (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 16 +#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000 +#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \ + (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 14 +#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000 +#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \ + (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 12 +#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000 +#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \ + (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 10 +#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00 +#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \ + (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 8 +#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300 +#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \ + (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 6 +#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0 +#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \ + (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 4 +#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030 +#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 2 +#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0 +#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL) +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3 + +#define HW_PXP_DATA_PATH_CTRL1 (0x00000350) +#define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354) +#define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358) +#define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c) + +#define BP_PXP_DATA_PATH_CTRL1_RSVD0 4 +#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0 +#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \ + (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0) +#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 2 +#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C +#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \ + (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3 +#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0 +#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003 +#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \ + (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL) +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2 +#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3 + +#define HW_PXP_INIT_MEM_CTRL (0x00000360) +#define HW_PXP_INIT_MEM_CTRL_SET (0x00000364) +#define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368) +#define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c) + +#define BM_PXP_INIT_MEM_CTRL_START 0x80000000 +#define BF_PXP_INIT_MEM_CTRL_START(v) \ + (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START) +#define BP_PXP_INIT_MEM_CTRL_SELECT 27 +#define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000 +#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \ + (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT) +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3 +#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5 +#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7 +#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8 +#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15 +#define BP_PXP_INIT_MEM_CTRL_RSVD0 16 +#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000 +#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \ + (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0) +#define BP_PXP_INIT_MEM_CTRL_ADDR 0 +#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF +#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \ + (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR) + +#define HW_PXP_INIT_MEM_DATA (0x00000370) + +#define BP_PXP_INIT_MEM_DATA_DATA 0 +#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_DATA(v) (v) + +#define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380) + +#define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0 +#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF +#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v) + +#define HW_PXP_IRQ_MASK (0x00000390) +#define HW_PXP_IRQ_MASK_SET (0x00000394) +#define HW_PXP_IRQ_MASK_CLR (0x00000398) +#define HW_PXP_IRQ_MASK_TOG (0x0000039c) + +#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000 +#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN) +#define BP_PXP_IRQ_MASK_RSVD1 16 +#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_MASK_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1) +#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000 +#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \ + (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000 +#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \ + (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000 +#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \ + (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000 +#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \ + (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800 +#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \ + (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400 +#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \ + (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200 +#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \ + (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100 +#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \ + (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080 +#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \ + (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040 +#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \ + (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020 +#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010 +#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008 +#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \ + (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004 +#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \ + (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002 +#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \ + (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN) +#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001 +#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \ + (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN) + +#define HW_PXP_IRQ (0x000003a0) +#define HW_PXP_IRQ_SET (0x000003a4) +#define HW_PXP_IRQ_CLR (0x000003a8) +#define HW_PXP_IRQ_TOG (0x000003ac) + +#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000 +#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \ + (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ) +#define BP_PXP_IRQ_RSVD1 16 +#define BM_PXP_IRQ_RSVD1 0x7FFF0000 +#define BF_PXP_IRQ_RSVD1(v) \ + (((v) << 16) & BM_PXP_IRQ_RSVD1) +#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000 +#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \ + (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000 +#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \ + (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000 +#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \ + (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000 +#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \ + (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800 +#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \ + (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400 +#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \ + (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200 +#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \ + (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) +#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100 +#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \ + (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080 +#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \ + (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040 +#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \ + (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) +#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020 +#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \ + (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010 +#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \ + (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008 +#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \ + (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004 +#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \ + (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) +#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002 +#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \ + (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) +#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001 +#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \ + (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) + +#define HW_PXP_NEXT (0x00000400) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BF_PXP_NEXT_RSVD(v) \ + (((v) << 1) & BM_PXP_NEXT_RSVD) +#define BM_PXP_NEXT_ENABLED 0x00000001 +#define BF_PXP_NEXT_ENABLED(v) \ + (((v) << 0) & BM_PXP_NEXT_ENABLED) + +#define HW_PXP_DEBUGCTRL (0x00000410) + +#define BP_PXP_DEBUGCTRL_RSVD 12 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 +#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 +#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 +#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 +#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 + +#define HW_PXP_DEBUG (0x00000420) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x00000430) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +#define HW_PXP_INPUT_FETCH_CTRL_CH0 (0x00000450) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_SET (0x00000454) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_CLR (0x00000458) +#define HW_PXP_INPUT_FETCH_CTRL_CH0_TOG (0x0000045c) + +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_INPUT_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_CTRL_CH1 (0x00000460) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_SET (0x00000464) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_CLR (0x00000468) +#define HW_PXP_INPUT_FETCH_CTRL_CH1_TOG (0x0000046c) + +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_INPUT_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_INPUT_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_FETCH_STATUS_CH0 (0x00000470) + +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_STATUS_CH1 (0x00000480) + +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000490) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000004a0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000004b0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000004c0) + +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_INPUT_FETCH_SIZE_CH0 (0x000004d0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_SIZE_CH1 (0x000004e0) + +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 (0x000004f0) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 (0x00000500) + +#define BP_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_INPUT_FETCH_PITCH (0x00000510) + +#define BP_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 (0x00000520) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SET (0x00000524) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_CLR (0x00000528) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_TOG (0x0000052c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 (0x00000530) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SET (0x00000534) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_CLR (0x00000538) +#define HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_TOG (0x0000053c) + +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 (0x00000540) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_SET (0x00000544) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000548) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000054c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 (0x00000550) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_SET (0x00000554) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000558) +#define HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000055c) + +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 (0x00000560) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_SET (0x00000564) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000568) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000056c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 (0x00000570) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_SET (0x00000574) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000578) +#define HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000057c) + +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH0 (0x00000580) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH0 (0x00000590) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_0_CH1 (0x000005a0) + +#define BP_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_FETCH_ADDR_1_CH1 (0x000005b0) + +#define BP_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_CTRL_CH0 (0x000005c0) +#define HW_PXP_INPUT_STORE_CTRL_CH0_SET (0x000005c4) +#define HW_PXP_INPUT_STORE_CTRL_CH0_CLR (0x000005c8) +#define HW_PXP_INPUT_STORE_CTRL_CH0_TOG (0x000005cc) + +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_CTRL_CH1 (0x000005d0) +#define HW_PXP_INPUT_STORE_CTRL_CH1_SET (0x000005d4) +#define HW_PXP_INPUT_STORE_CTRL_CH1_CLR (0x000005d8) +#define HW_PXP_INPUT_STORE_CTRL_CH1_TOG (0x000005dc) + +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_INPUT_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_INPUT_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_INPUT_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_INPUT_STORE_STATUS_CH0 (0x000005e0) + +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_STATUS_CH1 (0x000005f0) + +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_INPUT_STORE_SIZE_CH0 (0x00000600) + +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_SIZE_CH1 (0x00000610) + +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_INPUT_STORE_PITCH (0x00000620) + +#define BP_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 (0x00000630) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SET (0x00000634) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_CLR (0x00000638) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_TOG (0x0000063c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 (0x00000640) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_SET (0x00000644) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_CLR (0x00000648) +#define HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_TOG (0x0000064c) + +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH0 (0x00000690) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH0 (0x000006a0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_FILL_DATA_CH0 (0x000006b0) + +#define BP_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_0_CH1 (0x000006c0) + +#define BP_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_INPUT_STORE_ADDR_1_CH1 (0x000006d0) + +#define BP_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_H_CH0 (0x000006e0) + +#define BP_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK0_L_CH0 (0x000006f0) + +#define BP_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_H_CH0 (0x00000700) + +#define BP_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK1_L_CH0 (0x00000710) + +#define BP_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_H_CH0 (0x00000720) + +#define BP_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK2_L_CH0 (0x00000730) + +#define BP_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_H_CH0 (0x00000740) + +#define BP_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK3_L_CH0 (0x00000750) + +#define BP_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_H_CH0 (0x00000760) + +#define BP_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK4_L_CH0 (0x00000770) + +#define BP_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_H_CH0 (0x00000780) + +#define BP_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK5_L_CH0 (0x00000790) + +#define BP_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_H_CH0 (0x000007a0) + +#define BP_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK6_L_CH0 (0x000007b0) + +#define BP_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_H_CH0 (0x000007c0) + +#define BP_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_MASK7_L_CH0 (0x000007e0) + +#define BP_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 (0x000007f0) + +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 (0x00000800) + +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 (0x00000810) + +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 (0x00000820) + +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_INPUT_STORE_F_MASK_L_CH0 (0x00000830) + +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_INPUT_STORE_F_MASK_H_CH0 (0x00000840) + +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_DITHER_FETCH_CTRL_CH0 (0x00000850) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_SET (0x00000854) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_CLR (0x00000858) +#define HW_PXP_DITHER_FETCH_CTRL_CH0_TOG (0x0000085c) + +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0 0x7C000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH0_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH0_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 6 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4 0x000001C0 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_RSVD4(v) \ + (((v) << 6) & BM_PXP_DITHER_FETCH_CTRL_CH0_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE 0x00000020 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_CTRL_CH1 (0x00000860) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_SET (0x00000864) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_CLR (0x00000868) +#define HW_PXP_DITHER_FETCH_CTRL_CH1_TOG (0x0000086c) + +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 26 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0 0xFC000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD0(v) \ + (((v) << 26) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 24 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM 0x03000000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM__3 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 18 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 16 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 14 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2 0x0000C000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 12 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE 0x00003000 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_90 0x1 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_180 0x2 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE__ROT_270 0x3 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3 0x00000800 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD3(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD3) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP 0x00000400 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_VFLIP(v) \ + (((v) << 10) & BM_PXP_DITHER_FETCH_CTRL_CH1_VFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_VFLIP__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP 0x00000200 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HFLIP(v) \ + (((v) << 9) & BM_PXP_DITHER_FETCH_CTRL_CH1_HFLIP) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HFLIP__1 0x1 +#define BP_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 5 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4 0x000001E0 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_RSVD4(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_CTRL_CH1_RSVD4) +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN 0x00000010 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_FETCH_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_FETCH_STATUS_CH0 (0x00000870) + +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_STATUS_CH1 (0x00000880) + +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 16 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y) +#define BP_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0 +#define BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 (0x00000890) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 (0x000008a0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 (0x000008b0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X) + +#define HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 (0x000008c0) + +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 16 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y) +#define BP_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0 +#define BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X 0x0000FFFF +#define BF_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X) + +#define HW_PXP_DITHER_FETCH_SIZE_CH0 (0x000008d0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_SIZE_CH1 (0x000008e0) + +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 16 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT) +#define BP_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0 +#define BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 (0x000008f0) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 (0x00000900) + +#define BP_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0 +#define BM_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(v) (v) + +#define HW_PXP_DITHER_FETCH_PITCH (0x00000910) + +#define BP_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 16 +#define BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH) +#define BP_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0 +#define BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH) + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 (0x00000920) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SET (0x00000924) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_CLR (0x00000928) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_TOG (0x0000092c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 (0x00000930) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SET (0x00000934) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_CLR (0x00000938) +#define HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_TOG (0x0000093c) + +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 13 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0 0xFFFFE000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS 0x00001000 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN 0x00000800 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN__1 0x1 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 8 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT 0x00000700 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__3 0x3 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__4 0x4 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__5 0x5 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__6 0x6 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT__7 0x7 +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 2 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1 0x000000FC +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(v) \ + (((v) << 2) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0 +#define BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP 0x00000003 +#define BF_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP__3 0x3 + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 (0x00000940) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_SET (0x00000944) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_CLR (0x00000948) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_TOG (0x0000094c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 (0x00000950) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_SET (0x00000954) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_CLR (0x00000958) +#define HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_TOG (0x0000095c) + +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 29 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0 0xE0000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(v) \ + (((v) << 29) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 24 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3 0x1F000000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(v) \ + (((v) << 24) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 21 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1 0x00E00000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(v) \ + (((v) << 21) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 16 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2 0x001F0000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 13 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2 0x0000E000 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(v) \ + (((v) << 13) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 8 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1 0x00001F00 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 5 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3 0x000000E0 +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(v) \ + (((v) << 5) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3) +#define BP_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0 0x0000001F +#define BF_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 (0x00000960) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_SET (0x00000964) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_CLR (0x00000968) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_TOG (0x0000096c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0) + +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 (0x00000970) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_SET (0x00000974) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_CLR (0x00000978) +#define HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_TOG (0x0000097c) + +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 16 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0 0xFFFF0000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(v) \ + (((v) << 16) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 12 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3 0x0000F000 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(v) \ + (((v) << 12) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 8 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2 0x00000F00 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(v) \ + (((v) << 8) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 4 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1 0x000000F0 +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(v) \ + (((v) << 4) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1) +#define BP_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0 +#define BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0 0x0000000F +#define BF_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH0 (0x00000980) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH0 (0x00000990) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_0_CH1 (0x000009a0) + +#define BP_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_FETCH_ADDR_1_CH1 (0x000009b0) + +#define BP_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_CTRL_CH0 (0x000009c0) +#define HW_PXP_DITHER_STORE_CTRL_CH0_SET (0x000009c4) +#define HW_PXP_DITHER_STORE_CTRL_CH0_CLR (0x000009c8) +#define HW_PXP_DITHER_STORE_CTRL_CH0_TOG (0x000009cc) + +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_CTRL_CH1 (0x000009d0) +#define HW_PXP_DITHER_STORE_CTRL_CH1_SET (0x000009d4) +#define HW_PXP_DITHER_STORE_CTRL_CH1_CLR (0x000009d8) +#define HW_PXP_DITHER_STORE_CTRL_CH1_TOG (0x000009dc) + +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_DITHER_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_DITHER_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_DITHER_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_DITHER_STORE_STATUS_CH0 (0x000009e0) + +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_STATUS_CH1 (0x000009f0) + +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_DITHER_STORE_SIZE_CH0 (0x00000a00) + +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_SIZE_CH1 (0x00000a10) + +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_DITHER_STORE_PITCH (0x00000a20) + +#define BP_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 (0x00000a30) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SET (0x00000a34) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_CLR (0x00000a38) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_TOG (0x00000a3c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 (0x00000a40) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_SET (0x00000a44) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_CLR (0x00000a48) +#define HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_TOG (0x00000a4c) + +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH0 (0x00000a90) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH0 (0x00000aa0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_FILL_DATA_CH0 (0x00000ab0) + +#define BP_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_0_CH1 (0x00000ac0) + +#define BP_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_DITHER_STORE_ADDR_1_CH1 (0x00000ad0) + +#define BP_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_H_CH0 (0x00000ae0) + +#define BP_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK0_L_CH0 (0x00000af0) + +#define BP_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_H_CH0 (0x00000b00) + +#define BP_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK1_L_CH0 (0x00000b10) + +#define BP_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_H_CH0 (0x00000b20) + +#define BP_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK2_L_CH0 (0x00000b30) + +#define BP_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_H_CH0 (0x00000b40) + +#define BP_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK3_L_CH0 (0x00000b50) + +#define BP_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_H_CH0 (0x00000b60) + +#define BP_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK4_L_CH0 (0x00000b70) + +#define BP_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_H_CH0 (0x00000b80) + +#define BP_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK5_L_CH0 (0x00000b90) + +#define BP_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_H_CH0 (0x00000ba0) + +#define BP_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK6_L_CH0 (0x00000bb0) + +#define BP_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_H_CH0 (0x00000bc0) + +#define BP_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_MASK7_L_CH0 (0x00000bd0) + +#define BP_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 (0x00000be0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 (0x00000bf0) + +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 (0x00000c00) + +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 (0x00000c10) + +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_DITHER_STORE_F_MASK_L_CH0 (0x00000c20) + +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_DITHER_STORE_F_MASK_H_CH0 (0x00000c30) + +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFA_FETCH_CTRL (0x00000c40) +#define HW_PXP_WFA_FETCH_CTRL_SET (0x00000c44) +#define HW_PXP_WFA_FETCH_CTRL_CLR (0x00000c48) +#define HW_PXP_WFA_FETCH_CTRL_TOG (0x00000c4c) + +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFA_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFA_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFA_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFA_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFA_FETCH_CTRL_RSVD0) +#define BP_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFA_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFA_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFA_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFA_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_CTRL_RSVD1) +#define BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFA_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFA_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFA_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFA_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFA_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFA_FETCH_CTRL_RSVD2) +#define BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFA_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFA_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFA_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFA_FETCH_BUF1_ADDR (0x00000c50) + +#define BP_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF1_PITCH (0x00000c60) + +#define BP_PXP_WFA_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF1_SIZE (0x00000c70) + +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_FETCH_BUF2_ADDR (0x00000c80) + +#define BP_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFA_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFA_FETCH_BUF2_PITCH (0x00000c90) + +#define BP_PXP_WFA_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFA_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFA_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFA_FETCH_BUF2_SIZE (0x00000ca0) + +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_SIZE_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_SIZE_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFA_ARRAY_PIXEL0_MASK (0x00000cb0) + +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL1_MASK (0x00000cc0) + +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL2_MASK (0x00000cd0) + +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL3_MASK (0x00000ce0) + +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL4_MASK (0x00000cf0) + +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL5_MASK (0x00000d00) + +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL6_MASK (0x00000d10) + +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_PIXEL7_MASK (0x00000d20) + +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG0_MASK (0x00000d30) + +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG1_MASK (0x00000d40) + +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG2_MASK (0x00000d50) + +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG3_MASK (0x00000d60) + +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG4_MASK (0x00000d70) + +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG5_MASK (0x00000d80) + +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG6_MASK (0x00000d90) + +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG7_MASK (0x00000da0) + +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFA_FETCH_BUF1_CORD (0x00000db0) + +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFA_FETCH_BUF2_CORD (0x00000dc0) + +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFA_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFA_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFA_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFA_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFA_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFA_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFA_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFA_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFA_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFA_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFA_ARRAY_FLAG8_MASK (0x00000dd0) + +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG9_MASK (0x00000de0) + +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG10_MASK (0x00000df0) + +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG11_MASK (0x00000e00) + +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG12_MASK (0x00000e10) + +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG13_MASK (0x00000e20) + +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG14_MASK (0x00000e30) + +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_FLAG15_MASK (0x00000e40) + +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFA_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFA_ARRAY_REG0 (0x00000e50) + +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFA_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFA_ARRAY_REG1 (0x00000e60) + +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFA_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFA_ARRAY_REG2 (0x00000e70) + +#define BP_PXP_WFA_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFA_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFA_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFA_ARRAY_REG2_RSVD0) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFA_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFA_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFA_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_A_STORE_CTRL_CH0 (0x00000e80) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_SET (0x00000e84) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_CLR (0x00000e88) +#define HW_PXP_WFE_A_STORE_CTRL_CH0_TOG (0x00000e8c) + +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_CTRL_CH1 (0x00000e90) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_SET (0x00000e94) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_CLR (0x00000e98) +#define HW_PXP_WFE_A_STORE_CTRL_CH1_TOG (0x00000e9c) + +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_A_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_A_STORE_STATUS_CH0 (0x00000ea0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_STATUS_CH1 (0x00000eb0) + +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_A_STORE_SIZE_CH0 (0x00000ec0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_SIZE_CH1 (0x00000ed0) + +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_A_STORE_PITCH (0x00000ee0) + +#define BP_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0 (0x00000ef0) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SET (0x00000ef4) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_CLR (0x00000ef8) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_TOG (0x00000efc) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1 (0x00000f00) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_SET (0x00000f04) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_CLR (0x00000f08) +#define HW_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_TOG (0x00000f0c) + +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH0 (0x00000f50) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH0 (0x00000f60) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_FILL_DATA_CH0 (0x00000f70) + +#define BP_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_0_CH1 (0x00000f80) + +#define BP_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_A_STORE_ADDR_1_CH1 (0x00000f90) + +#define BP_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_H_CH0 (0x00000fa0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK0_L_CH0 (0x00000fb0) + +#define BP_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_H_CH0 (0x00000fc0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK1_L_CH0 (0x00000fd0) + +#define BP_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_H_CH0 (0x00000fe0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK2_L_CH0 (0x00000ff0) + +#define BP_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_H_CH0 (0x00001000) + +#define BP_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK3_L_CH0 (0x00001010) + +#define BP_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_H_CH0 (0x00001020) + +#define BP_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK4_L_CH0 (0x00001030) + +#define BP_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_H_CH0 (0x00001040) + +#define BP_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK5_L_CH0 (0x00001050) + +#define BP_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_H_CH0 (0x00001060) + +#define BP_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK6_L_CH0 (0x00001070) + +#define BP_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_H_CH0 (0x00001080) + +#define BP_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_MASK7_L_CH0 (0x00001090) + +#define BP_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_A_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_L_CH0 (0x000010a0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_D_SHIFT_H_CH0 (0x000010b0) + +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_L_CH0 (0x000010c0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_A_STORE_F_SHIFT_H_CH0 (0x000010d0) + +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_A_STORE_F_MASK_L_CH0 (0x000010e0) + +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_A_STORE_F_MASK_H_CH0 (0x000010f0) + +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_WFB_FETCH_CTRL (0x00001100) +#define HW_PXP_WFB_FETCH_CTRL_SET (0x00001104) +#define HW_PXP_WFB_FETCH_CTRL_CLR (0x00001108) +#define HW_PXP_WFB_FETCH_CTRL_TOG (0x0000110c) + +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN 0x80000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(v) \ + (((v) << 31) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN 0x40000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN) +#define BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ 0x20000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(v) \ + (((v) << 29) & BM_PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ) +#define BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ 0x10000000 +#define BF_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(v) \ + (((v) << 28) & BM_PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ) +#define BP_PXP_WFB_FETCH_CTRL_RSVD0 24 +#define BM_PXP_WFB_FETCH_CTRL_RSVD0 0x0F000000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFB_FETCH_CTRL_RSVD0) +#define BP_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 22 +#define BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE 0x00C00000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(v) \ + (((v) << 22) & BM_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF2_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 20 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP 0x00300000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(v) \ + (((v) << 20) & BM_PXP_WFB_FETCH_CTRL_BF2_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 18 +#define BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE 0x000C0000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(v) \ + (((v) << 18) & BM_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__1 0x1 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__2 0x2 +#define BV_PXP_WFB_FETCH_CTRL_BF1_LINE_MODE__3 0x3 +#define BP_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 16 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP 0x00030000 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_CTRL_BF1_BYTES_PP) +#define BP_PXP_WFB_FETCH_CTRL_RSVD1 14 +#define BM_PXP_WFB_FETCH_CTRL_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_CTRL_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_CTRL_RSVD1) +#define BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE 0x00002000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(v) \ + (((v) << 13) & BM_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN 0x00001000 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(v) \ + (((v) << 12) & BM_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE 0x00000800 +#define BF_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(v) \ + (((v) << 11) & BM_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE 0x00000400 +#define BF_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(v) \ + (((v) << 10) & BM_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF 0x00000200 +#define BF_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(v) \ + (((v) << 9) & BM_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF2_EN 0x00000100 +#define BF_PXP_WFB_FETCH_CTRL_BF2_EN(v) \ + (((v) << 8) & BM_PXP_WFB_FETCH_CTRL_BF2_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF2_EN__1 0x1 +#define BP_PXP_WFB_FETCH_CTRL_RSVD2 6 +#define BM_PXP_WFB_FETCH_CTRL_RSVD2 0x000000C0 +#define BF_PXP_WFB_FETCH_CTRL_RSVD2(v) \ + (((v) << 6) & BM_PXP_WFB_FETCH_CTRL_RSVD2) +#define BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE 0x00000020 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(v) \ + (((v) << 5) & BM_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN 0x00000010 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(v) \ + (((v) << 4) & BM_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BURST_LEN__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE 0x00000008 +#define BF_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(v) \ + (((v) << 3) & BM_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE 0x00000004 +#define BF_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(v) \ + (((v) << 2) & BM_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE) +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_HSK_MODE__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF 0x00000002 +#define BF_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(v) \ + (((v) << 1) & BM_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF) +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_SRAM_IF__1 0x1 +#define BM_PXP_WFB_FETCH_CTRL_BF1_EN 0x00000001 +#define BF_PXP_WFB_FETCH_CTRL_BF1_EN(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_CTRL_BF1_EN) +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__0 0x0 +#define BV_PXP_WFB_FETCH_CTRL_BF1_EN__1 0x1 + +#define HW_PXP_WFB_FETCH_BUF1_ADDR (0x00001110) + +#define BP_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF1_PITCH (0x00001120) + +#define BP_PXP_WFB_FETCH_BUF1_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF1_SIZE (0x00001130) + +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_FETCH_BUF2_ADDR (0x00001140) + +#define BP_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0 +#define BM_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(v) (v) + +#define HW_PXP_WFB_FETCH_BUF2_PITCH (0x00001150) + +#define BP_PXP_WFB_FETCH_BUF2_PITCH_RSVD 16 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_PITCH_RSVD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_PITCH_RSVD) +#define BP_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0 +#define BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_PITCH_PITCH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_PITCH_PITCH) + +#define HW_PXP_WFB_FETCH_BUF2_SIZE (0x00001160) + +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 16 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT 0xFFFF0000 +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT) +#define BP_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0 +#define BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH 0x0000FFFF +#define BF_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH) + +#define HW_PXP_WFB_ARRAY_PIXEL0_MASK (0x00001170) + +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL1_MASK (0x00001180) + +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL2_MASK (0x00001190) + +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL3_MASK (0x000011a0) + +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL4_MASK (0x000011b0) + +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL5_MASK (0x000011c0) + +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL6_MASK (0x000011d0) + +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_PIXEL7_MASK (0x000011e0) + +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG0_MASK (0x000011f0) + +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG0_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG0_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG0_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG1_MASK (0x00001200) + +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG1_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG1_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG1_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG2_MASK (0x00001210) + +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG2_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG2_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG2_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG3_MASK (0x00001220) + +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG3_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG3_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG3_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG4_MASK (0x00001230) + +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG4_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG4_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG4_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG5_MASK (0x00001240) + +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG5_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG5_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG5_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG6_MASK (0x00001250) + +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG6_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG6_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG6_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG7_MASK (0x00001260) + +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG7_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG7_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG7_MASK_L_OFS) + +#define HW_PXP_WFB_FETCH_BUF1_CORD (0x00001270) + +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF1_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF1_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF1_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF1_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF1_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF1_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF1_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF1_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF1_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF1_CORD_XCORD) + +#define HW_PXP_WFB_FETCH_BUF2_CORD (0x00001280) + +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD0 30 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0 0xC0000000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD0) +#define BP_PXP_WFB_FETCH_BUF2_CORD_YCORD 16 +#define BM_PXP_WFB_FETCH_BUF2_CORD_YCORD 0x3FFF0000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_YCORD(v) \ + (((v) << 16) & BM_PXP_WFB_FETCH_BUF2_CORD_YCORD) +#define BP_PXP_WFB_FETCH_BUF2_CORD_RSVD1 14 +#define BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1 0x0000C000 +#define BF_PXP_WFB_FETCH_BUF2_CORD_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFB_FETCH_BUF2_CORD_RSVD1) +#define BP_PXP_WFB_FETCH_BUF2_CORD_XCORD 0 +#define BM_PXP_WFB_FETCH_BUF2_CORD_XCORD 0x00003FFF +#define BF_PXP_WFB_FETCH_BUF2_CORD_XCORD(v) \ + (((v) << 0) & BM_PXP_WFB_FETCH_BUF2_CORD_XCORD) + +#define HW_PXP_WFB_ARRAY_FLAG8_MASK (0x00001290) + +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG8_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG8_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG8_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG9_MASK (0x000012a0) + +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG9_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG9_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG9_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG10_MASK (0x000012b0) + +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG10_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG10_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG10_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG11_MASK (0x000012c0) + +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG11_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG11_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG11_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG12_MASK (0x000012d0) + +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG12_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG12_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG12_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG13_MASK (0x000012e0) + +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG13_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG13_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG13_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG14_MASK (0x000012f0) + +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG14_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG14_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG14_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_FLAG15_MASK (0x00001300) + +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 30 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0 0xC0000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD0) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 28 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL 0x30000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__1 0x1 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL__2 0x2 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 26 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1 0x0C000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1(v) \ + (((v) << 26) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD1) +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y 0x02000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(v) \ + (((v) << 25) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y__1 0x1 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X 0x01000000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X) +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__0 0x0 +#define BV_PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X__1 0x1 +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 22 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2 0x00C00000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD2) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 20 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y 0x00300000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(v) \ + (((v) << 20) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 18 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3 0x000C0000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3(v) \ + (((v) << 18) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD3) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 16 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X 0x00030000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 13 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4 0x0000E000 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD4) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 8 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS 0x00001F00 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_FLAG15_MASK_H_OFS) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 5 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5 0x000000E0 +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_FLAG15_MASK_RSVD5) +#define BP_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0 +#define BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS 0x0000001F +#define BF_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_FLAG15_MASK_L_OFS) + +#define HW_PXP_WFB_ARRAY_REG0 (0x00001310) + +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE3 24 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE3(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE3) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE2 16 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE2(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE2) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE1 8 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE1(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE1) +#define BP_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0 +#define BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0 0x000000FF +#define BF_PXP_WFB_ARRAY_REG0_SW_PIXLE0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG0_SW_PIXLE0) + +#define HW_PXP_WFB_ARRAY_REG1 (0x00001320) + +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE7 24 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7 0xFF000000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE7(v) \ + (((v) << 24) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE7) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE6 16 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6 0x00FF0000 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE6(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE6) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE5 8 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5 0x0000FF00 +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE5(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE5) +#define BP_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0 +#define BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4 0x000000FF +#define BF_PXP_WFB_ARRAY_REG1_SW_PIXLE4(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG1_SW_PIXLE4) + +#define HW_PXP_WFB_ARRAY_REG2 (0x00001330) + +#define BP_PXP_WFB_ARRAY_REG2_RSVD0 16 +#define BM_PXP_WFB_ARRAY_REG2_RSVD0 0xFFFF0000 +#define BF_PXP_WFB_ARRAY_REG2_RSVD0(v) \ + (((v) << 16) & BM_PXP_WFB_ARRAY_REG2_RSVD0) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG15 0x00008000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG15(v) \ + (((v) << 15) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG15) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG14 0x00004000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG14(v) \ + (((v) << 14) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG14) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG13 0x00002000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG13(v) \ + (((v) << 13) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG13) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG12 0x00001000 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG12(v) \ + (((v) << 12) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG12) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG11 0x00000800 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG11(v) \ + (((v) << 11) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG11) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG10 0x00000400 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG10(v) \ + (((v) << 10) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG10) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG9 0x00000200 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG9(v) \ + (((v) << 9) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG9) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG8 0x00000100 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG8(v) \ + (((v) << 8) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG8) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG7 0x00000080 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG7(v) \ + (((v) << 7) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG7) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG6 0x00000040 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG6(v) \ + (((v) << 6) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG6) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG5 0x00000020 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG5(v) \ + (((v) << 5) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG5) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG4 0x00000010 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG4(v) \ + (((v) << 4) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG4) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG3 0x00000008 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG3(v) \ + (((v) << 3) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG3) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG2 0x00000004 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG2(v) \ + (((v) << 2) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG2) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG1 0x00000002 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG1(v) \ + (((v) << 1) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG1) +#define BM_PXP_WFB_ARRAY_REG2_SW_FLAG0 0x00000001 +#define BF_PXP_WFB_ARRAY_REG2_SW_FLAG0(v) \ + (((v) << 0) & BM_PXP_WFB_ARRAY_REG2_SW_FLAG0) + +#define HW_PXP_WFE_B_STORE_CTRL_CH0 (0x00001340) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_SET (0x00001344) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_CLR (0x00001348) +#define HW_PXP_WFE_B_STORE_CTRL_CH0_TOG (0x0000134c) + +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN 0x80000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 25 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0 0x7E000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD0(v) \ + (((v) << 25) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL 0x01000000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL__1 0x1 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1 0x00FC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD1(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 12 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2 0x0000F000 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD2(v) \ + (((v) << 12) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN 0x00000800 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH0_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH0_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH0_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_CTRL_CH1 (0x00001350) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_SET (0x00001354) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_CLR (0x00001358) +#define HW_PXP_WFE_B_STORE_CTRL_CH1_TOG (0x0000135c) + +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 18 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0 0xFFFC0000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD0(v) \ + (((v) << 18) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD0) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 16 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES 0x00030000 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__8_bytes 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__16_bytes 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__32_bytes 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES__64_bytes 0x3 +#define BP_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 11 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1 0x0000F800 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD1(v) \ + (((v) << 11) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD1) +#define BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL 0x00000400 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(v) \ + (((v) << 10) & BM_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN 0x00000200 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(v) \ + (((v) << 9) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN 0x00000100 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_CTRL_CH1_RSVD3) +#define BP_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 5 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM 0x00000060 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__1 0x1 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__2 0x2 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM__3 0x3 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN 0x00000008 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(v) \ + (((v) << 3) & BM_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16 0x00000004 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__8x8 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16__16x16 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN 0x00000002 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(v) \ + (((v) << 1) & BM_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN 0x00000001 +#define BF_PXP_WFE_B_STORE_CTRL_CH1_CH_EN(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_CTRL_CH1_CH_EN) +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_CTRL_CH1_CH_EN__1 0x1 + +#define HW_PXP_WFE_B_STORE_STATUS_CH0 (0x00001360) + +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_STATUS_CH1 (0x00001370) + +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 16 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y) +#define BP_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0 +#define BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X 0x0000FFFF +#define BF_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X) + +#define HW_PXP_WFE_B_STORE_SIZE_CH0 (0x00001380) + +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_SIZE_CH1 (0x00001390) + +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 16 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT) +#define BP_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0 +#define BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH) + +#define HW_PXP_WFE_B_STORE_PITCH (0x000013a0) + +#define BP_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 16 +#define BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH 0xFFFF0000 +#define BF_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH) +#define BP_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0 +#define BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH 0x0000FFFF +#define BF_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0 (0x000013b0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET (0x000013b4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR (0x000013b8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG (0x000013bc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 8 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0 0xFFFFFF00 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS 0x00000080 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1 0x00000040 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH0_RSVD2) + +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1 (0x000013c0) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET (0x000013c4) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR (0x000013c8) +#define HW_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG (0x000013cc) + +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 6 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD0) +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN 0x00000020 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(v) \ + (((v) << 5) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN__1 0x1 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN 0x00000010 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(v) \ + (((v) << 4) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN__1 0x1 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 2 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP 0x0000000C +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(v) \ + (((v) << 2) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP) +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__0 0x0 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__1 0x1 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__2 0x2 +#define BV_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP__3 0x3 +#define BP_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0 +#define BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2 0x00000003 +#define BF_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_SHIFT_CTRL_CH1_RSVD2) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH0 (0x00001410) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH0 (0x00001420) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_FILL_DATA_CH0 (0x00001430) + +#define BP_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0 +#define BM_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_0_CH1 (0x00001440) + +#define BP_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0 +#define BM_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(v) (v) + +#define HW_PXP_WFE_B_STORE_ADDR_1_CH1 (0x00001450) + +#define BP_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0 +#define BM_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_H_CH0 (0x00001460) + +#define BP_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK0_L_CH0 (0x00001470) + +#define BP_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_H_CH0 (0x00001480) + +#define BP_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK1_L_CH0 (0x00001490) + +#define BP_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_H_CH0 (0x000014a0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK2_L_CH0 (0x000014b0) + +#define BP_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_H_CH0 (0x000014c0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK3_L_CH0 (0x000014d0) + +#define BP_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_H_CH0 (0x000014e0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK4_L_CH0 (0x000014f0) + +#define BP_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_H_CH0 (0x00001500) + +#define BP_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK5_L_CH0 (0x00001510) + +#define BP_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_H_CH0 (0x00001520) + +#define BP_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK6_L_CH0 (0x00001530) + +#define BP_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_H_CH0 (0x00001540) + +#define BP_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_MASK7_L_CH0 (0x00001550) + +#define BP_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0 +#define BM_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0 0xFFFFFFFF +#define BF_PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(v) (v) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_L_CH0 (0x00001560) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0) +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_D_SHIFT_H_CH0 (0x00001570) + +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7 0x80000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0 0x40000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD0) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6 0x00800000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1 0x00400000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD1) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5 0x00008000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2 0x00004000 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD2) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4 0x00000080 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4) +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3 0x00000040 +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_RSVD3) +#define BP_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_L_CH0 (0x00001580) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0) +#define BP_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0) + +#define HW_PXP_WFE_B_STORE_F_SHIFT_H_CH0 (0x00001590) + +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0 0x80000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0(v) \ + (((v) << 31) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD0) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7 0x40000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(v) \ + (((v) << 30) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 24 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7 0x3F000000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1 0x00800000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1(v) \ + (((v) << 23) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD1) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6 0x00400000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(v) \ + (((v) << 22) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 16 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6 0x003F0000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2 0x00008000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2(v) \ + (((v) << 15) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD2) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5 0x00004000 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(v) \ + (((v) << 14) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 8 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5 0x00003F00 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3 0x00000080 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3(v) \ + (((v) << 7) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_RSVD3) +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4 0x00000040 +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(v) \ + (((v) << 6) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4) +#define BP_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0 +#define BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4 0x0000003F +#define BF_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4) + +#define HW_PXP_WFE_B_STORE_F_MASK_L_CH0 (0x000015a0) + +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 24 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 16 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 8 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1) +#define BP_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0 +#define BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0) + +#define HW_PXP_WFE_B_STORE_F_MASK_H_CH0 (0x000015b0) + +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 24 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7 0xFF000000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 16 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6 0x00FF0000 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 8 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5 0x0000FF00 +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5) +#define BP_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0 +#define BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4 0x000000FF +#define BF_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4) + +#define HW_PXP_FETCH_WFE_A_DEBUG (0x000015c0) + +#define BP_PXP_FETCH_WFE_A_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_A_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_A_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_A_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_A_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_A_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_A_DEBUG_DEBUG_VALUE) + +#define HW_PXP_FETCH_WFE_B_DEBUG (0x000015d0) + +#define BP_PXP_FETCH_WFE_B_DEBUG_RSVD 29 +#define BM_PXP_FETCH_WFE_B_DEBUG_RSVD 0xE0000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_RSVD(v) \ + (((v) << 29) & BM_PXP_FETCH_WFE_B_DEBUG_RSVD) +#define BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL 0x10000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_BUF_SEL(v) \ + (((v) << 28) & BM_PXP_FETCH_WFE_B_DEBUG_BUF_SEL) +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF0 0x0 +#define BV_PXP_FETCH_WFE_B_DEBUG_BUF_SEL__BF1 0x1 +#define BP_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 24 +#define BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL 0x0F000000 +#define BF_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(v) \ + (((v) << 24) & BM_PXP_FETCH_WFE_B_DEBUG_ITEM_SEL) +#define BP_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0 +#define BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE) + +#define HW_PXP_DITHER_CTRL (0x00001670) +#define HW_PXP_DITHER_CTRL_SET (0x00001674) +#define HW_PXP_DITHER_CTRL_CLR (0x00001678) +#define HW_PXP_DITHER_CTRL_TOG (0x0000167c) + +#define BM_PXP_DITHER_CTRL_BUSY0 0x80000000 +#define BF_PXP_DITHER_CTRL_BUSY0(v) \ + (((v) << 31) & BM_PXP_DITHER_CTRL_BUSY0) +#define BM_PXP_DITHER_CTRL_BUSY1 0x40000000 +#define BF_PXP_DITHER_CTRL_BUSY1(v) \ + (((v) << 30) & BM_PXP_DITHER_CTRL_BUSY1) +#define BM_PXP_DITHER_CTRL_BUSY2 0x20000000 +#define BF_PXP_DITHER_CTRL_BUSY2(v) \ + (((v) << 29) & BM_PXP_DITHER_CTRL_BUSY2) +#define BP_PXP_DITHER_CTRL_RSVD0 25 +#define BM_PXP_DITHER_CTRL_RSVD0 0x1E000000 +#define BF_PXP_DITHER_CTRL_RSVD0(v) \ + (((v) << 25) & BM_PXP_DITHER_CTRL_RSVD0) +#define BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE 0x01000000 +#define BF_PXP_DITHER_CTRL_ORDERED_ROUND_MODE(v) \ + (((v) << 24) & BM_PXP_DITHER_CTRL_ORDERED_ROUND_MODE) +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_ORDERED_ROUND_MODE__1 0x1 +#define BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE 0x00800000 +#define BF_PXP_DITHER_CTRL_FINAL_LUT_ENABLE(v) \ + (((v) << 23) & BM_PXP_DITHER_CTRL_FINAL_LUT_ENABLE) +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_FINAL_LUT_ENABLE__Enabled 0x1 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 21 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE 0x00600000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(v) \ + (((v) << 21) & BM_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 19 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE 0x00180000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(v) \ + (((v) << 19) & BM_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 17 +#define BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE 0x00060000 +#define BF_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(v) \ + (((v) << 17) & BM_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE) +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__0 0x0 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__1 0x1 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__2 0x2 +#define BV_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE__3 0x3 +#define BP_PXP_DITHER_CTRL_LUT_MODE 15 +#define BM_PXP_DITHER_CTRL_LUT_MODE 0x00018000 +#define BF_PXP_DITHER_CTRL_LUT_MODE(v) \ + (((v) << 15) & BM_PXP_DITHER_CTRL_LUT_MODE) +#define BV_PXP_DITHER_CTRL_LUT_MODE__0 0x0 +#define BV_PXP_DITHER_CTRL_LUT_MODE__1 0x1 +#define BV_PXP_DITHER_CTRL_LUT_MODE__2 0x2 +#define BV_PXP_DITHER_CTRL_LUT_MODE__3 0x3 +#define BP_PXP_DITHER_CTRL_NUM_QUANT_BIT 12 +#define BM_PXP_DITHER_CTRL_NUM_QUANT_BIT 0x00007000 +#define BF_PXP_DITHER_CTRL_NUM_QUANT_BIT(v) \ + (((v) << 12) & BM_PXP_DITHER_CTRL_NUM_QUANT_BIT) +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__0 0x0 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__1 0x1 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__2 0x2 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__3 0x3 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__4 0x4 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__5 0x5 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__6 0x6 +#define BV_PXP_DITHER_CTRL_NUM_QUANT_BIT__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE2 9 +#define BM_PXP_DITHER_CTRL_DITHER_MODE2 0x00000E00 +#define BF_PXP_DITHER_CTRL_DITHER_MODE2(v) \ + (((v) << 9) & BM_PXP_DITHER_CTRL_DITHER_MODE2) +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE2__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE1 6 +#define BM_PXP_DITHER_CTRL_DITHER_MODE1 0x000001C0 +#define BF_PXP_DITHER_CTRL_DITHER_MODE1(v) \ + (((v) << 6) & BM_PXP_DITHER_CTRL_DITHER_MODE1) +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE1__7 0x7 +#define BP_PXP_DITHER_CTRL_DITHER_MODE0 3 +#define BM_PXP_DITHER_CTRL_DITHER_MODE0 0x00000038 +#define BF_PXP_DITHER_CTRL_DITHER_MODE0(v) \ + (((v) << 3) & BM_PXP_DITHER_CTRL_DITHER_MODE0) +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__0 0x0 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__1 0x1 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__2 0x2 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__3 0x3 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__4 0x4 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__5 0x5 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__6 0x6 +#define BV_PXP_DITHER_CTRL_DITHER_MODE0__7 0x7 +#define BM_PXP_DITHER_CTRL_ENABLE2 0x00000004 +#define BF_PXP_DITHER_CTRL_ENABLE2(v) \ + (((v) << 2) & BM_PXP_DITHER_CTRL_ENABLE2) +#define BV_PXP_DITHER_CTRL_ENABLE2__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE2__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE1 0x00000002 +#define BF_PXP_DITHER_CTRL_ENABLE1(v) \ + (((v) << 1) & BM_PXP_DITHER_CTRL_ENABLE1) +#define BV_PXP_DITHER_CTRL_ENABLE1__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE1__Enabled 0x1 +#define BM_PXP_DITHER_CTRL_ENABLE0 0x00000001 +#define BF_PXP_DITHER_CTRL_ENABLE0(v) \ + (((v) << 0) & BM_PXP_DITHER_CTRL_ENABLE0) +#define BV_PXP_DITHER_CTRL_ENABLE0__Disabled 0x0 +#define BV_PXP_DITHER_CTRL_ENABLE0__Enabled 0x1 + +#define HW_PXP_DITHER_FINAL_LUT_DATA0 (0x00001680) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_SET (0x00001684) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_CLR (0x00001688) +#define HW_PXP_DITHER_FINAL_LUT_DATA0_TOG (0x0000168c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA3 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA3(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA3) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA2 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA2(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA2) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA1 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA1(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA1) +#define BP_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA0_DATA0(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA0_DATA0) + +#define HW_PXP_DITHER_FINAL_LUT_DATA1 (0x00001690) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_SET (0x00001694) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_CLR (0x00001698) +#define HW_PXP_DITHER_FINAL_LUT_DATA1_TOG (0x0000169c) + +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA7 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA7(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA7) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA6 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA6(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA6) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA5 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA5(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA5) +#define BP_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA1_DATA4(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA1_DATA4) + +#define HW_PXP_DITHER_FINAL_LUT_DATA2 (0x000016a0) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_SET (0x000016a4) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_CLR (0x000016a8) +#define HW_PXP_DITHER_FINAL_LUT_DATA2_TOG (0x000016ac) + +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA11 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA11(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA11) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA10 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA10(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA10) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA9 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA9(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA9) +#define BP_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA2_DATA8(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA2_DATA8) + +#define HW_PXP_DITHER_FINAL_LUT_DATA3 (0x000016b0) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_SET (0x000016b4) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_CLR (0x000016b8) +#define HW_PXP_DITHER_FINAL_LUT_DATA3_TOG (0x000016bc) + +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA15 24 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15 0xFF000000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA15(v) \ + (((v) << 24) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA15) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA14 16 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14 0x00FF0000 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA14(v) \ + (((v) << 16) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA14) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA13 8 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13 0x0000FF00 +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA13(v) \ + (((v) << 8) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA13) +#define BP_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0 +#define BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12 0x000000FF +#define BF_PXP_DITHER_FINAL_LUT_DATA3_DATA12(v) \ + (((v) << 0) & BM_PXP_DITHER_FINAL_LUT_DATA3_DATA12) + +#define HW_PXP_WFE_A_CTRL (0x000016c0) +#define HW_PXP_WFE_A_CTRL_SET (0x000016c4) +#define HW_PXP_WFE_A_CTRL_CLR (0x000016c8) +#define HW_PXP_WFE_A_CTRL_TOG (0x000016cc) + +#define BM_PXP_WFE_A_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_A_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_A_CTRL_DONE) +#define BP_PXP_WFE_A_CTRL_RSVD0 3 +#define BM_PXP_WFE_A_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_A_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_A_CTRL_RSVD0) +#define BM_PXP_WFE_A_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_A_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_A_CTRL_SW_RESET) +#define BM_PXP_WFE_A_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_A_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_A_CTRL_RSVD1) +#define BM_PXP_WFE_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_A_CTRL_ENABLE) +#define BV_PXP_WFE_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_A_DIMENSIONS (0x000016d0) + +#define BP_PXP_WFE_A_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_A_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_A_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_A_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_A_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_A_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_A_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_A_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_A_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_A_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_A_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_A_OFFSET (0x000016e0) + +#define BP_PXP_WFE_A_OFFSET_RSVD0 28 +#define BM_PXP_WFE_A_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_A_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_A_OFFSET_RSVD0) +#define BP_PXP_WFE_A_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_A_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_A_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_A_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_A_OFFSET_RSVD1 12 +#define BM_PXP_WFE_A_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_A_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_A_OFFSET_RSVD1) +#define BP_PXP_WFE_A_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_A_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_A_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_A_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_A_SW_DATA_REGS (0x000016f0) + +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_A_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_A_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_A_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_A_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_A_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_A_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_A_SW_FLAG_REGS (0x00001700) + +#define BP_PXP_WFE_A_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_A_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_A_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_A_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_A_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_A_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_A_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_A_STAGE1_MUX0 (0x00001710) +#define HW_PXP_WFE_A_STAGE1_MUX0_SET (0x00001714) +#define HW_PXP_WFE_A_STAGE1_MUX0_CLR (0x00001718) +#define HW_PXP_WFE_A_STAGE1_MUX0_TOG (0x0000171c) + +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE1_MUX1 (0x00001720) +#define HW_PXP_WFE_A_STAGE1_MUX1_SET (0x00001724) +#define HW_PXP_WFE_A_STAGE1_MUX1_CLR (0x00001728) +#define HW_PXP_WFE_A_STAGE1_MUX1_TOG (0x0000172c) + +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX1_MUX7) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX7__NOP 0xc +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX1_MUX4) +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__INC 0x0 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__DEC 0x1 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__ADD 0x2 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__AND 0x4 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__OR 0x5 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__XOR 0x6 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE1_MUX1_MUX4__NOP 0xc + +#define HW_PXP_WFE_A_STAGE1_MUX2 (0x00001730) +#define HW_PXP_WFE_A_STAGE1_MUX2_SET (0x00001734) +#define HW_PXP_WFE_A_STAGE1_MUX2_CLR (0x00001738) +#define HW_PXP_WFE_A_STAGE1_MUX2_TOG (0x0000173c) + +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE1_MUX3 (0x00001740) +#define HW_PXP_WFE_A_STAGE1_MUX3_SET (0x00001744) +#define HW_PXP_WFE_A_STAGE1_MUX3_CLR (0x00001748) +#define HW_PXP_WFE_A_STAGE1_MUX3_TOG (0x0000174c) + +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE1_MUX4 (0x00001750) +#define HW_PXP_WFE_A_STAGE1_MUX4_SET (0x00001754) +#define HW_PXP_WFE_A_STAGE1_MUX4_CLR (0x00001758) +#define HW_PXP_WFE_A_STAGE1_MUX4_TOG (0x0000175c) + +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD0 24 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD0 0xFF000000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD0(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD1 16 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD1 0x00FF0000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD1(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX0 (0x00001760) +#define HW_PXP_WFE_A_STAGE2_MUX0_SET (0x00001764) +#define HW_PXP_WFE_A_STAGE2_MUX0_CLR (0x00001768) +#define HW_PXP_WFE_A_STAGE2_MUX0_TOG (0x0000176c) + +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE2_MUX1 (0x00001770) +#define HW_PXP_WFE_A_STAGE2_MUX1_SET (0x00001774) +#define HW_PXP_WFE_A_STAGE2_MUX1_CLR (0x00001778) +#define HW_PXP_WFE_A_STAGE2_MUX1_TOG (0x0000177c) + +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE2_MUX2 (0x00001780) +#define HW_PXP_WFE_A_STAGE2_MUX2_SET (0x00001784) +#define HW_PXP_WFE_A_STAGE2_MUX2_CLR (0x00001788) +#define HW_PXP_WFE_A_STAGE2_MUX2_TOG (0x0000178c) + +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE2_MUX3 (0x00001790) +#define HW_PXP_WFE_A_STAGE2_MUX3_SET (0x00001794) +#define HW_PXP_WFE_A_STAGE2_MUX3_CLR (0x00001798) +#define HW_PXP_WFE_A_STAGE2_MUX3_TOG (0x0000179c) + +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_A_STAGE2_MUX4 (0x000017a0) +#define HW_PXP_WFE_A_STAGE2_MUX4_SET (0x000017a4) +#define HW_PXP_WFE_A_STAGE2_MUX4_CLR (0x000017a8) +#define HW_PXP_WFE_A_STAGE2_MUX4_TOG (0x000017ac) + +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_A_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_A_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_A_STAGE2_MUX5 (0x000017b0) +#define HW_PXP_WFE_A_STAGE2_MUX5_SET (0x000017b4) +#define HW_PXP_WFE_A_STAGE2_MUX5_CLR (0x000017b8) +#define HW_PXP_WFE_A_STAGE2_MUX5_TOG (0x000017bc) + +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_A_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_A_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_A_STAGE2_MUX6 (0x000017c0) +#define HW_PXP_WFE_A_STAGE2_MUX6_SET (0x000017c4) +#define HW_PXP_WFE_A_STAGE2_MUX6_CLR (0x000017c8) +#define HW_PXP_WFE_A_STAGE2_MUX6_TOG (0x000017cc) + +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_A_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_A_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_A_STAGE2_MUX7 (0x000017d0) +#define HW_PXP_WFE_A_STAGE2_MUX7_SET (0x000017d4) +#define HW_PXP_WFE_A_STAGE2_MUX7_CLR (0x000017d8) +#define HW_PXP_WFE_A_STAGE2_MUX7_TOG (0x000017dc) + +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_A_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_A_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_A_STAGE2_MUX8 (0x000017e0) +#define HW_PXP_WFE_A_STAGE2_MUX8_SET (0x000017e4) +#define HW_PXP_WFE_A_STAGE2_MUX8_CLR (0x000017e8) +#define HW_PXP_WFE_A_STAGE2_MUX8_TOG (0x000017ec) + +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_A_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_A_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_A_STAGE2_MUX9 (0x000017f0) +#define HW_PXP_WFE_A_STAGE2_MUX9_SET (0x000017f4) +#define HW_PXP_WFE_A_STAGE2_MUX9_CLR (0x000017f8) +#define HW_PXP_WFE_A_STAGE2_MUX9_TOG (0x000017fc) + +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_A_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_A_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_A_STAGE2_MUX10 (0x00001800) +#define HW_PXP_WFE_A_STAGE2_MUX10_SET (0x00001804) +#define HW_PXP_WFE_A_STAGE2_MUX10_CLR (0x00001808) +#define HW_PXP_WFE_A_STAGE2_MUX10_TOG (0x0000180c) + +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX10_MUX43) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX43__NOP 0xc +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_A_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_A_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_A_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_A_STAGE2_MUX11 (0x00001810) +#define HW_PXP_WFE_A_STAGE2_MUX11_SET (0x00001814) +#define HW_PXP_WFE_A_STAGE2_MUX11_CLR (0x00001818) +#define HW_PXP_WFE_A_STAGE2_MUX11_TOG (0x0000181c) + +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_A_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_A_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_A_STAGE2_MUX12 (0x00001820) +#define HW_PXP_WFE_A_STAGE2_MUX12_SET (0x00001824) +#define HW_PXP_WFE_A_STAGE2_MUX12_CLR (0x00001828) +#define HW_PXP_WFE_A_STAGE2_MUX12_TOG (0x0000182c) + +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD0 14 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD0 0xFFFFC000 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD0(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX49 8 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX49 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX49(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_MUX12_MUX49) +#define BP_PXP_WFE_A_STAGE2_MUX12_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_MUX12_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_MUX12_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_MUX12_RSVD3) +#define BP_PXP_WFE_A_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_A_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_A_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_A_STAGE3_MUX0 (0x00001830) +#define HW_PXP_WFE_A_STAGE3_MUX0_SET (0x00001834) +#define HW_PXP_WFE_A_STAGE3_MUX0_CLR (0x00001838) +#define HW_PXP_WFE_A_STAGE3_MUX0_TOG (0x0000183c) + +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_A_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_A_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_A_STAGE3_MUX1 (0x00001840) +#define HW_PXP_WFE_A_STAGE3_MUX1_SET (0x00001844) +#define HW_PXP_WFE_A_STAGE3_MUX1_CLR (0x00001848) +#define HW_PXP_WFE_A_STAGE3_MUX1_TOG (0x0000184c) + +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_A_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_A_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_A_STAGE3_MUX2 (0x00001850) +#define HW_PXP_WFE_A_STAGE3_MUX2_SET (0x00001854) +#define HW_PXP_WFE_A_STAGE3_MUX2_CLR (0x00001858) +#define HW_PXP_WFE_A_STAGE3_MUX2_TOG (0x0000185c) + +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_A_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_A_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_A_STAGE3_MUX3 (0x00001860) +#define HW_PXP_WFE_A_STAGE3_MUX3_SET (0x00001864) +#define HW_PXP_WFE_A_STAGE3_MUX3_CLR (0x00001868) +#define HW_PXP_WFE_A_STAGE3_MUX3_TOG (0x0000186c) + +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_A_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_A_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_A_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_A_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_A_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_0 (0x00001870) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_1 (0x00001880) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_2 (0x00001890) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_3 (0x000018a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_4 (0x000018b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_5 (0x000018c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_6 (0x000018d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT0_7 (0x000018e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_0 (0x000018f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_1 (0x00001900) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_2 (0x00001910) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_3 (0x00001920) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_4 (0x00001930) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_5 (0x00001940) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_6 (0x00001950) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT1_7 (0x00001960) + +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_0 (0x00001970) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_1 (0x00001980) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_2 (0x00001990) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_3 (0x000019a0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_4 (0x000019b0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_5 (0x000019c0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_6 (0x000019d0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT2_7 (0x000019e0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_0 (0x000019f0) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_1 (0x00001a00) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_2 (0x00001a10) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_3 (0x00001a20) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_4 (0x00001a30) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_5 (0x00001a40) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_6 (0x00001a50) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_A_STG1_8X1_OUT3_7 (0x00001a60) + +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_0 (0x00001a70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_1 (0x00001a80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_2 (0x00001a90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_3 (0x00001aa0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_4 (0x00001ab0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_5 (0x00001ac0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_6 (0x00001ad0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT0_7 (0x00001ae0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_0 (0x00001af0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_1 (0x00001b00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_2 (0x00001b10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_3 (0x00001b20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_4 (0x00001b30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_5 (0x00001b40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_6 (0x00001b50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT1_7 (0x00001b60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_0 (0x00001b70) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_1 (0x00001b80) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_2 (0x00001b90) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_3 (0x00001ba0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_4 (0x00001bb0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_5 (0x00001bc0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_6 (0x00001bd0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT2_7 (0x00001be0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_0 (0x00001bf0) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_1 (0x00001c00) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_2 (0x00001c10) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_3 (0x00001c20) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_4 (0x00001c30) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_5 (0x00001c40) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_6 (0x00001c50) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_A_STG2_5X6_OUT3_7 (0x00001c60) + +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_A_STAGE2_5X6_MASKS_0 (0x00001c70) + +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 29 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0 0xE0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 29) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 21 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1 0x00E00000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 21) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2 0x0000E000 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_A_STAGE2_5X6_ADDR_0 (0x00001c80) + +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 30 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 22 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 14 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 6 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT0 (0x00001c90) + +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT1 (0x00001ca0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT2 (0x00001cb0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_OUT3 (0x00001cc0) + +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_A_STG2_5X1_MASKS (0x00001cd0) + +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_A_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_A_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_A_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_A_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_CTRL (0x00001d00) +#define HW_PXP_WFE_B_CTRL_SET (0x00001d04) +#define HW_PXP_WFE_B_CTRL_CLR (0x00001d08) +#define HW_PXP_WFE_B_CTRL_TOG (0x00001d0c) + +#define BM_PXP_WFE_B_CTRL_DONE 0x80000000 +#define BF_PXP_WFE_B_CTRL_DONE(v) \ + (((v) << 31) & BM_PXP_WFE_B_CTRL_DONE) +#define BP_PXP_WFE_B_CTRL_RSVD0 3 +#define BM_PXP_WFE_B_CTRL_RSVD0 0x7FFFFFF8 +#define BF_PXP_WFE_B_CTRL_RSVD0(v) \ + (((v) << 3) & BM_PXP_WFE_B_CTRL_RSVD0) +#define BM_PXP_WFE_B_CTRL_SW_RESET 0x00000004 +#define BF_PXP_WFE_B_CTRL_SW_RESET(v) \ + (((v) << 2) & BM_PXP_WFE_B_CTRL_SW_RESET) +#define BM_PXP_WFE_B_CTRL_RSVD1 0x00000002 +#define BF_PXP_WFE_B_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_WFE_B_CTRL_RSVD1) +#define BM_PXP_WFE_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_WFE_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_WFE_B_CTRL_ENABLE) +#define BV_PXP_WFE_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_WFE_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_WFE_B_DIMENSIONS (0x00001d10) + +#define BP_PXP_WFE_B_DIMENSIONS_RSVD0 28 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_DIMENSIONS_RSVD0) +#define BP_PXP_WFE_B_DIMENSIONS_HEIGHT 16 +#define BM_PXP_WFE_B_DIMENSIONS_HEIGHT 0x0FFF0000 +#define BF_PXP_WFE_B_DIMENSIONS_HEIGHT(v) \ + (((v) << 16) & BM_PXP_WFE_B_DIMENSIONS_HEIGHT) +#define BP_PXP_WFE_B_DIMENSIONS_RSVD1 12 +#define BM_PXP_WFE_B_DIMENSIONS_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_DIMENSIONS_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_DIMENSIONS_RSVD1) +#define BP_PXP_WFE_B_DIMENSIONS_WIDTH 0 +#define BM_PXP_WFE_B_DIMENSIONS_WIDTH 0x00000FFF +#define BF_PXP_WFE_B_DIMENSIONS_WIDTH(v) \ + (((v) << 0) & BM_PXP_WFE_B_DIMENSIONS_WIDTH) + +#define HW_PXP_WFE_B_OFFSET (0x00001d20) + +#define BP_PXP_WFE_B_OFFSET_RSVD0 28 +#define BM_PXP_WFE_B_OFFSET_RSVD0 0xF0000000 +#define BF_PXP_WFE_B_OFFSET_RSVD0(v) \ + (((v) << 28) & BM_PXP_WFE_B_OFFSET_RSVD0) +#define BP_PXP_WFE_B_OFFSET_Y_OFFSET 16 +#define BM_PXP_WFE_B_OFFSET_Y_OFFSET 0x0FFF0000 +#define BF_PXP_WFE_B_OFFSET_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_WFE_B_OFFSET_Y_OFFSET) +#define BP_PXP_WFE_B_OFFSET_RSVD1 12 +#define BM_PXP_WFE_B_OFFSET_RSVD1 0x0000F000 +#define BF_PXP_WFE_B_OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_WFE_B_OFFSET_RSVD1) +#define BP_PXP_WFE_B_OFFSET_X_OFFSET 0 +#define BM_PXP_WFE_B_OFFSET_X_OFFSET 0x00000FFF +#define BF_PXP_WFE_B_OFFSET_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_WFE_B_OFFSET_X_OFFSET) + +#define HW_PXP_WFE_B_SW_DATA_REGS (0x00001d30) + +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL3 24 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL3 0xFF000000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL3(v) \ + (((v) << 24) & BM_PXP_WFE_B_SW_DATA_REGS_VAL3) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL2 16 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL2 0x00FF0000 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL2(v) \ + (((v) << 16) & BM_PXP_WFE_B_SW_DATA_REGS_VAL2) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL1 8 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL1 0x0000FF00 +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL1(v) \ + (((v) << 8) & BM_PXP_WFE_B_SW_DATA_REGS_VAL1) +#define BP_PXP_WFE_B_SW_DATA_REGS_VAL0 0 +#define BM_PXP_WFE_B_SW_DATA_REGS_VAL0 0x000000FF +#define BF_PXP_WFE_B_SW_DATA_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_DATA_REGS_VAL0) + +#define HW_PXP_WFE_B_SW_FLAG_REGS (0x00001d40) + +#define BP_PXP_WFE_B_SW_FLAG_REGS_RSVD 4 +#define BM_PXP_WFE_B_SW_FLAG_REGS_RSVD 0xFFFFFFF0 +#define BF_PXP_WFE_B_SW_FLAG_REGS_RSVD(v) \ + (((v) << 4) & BM_PXP_WFE_B_SW_FLAG_REGS_RSVD) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL3 0x00000008 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL3(v) \ + (((v) << 3) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL3) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL2 0x00000004 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL2(v) \ + (((v) << 2) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL2) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL1 0x00000002 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL1(v) \ + (((v) << 1) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL1) +#define BM_PXP_WFE_B_SW_FLAG_REGS_VAL0 0x00000001 +#define BF_PXP_WFE_B_SW_FLAG_REGS_VAL0(v) \ + (((v) << 0) & BM_PXP_WFE_B_SW_FLAG_REGS_VAL0) + +#define HW_PXP_WFE_B_STAGE1_MUX0 (0x00001d50) +#define HW_PXP_WFE_B_STAGE1_MUX0_SET (0x00001d54) +#define HW_PXP_WFE_B_STAGE1_MUX0_CLR (0x00001d58) +#define HW_PXP_WFE_B_STAGE1_MUX0_TOG (0x00001d5c) + +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE1_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE1_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE1_MUX1 (0x00001d60) +#define HW_PXP_WFE_B_STAGE1_MUX1_SET (0x00001d64) +#define HW_PXP_WFE_B_STAGE1_MUX1_CLR (0x00001d68) +#define HW_PXP_WFE_B_STAGE1_MUX1_TOG (0x00001d6c) + +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE1_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE1_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE1_MUX2 (0x00001d70) +#define HW_PXP_WFE_B_STAGE1_MUX2_SET (0x00001d74) +#define HW_PXP_WFE_B_STAGE1_MUX2_CLR (0x00001d78) +#define HW_PXP_WFE_B_STAGE1_MUX2_TOG (0x00001d7c) + +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE1_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE1_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE1_MUX3 (0x00001d80) +#define HW_PXP_WFE_B_STAGE1_MUX3_SET (0x00001d84) +#define HW_PXP_WFE_B_STAGE1_MUX3_CLR (0x00001d88) +#define HW_PXP_WFE_B_STAGE1_MUX3_TOG (0x00001d8c) + +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE1_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE1_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE1_MUX4 (0x00001d90) +#define HW_PXP_WFE_B_STAGE1_MUX4_SET (0x00001d94) +#define HW_PXP_WFE_B_STAGE1_MUX4_CLR (0x00001d98) +#define HW_PXP_WFE_B_STAGE1_MUX4_TOG (0x00001d9c) + +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE1_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE1_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE1_MUX5 (0x00001da0) +#define HW_PXP_WFE_B_STAGE1_MUX5_SET (0x00001da4) +#define HW_PXP_WFE_B_STAGE1_MUX5_CLR (0x00001da8) +#define HW_PXP_WFE_B_STAGE1_MUX5_TOG (0x00001dac) + +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE1_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE1_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX5_MUX20) +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__INC 0x0 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__DEC 0x1 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__ADD 0x2 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__AND 0x4 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__OR 0x5 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__XOR 0x6 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE1_MUX5_MUX20__NOP 0xc + +#define HW_PXP_WFE_B_STAGE1_MUX6 (0x00001db0) +#define HW_PXP_WFE_B_STAGE1_MUX6_SET (0x00001db4) +#define HW_PXP_WFE_B_STAGE1_MUX6_CLR (0x00001db8) +#define HW_PXP_WFE_B_STAGE1_MUX6_TOG (0x00001dbc) + +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE1_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE1_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE1_MUX7 (0x00001dc0) +#define HW_PXP_WFE_B_STAGE1_MUX7_SET (0x00001dc4) +#define HW_PXP_WFE_B_STAGE1_MUX7_CLR (0x00001dc8) +#define HW_PXP_WFE_B_STAGE1_MUX7_TOG (0x00001dcc) + +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE1_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE1_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE1_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE1_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE1_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE1_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE1_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE1_MUX8 (0x00001dd0) +#define HW_PXP_WFE_B_STAGE1_MUX8_SET (0x00001dd4) +#define HW_PXP_WFE_B_STAGE1_MUX8_CLR (0x00001dd8) +#define HW_PXP_WFE_B_STAGE1_MUX8_TOG (0x00001ddc) + +#define BP_PXP_WFE_B_STAGE1_MUX8_RSVD0 6 +#define BM_PXP_WFE_B_STAGE1_MUX8_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE1_MUX8_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE1_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE1_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE1_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE1_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX0 (0x00001de0) +#define HW_PXP_WFE_B_STAGE2_MUX0_SET (0x00001de4) +#define HW_PXP_WFE_B_STAGE2_MUX0_CLR (0x00001de8) +#define HW_PXP_WFE_B_STAGE2_MUX0_TOG (0x00001dec) + +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE2_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE2_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE2_MUX1 (0x00001df0) +#define HW_PXP_WFE_B_STAGE2_MUX1_SET (0x00001df4) +#define HW_PXP_WFE_B_STAGE2_MUX1_CLR (0x00001df8) +#define HW_PXP_WFE_B_STAGE2_MUX1_TOG (0x00001dfc) + +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE2_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE2_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE2_MUX2 (0x00001e00) +#define HW_PXP_WFE_B_STAGE2_MUX2_SET (0x00001e04) +#define HW_PXP_WFE_B_STAGE2_MUX2_CLR (0x00001e08) +#define HW_PXP_WFE_B_STAGE2_MUX2_TOG (0x00001e0c) + +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE2_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE2_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE2_MUX3 (0x00001e10) +#define HW_PXP_WFE_B_STAGE2_MUX3_SET (0x00001e14) +#define HW_PXP_WFE_B_STAGE2_MUX3_CLR (0x00001e18) +#define HW_PXP_WFE_B_STAGE2_MUX3_TOG (0x00001e1c) + +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE2_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE2_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE2_MUX4 (0x00001e20) +#define HW_PXP_WFE_B_STAGE2_MUX4_SET (0x00001e24) +#define HW_PXP_WFE_B_STAGE2_MUX4_CLR (0x00001e28) +#define HW_PXP_WFE_B_STAGE2_MUX4_TOG (0x00001e2c) + +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE2_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE2_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE2_MUX5 (0x00001e30) +#define HW_PXP_WFE_B_STAGE2_MUX5_SET (0x00001e34) +#define HW_PXP_WFE_B_STAGE2_MUX5_CLR (0x00001e38) +#define HW_PXP_WFE_B_STAGE2_MUX5_TOG (0x00001e3c) + +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE2_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE2_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE2_MUX6 (0x00001e40) +#define HW_PXP_WFE_B_STAGE2_MUX6_SET (0x00001e44) +#define HW_PXP_WFE_B_STAGE2_MUX6_CLR (0x00001e48) +#define HW_PXP_WFE_B_STAGE2_MUX6_TOG (0x00001e4c) + +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE2_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE2_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE2_MUX7 (0x00001e50) +#define HW_PXP_WFE_B_STAGE2_MUX7_SET (0x00001e54) +#define HW_PXP_WFE_B_STAGE2_MUX7_CLR (0x00001e58) +#define HW_PXP_WFE_B_STAGE2_MUX7_TOG (0x00001e5c) + +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE2_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE2_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE2_MUX8 (0x00001e60) +#define HW_PXP_WFE_B_STAGE2_MUX8_SET (0x00001e64) +#define HW_PXP_WFE_B_STAGE2_MUX8_CLR (0x00001e68) +#define HW_PXP_WFE_B_STAGE2_MUX8_TOG (0x00001e6c) + +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE2_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE2_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE2_MUX9 (0x00001e70) +#define HW_PXP_WFE_B_STAGE2_MUX9_SET (0x00001e74) +#define HW_PXP_WFE_B_STAGE2_MUX9_CLR (0x00001e78) +#define HW_PXP_WFE_B_STAGE2_MUX9_TOG (0x00001e7c) + +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE2_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE2_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE2_MUX10 (0x00001e80) +#define HW_PXP_WFE_B_STAGE2_MUX10_SET (0x00001e84) +#define HW_PXP_WFE_B_STAGE2_MUX10_CLR (0x00001e88) +#define HW_PXP_WFE_B_STAGE2_MUX10_TOG (0x00001e8c) + +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE2_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE2_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX10_MUX40) +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__INC 0x0 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__DEC 0x1 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__ADD 0x2 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__MINUS 0x3 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__AND 0x4 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__OR 0x5 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__XOR 0x6 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTLEFT 0x7 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__SHIFTRIGHT 0x8 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_AND 0x9 +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_OR 0xa +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__BIT_CMP 0xb +#define BV_PXP_WFE_B_STAGE2_MUX10_MUX40__NOP 0xc + +#define HW_PXP_WFE_B_STAGE2_MUX11 (0x00001e90) +#define HW_PXP_WFE_B_STAGE2_MUX11_SET (0x00001e94) +#define HW_PXP_WFE_B_STAGE2_MUX11_CLR (0x00001e98) +#define HW_PXP_WFE_B_STAGE2_MUX11_TOG (0x00001e9c) + +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD0 30 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX47 24 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX47 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX47(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_MUX11_MUX47) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD1 22 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD1) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX46 16 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX46 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX46(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_MUX11_MUX46) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD2 14 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD2) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX45 8 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX45 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX45(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_MUX11_MUX45) +#define BP_PXP_WFE_B_STAGE2_MUX11_RSVD3 6 +#define BM_PXP_WFE_B_STAGE2_MUX11_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_MUX11_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX11_RSVD3) +#define BP_PXP_WFE_B_STAGE2_MUX11_MUX44 0 +#define BM_PXP_WFE_B_STAGE2_MUX11_MUX44 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX11_MUX44(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX11_MUX44) + +#define HW_PXP_WFE_B_STAGE2_MUX12 (0x00001ea0) +#define HW_PXP_WFE_B_STAGE2_MUX12_SET (0x00001ea4) +#define HW_PXP_WFE_B_STAGE2_MUX12_CLR (0x00001ea8) +#define HW_PXP_WFE_B_STAGE2_MUX12_TOG (0x00001eac) + +#define BP_PXP_WFE_B_STAGE2_MUX12_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_MUX12_RSVD0 0xFFFFFFC0 +#define BF_PXP_WFE_B_STAGE2_MUX12_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_MUX12_RSVD0) +#define BP_PXP_WFE_B_STAGE2_MUX12_MUX48 0 +#define BM_PXP_WFE_B_STAGE2_MUX12_MUX48 0x0000003F +#define BF_PXP_WFE_B_STAGE2_MUX12_MUX48(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_MUX12_MUX48) + +#define HW_PXP_WFE_B_STAGE3_MUX0 (0x00001eb0) +#define HW_PXP_WFE_B_STAGE3_MUX0_SET (0x00001eb4) +#define HW_PXP_WFE_B_STAGE3_MUX0_CLR (0x00001eb8) +#define HW_PXP_WFE_B_STAGE3_MUX0_TOG (0x00001ebc) + +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX3 24 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX3 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX0_MUX3) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX2 16 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX2 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX0_MUX2) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX1 8 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX1 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX0_MUX1) +#define BP_PXP_WFE_B_STAGE3_MUX0_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX0_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX0_MUX0 0 +#define BM_PXP_WFE_B_STAGE3_MUX0_MUX0 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX0_MUX0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX0_MUX0) + +#define HW_PXP_WFE_B_STAGE3_MUX1 (0x00001ec0) +#define HW_PXP_WFE_B_STAGE3_MUX1_SET (0x00001ec4) +#define HW_PXP_WFE_B_STAGE3_MUX1_CLR (0x00001ec8) +#define HW_PXP_WFE_B_STAGE3_MUX1_TOG (0x00001ecc) + +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX7 24 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX7 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX1_MUX7) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX6 16 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX6 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX1_MUX6) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX5 8 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX5 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX1_MUX5) +#define BP_PXP_WFE_B_STAGE3_MUX1_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX1_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX1_MUX4 0 +#define BM_PXP_WFE_B_STAGE3_MUX1_MUX4 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX1_MUX4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX1_MUX4) + +#define HW_PXP_WFE_B_STAGE3_MUX2 (0x00001ed0) +#define HW_PXP_WFE_B_STAGE3_MUX2_SET (0x00001ed4) +#define HW_PXP_WFE_B_STAGE3_MUX2_CLR (0x00001ed8) +#define HW_PXP_WFE_B_STAGE3_MUX2_TOG (0x00001edc) + +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX11 24 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX11 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX2_MUX11) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX10 16 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX10 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX2_MUX10) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX9 8 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX9 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX2_MUX9) +#define BP_PXP_WFE_B_STAGE3_MUX2_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX2_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX2_MUX8 0 +#define BM_PXP_WFE_B_STAGE3_MUX2_MUX8 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX2_MUX8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX2_MUX8) + +#define HW_PXP_WFE_B_STAGE3_MUX3 (0x00001ee0) +#define HW_PXP_WFE_B_STAGE3_MUX3_SET (0x00001ee4) +#define HW_PXP_WFE_B_STAGE3_MUX3_CLR (0x00001ee8) +#define HW_PXP_WFE_B_STAGE3_MUX3_TOG (0x00001eec) + +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX15 24 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX15 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX3_MUX15) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX14 16 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX14 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX3_MUX14) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX13 8 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX13 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX3_MUX13) +#define BP_PXP_WFE_B_STAGE3_MUX3_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX3_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX3_MUX12 0 +#define BM_PXP_WFE_B_STAGE3_MUX3_MUX12 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX3_MUX12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX3_MUX12) + +#define HW_PXP_WFE_B_STAGE3_MUX4 (0x00001ef0) +#define HW_PXP_WFE_B_STAGE3_MUX4_SET (0x00001ef4) +#define HW_PXP_WFE_B_STAGE3_MUX4_CLR (0x00001ef8) +#define HW_PXP_WFE_B_STAGE3_MUX4_TOG (0x00001efc) + +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX19 24 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX19 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX4_MUX19) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX18 16 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX18 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX4_MUX18) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX17 8 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX17 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX4_MUX17) +#define BP_PXP_WFE_B_STAGE3_MUX4_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX4_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX4_MUX16 0 +#define BM_PXP_WFE_B_STAGE3_MUX4_MUX16 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX4_MUX16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX4_MUX16) + +#define HW_PXP_WFE_B_STAGE3_MUX5 (0x00001f00) +#define HW_PXP_WFE_B_STAGE3_MUX5_SET (0x00001f04) +#define HW_PXP_WFE_B_STAGE3_MUX5_CLR (0x00001f08) +#define HW_PXP_WFE_B_STAGE3_MUX5_TOG (0x00001f0c) + +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX23 24 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX23 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX5_MUX23) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX22 16 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX22 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX5_MUX22) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX21 8 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX21 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX5_MUX21) +#define BP_PXP_WFE_B_STAGE3_MUX5_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX5_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX5_MUX20 0 +#define BM_PXP_WFE_B_STAGE3_MUX5_MUX20 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX5_MUX20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX5_MUX20) + +#define HW_PXP_WFE_B_STAGE3_MUX6 (0x00001f10) +#define HW_PXP_WFE_B_STAGE3_MUX6_SET (0x00001f14) +#define HW_PXP_WFE_B_STAGE3_MUX6_CLR (0x00001f18) +#define HW_PXP_WFE_B_STAGE3_MUX6_TOG (0x00001f1c) + +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX27 24 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX27 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX6_MUX27) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX26 16 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX26 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX6_MUX26) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX25 8 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX25 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX6_MUX25) +#define BP_PXP_WFE_B_STAGE3_MUX6_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX6_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX6_MUX24 0 +#define BM_PXP_WFE_B_STAGE3_MUX6_MUX24 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX6_MUX24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX6_MUX24) + +#define HW_PXP_WFE_B_STAGE3_MUX7 (0x00001f20) +#define HW_PXP_WFE_B_STAGE3_MUX7_SET (0x00001f24) +#define HW_PXP_WFE_B_STAGE3_MUX7_CLR (0x00001f28) +#define HW_PXP_WFE_B_STAGE3_MUX7_TOG (0x00001f2c) + +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX31 24 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX31 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX7_MUX31) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX30 16 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX30 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX7_MUX30) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX29 8 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX29 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX7_MUX29) +#define BP_PXP_WFE_B_STAGE3_MUX7_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX7_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX7_MUX28 0 +#define BM_PXP_WFE_B_STAGE3_MUX7_MUX28 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX7_MUX28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX7_MUX28) + +#define HW_PXP_WFE_B_STAGE3_MUX8 (0x00001f30) +#define HW_PXP_WFE_B_STAGE3_MUX8_SET (0x00001f34) +#define HW_PXP_WFE_B_STAGE3_MUX8_CLR (0x00001f38) +#define HW_PXP_WFE_B_STAGE3_MUX8_TOG (0x00001f3c) + +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX35 24 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX35 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX35(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX8_MUX35) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX34 16 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX34 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX34(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX8_MUX34) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX33 8 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX33 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX33(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX8_MUX33) +#define BP_PXP_WFE_B_STAGE3_MUX8_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX8_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX8_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX8_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX8_MUX32 0 +#define BM_PXP_WFE_B_STAGE3_MUX8_MUX32 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX8_MUX32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX8_MUX32) + +#define HW_PXP_WFE_B_STAGE3_MUX9 (0x00001f40) +#define HW_PXP_WFE_B_STAGE3_MUX9_SET (0x00001f44) +#define HW_PXP_WFE_B_STAGE3_MUX9_CLR (0x00001f48) +#define HW_PXP_WFE_B_STAGE3_MUX9_TOG (0x00001f4c) + +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX39 24 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX39 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX39(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX9_MUX39) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX38 16 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX38 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX38(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX9_MUX38) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX37 8 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX37 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX37(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX9_MUX37) +#define BP_PXP_WFE_B_STAGE3_MUX9_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX9_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX9_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX9_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX9_MUX36 0 +#define BM_PXP_WFE_B_STAGE3_MUX9_MUX36 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX9_MUX36(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX9_MUX36) + +#define HW_PXP_WFE_B_STAGE3_MUX10 (0x00001f50) +#define HW_PXP_WFE_B_STAGE3_MUX10_SET (0x00001f54) +#define HW_PXP_WFE_B_STAGE3_MUX10_CLR (0x00001f58) +#define HW_PXP_WFE_B_STAGE3_MUX10_TOG (0x00001f5c) + +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD0 30 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD0) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX43 24 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX43 0x3F000000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX43(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE3_MUX10_MUX43) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD1 22 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD1) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX42 16 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX42 0x003F0000 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX42(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE3_MUX10_MUX42) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD2 14 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD2) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX41 8 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX41 0x00003F00 +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX41(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE3_MUX10_MUX41) +#define BP_PXP_WFE_B_STAGE3_MUX10_RSVD3 6 +#define BM_PXP_WFE_B_STAGE3_MUX10_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STAGE3_MUX10_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE3_MUX10_RSVD3) +#define BP_PXP_WFE_B_STAGE3_MUX10_MUX40 0 +#define BM_PXP_WFE_B_STAGE3_MUX10_MUX40 0x0000003F +#define BF_PXP_WFE_B_STAGE3_MUX10_MUX40(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE3_MUX10_MUX40) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_0 (0x00001f60) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_1 (0x00001f70) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_2 (0x00001f80) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_3 (0x00001f90) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_4 (0x00001fa0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_5 (0x00001fb0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_6 (0x00001fc0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT0_7 (0x00001fd0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_0 (0x00001fe0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_1 (0x00001ff0) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_2 (0x00002000) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_3 (0x00002010) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_4 (0x00002020) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_5 (0x00002030) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_6 (0x00002040) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG1_5X8_OUT1_7 (0x00002050) + +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31 0xFF000000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30 0x00FF0000 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29 0x0000FF00 +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28 0x000000FF +#define BF_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE1_5X8_MASKS_0 (0x00002060) + +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 13 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2 0xFFFFE000 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 5 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3 0x000000E0 +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STG1_5X1_OUT0 (0x00002070) + +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_5X1_MASKS (0x00002080) + +#define BP_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0 0xFFFFFFE0 +#define BF_PXP_WFE_B_STG1_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG1_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_0 (0x00002090) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_1 (0x000020a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_2 (0x000020b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_3 (0x000020c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_4 (0x000020d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_5 (0x000020e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_6 (0x000020f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT0_7 (0x00002100) + +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_0 (0x00002110) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_1 (0x00002120) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_2 (0x00002130) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_3 (0x00002140) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_4 (0x00002150) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_5 (0x00002160) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_6 (0x00002170) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT1_7 (0x00002180) + +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_0 (0x00002190) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_1 (0x000021a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_2 (0x000021b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_3 (0x000021c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_4 (0x000021d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_5 (0x000021e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_6 (0x000021f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT2_7 (0x00002200) + +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_0 (0x00002210) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_1 (0x00002220) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_2 (0x00002230) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_3 (0x00002240) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_4 (0x00002250) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_5 (0x00002260) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_6 (0x00002270) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT3_7 (0x00002280) + +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_0 (0x00002290) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_1 (0x000022a0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_2 (0x000022b0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_3 (0x000022c0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_4 (0x000022d0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_5 (0x000022e0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_6 (0x000022f0) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG1_8X1_OUT4_7 (0x00002300) + +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225) +#define BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_0 (0x00002310) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_1 (0x00002320) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_2 (0x00002330) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_3 (0x00002340) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_4 (0x00002350) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_5 (0x00002360) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_6 (0x00002370) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT0_7 (0x00002380) + +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_0 (0x00002390) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_1 (0x000023a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_2 (0x000023b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_3 (0x000023c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_4 (0x000023d0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_5 (0x000023e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_6 (0x000023f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT1_7 (0x00002400) + +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_0 (0x00002410) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_1 (0x00002420) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_2 (0x00002430) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_3 (0x00002440) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_4 (0x00002450) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_5 (0x00002460) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_6 (0x00002470) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT2_7 (0x00002480) + +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_0 (0x00002490) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_1 (0x000024a0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_2 (0x000024b0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_3 (0x000024c0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_4 (0x000024e0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_5 (0x000024f0) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_6 (0x00002500) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24) + +#define HW_PXP_WFE_B_STG2_5X6_OUT3_7 (0x00002510) + +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 30 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0 0xC0000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD0) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 24 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31 0x3F000000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 22 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1 0x00C00000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD1) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 16 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30 0x003F0000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 14 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2 0x0000C000 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD2) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 8 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29 0x00003F00 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 6 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3 0x000000C0 +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_RSVD3) +#define BP_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0 +#define BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28 0x0000003F +#define BF_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28) + +#define HW_PXP_WFE_B_STAGE2_5X6_MASKS_0 (0x00002520) + +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 29 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 21 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 13 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 5 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0 0x0000001F +#define BF_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0) + +#define HW_PXP_WFE_B_STAGE2_5X6_ADDR_0 (0x00002530) + +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 30 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3 0xC0000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3(v) \ + (((v) << 30) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 24 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3 0x3F000000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 22 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2 0x00C00000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2(v) \ + (((v) << 22) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 16 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2 0x003F0000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 14 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1 0x0000C000 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1(v) \ + (((v) << 14) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 8 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1 0x00003F00 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 6 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0 0x000000C0 +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0(v) \ + (((v) << 6) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_RSVD0) +#define BP_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0 +#define BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0 0x0000003F +#define BF_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT0 (0x00002540) + +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT1 (0x00002550) + +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT2 (0x00002560) + +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_OUT3 (0x00002570) + +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1) +#define BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0) + +#define HW_PXP_WFE_B_STG2_5X1_MASKS (0x00002580) + +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 29 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3 0xE0000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD3(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3 0x1F000000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 21 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2 0x00E00000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD2(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2 0x001F0000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 13 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1 0x0000E000 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD1(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1 0x00001F00 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 5 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0 0x000000E0 +#define BF_PXP_WFE_B_STG2_5X1_MASKS_RSVD0(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG2_5X1_MASKS_RSVD0) +#define BP_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0 0x0000001F +#define BF_PXP_WFE_B_STG2_5X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG2_5X1_MASKS_MASK0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_0 (0x00002590) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_1 (0x000025a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_2 (0x000025b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_3 (0x000025c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_4 (0x000025d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_5 (0x000025e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_6 (0x000025f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT0_7 (0x00002600) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_0 (0x00002610) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_1 (0x00002620) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_2 (0x00002630) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_3 (0x00002640) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_4 (0x00002650) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_5 (0x00002660) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_6 (0x00002670) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT1_7 (0x00002680) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_0 (0x00002690) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_1 (0x000026a0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_2 (0x000026b0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_3 (0x000026c0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_4 (0x000026d0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_5 (0x000026e0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_6 (0x000026f0) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT2_7 (0x00002700) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_0 (0x00002710) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_1 (0x00002720) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_2 (0x00002730) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_3 (0x00002740) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_4 (0x00002750) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_5 (0x00002760) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_6 (0x00002770) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192) + +#define HW_PXP_WFE_B_STG3_F8X1_OUT3_7 (0x00002780) + +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255 0x80000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(v) \ + (((v) << 31) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254 0x40000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(v) \ + (((v) << 30) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253 0x20000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(v) \ + (((v) << 29) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252 0x10000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(v) \ + (((v) << 28) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251 0x08000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(v) \ + (((v) << 27) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250 0x04000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(v) \ + (((v) << 26) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249 0x02000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(v) \ + (((v) << 25) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248 0x01000000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247 0x00800000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(v) \ + (((v) << 23) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246 0x00400000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(v) \ + (((v) << 22) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245 0x00200000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(v) \ + (((v) << 21) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244 0x00100000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(v) \ + (((v) << 20) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243 0x00080000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(v) \ + (((v) << 19) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242 0x00040000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(v) \ + (((v) << 18) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241 0x00020000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(v) \ + (((v) << 17) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240 0x00010000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239 0x00008000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(v) \ + (((v) << 15) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238 0x00004000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(v) \ + (((v) << 14) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237 0x00002000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(v) \ + (((v) << 13) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236 0x00001000 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(v) \ + (((v) << 12) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235 0x00000800 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(v) \ + (((v) << 11) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234 0x00000400 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(v) \ + (((v) << 10) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233 0x00000200 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(v) \ + (((v) << 9) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232 0x00000100 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231 0x00000080 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(v) \ + (((v) << 7) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230 0x00000040 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(v) \ + (((v) << 6) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229 0x00000020 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(v) \ + (((v) << 5) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228 0x00000010 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(v) \ + (((v) << 4) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227 0x00000008 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(v) \ + (((v) << 3) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226 0x00000004 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(v) \ + (((v) << 2) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225 0x00000002 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(v) \ + (((v) << 1) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225) +#define BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224 0x00000001 +#define BF_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224) + +#define HW_PXP_WFE_B_STG3_F8X1_MASKS (0x00002790) + +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 24 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3 0xFF000000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK3(v) \ + (((v) << 24) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK3) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 16 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2 0x00FF0000 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK2(v) \ + (((v) << 16) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK2) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 8 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1 0x0000FF00 +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK1(v) \ + (((v) << 8) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK1) +#define BP_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0 +#define BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0 0x000000FF +#define BF_PXP_WFE_B_STG3_F8X1_MASKS_MASK0(v) \ + (((v) << 0) & BM_PXP_WFE_B_STG3_F8X1_MASKS_MASK0) + +#define HW_PXP_ALU_A_CTRL (0x00002810) +#define HW_PXP_ALU_A_CTRL_SET (0x00002814) +#define HW_PXP_ALU_A_CTRL_CLR (0x00002818) +#define HW_PXP_ALU_A_CTRL_TOG (0x0000281c) + +#define BP_PXP_ALU_A_CTRL_RSVD0 29 +#define BM_PXP_ALU_A_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_A_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_A_CTRL_RSVD0) +#define BM_PXP_ALU_A_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_A_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_A_CTRL_DONE) +#define BP_PXP_ALU_A_CTRL_RSVD1 21 +#define BM_PXP_ALU_A_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_A_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_A_CTRL_RSVD1) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_A_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_A_CTRL_RSVD2 17 +#define BM_PXP_ALU_A_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_A_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_A_CTRL_RSVD2) +#define BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_A_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_A_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_A_CTRL_RSVD3 13 +#define BM_PXP_ALU_A_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_A_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_A_CTRL_RSVD3) +#define BM_PXP_ALU_A_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_A_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_A_CTRL_BYPASS) +#define BV_PXP_ALU_A_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_A_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_A_CTRL_RSVD4 9 +#define BM_PXP_ALU_A_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_A_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_A_CTRL_RSVD4) +#define BM_PXP_ALU_A_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_A_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_A_CTRL_SW_RESET) +#define BP_PXP_ALU_A_CTRL_RSVD5 5 +#define BM_PXP_ALU_A_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_A_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_A_CTRL_RSVD5) +#define BM_PXP_ALU_A_CTRL_START 0x00000010 +#define BF_PXP_ALU_A_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_A_CTRL_START) +#define BP_PXP_ALU_A_CTRL_RSVD6 1 +#define BM_PXP_ALU_A_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_A_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_A_CTRL_RSVD6) +#define BM_PXP_ALU_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_A_CTRL_ENABLE) +#define BV_PXP_ALU_A_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_A_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_A_BUF_SIZE (0x00002820) + +#define BP_PXP_ALU_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_A_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_A_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_A_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_A_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_A_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_A_INST_ENTRY (0x00002830) + +#define BP_PXP_ALU_A_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_A_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_A_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_A_PARAM (0x00002840) + +#define BP_PXP_ALU_A_PARAM_RSVD0 16 +#define BM_PXP_ALU_A_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_A_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_A_PARAM_RSVD0) +#define BP_PXP_ALU_A_PARAM_PARAM1 8 +#define BM_PXP_ALU_A_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_A_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_A_PARAM_PARAM1) +#define BP_PXP_ALU_A_PARAM_PARAM0 0 +#define BM_PXP_ALU_A_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_A_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_A_PARAM_PARAM0) + +#define HW_PXP_ALU_A_CONFIG (0x00002850) + +#define BP_PXP_ALU_A_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_A_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_A_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_A_LUT_CONFIG (0x00002860) +#define HW_PXP_ALU_A_LUT_CONFIG_SET (0x00002864) +#define HW_PXP_ALU_A_LUT_CONFIG_CLR (0x00002868) +#define HW_PXP_ALU_A_LUT_CONFIG_TOG (0x0000286c) + +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_A_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_A_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_A_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_A_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_A_LUT_CONFIG_MODE) +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_A_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_A_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_A_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_A_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_A_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_A_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_A_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_A_LUT_CONFIG_EN) + +#define HW_PXP_ALU_A_LUT_DATA0 (0x00002870) + +#define BP_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_A_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_A_LUT_DATA1 (0x00002880) + +#define BP_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_A_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_A_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_A_DBG (0x00002890) + +#define BP_PXP_ALU_A_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_A_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_A_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_A_DBG_DEBUG_SEL) +#define BP_PXP_ALU_A_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_A_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_A_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_A_DBG_DEBUG_VALUE) + +#define HW_PXP_ALU_B_CTRL (0x000028a0) +#define HW_PXP_ALU_B_CTRL_SET (0x000028a4) +#define HW_PXP_ALU_B_CTRL_CLR (0x000028a8) +#define HW_PXP_ALU_B_CTRL_TOG (0x000028ac) + +#define BP_PXP_ALU_B_CTRL_RSVD0 29 +#define BM_PXP_ALU_B_CTRL_RSVD0 0xE0000000 +#define BF_PXP_ALU_B_CTRL_RSVD0(v) \ + (((v) << 29) & BM_PXP_ALU_B_CTRL_RSVD0) +#define BM_PXP_ALU_B_CTRL_DONE 0x10000000 +#define BF_PXP_ALU_B_CTRL_DONE(v) \ + (((v) << 28) & BM_PXP_ALU_B_CTRL_DONE) +#define BP_PXP_ALU_B_CTRL_RSVD1 21 +#define BM_PXP_ALU_B_CTRL_RSVD1 0x0FE00000 +#define BF_PXP_ALU_B_CTRL_RSVD1(v) \ + (((v) << 21) & BM_PXP_ALU_B_CTRL_RSVD1) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_EN 0x00100000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_EN(v) \ + (((v) << 20) & BM_PXP_ALU_B_CTRL_DONE_IRQ_EN) +#define BP_PXP_ALU_B_CTRL_RSVD2 17 +#define BM_PXP_ALU_B_CTRL_RSVD2 0x000E0000 +#define BF_PXP_ALU_B_CTRL_RSVD2(v) \ + (((v) << 17) & BM_PXP_ALU_B_CTRL_RSVD2) +#define BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG 0x00010000 +#define BF_PXP_ALU_B_CTRL_DONE_IRQ_FLAG(v) \ + (((v) << 16) & BM_PXP_ALU_B_CTRL_DONE_IRQ_FLAG) +#define BP_PXP_ALU_B_CTRL_RSVD3 13 +#define BM_PXP_ALU_B_CTRL_RSVD3 0x0000E000 +#define BF_PXP_ALU_B_CTRL_RSVD3(v) \ + (((v) << 13) & BM_PXP_ALU_B_CTRL_RSVD3) +#define BM_PXP_ALU_B_CTRL_BYPASS 0x00001000 +#define BF_PXP_ALU_B_CTRL_BYPASS(v) \ + (((v) << 12) & BM_PXP_ALU_B_CTRL_BYPASS) +#define BV_PXP_ALU_B_CTRL_BYPASS__0 0x0 +#define BV_PXP_ALU_B_CTRL_BYPASS__1 0x1 +#define BP_PXP_ALU_B_CTRL_RSVD4 9 +#define BM_PXP_ALU_B_CTRL_RSVD4 0x00000E00 +#define BF_PXP_ALU_B_CTRL_RSVD4(v) \ + (((v) << 9) & BM_PXP_ALU_B_CTRL_RSVD4) +#define BM_PXP_ALU_B_CTRL_SW_RESET 0x00000100 +#define BF_PXP_ALU_B_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_ALU_B_CTRL_SW_RESET) +#define BP_PXP_ALU_B_CTRL_RSVD5 5 +#define BM_PXP_ALU_B_CTRL_RSVD5 0x000000E0 +#define BF_PXP_ALU_B_CTRL_RSVD5(v) \ + (((v) << 5) & BM_PXP_ALU_B_CTRL_RSVD5) +#define BM_PXP_ALU_B_CTRL_START 0x00000010 +#define BF_PXP_ALU_B_CTRL_START(v) \ + (((v) << 4) & BM_PXP_ALU_B_CTRL_START) +#define BP_PXP_ALU_B_CTRL_RSVD6 1 +#define BM_PXP_ALU_B_CTRL_RSVD6 0x0000000E +#define BF_PXP_ALU_B_CTRL_RSVD6(v) \ + (((v) << 1) & BM_PXP_ALU_B_CTRL_RSVD6) +#define BM_PXP_ALU_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_ALU_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_ALU_B_CTRL_ENABLE) +#define BV_PXP_ALU_B_CTRL_ENABLE__0 0x0 +#define BV_PXP_ALU_B_CTRL_ENABLE__1 0x1 + +#define HW_PXP_ALU_B_BUF_SIZE (0x000028b0) + +#define BP_PXP_ALU_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_ALU_B_BUF_SIZE_RSVD0) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 16 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT 0x0FFF0000 +#define BF_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(v) \ + (((v) << 16) & BM_PXP_ALU_B_BUF_SIZE_BUF_HEIGHT) +#define BP_PXP_ALU_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_ALU_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_ALU_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_ALU_B_BUF_SIZE_RSVD1) +#define BP_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0 +#define BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH 0x00000FFF +#define BF_PXP_ALU_B_BUF_SIZE_BUF_WIDTH(v) \ + (((v) << 0) & BM_PXP_ALU_B_BUF_SIZE_BUF_WIDTH) + +#define HW_PXP_ALU_B_INST_ENTRY (0x000028c0) + +#define BP_PXP_ALU_B_INST_ENTRY_RSVD0 16 +#define BM_PXP_ALU_B_INST_ENTRY_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_INST_ENTRY_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_INST_ENTRY_RSVD0) +#define BP_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0 +#define BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR 0x0000FFFF +#define BF_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(v) \ + (((v) << 0) & BM_PXP_ALU_B_INST_ENTRY_ENTRY_ADDR) + +#define HW_PXP_ALU_B_PARAM (0x000028d0) + +#define BP_PXP_ALU_B_PARAM_RSVD0 16 +#define BM_PXP_ALU_B_PARAM_RSVD0 0xFFFF0000 +#define BF_PXP_ALU_B_PARAM_RSVD0(v) \ + (((v) << 16) & BM_PXP_ALU_B_PARAM_RSVD0) +#define BP_PXP_ALU_B_PARAM_PARAM1 8 +#define BM_PXP_ALU_B_PARAM_PARAM1 0x0000FF00 +#define BF_PXP_ALU_B_PARAM_PARAM1(v) \ + (((v) << 8) & BM_PXP_ALU_B_PARAM_PARAM1) +#define BP_PXP_ALU_B_PARAM_PARAM0 0 +#define BM_PXP_ALU_B_PARAM_PARAM0 0x000000FF +#define BF_PXP_ALU_B_PARAM_PARAM0(v) \ + (((v) << 0) & BM_PXP_ALU_B_PARAM_PARAM0) + +#define HW_PXP_ALU_B_CONFIG (0x000028e0) + +#define BP_PXP_ALU_B_CONFIG_BUF_ADDR 0 +#define BM_PXP_ALU_B_CONFIG_BUF_ADDR 0xFFFFFFFF +#define BF_PXP_ALU_B_CONFIG_BUF_ADDR(v) (v) + +#define HW_PXP_ALU_B_LUT_CONFIG (0x000028f0) +#define HW_PXP_ALU_B_LUT_CONFIG_SET (0x000028f4) +#define HW_PXP_ALU_B_LUT_CONFIG_CLR (0x000028f8) +#define HW_PXP_ALU_B_LUT_CONFIG_TOG (0x000028fc) + +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD0 6 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD0 0xFFFFFFC0 +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD0(v) \ + (((v) << 6) & BM_PXP_ALU_B_LUT_CONFIG_RSVD0) +#define BP_PXP_ALU_B_LUT_CONFIG_MODE 4 +#define BM_PXP_ALU_B_LUT_CONFIG_MODE 0x00000030 +#define BF_PXP_ALU_B_LUT_CONFIG_MODE(v) \ + (((v) << 4) & BM_PXP_ALU_B_LUT_CONFIG_MODE) +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__0 0x0 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__1 0x1 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__2 0x2 +#define BV_PXP_ALU_B_LUT_CONFIG_MODE__3 0x3 +#define BP_PXP_ALU_B_LUT_CONFIG_RSVD1 1 +#define BM_PXP_ALU_B_LUT_CONFIG_RSVD1 0x0000000E +#define BF_PXP_ALU_B_LUT_CONFIG_RSVD1(v) \ + (((v) << 1) & BM_PXP_ALU_B_LUT_CONFIG_RSVD1) +#define BM_PXP_ALU_B_LUT_CONFIG_EN 0x00000001 +#define BF_PXP_ALU_B_LUT_CONFIG_EN(v) \ + (((v) << 0) & BM_PXP_ALU_B_LUT_CONFIG_EN) + +#define HW_PXP_ALU_B_LUT_DATA0 (0x00002900) + +#define BP_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0 +#define BM_PXP_ALU_B_LUT_DATA0_LUT_DATA_L 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA0_LUT_DATA_L(v) (v) + +#define HW_PXP_ALU_B_LUT_DATA1 (0x00002910) + +#define BP_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0 +#define BM_PXP_ALU_B_LUT_DATA1_LUT_DATA_H 0xFFFFFFFF +#define BF_PXP_ALU_B_LUT_DATA1_LUT_DATA_H(v) (v) + +#define HW_PXP_ALU_B_DBG (0x00002920) + +#define BP_PXP_ALU_B_DBG_DEBUG_SEL 24 +#define BM_PXP_ALU_B_DBG_DEBUG_SEL 0xFF000000 +#define BF_PXP_ALU_B_DBG_DEBUG_SEL(v) \ + (((v) << 24) & BM_PXP_ALU_B_DBG_DEBUG_SEL) +#define BP_PXP_ALU_B_DBG_DEBUG_VALUE 0 +#define BM_PXP_ALU_B_DBG_DEBUG_VALUE 0x00FFFFFF +#define BF_PXP_ALU_B_DBG_DEBUG_VALUE(v) \ + (((v) << 0) & BM_PXP_ALU_B_DBG_DEBUG_VALUE) + +#define HW_PXP_HIST_A_CTRL (0x00002a00) + +#define BP_PXP_HIST_A_CTRL_RSVD4 27 +#define BM_PXP_HIST_A_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_A_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_A_CTRL_RSVD4) +#define BP_PXP_HIST_A_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_A_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_A_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_A_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_A_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_A_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_A_CTRL_RSVD3) +#define BP_PXP_HIST_A_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_A_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_A_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_A_CTRL_RSVD2 13 +#define BM_PXP_HIST_A_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_A_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_A_CTRL_RSVD2) +#define BP_PXP_HIST_A_CTRL_STATUS 8 +#define BM_PXP_HIST_A_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_A_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_A_CTRL_STATUS) +#define BP_PXP_HIST_A_CTRL_RSVD1 5 +#define BM_PXP_HIST_A_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_A_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_A_CTRL_RSVD1) +#define BM_PXP_HIST_A_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_A_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_A_CTRL_CLEAR) +#define BP_PXP_HIST_A_CTRL_RSVD0 1 +#define BM_PXP_HIST_A_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_A_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_CTRL_RSVD0) +#define BM_PXP_HIST_A_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_A_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_A_CTRL_ENABLE) + +#define HW_PXP_HIST_A_MASK (0x00002a10) + +#define BP_PXP_HIST_A_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_A_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_A_MASK_MASK_VALUE1) +#define BP_PXP_HIST_A_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_A_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_A_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_A_MASK_MASK_VALUE0) +#define BP_PXP_HIST_A_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_A_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_A_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_A_MASK_MASK_WIDTH) +#define BP_PXP_HIST_A_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_A_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_A_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_A_MASK_MASK_OFFSET) +#define BP_PXP_HIST_A_MASK_MASK_MODE 4 +#define BM_PXP_HIST_A_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_A_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_A_MASK_MASK_MODE) +#define BV_PXP_HIST_A_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_A_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_A_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_A_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_A_MASK_RSVD0 1 +#define BM_PXP_HIST_A_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_A_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_A_MASK_RSVD0) +#define BM_PXP_HIST_A_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_A_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_A_MASK_MASK_EN) + +#define HW_PXP_HIST_A_BUF_SIZE (0x00002a20) + +#define BP_PXP_HIST_A_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_A_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_A_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_A_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_A_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_A_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_A_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_A_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_A_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_A_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_A_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_A_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_A_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_A_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_A_TOTAL_PIXEL (0x00002a30) + +#define BP_PXP_HIST_A_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_A_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_A_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_A_ACTIVE_AREA_X (0x00002a40) + +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_A_ACTIVE_AREA_Y (0x00002a50) + +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_A_RAW_STAT0 (0x00002a60) + +#define BP_PXP_HIST_A_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_A_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_A_RAW_STAT1 (0x00002a70) + +#define BP_PXP_HIST_A_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_A_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_A_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST_B_CTRL (0x00002a80) + +#define BP_PXP_HIST_B_CTRL_RSVD4 27 +#define BM_PXP_HIST_B_CTRL_RSVD4 0xF8000000 +#define BF_PXP_HIST_B_CTRL_RSVD4(v) \ + (((v) << 27) & BM_PXP_HIST_B_CTRL_RSVD4) +#define BP_PXP_HIST_B_CTRL_PIXEL_WIDTH 24 +#define BM_PXP_HIST_B_CTRL_PIXEL_WIDTH 0x07000000 +#define BF_PXP_HIST_B_CTRL_PIXEL_WIDTH(v) \ + (((v) << 24) & BM_PXP_HIST_B_CTRL_PIXEL_WIDTH) +#define BM_PXP_HIST_B_CTRL_RSVD3 0x00800000 +#define BF_PXP_HIST_B_CTRL_RSVD3(v) \ + (((v) << 23) & BM_PXP_HIST_B_CTRL_RSVD3) +#define BP_PXP_HIST_B_CTRL_PIXEL_OFFSET 16 +#define BM_PXP_HIST_B_CTRL_PIXEL_OFFSET 0x007F0000 +#define BF_PXP_HIST_B_CTRL_PIXEL_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_CTRL_PIXEL_OFFSET) +#define BP_PXP_HIST_B_CTRL_RSVD2 13 +#define BM_PXP_HIST_B_CTRL_RSVD2 0x0000E000 +#define BF_PXP_HIST_B_CTRL_RSVD2(v) \ + (((v) << 13) & BM_PXP_HIST_B_CTRL_RSVD2) +#define BP_PXP_HIST_B_CTRL_STATUS 8 +#define BM_PXP_HIST_B_CTRL_STATUS 0x00001F00 +#define BF_PXP_HIST_B_CTRL_STATUS(v) \ + (((v) << 8) & BM_PXP_HIST_B_CTRL_STATUS) +#define BP_PXP_HIST_B_CTRL_RSVD1 5 +#define BM_PXP_HIST_B_CTRL_RSVD1 0x000000E0 +#define BF_PXP_HIST_B_CTRL_RSVD1(v) \ + (((v) << 5) & BM_PXP_HIST_B_CTRL_RSVD1) +#define BM_PXP_HIST_B_CTRL_CLEAR 0x00000010 +#define BF_PXP_HIST_B_CTRL_CLEAR(v) \ + (((v) << 4) & BM_PXP_HIST_B_CTRL_CLEAR) +#define BP_PXP_HIST_B_CTRL_RSVD0 1 +#define BM_PXP_HIST_B_CTRL_RSVD0 0x0000000E +#define BF_PXP_HIST_B_CTRL_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_CTRL_RSVD0) +#define BM_PXP_HIST_B_CTRL_ENABLE 0x00000001 +#define BF_PXP_HIST_B_CTRL_ENABLE(v) \ + (((v) << 0) & BM_PXP_HIST_B_CTRL_ENABLE) + +#define HW_PXP_HIST_B_MASK (0x00002a90) + +#define BP_PXP_HIST_B_MASK_MASK_VALUE1 24 +#define BM_PXP_HIST_B_MASK_MASK_VALUE1 0xFF000000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE1(v) \ + (((v) << 24) & BM_PXP_HIST_B_MASK_MASK_VALUE1) +#define BP_PXP_HIST_B_MASK_MASK_VALUE0 16 +#define BM_PXP_HIST_B_MASK_MASK_VALUE0 0x00FF0000 +#define BF_PXP_HIST_B_MASK_MASK_VALUE0(v) \ + (((v) << 16) & BM_PXP_HIST_B_MASK_MASK_VALUE0) +#define BP_PXP_HIST_B_MASK_MASK_WIDTH 13 +#define BM_PXP_HIST_B_MASK_MASK_WIDTH 0x0000E000 +#define BF_PXP_HIST_B_MASK_MASK_WIDTH(v) \ + (((v) << 13) & BM_PXP_HIST_B_MASK_MASK_WIDTH) +#define BP_PXP_HIST_B_MASK_MASK_OFFSET 6 +#define BM_PXP_HIST_B_MASK_MASK_OFFSET 0x00001FC0 +#define BF_PXP_HIST_B_MASK_MASK_OFFSET(v) \ + (((v) << 6) & BM_PXP_HIST_B_MASK_MASK_OFFSET) +#define BP_PXP_HIST_B_MASK_MASK_MODE 4 +#define BM_PXP_HIST_B_MASK_MASK_MODE 0x00000030 +#define BF_PXP_HIST_B_MASK_MASK_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_B_MASK_MASK_MODE) +#define BV_PXP_HIST_B_MASK_MASK_MODE__EQUAL 0x0 +#define BV_PXP_HIST_B_MASK_MASK_MODE__NOT_EQUAL 0x1 +#define BV_PXP_HIST_B_MASK_MASK_MODE__INSIDE 0x2 +#define BV_PXP_HIST_B_MASK_MASK_MODE__OUTSIDE 0x3 +#define BP_PXP_HIST_B_MASK_RSVD0 1 +#define BM_PXP_HIST_B_MASK_RSVD0 0x0000000E +#define BF_PXP_HIST_B_MASK_RSVD0(v) \ + (((v) << 1) & BM_PXP_HIST_B_MASK_RSVD0) +#define BM_PXP_HIST_B_MASK_MASK_EN 0x00000001 +#define BF_PXP_HIST_B_MASK_MASK_EN(v) \ + (((v) << 0) & BM_PXP_HIST_B_MASK_MASK_EN) + +#define HW_PXP_HIST_B_BUF_SIZE (0x00002aa0) + +#define BP_PXP_HIST_B_BUF_SIZE_RSVD0 28 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD0 0xF0000000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD0(v) \ + (((v) << 28) & BM_PXP_HIST_B_BUF_SIZE_RSVD0) +#define BP_PXP_HIST_B_BUF_SIZE_HEIGHT 16 +#define BM_PXP_HIST_B_BUF_SIZE_HEIGHT 0x0FFF0000 +#define BF_PXP_HIST_B_BUF_SIZE_HEIGHT(v) \ + (((v) << 16) & BM_PXP_HIST_B_BUF_SIZE_HEIGHT) +#define BP_PXP_HIST_B_BUF_SIZE_RSVD1 12 +#define BM_PXP_HIST_B_BUF_SIZE_RSVD1 0x0000F000 +#define BF_PXP_HIST_B_BUF_SIZE_RSVD1(v) \ + (((v) << 12) & BM_PXP_HIST_B_BUF_SIZE_RSVD1) +#define BP_PXP_HIST_B_BUF_SIZE_WIDTH 0 +#define BM_PXP_HIST_B_BUF_SIZE_WIDTH 0x00000FFF +#define BF_PXP_HIST_B_BUF_SIZE_WIDTH(v) \ + (((v) << 0) & BM_PXP_HIST_B_BUF_SIZE_WIDTH) + +#define HW_PXP_HIST_B_TOTAL_PIXEL (0x00002ab0) + +#define BP_PXP_HIST_B_TOTAL_PIXEL_RSVD0 24 +#define BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0 0xFF000000 +#define BF_PXP_HIST_B_TOTAL_PIXEL_RSVD0(v) \ + (((v) << 24) & BM_PXP_HIST_B_TOTAL_PIXEL_RSVD0) +#define BP_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0 +#define BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL 0x00FFFFFF +#define BF_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(v) \ + (((v) << 0) & BM_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL) + +#define HW_PXP_HIST_B_ACTIVE_AREA_X (0x00002ac0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_X_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_X_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET) + +#define HW_PXP_HIST_B_ACTIVE_AREA_Y (0x00002ad0) + +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 28 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1 0xF0000000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(v) \ + (((v) << 28) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 16 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET 0x0FFF0000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(v) \ + (((v) << 16) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 12 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0 0x0000F000 +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(v) \ + (((v) << 12) & BM_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0) +#define BP_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0 +#define BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET 0x00000FFF +#define BF_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET) + +#define HW_PXP_HIST_B_RAW_STAT0 (0x00002ae0) + +#define BP_PXP_HIST_B_RAW_STAT0_STAT0 0 +#define BM_PXP_HIST_B_RAW_STAT0_STAT0 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT0_STAT0(v) (v) + +#define HW_PXP_HIST_B_RAW_STAT1 (0x00002af0) + +#define BP_PXP_HIST_B_RAW_STAT1_STAT1 0 +#define BM_PXP_HIST_B_RAW_STAT1_STAT1 0xFFFFFFFF +#define BF_PXP_HIST_B_RAW_STAT1_STAT1(v) (v) + +#define HW_PXP_HIST2_PARAM (0x00002b00) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 14 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 6 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x00002b10) + +#define BP_PXP_HIST4_PARAM_RSVD3 30 +#define BM_PXP_HIST4_PARAM_RSVD3 0xC0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x3F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 22 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00C00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x003F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 14 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000C000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00003F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 6 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000C0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000003F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x00002b20) + +#define BP_PXP_HIST8_PARAM0_RSVD3 30 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 22 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 14 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 6 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x00002b30) + +#define BP_PXP_HIST8_PARAM1_RSVD7 30 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 22 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 14 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 6 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x00002b40) + +#define BP_PXP_HIST16_PARAM0_RSVD3 30 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 22 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 14 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 6 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x00002b50) + +#define BP_PXP_HIST16_PARAM1_RSVD7 30 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 22 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 14 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 6 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00002b60) + +#define BP_PXP_HIST16_PARAM2_RSVD11 30 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 22 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 14 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 6 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00002b70) + +#define BP_PXP_HIST16_PARAM3_RSVD15 30 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 22 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 14 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 6 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM0 (0x00002b80) + +#define BP_PXP_HIST32_PARAM0_RSVD3 30 +#define BM_PXP_HIST32_PARAM0_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM0_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM0_RSVD3) +#define BP_PXP_HIST32_PARAM0_VALUE3 24 +#define BM_PXP_HIST32_PARAM0_VALUE3 0x3F000000 +#define BF_PXP_HIST32_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM0_VALUE3) +#define BP_PXP_HIST32_PARAM0_RSVD2 22 +#define BM_PXP_HIST32_PARAM0_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM0_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM0_RSVD2) +#define BP_PXP_HIST32_PARAM0_VALUE2 16 +#define BM_PXP_HIST32_PARAM0_VALUE2 0x003F0000 +#define BF_PXP_HIST32_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM0_VALUE2) +#define BP_PXP_HIST32_PARAM0_RSVD1 14 +#define BM_PXP_HIST32_PARAM0_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM0_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM0_RSVD1) +#define BP_PXP_HIST32_PARAM0_VALUE1 8 +#define BM_PXP_HIST32_PARAM0_VALUE1 0x00003F00 +#define BF_PXP_HIST32_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM0_VALUE1) +#define BP_PXP_HIST32_PARAM0_RSVD0 6 +#define BM_PXP_HIST32_PARAM0_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM0_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM0_RSVD0) +#define BP_PXP_HIST32_PARAM0_VALUE0 0 +#define BM_PXP_HIST32_PARAM0_VALUE0 0x0000003F +#define BF_PXP_HIST32_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM0_VALUE0) + +#define HW_PXP_HIST32_PARAM1 (0x00002b90) + +#define BP_PXP_HIST32_PARAM1_RSVD7 30 +#define BM_PXP_HIST32_PARAM1_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM1_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM1_RSVD7) +#define BP_PXP_HIST32_PARAM1_VALUE7 24 +#define BM_PXP_HIST32_PARAM1_VALUE7 0x3F000000 +#define BF_PXP_HIST32_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM1_VALUE7) +#define BP_PXP_HIST32_PARAM1_RSVD6 22 +#define BM_PXP_HIST32_PARAM1_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM1_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM1_RSVD6) +#define BP_PXP_HIST32_PARAM1_VALUE6 16 +#define BM_PXP_HIST32_PARAM1_VALUE6 0x003F0000 +#define BF_PXP_HIST32_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM1_VALUE6) +#define BP_PXP_HIST32_PARAM1_RSVD5 14 +#define BM_PXP_HIST32_PARAM1_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM1_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM1_RSVD5) +#define BP_PXP_HIST32_PARAM1_VALUE5 8 +#define BM_PXP_HIST32_PARAM1_VALUE5 0x00003F00 +#define BF_PXP_HIST32_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM1_VALUE5) +#define BP_PXP_HIST32_PARAM1_RSVD4 6 +#define BM_PXP_HIST32_PARAM1_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM1_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM1_RSVD4) +#define BP_PXP_HIST32_PARAM1_VALUE4 0 +#define BM_PXP_HIST32_PARAM1_VALUE4 0x0000003F +#define BF_PXP_HIST32_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM1_VALUE4) + +#define HW_PXP_HIST32_PARAM2 (0x00002ba0) + +#define BP_PXP_HIST32_PARAM2_RSVD11 30 +#define BM_PXP_HIST32_PARAM2_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM2_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM2_RSVD11) +#define BP_PXP_HIST32_PARAM2_VALUE11 24 +#define BM_PXP_HIST32_PARAM2_VALUE11 0x3F000000 +#define BF_PXP_HIST32_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM2_VALUE11) +#define BP_PXP_HIST32_PARAM2_RSVD10 22 +#define BM_PXP_HIST32_PARAM2_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM2_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM2_RSVD10) +#define BP_PXP_HIST32_PARAM2_VALUE10 16 +#define BM_PXP_HIST32_PARAM2_VALUE10 0x003F0000 +#define BF_PXP_HIST32_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM2_VALUE10) +#define BP_PXP_HIST32_PARAM2_RSVD9 14 +#define BM_PXP_HIST32_PARAM2_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM2_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM2_RSVD9) +#define BP_PXP_HIST32_PARAM2_VALUE9 8 +#define BM_PXP_HIST32_PARAM2_VALUE9 0x00003F00 +#define BF_PXP_HIST32_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM2_VALUE9) +#define BP_PXP_HIST32_PARAM2_RSVD8 6 +#define BM_PXP_HIST32_PARAM2_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM2_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM2_RSVD8) +#define BP_PXP_HIST32_PARAM2_VALUE8 0 +#define BM_PXP_HIST32_PARAM2_VALUE8 0x0000003F +#define BF_PXP_HIST32_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM2_VALUE8) + +#define HW_PXP_HIST32_PARAM3 (0x00002bb0) + +#define BP_PXP_HIST32_PARAM3_RSVD15 30 +#define BM_PXP_HIST32_PARAM3_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM3_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM3_RSVD15) +#define BP_PXP_HIST32_PARAM3_VALUE15 24 +#define BM_PXP_HIST32_PARAM3_VALUE15 0x3F000000 +#define BF_PXP_HIST32_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM3_VALUE15) +#define BP_PXP_HIST32_PARAM3_RSVD14 22 +#define BM_PXP_HIST32_PARAM3_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM3_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM3_RSVD14) +#define BP_PXP_HIST32_PARAM3_VALUE14 16 +#define BM_PXP_HIST32_PARAM3_VALUE14 0x003F0000 +#define BF_PXP_HIST32_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM3_VALUE14) +#define BP_PXP_HIST32_PARAM3_RSVD13 14 +#define BM_PXP_HIST32_PARAM3_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM3_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM3_RSVD13) +#define BP_PXP_HIST32_PARAM3_VALUE13 8 +#define BM_PXP_HIST32_PARAM3_VALUE13 0x00003F00 +#define BF_PXP_HIST32_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM3_VALUE13) +#define BP_PXP_HIST32_PARAM3_RSVD12 6 +#define BM_PXP_HIST32_PARAM3_RSVD12 0x000000C0 +#define BF_PXP_HIST32_PARAM3_RSVD12(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM3_RSVD12) +#define BP_PXP_HIST32_PARAM3_VALUE12 0 +#define BM_PXP_HIST32_PARAM3_VALUE12 0x0000003F +#define BF_PXP_HIST32_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM3_VALUE12) + +#define HW_PXP_HIST32_PARAM4 (0x00002bc0) + +#define BP_PXP_HIST32_PARAM4_RSVD3 30 +#define BM_PXP_HIST32_PARAM4_RSVD3 0xC0000000 +#define BF_PXP_HIST32_PARAM4_RSVD3(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM4_RSVD3) +#define BP_PXP_HIST32_PARAM4_VALUE19 24 +#define BM_PXP_HIST32_PARAM4_VALUE19 0x3F000000 +#define BF_PXP_HIST32_PARAM4_VALUE19(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM4_VALUE19) +#define BP_PXP_HIST32_PARAM4_RSVD2 22 +#define BM_PXP_HIST32_PARAM4_RSVD2 0x00C00000 +#define BF_PXP_HIST32_PARAM4_RSVD2(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM4_RSVD2) +#define BP_PXP_HIST32_PARAM4_VALUE18 16 +#define BM_PXP_HIST32_PARAM4_VALUE18 0x003F0000 +#define BF_PXP_HIST32_PARAM4_VALUE18(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM4_VALUE18) +#define BP_PXP_HIST32_PARAM4_RSVD1 14 +#define BM_PXP_HIST32_PARAM4_RSVD1 0x0000C000 +#define BF_PXP_HIST32_PARAM4_RSVD1(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM4_RSVD1) +#define BP_PXP_HIST32_PARAM4_VALUE17 8 +#define BM_PXP_HIST32_PARAM4_VALUE17 0x00003F00 +#define BF_PXP_HIST32_PARAM4_VALUE17(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM4_VALUE17) +#define BP_PXP_HIST32_PARAM4_RSVD0 6 +#define BM_PXP_HIST32_PARAM4_RSVD0 0x000000C0 +#define BF_PXP_HIST32_PARAM4_RSVD0(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM4_RSVD0) +#define BP_PXP_HIST32_PARAM4_VALUE16 0 +#define BM_PXP_HIST32_PARAM4_VALUE16 0x0000003F +#define BF_PXP_HIST32_PARAM4_VALUE16(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM4_VALUE16) + +#define HW_PXP_HIST32_PARAM5 (0x00002bd0) + +#define BP_PXP_HIST32_PARAM5_RSVD7 30 +#define BM_PXP_HIST32_PARAM5_RSVD7 0xC0000000 +#define BF_PXP_HIST32_PARAM5_RSVD7(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM5_RSVD7) +#define BP_PXP_HIST32_PARAM5_VALUE23 24 +#define BM_PXP_HIST32_PARAM5_VALUE23 0x3F000000 +#define BF_PXP_HIST32_PARAM5_VALUE23(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM5_VALUE23) +#define BP_PXP_HIST32_PARAM5_RSVD6 22 +#define BM_PXP_HIST32_PARAM5_RSVD6 0x00C00000 +#define BF_PXP_HIST32_PARAM5_RSVD6(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM5_RSVD6) +#define BP_PXP_HIST32_PARAM5_VALUE22 16 +#define BM_PXP_HIST32_PARAM5_VALUE22 0x003F0000 +#define BF_PXP_HIST32_PARAM5_VALUE22(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM5_VALUE22) +#define BP_PXP_HIST32_PARAM5_RSVD5 14 +#define BM_PXP_HIST32_PARAM5_RSVD5 0x0000C000 +#define BF_PXP_HIST32_PARAM5_RSVD5(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM5_RSVD5) +#define BP_PXP_HIST32_PARAM5_VALUE21 8 +#define BM_PXP_HIST32_PARAM5_VALUE21 0x00003F00 +#define BF_PXP_HIST32_PARAM5_VALUE21(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM5_VALUE21) +#define BP_PXP_HIST32_PARAM5_RSVD4 6 +#define BM_PXP_HIST32_PARAM5_RSVD4 0x000000C0 +#define BF_PXP_HIST32_PARAM5_RSVD4(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM5_RSVD4) +#define BP_PXP_HIST32_PARAM5_VALUE20 0 +#define BM_PXP_HIST32_PARAM5_VALUE20 0x0000003F +#define BF_PXP_HIST32_PARAM5_VALUE20(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM5_VALUE20) + +#define HW_PXP_HIST32_PARAM6 (0x00002be0) + +#define BP_PXP_HIST32_PARAM6_RSVD11 30 +#define BM_PXP_HIST32_PARAM6_RSVD11 0xC0000000 +#define BF_PXP_HIST32_PARAM6_RSVD11(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM6_RSVD11) +#define BP_PXP_HIST32_PARAM6_VALUE27 24 +#define BM_PXP_HIST32_PARAM6_VALUE27 0x3F000000 +#define BF_PXP_HIST32_PARAM6_VALUE27(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM6_VALUE27) +#define BP_PXP_HIST32_PARAM6_RSVD10 22 +#define BM_PXP_HIST32_PARAM6_RSVD10 0x00C00000 +#define BF_PXP_HIST32_PARAM6_RSVD10(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM6_RSVD10) +#define BP_PXP_HIST32_PARAM6_VALUE26 16 +#define BM_PXP_HIST32_PARAM6_VALUE26 0x003F0000 +#define BF_PXP_HIST32_PARAM6_VALUE26(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM6_VALUE26) +#define BP_PXP_HIST32_PARAM6_RSVD9 14 +#define BM_PXP_HIST32_PARAM6_RSVD9 0x0000C000 +#define BF_PXP_HIST32_PARAM6_RSVD9(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM6_RSVD9) +#define BP_PXP_HIST32_PARAM6_VALUE25 8 +#define BM_PXP_HIST32_PARAM6_VALUE25 0x00003F00 +#define BF_PXP_HIST32_PARAM6_VALUE25(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM6_VALUE25) +#define BP_PXP_HIST32_PARAM6_RSVD8 6 +#define BM_PXP_HIST32_PARAM6_RSVD8 0x000000C0 +#define BF_PXP_HIST32_PARAM6_RSVD8(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM6_RSVD8) +#define BP_PXP_HIST32_PARAM6_VALUE24 0 +#define BM_PXP_HIST32_PARAM6_VALUE24 0x0000003F +#define BF_PXP_HIST32_PARAM6_VALUE24(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM6_VALUE24) + +#define HW_PXP_HIST32_PARAM7 (0x00002bf0) + +#define BP_PXP_HIST32_PARAM7_RSVD15 30 +#define BM_PXP_HIST32_PARAM7_RSVD15 0xC0000000 +#define BF_PXP_HIST32_PARAM7_RSVD15(v) \ + (((v) << 30) & BM_PXP_HIST32_PARAM7_RSVD15) +#define BP_PXP_HIST32_PARAM7_VALUE31 24 +#define BM_PXP_HIST32_PARAM7_VALUE31 0x3F000000 +#define BF_PXP_HIST32_PARAM7_VALUE31(v) \ + (((v) << 24) & BM_PXP_HIST32_PARAM7_VALUE31) +#define BP_PXP_HIST32_PARAM7_RSVD14 22 +#define BM_PXP_HIST32_PARAM7_RSVD14 0x00C00000 +#define BF_PXP_HIST32_PARAM7_RSVD14(v) \ + (((v) << 22) & BM_PXP_HIST32_PARAM7_RSVD14) +#define BP_PXP_HIST32_PARAM7_VALUE30 16 +#define BM_PXP_HIST32_PARAM7_VALUE30 0x003F0000 +#define BF_PXP_HIST32_PARAM7_VALUE30(v) \ + (((v) << 16) & BM_PXP_HIST32_PARAM7_VALUE30) +#define BP_PXP_HIST32_PARAM7_RSVD13 14 +#define BM_PXP_HIST32_PARAM7_RSVD13 0x0000C000 +#define BF_PXP_HIST32_PARAM7_RSVD13(v) \ + (((v) << 14) & BM_PXP_HIST32_PARAM7_RSVD13) +#define BP_PXP_HIST32_PARAM7_VALUE29 8 +#define BM_PXP_HIST32_PARAM7_VALUE29 0x00003F00 +#define BF_PXP_HIST32_PARAM7_VALUE29(v) \ + (((v) << 8) & BM_PXP_HIST32_PARAM7_VALUE29) +#define BP_PXP_HIST32_PARAM7_RSVD2 6 +#define BM_PXP_HIST32_PARAM7_RSVD2 0x000000C0 +#define BF_PXP_HIST32_PARAM7_RSVD2(v) \ + (((v) << 6) & BM_PXP_HIST32_PARAM7_RSVD2) +#define BP_PXP_HIST32_PARAM7_VALUE28 0 +#define BM_PXP_HIST32_PARAM7_VALUE28 0x0000003F +#define BF_PXP_HIST32_PARAM7_VALUE28(v) \ + (((v) << 0) & BM_PXP_HIST32_PARAM7_VALUE28) + +#define HW_PXP_COMP_CTRL (0x00002c00) +#define HW_PXP_COMP_CTRL_SET (0x00002c04) +#define HW_PXP_COMP_CTRL_CLR (0x00002c08) +#define HW_PXP_COMP_CTRL_TOG (0x00002c0c) + +#define BP_PXP_COMP_CTRL_RSVD0 9 +#define BM_PXP_COMP_CTRL_RSVD0 0xFFFFFE00 +#define BF_PXP_COMP_CTRL_RSVD0(v) \ + (((v) << 9) & BM_PXP_COMP_CTRL_RSVD0) +#define BM_PXP_COMP_CTRL_SW_RESET 0x00000100 +#define BF_PXP_COMP_CTRL_SW_RESET(v) \ + (((v) << 8) & BM_PXP_COMP_CTRL_SW_RESET) +#define BP_PXP_COMP_CTRL_RSVD1 1 +#define BM_PXP_COMP_CTRL_RSVD1 0x000000FE +#define BF_PXP_COMP_CTRL_RSVD1(v) \ + (((v) << 1) & BM_PXP_COMP_CTRL_RSVD1) +#define BM_PXP_COMP_CTRL_START 0x00000001 +#define BF_PXP_COMP_CTRL_START(v) \ + (((v) << 0) & BM_PXP_COMP_CTRL_START) + +#define HW_PXP_COMP_FORMAT0 (0x00002c10) +#define HW_PXP_COMP_FORMAT0_SET (0x00002c14) +#define HW_PXP_COMP_FORMAT0_CLR (0x00002c18) +#define HW_PXP_COMP_FORMAT0_TOG (0x00002c1c) + +#define BP_PXP_COMP_FORMAT0_RSVD0 28 +#define BM_PXP_COMP_FORMAT0_RSVD0 0xF0000000 +#define BF_PXP_COMP_FORMAT0_RSVD0(v) \ + (((v) << 28) & BM_PXP_COMP_FORMAT0_RSVD0) +#define BP_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 16 +#define BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B 0x0FFF0000 +#define BF_PXP_COMP_FORMAT0_PIXEL_PITCH_64B(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT0_PIXEL_PITCH_64B) +#define BP_PXP_COMP_FORMAT0_RSVD1 10 +#define BM_PXP_COMP_FORMAT0_RSVD1 0x0000FC00 +#define BF_PXP_COMP_FORMAT0_RSVD1(v) \ + (((v) << 10) & BM_PXP_COMP_FORMAT0_RSVD1) +#define BP_PXP_COMP_FORMAT0_MASK_INDEX 8 +#define BM_PXP_COMP_FORMAT0_MASK_INDEX 0x00000300 +#define BF_PXP_COMP_FORMAT0_MASK_INDEX(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT0_MASK_INDEX) +#define BP_PXP_COMP_FORMAT0_RSVD2 6 +#define BM_PXP_COMP_FORMAT0_RSVD2 0x000000C0 +#define BF_PXP_COMP_FORMAT0_RSVD2(v) \ + (((v) << 6) & BM_PXP_COMP_FORMAT0_RSVD2) +#define BP_PXP_COMP_FORMAT0_FIELD_NUM 4 +#define BM_PXP_COMP_FORMAT0_FIELD_NUM 0x00000030 +#define BF_PXP_COMP_FORMAT0_FIELD_NUM(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT0_FIELD_NUM) +#define BP_PXP_COMP_FORMAT0_RSVD3 1 +#define BM_PXP_COMP_FORMAT0_RSVD3 0x0000000E +#define BF_PXP_COMP_FORMAT0_RSVD3(v) \ + (((v) << 1) & BM_PXP_COMP_FORMAT0_RSVD3) +#define BM_PXP_COMP_FORMAT0_FLAG_32B 0x00000001 +#define BF_PXP_COMP_FORMAT0_FLAG_32B(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT0_FLAG_32B) + +#define HW_PXP_COMP_FORMAT1 (0x00002c20) + +#define BP_PXP_COMP_FORMAT1_D_LEN 29 +#define BM_PXP_COMP_FORMAT1_D_LEN 0xE0000000 +#define BF_PXP_COMP_FORMAT1_D_LEN(v) \ + (((v) << 29) & BM_PXP_COMP_FORMAT1_D_LEN) +#define BP_PXP_COMP_FORMAT1_D_OFFSET 24 +#define BM_PXP_COMP_FORMAT1_D_OFFSET 0x1F000000 +#define BF_PXP_COMP_FORMAT1_D_OFFSET(v) \ + (((v) << 24) & BM_PXP_COMP_FORMAT1_D_OFFSET) +#define BP_PXP_COMP_FORMAT1_C_LEN 21 +#define BM_PXP_COMP_FORMAT1_C_LEN 0x00E00000 +#define BF_PXP_COMP_FORMAT1_C_LEN(v) \ + (((v) << 21) & BM_PXP_COMP_FORMAT1_C_LEN) +#define BP_PXP_COMP_FORMAT1_C_OFFSET 16 +#define BM_PXP_COMP_FORMAT1_C_OFFSET 0x001F0000 +#define BF_PXP_COMP_FORMAT1_C_OFFSET(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT1_C_OFFSET) +#define BP_PXP_COMP_FORMAT1_B_LEN 13 +#define BM_PXP_COMP_FORMAT1_B_LEN 0x0000E000 +#define BF_PXP_COMP_FORMAT1_B_LEN(v) \ + (((v) << 13) & BM_PXP_COMP_FORMAT1_B_LEN) +#define BP_PXP_COMP_FORMAT1_B_OFFSET 8 +#define BM_PXP_COMP_FORMAT1_B_OFFSET 0x00001F00 +#define BF_PXP_COMP_FORMAT1_B_OFFSET(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT1_B_OFFSET) +#define BP_PXP_COMP_FORMAT1_A_LEN 5 +#define BM_PXP_COMP_FORMAT1_A_LEN 0x000000E0 +#define BF_PXP_COMP_FORMAT1_A_LEN(v) \ + (((v) << 5) & BM_PXP_COMP_FORMAT1_A_LEN) +#define BP_PXP_COMP_FORMAT1_A_OFFSET 0 +#define BM_PXP_COMP_FORMAT1_A_OFFSET 0x0000001F +#define BF_PXP_COMP_FORMAT1_A_OFFSET(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT1_A_OFFSET) + +#define HW_PXP_COMP_FORMAT2 (0x00002c30) + +#define BP_PXP_COMP_FORMAT2_RSVD 16 +#define BM_PXP_COMP_FORMAT2_RSVD 0xFFFF0000 +#define BF_PXP_COMP_FORMAT2_RSVD(v) \ + (((v) << 16) & BM_PXP_COMP_FORMAT2_RSVD) +#define BP_PXP_COMP_FORMAT2_D_RUNLEN 12 +#define BM_PXP_COMP_FORMAT2_D_RUNLEN 0x0000F000 +#define BF_PXP_COMP_FORMAT2_D_RUNLEN(v) \ + (((v) << 12) & BM_PXP_COMP_FORMAT2_D_RUNLEN) +#define BP_PXP_COMP_FORMAT2_C_RUNLEN 8 +#define BM_PXP_COMP_FORMAT2_C_RUNLEN 0x00000F00 +#define BF_PXP_COMP_FORMAT2_C_RUNLEN(v) \ + (((v) << 8) & BM_PXP_COMP_FORMAT2_C_RUNLEN) +#define BP_PXP_COMP_FORMAT2_B_RUNLEN 4 +#define BM_PXP_COMP_FORMAT2_B_RUNLEN 0x000000F0 +#define BF_PXP_COMP_FORMAT2_B_RUNLEN(v) \ + (((v) << 4) & BM_PXP_COMP_FORMAT2_B_RUNLEN) +#define BP_PXP_COMP_FORMAT2_A_RUNLEN 0 +#define BM_PXP_COMP_FORMAT2_A_RUNLEN 0x0000000F +#define BF_PXP_COMP_FORMAT2_A_RUNLEN(v) \ + (((v) << 0) & BM_PXP_COMP_FORMAT2_A_RUNLEN) + +#define HW_PXP_COMP_MASK0 (0x00002c40) + +#define BP_PXP_COMP_MASK0_VLD_MASK_LOW 0 +#define BM_PXP_COMP_MASK0_VLD_MASK_LOW 0xFFFFFFFF +#define BF_PXP_COMP_MASK0_VLD_MASK_LOW(v) (v) + +#define HW_PXP_COMP_MASK1 (0x00002c50) + +#define BP_PXP_COMP_MASK1_VLD_MASK_HIGH 0 +#define BM_PXP_COMP_MASK1_VLD_MASK_HIGH 0xFFFFFFFF +#define BF_PXP_COMP_MASK1_VLD_MASK_HIGH(v) (v) + +#define HW_PXP_COMP_BUFFER_SIZE (0x00002c60) + +#define BP_PXP_COMP_BUFFER_SIZE_RSVD0 29 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD0 0xE0000000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD0(v) \ + (((v) << 29) & BM_PXP_COMP_BUFFER_SIZE_RSVD0) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 16 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH 0x1FFF0000 +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(v) \ + (((v) << 16) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH) +#define BP_PXP_COMP_BUFFER_SIZE_RSVD1 13 +#define BM_PXP_COMP_BUFFER_SIZE_RSVD1 0x0000E000 +#define BF_PXP_COMP_BUFFER_SIZE_RSVD1(v) \ + (((v) << 13) & BM_PXP_COMP_BUFFER_SIZE_RSVD1) +#define BP_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0 +#define BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH 0x00001FFF +#define BF_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(v) \ + (((v) << 0) & BM_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH) + +#define HW_PXP_COMP_SOURCE (0x00002c70) + +#define BP_PXP_COMP_SOURCE_SOURCE_ADDR 0 +#define BM_PXP_COMP_SOURCE_SOURCE_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_SOURCE_SOURCE_ADDR(v) (v) + +#define HW_PXP_COMP_TARGET (0x00002c80) + +#define BP_PXP_COMP_TARGET_TARGET_ADDR 0 +#define BM_PXP_COMP_TARGET_TARGET_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_TARGET_TARGET_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_A (0x00002c90) + +#define BP_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_A_A_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_A_A_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_B (0x00002ca0) + +#define BP_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_B_B_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_B_B_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_C (0x00002cb0) + +#define BP_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_C_C_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_C_C_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_BUFFER_D (0x00002cc0) + +#define BP_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0 +#define BM_PXP_COMP_BUFFER_D_D_SRAM_ADDR 0xFFFFFFFF +#define BF_PXP_COMP_BUFFER_D_D_SRAM_ADDR(v) (v) + +#define HW_PXP_COMP_DEBUG (0x00002cd0) + +#define BP_PXP_COMP_DEBUG_DEBUG_VALUE 8 +#define BM_PXP_COMP_DEBUG_DEBUG_VALUE 0xFFFFFF00 +#define BF_PXP_COMP_DEBUG_DEBUG_VALUE(v) \ + (((v) << 8) & BM_PXP_COMP_DEBUG_DEBUG_VALUE) +#define BP_PXP_COMP_DEBUG_DEBUG_SEL 0 +#define BM_PXP_COMP_DEBUG_DEBUG_SEL 0x000000FF +#define BF_PXP_COMP_DEBUG_DEBUG_SEL(v) \ + (((v) << 0) & BM_PXP_COMP_DEBUG_DEBUG_SEL) + +#define HW_PXP_BUS_MUX (0x00002ce0) + +#define BP_PXP_BUS_MUX_RSVD1 24 +#define BM_PXP_BUS_MUX_RSVD1 0xFF000000 +#define BF_PXP_BUS_MUX_RSVD1(v) \ + (((v) << 24) & BM_PXP_BUS_MUX_RSVD1) +#define BP_PXP_BUS_MUX_WR_SEL 16 +#define BM_PXP_BUS_MUX_WR_SEL 0x00FF0000 +#define BF_PXP_BUS_MUX_WR_SEL(v) \ + (((v) << 16) & BM_PXP_BUS_MUX_WR_SEL) +#define BP_PXP_BUS_MUX_RSVD0 8 +#define BM_PXP_BUS_MUX_RSVD0 0x0000FF00 +#define BF_PXP_BUS_MUX_RSVD0(v) \ + (((v) << 8) & BM_PXP_BUS_MUX_RSVD0) +#define BP_PXP_BUS_MUX_RD_SEL 0 +#define BM_PXP_BUS_MUX_RD_SEL 0x000000FF +#define BF_PXP_BUS_MUX_RD_SEL(v) \ + (((v) << 0) & BM_PXP_BUS_MUX_RD_SEL) + +#define HW_PXP_HANDSHAKE_READY_MUX0 (0x00002cf0) + +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_READY_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_READY_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_READY_MUX1 (0x00002d00) + +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_READY_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_READY_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_READY_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_READY_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_READY_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_READY_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_READY_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_READY_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_READY_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_READY_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_READY_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_DONE_MUX0 (0x00002d10) + +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK7 28 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK7 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK7(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK7) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK6 24 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK6 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK6(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK6) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK5 20 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK5 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK5(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK5) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK4 16 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK4 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK4(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK4) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK3 12 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK3 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK3(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK3) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK2 8 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK2 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK2(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK2) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK1 4 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK1 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK1(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK1) +#define BP_PXP_HANDSHAKE_DONE_MUX0_HSK0 0 +#define BM_PXP_HANDSHAKE_DONE_MUX0_HSK0 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX0_HSK0(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX0_HSK0) + +#define HW_PXP_HANDSHAKE_DONE_MUX1 (0x00002d20) + +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK15 28 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK15 0xF0000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK15(v) \ + (((v) << 28) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK15) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK14 24 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK14 0x0F000000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK14(v) \ + (((v) << 24) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK14) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK13 20 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK13 0x00F00000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK13(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK13) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK12 16 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK12 0x000F0000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK12(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK12) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK11 12 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK11 0x0000F000 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK11(v) \ + (((v) << 12) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK11) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK10 8 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK10 0x00000F00 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK10(v) \ + (((v) << 8) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK10) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK9 4 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK9 0x000000F0 +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK9(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK9) +#define BP_PXP_HANDSHAKE_DONE_MUX1_HSK8 0 +#define BM_PXP_HANDSHAKE_DONE_MUX1_HSK8 0x0000000F +#define BF_PXP_HANDSHAKE_DONE_MUX1_HSK8(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_DONE_MUX1_HSK8) + +#define HW_PXP_HANDSHAKE_CPU_FETCH (0x00002d30) +#define HW_PXP_HANDSHAKE_CPU_FETCH_SET (0x00002d34) +#define HW_PXP_HANDSHAKE_CPU_FETCH_CLR (0x00002d38) +#define HW_PXP_HANDSHAKE_CPU_FETCH_TOG (0x00002d3c) + +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_FETCH_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_FETCH_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_FETCH_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY) + +#define HW_PXP_HANDSHAKE_CPU_STORE (0x00002d40) +#define HW_PXP_HANDSHAKE_CPU_STORE_SET (0x00002d44) +#define HW_PXP_HANDSHAKE_CPU_STORE_CLR (0x00002d48) +#define HW_PXP_HANDSHAKE_CPU_STORE_TOG (0x00002d4c) + +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN 0x80000000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN(v) \ + (((v) << 31) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD1 22 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD1 0x7FC00000 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD1(v) \ + (((v) << 22) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD1) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 20 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES 0x00300000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(v) \ + (((v) << 20) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE 0x00080000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE(v) \ + (((v) << 19) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE 0x00040000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE(v) \ + (((v) << 18) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY 0x00020000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY(v) \ + (((v) << 17) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY 0x00010000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY(v) \ + (((v) << 16) & BM_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN 0x00008000 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN(v) \ + (((v) << 15) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN) +#define BP_PXP_HANDSHAKE_CPU_STORE_RSVD0 6 +#define BM_PXP_HANDSHAKE_CPU_STORE_RSVD0 0x00007FC0 +#define BF_PXP_HANDSHAKE_CPU_STORE_RSVD0(v) \ + (((v) << 6) & BM_PXP_HANDSHAKE_CPU_STORE_RSVD0) +#define BP_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 4 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES 0x00000030 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(v) \ + (((v) << 4) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES) +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_4 0x0 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_8 0x1 +#define BV_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES__LINE_16 0x2 +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE 0x00000008 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE(v) \ + (((v) << 3) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE 0x00000004 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE(v) \ + (((v) << 2) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY 0x00000002 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY(v) \ + (((v) << 1) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY) +#define BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY 0x00000001 +#define BF_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY(v) \ + (((v) << 0) & BM_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY) +#endif /* __ARCH_ARM___PXP_H */ |