diff options
Diffstat (limited to 'drivers/hwmon/imx_ahci_hwmon.c')
| -rw-r--r-- | drivers/hwmon/imx_ahci_hwmon.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/hwmon/imx_ahci_hwmon.c b/drivers/hwmon/imx_ahci_hwmon.c index 073a2d1697dc..030c455798b8 100644 --- a/drivers/hwmon/imx_ahci_hwmon.c +++ b/drivers/hwmon/imx_ahci_hwmon.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,7 +57,7 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, { void __iomem *mmio; u32 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, adc_out_reg; - u32 str1, str2, str3, str4, read_sum, index; + u32 str1, str2, str3, str4, read_sum, index, port_phy_ctl; int m1, m2, a, temp, ret; struct clk *sata_clk, *sata_ref_clk; struct imx_ahci_hwmon *hwmon; @@ -89,6 +89,11 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, return -1; } + /* Disable PDDQ mode if it is enabled */ + port_phy_ctl = readl(mmio + PORT_PHY_CTL); + if (port_phy_ctl & PORT_PHY_CTL_PDDQ_LOC) + writel(port_phy_ctl & ~PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL); + /* check rd-wr to reg */ read_sum = 0; sata_phy_cr_addr(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio); @@ -229,6 +234,9 @@ static ssize_t imx_ahci_hwmon_temp_show(struct device *dev, a = (m2 - m1) / (m2 / 1000); temp = ((((-559) * a) / 1000) * a) / 1000 + (1379) * a / 1000 + (-458); + /* Set the Port Phy ctl back */ + writel(port_phy_ctl, mmio + PORT_PHY_CTL); + iounmap(mmio); /* Release the clocks */ |