diff options
Diffstat (limited to 'drivers/mailbox')
| -rw-r--r-- | drivers/mailbox/Kconfig | 37 | ||||
| -rw-r--r-- | drivers/mailbox/Makefile | 8 | ||||
| -rw-r--r-- | drivers/mailbox/hi6220-mailbox.c | 395 | ||||
| -rw-r--r-- | drivers/mailbox/mailbox-test.c | 53 | ||||
| -rw-r--r-- | drivers/mailbox/mailbox-xgene-slimpro.c | 284 | ||||
| -rw-r--r-- | drivers/mailbox/pcc.c | 111 | ||||
| -rw-r--r-- | drivers/mailbox/rockchip-mailbox.c | 283 | ||||
| -rw-r--r-- | drivers/mailbox/ti-msgmgr.c | 639 |
8 files changed, 1781 insertions, 29 deletions
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index b2bbe8659bed..5305923752d2 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -43,6 +43,15 @@ config OMAP_MBOX_KFIFO_SIZE This can also be changed at runtime (via the mbox_kfifo_size module parameter). +config ROCKCHIP_MBOX + bool "Rockchip Soc Intergrated Mailbox Support" + depends on ARCH_ROCKCHIP || COMPILE_TEST + help + This driver provides support for inter-processor communication + between CPU cores and MCU processor on Some Rockchip SOCs. + Please check it that the Soc you use have Mailbox hardware. + Say Y here if you want to use the Rockchip Mailbox support. + config PCC bool "Platform Communication Channel Driver" depends on ACPI @@ -78,6 +87,25 @@ config STI_MBOX Mailbox implementation for STMicroelectonics family chips with hardware for interprocessor communication. +config TI_MESSAGE_MANAGER + tristate "Texas Instruments Message Manager Driver" + depends on ARCH_KEYSTONE + help + An implementation of Message Manager slave driver for Keystone + architecture SoCs from Texas Instruments. Message Manager is a + communication entity found on few of Texas Instrument's keystone + architecture SoCs. These may be used for communication between + multiple processors within the SoC. Select this driver if your + platform has support for the hardware block. + +config HI6220_MBOX + tristate "Hi6220 Mailbox" + depends on ARCH_HISI + help + An implementation of the hi6220 mailbox. It is used to send message + between application processors and MCU. Say Y here if you want to + build Hi6220 mailbox controller driver. + config MAILBOX_TEST tristate "Mailbox Test Client" depends on OF @@ -86,4 +114,13 @@ config MAILBOX_TEST Test client to help with testing new Controller driver implementations. +config XGENE_SLIMPRO_MBOX + tristate "APM SoC X-Gene SLIMpro Mailbox Controller" + depends on ARCH_XGENE + help + An implementation of the APM X-Gene Interprocessor Communication + Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller. + It is used to send short messages between ARM64-bit cores and + the SLIMpro Management Engine, primarily for PM. Say Y here if you + want to use the APM X-Gene SLIMpro IPCM support. endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 92435ef11f26..0be3e742bb7d 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -10,6 +10,8 @@ obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mailbox.o +obj-$(CONFIG_ROCKCHIP_MBOX) += rockchip-mailbox.o + obj-$(CONFIG_PCC) += pcc.o obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o @@ -17,3 +19,9 @@ obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o obj-$(CONFIG_BCM2835_MBOX) += bcm2835-mailbox.o obj-$(CONFIG_STI_MBOX) += mailbox-sti.o + +obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o + +obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o + +obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o diff --git a/drivers/mailbox/hi6220-mailbox.c b/drivers/mailbox/hi6220-mailbox.c new file mode 100644 index 000000000000..613722db5daf --- /dev/null +++ b/drivers/mailbox/hi6220-mailbox.c @@ -0,0 +1,395 @@ +/* + * Hisilicon's Hi6220 mailbox driver + * + * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 Linaro Limited. + * + * Author: Leo Yan <leo.yan@linaro.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/device.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kfifo.h> +#include <linux/mailbox_controller.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#define MBOX_CHAN_MAX 32 + +#define MBOX_TX 0x1 + +/* Mailbox message length: 8 words */ +#define MBOX_MSG_LEN 8 + +/* Mailbox Registers */ +#define MBOX_OFF(m) (0x40 * (m)) +#define MBOX_MODE_REG(m) (MBOX_OFF(m) + 0x0) +#define MBOX_DATA_REG(m) (MBOX_OFF(m) + 0x4) + +#define MBOX_STATE_MASK (0xF << 4) +#define MBOX_STATE_IDLE (0x1 << 4) +#define MBOX_STATE_TX (0x2 << 4) +#define MBOX_STATE_RX (0x4 << 4) +#define MBOX_STATE_ACK (0x8 << 4) +#define MBOX_ACK_CONFIG_MASK (0x1 << 0) +#define MBOX_ACK_AUTOMATIC (0x1 << 0) +#define MBOX_ACK_IRQ (0x0 << 0) + +/* IPC registers */ +#define ACK_INT_RAW_REG(i) ((i) + 0x400) +#define ACK_INT_MSK_REG(i) ((i) + 0x404) +#define ACK_INT_STAT_REG(i) ((i) + 0x408) +#define ACK_INT_CLR_REG(i) ((i) + 0x40c) +#define ACK_INT_ENA_REG(i) ((i) + 0x500) +#define ACK_INT_DIS_REG(i) ((i) + 0x504) +#define DST_INT_RAW_REG(i) ((i) + 0x420) + + +struct hi6220_mbox_chan { + + /* + * Description for channel's hardware info: + * - direction: tx or rx + * - dst irq: peer core's irq number + * - ack irq: local irq number + * - slot number + */ + unsigned int dir, dst_irq, ack_irq; + unsigned int slot; + + struct hi6220_mbox *parent; +}; + +struct hi6220_mbox { + struct device *dev; + + int irq; + + /* flag of enabling tx's irq mode */ + bool tx_irq_mode; + + /* region for ipc event */ + void __iomem *ipc; + + /* region for mailbox */ + void __iomem *base; + + unsigned int chan_num; + struct hi6220_mbox_chan *mchan; + + void *irq_map_chan[MBOX_CHAN_MAX]; + struct mbox_chan *chan; + struct mbox_controller controller; +}; + +static void mbox_set_state(struct hi6220_mbox *mbox, + unsigned int slot, u32 val) +{ + u32 status; + + status = readl(mbox->base + MBOX_MODE_REG(slot)); + status = (status & ~MBOX_STATE_MASK) | val; + writel(status, mbox->base + MBOX_MODE_REG(slot)); +} + +static void mbox_set_mode(struct hi6220_mbox *mbox, + unsigned int slot, u32 val) +{ + u32 mode; + + mode = readl(mbox->base + MBOX_MODE_REG(slot)); + mode = (mode & ~MBOX_ACK_CONFIG_MASK) | val; + writel(mode, mbox->base + MBOX_MODE_REG(slot)); +} + +static bool hi6220_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + u32 state; + + /* Only set idle state for polling mode */ + BUG_ON(mbox->tx_irq_mode); + + state = readl(mbox->base + MBOX_MODE_REG(mchan->slot)); + return ((state & MBOX_STATE_MASK) == MBOX_STATE_IDLE); +} + +static int hi6220_mbox_send_data(struct mbox_chan *chan, void *msg) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + unsigned int slot = mchan->slot; + u32 *buf = msg; + int i; + + /* indicate as a TX channel */ + mchan->dir = MBOX_TX; + + mbox_set_state(mbox, slot, MBOX_STATE_TX); + + if (mbox->tx_irq_mode) + mbox_set_mode(mbox, slot, MBOX_ACK_IRQ); + else + mbox_set_mode(mbox, slot, MBOX_ACK_AUTOMATIC); + + for (i = 0; i < MBOX_MSG_LEN; i++) + writel(buf[i], mbox->base + MBOX_DATA_REG(slot) + i * 4); + + /* trigger remote request */ + writel(BIT(mchan->dst_irq), DST_INT_RAW_REG(mbox->ipc)); + return 0; +} + +static irqreturn_t hi6220_mbox_interrupt(int irq, void *p) +{ + struct hi6220_mbox *mbox = p; + struct hi6220_mbox_chan *mchan; + struct mbox_chan *chan; + unsigned int state, intr_bit, i; + u32 msg[MBOX_MSG_LEN]; + + state = readl(ACK_INT_STAT_REG(mbox->ipc)); + if (!state) { + dev_warn(mbox->dev, "%s: spurious interrupt\n", + __func__); + return IRQ_HANDLED; + } + + while (state) { + intr_bit = __ffs(state); + state &= (state - 1); + + chan = mbox->irq_map_chan[intr_bit]; + if (!chan) { + dev_warn(mbox->dev, "%s: unexpected irq vector %d\n", + __func__, intr_bit); + continue; + } + + mchan = chan->con_priv; + if (mchan->dir == MBOX_TX) + mbox_chan_txdone(chan, 0); + else { + for (i = 0; i < MBOX_MSG_LEN; i++) + msg[i] = readl(mbox->base + + MBOX_DATA_REG(mchan->slot) + i * 4); + + mbox_chan_received_data(chan, (void *)msg); + } + + /* clear IRQ source */ + writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc)); + mbox_set_state(mbox, mchan->slot, MBOX_STATE_IDLE); + } + + return IRQ_HANDLED; +} + +static int hi6220_mbox_startup(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + + mchan->dir = 0; + + /* enable interrupt */ + writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc)); + return 0; +} + +static void hi6220_mbox_shutdown(struct mbox_chan *chan) +{ + struct hi6220_mbox_chan *mchan = chan->con_priv; + struct hi6220_mbox *mbox = mchan->parent; + + /* disable interrupt */ + writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc)); + mbox->irq_map_chan[mchan->ack_irq] = NULL; +} + +static struct mbox_chan_ops hi6220_mbox_ops = { + .send_data = hi6220_mbox_send_data, + .startup = hi6220_mbox_startup, + .shutdown = hi6220_mbox_shutdown, + .last_tx_done = hi6220_mbox_last_tx_done, +}; + +static struct mbox_chan *hi6220_mbox_xlate(struct mbox_controller *controller, + const struct of_phandle_args *spec) +{ + struct hi6220_mbox *mbox = dev_get_drvdata(controller->dev); + struct hi6220_mbox_chan *mchan; + struct mbox_chan *chan; + unsigned int i = spec->args[0]; + unsigned int dst_irq = spec->args[1]; + unsigned int ack_irq = spec->args[2]; + + /* Bounds checking */ + if (i >= mbox->chan_num || dst_irq >= mbox->chan_num || + ack_irq >= mbox->chan_num) { + dev_err(mbox->dev, + "Invalid channel idx %d dst_irq %d ack_irq %d\n", + i, dst_irq, ack_irq); + return ERR_PTR(-EINVAL); + } + + /* Is requested channel free? */ + chan = &mbox->chan[i]; + if (mbox->irq_map_chan[ack_irq] == (void *)chan) { + dev_err(mbox->dev, "Channel in use\n"); + return ERR_PTR(-EBUSY); + } + + mchan = chan->con_priv; + mchan->dst_irq = dst_irq; + mchan->ack_irq = ack_irq; + + mbox->irq_map_chan[ack_irq] = (void *)chan; + return chan; +} + +static const struct of_device_id hi6220_mbox_of_match[] = { + { .compatible = "hisilicon,hi6220-mbox", }, + {}, +}; +MODULE_DEVICE_TABLE(of, hi6220_mbox_of_match); + +static int hi6220_mbox_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct hi6220_mbox *mbox; + struct resource *res; + int i, err; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + mbox->dev = dev; + mbox->chan_num = MBOX_CHAN_MAX; + mbox->mchan = devm_kzalloc(dev, + mbox->chan_num * sizeof(*mbox->mchan), GFP_KERNEL); + if (!mbox->mchan) + return -ENOMEM; + + mbox->chan = devm_kzalloc(dev, + mbox->chan_num * sizeof(*mbox->chan), GFP_KERNEL); + if (!mbox->chan) + return -ENOMEM; + + mbox->irq = platform_get_irq(pdev, 0); + if (mbox->irq < 0) + return mbox->irq; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox->ipc = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->ipc)) { + dev_err(dev, "ioremap ipc failed\n"); + return PTR_ERR(mbox->ipc); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + mbox->base = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->base)) { + dev_err(dev, "ioremap buffer failed\n"); + return PTR_ERR(mbox->base); + } + + err = devm_request_irq(dev, mbox->irq, hi6220_mbox_interrupt, 0, + dev_name(dev), mbox); + if (err) { + dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n", + err); + return -ENODEV; + } + + mbox->controller.dev = dev; + mbox->controller.chans = &mbox->chan[0]; + mbox->controller.num_chans = mbox->chan_num; + mbox->controller.ops = &hi6220_mbox_ops; + mbox->controller.of_xlate = hi6220_mbox_xlate; + + for (i = 0; i < mbox->chan_num; i++) { + mbox->chan[i].con_priv = &mbox->mchan[i]; + mbox->irq_map_chan[i] = NULL; + + mbox->mchan[i].parent = mbox; + mbox->mchan[i].slot = i; + } + + /* mask and clear all interrupt vectors */ + writel(0x0, ACK_INT_MSK_REG(mbox->ipc)); + writel(~0x0, ACK_INT_CLR_REG(mbox->ipc)); + + /* use interrupt for tx's ack */ + if (of_find_property(node, "hi6220,mbox-tx-noirq", NULL)) + mbox->tx_irq_mode = false; + else + mbox->tx_irq_mode = true; + + if (mbox->tx_irq_mode) + mbox->controller.txdone_irq = true; + else { + mbox->controller.txdone_poll = true; + mbox->controller.txpoll_period = 5; + } + + err = mbox_controller_register(&mbox->controller); + if (err) { + dev_err(dev, "Failed to register mailbox %d\n", err); + return err; + } + + platform_set_drvdata(pdev, mbox); + dev_info(dev, "Mailbox enabled\n"); + return 0; +} + +static int hi6220_mbox_remove(struct platform_device *pdev) +{ + struct hi6220_mbox *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(&mbox->controller); + return 0; +} + +static struct platform_driver hi6220_mbox_driver = { + .driver = { + .name = "hi6220-mbox", + .owner = THIS_MODULE, + .of_match_table = hi6220_mbox_of_match, + }, + .probe = hi6220_mbox_probe, + .remove = hi6220_mbox_remove, +}; + +static int __init hi6220_mbox_init(void) +{ + return platform_driver_register(&hi6220_mbox_driver); +} +core_initcall(hi6220_mbox_init); + +static void __exit hi6220_mbox_exit(void) +{ + platform_driver_unregister(&hi6220_mbox_driver); +} +module_exit(hi6220_mbox_exit); + +MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>"); +MODULE_DESCRIPTION("Hi6220 mailbox driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c index 684ae17dcf39..dc11bbf27274 100644 --- a/drivers/mailbox/mailbox-test.c +++ b/drivers/mailbox/mailbox-test.c @@ -31,7 +31,8 @@ static struct dentry *root_debugfs_dir; struct mbox_test_device { struct device *dev; - void __iomem *mmio; + void __iomem *tx_mmio; + void __iomem *rx_mmio; struct mbox_chan *tx_channel; struct mbox_chan *rx_channel; char *rx_buffer; @@ -112,16 +113,16 @@ static ssize_t mbox_test_message_write(struct file *filp, * A separate signal is only of use if there is * MMIO to subsequently pass the message through */ - if (tdev->mmio && tdev->signal) { - print_hex_dump(KERN_INFO, "Client: Sending: Signal: ", DUMP_PREFIX_ADDRESS, - MBOX_BYTES_PER_LINE, 1, tdev->signal, MBOX_MAX_SIG_LEN, true); + if (tdev->tx_mmio && tdev->signal) { + print_hex_dump_bytes("Client: Sending: Signal: ", DUMP_PREFIX_ADDRESS, + tdev->signal, MBOX_MAX_SIG_LEN); data = tdev->signal; } else data = tdev->message; - print_hex_dump(KERN_INFO, "Client: Sending: Message: ", DUMP_PREFIX_ADDRESS, - MBOX_BYTES_PER_LINE, 1, tdev->message, MBOX_MAX_MSG_LEN, true); + print_hex_dump_bytes("Client: Sending: Message: ", DUMP_PREFIX_ADDRESS, + tdev->message, MBOX_MAX_MSG_LEN); ret = mbox_send_message(tdev->tx_channel, data); if (ret < 0) @@ -220,15 +221,13 @@ static void mbox_test_receive_message(struct mbox_client *client, void *message) unsigned long flags; spin_lock_irqsave(&tdev->lock, flags); - if (tdev->mmio) { - memcpy_fromio(tdev->rx_buffer, tdev->mmio, MBOX_MAX_MSG_LEN); - print_hex_dump(KERN_INFO, "Client: Received [MMIO]: ", - DUMP_PREFIX_ADDRESS, MBOX_BYTES_PER_LINE, 1, - tdev->rx_buffer, MBOX_MAX_MSG_LEN, true); + if (tdev->rx_mmio) { + memcpy_fromio(tdev->rx_buffer, tdev->rx_mmio, MBOX_MAX_MSG_LEN); + print_hex_dump_bytes("Client: Received [MMIO]: ", DUMP_PREFIX_ADDRESS, + tdev->rx_buffer, MBOX_MAX_MSG_LEN); } else if (message) { - print_hex_dump(KERN_INFO, "Client: Received [API]: ", - DUMP_PREFIX_ADDRESS, MBOX_BYTES_PER_LINE, 1, - message, MBOX_MAX_MSG_LEN, true); + print_hex_dump_bytes("Client: Received [API]: ", DUMP_PREFIX_ADDRESS, + message, MBOX_MAX_MSG_LEN); memcpy(tdev->rx_buffer, message, MBOX_MAX_MSG_LEN); } spin_unlock_irqrestore(&tdev->lock, flags); @@ -238,11 +237,11 @@ static void mbox_test_prepare_message(struct mbox_client *client, void *message) { struct mbox_test_device *tdev = dev_get_drvdata(client->dev); - if (tdev->mmio) { + if (tdev->tx_mmio) { if (tdev->signal) - memcpy_toio(tdev->mmio, tdev->message, MBOX_MAX_MSG_LEN); + memcpy_toio(tdev->tx_mmio, tdev->message, MBOX_MAX_MSG_LEN); else - memcpy_toio(tdev->mmio, message, MBOX_MAX_MSG_LEN); + memcpy_toio(tdev->tx_mmio, message, MBOX_MAX_MSG_LEN); } } @@ -296,9 +295,15 @@ static int mbox_test_probe(struct platform_device *pdev) /* It's okay for MMIO to be NULL */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - tdev->mmio = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(tdev->mmio)) - tdev->mmio = NULL; + tdev->tx_mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tdev->tx_mmio)) + tdev->tx_mmio = NULL; + + /* If specified, second reg entry is Rx MMIO */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + tdev->rx_mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tdev->rx_mmio)) + tdev->rx_mmio = tdev->tx_mmio; tdev->tx_channel = mbox_test_request_channel(pdev, "tx"); tdev->rx_channel = mbox_test_request_channel(pdev, "rx"); @@ -306,6 +311,10 @@ static int mbox_test_probe(struct platform_device *pdev) if (!tdev->tx_channel && !tdev->rx_channel) return -EPROBE_DEFER; + /* If Rx is not specified but has Rx MMIO, then Rx = Tx */ + if (!tdev->rx_channel && (tdev->rx_mmio != tdev->tx_mmio)) + tdev->rx_channel = tdev->tx_channel; + tdev->dev = &pdev->dev; platform_set_drvdata(pdev, tdev); @@ -342,13 +351,13 @@ static int mbox_test_remove(struct platform_device *pdev) } static const struct of_device_id mbox_test_match[] = { - { .compatible = "mailbox_test" }, + { .compatible = "mailbox-test" }, {}, }; static struct platform_driver mbox_test_driver = { .driver = { - .name = "mailbox_sti_test", + .name = "mailbox_test", .of_match_table = mbox_test_match, }, .probe = mbox_test_probe, diff --git a/drivers/mailbox/mailbox-xgene-slimpro.c b/drivers/mailbox/mailbox-xgene-slimpro.c new file mode 100644 index 000000000000..bd07f39f0692 --- /dev/null +++ b/drivers/mailbox/mailbox-xgene-slimpro.c @@ -0,0 +1,284 @@ +/* + * APM X-Gene SLIMpro MailBox Driver + * + * Copyright (c) 2015, Applied Micro Circuits Corporation + * Author: Feng Kan fkan@apm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + * + */ +#include <linux/acpi.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/mailbox_controller.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#define MBOX_CON_NAME "slimpro-mbox" +#define MBOX_REG_SET_OFFSET 0x1000 +#define MBOX_CNT 8 +#define MBOX_STATUS_AVAIL_MASK BIT(16) +#define MBOX_STATUS_ACK_MASK BIT(0) + +/* Configuration and Status Registers */ +#define REG_DB_IN 0x00 +#define REG_DB_DIN0 0x04 +#define REG_DB_DIN1 0x08 +#define REG_DB_OUT 0x10 +#define REG_DB_DOUT0 0x14 +#define REG_DB_DOUT1 0x18 +#define REG_DB_STAT 0x20 +#define REG_DB_STATMASK 0x24 + +/** + * X-Gene SlimPRO mailbox channel information + * + * @dev: Device to which it is attached + * @chan: Pointer to mailbox communication channel + * @reg: Base address to access channel registers + * @irq: Interrupt number of the channel + * @rx_msg: Received message storage + */ +struct slimpro_mbox_chan { + struct device *dev; + struct mbox_chan *chan; + void __iomem *reg; + int irq; + u32 rx_msg[3]; +}; + +/** + * X-Gene SlimPRO Mailbox controller data + * + * X-Gene SlimPRO Mailbox controller has 8 commnunication channels. + * Each channel has a separate IRQ number assgined to it. + * + * @mb_ctrl: Representation of the commnunication channel controller + * @mc: Array of SlimPRO mailbox channels of the controller + * @chans: Array of mailbox communication channels + * + */ +struct slimpro_mbox { + struct mbox_controller mb_ctrl; + struct slimpro_mbox_chan mc[MBOX_CNT]; + struct mbox_chan chans[MBOX_CNT]; +}; + +static void mb_chan_send_msg(struct slimpro_mbox_chan *mb_chan, u32 *msg) +{ + writel(msg[1], mb_chan->reg + REG_DB_DOUT0); + writel(msg[2], mb_chan->reg + REG_DB_DOUT1); + writel(msg[0], mb_chan->reg + REG_DB_OUT); +} + +static void mb_chan_recv_msg(struct slimpro_mbox_chan *mb_chan) +{ + mb_chan->rx_msg[1] = readl(mb_chan->reg + REG_DB_DIN0); + mb_chan->rx_msg[2] = readl(mb_chan->reg + REG_DB_DIN1); + mb_chan->rx_msg[0] = readl(mb_chan->reg + REG_DB_IN); +} + +static int mb_chan_status_ack(struct slimpro_mbox_chan *mb_chan) +{ + u32 val = readl(mb_chan->reg + REG_DB_STAT); + + if (val & MBOX_STATUS_ACK_MASK) { + writel(MBOX_STATUS_ACK_MASK, mb_chan->reg + REG_DB_STAT); + return 1; + } + return 0; +} + +static int mb_chan_status_avail(struct slimpro_mbox_chan *mb_chan) +{ + u32 val = readl(mb_chan->reg + REG_DB_STAT); + + if (val & MBOX_STATUS_AVAIL_MASK) { + mb_chan_recv_msg(mb_chan); + writel(MBOX_STATUS_AVAIL_MASK, mb_chan->reg + REG_DB_STAT); + return 1; + } + return 0; +} + +static irqreturn_t slimpro_mbox_irq(int irq, void *id) +{ + struct slimpro_mbox_chan *mb_chan = id; + + if (mb_chan_status_ack(mb_chan)) + mbox_chan_txdone(mb_chan->chan, 0); + + if (mb_chan_status_avail(mb_chan)) + mbox_chan_received_data(mb_chan->chan, mb_chan->rx_msg); + + return IRQ_HANDLED; +} + +static int slimpro_mbox_send_data(struct mbox_chan *chan, void *msg) +{ + struct slimpro_mbox_chan *mb_chan = chan->con_priv; + + mb_chan_send_msg(mb_chan, msg); + return 0; +} + +static int slimpro_mbox_startup(struct mbox_chan *chan) +{ + struct slimpro_mbox_chan *mb_chan = chan->con_priv; + int rc; + u32 val; + + rc = devm_request_irq(mb_chan->dev, mb_chan->irq, slimpro_mbox_irq, 0, + MBOX_CON_NAME, mb_chan); + if (unlikely(rc)) { + dev_err(mb_chan->dev, "failed to register mailbox interrupt %d\n", + mb_chan->irq); + return rc; + } + + /* Enable HW interrupt */ + writel(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK, + mb_chan->reg + REG_DB_STAT); + /* Unmask doorbell status interrupt */ + val = readl(mb_chan->reg + REG_DB_STATMASK); + val &= ~(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK); + writel(val, mb_chan->reg + REG_DB_STATMASK); + + return 0; +} + +static void slimpro_mbox_shutdown(struct mbox_chan *chan) +{ + struct slimpro_mbox_chan *mb_chan = chan->con_priv; + u32 val; + + /* Mask doorbell status interrupt */ + val = readl(mb_chan->reg + REG_DB_STATMASK); + val |= (MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK); + writel(val, mb_chan->reg + REG_DB_STATMASK); + + devm_free_irq(mb_chan->dev, mb_chan->irq, mb_chan); +} + +static struct mbox_chan_ops slimpro_mbox_ops = { + .send_data = slimpro_mbox_send_data, + .startup = slimpro_mbox_startup, + .shutdown = slimpro_mbox_shutdown, +}; + +static int slimpro_mbox_probe(struct platform_device *pdev) +{ + struct slimpro_mbox *ctx; + struct resource *regs; + void __iomem *mb_base; + int rc; + int i; + + ctx = devm_kzalloc(&pdev->dev, sizeof(struct slimpro_mbox), GFP_KERNEL); + if (IS_ERR(ctx)) + return PTR_ERR(ctx); + + platform_set_drvdata(pdev, ctx); + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mb_base = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); + if (!mb_base) + return -ENOMEM; + + /* Setup mailbox links */ + for (i = 0; i < MBOX_CNT; i++) { + ctx->mc[i].irq = platform_get_irq(pdev, i); + if (ctx->mc[i].irq < 0) { + if (i == 0) { + dev_err(&pdev->dev, "no available IRQ\n"); + return -EINVAL; + } + dev_info(&pdev->dev, "no IRQ for channel %d\n", i); + break; + } + + ctx->mc[i].dev = &pdev->dev; + ctx->mc[i].reg = mb_base + i * MBOX_REG_SET_OFFSET; + ctx->mc[i].chan = &ctx->chans[i]; + ctx->chans[i].con_priv = &ctx->mc[i]; + } + + /* Setup mailbox controller */ + ctx->mb_ctrl.dev = &pdev->dev; + ctx->mb_ctrl.chans = ctx->chans; + ctx->mb_ctrl.txdone_irq = true; + ctx->mb_ctrl.ops = &slimpro_mbox_ops; + ctx->mb_ctrl.num_chans = i; + + rc = mbox_controller_register(&ctx->mb_ctrl); + if (rc) { + dev_err(&pdev->dev, + "APM X-Gene SLIMpro MailBox register failed:%d\n", rc); + return rc; + } + + dev_info(&pdev->dev, "APM X-Gene SLIMpro MailBox registered\n"); + return 0; +} + +static int slimpro_mbox_remove(struct platform_device *pdev) +{ + struct slimpro_mbox *smb = platform_get_drvdata(pdev); + + mbox_controller_unregister(&smb->mb_ctrl); + return 0; +} + +static const struct of_device_id slimpro_of_match[] = { + {.compatible = "apm,xgene-slimpro-mbox" }, + { }, +}; +MODULE_DEVICE_TABLE(of, slimpro_of_match); + +#ifdef CONFIG_ACPI +static const struct acpi_device_id slimpro_acpi_ids[] = { + {"APMC0D01", 0}, + {} +}; +MODULE_DEVICE_TABLE(acpi, slimpro_acpi_ids); +#endif + +static struct platform_driver slimpro_mbox_driver = { + .probe = slimpro_mbox_probe, + .remove = slimpro_mbox_remove, + .driver = { + .name = "xgene-slimpro-mbox", + .of_match_table = of_match_ptr(slimpro_of_match), + .acpi_match_table = ACPI_PTR(slimpro_acpi_ids) + }, +}; + +static int __init slimpro_mbox_init(void) +{ + return platform_driver_register(&slimpro_mbox_driver); +} + +static void __exit slimpro_mbox_exit(void) +{ + platform_driver_unregister(&slimpro_mbox_driver); +} + +subsys_initcall(slimpro_mbox_init); +module_exit(slimpro_mbox_exit); + +MODULE_DESCRIPTION("APM X-Gene SLIMpro Mailbox Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mailbox/pcc.c b/drivers/mailbox/pcc.c index 8f779a1ec99c..043828d541f7 100644 --- a/drivers/mailbox/pcc.c +++ b/drivers/mailbox/pcc.c @@ -63,6 +63,7 @@ #include <linux/platform_device.h> #include <linux/mailbox_controller.h> #include <linux/mailbox_client.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include "mailbox.h" @@ -70,6 +71,9 @@ static struct mbox_chan *pcc_mbox_channels; +/* Array of cached virtual address for doorbell registers */ +static void __iomem **pcc_doorbell_vaddr; + static struct mbox_controller pcc_mbox_ctrl = {}; /** * get_pcc_channel - Given a PCC subspace idx, get @@ -160,6 +164,66 @@ void pcc_mbox_free_channel(struct mbox_chan *chan) } EXPORT_SYMBOL_GPL(pcc_mbox_free_channel); +/* + * PCC can be used with perf critical drivers such as CPPC + * So it makes sense to locally cache the virtual address and + * use it to read/write to PCC registers such as doorbell register + * + * The below read_register and write_registers are used to read and + * write from perf critical registers such as PCC doorbell register + */ +static int read_register(void __iomem *vaddr, u64 *val, unsigned int bit_width) +{ + int ret_val = 0; + + switch (bit_width) { + case 8: + *val = readb(vaddr); + break; + case 16: + *val = readw(vaddr); + break; + case 32: + *val = readl(vaddr); + break; + case 64: + *val = readq(vaddr); + break; + default: + pr_debug("Error: Cannot read register of %u bit width", + bit_width); + ret_val = -EFAULT; + break; + } + return ret_val; +} + +static int write_register(void __iomem *vaddr, u64 val, unsigned int bit_width) +{ + int ret_val = 0; + + switch (bit_width) { + case 8: + writeb(val, vaddr); + break; + case 16: + writew(val, vaddr); + break; + case 32: + writel(val, vaddr); + break; + case 64: + writeq(val, vaddr); + break; + default: + pr_debug("Error: Cannot write register of %u bit width", + bit_width); + ret_val = -EFAULT; + break; + } + return ret_val; +} + /** * pcc_send_data - Called from Mailbox Controller code. Used * here only to ring the channel doorbell. The PCC client @@ -175,21 +239,39 @@ EXPORT_SYMBOL_GPL(pcc_mbox_free_channel); static int pcc_send_data(struct mbox_chan *chan, void *data) { struct acpi_pcct_hw_reduced *pcct_ss = chan->con_priv; - struct acpi_generic_address doorbell; + struct acpi_generic_address *doorbell; u64 doorbell_preserve; u64 doorbell_val; u64 doorbell_write; + u32 id = chan - pcc_mbox_channels; + int ret = 0; + + if (id >= pcc_mbox_ctrl.num_chans) { + pr_debug("pcc_send_data: Invalid mbox_chan passed\n"); + return -ENOENT; + } - doorbell = pcct_ss->doorbell_register; + doorbell = &pcct_ss->doorbell_register; doorbell_preserve = pcct_ss->preserve_mask; doorbell_write = pcct_ss->write_mask; /* Sync notification from OS to Platform. */ - acpi_read(&doorbell_val, &doorbell); - acpi_write((doorbell_val & doorbell_preserve) | doorbell_write, - &doorbell); - - return 0; + if (pcc_doorbell_vaddr[id]) { + ret = read_register(pcc_doorbell_vaddr[id], &doorbell_val, + doorbell->bit_width); + if (ret) + return ret; + ret = write_register(pcc_doorbell_vaddr[id], + (doorbell_val & doorbell_preserve) | doorbell_write, + doorbell->bit_width); + } else { + ret = acpi_read(&doorbell_val, doorbell); + if (ret) + return ret; + ret = acpi_write((doorbell_val & doorbell_preserve) | doorbell_write, + doorbell); + } + return ret; } static const struct mbox_chan_ops pcc_chan_ops = { @@ -265,12 +347,27 @@ static int __init acpi_pcc_probe(void) return -ENOMEM; } + pcc_doorbell_vaddr = kcalloc(count, sizeof(void *), GFP_KERNEL); + if (!pcc_doorbell_vaddr) { + kfree(pcc_mbox_channels); + return -ENOMEM; + } + /* Point to the first PCC subspace entry */ pcct_entry = (struct acpi_subtable_header *) ( (unsigned long) pcct_tbl + sizeof(struct acpi_table_pcct)); for (i = 0; i < count; i++) { + struct acpi_generic_address *db_reg; + struct acpi_pcct_hw_reduced *pcct_ss; pcc_mbox_channels[i].con_priv = pcct_entry; + + /* If doorbell is in system memory cache the virt address */ + pcct_ss = (struct acpi_pcct_hw_reduced *)pcct_entry; + db_reg = &pcct_ss->doorbell_register; + if (db_reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) + pcc_doorbell_vaddr[i] = acpi_os_ioremap(db_reg->address, + db_reg->bit_width/8); pcct_entry = (struct acpi_subtable_header *) ((unsigned long) pcct_entry + pcct_entry->length); } diff --git a/drivers/mailbox/rockchip-mailbox.c b/drivers/mailbox/rockchip-mailbox.c new file mode 100644 index 000000000000..d702a204f5c1 --- /dev/null +++ b/drivers/mailbox/rockchip-mailbox.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mailbox_controller.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#define MAILBOX_A2B_INTEN 0x00 +#define MAILBOX_A2B_STATUS 0x04 +#define MAILBOX_A2B_CMD(x) (0x08 + (x) * 8) +#define MAILBOX_A2B_DAT(x) (0x0c + (x) * 8) + +#define MAILBOX_B2A_INTEN 0x28 +#define MAILBOX_B2A_STATUS 0x2C +#define MAILBOX_B2A_CMD(x) (0x30 + (x) * 8) +#define MAILBOX_B2A_DAT(x) (0x34 + (x) * 8) + +struct rockchip_mbox_msg { + u32 cmd; + int rx_size; +}; + +struct rockchip_mbox_data { + int num_chans; +}; + +struct rockchip_mbox_chan { + int idx; + int irq; + struct rockchip_mbox_msg *msg; + struct rockchip_mbox *mb; +}; + +struct rockchip_mbox { + struct mbox_controller mbox; + struct clk *pclk; + void __iomem *mbox_base; + + /* The maximum size of buf for each channel */ + u32 buf_size; + + struct rockchip_mbox_chan *chans; +}; + +static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev); + struct rockchip_mbox_msg *msg = data; + struct rockchip_mbox_chan *chans = mb->chans; + + if (!msg) + return -EINVAL; + + if (msg->rx_size > mb->buf_size) { + dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n", + mb->buf_size); + return -EINVAL; + } + + dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n", + chans->idx, msg->cmd); + + mb->chans[chans->idx].msg = msg; + + writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx)); + writel_relaxed(msg->rx_size, mb->mbox_base + + MAILBOX_A2B_DAT(chans->idx)); + + return 0; +} + +static int rockchip_mbox_startup(struct mbox_chan *chan) +{ + struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev); + + /* Enable all B2A interrupts */ + writel_relaxed((1 << mb->mbox.num_chans) - 1, + mb->mbox_base + MAILBOX_B2A_INTEN); + + return 0; +} + +static void rockchip_mbox_shutdown(struct mbox_chan *chan) +{ + struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev); + struct rockchip_mbox_chan *chans = mb->chans; + + /* Disable all B2A interrupts */ + writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN); + + mb->chans[chans->idx].msg = NULL; +} + +static const struct mbox_chan_ops rockchip_mbox_chan_ops = { + .send_data = rockchip_mbox_send_data, + .startup = rockchip_mbox_startup, + .shutdown = rockchip_mbox_shutdown, +}; + +static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id) +{ + int idx; + struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id; + u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS); + + for (idx = 0; idx < mb->mbox.num_chans; idx++) { + if ((status & (1 << idx)) && (irq == mb->chans[idx].irq)) { + /* Clear mbox interrupt */ + writel_relaxed(1 << idx, + mb->mbox_base + MAILBOX_B2A_STATUS); + return IRQ_WAKE_THREAD; + } + } + + return IRQ_NONE; +} + +static irqreturn_t rockchip_mbox_isr(int irq, void *dev_id) +{ + int idx; + struct rockchip_mbox_msg *msg = NULL; + struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id; + + for (idx = 0; idx < mb->mbox.num_chans; idx++) { + if (irq != mb->chans[idx].irq) + continue; + + msg = mb->chans[idx].msg; + if (!msg) { + dev_err(mb->mbox.dev, + "Chan[%d]: B2A message is NULL\n", idx); + break; /* spurious */ + } + + mbox_chan_received_data(&mb->mbox.chans[idx], msg); + mb->chans[idx].msg = NULL; + + dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n", + idx, msg->cmd); + + break; + } + + return IRQ_HANDLED; +} + +static const struct rockchip_mbox_data rk3368_drv_data = { + .num_chans = 4, +}; + +static const struct of_device_id rockchip_mbox_of_match[] = { + { .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data}, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match); + +static int rockchip_mbox_probe(struct platform_device *pdev) +{ + struct rockchip_mbox *mb; + const struct of_device_id *match; + const struct rockchip_mbox_data *drv_data; + struct resource *res; + int ret, irq, i; + + if (!pdev->dev.of_node) + return -ENODEV; + + match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node); + drv_data = (const struct rockchip_mbox_data *)match->data; + + mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL); + if (!mb) + return -ENOMEM; + + mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, + sizeof(*mb->chans), GFP_KERNEL); + if (!mb->chans) + return -ENOMEM; + + mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, + sizeof(*mb->mbox.chans), GFP_KERNEL); + if (!mb->mbox.chans) + return -ENOMEM; + + platform_set_drvdata(pdev, mb); + + mb->mbox.dev = &pdev->dev; + mb->mbox.num_chans = drv_data->num_chans; + mb->mbox.ops = &rockchip_mbox_chan_ops; + mb->mbox.txdone_irq = true; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + mb->mbox_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mb->mbox_base)) + return PTR_ERR(mb->mbox_base); + + /* Each channel has two buffers for A2B and B2A */ + mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2); + + mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox"); + if (IS_ERR(mb->pclk)) { + ret = PTR_ERR(mb->pclk); + dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n", + ret); + return ret; + } + + ret = clk_prepare_enable(mb->pclk); + if (ret) { + dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret); + return ret; + } + + for (i = 0; i < mb->mbox.num_chans; i++) { + irq = platform_get_irq(pdev, i); + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(&pdev->dev, irq, + rockchip_mbox_irq, + rockchip_mbox_isr, IRQF_ONESHOT, + dev_name(&pdev->dev), mb); + if (ret < 0) + return ret; + + mb->chans[i].idx = i; + mb->chans[i].irq = irq; + mb->chans[i].mb = mb; + mb->chans[i].msg = NULL; + } + + ret = mbox_controller_register(&mb->mbox); + if (ret < 0) + dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret); + + return ret; +} + +static int rockchip_mbox_remove(struct platform_device *pdev) +{ + struct rockchip_mbox *mb = platform_get_drvdata(pdev); + + if (!mb) + return -EINVAL; + + mbox_controller_unregister(&mb->mbox); + + return 0; +} + +static struct platform_driver rockchip_mbox_driver = { + .probe = rockchip_mbox_probe, + .remove = rockchip_mbox_remove, + .driver = { + .name = "rockchip-mailbox", + .of_match_table = of_match_ptr(rockchip_mbox_of_match), + }, +}; + +module_platform_driver(rockchip_mbox_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU"); +MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); +MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>"); diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c new file mode 100644 index 000000000000..54b9e4cb4cfa --- /dev/null +++ b/drivers/mailbox/ti-msgmgr.c @@ -0,0 +1,639 @@ +/* + * Texas Instruments' Message Manager Driver + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mailbox_controller.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/ti/ti-msgmgr.h> + +#define Q_DATA_OFFSET(proxy, queue, reg) \ + ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4)) +#define Q_STATE_OFFSET(queue) ((queue) * 0x4) +#define Q_STATE_ENTRY_COUNT_MASK (0xFFF000) + +/** + * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor + * @queue_id: Queue Number for this path + * @proxy_id: Proxy ID representing the processor in SoC + * @is_tx: Is this a receive path? + */ +struct ti_msgmgr_valid_queue_desc { + u8 queue_id; + u8 proxy_id; + bool is_tx; +}; + +/** + * struct ti_msgmgr_desc - Description of message manager integration + * @queue_count: Number of Queues + * @max_message_size: Message size in bytes + * @max_messages: Number of messages + * @q_slices: Number of queue engines + * @q_proxies: Number of queue proxies per page + * @data_first_reg: First data register for proxy data region + * @data_last_reg: Last data register for proxy data region + * @tx_polled: Do I need to use polled mechanism for tx + * @tx_poll_timeout_ms: Timeout in ms if polled + * @valid_queues: List of Valid queues that the processor can access + * @num_valid_queues: Number of valid queues + * + * This structure is used in of match data to describe how integration + * for a specific compatible SoC is done. + */ +struct ti_msgmgr_desc { + u8 queue_count; + u8 max_message_size; + u8 max_messages; + u8 q_slices; + u8 q_proxies; + u8 data_first_reg; + u8 data_last_reg; + bool tx_polled; + int tx_poll_timeout_ms; + const struct ti_msgmgr_valid_queue_desc *valid_queues; + int num_valid_queues; +}; + +/** + * struct ti_queue_inst - Description of a queue instance + * @name: Queue Name + * @queue_id: Queue Identifier as mapped on SoC + * @proxy_id: Proxy Identifier as mapped on SoC + * @irq: IRQ for Rx Queue + * @is_tx: 'true' if transmit queue, else, 'false' + * @queue_buff_start: First register of Data Buffer + * @queue_buff_end: Last (or confirmation) register of Data buffer + * @queue_state: Queue status register + * @chan: Mailbox channel + * @rx_buff: Receive buffer pointer allocated at probe, max_message_size + */ +struct ti_queue_inst { + char name[30]; + u8 queue_id; + u8 proxy_id; + int irq; + bool is_tx; + void __iomem *queue_buff_start; + void __iomem *queue_buff_end; + void __iomem *queue_state; + struct mbox_chan *chan; + u32 *rx_buff; +}; + +/** + * struct ti_msgmgr_inst - Description of a Message Manager Instance + * @dev: device pointer corresponding to the Message Manager instance + * @desc: Description of the SoC integration + * @queue_proxy_region: Queue proxy region where queue buffers are located + * @queue_state_debug_region: Queue status register regions + * @num_valid_queues: Number of valid queues defined for the processor + * Note: other queues are probably reserved for other processors + * in the SoC. + * @qinsts: Array of valid Queue Instances for the Processor + * @mbox: Mailbox Controller + * @chans: Array for channels corresponding to the Queue Instances. + */ +struct ti_msgmgr_inst { + struct device *dev; + const struct ti_msgmgr_desc *desc; + void __iomem *queue_proxy_region; + void __iomem *queue_state_debug_region; + u8 num_valid_queues; + struct ti_queue_inst *qinsts; + struct mbox_controller mbox; + struct mbox_chan *chans; +}; + +/** + * ti_msgmgr_queue_get_num_messages() - Get the number of pending messages + * @qinst: Queue instance for which we check the number of pending messages + * + * Return: number of messages pending in the queue (0 == no pending messages) + */ +static inline int ti_msgmgr_queue_get_num_messages(struct ti_queue_inst *qinst) +{ + u32 val; + + /* + * We cannot use relaxed operation here - update may happen + * real-time. + */ + val = readl(qinst->queue_state) & Q_STATE_ENTRY_COUNT_MASK; + val >>= __ffs(Q_STATE_ENTRY_COUNT_MASK); + + return val; +} + +/** + * ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue + * @irq: Interrupt number + * @p: Channel Pointer + * + * Return: -EINVAL if there is no instance + * IRQ_NONE if the interrupt is not ours. + * IRQ_HANDLED if the rx interrupt was successfully handled. + */ +static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) +{ + struct mbox_chan *chan = p; + struct device *dev = chan->mbox->dev; + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + struct ti_queue_inst *qinst = chan->con_priv; + const struct ti_msgmgr_desc *desc; + int msg_count, num_words; + struct ti_msgmgr_message message; + void __iomem *data_reg; + u32 *word_data; + + if (WARN_ON(!inst)) { + dev_err(dev, "no platform drv data??\n"); + return -EINVAL; + } + + /* Do I have an invalid interrupt source? */ + if (qinst->is_tx) { + dev_err(dev, "Cannot handle rx interrupt on tx channel %s\n", + qinst->name); + return IRQ_NONE; + } + + /* Do I actually have messages to read? */ + msg_count = ti_msgmgr_queue_get_num_messages(qinst); + if (!msg_count) { + /* Shared IRQ? */ + dev_dbg(dev, "Spurious event - 0 pending data!\n"); + return IRQ_NONE; + } + + /* + * I have no idea about the protocol being used to communicate with the + * remote producer - 0 could be valid data, so I wont make a judgement + * of how many bytes I should be reading. Let the client figure this + * out.. I just read the full message and pass it on.. + */ + desc = inst->desc; + message.len = desc->max_message_size; + message.buf = (u8 *)qinst->rx_buff; + + /* + * NOTE about register access involved here: + * the hardware block is implemented with 32bit access operations and no + * support for data splitting. We don't want the hardware to misbehave + * with sub 32bit access - For example: if the last register read is + * split into byte wise access, it can result in the queue getting + * stuck or indeterminate behavior. An out of order read operation may + * result in weird data results as well. + * Hence, we do not use memcpy_fromio or __ioread32_copy here, instead + * we depend on readl for the purpose. + * + * Also note that the final register read automatically marks the + * queue message as read. + */ + for (data_reg = qinst->queue_buff_start, word_data = qinst->rx_buff, + num_words = (desc->max_message_size / sizeof(u32)); + num_words; num_words--, data_reg += sizeof(u32), word_data++) + *word_data = readl(data_reg); + + /* + * Last register read automatically clears the IRQ if only 1 message + * is pending - so send the data up the stack.. + * NOTE: Client is expected to be as optimal as possible, since + * we invoke the handler in IRQ context. + */ + mbox_chan_received_data(chan, (void *)&message); + + return IRQ_HANDLED; +} + +/** + * ti_msgmgr_queue_peek_data() - Peek to see if there are any rx messages. + * @chan: Channel Pointer + * + * Return: 'true' if there is pending rx data, 'false' if there is none. + */ +static bool ti_msgmgr_queue_peek_data(struct mbox_chan *chan) +{ + struct ti_queue_inst *qinst = chan->con_priv; + int msg_count; + + if (qinst->is_tx) + return false; + + msg_count = ti_msgmgr_queue_get_num_messages(qinst); + + return msg_count ? true : false; +} + +/** + * ti_msgmgr_last_tx_done() - See if all the tx messages are sent + * @chan: Channel pointer + * + * Return: 'true' is no pending tx data, 'false' if there are any. + */ +static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan) +{ + struct ti_queue_inst *qinst = chan->con_priv; + int msg_count; + + if (!qinst->is_tx) + return false; + + msg_count = ti_msgmgr_queue_get_num_messages(qinst); + + /* if we have any messages pending.. */ + return msg_count ? false : true; +} + +/** + * ti_msgmgr_send_data() - Send data + * @chan: Channel Pointer + * @data: ti_msgmgr_message * Message Pointer + * + * Return: 0 if all goes good, else appropriate error messages. + */ +static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) +{ + struct device *dev = chan->mbox->dev; + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + const struct ti_msgmgr_desc *desc; + struct ti_queue_inst *qinst = chan->con_priv; + int num_words, trail_bytes; + struct ti_msgmgr_message *message = data; + void __iomem *data_reg; + u32 *word_data; + + if (WARN_ON(!inst)) { + dev_err(dev, "no platform drv data??\n"); + return -EINVAL; + } + desc = inst->desc; + + if (desc->max_message_size < message->len) { + dev_err(dev, "Queue %s message length %d > max %d\n", + qinst->name, message->len, desc->max_message_size); + return -EINVAL; + } + + /* NOTE: Constraints similar to rx path exists here as well */ + for (data_reg = qinst->queue_buff_start, + num_words = message->len / sizeof(u32), + word_data = (u32 *)message->buf; + num_words; num_words--, data_reg += sizeof(u32), word_data++) + writel(*word_data, data_reg); + + trail_bytes = message->len % sizeof(u32); + if (trail_bytes) { + u32 data_trail = *word_data; + + /* Ensure all unused data is 0 */ + data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes)); + writel(data_trail, data_reg); + data_reg++; + } + /* + * 'data_reg' indicates next register to write. If we did not already + * write on tx complete reg(last reg), we must do so for transmit + */ + if (data_reg <= qinst->queue_buff_end) + writel(0, qinst->queue_buff_end); + + return 0; +} + +/** + * ti_msgmgr_queue_startup() - Startup queue + * @chan: Channel pointer + * + * Return: 0 if all goes good, else return corresponding error message + */ +static int ti_msgmgr_queue_startup(struct mbox_chan *chan) +{ + struct ti_queue_inst *qinst = chan->con_priv; + struct device *dev = chan->mbox->dev; + int ret; + + if (!qinst->is_tx) { + /* + * With the expectation that the IRQ might be shared in SoC + */ + ret = request_irq(qinst->irq, ti_msgmgr_queue_rx_interrupt, + IRQF_SHARED, qinst->name, chan); + if (ret) { + dev_err(dev, "Unable to get IRQ %d on %s(res=%d)\n", + qinst->irq, qinst->name, ret); + return ret; + } + } + + return 0; +} + +/** + * ti_msgmgr_queue_shutdown() - Shutdown the queue + * @chan: Channel pointer + */ +static void ti_msgmgr_queue_shutdown(struct mbox_chan *chan) +{ + struct ti_queue_inst *qinst = chan->con_priv; + + if (!qinst->is_tx) + free_irq(qinst->irq, chan); +} + +/** + * ti_msgmgr_of_xlate() - Translation of phandle to queue + * @mbox: Mailbox controller + * @p: phandle pointer + * + * Return: Mailbox channel corresponding to the queue, else return error + * pointer. + */ +static struct mbox_chan *ti_msgmgr_of_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *p) +{ + struct ti_msgmgr_inst *inst; + int req_qid, req_pid; + struct ti_queue_inst *qinst; + int i; + + inst = container_of(mbox, struct ti_msgmgr_inst, mbox); + if (WARN_ON(!inst)) + return ERR_PTR(-EINVAL); + + /* #mbox-cells is 2 */ + if (p->args_count != 2) { + dev_err(inst->dev, "Invalid arguments in dt[%d] instead of 2\n", + p->args_count); + return ERR_PTR(-EINVAL); + } + req_qid = p->args[0]; + req_pid = p->args[1]; + + for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues; + i++, qinst++) { + if (req_qid == qinst->queue_id && req_pid == qinst->proxy_id) + return qinst->chan; + } + + dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %s\n", + req_qid, req_pid, p->np->name); + return ERR_PTR(-ENOENT); +} + +/** + * ti_msgmgr_queue_setup() - Setup data structures for each queue instance + * @idx: index of the queue + * @dev: pointer to the message manager device + * @np: pointer to the of node + * @inst: Queue instance pointer + * @d: Message Manager instance description data + * @qd: Queue description data + * @qinst: Queue instance pointer + * @chan: pointer to mailbox channel + * + * Return: 0 if all went well, else return corresponding error + */ +static int ti_msgmgr_queue_setup(int idx, struct device *dev, + struct device_node *np, + struct ti_msgmgr_inst *inst, + const struct ti_msgmgr_desc *d, + const struct ti_msgmgr_valid_queue_desc *qd, + struct ti_queue_inst *qinst, + struct mbox_chan *chan) +{ + qinst->proxy_id = qd->proxy_id; + qinst->queue_id = qd->queue_id; + + if (qinst->queue_id > d->queue_count) { + dev_err(dev, "Queue Data [idx=%d] queuid %d > %d\n", + idx, qinst->queue_id, d->queue_count); + return -ERANGE; + } + + qinst->is_tx = qd->is_tx; + snprintf(qinst->name, sizeof(qinst->name), "%s %s_%03d_%03d", + dev_name(dev), qinst->is_tx ? "tx" : "rx", qinst->queue_id, + qinst->proxy_id); + + if (!qinst->is_tx) { + char of_rx_irq_name[7]; + + snprintf(of_rx_irq_name, sizeof(of_rx_irq_name), + "rx_%03d", qinst->queue_id); + + qinst->irq = of_irq_get_byname(np, of_rx_irq_name); + if (qinst->irq < 0) { + dev_crit(dev, + "[%d]QID %d PID %d:No IRQ[%s]: %d\n", + idx, qinst->queue_id, qinst->proxy_id, + of_rx_irq_name, qinst->irq); + return qinst->irq; + } + /* Allocate usage buffer for rx */ + qinst->rx_buff = devm_kzalloc(dev, + d->max_message_size, GFP_KERNEL); + if (!qinst->rx_buff) + return -ENOMEM; + } + + qinst->queue_buff_start = inst->queue_proxy_region + + Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_first_reg); + qinst->queue_buff_end = inst->queue_proxy_region + + Q_DATA_OFFSET(qinst->proxy_id, qinst->queue_id, d->data_last_reg); + qinst->queue_state = inst->queue_state_debug_region + + Q_STATE_OFFSET(qinst->queue_id); + qinst->chan = chan; + + chan->con_priv = qinst; + + dev_dbg(dev, "[%d] qidx=%d pidx=%d irq=%d q_s=%p q_e = %p\n", + idx, qinst->queue_id, qinst->proxy_id, qinst->irq, + qinst->queue_buff_start, qinst->queue_buff_end); + return 0; +} + +/* Queue operations */ +static const struct mbox_chan_ops ti_msgmgr_chan_ops = { + .startup = ti_msgmgr_queue_startup, + .shutdown = ti_msgmgr_queue_shutdown, + .peek_data = ti_msgmgr_queue_peek_data, + .last_tx_done = ti_msgmgr_last_tx_done, + .send_data = ti_msgmgr_send_data, +}; + +/* Keystone K2G SoC integration details */ +static const struct ti_msgmgr_valid_queue_desc k2g_valid_queues[] = { + {.queue_id = 0, .proxy_id = 0, .is_tx = true,}, + {.queue_id = 1, .proxy_id = 0, .is_tx = true,}, + {.queue_id = 2, .proxy_id = 0, .is_tx = true,}, + {.queue_id = 3, .proxy_id = 0, .is_tx = true,}, + {.queue_id = 5, .proxy_id = 2, .is_tx = false,}, + {.queue_id = 56, .proxy_id = 1, .is_tx = true,}, + {.queue_id = 57, .proxy_id = 2, .is_tx = false,}, + {.queue_id = 58, .proxy_id = 3, .is_tx = true,}, + {.queue_id = 59, .proxy_id = 4, .is_tx = true,}, + {.queue_id = 60, .proxy_id = 5, .is_tx = true,}, + {.queue_id = 61, .proxy_id = 6, .is_tx = true,}, +}; + +static const struct ti_msgmgr_desc k2g_desc = { + .queue_count = 64, + .max_message_size = 64, + .max_messages = 128, + .q_slices = 1, + .q_proxies = 1, + .data_first_reg = 16, + .data_last_reg = 31, + .tx_polled = false, + .valid_queues = k2g_valid_queues, + .num_valid_queues = ARRAY_SIZE(k2g_valid_queues), +}; + +static const struct of_device_id ti_msgmgr_of_match[] = { + {.compatible = "ti,k2g-message-manager", .data = &k2g_desc}, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ti_msgmgr_of_match); + +static int ti_msgmgr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id; + struct device_node *np; + struct resource *res; + const struct ti_msgmgr_desc *desc; + struct ti_msgmgr_inst *inst; + struct ti_queue_inst *qinst; + struct mbox_controller *mbox; + struct mbox_chan *chans; + int queue_count; + int i; + int ret = -EINVAL; + const struct ti_msgmgr_valid_queue_desc *queue_desc; + + if (!dev->of_node) { + dev_err(dev, "no OF information\n"); + return -EINVAL; + } + np = dev->of_node; + + of_id = of_match_device(ti_msgmgr_of_match, dev); + if (!of_id) { + dev_err(dev, "OF data missing\n"); + return -EINVAL; + } + desc = of_id->data; + + inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->dev = dev; + inst->desc = desc; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "queue_proxy_region"); + inst->queue_proxy_region = devm_ioremap_resource(dev, res); + if (IS_ERR(inst->queue_proxy_region)) + return PTR_ERR(inst->queue_proxy_region); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "queue_state_debug_region"); + inst->queue_state_debug_region = devm_ioremap_resource(dev, res); + if (IS_ERR(inst->queue_state_debug_region)) + return PTR_ERR(inst->queue_state_debug_region); + + dev_dbg(dev, "proxy region=%p, queue_state=%p\n", + inst->queue_proxy_region, inst->queue_state_debug_region); + + queue_count = desc->num_valid_queues; + if (!queue_count || queue_count > desc->queue_count) { + dev_crit(dev, "Invalid Number of queues %d. Max %d\n", + queue_count, desc->queue_count); + return -ERANGE; + } + inst->num_valid_queues = queue_count; + + qinst = devm_kzalloc(dev, sizeof(*qinst) * queue_count, GFP_KERNEL); + if (!qinst) + return -ENOMEM; + inst->qinsts = qinst; + + chans = devm_kzalloc(dev, sizeof(*chans) * queue_count, GFP_KERNEL); + if (!chans) + return -ENOMEM; + inst->chans = chans; + + for (i = 0, queue_desc = desc->valid_queues; + i < queue_count; i++, qinst++, chans++, queue_desc++) { + ret = ti_msgmgr_queue_setup(i, dev, np, inst, + desc, queue_desc, qinst, chans); + if (ret) + return ret; + } + + mbox = &inst->mbox; + mbox->dev = dev; + mbox->ops = &ti_msgmgr_chan_ops; + mbox->chans = inst->chans; + mbox->num_chans = inst->num_valid_queues; + mbox->txdone_irq = false; + mbox->txdone_poll = desc->tx_polled; + if (desc->tx_polled) + mbox->txpoll_period = desc->tx_poll_timeout_ms; + mbox->of_xlate = ti_msgmgr_of_xlate; + + platform_set_drvdata(pdev, inst); + ret = mbox_controller_register(mbox); + if (ret) + dev_err(dev, "Failed to register mbox_controller(%d)\n", ret); + + return ret; +} + +static int ti_msgmgr_remove(struct platform_device *pdev) +{ + struct ti_msgmgr_inst *inst; + + inst = platform_get_drvdata(pdev); + mbox_controller_unregister(&inst->mbox); + + return 0; +} + +static struct platform_driver ti_msgmgr_driver = { + .probe = ti_msgmgr_probe, + .remove = ti_msgmgr_remove, + .driver = { + .name = "ti-msgmgr", + .of_match_table = of_match_ptr(ti_msgmgr_of_match), + }, +}; +module_platform_driver(ti_msgmgr_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("TI message manager driver"); +MODULE_AUTHOR("Nishanth Menon"); +MODULE_ALIAS("platform:ti-msgmgr"); |