summaryrefslogtreecommitdiff
path: root/drivers/media/platform/mxc/capture
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/media/platform/mxc/capture')
-rw-r--r--drivers/media/platform/mxc/capture/Kconfig28
-rw-r--r--drivers/media/platform/mxc/capture/Makefile12
-rw-r--r--drivers/media/platform/mxc/capture/adv7180.c265
-rw-r--r--drivers/media/platform/mxc/capture/adv7280.c1080
-rw-r--r--drivers/media/platform/mxc/capture/ipu_csi_enc.c2
-rw-r--r--drivers/media/platform/mxc/capture/ipu_prp_enc.c16
-rw-r--r--drivers/media/platform/mxc/capture/max9526.c1153
-rw-r--r--drivers/media/platform/mxc/capture/mxc_v4l2_capture.c181
-rw-r--r--drivers/media/platform/mxc/capture/mxc_v4l2_capture.h9
-rw-r--r--drivers/media/platform/mxc/capture/ov5640_mipi.c224
-rw-r--r--drivers/media/platform/mxc/capture/ov5640_mipi_nv.c1509
-rw-r--r--drivers/media/platform/mxc/capture/ov5642.c84
-rw-r--r--drivers/media/platform/mxc/capture/tc358743_h2c.c3401
13 files changed, 7664 insertions, 300 deletions
diff --git a/drivers/media/platform/mxc/capture/Kconfig b/drivers/media/platform/mxc/capture/Kconfig
index 040b6a051d04..189ba0ea0223 100644
--- a/drivers/media/platform/mxc/capture/Kconfig
+++ b/drivers/media/platform/mxc/capture/Kconfig
@@ -62,12 +62,26 @@ config MXC_CAMERA_OV5640_MIPI_V2
---help---
If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here.
+config MXC_CAMERA_OV5640_MIPI_NV
+ tristate "OmniVision ov5640 camera support using mipi (based on driver from nVidia)"
+ depends on MXC_MIPI_CSI && I2C
+ ---help---
+ If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here.
+
config MXC_CAMERA_OV5647_MIPI
tristate "OmniVision ov5647 camera support using mipi"
depends on MXC_MIPI_CSI && I2C
---help---
If you plan to use the ov5647 Camera with mipi interface in your MXC system, say Y here.
+config MXC_HDMI_CSI2_TC358743
+ tristate "Toshiba tc358743 Hdmi to CSI 2 bridge"
+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
+ select MXC_MIPI_CSI2 if ARCH_MX6Q
+ select MXC_CAMERA_SENSOR_CLK
+ ---help---
+ Toshina HDMI to MIPI-CSI2 bridge
+
config MXC_TVIN_ADV7180
tristate "Analog Device adv7180 TV Decoder Input support"
depends on !VIDEO_MXC_EMMA_CAMERA && I2C
@@ -75,6 +89,20 @@ config MXC_TVIN_ADV7180
---help---
If you plan to use the adv7180 video decoder with your MXC system, say Y here.
+config MXC_TVIN_ADV7280
+ tristate "Analog Device adv7280 TV Decoder Input support"
+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
+ select VIDEO_V4L2_MXC_INT_DEVICE
+ ---help---
+ If you plan to use the adv7280 video decoder with your MXC system, say Y here.
+
+config MXC_TVIN_MAX9526
+ tristate "Maxim Integrated MAX9526 NTSC/PAL Decoder Input support"
+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
+ select VIDEO_V4L2_MXC_INT_DEVICE
+ ---help---
+ If you plan to use the MAX9526 video decoder with your MXC system, say Y here.
+
choice
prompt "Select Overlay Rounting"
default MXC_IPU_DEVICE_QUEUE_SDC
diff --git a/drivers/media/platform/mxc/capture/Makefile b/drivers/media/platform/mxc/capture/Makefile
index e6e4b99f9435..1abe623d4048 100644
--- a/drivers/media/platform/mxc/capture/Makefile
+++ b/drivers/media/platform/mxc/capture/Makefile
@@ -29,10 +29,22 @@ obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI) += ov5640_camera_mipi_int.o
ov5640_camera_mipi_v2-objs := ov5640_mipi_v2.o
obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI_V2) += ov5640_camera_mipi_v2.o
+ov5640_camera_mipi_nv-objs := ov5640_mipi_nv.o
+obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI_NV) += ov5640_camera_mipi_nv.o
+
ov5647_camera_mipi-objs := ov5647_mipi.o
obj-$(CONFIG_MXC_CAMERA_OV5647_MIPI) += ov5647_camera_mipi.o
+tc358743_h2c_bridge-objs := tc358743_h2c.o
+obj-$(CONFIG_MXC_HDMI_CSI2_TC358743) += tc358743_h2c_bridge.o
+
adv7180_tvin-objs := adv7180.o
obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o
+adv7280_tvin-objs := adv7280.o
+obj-$(CONFIG_MXC_TVIN_ADV7280) += adv7280_tvin.o
+
+max9526_tvin-objs := max9526.o
+obj-$(CONFIG_MXC_TVIN_MAX9526) += max9526_tvin.o
+
obj-$(CONFIG_VIDEO_V4L2_MXC_INT_DEVICE) += v4l2-int-device.o
diff --git a/drivers/media/platform/mxc/capture/adv7180.c b/drivers/media/platform/mxc/capture/adv7180.c
index abd615927a48..a41aedf5e16b 100644
--- a/drivers/media/platform/mxc/capture/adv7180.c
+++ b/drivers/media/platform/mxc/capture/adv7180.c
@@ -33,6 +33,13 @@
#include "v4l2-int-device.h"
#include "mxc_v4l2_capture.h"
+#if 0
+#undef dev_dbg
+#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);}
+#undef pr_debug
+#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
#define ADV7180_VOLTAGE_ANALOG 1800000
#define ADV7180_VOLTAGE_DIGITAL_CORE 1800000
#define ADV7180_VOLTAGE_DIGITAL_IO 3300000
@@ -71,6 +78,7 @@ static struct i2c_driver adv7180_i2c_driver = {
struct sensor {
struct sensor_data sen;
v4l2_std_id std_id;
+ int rev_id;
} adv7180_data;
@@ -181,8 +189,10 @@ static struct v4l2_queryctrl adv7180_qctrl[] = {
static inline void adv7180_power_down(int enable)
{
- gpio_set_value_cansleep(pwn_gpio, !enable);
- msleep(2);
+ if (gpio_is_valid(pwn_gpio)) {
+ gpio_set_value_cansleep(pwn_gpio, !enable);
+ msleep(2);
+ }
}
static int adv7180_regulator_enable(struct device *dev)
@@ -278,6 +288,9 @@ static inline int adv7180_read(u8 reg)
"%s:read reg error: reg=%2x\n", __func__, reg);
return -1;
}
+ dev_dbg(&adv7180_data.sen.i2c_client->dev,
+ "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
return val;
}
@@ -291,6 +304,8 @@ static int adv7180_write_reg(u8 reg, u8 val)
{
s32 ret;
+ dev_dbg(&adv7180_data.sen.i2c_client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
ret = i2c_smbus_write_byte_data(adv7180_data.sen.i2c_client, reg, val);
if (ret < 0) {
dev_dbg(&adv7180_data.sen.i2c_client->dev,
@@ -378,10 +393,16 @@ static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
/* Initialize structure to 0s then set any non-0 values. */
memset(p, 0, sizeof(*p));
p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
+#if 0
p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
p->u.bt656.nobt_hs_inv = 1;
p->u.bt656.bt_sync_correct = 1;
-
+#else
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 0;
+ p->u.bt656.bt_sync_correct = 0;
+ p->u.bt656.clock_curr = 0; //BT656 interlace clock mode
+#endif
/* ADV7180 has a dedicated clock so no clock settings needed. */
return 0;
@@ -415,13 +436,13 @@ static int ioctl_s_power(struct v4l2_int_device *s, int on)
* This is a workaround for preview scrolling issue.
*/
msleep(400);
+
} else if (!on && sensor->sen.on) {
if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0)
return -EIO;
}
sensor->sen.on = on;
-
return 0;
}
@@ -924,8 +945,8 @@ static void adv7180_hard_reset(bool cvbs)
"In adv7180:adv7180_hard_reset\n");
if (cvbs) {
- /* Set CVBS input on AIN1 */
- adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
+ /* Set CVBS input on AIN4 */
+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x03);
} else {
/*
* Set YPbPr input on AIN1,4,5 and normal
@@ -934,13 +955,12 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
}
- /* Datasheet recommends */
+/* The used chip on the Toradex ACM module reacts badly to writes to
+ nonexisting/reserved/read only registers, so reduce the above list to the
+ writable ones in the datasheet sheet */
adv7180_write_reg(0x01, 0xc8);
- adv7180_write_reg(0x02, 0x04);
- adv7180_write_reg(0x03, 0x00);
+ adv7180_write_reg(0x03, 0x0C);
adv7180_write_reg(0x04, 0x45);
- adv7180_write_reg(0x05, 0x00);
- adv7180_write_reg(0x06, 0x02);
adv7180_write_reg(0x07, 0x7F);
adv7180_write_reg(0x08, 0x80);
adv7180_write_reg(0x0A, 0x00);
@@ -948,31 +968,15 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(0x0C, 0x36);
adv7180_write_reg(0x0D, 0x7C);
adv7180_write_reg(0x0E, 0x00);
- adv7180_write_reg(0x0F, 0x00);
- adv7180_write_reg(0x13, 0x00);
+ adv7180_write_reg(0x0F, 0x04);//00
+ adv7180_write_reg(0x13, 0x00);//R
adv7180_write_reg(0x14, 0x12);
adv7180_write_reg(0x15, 0x00);
- adv7180_write_reg(0x16, 0x00);
adv7180_write_reg(0x17, 0x01);
adv7180_write_reg(0x18, 0x93);
- adv7180_write_reg(0xF1, 0x19);
- adv7180_write_reg(0x1A, 0x00);
- adv7180_write_reg(0x1B, 0x00);
- adv7180_write_reg(0x1C, 0x00);
+ adv7180_write_reg(0x19, 0xF1);
adv7180_write_reg(0x1D, 0x40);
- adv7180_write_reg(0x1E, 0x00);
- adv7180_write_reg(0x1F, 0x00);
- adv7180_write_reg(0x20, 0x00);
- adv7180_write_reg(0x21, 0x00);
- adv7180_write_reg(0x22, 0x00);
- adv7180_write_reg(0x23, 0xC0);
- adv7180_write_reg(0x24, 0x00);
- adv7180_write_reg(0x25, 0x00);
- adv7180_write_reg(0x26, 0x00);
adv7180_write_reg(0x27, 0x58);
- adv7180_write_reg(0x28, 0x00);
- adv7180_write_reg(0x29, 0x00);
- adv7180_write_reg(0x2A, 0x00);
adv7180_write_reg(0x2B, 0xE1);
adv7180_write_reg(0x2C, 0xAE);
adv7180_write_reg(0x2D, 0xF4);
@@ -989,18 +993,8 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(0x38, 0x80);
adv7180_write_reg(0x39, 0xC0);
adv7180_write_reg(0x3A, 0x10);
- adv7180_write_reg(0x3B, 0x05);
- adv7180_write_reg(0x3C, 0x58);
adv7180_write_reg(0x3D, 0xB2);
- adv7180_write_reg(0x3E, 0x64);
- adv7180_write_reg(0x3F, 0xE4);
- adv7180_write_reg(0x40, 0x90);
adv7180_write_reg(0x41, 0x01);
- adv7180_write_reg(0x42, 0x7E);
- adv7180_write_reg(0x43, 0xA4);
- adv7180_write_reg(0x44, 0xFF);
- adv7180_write_reg(0x45, 0xB6);
- adv7180_write_reg(0x46, 0x12);
adv7180_write_reg(0x48, 0x00);
adv7180_write_reg(0x49, 0x00);
adv7180_write_reg(0x4A, 0x00);
@@ -1008,171 +1002,34 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(0x4C, 0x00);
adv7180_write_reg(0x4D, 0xEF);
adv7180_write_reg(0x4E, 0x08);
- adv7180_write_reg(0x4F, 0x08);
adv7180_write_reg(0x50, 0x08);
adv7180_write_reg(0x51, 0x24);
- adv7180_write_reg(0x52, 0x0B);
- adv7180_write_reg(0x53, 0x4E);
- adv7180_write_reg(0x54, 0x80);
- adv7180_write_reg(0x55, 0x00);
- adv7180_write_reg(0x56, 0x10);
- adv7180_write_reg(0x57, 0x00);
adv7180_write_reg(0x58, 0x00);
adv7180_write_reg(0x59, 0x00);
- adv7180_write_reg(0x5A, 0x00);
- adv7180_write_reg(0x5B, 0x00);
- adv7180_write_reg(0x5C, 0x00);
- adv7180_write_reg(0x5D, 0x00);
- adv7180_write_reg(0x5E, 0x00);
- adv7180_write_reg(0x5F, 0x00);
- adv7180_write_reg(0x60, 0x00);
- adv7180_write_reg(0x61, 0x00);
- adv7180_write_reg(0x62, 0x20);
- adv7180_write_reg(0x63, 0x00);
- adv7180_write_reg(0x64, 0x00);
- adv7180_write_reg(0x65, 0x00);
- adv7180_write_reg(0x66, 0x00);
- adv7180_write_reg(0x67, 0x03);
- adv7180_write_reg(0x68, 0x01);
- adv7180_write_reg(0x69, 0x00);
- adv7180_write_reg(0x6A, 0x00);
- adv7180_write_reg(0x6B, 0xC0);
- adv7180_write_reg(0x6C, 0x00);
- adv7180_write_reg(0x6D, 0x00);
- adv7180_write_reg(0x6E, 0x00);
- adv7180_write_reg(0x6F, 0x00);
- adv7180_write_reg(0x70, 0x00);
- adv7180_write_reg(0x71, 0x00);
- adv7180_write_reg(0x72, 0x00);
- adv7180_write_reg(0x73, 0x10);
- adv7180_write_reg(0x74, 0x04);
- adv7180_write_reg(0x75, 0x01);
- adv7180_write_reg(0x76, 0x00);
- adv7180_write_reg(0x77, 0x3F);
- adv7180_write_reg(0x78, 0xFF);
- adv7180_write_reg(0x79, 0xFF);
- adv7180_write_reg(0x7A, 0xFF);
- adv7180_write_reg(0x7B, 0x1E);
- adv7180_write_reg(0x7C, 0xC0);
- adv7180_write_reg(0x7D, 0x00);
- adv7180_write_reg(0x7E, 0x00);
- adv7180_write_reg(0x7F, 0x00);
- adv7180_write_reg(0x80, 0x00);
- adv7180_write_reg(0x81, 0xC0);
- adv7180_write_reg(0x82, 0x04);
- adv7180_write_reg(0x83, 0x00);
- adv7180_write_reg(0x84, 0x0C);
- adv7180_write_reg(0x85, 0x02);
- adv7180_write_reg(0x86, 0x03);
- adv7180_write_reg(0x87, 0x63);
- adv7180_write_reg(0x88, 0x5A);
- adv7180_write_reg(0x89, 0x08);
- adv7180_write_reg(0x8A, 0x10);
- adv7180_write_reg(0x8B, 0x00);
- adv7180_write_reg(0x8C, 0x40);
- adv7180_write_reg(0x8D, 0x00);
- adv7180_write_reg(0x8E, 0x40);
adv7180_write_reg(0x8F, 0x00);
- adv7180_write_reg(0x90, 0x00);
- adv7180_write_reg(0x91, 0x50);
- adv7180_write_reg(0x92, 0x00);
- adv7180_write_reg(0x93, 0x00);
- adv7180_write_reg(0x94, 0x00);
- adv7180_write_reg(0x95, 0x00);
- adv7180_write_reg(0x96, 0x00);
- adv7180_write_reg(0x97, 0xF0);
- adv7180_write_reg(0x98, 0x00);
- adv7180_write_reg(0x99, 0x00);
- adv7180_write_reg(0x9A, 0x00);
- adv7180_write_reg(0x9B, 0x00);
- adv7180_write_reg(0x9C, 0x00);
- adv7180_write_reg(0x9D, 0x00);
- adv7180_write_reg(0x9E, 0x00);
- adv7180_write_reg(0x9F, 0x00);
- adv7180_write_reg(0xA0, 0x00);
- adv7180_write_reg(0xA1, 0x00);
- adv7180_write_reg(0xA2, 0x00);
- adv7180_write_reg(0xA3, 0x00);
- adv7180_write_reg(0xA4, 0x00);
- adv7180_write_reg(0xA5, 0x00);
- adv7180_write_reg(0xA6, 0x00);
- adv7180_write_reg(0xA7, 0x00);
- adv7180_write_reg(0xA8, 0x00);
- adv7180_write_reg(0xA9, 0x00);
- adv7180_write_reg(0xAA, 0x00);
- adv7180_write_reg(0xAB, 0x00);
- adv7180_write_reg(0xAC, 0x00);
- adv7180_write_reg(0xAD, 0x00);
- adv7180_write_reg(0xAE, 0x60);
- adv7180_write_reg(0xAF, 0x00);
- adv7180_write_reg(0xB0, 0x00);
- adv7180_write_reg(0xB1, 0x60);
adv7180_write_reg(0xB2, 0x1C);
- adv7180_write_reg(0xB3, 0x54);
- adv7180_write_reg(0xB4, 0x00);
- adv7180_write_reg(0xB5, 0x00);
- adv7180_write_reg(0xB6, 0x00);
- adv7180_write_reg(0xB7, 0x13);
- adv7180_write_reg(0xB8, 0x03);
- adv7180_write_reg(0xB9, 0x33);
- adv7180_write_reg(0xBF, 0x02);
- adv7180_write_reg(0xC0, 0x00);
- adv7180_write_reg(0xC1, 0x00);
- adv7180_write_reg(0xC2, 0x00);
adv7180_write_reg(0xC3, 0x00);
adv7180_write_reg(0xC4, 0x00);
- adv7180_write_reg(0xC5, 0x81);
- adv7180_write_reg(0xC6, 0x00);
- adv7180_write_reg(0xC7, 0x00);
- adv7180_write_reg(0xC8, 0x00);
- adv7180_write_reg(0xC9, 0x04);
- adv7180_write_reg(0xCC, 0x69);
- adv7180_write_reg(0xCD, 0x00);
- adv7180_write_reg(0xCE, 0x01);
- adv7180_write_reg(0xCF, 0xB4);
- adv7180_write_reg(0xD0, 0x00);
- adv7180_write_reg(0xD1, 0x10);
- adv7180_write_reg(0xD2, 0xFF);
- adv7180_write_reg(0xD3, 0xFF);
- adv7180_write_reg(0xD4, 0x7F);
- adv7180_write_reg(0xD5, 0x7F);
- adv7180_write_reg(0xD6, 0x3E);
- adv7180_write_reg(0xD7, 0x08);
- adv7180_write_reg(0xD8, 0x3C);
- adv7180_write_reg(0xD9, 0x08);
- adv7180_write_reg(0xDA, 0x3C);
- adv7180_write_reg(0xDB, 0x9B);
adv7180_write_reg(0xDC, 0xAC);
adv7180_write_reg(0xDD, 0x4C);
- adv7180_write_reg(0xDE, 0x00);
- adv7180_write_reg(0xDF, 0x00);
- adv7180_write_reg(0xE0, 0x14);
adv7180_write_reg(0xE1, 0x80);
adv7180_write_reg(0xE2, 0x80);
adv7180_write_reg(0xE3, 0x80);
adv7180_write_reg(0xE4, 0x80);
adv7180_write_reg(0xE5, 0x25);
- adv7180_write_reg(0xE6, 0x44);
+ adv7180_write_reg(0xE6, 0x44);//0x04
adv7180_write_reg(0xE7, 0x63);
adv7180_write_reg(0xE8, 0x65);
adv7180_write_reg(0xE9, 0x14);
adv7180_write_reg(0xEA, 0x63);
adv7180_write_reg(0xEB, 0x55);
adv7180_write_reg(0xEC, 0x55);
- adv7180_write_reg(0xEE, 0x00);
- adv7180_write_reg(0xEF, 0x4A);
- adv7180_write_reg(0xF0, 0x44);
- adv7180_write_reg(0xF1, 0x0C);
- adv7180_write_reg(0xF2, 0x32);
adv7180_write_reg(0xF3, 0x00);
- adv7180_write_reg(0xF4, 0x3F);
- adv7180_write_reg(0xF5, 0xE0);
- adv7180_write_reg(0xF6, 0x69);
- adv7180_write_reg(0xF7, 0x10);
+ adv7180_write_reg(0xF4, 0x15);
adv7180_write_reg(0xF8, 0x00);
adv7180_write_reg(0xF9, 0x03);
- adv7180_write_reg(0xFA, 0xFA);
adv7180_write_reg(0xFB, 0x40);
+ adv7180_write_reg(0xFC, 0x04);//was missing
}
/*! ADV7180 I2C attach function.
@@ -1194,15 +1051,14 @@ static void adv7180_hard_reset(bool cvbs)
static int adv7180_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
- int rev_id;
int ret = 0;
u32 cvbs = true;
struct pinctrl *pinctrl;
struct device *dev = &client->dev;
- printk(KERN_ERR"DBG sensor data is at %p\n", &adv7180_data);
+ dev_dbg(dev, "%s sensor data is at %p\n", __func__, &adv7180_data);
- /* ov5640 pinctrl */
+ /* adv7180 pinctrl */
pinctrl = devm_pinctrl_get_select_default(dev);
if (IS_ERR(pinctrl)) {
dev_err(dev, "setup pinctrl failed\n");
@@ -1211,15 +1067,15 @@ static int adv7180_probe(struct i2c_client *client,
/* request power down pin */
pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
- if (!gpio_is_valid(pwn_gpio)) {
- dev_err(dev, "no sensor pwdn pin available\n");
- return -ENODEV;
- }
- ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+ if (!gpio_is_valid(pwn_gpio))
+ dev_warn(dev, "no sensor pwdn pin available\n");
+ else {
+ ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
"adv7180_pwdn");
- if (ret < 0) {
- dev_err(dev, "no power pin available!\n");
- return ret;
+ if (ret < 0) {
+ dev_err(dev, "no power pin available!\n");
+ //return ret;
+ }
}
adv7180_regulator_enable(dev);
@@ -1269,6 +1125,9 @@ static int adv7180_probe(struct i2c_client *client,
return ret;
}
+ /* ADV7180 is always parallel IF */
+ adv7180_data.sen.mipi_camera = 0;
+
clk_prepare_enable(adv7180_data.sen.sensor_clk);
dev_dbg(&adv7180_data.sen.i2c_client->dev,
@@ -1276,10 +1135,26 @@ static int adv7180_probe(struct i2c_client *client,
__func__, adv7180_data.sen.i2c_client->addr);
/*! Read the revision ID of the tvin chip */
- rev_id = adv7180_read(ADV7180_IDENT);
- dev_dbg(dev,
- "%s:Analog Device adv7%2X0 detected!\n", __func__,
- rev_id);
+ adv7180_data.rev_id = adv7180_read(ADV7180_IDENT);
+ switch(adv7180_data.rev_id) {
+ case 0x1b:
+ case 0x1c:
+ case 0x1e:
+ dev_dbg(dev,
+ "%s:Analog Device adv7180 ident %2X detected!\n", __func__,
+ adv7180_data.rev_id);
+ break;
+ case 0x40:
+ case 0x41:
+ dev_dbg(dev,
+ "%s:Analog Device adv7182 ident %2X detected!\n", __func__,
+ adv7180_data.rev_id);
+ break;
+ default:
+ dev_dbg(dev,
+ "%s:Analog Device adv7180 not detected!\n", __func__);
+ return -ENODEV;
+ }
ret = of_property_read_u32(dev->of_node, "cvbs", &(cvbs));
if (ret) {
diff --git a/drivers/media/platform/mxc/capture/adv7280.c b/drivers/media/platform/mxc/capture/adv7280.c
new file mode 100644
index 000000000000..b31e09ab9414
--- /dev/null
+++ b/drivers/media/platform/mxc/capture/adv7280.c
@@ -0,0 +1,1080 @@
+/*
+ * Copyright 2016 Toradex AG.
+ *
+ * Based on adv7180/max9526 driver for iMX6 and adv7280 driver for Tegra
+ * by Antmicro
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-chip-ident.h>
+#include "v4l2-int-device.h"
+#include "mxc_v4l2_capture.h"
+
+#define ADV7280_VOLTAGE_ANALOG 1800000
+#define ADV7280_VOLTAGE_DIGITAL_CORE 1800000
+#define ADV7280_VOLTAGE_DIGITAL_IO 3300000
+#define ADV7280_VOLTAGE_PLL 1800000
+
+static struct regulator *dvddio_regulator;
+static struct regulator *dvdd_regulator;
+static struct regulator *avdd_regulator;
+static struct regulator *pvdd_regulator;
+static int pwn_gpio;
+
+struct sensor {
+ struct sensor_data sen;
+ v4l2_std_id std_id;
+ int rev_id;
+} adv7280_data;
+
+typedef enum {
+ ADV7280_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
+ ADV7280_PAL, /*!< (B, G, H, I, N)PAL video signal. */
+ ADV7280_NOT_LOCKED, /*!< Not locked on a signal. */
+} video_fmt_idx;
+
+struct video_fmt_t {
+ int v4l2_id;
+ char name[16];
+ u16 raw_width;
+ u16 raw_height;
+ u16 active_width;
+ u16 active_height;
+ int frame_rate;
+};
+
+static const struct video_fmt_t video_fmts[] = {
+ {
+ .v4l2_id = V4L2_STD_NTSC,
+ .name = "NTSC",
+ .raw_width = 720,
+ .raw_height = 525,
+ .active_width = 720,
+ .active_height = 480,
+ .frame_rate = 30,
+ },
+ {
+ .v4l2_id = V4L2_STD_PAL,
+ .name = "PAL",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ .frame_rate = 25,
+ },
+ {
+ .v4l2_id = V4L2_STD_ALL,
+ .name = "Autodetect",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ .frame_rate = 0,
+ },
+};
+
+static video_fmt_idx video_idx = ADV7280_PAL;
+
+static DEFINE_MUTEX(mutex);
+
+#define IF_NAME "adv7280"
+
+#define ADV7280_INPUT_CONTROL 0x00
+#define ADV7280_VIDEO_SELECTION_1 0x01
+#define ADV7280_VIDEO_SELECTION_2 0x02
+#define ADV7280_OUTPUT_CONTROL 0x03
+#define ADV7280_EXTENDED_OUTPUT_CONTROL 0x04
+#define ADV7280_AUTODETECT_ENABLE 0x07
+#define ADV7280_BRIGHTNESS 0x0A
+#define ADV7280_ADI_CONTROL_1 0x0E
+#define ADV7280_POWER_MANAGEMENT 0x0F
+#define ADV7280_STATUS_1 0x10
+#define ADV7280_IDENT 0x11
+#define ADV7280_STATUS_3 0x13
+#define ADV7280_SHAPING_FILTER_CONTROL_1 0x17
+#define ADV7280_ADI_CONTROL_2 0x1D
+#define ADV7280_PIXEL_DELAY_CONTROL 0x27
+#define ADV7280_VPP_SLAVE_ADDRESS 0xFD
+#define ADV7280_OUTPUT_SYNC_SELECT_2 0x6B
+#define ADV7280_SD_SATURATION_CB 0xe3
+#define ADV7280_SD_SATURATION_CR 0xe4
+
+#define HW_DEINT /* Enable hardware deinterlacer */
+#define VPP_SLAVE_ADDRESS 0x42
+
+#define VPP_DEINT_RESET 0x41
+#define VPP_I2C_DEINT_ENABLE 0x55
+#define VPP_ADV_TIMING_MODE_EN 0x5B
+
+#define ADV7280_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
+#define ADV7280_AUTODETECT_DEFAULT 0x7f
+
+#define ADV7280_INPUT_CONTROL_COMPOSITE_IN1 0x00
+#define ADV7280_INPUT_CONTROL_AD_PAL_BG_NTSC_J_SECAM 0x00
+
+#define ADV7280_INPUT_CONTROL_NTSC_M 0x50
+#define ADV7280_INPUT_CONTROL_PAL60 0x60
+#define ADV7280_INPUT_CONTROL_NTSC_443 0x70
+#define ADV7280_INPUT_CONTROL_PAL_BG 0x80
+#define ADV7280_INPUT_CONTROL_PAL_N 0x90
+#define ADV7280_INPUT_CONTROL_PAL_M 0xa0
+#define ADV7280_INPUT_CONTROL_PAL_M_PED 0xb0
+#define ADV7280_INPUT_CONTROL_PAL_COMB_N 0xc0
+#define ADV7280_INPUT_CONTROL_PAL_COMB_N_PED 0xd0
+#define ADV7280_INPUT_CONTROL_PAL_SECAM 0xe0
+
+#define ADV7280_STATUS1_IN_LOCK 0x01
+/* Autodetection results */
+#define ADV7280_STATUS1_AUTOD_MASK 0x70
+#define ADV7280_STATUS1_AUTOD_NTSM_M_J 0x00
+#define ADV7280_STATUS1_AUTOD_NTSC_4_43 0x10
+#define ADV7280_STATUS1_AUTOD_PAL_M 0x20
+#define ADV7280_STATUS1_AUTOD_PAL_60 0x30
+#define ADV7280_STATUS1_AUTOD_PAL_B_G 0x40
+#define ADV7280_STATUS1_AUTOD_SECAM 0x50
+#define ADV7280_STATUS1_AUTOD_PAL_COMB 0x60
+#define ADV7280_STATUS1_AUTOD_SECAM_525 0x70
+
+static const struct v4l2_queryctrl adv7280_qctrl[] = {
+ {
+ .id = V4L2_CID_BRIGHTNESS,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Brightness",
+ .minimum = 0,
+ .maximum = 255,
+ .step = 1,
+ .default_value = 127,
+ .flags = 0,
+ }, {
+ .id = V4L2_CID_SATURATION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Saturation",
+ .minimum = 0,
+ .maximum = 255,
+ .step = 0x1,
+ .default_value = 127,
+ .flags = 0,
+ }
+};
+
+static inline void adv7280_power_down(int enable)
+{
+ if (gpio_is_valid(pwn_gpio)) {
+ gpio_set_value_cansleep(pwn_gpio, !enable);
+ msleep(2);
+ }
+}
+
+static int adv7280_regulator_enable(struct device *dev)
+{
+ int ret = 0;
+
+ dvddio_regulator = devm_regulator_get(dev, "DOVDD");
+
+ if (!IS_ERR(dvddio_regulator)) {
+ regulator_set_voltage(dvddio_regulator,
+ ADV7280_VOLTAGE_DIGITAL_IO,
+ ADV7280_VOLTAGE_DIGITAL_IO);
+ ret = regulator_enable(dvddio_regulator);
+ if (ret) {
+ dev_err(dev, "set io voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set io voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get io voltage\n");
+ dvddio_regulator = NULL;
+ }
+
+ dvdd_regulator = devm_regulator_get(dev, "DVDD");
+ if (!IS_ERR(dvdd_regulator)) {
+ regulator_set_voltage(dvdd_regulator,
+ ADV7280_VOLTAGE_DIGITAL_CORE,
+ ADV7280_VOLTAGE_DIGITAL_CORE);
+ ret = regulator_enable(dvdd_regulator);
+ if (ret) {
+ dev_err(dev, "set core voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set core voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get core voltage\n");
+ dvdd_regulator = NULL;
+ }
+
+ avdd_regulator = devm_regulator_get(dev, "AVDD");
+ if (!IS_ERR(avdd_regulator)) {
+ regulator_set_voltage(avdd_regulator,
+ ADV7280_VOLTAGE_ANALOG,
+ ADV7280_VOLTAGE_ANALOG);
+ ret = regulator_enable(avdd_regulator);
+ if (ret) {
+ dev_err(dev, "set analog voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set analog voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get analog voltage\n");
+ avdd_regulator = NULL;
+ }
+
+ pvdd_regulator = devm_regulator_get(dev, "PVDD");
+ if (!IS_ERR(pvdd_regulator)) {
+ regulator_set_voltage(pvdd_regulator,
+ ADV7280_VOLTAGE_PLL,
+ ADV7280_VOLTAGE_PLL);
+ ret = regulator_enable(pvdd_regulator);
+ if (ret) {
+ dev_err(dev, "set pll voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set pll voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get pll voltage\n");
+ pvdd_regulator = NULL;
+ }
+
+ return ret;
+}
+
+static inline int adv7280_read(u8 reg)
+{
+ int val;
+
+ val = i2c_smbus_read_byte_data(adv7280_data.sen.i2c_client, reg);
+ if (val < 0) {
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x\n", __func__, reg);
+ return val;
+ }
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ return val;
+}
+
+static int adv7280_write_reg(u8 reg, u8 val)
+{
+ s32 ret;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ ret = i2c_smbus_write_byte_data(adv7280_data.sen.i2c_client, reg, val);
+ if (ret < 0) {
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int adv7280_write_reg_with_client(struct i2c_client *client,
+ u8 reg, u8 val)
+{
+ s32 ret;
+
+ dev_dbg(&client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ ret = i2c_smbus_write_byte_data(client, reg, val);
+ if (ret < 0) {
+ dev_dbg(&client->dev,
+ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void adv7280_get_std(v4l2_std_id *std)
+{
+ int status_1, standard, idx;
+ bool locked = 0;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "In %s\n", __func__);
+
+ status_1 = adv7280_read(ADV7280_STATUS_1);
+ locked = status_1 & ADV7280_STATUS1_IN_LOCK;
+ standard = status_1 & ADV7280_STATUS1_AUTOD_MASK;
+
+ mutex_lock(&mutex);
+ *std = V4L2_STD_ALL;
+ idx = ADV7280_NOT_LOCKED;
+ if (locked) {
+ if (standard == ADV7280_STATUS1_AUTOD_PAL_B_G) {
+ *std = V4L2_STD_PAL;
+ idx = ADV7280_PAL;
+ } else if (standard == ADV7280_STATUS1_AUTOD_NTSM_M_J) {
+ *std = V4L2_STD_NTSC;
+ idx = ADV7280_NTSC;
+ }
+ }
+ mutex_unlock(&mutex);
+
+ /* This assumes autodetect which this device uses. */
+ if (*std != adv7280_data.std_id) {
+ video_idx = idx;
+ adv7280_data.std_id = *std;
+ adv7280_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ adv7280_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ }
+}
+
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+
+ dev_dbg(dev, "adv7280: %s\n", __func__);
+
+ if (s == NULL) {
+ dev_err(dev, " ERROR!! no slave device set!\n");
+ return -1;
+ }
+
+ memset(p, 0, sizeof(*p));
+ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
+#if 0
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 1;
+ p->u.bt656.bt_sync_correct = 1;
+#else
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 0;
+ p->u.bt656.bt_sync_correct = 0;
+#ifdef HW_DEINT
+ p->u.bt656.clock_curr = 1; /* BT656 de-interlace clock mode */
+#endif
+#endif
+ /* ADV7280 has a dedicated clock so no clock settings needed. */
+
+ return 0;
+}
+
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+ struct sensor *sensor = s->priv;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ if (on && !sensor->sen.on) {
+ if (adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x04) != 0)
+ return -EIO;
+
+ msleep(400);
+
+ } else if (!on && sensor->sen.on) {
+ if (adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x24) != 0)
+ return -EIO;
+ }
+
+ sensor->sen.on = on;
+
+ return 0;
+}
+
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor *sensor = s->priv;
+ struct v4l2_captureparm *cparm = &a->parm.capture;
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+
+ dev_dbg(dev, "adv7280: %s\n", __func__);
+
+ switch (a->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ dev_dbg(dev, " type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+ memset(a, 0, sizeof(*a));
+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ cparm->capability = sensor->sen.streamcap.capability;
+ cparm->timeperframe = sensor->sen.streamcap.timeperframe;
+ cparm->capturemode = sensor->sen.streamcap.capturemode;
+ break;
+
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ dev_dbg(dev, "ioctl_g_parm:type is unknown %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+
+ dev_dbg(dev, "adv7280: %s\n", __func__);
+
+ switch (a->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ dev_dbg(dev, " type is unknown - %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+ struct sensor *sensor = s->priv;
+ v4l2_std_id std;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ dev_dbg(dev, " Returning size of %dx%d\n",
+ sensor->sen.pix.width, sensor->sen.pix.height);
+ f->fmt.pix = sensor->sen.pix;
+ break;
+
+ case V4L2_BUF_TYPE_PRIVATE:
+ adv7280_get_std(&std);
+ f->fmt.pix.pixelformat = (u32)std;
+ break;
+
+ default:
+ f->fmt.pix = sensor->sen.pix;
+ break;
+ }
+
+ return 0;
+}
+
+static int ioctl_queryctrl(struct v4l2_int_device *s,
+ struct v4l2_queryctrl *qc)
+{
+ int i;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ for (i = 0; i < ARRAY_SIZE(adv7280_qctrl); i++)
+ if (qc->id && qc->id == adv7280_qctrl[i].id) {
+ *qc = adv7280_qctrl[i];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int ret = 0;
+ int sat = 0;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ adv7280_data.sen.brightness = adv7280_read(ADV7280_BRIGHTNESS);
+ vc->value = adv7280_data.sen.brightness;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ vc->value = adv7280_data.sen.contrast;
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ sat = adv7280_read(ADV7280_SD_SATURATION_CB);
+ adv7280_data.sen.saturation = sat;
+ vc->value = adv7280_data.sen.saturation;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ vc->value = adv7280_data.sen.hue;
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ vc->value = adv7280_data.sen.red;
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ vc->value = adv7280_data.sen.blue;
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ vc->value = adv7280_data.sen.ae_mode;
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " Default case\n");
+ vc->value = 0;
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int retval = 0;
+ u8 tmp;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ tmp = vc->value;
+ adv7280_write_reg(ADV7280_BRIGHTNESS, tmp);
+ adv7280_data.sen.brightness = vc->value;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ tmp = vc->value;
+ adv7280_write_reg(ADV7280_SD_SATURATION_CB, tmp);
+ adv7280_write_reg(ADV7280_SD_SATURATION_CR, tmp);
+ adv7280_data.sen.saturation = vc->value;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " Default case\n");
+ retval = -EINVAL;
+ break;
+ }
+
+ return retval;
+}
+
+static int ioctl_enum_framesizes(struct v4l2_int_device *s,
+ struct v4l2_frmsizeenum *fsize)
+{
+ if (fsize->index >= 1)
+ return -EINVAL;
+
+ fsize->discrete.width = video_fmts[video_idx].active_width;
+ fsize->discrete.height = video_fmts[video_idx].active_height;
+
+ return 0;
+}
+
+static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
+ struct v4l2_frmivalenum *fival)
+{
+ struct video_fmt_t fmt;
+ int i;
+
+ if (fival->index != 0)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(video_fmts) - 1; i++) {
+ fmt = video_fmts[i];
+ if (fival->width == fmt.active_width &&
+ fival->height == fmt.active_height) {
+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+ fival->discrete.numerator = 1;
+ fival->discrete.denominator = fmt.frame_rate;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
+{
+ ((struct v4l2_dbg_chip_ident *)id)->match.type =
+ V4L2_CHIP_MATCH_I2C_DRIVER;
+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
+ "adv7280_decoder");
+ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_ADV7280;
+
+ return 0;
+}
+
+static int ioctl_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ return 0;
+}
+
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ return 0;
+}
+
+static struct v4l2_int_ioctl_desc adv7280_ioctl_desc[] = {
+
+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init},
+
+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power},
+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm},
+ {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init},
+
+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap},
+
+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm},
+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm},
+ {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl},
+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl},
+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl},
+ {vidioc_int_enum_framesizes_num,
+ (v4l2_int_ioctl_func *)ioctl_enum_framesizes},
+ {vidioc_int_enum_frameintervals_num,
+ (v4l2_int_ioctl_func *)
+ ioctl_enum_frameintervals},
+ {vidioc_int_g_chip_ident_num,
+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident},
+};
+
+static struct v4l2_int_slave adv7280_slave = {
+ .ioctls = adv7280_ioctl_desc,
+ .num_ioctls = ARRAY_SIZE(adv7280_ioctl_desc),
+};
+
+static struct v4l2_int_device adv7280_int_device = {
+ .module = THIS_MODULE,
+ .name = "adv7280",
+ .type = v4l2_int_type_slave,
+ .u = {
+ .slave = &adv7280_slave,
+ },
+};
+
+static int adv7280_hard_reset(void)
+{
+ int ret;
+
+ struct i2c_client vpp_client = {
+ .flags = adv7280_data.sen.i2c_client->flags,
+ .addr = VPP_SLAVE_ADDRESS,
+ .name = "ADV7280_VPP",
+ .adapter = adv7280_data.sen.i2c_client->adapter,
+ .dev = adv7280_data.sen.i2c_client->dev,
+ };
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "In %s\n", __func__);
+
+ /* Reset */
+ ret = adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0xA0);
+ if (ret < 0)
+ goto error;
+ msleep(10);
+
+ /* Initialize adv7280 */
+ /* Exit Power Down Mode */
+ ret = adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(ADV7280_ADI_CONTROL_1, 0x80);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x9C, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x9C, 0xFF);
+ if (ret < 0)
+ goto error;
+
+ /* Enter User Sub Map */
+ ret = adv7280_write_reg(ADV7280_ADI_CONTROL_1, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* Enable Pixel & Sync output drivers */
+ ret = adv7280_write_reg(ADV7280_OUTPUT_CONTROL, 0x0C);
+ if (ret < 0)
+ goto error;
+
+ /* Power-up INTRQ, HS & VS pads */
+ ret = adv7280_write_reg(ADV7280_EXTENDED_OUTPUT_CONTROL, 0x07);
+ if (ret < 0)
+ goto error;
+
+ /* Enable SH1 */
+ /*
+ ret = adv7280_write_reg(ADV7280_SHAPING_FILTER_CONTROL_1, 0x41);
+ if (ret < 0)
+ goto error;
+ */
+
+ /* Disable comb filtering */
+ /*
+ ret = adv7280_write_reg(0x39, 0x24);
+ if (ret < 0)
+ goto error;
+ */
+
+ /* Enable LLC output driver */
+ ret = adv7280_write_reg(ADV7280_ADI_CONTROL_2, 0x40);
+ if (ret < 0)
+ goto error;
+
+ /* VSYNC on VS/FIELD/SFL pin */
+ ret = adv7280_write_reg(ADV7280_OUTPUT_SYNC_SELECT_2, 0x01);
+ if (ret < 0)
+ goto error;
+
+ /* Enable autodetection */
+ ret = adv7280_write_reg(ADV7280_INPUT_CONTROL,
+ ADV7280_INPUT_CONTROL_AD_PAL_BG_NTSC_J_SECAM |
+ (ADV7280_INPUT_CONTROL_COMPOSITE_IN1 +
+ 0));
+ if (ret < 0)
+ goto error;
+
+ ret = adv7280_write_reg(ADV7280_AUTODETECT_ENABLE,
+ ADV7280_AUTODETECT_DEFAULT);
+ if (ret < 0)
+ goto error;
+
+ /* ITU-R BT.656-4 compatible */
+ /*ret = adv7280_write_reg(ADV7280_EXTENDED_OUTPUT_CONTROL,
+ ADV7280_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
+ if (ret < 0)
+ goto error;
+ */
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x52, 0xCD);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x80, 0x51);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x81, 0x51);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x82, 0x68);
+ if (ret < 0)
+ goto error;
+
+#ifdef HW_DEINT
+ /* Set VPP Map */
+ ret = adv7280_write_reg(ADV7280_VPP_SLAVE_ADDRESS, (VPP_SLAVE_ADDRESS << 1));
+ if (ret < 0)
+ goto error;
+
+ /* VPP - not documented */
+ ret = adv7280_write_reg_with_client(&vpp_client,
+ 0xA3, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* VPP - Enbable Advanced Timing Mode */
+ ret = adv7280_write_reg_with_client(&vpp_client,
+ VPP_ADV_TIMING_MODE_EN, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* VPP - Enable Deinterlacer */
+ ret = adv7280_write_reg_with_client(&vpp_client,
+ VPP_I2C_DEINT_ENABLE, 0x80);
+ if (ret < 0)
+ goto error;
+#endif
+
+ return 0;
+
+error:
+ return ret;
+}
+
+static int adv7280_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret = 0;
+ struct pinctrl *pinctrl;
+ struct device *dev = &client->dev;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(dev, "Required functionality not supported by I2C adapter\n");
+ return -EIO;
+ }
+
+ v4l_info(client, "chip found @ 0x%02x (%s)\n",
+ client->addr << 1, client->adapter->name);
+
+ pinctrl = devm_pinctrl_get_select_default(dev);
+ if (IS_ERR(pinctrl)) {
+ dev_err(dev, "setup pinctrl failed\n");
+ return PTR_ERR(pinctrl);
+ }
+
+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
+ if (!gpio_is_valid(pwn_gpio))
+ dev_warn(dev, "no sensor pwdn pin available\n");
+ else {
+ ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+ "adv7280_pwdn");
+ if (ret < 0)
+ dev_err(dev, "no power pin available!\n");
+ }
+
+ adv7280_regulator_enable(dev);
+
+ adv7280_power_down(0);
+
+ msleep(1);
+
+ memset(&adv7280_data, 0, sizeof(adv7280_data));
+ adv7280_data.sen.i2c_client = client;
+ adv7280_data.sen.streamcap.timeperframe.denominator = 30;
+ adv7280_data.sen.streamcap.timeperframe.numerator = 1;
+ adv7280_data.std_id = V4L2_STD_ALL;
+ video_idx = ADV7280_NOT_LOCKED;
+ adv7280_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ adv7280_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ adv7280_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */
+ adv7280_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */
+ adv7280_data.sen.on = true;
+
+ adv7280_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk");
+ if (IS_ERR(adv7280_data.sen.sensor_clk)) {
+ dev_err(dev, "get mclk failed\n");
+ return PTR_ERR(adv7280_data.sen.sensor_clk);
+ }
+
+ ret = of_property_read_u32(dev->of_node, "mclk",
+ &adv7280_data.sen.mclk);
+ if (ret) {
+ dev_err(dev, "mclk frequency is invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(
+ dev->of_node, "mclk_source",
+ (u32 *) &(adv7280_data.sen.mclk_source));
+ if (ret) {
+ dev_err(dev, "mclk_source invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "csi_id",
+ &(adv7280_data.sen.csi));
+ if (ret) {
+ dev_err(dev, "csi_id invalid\n");
+ return ret;
+ }
+
+ /* ADV7280 is always parallel IF */
+ adv7280_data.sen.mipi_camera = 0;
+
+ clk_prepare_enable(adv7280_data.sen.sensor_clk);
+
+ adv7280_data.rev_id = adv7280_read(ADV7280_IDENT);
+ switch (adv7280_data.rev_id) {
+ case 0x42:
+ dev_dbg(dev,
+ "%s:Analog Device adv7280 ident %2X detected!\n",
+ __func__, adv7280_data.rev_id);
+ break;
+ default:
+ dev_err(dev,
+ "%s:Analog Device adv7280 not detected %d!\n", __func__,
+ adv7280_data.rev_id);
+ return -ENODEV;
+
+ }
+
+ dev_dbg(dev, " type is %d (expect %d)\n",
+ adv7280_int_device.type, v4l2_int_type_slave);
+ dev_dbg(dev, " num ioctls is %d\n",
+ adv7280_int_device.u.slave->num_ioctls);
+
+ ret = adv7280_hard_reset();
+ if (ret) {
+ dev_err(dev, "error resetting adv7280\n");
+ return ret;
+ }
+
+ /* This function attaches this structure to the /dev/video0 device.
+ * The pointer in priv points to the adv7280_data structure here.*/
+ adv7280_int_device.priv = &adv7280_data;
+ ret = v4l2_int_device_register(&adv7280_int_device);
+
+ clk_disable_unprepare(adv7280_data.sen.sensor_clk);
+
+ return 0;
+}
+
+static int adv7280_detach(struct i2c_client *client)
+{
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:Removing %s video decoder @ 0x%02X from adapter %s\n",
+ __func__, IF_NAME, client->addr << 1, client->adapter->name);
+
+ adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x24);
+
+ if (dvddio_regulator)
+ regulator_disable(dvddio_regulator);
+
+ if (dvdd_regulator)
+ regulator_disable(dvdd_regulator);
+
+ if (avdd_regulator)
+ regulator_disable(avdd_regulator);
+
+ if (pvdd_regulator)
+ regulator_disable(pvdd_regulator);
+
+ v4l2_int_device_unregister(&adv7280_int_device);
+
+ return 0;
+}
+
+static const struct i2c_device_id adv7280_id[] = {
+ {"adv7280", 0},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, adv7280_id);
+
+static struct i2c_driver adv7280_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "adv7280",
+ },
+ .probe = adv7280_probe,
+ .remove = adv7280_detach,
+ .id_table = adv7280_id,
+};
+module_i2c_driver(adv7280_i2c_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("Analog Device ADV7280 video decoder driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/mxc/capture/ipu_csi_enc.c b/drivers/media/platform/mxc/capture/ipu_csi_enc.c
index 3a824a9659e7..819b76ed1d4b 100644
--- a/drivers/media/platform/mxc/capture/ipu_csi_enc.c
+++ b/drivers/media/platform/mxc/capture/ipu_csi_enc.c
@@ -262,7 +262,7 @@ static int csi_enc_enabling_tasks(void *private)
err = ipu_request_irq(
cam->ipu, irq, csi_enc_callback, 0, "Mxc Camera", cam);
if (err != 0) {
- printk(KERN_ERR "Error registering rot irq\n");
+ pr_err("%s: Error requesting IPU_IRQ_CSI0_OUT_EOF\n", __func__);
return err;
}
diff --git a/drivers/media/platform/mxc/capture/ipu_prp_enc.c b/drivers/media/platform/mxc/capture/ipu_prp_enc.c
index 1e4420b952f8..bcd7405879cb 100644
--- a/drivers/media/platform/mxc/capture/ipu_prp_enc.c
+++ b/drivers/media/platform/mxc/capture/ipu_prp_enc.c
@@ -384,6 +384,7 @@ static int prp_enc_enabling_tasks(void *private)
{
cam_data *cam = (cam_data *) private;
int err = 0;
+ int irq;
CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n");
cam->dummy_frame.vaddress = dma_alloc_coherent(0,
@@ -400,15 +401,12 @@ static int prp_enc_enabling_tasks(void *private)
PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
- if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
- err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF,
- prp_enc_callback, 0, "Mxc Camera", cam);
- } else {
- err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF,
- prp_enc_callback, 0, "Mxc Camera", cam);
- }
- if (err != 0) {
- printk(KERN_ERR "Error registering rot irq\n");
+ irq = (cam->rotation >= IPU_ROTATE_90_RIGHT) ?
+ IPU_IRQ_PRP_ENC_ROT_OUT_EOF : IPU_IRQ_PRP_ENC_OUT_EOF;
+ err = ipu_request_irq(cam->ipu, irq,
+ prp_enc_callback, 0, "Mxc Camera", cam);
+ if (err) {
+ pr_err("%s: Error requesting irq=%d\n", __func__, irq);
return err;
}
diff --git a/drivers/media/platform/mxc/capture/max9526.c b/drivers/media/platform/mxc/capture/max9526.c
new file mode 100644
index 000000000000..06242b727ca2
--- /dev/null
+++ b/drivers/media/platform/mxc/capture/max9526.c
@@ -0,0 +1,1153 @@
+/*
+ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2015 Toradex AG All Rights Reserved.
+ * copied and adapted from adv7180.c
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file max9526.c
+ *
+ * @brief Maxim Integrated MAX9526 video decoder functions
+ *
+ * @ingroup Camera
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-chip-ident.h>
+#include "v4l2-int-device.h"
+#include "mxc_v4l2_capture.h"
+
+#if 0
+#undef dev_dbg
+#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);}
+#undef pr_debug
+#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
+#define MAX9526_VOLTAGE_ANALOG 1800000
+#define MAX9526_VOLTAGE_DIGITAL_CORE 1800000
+#define MAX9526_VOLTAGE_DIGITAL_IO 3300000
+#define MAX9526_VOLTAGE_PLL 1800000
+
+static struct regulator *dvddio_regulator;
+static struct regulator *dvdd_regulator;
+static struct regulator *avdd_regulator;
+
+static int max9526_probe(struct i2c_client *adapter,
+ const struct i2c_device_id *id);
+static int max9526_detach(struct i2c_client *client);
+
+static const struct i2c_device_id max9526_id[] = {
+ {"max9526", 0},
+ {},
+};
+
+MODULE_DEVICE_TABLE(i2c, max9526_id);
+
+static struct i2c_driver max9526_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "max9526",
+ },
+ .probe = max9526_probe,
+ .remove = max9526_detach,
+ .id_table = max9526_id,
+};
+
+/*!
+ * Maintains the information on the current state of the sensor.
+ */
+struct sensor {
+ struct sensor_data sen;
+ v4l2_std_id std_id;
+} max9526_data;
+
+
+/*! List of input video formats supported. The video formats is corresponding
+ * with v4l2 id in video_fmt_t
+ */
+typedef enum {
+ MAX9526_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
+ MAX9526_PAL, /*!< (B, G, H, I, N)PAL video signal. */
+ MAX9526_NOT_LOCKED, /*!< Not locked on a signal. */
+} video_fmt_idx;
+
+/*! Number of video standards supported (including 'not locked' signal). */
+#define MAX9526_STD_MAX (MAX9526_PAL + 1)
+
+/*! Video format structure. */
+typedef struct {
+ int v4l2_id; /*!< Video for linux ID. */
+ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */
+ u16 raw_width; /*!< Raw width. */
+ u16 raw_height; /*!< Raw height. */
+ u16 active_width; /*!< Active width. */
+ u16 active_height; /*!< Active height. */
+} video_fmt_t;
+
+/*! Description of video formats supported.
+ *
+ * PAL: raw=720x625, active=720x576.
+ * NTSC: raw=720x525, active=720x480.
+ */
+static video_fmt_t video_fmts[] = {
+ { /*! NTSC */
+ .v4l2_id = V4L2_STD_NTSC,
+ .name = "NTSC",
+ .raw_width = 720, /* SENS_FRM_WIDTH */
+ .raw_height = 525, /* SENS_FRM_HEIGHT */
+ .active_width = 720, /* ACT_FRM_WIDTH plus 1 */
+ .active_height = 480, /* ACT_FRM_WIDTH plus 1 */
+ },
+ { /*! (B, G, H, I, N) PAL */
+ .v4l2_id = V4L2_STD_PAL,
+ .name = "PAL",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ },
+ { /*! Unlocked standard */
+ .v4l2_id = V4L2_STD_ALL,
+ .name = "Autodetect",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ },
+};
+
+/*!* Standard index of MAX9526. */
+static video_fmt_idx video_idx = MAX9526_PAL;
+
+/*! @brief This mutex is used to provide mutual exclusion.
+ *
+ * Create a mutex that can be used to provide mutually exclusive
+ * read/write access to the globally accessible data structures
+ * and variables that were defined above.
+ */
+static DEFINE_MUTEX(mutex);
+
+#define IF_NAME "max9526"
+/* registers */
+#define REG_STATUS_0 0x00
+#define REG_STATUS_1 0x01
+#define REG_IRQMASK_0 0x02
+#define REG_IRQMASK_1 0x03
+#define REG_STANDARD_SELECT_SHUTDOWN_CONTROL 0x04
+#define REG_CONTRAST 0x05
+#define REG_BRIGHTNESS 0x06
+#define REG_HUE 0x07
+#define REG_SATURATION 0x08
+#define REG_VIDEO_INPUT_SELECT_AND_CLAMP 0x09
+#define REG_GAIN_CONTROL 0x0A
+#define REG_COLOR_KILL 0x0B
+#define REG_OUTPUT_TEST_SIGNAL 0x0C
+#define REG_CLOCK_AND_OUTPUT 0x0D
+#define REG_PLL_CONTROL 0x0E
+#define REG_MISCELLANEOUS 0x0F
+
+#define I2C_RETRY_COUNT 5
+
+/* supported controls */
+/* This hasn't been fully implemented yet.
+ * This is how it should work, though. */
+static struct v4l2_queryctrl max9526_qctrl[] = {
+ {
+ .id = V4L2_CID_BRIGHTNESS,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Brightness",
+ .minimum = 0, /* check this value */
+ .maximum = 255, /* check this value */
+ .step = 1, /* check this value */
+ .default_value = 127, /* check this value */
+ .flags = 0,
+ }, {
+ .id = V4L2_CID_SATURATION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Saturation",
+ .minimum = 0, /* check this value */
+ .maximum = 255, /* check this value */
+ .step = 0x1, /* check this value */
+ .default_value = 127, /* check this value */
+ .flags = 0,
+ }
+};
+
+static inline void max9526_power_down(int enable)
+{
+}
+
+static int max9526_regulator_enable(struct device *dev)
+{
+ int ret = 0;
+
+ dvddio_regulator = devm_regulator_get(dev, "DVDDIO");
+
+ if (!IS_ERR(dvddio_regulator)) {
+ regulator_set_voltage(dvddio_regulator,
+ MAX9526_VOLTAGE_DIGITAL_IO,
+ MAX9526_VOLTAGE_DIGITAL_IO);
+ ret = regulator_enable(dvddio_regulator);
+ if (ret) {
+ dev_err(dev, "set io voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set io voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get io voltage\n");
+ }
+
+ dvdd_regulator = devm_regulator_get(dev, "DVDD");
+ if (!IS_ERR(dvdd_regulator)) {
+ regulator_set_voltage(dvdd_regulator,
+ MAX9526_VOLTAGE_DIGITAL_CORE,
+ MAX9526_VOLTAGE_DIGITAL_CORE);
+ ret = regulator_enable(dvdd_regulator);
+ if (ret) {
+ dev_err(dev, "set core voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set core voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get core voltage\n");
+ }
+
+ avdd_regulator = devm_regulator_get(dev, "AVDD");
+ if (!IS_ERR(avdd_regulator)) {
+ regulator_set_voltage(avdd_regulator,
+ MAX9526_VOLTAGE_ANALOG,
+ MAX9526_VOLTAGE_ANALOG);
+ ret = regulator_enable(avdd_regulator);
+ if (ret) {
+ dev_err(dev, "set analog voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set analog voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get analog voltage\n");
+ }
+
+ return ret;
+}
+
+
+/***********************************************************************
+ * I2C transfert.
+ ***********************************************************************/
+
+/*! Read one register from a MAX9526 i2c slave device.
+ *
+ * @param *reg register in the device we wish to access.
+ *
+ * @return 0 if success, an error code otherwise.
+ */
+static inline int __max9526_read__(u8 reg)
+{
+ int val;
+ unsigned retry = 0;
+
+ do {
+ val = i2c_smbus_read_byte_data(max9526_data.sen.i2c_client, reg);
+ if (val < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x, retry %u\n", __func__, reg, retry);
+ val = -1;
+ i2c_recover_bus(max9526_data.sen.i2c_client->adapter);
+ }
+ } while ((val < 0) && (++retry < I2C_RETRY_COUNT));
+
+ if (val < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg ERROR:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ }
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ return val;
+}
+static inline int max9526_read(u8 reg)
+{
+ int val, last_val;
+ unsigned retry = 0;
+
+ last_val = __max9526_read__(reg);
+
+ do {
+ val = __max9526_read__(reg);
+ if (val != last_val) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x, retry %u\n", __func__, reg, retry);
+ last_val = val;
+ val = -1;
+ msleep(1);
+ }
+ } while ((val == -1) && (++retry < I2C_RETRY_COUNT));
+ return val;
+}
+/*! Write one register of a MAX9526 i2c slave device.
+ *
+ * @param *reg register in the device we wish to access.
+ *
+ * @return 0 if success, an error code otherwise.
+ */
+static int max9526_write_reg(u8 reg, u8 val)
+{
+ s32 ret = 0;
+ unsigned retry = 0;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ do {
+ ret = i2c_smbus_write_byte_data(max9526_data.sen.i2c_client, reg, val);
+ if (ret < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:write reg error:reg=%2x,val=%2x, retry %u\n", __func__,
+ reg, val, retry+1);
+ ret = -1;
+ i2c_recover_bus(max9526_data.sen.i2c_client->adapter);
+ }
+ } while ((ret < 0) && (++retry < I2C_RETRY_COUNT));
+
+ if (ret < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:write reg ERROR:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ }
+
+ return ret;
+}
+
+/***********************************************************************
+ * mxc_v4l2_capture interface.
+ ***********************************************************************/
+
+/*!
+ * Return attributes of current video standard.
+ * Since this device autodetects the current standard, this function also
+ * sets the values that need to be changed if the standard changes.
+ * There is no set std equivalent function.
+ *
+ * @return None.
+ */
+static void max9526_get_std(v4l2_std_id *std)
+{
+ int tmp = 0;
+ int idx;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526_get_std\n");
+
+ /* reset the status flag to get current state */
+#if 0
+ (void) max9526_read(REG_STATUS_0);
+ msleep(1);
+ tmp = max9526_read(REG_STATUS_0) & 0x1;
+#endif
+ tmp |= max9526_read(REG_STATUS_1) & 0x40;
+
+ mutex_lock(&mutex);
+ if (tmp == 0x0) {
+ /* PAL */
+ *std = V4L2_STD_PAL;
+ idx = MAX9526_PAL;
+ } else if (tmp == 0x40) {
+ /*NTSC*/
+ *std = V4L2_STD_NTSC;
+ idx = MAX9526_NTSC;
+ } else {
+ *std = V4L2_STD_ALL;
+ idx = MAX9526_NOT_LOCKED;
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "Got invalid video standard!\n");
+ }
+ mutex_unlock(&mutex);
+
+ /* This assumes autodetect which this device uses. */
+ if (*std != max9526_data.std_id) {
+ video_idx = idx;
+ max9526_data.std_id = *std;
+ max9526_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ max9526_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ }
+}
+
+/***********************************************************************
+ * IOCTL Functions from v4l2_int_ioctl_desc.
+ ***********************************************************************/
+
+/*!
+ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
+ * s: pointer to standard V4L2 device structure
+ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
+ *
+ * Gets slave interface parameters.
+ * Calculates the required xclk value to support the requested
+ * clock parameters in p. This value is returned in the p
+ * parameter.
+ *
+ * vidioc_int_g_ifparm returns platform-specific information about the
+ * interface settings used by the sensor.
+ *
+ * Called on open.
+ */
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_g_ifparm\n");
+
+ if (s == NULL) {
+ pr_err(" ERROR!! no slave device set!\n");
+ return -1;
+ }
+
+ /* Initialize structure to 0s then set any non-0 values. */
+ memset(p, 0, sizeof(*p));
+ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
+#if 0
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 1;
+ p->u.bt656.bt_sync_correct = 1;
+#elif 0
+//working for PAL
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 0;
+ p->u.bt656.bt_sync_correct = 0;
+ p->u.bt656.clock_curr = 0; //BT656 interlace clock mode
+#else
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_BT_8BIT;
+ p->u.bt656.nobt_hs_inv = 1;
+ p->u.bt656.nobt_vs_inv = 1;
+ p->u.bt656.bt_sync_correct = 0;
+ p->u.bt656.clock_curr = 0; //BT656 interlace clock mode
+#endif
+ /* MAX9526 has a dedicated clock so no clock settings needed. */
+
+ return 0;
+}
+
+/*!
+ * Sets the camera power.
+ *
+ * s pointer to the camera device
+ * on if 1, power is to be turned on. 0 means power is to be turned off
+ *
+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
+ * @s: pointer to standard V4L2 device structure
+ * @on: power state to which device is to be set
+ *
+ * Sets devices power state to requrested state, if possible.
+ * This is called on open, close, suspend and resume.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+ struct sensor *sensor = s->priv;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_s_power\n");
+
+ if (on && !sensor->sen.on) {
+ if (max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x10) != 0)
+ return -EIO;
+
+ /*
+ * FIXME:Additional 400ms to wait the chip to be stable?
+ * This is a workaround for preview scrolling issue.
+ * Taken from ADV7180, really needed on MAX9526??
+ */
+ msleep(400);
+
+ } else if (!on && sensor->sen.on) {
+ if (max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18) != 0)
+ return -EIO;
+ }
+
+ sensor->sen.on = on;
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor *sensor = s->priv;
+ struct v4l2_captureparm *cparm = &a->parm.capture;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_g_parm\n");
+
+ switch (a->type) {
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+ memset(a, 0, sizeof(*a));
+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ cparm->capability = sensor->sen.streamcap.capability;
+ cparm->timeperframe = sensor->sen.streamcap.timeperframe;
+ cparm->capturemode = sensor->sen.streamcap.capturemode;
+ break;
+
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ pr_debug("ioctl_g_parm:type is unknown %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible. If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ *
+ * This driver cannot change these settings.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_s_parm\n");
+
+ switch (a->type) {
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ pr_debug(" type is unknown - %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+ struct sensor *sensor = s->priv;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_g_fmt_cap\n");
+ //dump_stack();
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ pr_debug(" Returning size of %dx%d\n",
+ sensor->sen.pix.width, sensor->sen.pix.height);
+ f->fmt.pix = sensor->sen.pix;
+ break;
+
+ case V4L2_BUF_TYPE_PRIVATE: {
+ v4l2_std_id std;
+ max9526_get_std(&std);
+ f->fmt.pix.pixelformat = (u32)std;
+ }
+ break;
+
+ default:
+ f->fmt.pix = sensor->sen.pix;
+ break;
+ }
+
+ return 0;
+}
+
+/*!
+ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control information
+ * from the video_control[] array. Otherwise, returns -EINVAL if the
+ * control is not supported.
+ */
+static int ioctl_queryctrl(struct v4l2_int_device *s,
+ struct v4l2_queryctrl *qc)
+{
+ int i;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_queryctrl\n");
+
+ for (i = 0; i < ARRAY_SIZE(max9526_qctrl); i++)
+ if (qc->id && qc->id == max9526_qctrl[i].id) {
+ memcpy(qc, &(max9526_qctrl[i]),
+ sizeof(*qc));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array. Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int ret = 0;
+ int sat = 0;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_g_ctrl\n");
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ max9526_data.sen.brightness = max9526_read(REG_BRIGHTNESS);
+ vc->value = max9526_data.sen.brightness;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ vc->value = max9526_data.sen.contrast;
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ sat = max9526_read(REG_SATURATION);
+ max9526_data.sen.saturation = sat;
+ vc->value = max9526_data.sen.saturation;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ vc->value = max9526_data.sen.hue;
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ vc->value = max9526_data.sen.red;
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ vc->value = max9526_data.sen.blue;
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ vc->value = max9526_data.sen.ae_mode;
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " Default case\n");
+ vc->value = 0;
+ ret = -EPERM;
+ break;
+ }
+
+ return ret;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array). Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int retval = 0;
+ u8 tmp;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_s_ctrl\n");
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ tmp = vc->value;
+ max9526_write_reg(REG_BRIGHTNESS, tmp);
+ max9526_data.sen.brightness = vc->value;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ tmp = vc->value;
+ max9526_write_reg(REG_SATURATION, tmp);
+ max9526_data.sen.saturation = vc->value;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " Default case\n");
+ retval = -EPERM;
+ break;
+ }
+
+ return retval;
+}
+
+/*!
+ * ioctl_enum_framesizes - V4L2 sensor interface handler for
+ * VIDIOC_ENUM_FRAMESIZES ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
+ *
+ * Return 0 if successful, otherwise -EINVAL.
+ */
+static int ioctl_enum_framesizes(struct v4l2_int_device *s,
+ struct v4l2_frmsizeenum *fsize)
+{
+ if (fsize->index >= 1)
+ return -EINVAL;
+
+ fsize->discrete.width = video_fmts[video_idx].active_width;
+ fsize->discrete.height = video_fmts[video_idx].active_height;
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_chip_ident - V4L2 sensor interface handler for
+ * VIDIOC_DBG_G_CHIP_IDENT ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @id: pointer to int
+ *
+ * Return 0.
+ */
+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
+{
+ ((struct v4l2_dbg_chip_ident *)id)->match.type =
+ V4L2_CHIP_MATCH_I2C_DRIVER;
+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
+ "max9526_decoder");
+ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_AMBIGUOUS;
+
+ return 0;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_init\n");
+ return 0;
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_dev_init\n");
+ return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module.
+ */
+static struct v4l2_int_ioctl_desc max9526_ioctl_desc[] = {
+
+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init},
+
+ /*!
+ * Delinitialise the dev. at slave detach.
+ * The complement of ioctl_dev_init.
+ */
+/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */
+
+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power},
+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm},
+/* {vidioc_int_g_needs_reset_num,
+ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
+/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
+ {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init},
+
+ /*!
+ * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
+ */
+/* {vidioc_int_enum_fmt_cap_num,
+ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */
+
+ /*!
+ * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type.
+ * This ioctl is used to negotiate the image capture size and
+ * pixel format without actually making it take effect.
+ */
+/* {vidioc_int_try_fmt_cap_num,
+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
+
+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap},
+
+ /*!
+ * If the requested format is supported, configures the HW to use that
+ * format, returns error code if format not supported or HW can't be
+ * correctly configured.
+ */
+/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
+
+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm},
+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm},
+ {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl},
+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl},
+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl},
+ {vidioc_int_enum_framesizes_num,
+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
+ {vidioc_int_g_chip_ident_num,
+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident},
+};
+
+static struct v4l2_int_slave max9526_slave = {
+ .ioctls = max9526_ioctl_desc,
+ .num_ioctls = ARRAY_SIZE(max9526_ioctl_desc),
+};
+
+static struct v4l2_int_device max9526_int_device = {
+ .module = THIS_MODULE,
+ .name = "max9526",
+ .type = v4l2_int_type_slave,
+ .u = {
+ .slave = &max9526_slave,
+ },
+};
+
+
+/***********************************************************************
+ * I2C client and driver.
+ ***********************************************************************/
+
+/*! MAX9526 Reset function.
+ *
+ * @return None.
+ */
+static void max9526_hard_reset(void)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "In max9526:max9526_hard_reset\n");
+
+ /* System Reset */
+ max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x04);
+ msleep(10);
+
+ /* Delta to Datasheet poweron state */
+ max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18); /* shutdown */
+ max9526_write_reg(REG_VIDEO_INPUT_SELECT_AND_CLAMP, 0x82); /* autom. input sel. */
+ max9526_write_reg(REG_OUTPUT_TEST_SIGNAL, 0x03); /* select 100% color bars */
+ max9526_write_reg(REG_CLOCK_AND_OUTPUT, 0x04); /* Output HSync/Vsync */
+ max9526_write_reg(REG_MISCELLANEOUS, 0x14); /* Output HSync/Vsync */
+}
+
+/*! MAX9526 I2C attach function.
+ *
+ * @param *adapter struct i2c_adapter *.
+ *
+ * @return Error code indicating success or failure.
+ */
+
+/*!
+ * MAX9526 I2C probe function.
+ * Function set in i2c_driver struct.
+ * Called by insmod.
+ *
+ * @param *adapter I2C adapter descriptor.
+ *
+ * @return Error code indicating success or failure.
+ */
+static int max9526_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret = 0;
+ struct pinctrl *pinctrl;
+ struct device *dev = &client->dev;
+
+ dev_dbg(dev, "%s sensor data is at %p\n", __func__, &max9526_data);
+
+ /* Set initial values for the sensor struct. */
+ memset(&max9526_data, 0, sizeof(max9526_data));
+ max9526_data.sen.i2c_client = client;
+ max9526_data.sen.streamcap.timeperframe.denominator = 30;
+ max9526_data.sen.streamcap.timeperframe.numerator = 1;
+ max9526_data.std_id = V4L2_STD_ALL;
+ video_idx = MAX9526_NOT_LOCKED;
+ max9526_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ max9526_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ max9526_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */
+ max9526_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */
+ max9526_data.sen.on = false;
+
+ max9526_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk");
+ if (IS_ERR(max9526_data.sen.sensor_clk)) {
+ dev_err(dev, "get mclk failed\n");
+ return PTR_ERR(max9526_data.sen.sensor_clk);
+ }
+
+ ret = of_property_read_u32(dev->of_node, "mclk",
+ &max9526_data.sen.mclk);
+ if (ret) {
+ dev_err(dev, "mclk frequency is invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(
+ dev->of_node, "mclk_source",
+ (u32 *) &(max9526_data.sen.mclk_source));
+ if (ret) {
+ dev_err(dev, "mclk_source invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "csi_id",
+ &(max9526_data.sen.csi));
+ if (ret) {
+ dev_err(dev, "csi_id invalid\n");
+ return ret;
+ }
+
+ /* MAX9526 is always parallel IF */
+ max9526_data.sen.mipi_camera = 0;
+
+ clk_prepare_enable(max9526_data.sen.sensor_clk);
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:max9526 probe i2c address is 0x%02X\n",
+ __func__, max9526_data.sen.i2c_client->addr);
+
+ /*! Read a register to test I2C device address */
+ ret = max9526_read(REG_MISCELLANEOUS) & 0xd0;
+ if(ret != 0x10) {
+ /* if the first read fails, that might go undetected */
+ ret = max9526_read(REG_MISCELLANEOUS) & 0xd0;
+ if(ret != 0x10) {
+ dev_err(dev, "Device seems not to be a MAX9526\n");
+ return -ENODEV;
+ }
+ }
+
+ /* MAX9526 pinctrl */
+ pinctrl = devm_pinctrl_get_select_default(dev);
+ if (IS_ERR(pinctrl)) {
+ dev_err(dev, "setup pinctrl failed\n");
+ return PTR_ERR(pinctrl);
+ }
+
+ max9526_regulator_enable(dev);
+
+ max9526_power_down(0);
+
+ msleep(1);
+
+ /*! MAX9526 initialization. */
+ max9526_hard_reset();
+
+ pr_debug(" type is %d (expect %d)\n",
+ max9526_int_device.type, v4l2_int_type_slave);
+ pr_debug(" num ioctls is %d\n",
+ max9526_int_device.u.slave->num_ioctls);
+
+ /* This function attaches this structure to the /dev/video0 device.
+ * The pointer in priv points to the max9526_data structure here.*/
+ max9526_int_device.priv = &max9526_data;
+ ret = v4l2_int_device_register(&max9526_int_device);
+
+ clk_disable_unprepare(max9526_data.sen.sensor_clk);
+
+ return ret;
+}
+
+/*!
+ * MAX9526 I2C detach function.
+ * Called on rmmod.
+ *
+ * @param *client struct i2c_client*.
+ *
+ * @return Error code indicating success or failure.
+ */
+static int max9526_detach(struct i2c_client *client)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:Removing %s video decoder @ 0x%02X from adapter %s\n",
+ __func__, IF_NAME, client->addr << 1, client->adapter->name);
+
+ /* Power down via i2c */
+ max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18);
+
+ if (dvddio_regulator)
+ regulator_disable(dvddio_regulator);
+
+ if (dvdd_regulator)
+ regulator_disable(dvdd_regulator);
+
+ if (avdd_regulator)
+ regulator_disable(avdd_regulator);
+
+ v4l2_int_device_unregister(&max9526_int_device);
+
+ return 0;
+}
+
+/*!
+ * MAX9526 init function.
+ * Called on insmod.
+ *
+ * @return Error code indicating success or failure.
+ */
+static __init int max9526_init(void)
+{
+ u8 err = 0;
+
+ pr_debug("In max9526_init\n");
+
+ /* Tells the i2c driver what functions to call for this driver. */
+ err = i2c_add_driver(&max9526_i2c_driver);
+ if (err != 0)
+ pr_err("%s:driver registration failed, error=%d\n",
+ __func__, err);
+
+ return err;
+}
+
+/*!
+ * MAX9526 cleanup function.
+ * Called on rmmod.
+ *
+ * @return Error code indicating success or failure.
+ */
+static void __exit max9526_clean(void)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526_clean\n");
+ i2c_del_driver(&max9526_i2c_driver);
+}
+
+module_init(max9526_init);
+module_exit(max9526_clean);
+
+MODULE_AUTHOR("max.krummenacher@toradex.com");
+MODULE_DESCRIPTION("Maxim Integrated MAX9526 video decoder driver for i.MX6");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
index 3d7adecaa325..de198ca1e69f 100644
--- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
+++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
@@ -34,8 +34,12 @@
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/mutex.h>
#include <linux/mxcfb.h>
#include <linux/of_device.h>
+#include <linux/regmap.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-device.h>
@@ -44,6 +48,13 @@
#include "mxc_v4l2_capture.h"
#include "ipu_prp_sw.h"
+#if 0
+#undef dev_dbg
+#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);}
+#undef pr_debug
+#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
#define init_MUTEX(sem) sema_init(sem, 1)
static struct platform_device_id imx_v4l2_devtype[] = {
@@ -993,7 +1004,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->bright = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BRIGHTNESS\n");
status = -ENODEV;
}
break;
@@ -1003,7 +1014,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->hue = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n");
status = -ENODEV;
}
break;
@@ -1013,7 +1024,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->contrast = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_CONTRAST\n");
status = -ENODEV;
}
break;
@@ -1023,7 +1034,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->saturation = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_SATURATION\n");
status = -ENODEV;
}
break;
@@ -1033,7 +1044,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->red = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_RED_BALANCE\n");
status = -ENODEV;
}
break;
@@ -1043,7 +1054,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->blue = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLUE_BALANCE\n");
status = -ENODEV;
}
break;
@@ -1053,12 +1064,12 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->ae_mode = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLACK_LEVEL\n");
status = -ENODEV;
}
break;
default:
- pr_err("ERROR: v4l2 capture: unsupported ioctrl!\n");
+ pr_debug("ERROR: v4l2 capture: unsupported ioctrl!\n");
}
return status;
@@ -1163,7 +1174,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->hue = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n");
ret = -ENODEV;
}
break;
@@ -1172,7 +1183,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->contrast = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_CONTRAST\n");
ret = -ENODEV;
}
break;
@@ -1181,7 +1192,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->bright = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BRIGHTNESS\n");
ret = -ENODEV;
}
break;
@@ -1190,7 +1201,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->saturation = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_SATURATION\n");
ret = -ENODEV;
}
break;
@@ -1199,7 +1210,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->red = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_RED_BALANCE\n");
ret = -ENODEV;
}
break;
@@ -1208,7 +1219,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->blue = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLUE_BALANCE\n");
ret = -ENODEV;
}
break;
@@ -1217,7 +1228,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->ae_mode = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_EXPOSURE\n");
ret = -ENODEV;
}
break;
@@ -1347,6 +1358,8 @@ static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
if (ifparm.u.bt656.clock_curr == 0)
csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
+ else if (ifparm.u.bt656.clock_curr == 1)
+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
else
csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
@@ -1555,6 +1568,39 @@ static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
return retval;
}
+static void power_down_callback(struct work_struct *work)
+{
+ cam_data *cam = container_of(work, struct _cam_data, power_down_work.work);
+
+ down(&cam->busy_lock);
+ if (!cam->open_count) {
+ vidioc_int_s_power(cam->sensor, 0);
+ cam->power_on = 0;
+ }
+ up(&cam->busy_lock);
+}
+
+/* cam->busy_lock is held */
+void power_up_camera(cam_data *cam)
+{
+ if (cam->power_on) {
+ cancel_delayed_work(&cam->power_down_work);
+ return;
+ }
+ vidioc_int_s_power(cam->sensor, 1);
+ vidioc_int_init(cam->sensor);
+ vidioc_int_dev_init(cam->sensor);
+ cam->power_on = 1;
+}
+
+
+void power_off_camera(cam_data *cam)
+{
+ schedule_delayed_work(&cam->power_down_work, (HZ * 2));
+}
+
+unsigned long csi_in_use;
+
/*!
* V4L interface - open function
*
@@ -1572,6 +1618,7 @@ static int mxc_v4l_open(struct file *file)
cam_data *cam = video_get_drvdata(dev);
int err = 0;
struct sensor_data *sensor;
+ int csi_bit;
pr_debug("\nIn MVC: mxc_v4l_open\n");
pr_debug(" device name is %s\n", dev->name);
@@ -1584,7 +1631,7 @@ static int mxc_v4l_open(struct file *file)
if (cam->sensor == NULL ||
cam->sensor->type != v4l2_int_type_slave) {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n");
return -EAGAIN;
}
@@ -1596,11 +1643,45 @@ static int mxc_v4l_open(struct file *file)
}
down(&cam->busy_lock);
+
err = 0;
if (signal_pending(current))
goto oops;
if (cam->open_count++ == 0) {
+ struct regmap *gpr;
+
+ csi_bit = (cam->ipu_id << 1) | cam->csi;
+ if (test_and_set_bit(csi_bit, &csi_in_use)) {
+ pr_err("%s: %s CSI already in use\n", __func__, dev->name);
+ err = -EBUSY;
+ cam->open_count = 0;
+ goto oops;
+ }
+ cam->csi_in_use = 1;
+
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ if (cam->ipu_id == cam->csi) {
+ unsigned shift = 19 + cam->csi;
+ unsigned mask = 1 << shift;
+ unsigned val = (cam->mipi_camera ? 0 : 1) << shift;
+
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, val);
+ }
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ unsigned shift = cam->csi * 3;
+ unsigned mask = 7 << shift;
+ unsigned val = (cam->mipi_camera ? csi_bit : 4) << shift;
+
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
wait_event_interruptible(cam->power_queue,
cam->low_power == false);
@@ -1698,9 +1779,7 @@ static int mxc_v4l_open(struct file *file)
cam_fmt.fmt.pix.pixelformat,
csi_param);
clk_prepare_enable(sensor->sensor_clk);
- vidioc_int_s_power(cam->sensor, 1);
- vidioc_int_init(cam->sensor);
- vidioc_int_dev_init(cam->sensor);
+ power_up_camera(cam);
}
file->private_data = dev;
@@ -1757,7 +1836,6 @@ static int mxc_v4l_close(struct file *file)
}
if (--cam->open_count == 0) {
- vidioc_int_s_power(cam->sensor, 0);
clk_disable_unprepare(sensor->sensor_clk);
wait_event_interruptible(cam->power_queue,
cam->low_power == false);
@@ -1782,6 +1860,14 @@ static int mxc_v4l_close(struct file *file)
wake_up_interruptible(&cam->enc_queue);
mxc_free_frames(cam);
cam->enc_counter++;
+ power_off_camera(cam);
+
+ if (cam->csi_in_use) {
+ int csi_bit = (cam->ipu_id << 1) | cam->csi;
+
+ clear_bit(csi_bit, &csi_in_use);
+ cam->csi_in_use = 0;
+ }
}
up(&cam->busy_lock);
@@ -2228,7 +2314,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_g_parm(cam->sensor, parm);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_G_PARM\n");
retval = -ENODEV;
}
break;
@@ -2240,7 +2326,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = mxc_v4l2_s_param(cam, parm);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_S_PARM\n");
retval = -ENODEV;
}
break;
@@ -2250,6 +2336,10 @@ static long mxc_v4l_do_ioctl(struct file *file,
case VIDIOC_ENUMSTD: {
struct v4l2_standard *e = arg;
pr_debug(" case VIDIOC_ENUMSTD\n");
+ if (e->index > 0) {
+ retval = -EINVAL;
+ break;
+ }
*e = cam->standard;
break;
}
@@ -2260,7 +2350,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = mxc_v4l2_g_std(cam, e);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_G_STD\n");
retval = -ENODEV;
}
break;
@@ -2365,7 +2455,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_enum_fmt_cap(cam->sensor, f);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FMT\n");
retval = -ENODEV;
}
break;
@@ -2375,7 +2465,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_enum_framesizes(cam->sensor, fsize);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FRAMESIZES\n");
retval = -ENODEV;
}
break;
@@ -2386,7 +2476,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
retval = vidioc_int_enum_frameintervals(cam->sensor,
fival);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FRAMEINTERVALS\n");
retval = -ENODEV;
}
break;
@@ -2398,7 +2488,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_DBG_G_CHIP_IDENT\n");
retval = -ENODEV;
}
break;
@@ -2624,9 +2714,10 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
const struct of_device_id *of_id =
of_match_device(mxc_v4l2_dt_ids, &pdev->dev);
struct device_node *np = pdev->dev.of_node;
- int ipu_id, csi_id, mclk_source;
+ int ipu_id, csi_id, mclk_source, mipi_camera;
int ret = 0;
struct v4l2_device *v4l2_dev;
+ static int camera_id;
pr_debug("In MVC: init_camera_struct\n");
@@ -2648,6 +2739,10 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
return ret;
}
+ ret = of_property_read_u32(np, "mipi_camera", &mipi_camera);
+ if (ret)
+ mipi_camera = 0;
+
/* Default everything to 0 */
memset(cam, 0, sizeof(cam_data));
@@ -2670,6 +2765,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
init_MUTEX(&cam->param_lock);
init_MUTEX(&cam->busy_lock);
+ INIT_DELAYED_WORK(&cam->power_down_work, power_down_callback);
cam->video_dev = video_device_alloc();
if (cam->video_dev == NULL)
@@ -2736,6 +2832,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
cam->ipu_id = ipu_id;
cam->csi = csi_id;
+ cam->mipi_camera = mipi_camera;
cam->mclk_source = mclk_source;
cam->mclk_on[cam->mclk_source] = false;
@@ -2746,7 +2843,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL);
cam->self->module = THIS_MODULE;
- sprintf(cam->self->name, "mxc_v4l2_cap%d", cam->csi);
+ sprintf(cam->self->name, "mxc_v4l2_cap%d", camera_id++);
cam->self->type = v4l2_int_type_master;
cam->self->u.master = &mxc_v4l2_master;
@@ -2957,7 +3054,8 @@ static int mxc_v4l2_resume(struct platform_device *pdev)
wake_up_interruptible(&cam->power_queue);
if (cam->sensor && cam->open_count) {
- vidioc_int_s_power(cam->sensor, 1);
+ if ((cam->overlay_on == true) || (cam->capture_on == true))
+ vidioc_int_s_power(cam->sensor, 1);
if (!cam->mclk_on[cam->mclk_source]) {
ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
@@ -3018,8 +3116,9 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
return -1;
}
- if (sdata->csi != cam->csi) {
- pr_debug("%s: csi doesn't match\n", __func__);
+ if ((sdata->ipu_id != cam->ipu_id) || (sdata->csi != cam->csi) || (sdata->mipi_camera != cam->mipi_camera)) {
+ pr_info("%s: ipu(%d:%d)/csi(%d:%d)/mipi(%d:%d) doesn't match\n", __func__,
+ sdata->ipu_id, cam->ipu_id, sdata->csi, cam->csi, sdata->mipi_camera, cam->mipi_camera);
return -1;
}
@@ -3073,6 +3172,10 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
__func__,
cam->crop_current.width, cam->crop_current.height);
+ pr_info("%s: ipu%d:/csi%d %s attached %s:%s\n", __func__,
+ cam->ipu_id, cam->csi, cam->mipi_camera ? "mipi" : "parallel",
+ slave->name, slave->u.slave->master->name);
+
return 0;
}
@@ -3106,6 +3209,20 @@ static void mxc_v4l2_master_detach(struct v4l2_int_device *slave)
vidioc_int_dev_exit(slave);
}
+DEFINE_MUTEX(camera_common_mutex);
+
+void mxc_camera_common_lock(void)
+{
+ mutex_lock(&camera_common_mutex);
+}
+EXPORT_SYMBOL(mxc_camera_common_lock);
+
+void mxc_camera_common_unlock(void)
+{
+ mutex_unlock(&camera_common_mutex);
+}
+EXPORT_SYMBOL(mxc_camera_common_unlock);
+
/*!
* Entry point for the V4L2
*
diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
index f6717752d4b9..bfded3a3e9f9 100644
--- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
+++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
@@ -114,6 +114,8 @@ typedef struct _cam_data {
struct semaphore busy_lock;
int open_count;
+ struct delayed_work power_down_work;
+ int power_on;
/* params lock for this camera */
struct semaphore param_lock;
@@ -207,6 +209,8 @@ typedef struct _cam_data {
wait_queue_head_t power_queue;
unsigned int ipu_id;
unsigned int csi;
+ unsigned mipi_camera;
+ int csi_in_use;
u8 mclk_source;
bool mclk_on[2]; /* two mclk sources at most now */
int current_input;
@@ -253,10 +257,15 @@ struct sensor_data {
u32 mclk;
u8 mclk_source;
struct clk *sensor_clk;
+ int ipu_id;
int csi;
+ int mipi_camera; /* 0: parallel camera hw if, != 0: mipi csi hw if */
void (*io_init)(void);
};
void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi);
+void mxc_camera_common_lock(void);
+void mxc_camera_common_unlock(void);
+
#endif /* __MXC_V4L2_CAPTURE_H__ */
diff --git a/drivers/media/platform/mxc/capture/ov5640_mipi.c b/drivers/media/platform/mxc/capture/ov5640_mipi.c
index 0d146b534f61..8d600afc063b 100644
--- a/drivers/media/platform/mxc/capture/ov5640_mipi.c
+++ b/drivers/media/platform/mxc/capture/ov5640_mipi.c
@@ -27,8 +27,12 @@
#include <linux/clk.h>
#include <linux/of_device.h>
#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/fsl_devices.h>
#include <linux/mipi_csi2.h>
@@ -685,12 +689,40 @@ static void ov5640_standby(s32 enable)
gpio_set_value(pwn_gpio, 1);
else
gpio_set_value(pwn_gpio, 0);
-
+ pr_debug("ov5640_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio);
msleep(100);
}
+static s32 update_device_addr(struct sensor_data *sensor)
+{
+ int ret;
+ u8 buf[4];
+ unsigned reg = 0x3100;
+ unsigned default_addr = 0x3c;
+ struct i2c_msg msg;
+
+ if (sensor->i2c_client->addr == default_addr)
+ return 0;
+
+ buf[0] = reg >> 8;
+ buf[1] = reg & 0xff;
+ buf[2] = sensor->i2c_client->addr << 1;
+ msg.addr = default_addr;
+ msg.flags = 0;
+ msg.len = 3;
+ msg.buf = buf;
+
+
+ ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1);
+ if (ret < 0)
+ pr_err("%s: ov5642 ret=%d\n", __func__, ret);
+ return ret;
+}
+
static void ov5640_reset(void)
{
+ mxc_camera_common_lock();
+
/* camera reset */
gpio_set_value(rst_gpio, 1);
@@ -705,7 +737,9 @@ static void ov5640_reset(void)
msleep(1);
gpio_set_value(rst_gpio, 1);
- msleep(5);
+ msleep(20);
+ update_device_addr(&ov5640_data);
+ mxc_camera_common_unlock();
gpio_set_value(pwn_gpio, 1);
}
@@ -774,18 +808,33 @@ static int ov5640_power_on(struct device *dev)
static s32 ov5640_write_reg(u16 reg, u8 val)
{
+ int ret;
u8 au8Buf[3] = {0};
au8Buf[0] = reg >> 8;
au8Buf[1] = reg & 0xff;
au8Buf[2] = val;
- if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
- pr_err("%s:write reg error:reg=%x,val=%x\n",
- __func__, reg, val);
- return -1;
+#if 0 /* Software reset does not affect the i2c address register like it does on ov5642 */
+ if ((reg == 0x3008) && (val & 0x80)) {
+ mxc_camera_common_lock();
+
+ ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3);
+ update_device_addr(&ov5640_data);
+
+ mxc_camera_common_unlock();
+ } else
+#endif
+ {
+ ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3);
}
+ if (ret < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x ret=%d\n",
+ __func__, reg, val, ret);
+ return ret;
+ }
+ pr_debug("reg=%x,val=%x\n", reg, val);
return 0;
}
@@ -827,43 +876,64 @@ static void OV5640_stream_off(void)
ov5640_write_reg(0x4202, 0x0f);
}
-
+static const int sclk_rdiv_map[] = {1, 2, 4, 8};
+
static int OV5640_get_sysclk(void)
{
/* calculate sysclk */
- int xvclk = ov5640_data.mclk / 10000;
- int temp1, temp2;
- int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv;
- int Bit_div2x = 1, sclk_rdiv, sysclk;
+ int tmp;
+ unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1;
+ unsigned div, sclk_rdiv, sysclk;
u8 temp;
int sclk_rdiv_map[] = {1, 2, 4, 8};
- temp1 = ov5640_read_reg(0x3034, &temp);
- temp2 = temp1 & 0x0f;
- if (temp2 == 8 || temp2 == 10)
- Bit_div2x = temp2 / 2;
-
- temp1 = ov5640_read_reg(0x3035, &temp);
- SysDiv = temp1>>4;
- if (SysDiv == 0)
+ tmp = ov5640_read_reg(0x3034, &temp);
+ if (tmp < 0)
+ return tmp;
+ tmp &= 0x0f;
+ if (tmp == 8 || tmp == 10)
+ Bit_div2x = tmp / 2;
+
+ tmp = ov5640_read_reg(0x3035, &temp);
+ if (tmp < 0)
+ return tmp;
+ SysDiv = tmp >> 4;
+ if (SysDiv == 0)
SysDiv = 16;
- temp1 = ov5640_read_reg(0x3036, &temp);
- Multiplier = temp1;
-
- temp1 = ov5640_read_reg(0x3037, &temp);
- PreDiv = temp1 & 0x0f;
- Pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
-
- temp1 = ov5640_read_reg(0x3108, &temp);
- temp2 = temp1 & 0x03;
- sclk_rdiv = sclk_rdiv_map[temp2];
-
- VCO = xvclk * Multiplier / PreDiv;
-
- sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv;
-
+ tmp = ov5640_read_reg(0x3036, &temp);
+ if (tmp < 0)
+ return tmp;
+ Multiplier = tmp;
+
+ tmp = ov5640_read_reg(0x3037, &temp);
+ if (tmp < 0)
+ return tmp;
+ PreDiv = tmp & 0x0f;
+ Pll_rdiv = ((tmp >> 4) & 0x01) + 1;
+
+ tmp = ov5640_read_reg(0x3108, &temp);
+ if (tmp < 0)
+ return tmp;
+ sclk_rdiv = sclk_rdiv_map[tmp & 0x03];
+
+ sysclk = ov5640_data.mclk / 10000 * Multiplier;
+ div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv;
+ if (!div) {
+ pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n",
+ __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
+ return -EINVAL;
+ }
+ if (!sysclk) {
+ pr_err("%s:Error 0 clk, ov5640_data.mclk=%d, Multiplier=%d\n",
+ __func__, ov5640_data.mclk, Multiplier);
+ return -EINVAL;
+ }
+ sysclk /= div;
+ pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n",
+ __func__, sysclk, ov5640_data.mclk, Multiplier,
+ PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
return sysclk;
}
@@ -1004,6 +1074,7 @@ static int OV5640_get_light_freq(void)
light_freq = 50;
} else {
/* 60Hz */
+ light_freq = 60;
}
}
return light_freq;
@@ -1096,6 +1167,7 @@ static void ov5640_set_virtual_channel(int channel)
ov5640_read_reg(0x4814, &channel_id);
channel_id &= ~(3 << 6);
ov5640_write_reg(0x4814, channel_id | (channel << 6));
+ pr_info("%s: virtual channel=%d\n", __func__, channel);
}
/* download ov5640 settings to sensor through i2c */
@@ -1387,7 +1459,7 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate,
OV5640_set_AE_target(AE_Target);
OV5640_get_light_freq();
OV5640_set_bandingfilter();
- ov5640_set_virtual_channel(ov5640_data.csi);
+ ov5640_set_virtual_channel(ov5640_data.csi | (ov5640_data.ipu_id << 1));
/* add delay to wait for sensor stable */
if (mode == ov5640_mode_QSXGA_2592_1944) {
@@ -1404,37 +1476,33 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate,
msleep(msec_wait4stable);
if (mipi_csi2_info) {
- unsigned int i;
-
- i = 0;
+ unsigned int i = 0;
/* wait for mipi sensor ready */
- mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
- while ((mipi_reg == 0x200) && (i < 10)) {
+ while (1) {
mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
- i++;
+ if (mipi_reg != 0x200)
+ break;
+ if (i++ >= 20) {
+ pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg);
+ return -1;
+ }
msleep(10);
}
- if (i >= 10) {
- pr_err("mipi csi2 can not receive sensor clk!\n");
- return -1;
- }
-
i = 0;
-
/* wait for mipi stable */
- mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
- while ((mipi_reg != 0x0) && (i < 10)) {
+ while (1) {
mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
- i++;
+ if (!mipi_reg)
+ break;
+ if (i++ >= 20) {
+ pr_err("mipi csi2 can not receive data correctly!\n");
+ return -1;
+ }
msleep(10);
}
- if (i >= 10) {
- pr_err("mipi csi2 can not reveive data correctly!\n");
- return -1;
- }
}
err:
return retval;
@@ -1962,7 +2030,7 @@ static struct v4l2_int_slave ov5640_slave = {
static struct v4l2_int_device ov5640_int_device = {
.module = THIS_MODULE,
- .name = "ov564x",
+ .name = "ov564x_mipi",
.type = v4l2_int_type_slave,
.u = {
.slave = &ov5640_slave,
@@ -1978,9 +2046,12 @@ static struct v4l2_int_device ov5640_int_device = {
static int ov5640_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
+ struct pwm_device *pwm;
struct device *dev = &client->dev;
int retval;
u8 chip_id_high, chip_id_low;
+ struct regmap *gpr;
+ struct sensor_data *sensor = &ov5640_data;
/* request power down pin */
pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
@@ -1990,8 +2061,10 @@ static int ov5640_probe(struct i2c_client *client,
}
retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
"ov5640_mipi_pwdn");
- if (retval < 0)
+ if (retval < 0) {
+ dev_warn(dev, "request of pwn_gpio failed");
return retval;
+ }
/* request reset pin */
rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
@@ -2001,8 +2074,10 @@ static int ov5640_probe(struct i2c_client *client,
}
retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
"ov5640_mipi_reset");
- if (retval < 0)
+ if (retval < 0) {
+ dev_warn(dev, "request of ov5640_mipi_reset failed");
return retval;
+ }
/* Set initial values for the sensor struct. */
memset(&ov5640_data, 0, sizeof(ov5640_data));
@@ -2028,6 +2103,13 @@ static int ov5640_probe(struct i2c_client *client,
return retval;
}
+ retval = of_property_read_u32(dev->of_node, "ipu_id",
+ &sensor->ipu_id);
+ if (retval) {
+ dev_err(dev, "ipu_id missing or invalid\n");
+ return retval;
+ }
+
retval = of_property_read_u32(dev->of_node, "csi_id",
&(ov5640_data.csi));
if (retval) {
@@ -2048,6 +2130,13 @@ static int ov5640_probe(struct i2c_client *client,
ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
ov5640_data.streamcap.timeperframe.numerator = 1;
+ pwm = pwm_get(dev, NULL);
+ if (!IS_ERR(pwm)) {
+ dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->state.period);
+ pwm_config(pwm, pwm->state.period >> 1, pwm->state.period);
+ pwm_enable(pwm);
+ }
+
ov5640_power_on(dev);
ov5640_reset();
@@ -2067,12 +2156,31 @@ static int ov5640_probe(struct i2c_client *client,
return -ENODEV;
}
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ if (sensor->csi == sensor->ipu_id) {
+ int mask = sensor->csi ? (1 << 20) : (1 << 19);
+
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0);
+ }
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ int mask = sensor->csi ? (7 << 3) : (7 << 0);
+ int val = sensor->csi ? (3 << 3) : (0 << 0);
+
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
ov5640_standby(1);
ov5640_int_device.priv = &ov5640_data;
retval = v4l2_int_device_register(&ov5640_int_device);
- clk_disable_unprepare(ov5640_data.sensor_clk);
+// clk_disable_unprepare(ov5640_data.sensor_clk);
pr_info("camera ov5640_mipi is found\n");
return retval;
diff --git a/drivers/media/platform/mxc/capture/ov5640_mipi_nv.c b/drivers/media/platform/mxc/capture/ov5640_mipi_nv.c
new file mode 100644
index 000000000000..c10b6091208a
--- /dev/null
+++ b/drivers/media/platform/mxc/capture/ov5640_mipi_nv.c
@@ -0,0 +1,1509 @@
+/*
+ * Copyright (c) 2012-2013 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <media/v4l2-chip-ident.h>
+#include <media/v4l2-mediabus.h>
+#include <media/soc_camera.h>
+#include <linux/of_gpio.h>
+
+struct ov5640_reg {
+ u16 addr;
+ u16 val;
+};
+
+#define MIPI_CSI2_SENS_VC0_PAD_SOURCE 0
+#define MIPI_CSI2_SENS_VC1_PAD_SOURCE 1
+#define MIPI_CSI2_SENS_VC2_PAD_SOURCE 2
+#define MIPI_CSI2_SENS_VC3_PAD_SOURCE 3
+#define MIPI_CSI2_SENS_VCX_PADS_NUM 4
+
+#define OV5640_TABLE_WAIT_MS 0
+#define OV5640_TABLE_END 1
+
+/* -> mode_2592x1944 mode_1920x1080 mode_1280x960 mode_640x480 */
+
+/* System and IO Pad Control [0x3000 ~ 0x3052] */
+#define OV5640_SYSTEM_RESET_00 0x3000 /* default 0x30 -> all 0x00 */
+#define OV5640_SYSTEM_RESET_01 0x3001 /* default 0x08 */
+#define OV5640_SYSTEM_RESET_02 0x3002 /* default 0x1c */
+#define OV5640_SYSTEM_RESET_03 0x3003 /* default 0x00 */
+#define OV5640_SYSTEM_CLK_EN_00 0x3004 /* default 0xcf -> all 0xff */
+#define OV5640_SYSTEM_CLK_EN_01 0x3005 /* default 0xf7 */
+#define OV5640_SYSTEM_CLK_EN_02 0x3006 /* default 0xe3 -> all 0xc3 */
+#define OV5640_SYSTEM_CLK_EN_03 0x3007 /* default 0xff */
+#define OV5640_SYSTEM_CTRL 0x3008 /* default 0x02 all -> (0x82, 0x42, 0x02) */
+#define OV5640_CHIP_ID_H 0x300a /* default 0x56 */
+#define OV5640_CHIP_ID_L 0x300b /* default 0x40 */
+#define OV5640_SYSTEM_MIPI_CTRL 0x300e /* default 0x58 -> all 0x45 */
+#define OV5640_IO_CTRL_01 0x3017 /* default 0x00 */
+#define OV5640_IO_CTRL_02 0x3018 /* default 0x00 */
+#define OV5640_SYSTEM_CTRL_2D 0x302d /* default ---- -> all 0x60 !! */
+#define OV5640_SYSTEM_CTRL_2E 0x302e /* default ---- -> all 0x08 !! */
+#define OV5640_SC_PLL_CTRL0 0x3034 /* default 0x1a -> all 0x18 MIPI_MODE */
+#define OV5640_SC_PLL_CTRL1 0x3035 /* default 0x11 -> 0x11 0x11 0x21 0x14 */
+#define OV5640_SC_PLL_CTRL2 0x3036 /* default 0x69 -> 0x7d 0x54 0x70 0x70 */
+#define OV5640_SC_PLL_CTRL3 0x3037 /* default 0x03 -> all 0x13 */
+#define OV5640_SC_PLL_CTRL5 0x3039 /* not use */
+
+#define SYSTEM_CTRL_SRST 0x80 /* Bit[7]: Software reset */
+#define SYSTEM_CTRL_PDOWN 0x40 /* Bit[6]: Software power down */
+#define MIPI_MODE_8BIT 0x08 /* Bit[3:0]: MIPI bit mode - 8-bit mode */
+#define MIPI_MODE_10BIT 0x0a /* Bit[3:0]: MIPI bit mode - 10-bit mode */
+
+/* SCCB Control [0x3100 ~ 0x3108] */
+#define OV5640_SCCB_SYSTEM_CTRL 0x3103 /* default 0x00 -> all 0x03 */
+#define OV5640_SCCB_SCLK 0x3108 /* default 0x16 -> all 0x01 */
+
+/* VCM Control [0x3600 ~ 0x3606] */
+#define OV5640_VCM_DEBUG_MODE_0 0x3600 /* default ---- -> all 0x08 */
+#define OV5640_VCM_DEBUG_MODE_1 0x3601 /* default ---- -> all 0x33 */
+
+/* Timing Control [0x3800 ~ 0x3821] */
+#define OV5640_TIMING_HS_H 0x3800 /* default 0x00 -> 0x00 0x01 0x00 0x00 X_ADDR_ST */
+#define OV5640_TIMING_HS_L 0x3801 /* default 0x00 -> 0x00 0x50 0x00 0x00 */
+#define OV5640_TIMING_VS_H 0x3802 /* default 0x00 -> 0x00 0x01 0x00 0x00 Y_ADDR_ST */
+#define OV5640_TIMING_VS_L 0x3803 /* default 0x00 -> 0x00 0xaa 0x00 0x04 */
+#define OV5640_TIMING_HW_H 0x3804 /* default 0x0a -> 0x0a 0x08 0x0a 0x0a X_ADDR_END */
+#define OV5640_TIMING_HW_L 0x3805 /* default 0x3f -> 0x3f 0xef 0x3f 0x3f 2623 */
+#define OV5640_TIMING_VH_H 0x3806 /* default 0x07 -> 0x07 0x05 0x07 0x07 Y_ADDR_END */
+#define OV5640_TIMING_VH_L 0x3807 /* default 0x9f -> 0x9f 0xf9 0x9f 0x9b */
+#define OV5640_TIMING_DVPHO_H 0x3808 /* default 0x0a -> 0x0a 0x07 0x05 0x02 width[11:8] */
+#define OV5640_TIMING_DVPHO_L 0x3809 /* default 0x20 -> 0x30 0x90 0x18 0x80 width[7:0] */
+#define OV5640_TIMING_DVPVO_H 0x380a /* default 0x07 -> 0x07 0x04 0x03 0x01 height[11:8] */
+#define OV5640_TIMING_DVPVO_L 0x380b /* default 0x98 -> 0x9c 0x48 0xcc 0xe0 height[7:0] */
+#define OV5640_TIMING_HTS_H 0x380c /* default 0x0b -> 0x0b 0x09 0x07 0x07 */
+#define OV5640_TIMING_HTS_L 0x380d /* default 0x1c -> 0x1c 0xc4 0x5e 0x68 */
+#define OV5640_TIMING_VTS_H 0x380e /* default 0x07 -> 0x07 0x04 0x03 0x03 */
+#define OV5640_TIMING_VTS_L 0x380f /* default 0xb0 -> 0xb0 0x60 0xde 0xd8 */
+#define OV5640_TIMING_HOFFSET_H 0x3810 /* default 0x00 */
+#define OV5640_TIMING_HOFFSET_L 0x3811 /* default 0x10 -> 0x08 0x08 0x06 0x10 */
+#define OV5640_TIMING_VOFFSET_H 0x3812 /* default 0x00 */
+#define OV5640_TIMING_VOFFSET_L 0x3813 /* default 0x04 -> 0x02 0x04 0x02 0x06 */
+#define OV5640_TIMING_X_INC 0x3814 /* default 0x11 -> 0x11 0x11 0x31 0x31 */
+#define OV5640_TIMING_Y_INC 0x3815 /* default 0x11 -> 0x11 0x11 0x31 0x31 */
+#define OV5640_TIMING_REG20 0x3820 /* default 0x40 -> 0x40 0x40 0x41 0x41 sensor vflip */
+#define OV5640_TIMING_REG21 0x3821 /* default 0x00 -> 0x06 0x06 0x07 0x07 */
+#define REG20_SENSOR_VFLIP 0x02
+#define REG20_SENSOR_ISP_FLIP 0x04
+#define REG21_BINNING_EN 0x01
+#define REG21_SENSOR_MIRROR 0x02
+#define REG21_ISP_MIRROR 0x04
+
+#define OV5640_ADDR_H(x) ((x >> 8 ) & 0x0f)
+#define OV5640_ADDR_L(x) (x & 0xff)
+#define OV5640_WIDTH_H(x) ((x >> 8 ) & 0x0f)
+#define OV5640_WIDTH_L(x) (x & 0xff)
+#define OV5640_HEIGHT_H(x) ((x >> 8 ) & 0x0f)
+#define OV5640_HEIGHT_L(x) (x & 0xff)
+#define OV5640_HTS_H(x) ((x >> 8 ) & 0x1f)
+#define OV5640_HTS_L(x) (x & 0xff)
+#define OV5640_VTS_H(x) ((x >> 8 ) & 0xff)
+#define OV5640_VTS_L(x) (x & 0xff)
+#define OV5640_H_OFFSET_H(x) ((x >> 8 ) & 0x0F)
+#define OV5640_H_OFFSET_L(x) (x & 0xff)
+#define OV5640_V_OFFSET_H(x) ((x >> 8 ) & 0x03)
+#define OV5640_V_OFFSET_L(x) (x & 0xff)
+
+/* AEC/AGC power down domain control [0x3A00 ~ 0x3A25] */
+#define OV5640_AEC_CTRL_0F 0x3a0f /* default 0x78 -> all 0x30 */
+#define OV5640_AEC_CTRL_10 0x3a10 /* default 0x68 -> all 0x28 */
+#define OV5640_AEC_CTRL_11 0x3a11 /* default 0xd0 -> all 0x60 */
+#define OV5640_AEC_CTRL_1B 0x3a1b /* default 0x78 -> all 0x30 */
+#define OV5640_AEC_CTRL_1E 0x3a1e /* default 0x68 -> all 0x26 */
+#define OV5640_AEC_CTRL_1F 0x3a1f /* default 0x40 -> all 0x14 */
+#define OV5640_AEC_MAX_EXPO60_H 0x3a02 /* default 0x3d -> 0x07 0x04 0x03 0x03 */
+#define OV5640_AEC_MAX_EXPO60_L 0x3a03 /* default 0x80 -> 0xb6 0x60 0xd8 0xd8 */
+#define OV5640_AEC_B50_STEP_H 0x3a08 /* default 0x01 */
+#define OV5640_AEC_B50_STEP_L 0x3a09 /* default 0x27 -> 0x27 0x50 0x27 0x27 */
+#define OV5640_AEC_B60_STEP_H 0x3a0a /* default 0x00 -> 0x00 0x01 0x00 0x00 */
+#define OV5640_AEC_B60_STEP_L 0x3a0b /* default 0xf6 -> 0xf6 0x18 0xf6 0xf6 */
+#define OV5640_AEC_CTRL_0D 0x3a0d /* default 0x08 -> 0x06 0x03 0x03 0x03 */
+#define OV5640_AEC_CTRL_0E 0x3a0e /* default 0x06 -> 0x06 0x04 0x04 0x04 */
+#define OV5640_AEC_CTRL_13 0x3a13 /* default 0x40 -> all 0x43 */
+#define OV5640_AEC_MAX_EXPO_H 0x3a14 /* default 0x0e -> 0x07 0x04 0x03 0x03 */
+#define OV5640_AEC_MAX_EXPO_L 0x3a15 /* default 0x40 -> 0xb0 0xd0 0xd8 0xd8 */
+#define OV5640_AEC_GAIN_CEILING_0 0x3a18 /* default 0x03 -> all 0x00 */
+#define OV5640_AEC_GAIN_CEILING_1 0x3a19 /* default 0xE0 -> all 0xf8 */
+
+/* 50/60Hz detector control [0x3C00 ~ 0x3C1E] */
+#define OV5640_5060_CTRL_01 0x3c01 /* default 0x00 -> all 0x34 */
+#define OV5640_5060_CTRL_04 0x3c04 /* default 0x20 -> all 0x28 */
+#define OV5640_5060_CTRL_05 0x3c05 /* default 0x70 -> all 0x98 */
+
+#define OV5640_5060_THRESHOLD_1_H 0x3c06 /* default 0x00 -> all 0x00 */
+#define OV5640_5060_THRESHOLD_1_L 0x3c07 /* default 0x00 -> all 0x07 0x07 0x07 0x07 0x08 */
+#define OV5640_5060_THRESHOLD_2_H 0x3c08 /* default 0x01 -> all 0x00 */
+#define OV5640_5060_THRESHOLD_2_L 0x3c09 /* default 0x2c -> all 0x1c */
+#define OV5640_5060_SAMPLE_NUM_H 0x3c0a /* default 0x4e -> all 0x9c */
+#define OV5640_5060_SAMPLE_NUM_L 0x3c0b /* default 0x1f -> all 0x40 */
+
+/* BLC Control [0x4000 ~ 0x4033] */
+#define OV5640_BLC_CTRL_01 0x4001 /* default 0x00 -> 0x02 */
+#define OV5640_BLC_CTRL_04 0x4004 /* default 0x08 -> 0x06 0x06 0x02 0x02 */
+
+/* MIPI control [0x4800 ~ 0x4837] */
+#define OV5640_MIPI_CTRL_00 0x4800 /* default 0x04 */
+#define OV5640_MIPI_CTRL_01 0x4801 /* not use */
+#define OV5640_MIPI_CTRL_05 0x4805 /* not use */
+#define OV5640_MIPI_PCLK_PERIOD 0x4837 /* default 0x10 -> 0x0a 0x0a 0x10 0x44 */
+
+/* Format Control [0x4300 ~ 0x430D] */
+#define FMT_CTRL_00 0x4300 /* default 0xF8 -> all 0x32 */
+
+/* Format Control */
+#define FMT_YUV422 0x30
+/* Output sequence */
+#define OFMT_YUYV 0x00
+#define OFMT_YVYU 0x01
+#define OFMT_UYVY 0x02
+#define OFMT_VYUY 0x03
+
+/* ISP Control [0x5000 ~ 0x5063] */
+#define OV5640_ISP_CTRL_00 0x5000 /* default 0x06 -> all 0xa7 */
+#define OV5640_ISP_CTRL_01 0x5001 /* default 0x01 -> 0x83 0x83 0x83 0xa3 */
+#define OV5640_ISP_MUX_CTRL 0x501F /* default 0x00 -> all 0x00 (000: ISP YUV422) */
+#define OV5640_ISP_DEBUG_25 0x5025 /* default ---- -> all 0x00 */
+#define OV5640_ISP_TEST 0x503D /* default 0x00 */
+#define OV5640_ISP_DEBUG_3E 0x503E /* default ---- */
+#define OV5640_ISP_DEBUG_46 0x5046 /* default ---- */
+
+#define ISP_SCALE_DIGITAL 0x80 /* Special digital effect */
+#define ISP_SCALE_EN 0x20 /* Scale enable */
+#define ISP_AUTO_BALANCE_EN 0x01 /* Auto white balance enable */
+#define ISP_COLOR_MATRIX_EN 0x02 /* Color matrix enable */
+#define ISP_TEST_EN 0x80
+#define ISP_TEST_00 0x00 /* 00: Standard eight color bar */
+#define ISP_TEST_01 0x01 /* 01: Gradual change at vertical mode 1 */
+#define ISP_TEST_10 0x02 /* 10: Gradual change at horizontal */
+#define ISP_TEST_11 0x03 /* 11: Gradual change at vertical mode 2 */
+#define ISP_TEST_TRANSPARENT 0x20 /* Transparent */
+#define ISP_TEST_ROLLING 0x40 /* Rolling */
+
+/* AWB Control [0x5180 ~ 0x51D0] */
+#define OV5640_AWB_CTRL_00 0x5180 /* default 0xff */
+#define OV5640_AWB_CTRL_01 0x5181 /* default 0x58 -> all 0xf2 */
+#define OV5640_AWB_CTRL_02 0x5182 /* default 0x11 -> all 0x00 */
+#define OV5640_AWB_CTRL_03 0x5183 /* default 0x90 -> all 0x14 */
+#define OV5640_AWB_CTRL_04 0x5184 /* default 0x25 */
+#define OV5640_AWB_CTRL_05 0x5185 /* default 0x24 */
+#define OV5640_AWB_CTRL_06 0x5186 /* default ---- -> all 0x09 */
+#define OV5640_AWB_CTRL_07 0x5187 /* default ---- -> all 0x09 */
+#define OV5640_AWB_CTRL_08 0x5188 /* default ---- -> all 0x09 */
+#define OV5640_AWB_CTRL_09 0x5189 /* default ---- -> all 0x75 */
+#define OV5640_AWB_CTRL_10 0x518a /* default ---- -> all 0x54 */
+#define OV5640_AWB_CTRL_11 0x518b /* default ---- -> all 0xe0 */
+#define OV5640_AWB_CTRL_12 0x518c /* default ---- -> all 0xb2 */
+#define OV5640_AWB_CTRL_13 0x518d /* default ---- -> all 0x42 */
+#define OV5640_AWB_CTRL_14 0x518e /* default ---- -> all 0x3d */
+#define OV5640_AWB_CTRL_15 0x518f /* default ---- -> all 0x56 */
+#define OV5640_AWB_CTRL_16 0x5190 /* default ---- -> all 0x46 */
+#define OV5640_AWB_CTRL_17 0x5191 /* default 0xff -> all 0xf8 */
+#define OV5640_AWB_CTRL_18 0x5192 /* default 0x00 -> all 0x04 */
+#define OV5640_AWB_CTRL_19 0x5193 /* default 0xf0 -> all 0x70 */
+#define OV5640_AWB_CTRL_20 0x5194 /* default 0xf0 */
+#define OV5640_AWB_CTRL_21 0x5195 /* default 0xf0 */
+#define OV5640_AWB_CTRL_22 0x5196 /* default 0x03 */
+#define OV5640_AWB_CTRL_23 0x5197 /* default 0x02 -> all 0x01 */
+#define OV5640_AWB_CTRL_24 0x5198 /* default ---- -> all 0x04 */
+#define OV5640_AWB_CTRL_25 0x5199 /* default ---- -> all 0x12 */
+#define OV5640_AWB_CTRL_26 0x519a /* default ---- -> all 0x04 */
+#define OV5640_AWB_CTRL_27 0x519b /* default ---- -> all 0x00 */
+#define OV5640_AWB_CTRL_28 0x519c /* default ---- -> all 0x06 */
+#define OV5640_AWB_CTRL_29 0x519d /* default ---- -> all 0x82 */
+#define OV5640_AWB_CTRL_30 0x519e /* default 0x02 -> all 0x38 */
+
+/* CIP Control [0x5300 ~ 0x530F] */
+#define OV5640_CIP_SH_MT_THRES_1 0x5300 /* default 0x08 */
+#define OV5640_CIP_SH_MT_THRES_2 0x5301 /* default 0x48 -> all 0x30 */
+#define OV5640_CIP_SH_MT_OFFSET_1 0x5302 /* default 0x18 -> all 0x10 */
+#define OV5640_CIP_SH_MT_OFFSET_2 0x5303 /* default 0x0e -> all 0x00 */
+#define OV5640_CIP_DNS_THRES_1 0x5304 /* default 0x08 */
+#define OV5640_CIP_DNS_THRES_2 0x5305 /* default 0x48 -> all 0x30 */
+#define OV5640_CIP_DNS_OFFSET_1 0x5306 /* default 0x09 -> all 0x08 */
+#define OV5640_CIP_DNS_OFFSET_2 0x5307 /* default 0x16 */
+#define OV5640_CIP_SH_TH_THRES_1 0x5309 /* default 0x08 */
+#define OV5640_CIP_SH_TH_THRES_2 0x530a /* default 0x48 -> all 0x30 */
+#define OV5640_CIP_SH_TH_OFFSET_1 0x530b /* default 0x04 */
+#define OV5640_CIP_SH_TH_OFFSET_2 0x530c /* default 0x06 */
+
+/* CMX Control [0x5380 ~ 0x538B] */
+#define OV5640_CMX1 0x5381 /* default 0x20 -> all 0x1e */
+#define OV5640_CMX2 0x5382 /* default 0x64 -> all 0x5b */
+#define OV5640_CMX3 0x5383 /* default 0x08 */
+#define OV5640_CMX4 0x5384 /* default 0x30 -> all 0x0a */
+#define OV5640_CMX5 0x5385 /* default 0x80 -> all 0x7e */
+#define OV5640_CMX6 0x5386 /* default 0xc0 -> all 0x88 */
+#define OV5640_CMX7 0x5387 /* default 0xa0 -> all 0x7c */
+#define OV5640_CMX8 0x5388 /* default 0x98 -> all 0x6c */
+#define OV5640_CMX9 0x5389 /* default 0x08 -> all 0x10 */
+#define OV5640_CMX_SIGN_0 0x538A /* default 0x01 */
+#define OV5640_CMX_SIGN_1 0x538B /* default 0x98 */
+
+/* Gamma Control [0x5480 ~ 0x5490] */
+#define OV5640_GAMMA_CTRL_00 0x5480 /* default 0x00 -> all 0x01 */
+#define OV5640_GAMMA_YST_00 0x5481 /* default 0x26 -> all 0x08 */
+#define OV5640_GAMMA_YST_01 0x5482 /* default 0x35 -> all 0x14 */
+
+#define OV5640_GAMMA_YST_02 0x5483 /* default 0x48 -> all 0x28 */
+#define OV5640_GAMMA_YST_03 0x5484 /* default 0x57 -> all 0x51 */
+#define OV5640_GAMMA_YST_04 0x5485 /* default 0x63 -> all 0x65 */
+#define OV5640_GAMMA_YST_05 0x5486 /* default 0x6e -> all 0x71 */
+
+#define OV5640_GAMMA_YST_06 0x5487 /* default 0x77 -> all 0x7d */
+#define OV5640_GAMMA_YST_07 0x5488 /* default 0x80 -> all 0x87 */
+#define OV5640_GAMMA_YST_08 0x5489 /* default 0x88 -> all 0x91 */
+#define OV5640_GAMMA_YST_09 0x548a /* default 0x96 -> all 0x9a */
+#define OV5640_GAMMA_YST_0A 0x548b /* default 0xa3 -> all 0xaa */
+#define OV5640_GAMMA_YST_0B 0x548c /* default 0xaf -> all 0xb8 */
+#define OV5640_GAMMA_YST_0C 0x548d /* default 0xc5 -> all 0xcd */
+#define OV5640_GAMMA_YST_0D 0x548e /* default 0xd7 -> all 0xdd */
+#define OV5640_GAMMA_YST_0E 0x548f /* default 0xe8 -> all 0xea */
+#define OV5640_GAMMA_YST_0F 0x5490 /* default 0x0f -> all 0x1d */
+
+/* SDE Control [0x5580 ~ 0x558C] */
+#define OV5640_SDE_CTRL_0 0x5580 /* default 0x00 -> all 0x02 */
+#define OV5640_SDE_CTRL_3 0x5583 /* default 0x40 */
+#define OV5640_SDE_CTRL_4 0x5584 /* default 0x40 -> all 0x10 */
+#define OV5640_SDE_CTRL_9 0x5589 /* default 0x01 -> all 0x10 */
+#define OV5640_SDE_CTRL_10 0x558a /* default 0x01 -> all 0x00 */
+#define OV5640_SDE_CTRL_11 0x558b /* default 0xff -> all 0xf8 */
+
+/* LENC Control [0x5800 ~ 0x5849] */
+#define OV5640_LENC_GMTRX_00 0x5800 /* default 0x10 -> all 0x23 */
+#define OV5640_LENC_GMTRX_01 0x5801 /* default 0x10 -> all 0x14 */
+#define OV5640_LENC_GMTRX_02 0x5802 /* default 0x10 -> all 0x0f */
+#define OV5640_LENC_GMTRX_03 0x5803 /* default 0x10 -> all 0x0f */
+#define OV5640_LENC_GMTRX_04 0x5804 /* default 0x10 -> all 0x12 */
+#define OV5640_LENC_GMTRX_05 0x5805 /* default 0x10 -> all 0x26 */
+#define OV5640_LENC_GMTRX_10 0x5806 /* default 0x10 -> all 0x0c */
+#define OV5640_LENC_GMTRX_11 0x5807 /* default 0x08 */
+#define OV5640_LENC_GMTRX_12 0x5808 /* default 0x08 -> all 0x05 */
+#define OV5640_LENC_GMTRX_13 0x5809 /* default 0x08 -> all 0x05 */
+#define OV5640_LENC_GMTRX_14 0x580a /* default 0x08 -> all */
+#define OV5640_LENC_GMTRX_15 0x580b /* default 0x10 -> all 0x0d */
+#define OV5640_LENC_GMTRX_20 0x580c /* default 0x10 -> all 0x08 */
+#define OV5640_LENC_GMTRX_21 0x580d /* default 0x08 -> all 0x03 */
+#define OV5640_LENC_GMTRX_22 0x580e /* default 0x00 */
+#define OV5640_LENC_GMTRX_23 0x580f /* default 0x00 */
+#define OV5640_LENC_GMTRX_24 0x5810 /* default 0x08 -> all 0x03 */
+#define OV5640_LENC_GMTRX_25 0x5811 /* default 0x10 -> all 0x09 */
+#define OV5640_LENC_GMTRX_30 0x5812 /* default 0x10 -> all 0x07 */
+#define OV5640_LENC_GMTRX_31 0x5813 /* default 0x08 -> all 0x03 */
+#define OV5640_LENC_GMTRX_32 0x5814 /* default 0x00 */
+#define OV5640_LENC_GMTRX_33 0x5815 /* default 0x00 -> all 0x01 */
+#define OV5640_LENC_GMTRX_34 0x5816 /* default 0x08 -> all 0x03 */
+#define OV5640_LENC_GMTRX_35 0x5817 /* default 0x10 -> all 0x08 */
+#define OV5640_LENC_GMTRX_40 0x5818 /* default 0x10 -> all 0x0d */
+#define OV5640_LENC_GMTRX_41 0x5819 /* default 0x08 */
+#define OV5640_LENC_GMTRX_42 0x581a /* default 0x08 -> all 0x05 */
+#define OV5640_LENC_GMTRX_43 0x581b /* default 0x08 -> all 0x06 */
+#define OV5640_LENC_GMTRX_44 0x581c /* default 0x08 */
+#define OV5640_LENC_GMTRX_45 0x581d /* default 0x10 -> all 0x0e */
+#define OV5640_LENC_GMTRX_50 0x581e /* default 0x10 -> all 0x29 */
+#define OV5640_LENC_GMTRX_51 0x581f /* default 0x10 -> all 0x17 */
+#define OV5640_LENC_GMTRX_52 0x5820 /* default 0x10 -> all 0x11 */
+#define OV5640_LENC_GMTRX_53 0x5821 /* default 0x10 -> all 0x11 */
+#define OV5640_LENC_GMTRX_54 0x5822 /* default 0x10 -> all 0x15 */
+#define OV5640_LENC_GMTRX_55 0x5823 /* default 0x10 -> all 0x28 */
+#define OV5640_LENC_BRMATRX_00 0x5824 /* default 0xaa -> all 0x46 */
+#define OV5640_LENC_BRMATRX_01 0x5825 /* default 0xaa -> all 0x26 */
+#define OV5640_LENC_BRMATRX_02 0x5826 /* default 0xaa -> all 0x08 */
+#define OV5640_LENC_BRMATRX_03 0x5827 /* default 0xaa -> all 0x26 */
+#define OV5640_LENC_BRMATRX_04 0x5828 /* default 0xaa -> all 0x64 */
+#define OV5640_LENC_BRMATRX_05 0x5829 /* default 0xaa -> all 0x26 */
+#define OV5640_LENC_BRMATRX_06 0x582a /* default 0x99 -> all 0x24 */
+#define OV5640_LENC_BRMATRX_07 0x582b /* default 0x99 -> all 0x22 */
+#define OV5640_LENC_BRMATRX_08 0x582c /* default 0x99 -> all 0x24 */
+#define OV5640_LENC_BRMATRX_09 0x582d /* default 0xaa -> all 0x24 */
+#define OV5640_LENC_BRMATRX_20 0x582e /* default 0xaa -> all 0x06 */
+#define OV5640_LENC_BRMATRX_21 0x582f /* default 0x99 -> all 0x22 */
+#define OV5640_LENC_BRMATRX_22 0x5830 /* default 0x88 -> all 0x40 */
+#define OV5640_LENC_BRMATRX_23 0x5831 /* default 0x99 -> all 0x42 */
+#define OV5640_LENC_BRMATRX_24 0x5832 /* default 0xaa -> all 0x24 */
+#define OV5640_LENC_BRMATRX_30 0x5833 /* default 0xaa -> all 0x26 */
+#define OV5640_LENC_BRMATRX_31 0x5834 /* default 0x99 -> all 0x24 */
+#define OV5640_LENC_BRMATRX_32 0x5835 /* default 0x99 -> all 0x22 */
+#define OV5640_LENC_BRMATRX_33 0x5836 /* default 0x99 -> all 0x22 */
+#define OV5640_LENC_BRMATRX_34 0x5837 /* default 0xaa -> all 0x26 */
+#define OV5640_LENC_BRMATRX_40 0x5838 /* default 0xaa -> all 0x44 */
+#define OV5640_LENC_BRMATRX_41 0x5839 /* default 0xaa -> all 0x24 */
+#define OV5640_LENC_BRMATRX_42 0x583a /* default 0xaa -> all 0x26 */
+#define OV5640_LENC_BRMATRX_43 0x583b /* default 0xaa -> all 0x28 */
+#define OV5640_LENC_BRMATRX_44 0x583c /* default 0xaa -> all 0x42 */
+#define OV5640_LENC_BR_OFFSET 0x583d /* default 0x88 -> all 0xce */
+
+
+static struct ov5640_reg mode_2592x1944[] = {
+ /* PLL Control MIPI bit rate/lane = 672MHz, 16-bit mode.
+ * Output size: 2592x1944 (0, 0) - (2623, 1951),
+ * Line Length = 2844, Frame Length = 1968
+ * Scaling method: full resolution (dummy 16 pixel
+ * horizontal, 8 lines) 2608x1952 with dummy
+ */
+
+ {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT },
+ {OV5640_SC_PLL_CTRL1, 0x11},
+ {OV5640_SC_PLL_CTRL2, 0x7d}, /* default 0x69 PLL multipier */
+ {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */
+
+ {OV5640_MIPI_CTRL_00, 0x04},
+ {OV5640_MIPI_PCLK_PERIOD, 0x0a},
+
+ {OV5640_ISP_CTRL_00, 0xa7},
+ {OV5640_ISP_CTRL_01, 0x83},
+ {OV5640_ISP_MUX_CTRL, 0x00},
+
+ /* Timing Control */
+ {OV5640_TIMING_HS_H, OV5640_ADDR_H(0) },
+ {OV5640_TIMING_HS_L, OV5640_ADDR_L(0) },
+ {OV5640_TIMING_VS_H, OV5640_ADDR_H(0) },
+ {OV5640_TIMING_VS_L, OV5640_ADDR_L(0) },
+ {OV5640_TIMING_HW_H, OV5640_ADDR_H(2623) },
+ {OV5640_TIMING_HW_L, OV5640_ADDR_L(2623) },
+ {OV5640_TIMING_VH_H, OV5640_ADDR_H(1951) },
+ {OV5640_TIMING_VH_L, OV5640_ADDR_L(1951) },
+ {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(2592) },
+ {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(2592) },
+ {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(1944) },
+ {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(1944) },
+ {OV5640_TIMING_HTS_H, OV5640_HTS_H(2844) },
+ {OV5640_TIMING_HTS_L, OV5640_HTS_L(2844) },
+ {OV5640_TIMING_VTS_H, OV5640_VTS_H(1968) },
+ {OV5640_TIMING_VTS_L, OV5640_VTS_L(1968) },
+ {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(16) }, // (2623-2592-1)/2
+ {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(16) },
+ {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(4) }, // (1951-1944-1)/2
+ {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(4) },
+ {OV5640_TIMING_X_INC, 0x11},
+ {OV5640_TIMING_Y_INC, 0x11},
+ {OV5640_TIMING_REG20, 0x40},
+ {OV5640_TIMING_REG21, 0},
+
+ /* magic registers */
+ {0x3612, 0x2b},
+ {0x3618, 0x04},
+ {0x3708, 0x64},
+ {0x3709, 0x12},
+ {0x370c, 0x00},
+
+ /* AEC/AGC Power Down Domain Control */
+ {OV5640_AEC_MAX_EXPO60_H, 0x07},
+ {OV5640_AEC_MAX_EXPO60_L, 0xb0},
+ {OV5640_AEC_B50_STEP_H, 0x01},
+ {OV5640_AEC_B50_STEP_L, 0x27},
+ {OV5640_AEC_B60_STEP_H, 0x00},
+ {OV5640_AEC_B60_STEP_L, 0xf6},
+ {OV5640_AEC_CTRL_0E, 0x06},
+ {OV5640_AEC_CTRL_0D, 0x08},
+ {OV5640_AEC_MAX_EXPO_H, 0x07},
+ {OV5640_AEC_MAX_EXPO_L, 0xb0},
+ {OV5640_AEC_CTRL_13, 0x43},
+ {OV5640_AEC_GAIN_CEILING_0, 0x00},
+ {OV5640_AEC_GAIN_CEILING_1, 0xf8},
+ {OV5640_AEC_CTRL_0F, 0x30},
+ {OV5640_AEC_CTRL_10, 0x28},
+ {OV5640_AEC_CTRL_1B, 0x30},
+ {OV5640_AEC_CTRL_1E, 0x26},
+ {OV5640_AEC_CTRL_11, 0x60},
+ {OV5640_AEC_CTRL_1F, 0x14},
+
+ {OV5640_SYSTEM_CTRL, 0x02},
+ {OV5640_TABLE_END, 0x0000}
+};
+
+static struct ov5640_reg mode_1920x1080[] = {
+ /* PLL Control MIPI bit rate/lane = 672MHz, 16-bit mode.
+ * Output size: 1936x1088 (336, 426) - (2287, 1529),
+ * Line Length = 2500, Frame Length = 1120.
+ * Scaling method: cropping from full resolution
+ * 1936x1088 with dummy pixels
+ */
+
+ {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT },
+ {OV5640_SC_PLL_CTRL1, 0x11},
+ {OV5640_SC_PLL_CTRL2, 0x54}, /* default 0x69 PLL multipier */
+ {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */
+
+ {OV5640_MIPI_CTRL_00, 0x04},
+ {OV5640_MIPI_PCLK_PERIOD, 0x0a},
+
+ {OV5640_ISP_CTRL_00, 0xa7},
+ {OV5640_ISP_CTRL_01, 0x83},
+ {OV5640_ISP_MUX_CTRL, 0x00},
+
+ /* Timing Control */
+ {OV5640_TIMING_HS_H, OV5640_ADDR_H(336) },
+ {OV5640_TIMING_HS_L, OV5640_ADDR_L(336) },
+ {OV5640_TIMING_VS_H, OV5640_ADDR_H(426) },
+ {OV5640_TIMING_VS_L, OV5640_ADDR_L(426) },
+ {OV5640_TIMING_HW_H, OV5640_ADDR_H(2287) },
+ {OV5640_TIMING_HW_L, OV5640_ADDR_L(2287) },
+ {OV5640_TIMING_VH_H, OV5640_ADDR_H(1529) },
+ {OV5640_TIMING_VH_L, OV5640_ADDR_L(1529) },
+ {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(1920) }, //1936
+ {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(1920) },
+ {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(1080) }, //1088
+ {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(1080) },
+ {OV5640_TIMING_HTS_H, OV5640_HTS_H(2500) },
+ {OV5640_TIMING_HTS_L, OV5640_HTS_L(2500) },
+ {OV5640_TIMING_VTS_H, OV5640_VTS_H(1120) },
+ {OV5640_TIMING_VTS_L, OV5640_VTS_L(1120) },
+ {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(15) }, // (2287-336-1936-1)/2
+ {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(15) },
+ {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(11) }, // (1529-426-1088-1)/2
+ {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(11) },
+ {OV5640_TIMING_X_INC, 0x11},
+ {OV5640_TIMING_Y_INC, 0x11},
+ {OV5640_TIMING_REG20, 0x40},
+ {OV5640_TIMING_REG21, 0},
+
+ /* magic registers */
+ {0x3612, 0x2b},
+ {0x3618, 0x04},
+ {0x3708, 0x64},
+ {0x3709, 0x12},
+ {0x370c, 0x00},
+
+ /* AEC/AGC Power Down Domain Control */
+ {OV5640_AEC_MAX_EXPO60_H, 0x04},
+ {OV5640_AEC_MAX_EXPO60_L, 0x60},
+ {OV5640_AEC_B50_STEP_H, 0x01},
+ {OV5640_AEC_B50_STEP_L, 0x50},
+ {OV5640_AEC_B60_STEP_H, 0x01},
+ {OV5640_AEC_B60_STEP_L, 0x18},
+ {OV5640_AEC_CTRL_0E, 0x03},
+ {OV5640_AEC_CTRL_0D, 0x04},
+ {OV5640_AEC_MAX_EXPO_H, 0x04},
+ {OV5640_AEC_MAX_EXPO_L, 0x60},
+ {OV5640_AEC_CTRL_13, 0x43},
+ {OV5640_AEC_GAIN_CEILING_0, 0x00},
+ {OV5640_AEC_GAIN_CEILING_1, 0xf8},
+ {OV5640_AEC_CTRL_0F, 0x30},
+ {OV5640_AEC_CTRL_10, 0x28},
+ {OV5640_AEC_CTRL_1B, 0x30},
+ {OV5640_AEC_CTRL_1E, 0x26},
+ {OV5640_AEC_CTRL_11, 0x60},
+ {OV5640_AEC_CTRL_1F, 0x14},
+
+ {OV5640_SYSTEM_CTRL, 0x02},
+ {OV5640_TABLE_END, 0x0000}
+};
+
+static struct ov5640_reg mode_1280x960[] = {
+ /* PLL Control MIPI bit rate/lane = 448MHz, 16-bit mode.
+ * Output size: 1304x972 (0, 0) - (2623, 1951),
+ * Line Length = 1886, Frame Length = 990.
+ * Scaling method: subsampling in vertical and horizontal
+ * 1296x968 supports 2x2 binning
+ */
+
+ {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT },
+ {OV5640_SC_PLL_CTRL1, 0x21},
+ {OV5640_SC_PLL_CTRL2, 0x70}, /* default 0x69 PLL multipier */
+ {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */
+
+ {OV5640_MIPI_CTRL_00, 0x04},
+ {OV5640_MIPI_PCLK_PERIOD, 0x10},
+
+ {OV5640_ISP_CTRL_00, 0xa7},
+ {OV5640_ISP_CTRL_01, 0x83},
+ {OV5640_ISP_MUX_CTRL, 0x00},
+
+ /* Timing Control */
+ {OV5640_TIMING_HS_H, OV5640_ADDR_H(0) },
+ {OV5640_TIMING_HS_L, OV5640_ADDR_L(0) },
+ {OV5640_TIMING_VS_H, OV5640_ADDR_H(0) },
+ {OV5640_TIMING_VS_L, OV5640_ADDR_L(0) },
+ {OV5640_TIMING_HW_H, OV5640_ADDR_H(2623) },
+ {OV5640_TIMING_HW_L, OV5640_ADDR_L(2623) },
+ {OV5640_TIMING_VH_H, OV5640_ADDR_H(1951) },
+ {OV5640_TIMING_VH_L, OV5640_ADDR_L(1951) },
+ {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(1280) },
+ {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(1280) },
+ {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(960) },
+ {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(960) },
+ {OV5640_TIMING_HTS_H, OV5640_HTS_H(1886) },
+ {OV5640_TIMING_HTS_L, OV5640_HTS_L(1886) },
+ {OV5640_TIMING_VTS_H, OV5640_VTS_H(990) },
+ {OV5640_TIMING_VTS_L, OV5640_VTS_L(990) },
+ {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(31) }, // (2623-0-(1280*2)-1)/2
+ {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(31) },
+ {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(15) }, // (1951-0-(960*2)-1)/2
+ {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(15) },
+ {OV5640_TIMING_X_INC, 0x11 | (3<<4) },
+ {OV5640_TIMING_Y_INC, 0x11 | (3<<4) },
+ {OV5640_TIMING_REG20, 0x40},
+ {OV5640_TIMING_REG21, REG21_BINNING_EN},
+
+ /* magic registers */
+ {0x3612, 0x29},
+ {0x3618, 0x00},
+ {0x3708, 0x62},
+ {0x3709, 0x52},
+ {0x370c, 0x03},
+
+ /* AEC/AGC Power Down Domain Control */
+ {OV5640_AEC_MAX_EXPO60_H, 0x03},
+ {OV5640_AEC_MAX_EXPO60_L, 0xd8},
+ {OV5640_AEC_B50_STEP_H, 0x01},
+ {OV5640_AEC_B50_STEP_L, 0x27},
+ {OV5640_AEC_B60_STEP_H, 0x00},
+ {OV5640_AEC_B60_STEP_L, 0xf6},
+ {OV5640_AEC_CTRL_0E, 0x03},
+ {OV5640_AEC_CTRL_0D, 0x04},
+ {OV5640_AEC_MAX_EXPO_H, 0x03},
+ {OV5640_AEC_MAX_EXPO_L, 0xd8},
+ {OV5640_AEC_CTRL_13, 0x43},
+ {OV5640_AEC_GAIN_CEILING_0, 0x00},
+ {OV5640_AEC_GAIN_CEILING_1, 0xf8},
+ {OV5640_AEC_CTRL_0F, 0x30},
+ {OV5640_AEC_CTRL_10, 0x28},
+ {OV5640_AEC_CTRL_1B, 0x30},
+ {OV5640_AEC_CTRL_1E, 0x26},
+ {OV5640_AEC_CTRL_11, 0x60},
+ {OV5640_AEC_CTRL_1F, 0x14},
+
+ {OV5640_SYSTEM_CTRL, 0x02},
+ {OV5640_TABLE_END, 0x0000}
+};
+
+static struct ov5640_reg mode_640x480[] = {
+ /* PLL Control MIPI bit rate/lane = ?MHz, 16-bit mode.
+ * Output size: 640x480 (0, 4) - (2623, 1951),
+ * Line Length = 1896, Frame Length = 984.
+ * Scaling method: subsampling from 1280x960
+ * 648x484 with dummy
+ * supports 2x2 binning
+ */
+
+ {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT },
+ {OV5640_SC_PLL_CTRL1, 0x14},
+ {OV5640_SC_PLL_CTRL2, 0x70}, /* default 0x69 PLL multipier */
+ {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */
+
+ {OV5640_MIPI_CTRL_00, 0x04},
+ {OV5640_MIPI_PCLK_PERIOD, 0x44},
+
+ {OV5640_ISP_CTRL_00, 0xa7},
+ {OV5640_ISP_CTRL_01, 0x83 | ISP_SCALE_EN},
+ {OV5640_ISP_MUX_CTRL, 0x00},
+
+ /* Timing Control */
+ {OV5640_TIMING_HS_H, OV5640_ADDR_H(0) },
+ {OV5640_TIMING_HS_L, OV5640_ADDR_L(0) },
+ {OV5640_TIMING_VS_H, OV5640_ADDR_H(0) },
+ {OV5640_TIMING_VS_L, OV5640_ADDR_L(4) },
+ {OV5640_TIMING_HW_H, OV5640_ADDR_H(2623) },
+ {OV5640_TIMING_HW_L, OV5640_ADDR_L(2623) },
+ {OV5640_TIMING_VH_H, OV5640_ADDR_H(1947) },
+ {OV5640_TIMING_VH_L, OV5640_ADDR_L(1947) },
+ {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(640) },
+ {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(640) },
+ {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(480) },
+ {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(480) },
+ {OV5640_TIMING_HTS_H, OV5640_HTS_H(1896) },
+ {OV5640_TIMING_HTS_L, OV5640_HTS_L(1896) },
+ {OV5640_TIMING_VTS_H, OV5640_VTS_H(984) },
+ {OV5640_TIMING_VTS_L, OV5640_VTS_L(984) },
+ {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(31) }, // (2623-0-(640*2*2)-1)/2
+ {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(31) },
+ {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(11) }, // (1947-4-(480*2*2)-1)/2
+ {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(11) },
+ {OV5640_TIMING_X_INC, 0x11 | (3<<4) },
+ {OV5640_TIMING_Y_INC, 0x11 | (3<<4) },
+ {OV5640_TIMING_REG20, 0x40},
+ {OV5640_TIMING_REG21, REG21_BINNING_EN},
+
+ /* magic registers */
+ {0x3612, 0x29},
+ {0x3618, 0x00},
+ {0x3708, 0x64},
+ {0x3709, 0x52},
+ {0x370c, 0x03},
+
+ /* AEC/AGC Power Down Domain Control */
+ {OV5640_AEC_MAX_EXPO60_H, 0x03},
+ {OV5640_AEC_MAX_EXPO60_L, 0xd8},
+ {OV5640_AEC_B50_STEP_H, 0x01},
+ {OV5640_AEC_B50_STEP_L, 0x27},
+ {OV5640_AEC_B60_STEP_H, 0x00},
+ {OV5640_AEC_B60_STEP_L, 0xf6},
+ {OV5640_AEC_CTRL_0E, 0x03},
+ {OV5640_AEC_CTRL_0D, 0x04},
+ {OV5640_AEC_MAX_EXPO_H, 0x03},
+ {OV5640_AEC_MAX_EXPO_L, 0xd8},
+ {OV5640_AEC_CTRL_13, 0x43},
+ {OV5640_AEC_GAIN_CEILING_0, 0x00},
+ {OV5640_AEC_GAIN_CEILING_1, 0xf8},
+ {OV5640_AEC_CTRL_0F, 0x30},
+ {OV5640_AEC_CTRL_10, 0x28},
+ {OV5640_AEC_CTRL_1B, 0x30},
+ {OV5640_AEC_CTRL_1E, 0x26},
+ {OV5640_AEC_CTRL_11, 0x60},
+ {OV5640_AEC_CTRL_1F, 0x14},
+
+ {OV5640_SYSTEM_CTRL, 0x02},
+ {OV5640_TABLE_END, 0x0000},
+};
+
+static struct ov5640_reg mode_common_registers[] = {
+
+ /* SCCB Control */
+ {OV5640_SCCB_SYSTEM_CTRL, 0x03}, /* Clock from PLL */
+ {OV5640_SCCB_SCLK, 0x01}, /* PCLK = pll_clki, SCLK = pll_clki/2 */
+
+ /* System Control */
+ {OV5640_SYSTEM_CTRL, 0x02 | SYSTEM_CTRL_SRST }, /* Software reset */
+ {OV5640_TABLE_WAIT_MS, 5},
+ {OV5640_SYSTEM_CTRL, 0x02 | SYSTEM_CTRL_PDOWN }, /* Software power down */
+ {OV5640_SYSTEM_RESET_00, 0x00},
+ {OV5640_SYSTEM_RESET_01, 0x00},
+ {OV5640_SYSTEM_RESET_02, 0x1c},
+ {OV5640_SYSTEM_CLK_EN_00, 0xff},
+ {OV5640_SYSTEM_CLK_EN_02, 0xc3},
+ {OV5640_SYSTEM_MIPI_CTRL, 0x45},
+
+ {OV5640_SYSTEM_CTRL_2D, 0x60}, /* magic values */
+ {OV5640_SYSTEM_CTRL_2E, 0x08}, /* magic values */
+
+ /* Format Control */
+ {FMT_CTRL_00, FMT_YUV422 | OFMT_UYVY },
+
+ /* VCM Control */
+/* {OV5640_VCM_DEBUG_MODE_0, 0x08},*/
+/* {OV5640_VCM_DEBUG_MODE_1, 0x33},*/
+
+ /* 50/60Hz detector control */
+ {OV5640_5060_CTRL_01, 0x34},
+ {OV5640_5060_CTRL_04, 0x28},
+ {OV5640_5060_CTRL_05, 0x98},
+ {OV5640_5060_THRESHOLD_1_H, 0x00},
+ {OV5640_5060_THRESHOLD_1_L, 0x07},
+ {OV5640_5060_THRESHOLD_2_H, 0x00},
+ {OV5640_5060_THRESHOLD_2_L, 0x1c},
+ {OV5640_5060_SAMPLE_NUM_H, 0x9c},
+ {OV5640_5060_SAMPLE_NUM_L, 0x40},
+
+ /* BLC Control */
+ {OV5640_BLC_CTRL_01, 0x02},
+ {OV5640_BLC_CTRL_04, 0x06},
+
+ /* AWB Control */
+ {OV5640_AWB_CTRL_00, 0xff},
+ {OV5640_AWB_CTRL_01, 0xf2},
+ {OV5640_AWB_CTRL_02, 0x00},
+ {OV5640_AWB_CTRL_03, 0x14},
+ {OV5640_AWB_CTRL_04, 0x25},
+ {OV5640_AWB_CTRL_05, 0x24},
+ {OV5640_AWB_CTRL_06, 0x09},
+ {OV5640_AWB_CTRL_07, 0x09},
+ {OV5640_AWB_CTRL_08, 0x09},
+ {OV5640_AWB_CTRL_09, 0x75},
+ {OV5640_AWB_CTRL_10, 0x54},
+ {OV5640_AWB_CTRL_11, 0xe0},
+ {OV5640_AWB_CTRL_12, 0xb2},
+ {OV5640_AWB_CTRL_13, 0x42},
+ {OV5640_AWB_CTRL_14, 0x3d},
+ {OV5640_AWB_CTRL_15, 0x56},
+ {OV5640_AWB_CTRL_16, 0x46},
+ {OV5640_AWB_CTRL_17, 0xf8},
+ {OV5640_AWB_CTRL_18, 0x04},
+ {OV5640_AWB_CTRL_19, 0x70},
+ {OV5640_AWB_CTRL_20, 0xf0},
+ {OV5640_AWB_CTRL_21, 0xf0},
+ {OV5640_AWB_CTRL_22, 0x03},
+ {OV5640_AWB_CTRL_23, 0x01},
+ {OV5640_AWB_CTRL_24, 0x04},
+ {OV5640_AWB_CTRL_25, 0x12},
+ {OV5640_AWB_CTRL_26, 0x04},
+ {OV5640_AWB_CTRL_27, 0x00},
+ {OV5640_AWB_CTRL_28, 0x06},
+ {OV5640_AWB_CTRL_29, 0x82},
+ {OV5640_AWB_CTRL_30, 0x38},
+
+ /* CMX Control */
+ {OV5640_CMX1, 0x1e},
+ {OV5640_CMX2, 0x5b},
+ {OV5640_CMX3, 0x08},
+ {OV5640_CMX4, 0x0a},
+ {OV5640_CMX5, 0x7e},
+ {OV5640_CMX6, 0x88},
+ {OV5640_CMX7, 0x7c},
+ {OV5640_CMX8, 0x6c},
+ {OV5640_CMX9, 0x10},
+ {OV5640_CMX_SIGN_0, 0x01},
+ {OV5640_CMX_SIGN_1, 0x98},
+
+ /* CIP Control */
+ {OV5640_CIP_SH_MT_THRES_1, 0x08},
+ {OV5640_CIP_SH_MT_THRES_2, 0x30},
+ {OV5640_CIP_SH_MT_OFFSET_1, 0x10},
+ {OV5640_CIP_SH_MT_OFFSET_2, 0x00},
+ {OV5640_CIP_DNS_THRES_1, 0x08},
+ {OV5640_CIP_DNS_THRES_2, 0x30},
+ {OV5640_CIP_DNS_OFFSET_1, 0x08},
+ {OV5640_CIP_DNS_OFFSET_2, 0x16},
+ {OV5640_CIP_SH_TH_THRES_1, 0x08},
+ {OV5640_CIP_SH_TH_THRES_2, 0x30},
+ {OV5640_CIP_SH_TH_OFFSET_1, 0x04},
+ {OV5640_CIP_SH_TH_OFFSET_2, 0x06},
+
+ /* Gamma Control */
+ {OV5640_GAMMA_CTRL_00, 0x01},
+ {OV5640_GAMMA_YST_00, 0x08},
+ {OV5640_GAMMA_YST_01, 0x14},
+ {OV5640_GAMMA_YST_02, 0x28},
+ {OV5640_GAMMA_YST_03, 0x51},
+ {OV5640_GAMMA_YST_04, 0x65},
+ {OV5640_GAMMA_YST_05, 0x71},
+ {OV5640_GAMMA_YST_06, 0x7d},
+ {OV5640_GAMMA_YST_07, 0x87},
+ {OV5640_GAMMA_YST_08, 0x91},
+ {OV5640_GAMMA_YST_09, 0x9a},
+ {OV5640_GAMMA_YST_0A, 0xaa},
+ {OV5640_GAMMA_YST_0B, 0xb8},
+ {OV5640_GAMMA_YST_0C, 0xcd},
+ {OV5640_GAMMA_YST_0D, 0xdd},
+ {OV5640_GAMMA_YST_0E, 0xea},
+ {OV5640_GAMMA_YST_0F, 0x1d},
+
+ /* SDE Control */
+ {OV5640_SDE_CTRL_0, 0x02},
+ {OV5640_SDE_CTRL_3, 0x40},
+ {OV5640_SDE_CTRL_4, 0x10},
+ {OV5640_SDE_CTRL_9, 0x10},
+ {OV5640_SDE_CTRL_10, 0x00},
+ {OV5640_SDE_CTRL_11, 0xf8},
+
+ /* LENC Control */
+ {OV5640_LENC_GMTRX_00, 0x23},
+ {OV5640_LENC_GMTRX_01, 0x14},
+ {OV5640_LENC_GMTRX_02, 0x0f},
+ {OV5640_LENC_GMTRX_03, 0x0f},
+ {OV5640_LENC_GMTRX_04, 0x12},
+ {OV5640_LENC_GMTRX_05, 0x26},
+ {OV5640_LENC_GMTRX_10, 0x0c},
+ {OV5640_LENC_GMTRX_11, 0x08},
+ {OV5640_LENC_GMTRX_12, 0x05},
+ {OV5640_LENC_GMTRX_13, 0x05},
+ {OV5640_LENC_GMTRX_14, 0x08},
+ {OV5640_LENC_GMTRX_15, 0x0d},
+ {OV5640_LENC_GMTRX_20, 0x08},
+ {OV5640_LENC_GMTRX_21, 0x03},
+ {OV5640_LENC_GMTRX_22, 0x00},
+ {OV5640_LENC_GMTRX_23, 0x00},
+ {OV5640_LENC_GMTRX_24, 0x03},
+ {OV5640_LENC_GMTRX_25, 0x09},
+ {OV5640_LENC_GMTRX_30, 0x07},
+ {OV5640_LENC_GMTRX_31, 0x03},
+ {OV5640_LENC_GMTRX_32, 0x00},
+ {OV5640_LENC_GMTRX_33, 0x01},
+ {OV5640_LENC_GMTRX_34, 0x03},
+ {OV5640_LENC_GMTRX_35, 0x08},
+ {OV5640_LENC_GMTRX_40, 0x0d},
+ {OV5640_LENC_GMTRX_41, 0x08},
+ {OV5640_LENC_GMTRX_42, 0x05},
+ {OV5640_LENC_GMTRX_43, 0x06},
+ {OV5640_LENC_GMTRX_44, 0x08},
+ {OV5640_LENC_GMTRX_45, 0x0e},
+ {OV5640_LENC_GMTRX_50, 0x29},
+ {OV5640_LENC_GMTRX_51, 0x17},
+ {OV5640_LENC_GMTRX_52, 0x11},
+ {OV5640_LENC_GMTRX_53, 0x11},
+ {OV5640_LENC_GMTRX_54, 0x15},
+ {OV5640_LENC_GMTRX_55, 0x28},
+ {OV5640_LENC_BRMATRX_00, 0x46},
+ {OV5640_LENC_BRMATRX_01, 0x26},
+ {OV5640_LENC_BRMATRX_02, 0x08},
+ {OV5640_LENC_BRMATRX_03, 0x26},
+ {OV5640_LENC_BRMATRX_04, 0x64},
+ {OV5640_LENC_BRMATRX_05, 0x26},
+ {OV5640_LENC_BRMATRX_06, 0x24},
+ {OV5640_LENC_BRMATRX_07, 0x22},
+ {OV5640_LENC_BRMATRX_08, 0x24},
+ {OV5640_LENC_BRMATRX_09, 0x24},
+ {OV5640_LENC_BRMATRX_20, 0x06},
+ {OV5640_LENC_BRMATRX_21, 0x22},
+ {OV5640_LENC_BRMATRX_22, 0x40},
+ {OV5640_LENC_BRMATRX_23, 0x42},
+ {OV5640_LENC_BRMATRX_24, 0x24},
+ {OV5640_LENC_BRMATRX_30, 0x26},
+ {OV5640_LENC_BRMATRX_31, 0x24},
+ {OV5640_LENC_BRMATRX_32, 0x22},
+ {OV5640_LENC_BRMATRX_33, 0x22},
+ {OV5640_LENC_BRMATRX_34, 0x26},
+ {OV5640_LENC_BRMATRX_40, 0x44},
+ {OV5640_LENC_BRMATRX_41, 0x24},
+ {OV5640_LENC_BRMATRX_42, 0x26},
+ {OV5640_LENC_BRMATRX_43, 0x28},
+ {OV5640_LENC_BRMATRX_44, 0x42},
+ {OV5640_LENC_BR_OFFSET, 0xce},
+
+ /* magic registers */
+ {0x3620, 0x52},
+ {0x3621, 0xe0},
+ {0x3622, 0x01},
+ {0x3630, 0x36},
+ {0x3631, 0x0e},
+ {0x3632, 0xe2},
+ {0x3633, 0x12},
+ {0x3634, 0x40},
+ {0x3635, 0x13},
+ {0x3636, 0x03},
+ {0x3703, 0x5a},
+ {0x3704, 0xa0},
+ {0x3705, 0x1a},
+ {0x370b, 0x60},
+ {0x3715, 0x78},
+ {0x3717, 0x01},
+ {0x371b, 0x20},
+ {0x3731, 0x12},
+ {0x3901, 0x0a},
+ {0x3905, 0x02},
+ {0x3906, 0x10},
+ {0x471c, 0x50},
+
+ {OV5640_TABLE_END, 0x0000},
+};
+
+enum {
+ OV5640_MODE_640x480,
+ OV5640_MODE_1280x960,
+ OV5640_MODE_1920x1080,
+ OV5640_MODE_2592x1944,
+ OV5640_SIZE_LAST,
+};
+
+static struct ov5640_reg *mode_table[] = {
+ mode_640x480,
+ mode_1280x960,
+ mode_1920x1080,
+ mode_2592x1944,
+};
+
+static int pwn_gpio, rst_gpio;
+static int test_pattern;
+
+module_param(test_pattern, int, 0644);
+
+static struct ov5640_reg tp_cbars[] = {
+ {OV5640_ISP_TEST, ISP_TEST_EN | ISP_TEST_00 | ISP_TEST_TRANSPARENT | ISP_TEST_ROLLING },
+ {OV5640_TABLE_END, 0x0000}
+};
+
+#define to_ov5640(sd) container_of(sd, struct ov5640_priv, subdev)
+
+#define SIZEOF_I2C_TRANSBUF 32
+
+struct ov5640_priv {
+ struct v4l2_subdev subdev;
+ struct media_pad pads[MIPI_CSI2_SENS_VCX_PADS_NUM];
+ struct v4l2_mbus_framefmt mf;
+
+ int ident;
+ u16 chip_id;
+ u8 revision;
+ bool on;
+
+ int mode;
+
+ struct i2c_client *client;
+ u8 i2c_trans_buf[SIZEOF_I2C_TRANSBUF];
+};
+
+static const struct v4l2_frmsize_discrete ov5640_frmsizes[] = {
+ {640, 480},
+ {1280, 960},
+ {1920, 1080},
+ {2592, 1944},
+};
+
+static uint32_t ov5640_codes[] = {
+ MEDIA_BUS_FMT_UYVY8_2X8,
+};
+
+static int ov5640_find_mode(u32 width, u32 height)
+{
+ int i;
+
+ for (i = 0; i < OV5640_SIZE_LAST; i++) {
+ if ((ov5640_frmsizes[i].width >= width) &&
+ (ov5640_frmsizes[i].height >= height))
+ break;
+ }
+
+ /* If not found, select biggest */
+ if (i >= OV5640_SIZE_LAST)
+ i = OV5640_SIZE_LAST - 1;
+
+ return i;
+}
+
+static int ov5640_read_reg(struct i2c_client *client, u16 addr, u8 *val)
+{
+ int err;
+ struct i2c_msg msg[2];
+ unsigned char data[3];
+
+ if (!client->adapter)
+ return -ENODEV;
+
+ msg[0].addr = client->addr;
+ msg[0].flags = 0;
+ msg[0].len = 2;
+ msg[0].buf = data;
+
+ /* high byte goes out first */
+ data[0] = (u8) (addr >> 8);
+ data[1] = (u8) (addr & 0xff);
+
+ msg[1].addr = client->addr;
+ msg[1].flags = I2C_M_RD;
+ msg[1].len = 1;
+ msg[1].buf = data + 2;
+
+ err = i2c_transfer(client->adapter, msg, 2);
+
+ if (err != 2)
+ return -EINVAL;
+
+ *val = data[2];
+
+ return 0;
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+static int ov5640_write_reg(struct i2c_client *client, u16 addr, u8 value)
+{
+ int count;
+ struct i2c_msg msg[1];
+ unsigned char data[4];
+
+ if (!client->adapter)
+ return -ENODEV;
+
+ data[0] = addr;
+ data[1] = (u8) (addr & 0xff);
+ data[2] = value;
+
+ msg[0].addr = client->addr;
+ msg[0].flags = 0;
+ msg[0].len = 3;
+ msg[0].buf = data;
+
+ count = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
+ if (count == ARRAY_SIZE(msg)) {
+ return 0;
+ }
+ dev_err(&client->dev,
+ "ov5840: i2c transfer failed, addr: %x, value: %02x\n",
+ addr, (u32)value);
+ return -EIO;
+}
+#endif
+
+static int ov5640_write_bulk_reg(struct i2c_client *client, u8 *data, int len)
+{
+ int err;
+ struct i2c_msg msg;
+
+ if (!client->adapter)
+ return -ENODEV;
+
+ msg.addr = client->addr;
+ msg.flags = 0;
+ msg.len = len;
+ msg.buf = data;
+
+ err = i2c_transfer(client->adapter, &msg, 1);
+ if (err == 1)
+ return 0;
+
+ dev_err(&client->dev, "ov5640: i2c transfer failed at %x\n",
+ (int)data[0] << 8 | data[1]);
+
+ return err;
+}
+
+static int ov5640_write_table(struct ov5640_priv *priv,
+ struct ov5640_reg table[])
+{
+ int err;
+ struct ov5640_reg *next, *n_next;
+ u8 *b_ptr = priv->i2c_trans_buf;
+ unsigned int buf_filled = 0;
+ u16 val;
+
+ for (next = table; next->addr != OV5640_TABLE_END; next++) {
+ if (next->addr == OV5640_TABLE_WAIT_MS) {
+ msleep(next->val);
+ continue;
+ }
+
+ val = next->val;
+
+ if (!buf_filled) {
+ b_ptr = priv->i2c_trans_buf;
+ *b_ptr++ = next->addr >> 8;
+ *b_ptr++ = next->addr & 0xff;
+ buf_filled = 2;
+ }
+ *b_ptr++ = val;
+ buf_filled++;
+
+ n_next = next + 1;
+ if (n_next->addr != OV5640_TABLE_END &&
+ n_next->addr != OV5640_TABLE_WAIT_MS &&
+ buf_filled < SIZEOF_I2C_TRANSBUF &&
+ n_next->addr == next->addr + 1) {
+ continue;
+ }
+
+ err = ov5640_write_bulk_reg(priv->client,
+ priv->i2c_trans_buf, buf_filled);
+ if (err)
+ return err;
+
+ buf_filled = 0;
+ }
+ return 0;
+}
+
+static void ov5640_set_default_fmt(struct ov5640_priv *priv)
+{
+ struct v4l2_mbus_framefmt *mf = &priv->mf;
+
+ mf->width = ov5640_frmsizes[OV5640_MODE_1920x1080].width;
+ mf->height = ov5640_frmsizes[OV5640_MODE_1920x1080].height;
+ mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
+ mf->field = V4L2_FIELD_NONE;
+ mf->colorspace = V4L2_COLORSPACE_SRGB;
+}
+
+/* Start/Stop streaming from the device */
+static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct ov5640_priv *priv = to_ov5640(sd);
+ int ret = 0;
+
+ if (!enable) {
+ ov5640_set_default_fmt(priv);
+ return 0;
+ }
+
+ ret = ov5640_write_table(priv, mode_common_registers);
+ if (ret)
+ return ret;
+
+ ret = ov5640_write_table(priv, mode_table[priv->mode]);
+ if (ret)
+ return ret;
+
+ if (test_pattern == 1) {
+ ret = ov5640_write_table(priv, tp_cbars);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int ov5640_try_fmt(struct v4l2_subdev *sd,
+ struct v4l2_mbus_framefmt *mf)
+{
+ int mode;
+
+ mode = ov5640_find_mode(mf->width, mf->height);
+ mf->width = ov5640_frmsizes[mode].width;
+ mf->height = ov5640_frmsizes[mode].height;
+
+ mf->field = V4L2_FIELD_NONE;
+ mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
+ mf->colorspace = V4L2_COLORSPACE_SRGB;
+
+ return 0;
+}
+
+static int ov5640_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->pad || code->index >= ARRAY_SIZE(ov5640_codes))
+ return -EINVAL;
+
+ code->code = ov5640_codes[code->index];
+ return 0;
+}
+
+static int ov5640_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *format)
+{
+ struct ov5640_priv *priv = to_ov5640(sd);
+ struct v4l2_mbus_framefmt *mf = &format->format;
+
+ if (format->pad) {
+ return -EINVAL;
+ }
+
+ memcpy(mf, &priv->mf, sizeof(struct v4l2_mbus_framefmt));
+
+ return 0;
+}
+
+/* set the format we will capture in */
+static int ov5640_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *format)
+{
+ struct v4l2_mbus_framefmt *mf = &format->format;
+ struct ov5640_priv *priv = to_ov5640(sd);
+ int ret;
+
+ ret = ov5640_try_fmt(sd, mf);
+ if (ret < 0)
+ return ret;
+
+ priv->mode = ov5640_find_mode(mf->width, mf->height);
+
+ if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+ return 0;
+
+ memcpy(&priv->mf, mf, sizeof(struct v4l2_mbus_framefmt));
+
+ return 0;
+}
+
+static int ov5640_s_power(struct v4l2_subdev *sd, int on)
+{
+ struct ov5640_priv *sensor = to_ov5640(sd);
+
+ sensor->on = on;
+
+ return 0;
+}
+
+static int ov5640_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
+{
+ return 0;
+}
+
+/* Get chip identification */
+static int ov5640_g_chip_ident(struct v4l2_subdev *sd,
+ struct v4l2_dbg_chip_ident *id)
+{
+ struct ov5640_priv *priv = to_ov5640(sd);
+
+ id->ident = priv->ident;
+ id->revision = priv->revision;
+
+ return 0;
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+static int ov5640_get_register(struct v4l2_subdev *sd,
+ struct v4l2_dbg_register *reg)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+ int ret;
+ u8 val;
+
+ if (reg->reg & ~0xffff)
+ return -EINVAL;
+
+ reg->size = 2;
+
+ ret = ov5640_read_reg(client, reg->reg, &val);
+ if (ret)
+ return ret;
+
+ reg->val = (__u64)val;
+
+ return ret;
+}
+
+static int ov5640_set_register(struct v4l2_subdev *sd,
+ struct v4l2_dbg_register *reg)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+ if (reg->reg & ~0xffff || reg->val & ~0xff)
+ return -EINVAL;
+
+ return ov5640_write_reg(client, reg->reg, reg->val);
+}
+#endif
+
+static int ov5640_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
+ struct v4l2_mbus_frame_desc *fd)
+{
+ return 0;
+}
+
+static int ov5640_set_frame_desc(struct v4l2_subdev *sd,
+ unsigned int pad,
+ struct v4l2_mbus_frame_desc *fd)
+{
+ return 0;
+}
+
+static int ov5640_enum_framesizes(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->index >= OV5640_SIZE_LAST)
+ return -EINVAL;
+
+ fse->min_width = fse->max_width = ov5640_frmsizes[fse->index].width;
+ fse->min_height = fse->max_height = ov5640_frmsizes[fse->index].height;
+
+ return 0;
+}
+
+static int ov5640_enum_frame_interval(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_interval_enum *fie)
+{
+ if (fie->index > 1)
+ return -EINVAL;
+
+ /* Force 30 fps */
+ fie->interval.numerator = 1;
+ fie->interval.denominator = 30;
+
+ return 0;
+}
+
+static const struct v4l2_subdev_pad_ops ov5640_pad_ops = {
+ .enum_mbus_code = ov5640_enum_mbus_code,
+ .set_fmt = ov5640_set_fmt,
+ .get_fmt = ov5640_get_fmt,
+ .get_frame_desc = ov5640_get_frame_desc,
+ .set_frame_desc = ov5640_set_frame_desc,
+ .enum_frame_size = ov5640_enum_framesizes,
+ .enum_frame_interval = ov5640_enum_frame_interval,
+};
+
+static struct v4l2_subdev_video_ops ov5640_video_ops = {
+ .s_stream = ov5640_s_stream,
+ .querystd = ov5640_querystd,
+};
+
+static struct v4l2_subdev_core_ops ov5640_core_ops = {
+ .g_chip_ident = ov5640_g_chip_ident,
+ .s_power = ov5640_s_power,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ .g_register = ov5640_get_register,
+ .s_register = ov5640_set_register,
+#endif
+};
+
+static struct v4l2_subdev_ops ov5640_subdev_ops = {
+ .core = &ov5640_core_ops,
+ .video = &ov5640_video_ops,
+ .pad = &ov5640_pad_ops,
+};
+
+int ov5640_link_setup(struct media_entity *entity,
+ const struct media_pad *local,
+ const struct media_pad *remote, u32 flags)
+{
+ return 0;
+}
+
+struct media_entity_operations ov5640_entity_ops = {
+ .link_setup = ov5640_link_setup,
+};
+
+
+static inline void ov5640_power_down(int enable)
+{
+ if (pwn_gpio < 0)
+ return;
+
+ if (!enable)
+ gpio_set_value_cansleep(pwn_gpio, 0);
+ else
+ gpio_set_value_cansleep(pwn_gpio, 1);
+
+ msleep(2);
+}
+
+static void ov5640_reset(void)
+{
+ if (rst_gpio < 0 || pwn_gpio < 0)
+ return;
+
+ /* camera reset */
+ gpio_set_value(rst_gpio, 1);
+
+ /* camera power dowmn */
+ gpio_set_value(pwn_gpio, 1);
+ msleep(5);
+
+ gpio_set_value(rst_gpio, 0);
+ msleep(1);
+
+ gpio_set_value(pwn_gpio, 0);
+ msleep(5);
+
+ gpio_set_value(rst_gpio, 1);
+ msleep(5);
+}
+
+/*
+ * i2c_driver function
+ */
+static int ov5640_probe(struct i2c_client *client,
+ const struct i2c_device_id *did)
+{
+ struct pinctrl *pinctrl;
+ struct device *dev = &client->dev;
+ struct v4l2_subdev *sd;
+ int retval;
+ u8 chip_id_high, chip_id_low;
+
+ struct ov5640_priv *priv;
+
+ priv = devm_kzalloc(&client->dev, sizeof(struct ov5640_priv),
+ GFP_KERNEL);
+ if (!priv) {
+ dev_err(&client->dev, "Failed to allocate private data!\n");
+ return -ENOMEM;
+ }
+
+ /* init using default mode */
+ priv->mode = 2;
+ ov5640_set_default_fmt(priv);
+
+ /* ov5640 pinctrl */
+ pinctrl = devm_pinctrl_get_select_default(dev);
+ if (IS_ERR(pinctrl))
+ dev_warn(dev, "no pin available\n");
+
+ /* request power down pin */
+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
+ if (!gpio_is_valid(pwn_gpio)) {
+ dev_warn(dev, "no sensor pwdn pin available");
+ } else {
+ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+ "ov5640_mipi_pwdn");
+ if (retval < 0) {
+ dev_warn(dev, "Failed to set power pin\n");
+ dev_warn(dev, "retval=%d\n", retval);
+ return retval;
+ }
+ }
+
+ /* request reset pin */
+ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
+ if (!gpio_is_valid(rst_gpio))
+ dev_warn(dev, "no sensor reset pin available");
+ else {
+ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
+ "ov5640_mipi_reset");
+ if (retval < 0) {
+ dev_warn(dev, "Failed to set reset pin\n");
+ return retval;
+ }
+ }
+
+ priv->client = client;
+
+ ov5640_reset();
+
+ ov5640_power_down(0);
+
+ retval = ov5640_read_reg(client, OV5640_CHIP_ID_H, &chip_id_high);
+ if (retval < 0 || chip_id_high != 0x56) {
+ pr_warning("camera ov5640_mipi is not found\n");
+ return -ENODEV;
+ }
+ retval = ov5640_read_reg(client, OV5640_CHIP_ID_L, &chip_id_low);
+ if (retval < 0 || chip_id_low != 0x40) {
+ pr_warning("camera ov5640_mipi is not found\n");
+ return -ENODEV;
+ }
+
+ sd = &priv->subdev;
+ v4l2_i2c_subdev_init(sd, client, &ov5640_subdev_ops);
+
+ ov5640_s_stream(sd, 1);
+
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+
+ sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ priv->pads[MIPI_CSI2_SENS_VC0_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+ priv->pads[MIPI_CSI2_SENS_VC1_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+ priv->pads[MIPI_CSI2_SENS_VC2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+ priv->pads[MIPI_CSI2_SENS_VC3_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+
+ retval = media_entity_pads_init(&sd->entity, MIPI_CSI2_SENS_VCX_PADS_NUM,
+ priv->pads);
+ if (retval < 0)
+ return retval;
+
+ sd->entity.ops = &ov5640_entity_ops;
+ retval = v4l2_async_register_subdev(&priv->subdev);
+
+ if (retval < 0)
+ dev_err(&client->dev, "%s--Async register failed, ret=%d\n", __func__, retval);
+
+ pr_info("camera ov5640_mipi is found, ret: %d\n", retval);
+ return retval;
+}
+
+static int ov5640_remove(struct i2c_client *client)
+{
+ return 0;
+}
+
+static const struct i2c_device_id ov5640_id[] = {
+ {"ov5640_mipi", 0},
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, ov5640_id);
+
+static struct i2c_driver ov5640_i2c_driver = {
+ .driver = {
+ .name = "ov5640_mipi_nv",
+ },
+ .probe = ov5640_probe,
+ .remove = ov5640_remove,
+ .id_table = ov5640_id,
+};
+
+static int __init ov5640_module_init(void)
+{
+ return i2c_add_driver(&ov5640_i2c_driver);
+}
+
+static void __exit ov5640_module_exit(void)
+{
+ i2c_del_driver(&ov5640_i2c_driver);
+}
+
+module_init(ov5640_module_init);
+module_exit(ov5640_module_exit);
+
+MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV5640");
+MODULE_AUTHOR("Andrew Chew <achew@nvidia.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/mxc/capture/ov5642.c b/drivers/media/platform/mxc/capture/ov5642.c
index be6122205c18..c8b8729f9931 100644
--- a/drivers/media/platform/mxc/capture/ov5642.c
+++ b/drivers/media/platform/mxc/capture/ov5642.c
@@ -27,8 +27,11 @@
#include <linux/clk.h>
#include <linux/of_device.h>
#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/fsl_devices.h>
#include <media/v4l2-chip-ident.h>
@@ -3028,8 +3031,36 @@ static void ov5642_standby(s32 enable)
msleep(2);
}
+static s32 update_device_addr(struct sensor_data *sensor)
+{
+ int ret;
+ u8 buf[4];
+ unsigned reg = 0x3100;
+ unsigned default_addr = 0x3c;
+ struct i2c_msg msg;
+
+ if (sensor->i2c_client->addr == default_addr)
+ return 0;
+
+ buf[0] = reg >> 8;
+ buf[1] = reg & 0xff;
+ buf[2] = sensor->i2c_client->addr << 1;
+ msg.addr = default_addr;
+ msg.flags = 0;
+ msg.len = 3;
+ msg.buf = buf;
+
+
+ ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1);
+ if (ret < 0)
+ pr_err("%s: ov5642 ret=%d\n", __func__, ret);
+ return ret;
+}
+
static void ov5642_reset(void)
{
+ mxc_camera_common_lock();
+
/* camera reset */
gpio_set_value(rst_gpio, 1);
@@ -3044,7 +3075,9 @@ static void ov5642_reset(void)
msleep(1);
gpio_set_value(rst_gpio, 1);
- msleep(5);
+ msleep(20);
+ update_device_addr(&ov5642_data);
+ mxc_camera_common_unlock();
gpio_set_value(pwn_gpio, 1);
}
@@ -3113,18 +3146,29 @@ static int ov5642_power_on(struct device *dev)
static s32 ov5642_write_reg(u16 reg, u8 val)
{
+ int ret;
u8 au8Buf[3] = {0};
au8Buf[0] = reg >> 8;
au8Buf[1] = reg & 0xff;
au8Buf[2] = val;
- if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) {
- pr_err("%s:write reg error:reg=%x,val=%x\n",
- __func__, reg, val);
- return -1;
+ if ((reg == 0x3008) && (val & 0x80)) {
+ mxc_camera_common_lock();
+
+ ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3);
+ update_device_addr(&ov5642_data);
+
+ mxc_camera_common_unlock();
+ } else {
+ ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3);
}
+ if (ret < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x ret=%d\n",
+ __func__, reg, val, ret);
+ return ret;
+ }
return 0;
}
@@ -4084,6 +4128,8 @@ static int ov5642_probe(struct i2c_client *client,
struct device *dev = &client->dev;
int retval;
u8 chip_id_high, chip_id_low;
+ struct regmap *gpr;
+ struct sensor_data *sensor = &ov5642_data;
/* ov5642 pinctrl */
pinctrl = devm_pinctrl_get_select_default(dev);
@@ -4138,6 +4184,13 @@ static int ov5642_probe(struct i2c_client *client,
return retval;
}
+ retval = of_property_read_u32(dev->of_node, "ipu_id",
+ &sensor->ipu_id);
+ if (retval) {
+ dev_err(dev, "ipu_id missing or invalid\n");
+ return retval;
+ }
+
retval = of_property_read_u32(dev->of_node, "csi_id",
&(ov5642_data.csi));
if (retval) {
@@ -4177,6 +4230,27 @@ static int ov5642_probe(struct i2c_client *client,
return -ENODEV;
}
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ int mask = ov5642_data.csi ? (1 << 20) : (1 << 19);
+
+ if (sensor->csi != sensor->ipu_id) {
+ pr_warning("%s: csi_id != ipu_id\n", __func__);
+ return -ENODEV;
+ }
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, mask);
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ int mask = ov5642_data.csi ? (7 << 3) : (7 << 0);
+ int val = ov5642_data.csi ? (4 << 3) : (4 << 0);
+
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
ov5642_standby(1);
ov5642_int_device.priv = &ov5642_data;
diff --git a/drivers/media/platform/mxc/capture/tc358743_h2c.c b/drivers/media/platform/mxc/capture/tc358743_h2c.c
new file mode 100644
index 000000000000..8d2e8f7f1ab8
--- /dev/null
+++ b/drivers/media/platform/mxc/capture/tc358743_h2c.c
@@ -0,0 +1,3401 @@
+/*
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * Modifyed by: Edison Fernández <edison.fernandez@ridgerun.com>
+ * Added support to use it with Nitrogen6x
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/fsl_devices.h>
+#include <linux/mutex.h>
+#include <linux/mipi_csi2.h>
+#include <linux/pwm.h>
+#include <media/v4l2-chip-ident.h>
+#include <media/v4l2-int-device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <sound/soc-dapm.h>
+#include <asm/mach-types.h>
+//#include <mach/audmux.h>
+#include <linux/slab.h>
+#include "mxc_v4l2_capture.h"
+
+#define CODEC_CLOCK 16500000
+/* SSI clock sources */
+#define IMX_SSP_SYS_CLK 0
+
+
+#define TC358743_VOLTAGE_ANALOG 2800000
+#define TC358743_VOLTAGE_DIGITAL_CORE 1500000
+#define TC358743_VOLTAGE_DIGITAL_IO 1800000
+
+#define MIN_FPS 30
+#define MAX_FPS 60
+#define DEFAULT_FPS 60
+
+#define TC358743_XCLK_MIN 27000000
+#define TC358743_XCLK_MAX 42000000
+
+#define TC358743_CHIP_ID_HIGH_BYTE 0x0
+#define TC358743_CHIP_ID_LOW_BYTE 0x0
+#define TC3587430_HDMI_DETECT 0x0f //0x10
+
+#define TC_VOLTAGE_ANALOG 2800000
+#define TC_VOLTAGE_DIGITAL_CORE 1500000
+#define TC_VOLTAGE_DIGITAL_IO 1800000
+
+enum tc358743_mode {
+ tc358743_mode_INIT, /*only for sensor init*/
+ tc358743_mode_INIT1, /*only for sensor init*/
+ tc358743_mode_480P_720_480,
+ tc358743_mode_720P_60_1280_720,
+ tc358743_mode_480P_640_480,
+ tc358743_mode_1080P_1920_1080,
+ tc358743_mode_INIT2, /*only for sensor init*/
+ tc358743_mode_INIT3, /*only for sensor init*/
+ tc358743_mode_INIT4, /*only for sensor init*/
+ tc358743_mode_INIT5, /*only for sensor init*/
+ tc358743_mode_INIT6, /*only for sensor init*/
+ tc358743_mode_720P_1280_720,
+ tc358743_mode_MAX ,
+};
+
+enum tc358743_frame_rate {
+ tc358743_60_fps,
+ tc358743_30_fps,
+ tc358743_max_fps
+};
+
+struct reg_value {
+ u16 u16RegAddr;
+ u32 u32Val;
+ u32 u32Mask;
+ u8 u8Length;
+ u32 u32Delay_ms;
+};
+
+struct tc358743_mode_info {
+ enum tc358743_mode mode;
+ u32 width;
+ u32 height;
+ u32 vformat;
+ u32 fps;
+ u32 lanes;
+ u32 freq;
+ struct reg_value *init_data_ptr;
+ u32 init_data_size;
+ __u32 flags;
+};
+
+static struct delayed_work det_work;
+static struct sensor_data tc358743_data;
+static int pwn_gpio, rst_gpio;
+static struct regulator *io_regulator;
+static struct regulator *core_regulator;
+static struct regulator *analog_regulator;
+static struct regulator *gpo_regulator;
+
+static u16 hpd_active = 1;
+
+#define DET_WORK_TIMEOUT_DEFAULT 100
+#define DET_WORK_TIMEOUT_DEFERRED 2000
+#define MAX_BOUNCE 5
+
+static DEFINE_MUTEX(access_lock);
+static int det_work_disable = 0;
+static int det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+static u32 hdmi_mode = 0, lock = 0, bounce = 0, fps = 0, audio = 2;
+
+static int tc358743_init_mode(enum tc358743_frame_rate frame_rate,
+ enum tc358743_mode mode);
+
+static int tc358743_toggle_hpd(int active);
+
+static void tc_standby(s32 enable)
+{
+ if (gpio_is_valid(pwn_gpio))
+ gpio_set_value(pwn_gpio, enable ? 1 : 0);
+ pr_debug("tc_standby: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio);
+ msleep(2);
+}
+
+static void tc_reset(void)
+{
+ /* camera reset */
+ gpio_set_value(rst_gpio, 1);
+
+ /* camera power dowmn */
+ if (gpio_is_valid(pwn_gpio)) {
+ gpio_set_value(pwn_gpio, 1);
+ msleep(5);
+
+ gpio_set_value(pwn_gpio, 0);
+ }
+ msleep(5);
+
+ gpio_set_value(rst_gpio, 0);
+ msleep(1);
+
+ gpio_set_value(rst_gpio, 1);
+ msleep(20);
+
+ if (gpio_is_valid(pwn_gpio))
+ gpio_set_value(pwn_gpio, 1);
+}
+
+static int tc_power_on(struct device *dev)
+{
+ int ret = 0;
+
+ io_regulator = devm_regulator_get(dev, "DOVDD");
+ if (!IS_ERR(io_regulator)) {
+ regulator_set_voltage(io_regulator,
+ TC_VOLTAGE_DIGITAL_IO,
+ TC_VOLTAGE_DIGITAL_IO);
+ ret = regulator_enable(io_regulator);
+ if (ret) {
+ pr_err("%s:io set voltage error\n", __func__);
+ return ret;
+ } else {
+ dev_dbg(dev,
+ "%s:io set voltage ok\n", __func__);
+ }
+ } else {
+ pr_err("%s: cannot get io voltage error\n", __func__);
+ io_regulator = NULL;
+ }
+
+ core_regulator = devm_regulator_get(dev, "DVDD");
+ if (!IS_ERR(core_regulator)) {
+ regulator_set_voltage(core_regulator,
+ TC_VOLTAGE_DIGITAL_CORE,
+ TC_VOLTAGE_DIGITAL_CORE);
+ ret = regulator_enable(core_regulator);
+ if (ret) {
+ pr_err("%s:core set voltage error\n", __func__);
+ return ret;
+ } else {
+ dev_dbg(dev,
+ "%s:core set voltage ok\n", __func__);
+ }
+ } else {
+ core_regulator = NULL;
+ pr_err("%s: cannot get core voltage error\n", __func__);
+ }
+
+ analog_regulator = devm_regulator_get(dev, "AVDD");
+ if (!IS_ERR(analog_regulator)) {
+ regulator_set_voltage(analog_regulator,
+ TC_VOLTAGE_ANALOG,
+ TC_VOLTAGE_ANALOG);
+ ret = regulator_enable(analog_regulator);
+ if (ret) {
+ pr_err("%s:analog set voltage error\n",
+ __func__);
+ return ret;
+ } else {
+ dev_dbg(dev,
+ "%s:analog set voltage ok\n", __func__);
+ }
+ } else {
+ analog_regulator = NULL;
+ pr_err("%s: cannot get analog voltage error\n", __func__);
+ }
+
+ return ret;
+}
+
+static void det_work_enable(int i)
+{
+ mutex_lock(&access_lock);
+ if (i) {
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+ det_work_disable = 0;
+ } else {
+ det_work_disable = 1;
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ }
+ mutex_unlock(&access_lock);
+ pr_debug("%s: %d %d\n", __func__, det_work_disable, det_work_timeout);
+}
+
+static u8 cHDMIEDID[256] = {
+ /* FIXME! This is the edid that my ASUS HDMI monitor returns */
+ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x04, 0x69, 0xf3, 0x24, 0xd6, 0x12, 0x00, 0x00,
+ 0x16, 0x16, 0x01, 0x03, 0x80, 0x34, 0x1d, 0x78, 0x2a, 0xc7, 0x20, 0xa4, 0x55, 0x49, 0x99, 0x27,
+ 0x13, 0x50, 0x54, 0xbf, 0xef, 0x00, 0x71, 0x4f, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
+ 0xd1, 0xc0, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a, 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
+ 0x45, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x36, 0x4c,
+ 0x4d, 0x54, 0x46, 0x30, 0x30, 0x34, 0x38, 0x32, 0x32, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x37,
+ 0x4b, 0x1e, 0x55, 0x10, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
+ 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x48, 0x32, 0x34, 0x32, 0x48, 0x0a, 0x20, 0x01, 0x78,
+ 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03, 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
+ 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
+ 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0, 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0x09, 0x25,
+ 0x21, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72, 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
+ 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x01, 0x1d, 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
+ 0x55, 0x40, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
+ 0x0c, 0x40, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73,
+};
+
+/*!
+ * Maintains the information on the current state of the sesor.
+ */
+
+static struct reg_value tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000040, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000402d, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000801, 0x00000000, 4, 0},
+ {0x021c, 0x00000001, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004800, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa300be82, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (26 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x0000008c, 0x00000000, 1, 0},
+ {0x8541, 0x0000000a, 0x00000000, 1, 0},
+ {0x8630, 0x000000b0, 0x00000000, 1, 0},
+ {0x8631, 0x0000001e, 0x00000000, 1, 0},
+ {0x8632, 0x00000004, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+// {0x8544, 0x00000000, 0x00000000, 1, 1000},
+// {0x8544, 0x00000001, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// Video settings
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+// {0x8651, 0x00000003, 0x00000000, 1, 0}, // Inverted LRCK polarity - (Sony) format
+ {0x8652, 0x00000002, 0x00000000, 1, 0}, // Left-justified I2S (Phillips) format
+// {0x8652, 0x00000000, 0x00000000, 1, 0}, // Right-justified (Sony) format
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+ };
+
+static struct reg_value tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0014, 0x0000ffff, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x00004062, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000d00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000701, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa300be86, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (26 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000000, 0x00000000, 1, 0},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+// {0x8574, 0x00000000, 0x00000000, 1, 0},
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405c, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000801, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000006, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x00000007, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a2, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000a00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x00000580, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405c, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000801, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000006, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001F, 0x00000000, 4, 0}, //{0x0234, 0x00000007, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, //{0x0500, 0xa30080a2, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000a00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x00000300, 0x00000000, 2, 0}, //{0x7092, 0x00000580, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x00004050, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001800, 0x00000000, 4, 0},
+ {0x0214, 0x00000002, 0x00000000, 4, 0},
+ {0x0218, 0x00001102, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000007, 0x00000000, 4, 0},
+ {0x022c, 0x00000001, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000800, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x0020, 0x0000406f, 0x00000000, 2, 100},
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x00000540, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x000080c7, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000003, 0x00000000, 4, 0},
+ {0x0218, 0x00001402, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004a00, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000a00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x000006b8, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x000080c7, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000003, 0x00000000, 4, 0},
+ {0x0218, 0x00001402, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004a00, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// 1920x1023 colorbar
+ {0x000a, 0x00000f00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 1023 lines
+ {0x7090, 0x000003fe, 0x00000000, 2, 0},
+ {0x7092, 0x000004d8, 0x00000000, 2, 0},
+ {0x7094, 0x0000002d, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x00008073, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+// {0x014c, 0x00000000, 0x00000000, 4, 0},
+// {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001200, 0x00000000, 4, 0},
+ {0x0214, 0x00000002, 0x00000000, 4, 0},
+ {0x0218, 0x00000b02, 0x00000000, 4, 0},
+ {0x021c, 0x00000001, 0x00000000, 4, 0},
+ {0x0220, 0x00000103, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000000, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA3008082, 0x00000000, 4, 0},
+// 640x480 colorbar
+ {0x000a, 0x00000500, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 80 pixel black - repeate 80 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)},
+// 80 pixel blue - repeate 40 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel red - repeate 40 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel pink - repeate 40 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel green - repeate 40 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel light blue - repeate 40 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel yellow - repeate 40 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel white - repeate 40 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)},
+// 480 lines
+ {0x7090, 0x000001df, 0x00000000, 2, 0},
+ {0x7092, 0x00000898, 0x00000000, 2, 0},
+ {0x7094, 0x00000285, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000404F, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001800, 0x00000000, 4, 0},
+ {0x0214, 0x00000002, 0x00000000, 4, 0},
+ {0x0218, 0x00001102, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000007, 0x00000000, 4, 0},
+ {0x022c, 0x00000001, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
+// 640x480 colorbar
+ {0x000a, 0x00000500, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 80 pixel black - repeate 80 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)},
+// 80 pixel blue - repeate 40 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel red - repeate 40 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel pink - repeate 40 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel green - repeate 40 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel light blue - repeate 40 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel yellow - repeate 40 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel white - repeate 40 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)},
+// 480 lines
+ {0x7090, 0x000001df, 0x00000000, 2, 0},
+ {0x7092, 0x00000700, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+//480p RGB2YUV442
+static struct reg_value tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000040, 0x00000000, 2, 0},
+// {0x000a, 0x000005a0, 0x00000000, 2, 0},
+// {0x0010, 0x0000001e, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405c, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000d00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000701, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (26 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000000, 0x00000000, 1, 100},
+// {0x8544, 0x00000001, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+ };
+
+//480p RGB2YUV442
+static struct reg_value tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000040, 0x00000000, 2, 0},
+ {0x000a, 0x000005a0, 0x00000000, 2, 0},
+// {0x0010, 0x0000001e, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405b, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000d00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000701, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (27 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000000, 0x00000000, 1, 100},
+// {0x8544, 0x00000001, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+ };
+
+static struct reg_value tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},//0},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},//0},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x000080c7, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000003, 0x00000000, 4, 0},
+ {0x0218, 0x00001402, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004a00, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (27 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000010, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8576, 0x00000060, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0}, // IR control resister
+ {0x0004, 0x00000084, 0x00000000, 2, 0}, // Internal Generated output pattern,Do not send InfoFrame data out to CSI2,Audio output to CSI2-TX i/f,I2C address index increments on every data byte transfer, disable audio and video TX buffers
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},//0}, // Reset devices and set normal operatio (not sleep)
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},//0}, // Clear reset bits
+ {0x0006, 0x000001f8, 0x00000000, 2, 0}, // FIFO level = 1f8 = 504
+ {0x0014, 0x00000000, 0x00000000, 2, 0}, // Clear interrupt status bits
+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, // Mask audio mute, CSI-TX, and the other interrups
+// Program CSI Tx PLL
+ //{0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200
+ {0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200
+ {0x0022, 0x00000213, 0x00000000, 2, 0}, // HSCK frequency = 500MHz – 1GHz HSCK frequency, Loop bandwidth setting = 50% of maximum loop bandwidth (default), REFCLK toggling –> normal operation, REFCLK stops -> no oscillation, Bypass clock = normal operation, clocks switched off (output LOW), PLL Reset normal operation, PLL Enable = PLL on
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0}, // Clock Lane DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x0144, 0x00000000, 0x00000000, 4, 0}, // Data Lane 0 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x0148, 0x00000000, 0x00000000, 4, 0}, // Data Lane 1 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x014c, 0x00000000, 0x00000000, 4, 0}, // Data Lane 2 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x0150, 0x00000000, 0x00000000, 4, 0}, // Data Lane 3 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0}, // LINEINITCNT: Line Initialization Wait Counter = 0x1e00 = 7680
+ {0x0214, 0x00000003, 0x00000000, 4, 0}, // LPTXTIMECNT: SYSLPTX Timing Generation Counter = 3
+ {0x0218, 0x00001402, 0x00000000, 4, 0}, // TCLK_HEADERCNT: TCLK_ZERO Counter = 0x14 = 20, TCLK_PREPARE Counter = 0x02 = 2
+ {0x021c, 0x00000000, 0x00000000, 4, 0}, // TCLK_TRAILCNT: TCLK_TRAIL Counter = 0
+ {0x0220, 0x00000003, 0x00000000, 4, 0}, // THS_HEADERCNT: THS_ZERO Counter = 0, THS_PREPARE Counter = 3
+ {0x0224, 0x00004a00, 0x00000000, 4, 0}, // TWAKEUP: TWAKEUP Counter = 0x4a00 = 18944
+ {0x0228, 0x00000008, 0x00000000, 4, 0}, // TCLK_POSTCNT: TCLK_POST Counter = 8
+ {0x022c, 0x00000002, 0x00000000, 4, 0}, // THS_TRAILCNT: THS_TRAIL Counter = 2
+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, // HSTXVREGEN: Enable voltage regulators for lanes and clk
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, // TXOPTIONCNTRL: Set Continuous Clock Mode
+ {0x0204, 0x00000001, 0x00000000, 4, 0}, // PPI STARTCNTRL: start PPI function
+ {0x0518, 0x00000001, 0x00000000, 4, 0}, // CSI_START: start
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, // CSI Configuration Register: set register 0x040C with data 0x80a6 (CSI MOde, Disables the HTX_TO timer, High-Speed data transfer is performed to Tx, DSCClk Stays in HS mode when Data Lane goes to LP, 4 Data Lanes,The EOT packet is automatically granted at the end of HS transfer then is transmitted)
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0}, // SYSTEM INTERRUPT: clear DDC power change detection interrupt
+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, // SYS INTERRUPT MASK: DDC power change detection interrupt not masked
+ {0x8514, 0x00000000, 0x00000000, 1, 0}, // PACKET INTERRUPT MASK: unmask all
+ {0x8515, 0x00000000, 0x00000000, 1, 0}, // CBIT INTERRUPT MASK: unmask all
+ {0x8516, 0x00000000, 0x00000000, 1, 0}, // AUDIO INTERRUPT MASK: unmask all
+// HDMI Audio RefClk (27 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0}, // PHY CONTROL0: 27MHz, DDC5V detection operation.
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0}, // SYS FREQ0 Register: 27MHz
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, // Audio FS Lock Detect Control: for 27MHz
+ {0x8670, 0x00000001, 0x00000000, 1, 0}, // AUDIO PLL Setting: For REFCLK = 27MHz
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0}, //
+ {0x8536, 0x00000040, 0x00000000, 1, 0}, //
+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, //
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0}, // DDC CONTROL: DDC_ACK output terminal H active, DDC5V_active detect delay 200ms
+ {0x8544, 0x00000010, 0x00000000, 1, 100}, // HPD Control Register: HOTPLUG output ON/OFF control mode = DDC5V detection interlock
+ {0x8545, 0x00000031, 0x00000000, 1, 0}, // ANA CONTROL: PLL charge pump setting for Audio = normal, DAC/PLL power ON/OFF setting for Audio = ON
+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, // AVMUTE CONTROL: AVM_CTL = 0x2d
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0}, // EDID MODE REGISTER: nternal EDID-RAM & DDC2B mode
+ {0x85cb, 0x00000001, 0x00000000, 1, 0}, // EDID Length REGISTER 2: EDID data size stored in RAM (upper address bits) = 0x1 (Size = 0x100 = 256)
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, //
+ {0x8560, 0x00000024, 0x00000000, 1, 0}, // HDCP MODE: HDCP automatic reset when DVI⇔HDMI switched = on, HDCP Line Rekey timing switch = 7clk mode (Data island delay ON), Bcaps[5] KSVINFO_READY(0x8840[5]) auto clear mode = Auto clear using AKSV write
+ {0x8563, 0x00000011, 0x00000000, 1, 0}, //
+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, //
+// RGB --> YUV Conversion
+ {0x8571, 0x00000002, 0x00000000, 1, 0}, //
+ {0x8573, 0x000000c1, 0x00000000, 1, 0}, // VOUT SET2 REGISTER: 422 fixed output, Video Output 422 conversion mode selection 000: During 444 input, 3tap filter; during 422 input, simple decimation, Enable RGB888 to YUV422 Conversion (Fixed Color output)
+ {0x8574, 0x00000008, 0x00000000, 1, 0}, // VOUT SET3 REGISTER (VOUT_SET3): Follow register bit 0x8573[7] setting
+ {0x8576, 0x00000060, 0x00000000, 1, 0}, // VOUT_COLOR: Output Color = 601 YCbCr Limited, Input Pixel Repetition judgment = automatic, Input Pixel Repetition HOST setting = no repetition
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, // PACKET INTERRUPT MODE: all enable
+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, // NO PACKET LIMIT: NO_ACP_LIMIT = 0x2, NO_AVI_LIMIT = 0xC
+ {0x870c, 0x00000053, 0x00000000, 1, 0}, // When VS receive interrupt is detected, VS storage register automatic clear, When ACP receive interrupt is detected, ACP storage register automatic clear, When AVI receive interrupt occurs, judge input video signal with RGB and no Repetition, When AVI receive interrupt is detected, AVI storage register automatic clear.
+ {0x870d, 0x00000001, 0x00000000, 1, 0}, // ERROR PACKET LIMIT: Packet continuing receive error occurrence detection threshold = 1
+ {0x870e, 0x00000030, 0x00000000, 1, 0}, // NO PACKET LIMIT:
+ {0x9007, 0x00000010, 0x00000000, 1, 0}, //
+ {0x854a, 0x00000001, 0x00000000, 1, 0}, // Initialization completed flag
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, // Configuration Control Register: Power Island Normal, I2S/TDM clock are free running, Enable 2 Audio channels, Audio channel number Auto detect by HW, I2S/TDM Data no delay, Select YCbCr422 8-bit (HDMI YCbCr422 12-bit data format), Send InfoFrame data out to CSI2, Audio output to I2S i/f (valid for 2 channel only), I2C address index increments on every data byte transfer, Audio and Video tx buffres enable.
+};
+
+/* list of image formats supported by TCM825X sensor */
+static const struct v4l2_fmtdesc tc358743_formats[] = {
+ {
+ .description = "RGB888 (RGB24)",
+ .pixelformat = V4L2_PIX_FMT_RGB24, /* 24 RGB-8-8-8 */
+ .flags = MIPI_DT_RGB888 // 0x24
+ },
+ {
+ .description = "RAW12 (Y/CbCr 4:2:0)",
+ .pixelformat = V4L2_PIX_FMT_UYVY, /* 12 Y/CbCr 4:2:0 */
+ .flags = MIPI_DT_RAW12 // 0x2c
+ },
+ {
+ .description = "YUV 4:2:2 8-bit",
+ .pixelformat = V4L2_PIX_FMT_YUYV, /* 8 8-bit color */
+ .flags = MIPI_DT_YUV422 // 0x1e /* UYVY... */
+ },
+};
+
+
+static struct tc358743_mode_info tc358743_mode_info_data[2][tc358743_mode_MAX] = {
+ [0][tc358743_mode_720P_60_1280_720] =
+ {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133,
+ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_1080P_1920_1080] =
+ {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0x0b, 4, 300,
+ tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT1] =
+ {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125,
+ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT2] =
+ {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT] =
+ {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT4] =
+ {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT3] =
+ {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_720P_1280_720] =
+ {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125,
+ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_480P_720_480] =
+ {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_480P_640_480] =
+ {tc358743_mode_480P_640_480, 640, 480, 6, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_INIT5] =
+ {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT6] =
+ {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_720P_60_1280_720] =
+ {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133,
+ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_1080P_1920_1080] =
+ {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0xa, 4, 300,
+ tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT1] =
+ {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125,
+ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT2] =
+ {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+
+ [1][tc358743_mode_INIT] =
+ {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT4] =
+ {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT3] =
+ {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_720P_1280_720] =
+ {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125,
+ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz),
+ MIPI_DT_YUV422,
+ },
+ [1][tc358743_mode_480P_720_480] =
+ {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_480P_640_480] =
+ {tc358743_mode_480P_640_480, 640, 480, 1, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [1][tc358743_mode_INIT5] =
+ {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT6] =
+ {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz),
+ MIPI_DT_YUV422
+ },
+};
+
+static int tc358743_probe(struct i2c_client *adapter,
+ const struct i2c_device_id *device_id);
+static int tc358743_remove(struct i2c_client *client);
+
+static s32 tc358743_read_reg(u16 reg, u32 *val);
+static s32 tc358743_write_reg(u16 reg, u32 val, int len);
+
+static const struct i2c_device_id tc358743_id[] = {
+ {"tc358743_mipi", 0},
+ {},
+};
+
+MODULE_DEVICE_TABLE(i2c, tc358743_id);
+
+static struct i2c_driver tc358743_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "tc358743_mipi",
+ },
+ .probe = tc358743_probe,
+ .remove = tc358743_remove,
+ .id_table = tc358743_id,
+};
+
+struct _reg_size
+{
+ u16 startaddr, endaddr;
+ int size;
+}
+tc358743_read_reg_size [] =
+{
+ {0x0000, 0x005a, 2},
+ {0x0140, 0x0150, 4},
+ {0x0204, 0x0238, 4},
+ {0x040c, 0x0418, 4},
+ {0x044c, 0x0454, 4},
+ {0x0500, 0x0518, 4},
+ {0x0600, 0x06cc, 4},
+ {0x7000, 0x7100, 2},
+ {0x8500, 0x8bff, 1},
+ {0x8c00, 0x8fff, 4},
+ {0x9000, 0x90ff, 1},
+ {0x9100, 0x92ff, 1},
+ {0, 0, 0},
+};
+
+static s32 tc358743_write_reg(u16 reg, u32 val, int len)
+{
+ int i = 0;
+ u32 data = val;
+ u8 au8Buf[6] = {0};
+ int size = 0;
+
+ while (0 != tc358743_read_reg_size[i].startaddr ||
+ 0 != tc358743_read_reg_size[i].endaddr ||
+ 0 != tc358743_read_reg_size[i].size) {
+ if (tc358743_read_reg_size[i].startaddr <= reg
+ && tc358743_read_reg_size[i].endaddr >= reg) {
+ size = tc358743_read_reg_size[i].size;
+ break;
+ }
+ i++;
+ }
+ if (!size) {
+ pr_err("%s:write reg error:reg=%x is not found\n",__func__, reg);
+ return -1;
+ }
+ if (size == 3) {
+ size = 2;
+ } else if (size != len) {
+ pr_err("%s:write reg len error:reg=%x %d instead of %d\n",
+ __func__, reg, len, size);
+ return 0;
+ }
+
+ while (len > 0) {
+ i = 0;
+ au8Buf[i++] = (reg >> 8) & 0xff;
+ au8Buf[i++] = reg & 0xff;
+ while (size-- > 0)
+ {
+ au8Buf[i++] = (u8)data;
+ data >>= 8;
+ }
+
+ if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x\n",
+ __func__, reg, val);
+ return -1;
+ }
+ len -= (u8)size;
+ reg += (u16)size;
+ }
+
+ return 0;
+}
+
+static s32 tc358743_read_reg(u16 reg, u32 *val)
+{
+ u8 au8RegBuf[2] = {0};
+ u32 u32RdVal = 0;
+ int i=0;
+ int size = 0;
+
+ while (0 != tc358743_read_reg_size[i].startaddr ||
+ 0 != tc358743_read_reg_size[i].endaddr ||
+ 0 != tc358743_read_reg_size[i].size) {
+ if (tc358743_read_reg_size[i].startaddr <= reg &&
+ tc358743_read_reg_size[i].endaddr >= reg) {
+ size = tc358743_read_reg_size[i].size;
+ break;
+ }
+ i++;
+ }
+ if (!size)
+ return -1;
+
+ au8RegBuf[0] = reg >> 8;
+ au8RegBuf[1] = reg & 0xff;
+
+ if (2 != i2c_master_send(tc358743_data.i2c_client, au8RegBuf, 2)) {
+ pr_err("%s:read reg error:reg=%x\n",
+ __func__, reg);
+ return -1;
+ }
+
+ if (size /*of(u32RdVal)*/ != i2c_master_recv(tc358743_data.i2c_client, (char *)&u32RdVal, size /*of(u32RdVal)*/)) {
+ pr_err("%s:read reg error:reg=%x,val=%x\n",
+ __func__, reg, u32RdVal);
+ return -1;
+ }
+ *val = u32RdVal;
+ return size;
+}
+
+static int tc358743_write_edid(u8 *edid, int len)
+{
+ int i = 0, off = 0;
+ u8 au8Buf[8+2] = {0};
+ int size = 0;
+ u16 reg;
+
+ reg = 0x8C00;
+ off = 0;
+ size = ARRAY_SIZE(au8Buf)-2;
+ pr_debug("Write EDID: %d (%d)\n", len, size);
+ while (len > 0) {
+ i = 0;
+ au8Buf[i++] = (reg >> 8) & 0xff;
+ au8Buf[i++] = reg & 0xff;
+ while (i < ARRAY_SIZE(au8Buf)) {
+ au8Buf[i++] = edid[off++];
+ }
+
+ if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x\n",
+ __func__, reg, off);
+ return -1;
+ }
+ len -= (u8)size;
+ reg += (u16)size;
+ }
+ pr_debug("Activate EDID\n");
+ tc358743_write_reg(0x85c7, 0x01, 1);
+ tc358743_write_reg(0x85ca, 0x00, 1);
+ tc358743_write_reg(0x85cb, 0x01, 1);
+ return 0;
+}
+
+static int tc358743_reset(struct sensor_data *sensor)
+{
+ u32 tgt_fps; /* target frames per secound */
+ enum tc358743_frame_rate frame_rate = tc358743_60_fps;
+ int ret = -1;
+
+ det_work_enable(0);
+ while (ret) {
+ tc_standby(1);
+ mdelay(100);
+ tc_standby(0);
+ mdelay(1000);
+
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60)
+ frame_rate = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate = tc358743_30_fps;
+
+ pr_debug("%s: capture mode: %d extended mode: %d fps: %d\n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode, tgt_fps);
+
+ ret = tc358743_init_mode(frame_rate,
+ sensor->streamcap.capturemode);
+ if (ret)
+ pr_err("%s: Fail to init tc35874! - retry\n", __func__);
+ }
+ det_work_enable(1);
+ return ret;
+}
+
+void mipi_csi2_swreset(struct mipi_csi2_info *info);
+#include "../../../../mxc/mipi/mxc_mipi_csi2.h"
+static int tc358743_init_mode(enum tc358743_frame_rate frame_rate,
+ enum tc358743_mode mode)
+{
+
+ struct reg_value *pModeSetting = NULL;
+ s32 i = 0;
+ s32 iModeSettingArySize = 0;
+ register u32 RepeateLines = 0;
+ register int RepeateTimes = 0;
+ register u32 Delay_ms = 0;
+ register u16 RegAddr = 0;
+ register u32 Mask = 0;
+ register u32 Val = 0;
+ u8 Length;
+ u32 RegVal = 0;
+ int retval = 0;
+ void *mipi_csi2_info;
+ u32 mipi_reg;
+ u32 mipi_reg_test[10];
+
+ pr_debug("%s rate: %d mode: %d\n", __func__, frame_rate, mode);
+ if ((mode > tc358743_mode_MAX || mode < 0)
+ && (mode != tc358743_mode_INIT)) {
+ pr_debug("%s Wrong tc358743 mode detected! %d. Set mode 0\n", __func__, mode);
+ mode = 0;
+ }
+
+ mipi_csi2_info = mipi_csi2_get_info();
+ pr_debug("%s rate: %d mode: %d, info %p\n", __func__, frame_rate, mode, mipi_csi2_info);
+
+ /* initial mipi dphy */
+ tc358743_toggle_hpd(!hpd_active);
+ if (mipi_csi2_info) {
+ pr_debug("%s: mipi_csi2_info:\n"
+ "mipi_en: %d\n"
+ "ipu_id: %d\n"
+ "csi_id: %d\n"
+ "v_channel: %d\n"
+ "lanes: %d\n"
+ "datatype: %d\n"
+ "dphy_clk: %p\n"
+ "pixel_clk: %p\n"
+ "mipi_csi2_base:%p\n"
+ "pdev: %p\n"
+ , __func__,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_en,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->ipu_id,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->csi_id,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->v_channel,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->lanes,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->datatype,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->dphy_clk,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->pixel_clk,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_csi2_base,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->pdev
+ );
+ if (!mipi_csi2_get_status(mipi_csi2_info))
+ mipi_csi2_enable(mipi_csi2_info);
+
+ if (mipi_csi2_get_status(mipi_csi2_info)) {
+ int ifmt;
+ if (tc358743_mode_info_data[frame_rate][mode].lanes != 0) {
+ pr_debug("%s Change lanes: from %d to %d\n", __func__, ((struct mipi_csi2_info *)mipi_csi2_info)->lanes, tc358743_mode_info_data[frame_rate][mode].lanes);
+ ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes;
+ ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes;
+ }
+ pr_debug("Now Using %d lanes\n",mipi_csi2_set_lanes(mipi_csi2_info));
+
+ /*Only reset MIPI CSI2 HW at sensor initialize*/
+ if (!hdmi_mode) // is this during reset
+ mipi_csi2_reset(mipi_csi2_info);
+
+
+ pr_debug("%s format: %x\n", __func__, tc358743_data.pix.pixelformat);
+ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++)
+ if (tc358743_mode_info_data[frame_rate][mode].flags == tc358743_formats[ifmt].flags) {
+ tc358743_data.pix.pixelformat = tc358743_formats[ifmt].pixelformat;
+ pr_debug("%s: %s (%x, %x)\n", __func__, tc358743_formats[ifmt].description, tc358743_data.pix.pixelformat, tc358743_formats[ifmt].flags);
+ mipi_csi2_set_datatype(mipi_csi2_info, tc358743_formats[ifmt].flags);
+ break;
+ }
+ if (ifmt >= ARRAY_SIZE(tc358743_formats)) {
+ pr_err("currently this sensor format (0x%x) can not be supported!\n", tc358743_data.pix.pixelformat);
+ return -1;
+ }
+ } else {
+ pr_err("Can not enable mipi csi2 driver!\n");
+ return -1;
+ }
+ } else {
+ pr_err("Fail to get mipi_csi2_info!\n");
+ return -1;
+ }
+
+ {
+ pModeSetting =
+ tc358743_mode_info_data[frame_rate][mode].init_data_ptr;
+ iModeSettingArySize =
+ tc358743_mode_info_data[frame_rate][mode].init_data_size;
+
+ tc358743_data.pix.width =
+ tc358743_mode_info_data[frame_rate][mode].width;
+ tc358743_data.pix.height =
+ tc358743_mode_info_data[frame_rate][mode].height;
+ pr_debug("%s: Set %d regs from %p for frs %d mode %d with width %d height %d\n", __func__,
+ iModeSettingArySize,
+ pModeSetting,
+ frame_rate,
+ mode,
+ tc358743_data.pix.width,
+ tc358743_data.pix.height);
+ for (i = 0; i < iModeSettingArySize; ++i) {
+ pModeSetting = tc358743_mode_info_data[frame_rate][mode].init_data_ptr + i;
+
+ Delay_ms = pModeSetting->u32Delay_ms & (0xffff);
+ RegAddr = pModeSetting->u16RegAddr;
+ Val = pModeSetting->u32Val;
+ Mask = pModeSetting->u32Mask;
+ Length = pModeSetting->u8Length;
+ if (Mask) {
+ retval = tc358743_read_reg(RegAddr, &RegVal);
+ if (retval < 0)
+ break;
+
+ RegVal &= ~(u8)Mask;
+ Val &= Mask;
+ Val |= RegVal;
+ }
+
+ retval = tc358743_write_reg(RegAddr, Val, Length);
+ if (retval < 0)
+ break;
+
+ if (Delay_ms)
+ msleep(Delay_ms);
+
+ if (0 != ((pModeSetting->u32Delay_ms>>16) & (0xff))) {
+ if (!RepeateTimes) {
+ RepeateTimes = (pModeSetting->u32Delay_ms>>16) & (0xff);
+ RepeateLines = (pModeSetting->u32Delay_ms>>24) & (0xff);
+ }
+ if (--RepeateTimes > 0) {
+ i -= RepeateLines;
+ }
+ }
+ }
+ if (retval < 0) {
+ pr_err("%s: Fail to write REGS to tc35874!\n", __func__);
+ goto err;
+ }
+ }
+ if (!hdmi_mode) // is this during reset
+ if ((retval = tc358743_write_edid(cHDMIEDID, ARRAY_SIZE(cHDMIEDID))))
+ pr_err("%s: Fail to write EDID to tc35874!\n", __func__);
+
+ tc358743_toggle_hpd(hpd_active);
+ if (mipi_csi2_info) {
+ unsigned int i = 0;
+
+ /* wait for mipi sensor ready */
+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
+ while ((mipi_reg == 0x200) && (i < 10)) {
+ mipi_reg_test[i] = mipi_reg;
+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
+ i++;
+ msleep(10);
+ }
+
+ if (i >= 10) {
+ pr_err("mipi csi2 can not receive sensor clk!\n");
+ return -1;
+ }
+
+ {
+ int j;
+ for (j = 0; j < i; j++)
+ {
+ pr_debug("%d mipi csi2 dphy status %x\n", j, mipi_reg_test[j]);
+ }
+ }
+
+ i = 0;
+
+ /* wait for mipi stable */
+ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
+ while ((mipi_reg != 0x0) && (i < 10)) {
+ mipi_reg_test[i] = mipi_reg;
+ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
+ i++;
+ msleep(10);
+ }
+
+ if (i >= 10) {
+ pr_err("mipi csi2 can not reveive data correctly!\n");
+ return -1;
+ }
+
+ {
+ int j;
+ for (j = 0; j < i; j++) {
+ pr_debug("%d mipi csi2 err1 %x\n", j, mipi_reg_test[j]);
+ }
+ }
+ }
+err:
+ return (retval>0)?0:retval;
+}
+
+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
+
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+ pr_debug("%s\n", __func__);
+ if (s == NULL) {
+ pr_err(" ERROR!! no slave device set!\n");
+ return -1;
+ }
+
+ memset(p, 0, sizeof(*p));
+ p->u.bt656.clock_curr = TC358743_XCLK_MIN; //tc358743_data.mclk;
+ pr_debug("%s: clock_curr=mclk=%d\n", __func__, tc358743_data.mclk);
+ p->if_type = V4L2_IF_TYPE_BT656;
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.clock_min = TC358743_XCLK_MIN;
+ p->u.bt656.clock_max = TC358743_XCLK_MAX;
+ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
+
+ return 0;
+}
+
+/*!
+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @on: indicates power mode (on or off)
+ *
+ * Turns the power on or off, depending on the value of on and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+ struct sensor_data *sensor = s->priv;
+
+ pr_debug("%s: %d\n", __func__, on);
+ if (on && !sensor->on) {
+ if (io_regulator)
+ if (regulator_enable(io_regulator) != 0)
+ return -EIO;
+ if (core_regulator)
+ if (regulator_enable(core_regulator) != 0)
+ return -EIO;
+ if (gpo_regulator)
+ if (regulator_enable(gpo_regulator) != 0)
+ return -EIO;
+ if (analog_regulator)
+ if (regulator_enable(analog_regulator) != 0)
+ return -EIO;
+ /* Make sure power on */
+ tc_standby(0);
+
+ } else if (!on && sensor->on) {
+ if (analog_regulator)
+ regulator_disable(analog_regulator);
+ if (core_regulator)
+ regulator_disable(core_regulator);
+ if (io_regulator)
+ regulator_disable(io_regulator);
+ if (gpo_regulator)
+ regulator_disable(gpo_regulator);
+ if (!hdmi_mode)
+ tc358743_reset(sensor);
+ }
+
+ sensor->on = on;
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor_data *sensor = s->priv;
+ struct v4l2_captureparm *cparm = &a->parm.capture;
+ int ret = 0;
+
+ pr_debug("%s type: %x\n", __func__, a->type);
+ switch (a->type) {
+ /* This is the only case currently handled. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ memset(a, 0, sizeof(*a));
+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ cparm->capability = sensor->streamcap.capability;
+ cparm->timeperframe = sensor->streamcap.timeperframe;
+ cparm->capturemode = sensor->streamcap.capturemode;
+ cparm->extendedmode = sensor->streamcap.extendedmode;
+ ret = 0;
+ break;
+
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ ret = -EINVAL;
+ break;
+
+ default:
+ pr_debug(" type is unknown - %d\n", a->type);
+ ret = -EINVAL;
+ break;
+ }
+
+ det_work_enable(1);
+ pr_debug("%s done %d\n", __func__, ret);
+ return ret;
+}
+
+static int tc358743_toggle_hpd(int active)
+{
+ int ret = 0;
+ if (active) {
+ ret += tc358743_write_reg(0x8544, 0x00, 1);
+ mdelay(500);
+ ret += tc358743_write_reg(0x8544, 0x10, 1);
+ } else {
+ ret += tc358743_write_reg(0x8544, 0x10, 1);
+ mdelay(500);
+ ret += tc358743_write_reg(0x8544, 0x00, 1);
+ }
+ return ret;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible. If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor_data *sensor = s->priv;
+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
+ u32 tgt_fps; /* target frames per secound */
+ enum tc358743_frame_rate frame_rate = tc358743_60_fps, frame_rate_now = tc358743_60_fps;
+ int ret = 0;
+
+ pr_debug("%s\n", __func__);
+ det_work_enable(0);
+ /* Make sure power on */
+ tc_standby(0);
+
+ switch (a->type) {
+ /* This is the only case currently handled. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ /* Check that the new frame rate is allowed. */
+ if ((timeperframe->numerator == 0) ||
+ (timeperframe->denominator == 0)) {
+ timeperframe->denominator = DEFAULT_FPS;
+ timeperframe->numerator = 1;
+ }
+
+ tgt_fps = timeperframe->denominator /
+ timeperframe->numerator;
+
+ if (tgt_fps > MAX_FPS) {
+ timeperframe->denominator = MAX_FPS;
+ timeperframe->numerator = 1;
+ } else if (tgt_fps < MIN_FPS) {
+ timeperframe->denominator = MIN_FPS;
+ timeperframe->numerator = 1;
+ }
+
+ /* Actual frame rate we use */
+ tgt_fps = timeperframe->denominator /
+ timeperframe->numerator;
+
+ if (tgt_fps == 60)
+ frame_rate = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate = tc358743_30_fps;
+ else {
+ pr_err(" The camera frame rate is not supported!\n");
+ ret = -EINVAL;
+ break;
+ }
+
+ if ((u32)a->parm.capture.capturemode > tc358743_mode_MAX) {
+ a->parm.capture.capturemode = 0;
+ pr_debug("%s: Forse extended mode: %d \n", __func__,(u32)a->parm.capture.capturemode);
+ }
+
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60)
+ frame_rate_now = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate_now = tc358743_30_fps;
+
+ if (frame_rate_now != frame_rate ||
+ sensor->streamcap.capturemode != (u32)a->parm.capture.capturemode ||
+ sensor->streamcap.extendedmode != (u32)a->parm.capture.extendedmode) {
+ sensor->streamcap.timeperframe = *timeperframe;
+ sensor->streamcap.capturemode =
+ (u32)a->parm.capture.capturemode;
+ sensor->streamcap.extendedmode =
+ (u32)a->parm.capture.extendedmode;
+
+ pr_debug("%s: capture mode: %d extended mode: %d \n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode);
+
+ ret = tc358743_init_mode(frame_rate,
+ sensor->streamcap.capturemode);
+ } else {
+ pr_debug("%s: Keep current settings\n", __func__);
+ }
+ break;
+
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ pr_debug(" type is not " \
+ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
+ a->type);
+ ret = -EINVAL;
+ break;
+
+ default:
+ pr_debug(" type is unknown - %d\n", a->type);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ det_work_enable(1);
+ return ret;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array. Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int ret = 0;
+
+ pr_debug("%s\n", __func__);
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ vc->value = tc358743_data.brightness;
+ break;
+ case V4L2_CID_HUE:
+ vc->value = tc358743_data.hue;
+ break;
+ case V4L2_CID_CONTRAST:
+ vc->value = tc358743_data.contrast;
+ break;
+ case V4L2_CID_SATURATION:
+ vc->value = tc358743_data.saturation;
+ break;
+ case V4L2_CID_RED_BALANCE:
+ vc->value = tc358743_data.red;
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ vc->value = tc358743_data.blue;
+ break;
+ case V4L2_CID_EXPOSURE:
+ vc->value = tc358743_data.ae_mode;
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array). Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int retval = 0;
+
+ pr_debug("In tc358743:ioctl_s_ctrl %d\n",
+ vc->id);
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ break;
+ case V4L2_CID_CONTRAST:
+ break;
+ case V4L2_CID_SATURATION:
+ break;
+ case V4L2_CID_HUE:
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ break;
+ case V4L2_CID_RED_BALANCE:
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ break;
+ case V4L2_CID_GAMMA:
+ break;
+ case V4L2_CID_EXPOSURE:
+ break;
+ case V4L2_CID_AUTOGAIN:
+ break;
+ case V4L2_CID_GAIN:
+ break;
+ case V4L2_CID_HFLIP:
+ break;
+ case V4L2_CID_VFLIP:
+ break;
+ default:
+ retval = -EPERM;
+ break;
+ }
+
+ return retval;
+}
+
+int get_pixelformat(int index)
+{
+ int ifmt;
+
+ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++)
+ if (tc358743_mode_info_data[0][index].flags == tc358743_formats[ifmt].flags)
+ break;
+
+ if (ifmt == ARRAY_SIZE(tc358743_formats))
+ ifmt = 0; /* Default = RBG888 */
+ return ifmt;
+}
+
+/*!
+ * ioctl_enum_framesizes - V4L2 sensor interface handler for
+ * VIDIOC_ENUM_FRAMESIZES ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
+ *
+ * Return 0 if successful, otherwise -EINVAL.
+ */
+static int ioctl_enum_framesizes(struct v4l2_int_device *s,
+ struct v4l2_frmsizeenum *fsize)
+{
+ pr_debug("%s, INDEX: %d\n", __func__,fsize->index);
+ if (fsize->index > tc358743_mode_MAX)
+ return -EINVAL;
+
+ fsize->pixel_format = tc358743_formats[get_pixelformat(fsize->index)].pixelformat;
+ fsize->discrete.width =
+ tc358743_mode_info_data[0][fsize->index].width;
+ fsize->discrete.height =
+ tc358743_mode_info_data[0][fsize->index].height;
+ pr_debug("%s %d:%d format: %x\n", __func__, fsize->discrete.width, fsize->discrete.height, fsize->pixel_format);
+ return 0;
+}
+
+/*!
+ * ioctl_g_chip_ident - V4L2 sensor interface handler for
+ * VIDIOC_DBG_G_CHIP_IDENT ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @id: pointer to int
+ *
+ * Return 0.
+ */
+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
+{
+ ((struct v4l2_dbg_chip_ident *)id)->match.type =
+ V4L2_CHIP_MATCH_I2C_DRIVER;
+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
+ "tc358743_mipi");
+
+ return 0;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+ pr_debug("%s\n", __func__);
+ return 0;
+}
+
+/*!
+ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
+ * @s: pointer to standard V4L2 device structure
+ * @fmt: pointer to standard V4L2 fmt description structure
+ *
+ * Return 0.
+ */
+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
+ struct v4l2_fmtdesc *fmt)
+{
+ pr_debug("%s\n", __func__);
+ if (fmt->index > tc358743_mode_MAX)
+ return -EINVAL;
+
+ fmt->pixelformat = tc358743_formats[get_pixelformat(fmt->index)].pixelformat;
+
+ pr_debug("%s: format: %x\n", __func__, fmt->pixelformat);
+ return 0;
+}
+
+static int ioctl_try_fmt_cap(struct v4l2_int_device *s,
+ struct v4l2_format *f)
+{
+ struct sensor_data *sensor = s->priv;
+ u32 tgt_fps; /* target frames per secound */
+ enum tc358743_frame_rate frame_rate;
+// enum image_size isize;
+ int ifmt;
+ struct v4l2_pix_format *pix = &f->fmt.pix;
+ pr_debug("%s\n", __func__);
+
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60) {
+ frame_rate = tc358743_60_fps;
+ } else if (tgt_fps == 30) {
+ frame_rate = tc358743_30_fps;
+ } else {
+ pr_debug("%s: %d fps (%d,%d) is not supported\n", __func__, tgt_fps, sensor->streamcap.timeperframe.denominator,sensor->streamcap.timeperframe.numerator);
+ return -EINVAL;
+ }
+
+ tc358743_data.pix.width = pix->width = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].width;
+ tc358743_data.pix.height = pix->height = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].height;
+
+ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++)
+ if (tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].flags == tc358743_formats[ifmt].flags)
+ break;
+
+ if (ifmt == ARRAY_SIZE(tc358743_formats))
+ ifmt = 0; /* Default = RBG888 */
+
+ tc358743_data.pix.pixelformat = pix->pixelformat = tc358743_formats[ifmt].pixelformat;
+ pix->field = V4L2_FIELD_NONE;
+ pix->bytesperline = pix->width * 4;
+ pix->sizeimage = pix->bytesperline * pix->height;
+ pix->priv = 0;
+
+ switch (pix->pixelformat) {
+ case V4L2_PIX_FMT_UYVY:
+ default:
+ pix->colorspace = V4L2_COLORSPACE_SRGB;
+ break;
+ }
+
+ {
+ u32 u32val;
+ int ret = tc358743_read_reg(0x8520,&u32val);
+ pr_debug("SYS_STATUS: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8521,&u32val);
+ pr_debug("VI_STATUS0: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8522,&u32val);
+ pr_debug("VI_STATUS1: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8525,&u32val);
+ pr_debug("VI_STATUS2: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8528,&u32val);
+ pr_debug("VI_STATUS3: 0x%x, ret val: %d \n",u32val,ret);
+ pr_debug("%s %d:%d format: %x\n", __func__, pix->width, pix->height, pix->pixelformat);
+ }
+ return 0;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+
+ pr_debug("%s\n", __func__);
+ return ioctl_try_fmt_cap(s, f);
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+ struct sensor_data *sensor = s->priv;
+ u32 tgt_xclk; /* target xclk */
+ u32 tgt_fps; /* target frames per secound */
+ int ret = 0;
+ enum tc358743_frame_rate frame_rate;
+ void *mipi_csi2_info;
+
+ pr_debug("%s\n", __func__);
+ tc358743_data.on = true;
+
+ /* mclk */
+ tgt_xclk = tc358743_data.mclk;
+ tgt_xclk = min(tgt_xclk, (u32)TC358743_XCLK_MAX);
+ tgt_xclk = max(tgt_xclk, (u32)TC358743_XCLK_MIN);
+ tc358743_data.mclk = tgt_xclk;
+
+ pr_debug("%s: Setting mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000);
+// set_mclk_rate(&tc358743_data.mclk, tc358743_data.mclk_source);
+// pr_debug("%s: After mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000);
+
+ /* Default camera frame rate is set in probe */
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60)
+ frame_rate = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate = tc358743_30_fps;
+ else
+ return -EINVAL;
+
+ mipi_csi2_info = mipi_csi2_get_info();
+
+ /* enable mipi csi2 */
+ if (mipi_csi2_info) {
+ mipi_csi2_enable(mipi_csi2_info);
+ } else {
+ pr_err("Fail to get mipi_csi2_info!\n");
+ return -EPERM;
+ }
+
+ pr_debug("%s done\n", __func__);
+ return ret;
+}
+
+/*!
+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Delinitialise the device when slave detaches to the master.
+ */
+static int ioctl_dev_exit(struct v4l2_int_device *s)
+{
+ void *mipi_csi2_info;
+
+ mipi_csi2_info = mipi_csi2_get_info();
+
+ /* disable mipi csi2 */
+ if (mipi_csi2_info)
+ if (mipi_csi2_get_status(mipi_csi2_info))
+ mipi_csi2_disable(mipi_csi2_info);
+
+ return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module and links them to the
+ * enumeration.
+ */
+static struct v4l2_int_ioctl_desc tc358743_ioctl_desc[] = {
+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init},
+ {vidioc_int_dev_exit_num, ioctl_dev_exit},
+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power},
+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm},
+ {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init},
+ {vidioc_int_enum_fmt_cap_num,
+ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap},
+ {vidioc_int_try_fmt_cap_num,
+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap},
+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl},
+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
+ {vidioc_int_enum_framesizes_num,
+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
+ {vidioc_int_g_chip_ident_num,
+ (v4l2_int_ioctl_func *) ioctl_g_chip_ident},
+};
+
+static struct v4l2_int_slave tc358743_slave = {
+ .ioctls = tc358743_ioctl_desc,
+ .num_ioctls = ARRAY_SIZE(tc358743_ioctl_desc),
+};
+
+static struct v4l2_int_device tc358743_int_device = {
+ .module = THIS_MODULE,
+ .name = "tc358743",
+ .type = v4l2_int_type_slave,
+ .u = {
+ .slave = &tc358743_slave,
+ },
+};
+
+
+#ifdef AUDIO_ENABLE
+struct imx_ssi {
+ struct platform_device *ac97_dev;
+
+ struct snd_soc_dai *imx_ac97;
+ struct clk *clk;
+ void __iomem *base;
+ int irq;
+ int fiq_enable;
+ unsigned int offset;
+
+ unsigned int flags;
+
+ void (*ac97_reset) (struct snd_ac97 *ac97);
+ void (*ac97_warm_reset)(struct snd_ac97 *ac97);
+
+ struct imx_pcm_dma_params dma_params_rx;
+ struct imx_pcm_dma_params dma_params_tx;
+
+ int enabled;
+
+ struct platform_device *soc_platform_pdev;
+ struct platform_device *soc_platform_pdev_fiq;
+};
+#define SSI_SCR 0x10
+#define SSI_SRCR 0x20
+#define SSI_STCCR 0x24
+#define SSI_SRCCR 0x28
+#define SSI_SCR_I2S_MODE_NORM (0 << 5)
+#define SSI_SCR_I2S_MODE_MSTR (1 << 5)
+#define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
+#define SSI_I2S_MODE_MASK (3 << 5)
+#define SSI_SCR_SYN (1 << 4)
+#define SSI_SRCR_RSHFD (1 << 4)
+#define SSI_SRCR_RSCKP (1 << 3)
+#define SSI_SRCR_RFSI (1 << 2)
+#define SSI_SRCR_REFS (1 << 0)
+#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
+#define SSI_STCCR_WL_MASK (0xf << 13)
+#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
+#define SSI_SRCCR_WL_MASK (0xf << 13)
+/* Audio setup */
+
+static int imxpac_tc358743_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ int ret;
+
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_IF |
+ SND_SOC_DAIFMT_CBM_CFM);
+ if (ret) {
+ pr_err("%s: failed set cpu dai format\n", __func__);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM);
+ if (ret) {
+ pr_err("%s: failed set codec dai format\n", __func__);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0,
+ CODEC_CLOCK, SND_SOC_CLOCK_OUT);
+ if (ret) {
+ pr_err("%s: failed setting codec sysclk\n", __func__);
+ return ret;
+ }
+ snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0);
+
+ ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
+ SND_SOC_CLOCK_IN);
+ if (ret) {
+ pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n");
+ return ret;
+ }
+#if 1
+// clear SSI_SRCR_RXBIT0 and SSI_SRCR_RSHFD in order to push Right-justified MSB data fro
+ {
+ struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
+ u32 scr = 0, srcr = 0, stccr = 0, srccr = 0;
+
+ pr_debug("%s: base %p\n", __func__, (void *)ssi->base);
+ scr = readl(ssi->base + SSI_SCR);
+ pr_debug("%s: SSI_SCR before: %p\n", __func__, (void *)scr);
+ writel(scr, ssi->base + SSI_SCR);
+ pr_debug("%s: SSI_SCR after: %p\n", __func__, (void *)scr);
+
+ srcr = readl(ssi->base + SSI_SRCR);
+ pr_debug("%s: SSI_SRCR before: %p\n", __func__, (void *)srcr);
+ writel(srcr, ssi->base + SSI_SRCR);
+ pr_debug("%s: SSI_SRCR after: %p\n", __func__, (void *)srcr);
+
+ stccr = readl(ssi->base + SSI_STCCR);
+ pr_debug("%s: SSI_STCCR before: %p\n", __func__, (void *)stccr);
+ stccr &= ~SSI_STCCR_WL_MASK;
+ stccr |= SSI_STCCR_WL(16);
+ writel(stccr, ssi->base + SSI_STCCR);
+ pr_debug("%s: SSI_STCCR after: %p\n", __func__, (void *)stccr);
+
+ srccr = readl(ssi->base + SSI_SRCCR);
+ pr_debug("%s: SSI_SRCCR before: %p\n", __func__, (void *)srccr);
+ srccr &= ~SSI_SRCCR_WL_MASK;
+ srccr |= SSI_SRCCR_WL(16);
+ writel(srccr, ssi->base + SSI_SRCCR);
+ pr_debug("%s: SSI_SRCCR after: %p\n", __func__, (void *)srccr);
+ }
+#endif
+ return 0;
+}
+
+
+
+/* Headphones jack detection DAPM pins */
+static struct snd_soc_jack_pin hs_jack_pins_a[] = {
+};
+
+/* imx_3stack card dapm widgets */
+static struct snd_soc_dapm_widget imx_3stack_dapm_widgets_a[] = {
+};
+
+
+
+static struct snd_kcontrol_new tc358743_machine_controls_a[] = {
+};
+
+/* imx_3stack machine connections to the codec pins */
+static struct snd_soc_dapm_route audio_map_a[] = {
+};
+
+static int imx_3stack_tc358743_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_codec *codec = rtd->codec;
+ int ret;
+ struct snd_soc_jack *hs_jack;
+
+ struct snd_soc_jack_pin *hs_jack_pins;
+ int hs_jack_pins_size;
+ struct snd_soc_dapm_widget *imx_3stack_dapm_widgets;
+ int imx_3stack_dapm_widgets_size;
+ struct snd_kcontrol_new *tc358743_machine_controls;
+ int tc358743_machine_controls_size;
+ struct snd_soc_dapm_route *audio_map;
+ int audio_map_size;
+ int gpio_num = -1;
+ char *gpio_name;
+
+ pr_debug("%s started\n", __func__);
+
+ hs_jack_pins = hs_jack_pins_a;
+ hs_jack_pins_size = ARRAY_SIZE(hs_jack_pins_a);
+ imx_3stack_dapm_widgets = imx_3stack_dapm_widgets_a;
+ imx_3stack_dapm_widgets_size = ARRAY_SIZE(imx_3stack_dapm_widgets_a);
+ tc358743_machine_controls = tc358743_machine_controls_a;
+ tc358743_machine_controls_size = ARRAY_SIZE(tc358743_machine_controls_a);
+ audio_map = audio_map_a;
+ audio_map_size = ARRAY_SIZE(audio_map_a);
+ gpio_num = -1; //card_a_gpio_num;
+ gpio_name = NULL;
+
+ ret = snd_soc_add_controls(codec, tc358743_machine_controls,
+ tc358743_machine_controls_size);
+ if (ret) {
+ pr_err("%s: snd_soc_add_controls failed. err = %d\n", __func__, ret);
+ return ret;
+ }
+ /* Add imx_3stack specific widgets */
+ snd_soc_dapm_new_controls(&codec->dapm, imx_3stack_dapm_widgets,
+ imx_3stack_dapm_widgets_size);
+
+ /* Set up imx_3stack specific audio path audio_map */
+ snd_soc_dapm_add_routes(&codec->dapm, audio_map, audio_map_size);
+
+ snd_soc_dapm_enable_pin(&codec->dapm, hs_jack_pins->pin);
+ snd_soc_dapm_sync(&codec->dapm);
+
+ hs_jack = kzalloc(sizeof(struct snd_soc_jack), GFP_KERNEL);
+
+
+ ret = snd_soc_jack_new(codec, hs_jack_pins->pin,
+ SND_JACK_HEADPHONE, hs_jack);
+ if (ret) {
+ pr_err("%s: snd_soc_jack_new failed. err = %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = snd_soc_jack_add_pins(hs_jack,hs_jack_pins_size,
+ hs_jack_pins);
+ if (ret) {
+ pr_err("%s: snd_soc_jack_add_pinsfailed. err = %d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+
+static struct snd_soc_ops imxpac_tc358743_snd_ops = {
+ .hw_params = imxpac_tc358743_hw_params,
+};
+
+static struct snd_soc_dai_link imxpac_tc358743_dai = {
+ .name = "tc358743",
+ .stream_name = "TC358743",
+ .codec_dai_name = "tc358743-hifi",
+ .platform_name = "imx-pcm-audio.2",
+ .codec_name = "tc358743_mipi.1-000f",
+ .cpu_dai_name = "imx-ssi.2",
+ .init = imx_3stack_tc358743_init,
+ .ops = &imxpac_tc358743_snd_ops,
+};
+
+static struct snd_soc_card imxpac_tc358743 = {
+ .name = "cpuimx-audio_hdmi_in",
+ .dai_link = &imxpac_tc358743_dai,
+ .num_links = 1,
+};
+
+static struct platform_device *imxpac_tc358743_snd_device;
+static struct platform_device *imxpac_tc358743_snd_device;
+
+static int imx_audmux_config(int slave, int master)
+{
+ unsigned int ptcr, pdcr;
+ slave = slave - 1;
+ master = master - 1;
+
+ /* SSI0 mastered by port 5 */
+ ptcr = MXC_AUDMUX_V2_PTCR_SYN |
+ MXC_AUDMUX_V2_PTCR_TFSDIR |
+ MXC_AUDMUX_V2_PTCR_TFSEL(master | 0x8) |
+ MXC_AUDMUX_V2_PTCR_TCLKDIR |
+ MXC_AUDMUX_V2_PTCR_RFSDIR |
+ MXC_AUDMUX_V2_PTCR_RFSEL(master | 0x8) |
+ MXC_AUDMUX_V2_PTCR_RCLKDIR |
+ MXC_AUDMUX_V2_PTCR_RCSEL(master | 0x8) |
+ MXC_AUDMUX_V2_PTCR_TCSEL(master | 0x8);
+ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
+ mxc_audmux_v2_configure_port(slave, ptcr, pdcr);
+
+ ptcr = MXC_AUDMUX_V2_PTCR_SYN;
+ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
+ mxc_audmux_v2_configure_port(master, ptcr, pdcr);
+ return 0;
+}
+
+static int __devinit imx_tc358743_probe(struct platform_device *pdev)
+{
+ struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
+ int ret = 0;
+
+
+ imx_audmux_config(plat->src_port, plat->ext_port);
+
+ ret = -EINVAL;
+ if (plat->init && plat->init())
+ return ret;
+
+ printk("%s %d %s\n",__func__,__LINE__,pdev->name);
+ return 0;
+}
+
+static int imx_tc358743_remove(struct platform_device *pdev)
+{
+ struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
+
+ if (plat->finit)
+ plat->finit();
+
+ return 0;
+}
+
+static struct platform_driver imx_tc358743_audio1_driver = {
+ .probe = imx_tc358743_probe,
+ .remove = imx_tc358743_remove,
+ .driver = {
+ .name = "imx-tc358743",
+ },
+};
+
+
+/* Codec setup */
+static int tc358743_codec_probe(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+
+static int tc358743_codec_remove(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+
+static int tc358743_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+// tc358743_set_bias_level(codec, SND_SOC_BIAS_OFF);
+ return 0;
+}
+
+static int tc358743_codec_resume(struct snd_soc_codec *codec)
+{
+// tc358743_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+ return 0;
+}
+
+static int tc358743_set_bias_level(struct snd_soc_codec *codec,
+ enum snd_soc_bias_level level)
+{
+ return 0;
+}
+
+static const u8 tc358743_reg[0] = {
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_tc358743 = {
+ .set_bias_level = tc358743_set_bias_level,
+ .reg_cache_size = ARRAY_SIZE(tc358743_reg),
+ .reg_word_size = sizeof(u8),
+ .reg_cache_default = tc358743_reg,
+ .probe = tc358743_codec_probe,
+ .remove = tc358743_codec_remove,
+ .suspend = tc358743_codec_suspend,
+ .resume = tc358743_codec_resume,
+};
+
+#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
+#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+static int tc358743_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ return 0;
+}
+
+static int tc358743_mute(struct snd_soc_dai *dai, int mute)
+{
+ return 0;
+}
+
+static int tc358743_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ return 0;
+}
+
+static int tc358743_set_dai_fmt(struct snd_soc_dai *codec_dai,
+ unsigned int fmt)
+{
+ return 0;
+}
+
+static struct snd_soc_dai_ops tc358743_dai_ops = {
+ .hw_params = tc358743_hw_params,
+ .digital_mute = tc358743_mute,
+ .set_sysclk = tc358743_set_dai_sysclk,
+ .set_fmt = tc358743_set_dai_fmt,
+};
+
+static struct snd_soc_dai_driver tc358743_dai = {
+ .name = "tc358743-hifi",
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = AIC3X_RATES,
+ .formats = AIC3X_FORMATS,},
+ .ops = &tc358743_dai_ops,
+ .symmetric_rates = 1,
+};
+
+#endif
+
+static char tc358743_mode_list[16][12] =
+{
+ "None",
+ "VGA",
+ "240p/480i",
+ "288p/576i",
+ "W240p/480i",
+ "W288p/576i",
+ "480p",
+ "576p",
+ "W480p",
+ "W576p",
+ "WW480p",
+ "WW576p",
+ "720p",
+ "1035i",
+ "1080i",
+ "1080p"
+};
+
+static char tc358743_fps_list[tc358743_max_fps+1] =
+{
+[tc358743_60_fps] = 60,
+[tc358743_30_fps] = 30,
+[tc358743_max_fps] = 0
+};
+
+static int tc358743_audio_list[16] =
+{
+ 44100,
+ 0,
+ 48000,
+ 32000,
+ 22050,
+ 384000,
+ 24000,
+ 352800,
+ 88200,
+ 768000,
+ 96000,
+ 705600,
+ 176400,
+ 0,
+ 192000,
+ 0
+};
+
+static char str_on[80];
+static void report_netlink(void)
+{
+ char *envp[2];
+ envp[0] = &str_on[0];
+ envp[1] = NULL;
+ sprintf(envp[0], "HDMI RX: %d (%s) %d %d", (unsigned char)hdmi_mode & 0xf, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], tc358743_fps_list[fps], tc358743_audio_list[audio]);
+ kobject_uevent_env(&(tc358743_data.i2c_client->dev.kobj), KOBJ_CHANGE, envp);
+ det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+ pr_debug("%s: HDMI RX (%d) mode: %s fps: %d (%d, %d) audio: %d\n", __func__, (unsigned char)hdmi_mode, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout, tc358743_audio_list[audio]);
+}
+
+static void det_worker(struct work_struct *work)
+{
+ u32 u32val;
+ u16 reg;
+ int ret;
+
+ mutex_lock(&access_lock);
+ if (!det_work_disable) {
+ reg = 0x8621;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0) {
+ if (audio != (((unsigned char)u32val) & 0x0f)) {
+ audio = ((unsigned char)u32val) & 0x0f;
+ report_netlink();
+ }
+ }
+ reg = 0x852f;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0) {
+ while (1) {
+ if (u32val & TC3587430_HDMI_DETECT) {
+ lock = u32val & TC3587430_HDMI_DETECT;
+ reg = 0x8521;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret < 0) {
+ pr_err("%s: Error reading mode\n", __func__);
+ }
+ } else {
+ if (lock) { // check if it is realy un-plug
+ lock = 0;
+ u32val = 0x0;
+ hdmi_mode = 0xF0; // fake mode to detect un-plug if mode was not detected before.
+ }
+ }
+ if ((unsigned char)hdmi_mode != (unsigned char)u32val) {
+ if (u32val)
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ else
+ det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+ bounce = MAX_BOUNCE;
+ pr_debug("%s: HDMI RX (%d != %d) mode: %s fps: %d (%d, %d)\n", __func__, (unsigned char)hdmi_mode, (unsigned char)u32val, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout);
+ hdmi_mode = u32val;
+ } else if (bounce) {
+ bounce--;
+ det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+ }
+
+ if (1 == bounce) {
+ if (hdmi_mode >= 0xe) {
+ reg = 0x852f;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0)
+ fps = ((((unsigned char)u32val) & 0x0f) > 0xa)? tc358743_60_fps: tc358743_30_fps;
+ }
+ reg = 0x8621;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0) {
+ audio = ((unsigned char)u32val) & 0x0f;
+ report_netlink();
+ }
+ }
+ break;
+ }
+ } else {
+ pr_err("%s: Error reading lock\n", __func__);
+ }
+ } else {
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ }
+ mutex_unlock(&access_lock);
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+}
+
+static irqreturn_t tc358743_detect_handler(int irq, void *data)
+{
+
+ pr_debug("%s: IRQ %d\n", __func__, tc358743_data.i2c_client->irq);
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+ return IRQ_HANDLED;
+}
+
+
+/*!
+ * tc358743 I2C probe function
+ *
+ * @param adapter struct i2c_adapter *
+ * @return Error code indicating success or failure
+ */
+#define DUMP_LENGTH 256
+static u16 regoffs = 0;
+
+static ssize_t tc358743_show_regdump(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int i, len = 0;
+ int retval;
+ u32 u32val;
+
+ mutex_lock(&access_lock);
+ for (i=0; i<DUMP_LENGTH; ) {
+ retval = tc358743_read_reg(regoffs+i, &u32val);
+ if (retval < 0) {
+ u32val =0xff;
+ retval = 1;
+ }
+ while (retval-- > 0) {
+ if (0 == (i & 0xf))
+ len += sprintf(buf+len, "\n%04X:", regoffs+i);
+ len += sprintf(buf+len, " %02X", u32val&0xff);
+ u32val >>= 8;
+ i++;
+ }
+ }
+ mutex_unlock(&access_lock);
+ len += sprintf(buf+len, "\n");
+ return len;
+}
+
+static DEVICE_ATTR(regdump, S_IRUGO, tc358743_show_regdump, NULL);
+
+static ssize_t tc358743_store_regoffs(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 val;
+ int retval;
+ retval = sscanf(buf, "%x", &val);
+ if (1 == retval)
+ regoffs = (u16)val;
+ return count;
+}
+
+static ssize_t tc358743_show_regoffs(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "0x%04X\n", regoffs);
+ return len;
+}
+
+static DEVICE_ATTR(regoffs, S_IRUGO|S_IWUSR, tc358743_show_regoffs, tc358743_store_regoffs);
+
+static ssize_t tc358743_store_hpd(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 val;
+ int retval;
+ retval = sscanf(buf, "%d", &val);
+ if (1 == retval)
+ hpd_active = (u16)val;
+ return count;
+}
+
+static ssize_t tc358743_show_hpd(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", hpd_active);
+ return len;
+}
+
+static DEVICE_ATTR(hpd, S_IRUGO|S_IWUSR, tc358743_show_hpd, tc358743_store_hpd);
+
+static ssize_t tc358743_show_hdmirx(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", hdmi_mode);
+ return len;
+}
+
+static DEVICE_ATTR(hdmirx, S_IRUGO, tc358743_show_hdmirx, NULL);
+
+static ssize_t tc358743_show_fps(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", tc358743_fps_list[fps]);
+ return len;
+}
+
+static DEVICE_ATTR(fps, S_IRUGO, tc358743_show_fps, NULL);
+
+#ifdef AUDIO_ENABLE
+static ssize_t tc358743_show_audio(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", tc358743_audio_list[audio]);
+ return len;
+}
+
+static DEVICE_ATTR(audio, S_IRUGO, tc358743_show_audio, NULL);
+#endif
+
+static int tc358743_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct pwm_device *pwm;
+ struct device *dev = &client->dev;
+ int retval;
+ struct regmap *gpr;
+ struct sensor_data *sensor = &tc358743_data;
+ u32 u32val;
+
+
+ /* request power down pin */
+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
+ if (!gpio_is_valid(pwn_gpio)) {
+ dev_warn(dev, "no sensor pwdn pin available");
+ } else {
+ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+ "tc_mipi_pwdn");
+ if (retval < 0) {
+ dev_warn(dev, "request of pwn_gpio failed");
+ return retval;
+ }
+ }
+ /* request reset pin */
+ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
+ if (!gpio_is_valid(rst_gpio)) {
+ dev_warn(dev, "no sensor reset pin available");
+ return -EINVAL;
+ }
+ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
+ "tc_mipi_reset");
+ if (retval < 0) {
+ dev_warn(dev, "request of tc_mipi_reset failed");
+ return retval;
+ }
+
+ /* Set initial values for the sensor struct. */
+ memset(sensor, 0, sizeof(*sensor));
+
+ sensor->sensor_clk = devm_clk_get(dev, "csi_mclk");
+ if (IS_ERR(sensor->sensor_clk)) {
+ /* assuming clock enabled by default */
+ sensor->sensor_clk = NULL;
+ dev_err(dev, "clock-frequency missing or invalid\n");
+ return PTR_ERR(sensor->sensor_clk);
+ }
+
+ retval = of_property_read_u32(dev->of_node, "mclk",
+ &(sensor->mclk));
+ if (retval) {
+ dev_err(dev, "mclk missing or invalid\n");
+ return retval;
+ }
+
+ retval = of_property_read_u32(dev->of_node, "mclk_source",
+ (u32 *) &(sensor->mclk_source));
+ if (retval) {
+ dev_err(dev, "mclk_source missing or invalid\n");
+ return retval;
+ }
+
+ retval = of_property_read_u32(dev->of_node, "ipu_id",
+ &sensor->ipu_id);
+ if (retval) {
+ dev_err(dev, "ipu_id missing or invalid\n");
+ return retval;
+ }
+
+ retval = of_property_read_u32(dev->of_node, "csi_id",
+ &(sensor->csi));
+ if (retval) {
+ dev_err(dev, "csi id missing or invalid\n");
+ return retval;
+ }
+ if (((unsigned)sensor->ipu_id > 1) || ((unsigned)sensor->csi > 1)) {
+ dev_err(dev, "invalid ipu/csi\n");
+ return -EINVAL;
+ }
+
+ clk_prepare_enable(sensor->sensor_clk);
+
+ sensor->io_init = tc_reset;
+ sensor->i2c_client = client;
+ sensor->pix.pixelformat = tc358743_formats[0].pixelformat;
+ sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY |
+ V4L2_CAP_TIMEPERFRAME;
+ sensor->streamcap.capturemode = 0;
+ sensor->streamcap.extendedmode = tc358743_mode_1080P_1920_1080;
+ sensor->streamcap.timeperframe.denominator = DEFAULT_FPS;
+ sensor->streamcap.timeperframe.numerator = 1;
+
+ sensor->pix.width = tc358743_mode_info_data[0][sensor->streamcap.capturemode].width;
+ sensor->pix.height = tc358743_mode_info_data[0][sensor->streamcap.capturemode].height;
+ pr_debug("%s: format: %x, capture mode: %d extended mode: %d fps: %d width: %d height: %d\n",__func__,
+ sensor->pix.pixelformat,
+ sensor->streamcap.capturemode, sensor->streamcap.extendedmode,
+ sensor->streamcap.timeperframe.denominator *
+ sensor->streamcap.timeperframe.numerator,
+ sensor->pix.width,
+ sensor->pix.height);
+
+ pwm = pwm_get(dev, NULL);
+ if (!IS_ERR(pwm)) {
+ dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->period);
+ pwm_config(pwm, pwm->period >> 1, pwm->period);
+ pwm_enable(pwm);
+ }
+
+ tc_power_on(dev);
+ tc_reset();
+ tc_standby(0);
+
+ retval = tc358743_read_reg(TC358743_CHIP_ID_HIGH_BYTE, &u32val);
+ if (retval < 0) {
+ pr_err("%s:cannot find camera\n", __func__);
+ retval = -ENODEV;
+ goto err4;
+ }
+
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ if (sensor->csi == sensor->ipu_id) {
+ int mask = sensor->csi ? (1 << 20) : (1 << 19);
+
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0);
+ }
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ int mask = sensor->csi ? (7 << 3) : (7 << 0);
+ int val = sensor->csi ? (3 << 3) : (0 << 0);
+
+ if (sensor->ipu_id) {
+ dev_err(dev, "invalid ipu\n");
+ return -EINVAL;
+ }
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
+ tc358743_int_device.priv = sensor;
+
+ //retval = device_create_file(&client->dev, &dev_attr_audio);
+ retval = device_create_file(&client->dev, &dev_attr_fps);
+ retval = device_create_file(&client->dev, &dev_attr_hdmirx);
+ retval = device_create_file(&client->dev, &dev_attr_hpd);
+ retval = device_create_file(&client->dev, &dev_attr_regoffs);
+ retval = device_create_file(&client->dev, &dev_attr_regdump);
+
+ if (retval) {
+ pr_err("%s: create bin file failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+#ifdef AUDIO_ENABLE
+/* Audio setup */
+ retval = snd_soc_register_codec(&client->dev,
+ &soc_codec_dev_tc358743, &tc358743_dai, 1);
+ if (retval) {
+ pr_err("%s: register failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+ retval = platform_driver_register(&imx_tc358743_audio1_driver);
+ if (retval) {
+ pr_err("%s: Platform driver register failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+ imxpac_tc358743_snd_device = platform_device_alloc("soc-audio", 5);
+ if (!imxpac_tc358743_snd_device) {
+ pr_err("%s: Platform device allocation failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+ platform_set_drvdata(imxpac_tc358743_snd_device, &imxpac_tc358743);
+ retval = platform_device_add(imxpac_tc358743_snd_device);
+
+ if (retval) {
+ pr_err("%s: Platform device add failed, error=%d\n",
+ __func__, retval);
+ platform_device_put(imxpac_tc358743_snd_device);
+ goto err4;
+ }
+#endif
+
+#if 1
+ INIT_DELAYED_WORK(&(det_work), det_worker);
+ if (sensor->i2c_client->irq) {
+ retval = request_irq(sensor->i2c_client->irq, tc358743_detect_handler,
+ IRQF_SHARED | IRQF_TRIGGER_FALLING,
+ "tc358743_det", sensor);
+ if (retval < 0)
+ dev_warn(&sensor->i2c_client->dev,
+ "cound not request det irq %d\n",
+ sensor->i2c_client->irq);
+ }
+
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+#endif
+ retval = tc358743_reset(sensor);
+
+ tc_standby(1);
+ retval = v4l2_int_device_register(&tc358743_int_device);
+ if (retval) {
+ pr_err("%s: v4l2_int_device_register failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+ pr_debug("%s: finished, error=%d\n",
+ __func__, retval);
+ return retval;
+
+err4:
+ pr_err("%s: failed, error=%d\n",
+ __func__, retval);
+ return retval;
+}
+
+/*!
+ * tc358743 I2C detach function
+ *
+ * @param client struct i2c_client *
+ * @return Error code indicating success or failure
+ */
+static int tc358743_remove(struct i2c_client *client)
+{
+ // Stop delayed work
+ cancel_delayed_work_sync(&(det_work));
+
+ // Remove IRQ
+ if (tc358743_data.i2c_client->irq) {
+ free_irq(tc358743_data.i2c_client->irq, &tc358743_data);
+ }
+
+ /*Remove sysfs entries*/
+ device_remove_file(&client->dev, &dev_attr_fps);
+ device_remove_file(&client->dev, &dev_attr_hdmirx);
+ device_remove_file(&client->dev, &dev_attr_hpd);
+ device_remove_file(&client->dev, &dev_attr_regoffs);
+ device_remove_file(&client->dev, &dev_attr_regdump);
+
+ v4l2_int_device_unregister(&tc358743_int_device);
+
+ if (gpo_regulator) {
+ regulator_disable(gpo_regulator);
+ regulator_put(gpo_regulator);
+ }
+
+ if (analog_regulator) {
+ regulator_disable(analog_regulator);
+ regulator_put(analog_regulator);
+ }
+
+ if (core_regulator) {
+ regulator_disable(core_regulator);
+ regulator_put(core_regulator);
+ }
+
+ if (io_regulator) {
+ regulator_disable(io_regulator);
+ regulator_put(io_regulator);
+ }
+
+ return 0;
+}
+
+/*!
+ * tc358743 init function
+ * Called by insmod tc358743_camera.ko.
+ *
+ * @return Error code indicating success or failure
+ */
+static __init int tc358743_init(void)
+{
+ int err;
+
+ err = i2c_add_driver(&tc358743_i2c_driver);
+ if (err != 0)
+ pr_err("%s:driver registration failed, error=%d\n",
+ __func__, err);
+
+ return err;
+}
+
+/*!
+ * tc358743 cleanup function
+ * Called on rmmod tc358743_camera.ko
+ *
+ * @return Error code indicating success or failure
+ */
+static void __exit tc358743_clean(void)
+{
+ i2c_del_driver(&tc358743_i2c_driver);
+}
+
+module_init(tc358743_init);
+module_exit(tc358743_clean);
+
+MODULE_AUTHOR("Panasonic Avionics Corp.");
+MODULE_DESCRIPTION("Toshiba TC358743 HDMI-to-CSI2 Bridge MIPI Input Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("CSI");
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-02 16:29:31 +0000