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Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pci-imx6.c40
-rw-r--r--drivers/pci/probe.c7
-rw-r--r--drivers/pci/quirks.c24
3 files changed, 59 insertions, 12 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index c3cc315473ce..24d7ea634453 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -73,6 +73,7 @@ struct imx_pcie {
int power_on_gpio;
int reset_gpio;
bool gpio_active_high;
+ int reset_ep_gpio;
struct clk *pcie_bus;
struct clk *pcie_inbound_axi;
struct clk *pcie_phy;
@@ -95,6 +96,7 @@ struct imx_pcie {
struct regulator *pcie_phy_regulator;
struct regulator *pcie_bus_regulator;
struct regulator *epdev_on;
+ int force_detect_state;
};
/* PCIe Root Complex registers (memory-mapped) */
@@ -495,11 +497,7 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
- val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR);
- val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
- val |= PCIE_PL_PFLR_FORCE_LINK;
- dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
-
+ imx_pcie->force_detect_state = 1;
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
}
@@ -932,13 +930,22 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
/* Some boards don't have PCIe reset GPIO. */
if (gpio_is_valid(imx_pcie->reset_gpio)) {
+ if (gpio_is_valid(imx_pcie->reset_ep_gpio))
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 1);
gpio_set_value_cansleep(imx_pcie->reset_gpio,
imx_pcie->gpio_active_high);
mdelay(20);
gpio_set_value_cansleep(imx_pcie->reset_gpio,
!imx_pcie->gpio_active_high);
- mdelay(20);
+ mdelay(1);
+ if (gpio_is_valid(imx_pcie->reset_ep_gpio))
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 0);
+ } else if (gpio_is_valid(imx_pcie->reset_ep_gpio)) {
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 1);
+ mdelay(100);
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 0);
}
+ mdelay(20);
if (ret == 0)
return ret;
@@ -1552,6 +1559,16 @@ static int imx_pcie_establish_link(struct imx_pcie *imx_pcie)
goto out;
}
+ if (imx_pcie->force_detect_state) {
+ u32 val;
+
+ imx_pcie->force_detect_state = 0;
+ val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR);
+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+ val |= PCIE_PL_PFLR_FORCE_LINK;
+ dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
+ }
+
/*
* Start Directed Speed Change so the best possible speed both link
* partners support can be negotiated.
@@ -2330,6 +2347,17 @@ static int imx_pcie_probe(struct platform_device *pdev)
} else if (imx_pcie->dis_gpio == -EPROBE_DEFER) {
return imx_pcie->dis_gpio;
}
+ imx_pcie->reset_ep_gpio = of_get_named_gpio(node, "reset-ep-gpio", 0);
+ if (gpio_is_valid(imx_pcie->reset_ep_gpio)) {
+ ret = devm_gpio_request_one(&pdev->dev,
+ imx_pcie->reset_ep_gpio,
+ GPIOF_OUT_INIT_HIGH,
+ "PCIe EP reset");
+ if (ret) {
+ dev_err(&pdev->dev, "unable to get reset end point gpio\n");
+ return ret;
+ }
+ }
imx_pcie->power_on_gpio = of_get_named_gpio(node, "power-on-gpio", 0);
if (gpio_is_valid(imx_pcie->power_on_gpio)) {
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 16611cf3aba4..6b5cee5ae933 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -932,8 +932,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
child = pci_add_new_bus(bus, dev, max+1);
if (!child)
goto out;
- pci_bus_insert_busn_res(child, max+1,
- bus->busn_res.end);
+ pci_bus_insert_busn_res(child, max+1, 0xff);
}
max++;
buses = (buses & 0xff000000)
@@ -2141,10 +2140,6 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
max = bus->busn_res.start + pci_hotplug_bus_size - 1;
-
- /* Do not allocate more buses than we have room left */
- if (max > bus->busn_res.end)
- max = bus->busn_res.end;
}
/*
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 496296bc3581..ff5bfb6d5ce2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2319,6 +2319,21 @@ static void quirk_tile_plx_gen1(struct pci_dev *dev)
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
#endif /* CONFIG_TILEPRO */
+#ifdef CONFIG_PCI_FORCE_GEN1
+/*
+ * The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1).
+ * The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2
+ * PCIe Capability Register of the PEX8605 PCIe switch. The switch supports
+ * link speed auto negotiation, but falsely sets the link speed to 5 GT/s.
+ */
+static void quirk_apalis_plx_gen1(struct pci_dev *dev)
+{
+ pci_write_config_dword(dev, 0x98, 0x1);
+ mdelay(50);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1);
+#endif /* CONFIG_PCI_FORCE_GEN1 */
+
#ifdef CONFIG_PCI_MSI
/* Some chipsets do not support MSI. We cannot easily rely on setting
* PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
@@ -2974,6 +2989,15 @@ static void fixup_ti816x_class(struct pci_dev *dev)
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
+/* TW6869 Frame grabber has same problem as ti816x */
+static void fixup_tw6869_class(struct pci_dev* dev)
+{
+ dev_info(&dev->dev, "Setting PCI class for tw6869 PCIe device\n");
+ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869,
+ PCI_CLASS_NOT_DEFINED, 0, fixup_tw6869_class);
+
/* Some PCIe devices do not work reliably with the claimed maximum
* payload size supported.
*/
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-12 14:00:05 +0000