diff options
Diffstat (limited to 'drivers/video/geode/display_gx.c')
| -rw-r--r-- | drivers/video/geode/display_gx.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c index 47f422e19974..acf20bf2d26c 100644 --- a/drivers/video/geode/display_gx.c +++ b/drivers/video/geode/display_gx.c @@ -51,20 +51,21 @@ static void gx_set_mode(struct fb_info *info) int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; /* Unlock the display controller registers. */ - write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE); + write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); gcfg = read_dc(par, DC_GENERAL_CFG); dcfg = read_dc(par, DC_DISPLAY_CFG); /* Disable the timing generator. */ - dcfg &= ~(DC_DCFG_TGEN); + dcfg &= ~DC_DISPLAY_CFG_TGEN; write_dc(par, DC_DISPLAY_CFG, dcfg); /* Wait for pending memory requests before disabling the FIFO load. */ udelay(100); /* Disable FIFO load and compression. */ - gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); + gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE | + DC_GENERAL_CFG_DECE); write_dc(par, DC_GENERAL_CFG, gcfg); /* Setup DCLK and its divisor. */ @@ -75,12 +76,13 @@ static void gx_set_mode(struct fb_info *info) */ /* Clear all unused feature bits. */ - gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE; + gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE; dcfg = 0; /* Set FIFO priority (default 6/5) and enable. */ /* FIXME: increase fifo priority for 1280x1024 and higher modes? */ - gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; + gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) | + (5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE; /* Framebuffer start offset. */ write_dc(par, DC_FB_ST_OFFSET, 0); @@ -92,25 +94,25 @@ static void gx_set_mode(struct fb_info *info) /* Enable graphics and video data and unmask address lines. */ - dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M; + dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN | + DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M; /* Set pixel format. */ switch (info->var.bits_per_pixel) { case 8: - dcfg |= DC_DCFG_DISP_MODE_8BPP; + dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; break; case 16: - dcfg |= DC_DCFG_DISP_MODE_16BPP; - dcfg |= DC_DCFG_16BPP_MODE_565; + dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; break; case 32: - dcfg |= DC_DCFG_DISP_MODE_24BPP; - dcfg |= DC_DCFG_PALB; + dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; + dcfg |= DC_DISPLAY_CFG_PALB; break; } /* Enable timing generator. */ - dcfg |= DC_DCFG_TGEN; + dcfg |= DC_DISPLAY_CFG_TGEN; /* Horizontal and vertical timings. */ hactive = info->var.xres; @@ -148,7 +150,7 @@ static void gx_set_mode(struct fb_info *info) par->vid_ops->configure_display(info); /* Relock display controller registers */ - write_dc(par, DC_UNLOCK, 0); + write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); } static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, |