diff options
Diffstat (limited to 'include/asm-mips')
100 files changed, 640 insertions, 4642 deletions
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index ef33c3f13484..bf55a5b34bef 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h @@ -38,8 +38,10 @@ struct exec #define STACK_TOP TASK_SIZE #endif #ifdef CONFIG_64BIT -#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) +#define STACK_TOP \ + (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) #endif +#define STACK_TOP_MAX TASK_SIZE #endif diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 964c5eddc21b..0b3ff9c48409 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -129,29 +129,12 @@ #define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ ((cm)<<59) | (a)) -#if defined (CONFIG_CPU_R4300) \ - || defined (CONFIG_CPU_R4X00) \ - || defined (CONFIG_CPU_R5000) \ - || defined (CONFIG_CPU_RM7000) \ - || defined (CONFIG_CPU_RM9000) \ - || defined (CONFIG_CPU_NEVADA) \ - || defined (CONFIG_CPU_TX49XX) \ - || defined (CONFIG_CPU_MIPS64) -#define TO_PHYS_MASK _CONST64_(0x0000000fffffffff) /* 2^^36 - 1 */ -#endif - -#if defined (CONFIG_CPU_R8000) -/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ -#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ -#endif - -#if defined (CONFIG_CPU_R10000) -#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ -#endif - -#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) -#define TO_PHYS_MASK _CONST64_(0x00000fffffffffff) /* 2^^44 - 1 */ -#endif +/* + * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * R8000 implements most with its 48-bit physical address space. + */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ #ifndef CONFIG_CPU_R8000 diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 1b60624dab7e..7d8003769a44 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -138,7 +138,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -181,7 +181,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -190,7 +190,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -233,7 +233,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -250,7 +250,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -302,7 +302,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -519,7 +519,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -562,7 +562,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -614,7 +614,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -631,7 +631,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) { unsigned long result; - smp_mb(); + smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long temp; @@ -683,7 +683,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return result; } @@ -791,10 +791,11 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) * atomic*_return operations are serializing but not the non-*_return * versions. */ -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() +#define smp_mb__before_atomic_dec() smp_llsc_mb() +#define smp_mb__after_atomic_dec() smp_llsc_mb() +#define smp_mb__before_atomic_inc() smp_llsc_mb() +#define smp_mb__after_atomic_inc() smp_llsc_mb() #include <asm-generic/atomic.h> + #endif /* _ASM_ATOMIC_H */ diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h index ed82631b0017..9d8cfbb5e796 100644 --- a/include/asm-mips/barrier.h +++ b/include/asm-mips/barrier.h @@ -121,6 +121,11 @@ #else #define __WEAK_ORDERING_MB " \n" #endif +#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) +#define __WEAK_LLSC_MB " sync \n" +#else +#define __WEAK_LLSC_MB " \n" +#endif #define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") #define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") @@ -129,4 +134,8 @@ #define set_mb(var, value) \ do { var = value; smp_mb(); } while (0) +#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") + #endif /* __ASM_BARRIER_H */ diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h index 3646a3f2ed38..0ba9d6ef76a7 100644 --- a/include/asm-mips/bcache.h +++ b/include/asm-mips/bcache.h @@ -21,7 +21,6 @@ struct bcache_ops { }; extern void indy_sc_init(void); -extern void sni_pcimt_sc_init(void); #ifdef CONFIG_BOARD_SCACHE diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index d9e81af53f78..148bc79557f1 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -38,8 +38,8 @@ /* * clear_bit() doesn't provide any barrier for the compiler. */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#define smp_mb__before_clear_bit() smp_llsc_mb() +#define smp_mb__after_clear_bit() smp_llsc_mb() /* * set_bit - Atomically set a bit in memory @@ -289,7 +289,7 @@ static inline int test_and_set_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -377,7 +377,7 @@ static inline int test_and_clear_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } @@ -445,7 +445,7 @@ static inline int test_and_change_bit(unsigned long nr, raw_local_irq_restore(flags); } - smp_mb(); + smp_llsc_mb(); return res != 0; } diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index b0c329783ac5..c0f052b37b9e 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -86,16 +86,6 @@ #define MACH_COBALT_27 0 /* Proto "27" hardware */ /* - * Valid machtype for group NEC DDB - */ -#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ -#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ -#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ -#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ -#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */ -#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */ - -/* * Valid machtype for group BAGET */ #define MACH_GROUP_BAGET 9 /* Baget */ @@ -109,18 +99,12 @@ #define MACH_COSINE_ORION 0 /* - * Valid machtype for group GALILEO - */ -#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ -#define MACH_EV64120A 0 /* EV64120A */ - -/* * Valid machtype for group MOMENCO */ #define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ #define MACH_MOMENCO_OCELOT 0 #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ -#define MACH_MOMENCO_OCELOT_C 2 +#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */ #define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */ #define MACH_MOMENCO_OCELOT_3 4 @@ -151,9 +135,6 @@ #define MACH_TOSHIBA_RBTX4937 5 #define MACH_TOSHIBA_RBTX4938 6 -#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ - "RBTX4927", "RBTX4937" } - /* * Valid machtype for group Alchemy */ @@ -194,13 +175,6 @@ #define MACH_HP_LASERJET 1 /* - * Valid machtype for group LASAT - */ -#define MACH_GROUP_LASAT 21 -#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ -#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ - -/* * Valid machtype for group TITAN */ #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ @@ -213,6 +187,27 @@ #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ +/* + * Valid machtype for group LEMOTE + */ +#define MACH_GROUP_LEMOTE 27 +#define MACH_LEMOTE_FULONG 0 + +/* + * Valid machtype for group PMC-MSP + */ +#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */ +#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ +#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ +#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ +#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ +#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ +#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ +#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ + +#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ +#define MACH_WRPPMC 1 + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index c4a1ec31ff6a..df7f2deb3b56 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -20,7 +20,11 @@ #define Index_Load_Tag_D 0x05 #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else #define Hit_Invalidate_I 0x10 +#endif #define Hit_Invalidate_D 0x11 #define Hit_Writeback_Inv_D 0x15 diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h index 432653d7ae09..568c76cdd900 100644 --- a/include/asm-mips/compat.h +++ b/include/asm-mips/compat.h @@ -37,8 +37,10 @@ typedef s32 compat_key_t; typedef s32 compat_int_t; typedef s32 compat_long_t; +typedef s64 compat_s64; typedef u32 compat_uint_t; typedef u32 compat_ulong_t; +typedef u64 compat_u64; struct compat_timespec { compat_time_t tv_sec; @@ -132,7 +134,8 @@ typedef u32 compat_uptr_t; static inline void __user *compat_ptr(compat_uptr_t uptr) { - return (void __user *)(long)uptr; + /* cast to a __user pointer via "unsigned long" makes sparse happy */ + return (void __user *)(unsigned long)(long)uptr; } static inline compat_uptr_t ptr_to_compat(void __user *uptr) diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h index 169ae26105e9..aa6b876bbd78 100644 --- a/include/asm-mips/compiler.h +++ b/include/asm-mips/compiler.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Maciej W. Rozycki + * Copyright (C) 2004, 2007 Maciej W. Rozycki * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -9,8 +9,10 @@ #define _ASM_COMPILER_H #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) +#define GCC_IMM_ASM "n" #define GCC_REG_ACCUM "$0" #else +#define GCC_IMM_ASM "rn" #define GCC_REG_ACCUM "accum" #endif diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 5e4bed123b48..d95a83e3e1d7 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -150,6 +150,10 @@ #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) #endif +#ifndef cpu_has_userlocal +#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) +#endif + #ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 2924069075e0..3857358fb6de 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -89,6 +89,8 @@ #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -107,6 +109,7 @@ * Definitions for 7:0 on legacy processors */ +#define PRID_REV_MASK 0x00ff #define PRID_REV_TX4927 0x0022 #define PRID_REV_TX4937 0x0030 @@ -123,6 +126,7 @@ #define PRID_REV_VR4122 0x0070 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 +#define PRID_REV_34K_V1_0_2 0x0022 /* * Older processors used to encode processor version and revision in two @@ -211,7 +215,10 @@ #define CPU_SB1A 62 #define CPU_74K 63 #define CPU_R14000 64 -#define CPU_LAST 64 +#define CPU_LOONGSON1 65 +#define CPU_LOONGSON2 66 + +#define CPU_LAST 66 /* * ISA Level encodings @@ -257,6 +264,7 @@ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ /* * CPU ASE encodings diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h deleted file mode 100644 index 6cf177caf6d5..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ /dev/null @@ -1,342 +0,0 @@ -/*********************************************************************** - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * include/asm-mips/ddb5xxx/ddb5477.h - * DDB 5477 specific definitions and macros. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - *********************************************************************** - */ - -#ifndef __ASM_DDB5XXX_DDB5477_H -#define __ASM_DDB5XXX_DDB5477_H - -#include <irq.h> - -/* - * This contains macros that are specific to DDB5477 or renamed from - * DDB5476. - */ - -/* - * renamed PADRs - */ -#define DDB_LCS0 DDB_DCS2 -#define DDB_LCS1 DDB_DCS3 -#define DDB_LCS2 DDB_DCS4 -#define DDB_VRC5477 DDB_INTCS - -/* - * New CPU interface registers - */ -#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ -#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */ -#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */ -#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */ - -#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */ -#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */ -#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */ -#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */ -#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */ -#define DDB_NMISTAT 0x0450 /* NMI Status [R] */ - -#define DDB_INTCLR32 0x0468 /* Interrupt Clear */ - -#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ -#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ - -#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */ -#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */ -#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */ - - -/* - * Timer registers - */ -#define DDB_REFCTRL_L DDB_T0CTRL -#define DDB_REFCTRL_H (DDB_T0CTRL+4) -#define DDB_REFCNTR DDB_T0CNTR -#define DDB_SPT0CTRL_L DDB_T1CTRL -#define DDB_SPT0CTRL_H (DDB_T1CTRL+4) -#define DDB_SPT1CTRL_L DDB_T2CTRL -#define DDB_SPT1CTRL_H (DDB_T2CTRL+4) -#define DDB_SPT1CNTR DDB_T1CTRL -#define DDB_WDTCTRL_L DDB_T3CTRL -#define DDB_WDTCTRL_H (DDB_T3CTRL+4) -#define DDB_WDTCNTR DDB_T3CNTR - -/* - * DMA registers are moved. We don't care about it for now. TODO. - */ - -/* - * BARs for ext PCI (PCI0) - */ -#undef DDB_BARC -#undef DDB_BARB - -#define DDB_BARC0 0x0210 /* PCI0 Control */ -#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */ -#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */ -#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */ -#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */ -#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */ -#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */ -#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */ -#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */ -#define DDB_BARB0 0x0280 /* PCI0 BOOT */ -#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */ -#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */ - -/* - * BARs for IOPIC (PCI1) - */ -#define DDB_BARC1 0x0610 /* PCI1 Control */ -#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */ -#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */ -#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */ -#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */ -#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */ -#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */ -#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */ -#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */ -#define DDB_BARB1 0x0680 /* PCI1 BOOT */ -#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */ -#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */ - -/* - * Other registers for ext PCI (PCI0) - */ -#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */ -#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */ - -#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */ -#define DDB_PCIERR0 0x02b8 /* PCI0 Error */ - -#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ -#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */ -#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */ -#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */ - -/* - * Other registers for IOPCI (PCI1) - */ -#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */ -#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */ - -#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */ -#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */ - -#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */ -#define DDB_PCIERR1 0x06b8 /* PCI1 Error */ - -#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */ -#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */ -#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */ -#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */ - -/* - * Local Bus - */ -#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */ -#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */ -#undef DDB_LCST2 -#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */ -#undef DDB_LCST3 -#undef DDB_LCST4 -#undef DDB_LCST5 -#undef DDB_LCST6 -#undef DDB_LCST7 -#undef DDB_LCST8 -#define DDB_ERRADR 0x0150 /* Error Address Register */ -#define DDB_ERRCS 0x0160 -#define DDB_BTM 0x0170 /* Boot Time Mode value */ - -/* - * MISC registers - */ -#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */ -#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */ - -/* - * Memory map (physical address) - * - * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then - * PCI_IO_BASE must be aligned along 16MB boundary. - */ - -/* the actual ram size is detected at run-time */ -#define DDB_SDRAM_BASE 0x00000000 -#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */ - -#define DDB_PCI0_MEM_BASE 0x08000000 -#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_PCI1_MEM_BASE 0x10000000 -#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_PCI0_CONFIG_BASE 0x18000000 -#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */ - -#define DDB_PCI1_CONFIG_BASE 0x19000000 -#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */ - -#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */ -#define DDB_PCI0_IO_BASE 0x1a000000 -#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */ -#define DDB_PCI1_IO_BASE 0x1b000000 -#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS0_BASE 0x1c000000 /* flash memory */ -#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS1_BASE 0x1d000000 /* misc */ -#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */ - -#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */ -#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */ - -#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */ -#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */ - -#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */ -#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */ - -#define DDB_LED DDB_LCS1_BASE + 0x10000 - - -/* - * DDB5477 specific functions - */ -#ifndef __ASSEMBLY__ -extern void ddb5477_irq_setup(void); - -/* route irq to cpu int pin */ -extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip); - -/* low-level routine for enabling vrc5477 irq, bypassing high-level */ -extern void ll_vrc5477_irq_enable(int vrc5477_irq); -extern void ll_vrc5477_irq_disable(int vrc5477_irq); -#endif /* !__ASSEMBLY__ */ - -/* PCI intr ack share PCIW0 with PCI IO */ -#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE - -/* - * Interrupt mapping - * - * We have three interrupt controllers: - * - * . CPU itself - 8 sources - * . i8259 - 16 sources - * . vrc5477 - 32 sources - * - * They connected as follows: - * all vrc5477 interrupts are routed to cpu IP2 (by software setting) - * all i8359 are routed to INTC in vrc5477 (by hardware connection) - * - * All VRC5477 PCI interrupts are level-triggered (no ack needed). - * All PCI irq but INTC are active low. - */ - -/* - * irq number block assignment - */ - -#define NUM_CPU_IRQ 8 -#define NUM_VRC5477_IRQ 32 - -#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE -#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) - -/* - * vrc5477 irq defs - */ - -#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */ -#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */ -#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */ -#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */ -#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */ -#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */ -#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */ -#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */ -#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */ -#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */ -#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */ -#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */ -#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */ -#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */ -#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */ -#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */ -#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ -#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ -#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ -#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ -#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ -#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ -#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */ -#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */ -#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE) -#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */ -#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */ -#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE) - -/* - * i2859 irq assignment - */ -#define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE) -#define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE) -#define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ -#define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */ -#define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE) -#define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE) -#define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */ -#define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */ -#define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */ -#define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE) -#define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */ -#define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE) -#define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */ -#define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */ - - -/* - * misc - */ -#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE) -#define CPU_VRC5477_CASCADE 2 - -/* - * debug routines - */ -#ifndef __ASSEMBLY__ -#if defined(CONFIG_RUNTIME_DEBUG) -extern void vrc5477_show_pdar_regs(void); -extern void vrc5477_show_pci_regs(void); -extern void vrc5477_show_bar_regs(void); -extern void vrc5477_show_int_regs(void); -extern void vrc5477_show_all_regs(void); -#endif - -/* - * RAM size - */ -extern int board_ram_size; -#endif /* !__ASSEMBLY__ */ - -#endif /* __ASM_DDB5XXX_DDB5477_H */ diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h deleted file mode 100644 index e97fcc8d548b..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5xxx.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * include/asm-mips/ddb5xxx/ddb5xxx.h - * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef __ASM_DDB5XXX_DDB5XXX_H -#define __ASM_DDB5XXX_DDB5XXX_H - -#include <linux/types.h> - -/* - * This file is based on the following documentation: - * - * NEC Vrc 5074 System Controller Data Sheet, June 1998 - * - * [jsun] It is modified so that this file only contains the macros - * that are true for all DDB 5xxx boards. The modification is based on - * - * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke) - * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000 - * - */ - - -#define DDB_BASE 0xbfa00000 -#define DDB_SIZE 0x00200000 /* 2 MB */ - - -/* - * Physical Device Address Registers (PDARs) - */ - -#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ -#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ -#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ -#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ -#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ -#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ -#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ -#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ -#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ -#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ -#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ -#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */ - /* [R/W] */ -#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ -/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */ - -/* - * CPU Interface Registers - */ -#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */ -#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */ -#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ -#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ - /* Enable [R/W] */ -#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ -#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ - - -/* - * Memory-Interface Registers - */ -#define DDB_MEMCTRL 0x00C0 /* Memory Control */ -#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ -#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */ - - -/* - * PCI-Bus Registers - */ -#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */ -#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ -#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ -#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ -#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */ - - -/* - * Local-Bus Registers - */ -#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ -#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ -#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ -#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ -#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ -#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ -#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ -#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ -#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ - /* Enables [R/W] */ -#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ -#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ - - -/* - * DMA Registers - */ -#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ -#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ -#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ -#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ -#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ -#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ - - -/* - * Timer Registers - */ -#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ -#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ -#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ -#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ -#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ -#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ -#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ -#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ - - -/* - * PCI Configuration Space Registers - */ -#define DDB_PCI_BASE 0x0200 - -#define DDB_VID 0x0200 /* PCI Vendor ID [R] */ -#define DDB_DID 0x0202 /* PCI Device ID [R] */ -#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */ -#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */ -#define DDB_REVID 0x0208 /* PCI Revision ID [R] */ -#define DDB_CLASS 0x0209 /* PCI Class Code [R] */ -#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ -#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */ -#define DDB_HTYPE 0x020E /* PCI Header Type [R] */ -#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */ -#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ -#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ -#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ -#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ - /* (unimplemented) */ -#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ -#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */ -#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */ - /* (unimplemented) */ -#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ -#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */ -#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ -#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ -#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ -#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ -#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ -#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ -#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ -#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ -#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ -#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ - - -/* - * Nile 4 Register Access - */ - -static inline void ddb_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void ddb_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u32 ddb_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - -static inline void ddb_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u16 ddb_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - -static inline void ddb_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(DDB_BASE+offset) = val; - ddb_sync(); -} - -static inline u8 ddb_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(DDB_BASE+offset); - ddb_sync(); - return val; -} - - -/* - * Physical Device Address Registers - */ - -extern u32 -ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible); -extern void -ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int pci_visible); - -/* - * PCI Master Registers - */ - -#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ -#define DDB_PCICMD_IO 1 /* PCI I/O Space */ -#define DDB_PCICMD_MEM 3 /* PCI Memory Space */ -#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */ - -/* - * additional options for pci init reg (no shifting needed) - */ -#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */ -#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */ - - -extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options); - -/* - * we need to reset pci bus when we start up and shutdown - */ -extern void ddb_pci_reset_bus(void); - - -/* - * include the board dependent part - */ -#if defined(CONFIG_DDB5477) -#include <asm/ddb5xxx/ddb5477.h> -#else -#error "Unknown DDB board!" -#endif - -#endif /* __ASM_DDB5XXX_DDB5XXX_H */ diff --git a/include/asm-mips/dec/serial.h b/include/asm-mips/dec/serial.h deleted file mode 100644 index acad75890a05..000000000000 --- a/include/asm-mips/dec/serial.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * include/asm-mips/dec/serial.h - * - * Definitions common to all DECstation serial devices. - * - * Copyright (C) 2004 Maciej W. Rozycki - * - * Based on bits extracted from drivers/tc/zs.h for which - * the following copyrights apply: - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) - * Copyright (C) Harald Koerfgen - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_SERIAL_H -#define __ASM_MIPS_DEC_SERIAL_H - -struct dec_serial_hook { - int (*init_channel)(void *handle); - void (*init_info)(void *handle); - void (*rx_char)(unsigned char ch, unsigned char fl); - int (*poll_rx_char)(void *handle); - int (*poll_tx_char)(void *handle, unsigned char ch); - unsigned int cflags; -}; - -extern int register_dec_serial_hook(unsigned int channel, - struct dec_serial_hook *hook); -extern int unregister_dec_serial_hook(unsigned int channel); - -#endif /* __ASM_MIPS_DEC_SERIAL_H */ diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h index 66189f5f6399..716371bd0980 100644 --- a/include/asm-mips/div64.h +++ b/include/asm-mips/div64.h @@ -20,7 +20,7 @@ */ #define do_div64_32(res, high, low, base) ({ \ - unsigned long __quot, __mod; \ + unsigned long __quot32, __mod32; \ unsigned long __cf, __tmp, __tmp2, __i; \ \ __asm__(".set push\n\t" \ @@ -48,12 +48,13 @@ "bnez %4, 0b\n\t" \ " srl %5, %1, 0x1f\n\t" \ ".set pop" \ - : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \ + : "=&r" (__mod32), "=&r" (__tmp), \ + "=&r" (__quot32), "=&r" (__cf), \ "=&r" (__i), "=&r" (__tmp2) \ : "Jr" (base), "0" (high), "1" (low)); \ \ - (res) = __quot; \ - __mod; }) + (res) = __quot32; \ + __mod32; }) #define do_div(n, base) ({ \ unsigned long long __quot; \ diff --git a/include/asm-mips/ds1216.h b/include/asm-mips/ds1216.h deleted file mode 100644 index 1ff8b73f7a6a..000000000000 --- a/include/asm-mips/ds1216.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _DS1216_H -#define _DS1216_H - -extern volatile unsigned char *ds1216_base; -unsigned long ds1216_get_cmos_time(void); -int ds1216_set_rtc_mmss(unsigned long nowtime); - -#define DS1216_SEC_BYTE 1 -#define DS1216_MIN_BYTE 2 -#define DS1216_HOUR_BYTE 3 -#define DS1216_HOUR_MASK (0x1f) -#define DS1216_AMPM_MASK (1<<5) -#define DS1216_1224_MASK (1<<7) -#define DS1216_DAY_BYTE 4 -#define DS1216_DAY_MASK (0x7) -#define DS1216_DATE_BYTE 5 -#define DS1216_DATE_MASK (0x3f) -#define DS1216_MONTH_BYTE 6 -#define DS1216_MONTH_MASK (0x1f) -#define DS1216_YEAR_BYTE 7 - -#define DS1216_SEC(buf) (buf[DS1216_SEC_BYTE]) -#define DS1216_MIN(buf) (buf[DS1216_MIN_BYTE]) -#define DS1216_HOUR(buf) (buf[DS1216_HOUR_BYTE] & DS1216_HOUR_MASK) -#define DS1216_AMPM(buf) (buf[DS1216_HOUR_BYTE] & DS1216_AMPM_MASK) -#define DS1216_1224(buf) (buf[DS1216_HOUR_BYTE] & DS1216_1224_MASK) -#define DS1216_DATE(buf) (buf[DS1216_DATE_BYTE] & DS1216_DATE_MASK) -#define DS1216_MONTH(buf) (buf[DS1216_MONTH_BYTE] & DS1216_MONTH_MASK) -#define DS1216_YEAR(buf) (buf[DS1216_YEAR_BYTE]) - -#endif diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index ebd6bfb19d66..e7d95d48177d 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -265,7 +265,7 @@ do { \ #ifdef CONFIG_MIPS32_N32 #define __SET_PERSONALITY32_N32() \ do { \ - current->thread.mflags |= MF_N32; \ + set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_n32; \ } while (0) #else @@ -276,7 +276,8 @@ do { \ #ifdef CONFIG_MIPS32_O32 #define __SET_PERSONALITY32_O32() \ do { \ - current->thread.mflags |= MF_O32; \ + set_thread_flag(TIF_32BIT_REGS); \ + set_thread_flag(TIF_32BIT_ADDR); \ current->thread.abi = &mips_abi_32; \ } while (0) #else @@ -299,13 +300,13 @@ do { \ #define SET_PERSONALITY(ex, ibcs2) \ do { \ - current->thread.mflags &= ~MF_ABI_MASK; \ + clear_thread_flag(TIF_32BIT_REGS); \ + clear_thread_flag(TIF_32BIT_ADDR); \ + \ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ __SET_PERSONALITY32(ex); \ - else { \ - current->thread.mflags |= MF_N64; \ + else \ current->thread.abi = &mips_abi; \ - } \ \ if (ibcs2) \ set_personality(PER_SVR4); \ diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h index 00a50ec1c19f..2a52333a062d 100644 --- a/include/asm-mips/fcntl.h +++ b/include/asm-mips/fcntl.h @@ -13,6 +13,7 @@ #define O_SYNC 0x0010 #define O_NONBLOCK 0x0080 #define O_CREAT 0x0100 /* not fcntl */ +#define O_TRUNC 0x0200 /* not fcntl */ #define O_EXCL 0x0400 /* not fcntl */ #define O_NOCTTY 0x0800 /* not fcntl */ #define FASYNC 0x1000 /* fcntl, for BSD compatibility */ diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index 47e5679c2353..b623882bce19 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h @@ -29,7 +29,7 @@ " .set mips3 \n" \ "2: sc $1, %2 \n" \ " beqzl $1, 1b \n" \ - __WEAK_ORDERING_MB \ + __WEAK_LLSC_MB \ "3: \n" \ " .set pop \n" \ " .set mips0 \n" \ @@ -55,7 +55,7 @@ " .set mips3 \n" \ "2: sc $1, %2 \n" \ " beqz $1, 1b \n" \ - __WEAK_ORDERING_MB \ + __WEAK_LLSC_MB \ "3: \n" \ " .set pop \n" \ " .set mips0 \n" \ @@ -152,7 +152,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set mips3 \n" "2: sc $1, %1 \n" " beqzl $1, 1b \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" @@ -179,7 +179,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) " .set mips3 \n" "2: sc $1, %1 \n" " beqz $1, 1b \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB "3: \n" " .set pop \n" " .section .fixup,\"ax\" \n" diff --git a/include/asm-mips/gfx.h b/include/asm-mips/gfx.h deleted file mode 100644 index 37235e41a6fd..000000000000 --- a/include/asm-mips/gfx.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This is the user-visible SGI GFX interface. - * - * This must be used verbatim into the GNU libc. It does not include - * any kernel-only bits on it. - * - * miguel@nuclecu.unam.mx - */ -#ifndef _ASM_GFX_H -#define _ASM_GFX_H - -/* The iocls, yes, they do not make sense, but such is life */ -#define GFX_BASE 100 -#define GFX_GETNUM_BOARDS (GFX_BASE + 1) -#define GFX_GETBOARD_INFO (GFX_BASE + 2) -#define GFX_ATTACH_BOARD (GFX_BASE + 3) -#define GFX_DETACH_BOARD (GFX_BASE + 4) -#define GFX_IS_MANAGED (GFX_BASE + 5) - -#define GFX_MAPALL (GFX_BASE + 10) -#define GFX_LABEL (GFX_BASE + 11) - -#define GFX_INFO_NAME_SIZE 16 -#define GFX_INFO_LABEL_SIZE 16 - -struct gfx_info { - char name [GFX_INFO_NAME_SIZE]; /* board name */ - char label [GFX_INFO_LABEL_SIZE]; /* label name */ - unsigned short int xpmax, ypmax; /* screen resolution */ - unsigned int lenght; /* size of a complete gfx_info for this board */ -}; - -struct gfx_getboardinfo_args { - unsigned int board; /* board number. starting from zero */ - void *buf; /* pointer to gfx_info */ - unsigned int len; /* buffer size of buf */ -}; - -struct gfx_attach_board_args { - unsigned int board; /* board number, starting from zero */ - void *vaddr; /* address where the board registers should be mapped */ -}; - -#ifdef __KERNEL__ -/* umap.c */ -extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long); -extern void *vmalloc_uncached (unsigned long size); -extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr); -#endif - -#endif /* _ASM_GFX_H */ diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h deleted file mode 100644 index 8f9bd341ed49..000000000000 --- a/include/asm-mips/gt64240.h +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright - Galileo technology. - * Copyright (C) 2004 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MV64240_H -#define __ASM_MIPS_MV64240_H - -#include <asm/addrspace.h> -#include <asm/marvell.h> - -/* - * CPU Control Registers - */ - -#define CPU_CONFIGURATION 0x000 -#define CPU_MODE 0x120 -#define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170 -#define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178 - -/* - * Processor Address Space - */ - -/* Sdram's BAR'S */ -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 -/* Devices BAR'S */ -#define CS_0_LOW_DECODE_ADDRESS 0x028 -#define CS_0_HIGH_DECODE_ADDRESS 0x030 -#define CS_1_LOW_DECODE_ADDRESS 0x228 -#define CS_1_HIGH_DECODE_ADDRESS 0x230 -#define CS_2_LOW_DECODE_ADDRESS 0x248 -#define CS_2_HIGH_DECODE_ADDRESS 0x250 -#define CS_3_LOW_DECODE_ADDRESS 0x038 -#define CS_3_HIGH_DECODE_ADDRESS 0x040 -#define BOOTCS_LOW_DECODE_ADDRESS 0x238 -#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 - -#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 -#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 -#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 -#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 -#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 -#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 -#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 -#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 -#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 -#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 - -#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 -#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 -#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 -#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 -#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 -#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 -#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 -#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 -#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 -#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 - -#define INTERNAL_SPACE_DECODE 0x068 - -#define CPU_0_LOW_DECODE_ADDRESS 0x290 -#define CPU_0_HIGH_DECODE_ADDRESS 0x298 -#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 -#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 - -#define PCI_0I_O_ADDRESS_REMAP 0x0f0 -#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 -#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 -#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 -#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 -#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 -#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 -#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 -#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 - -#define PCI_1I_O_ADDRESS_REMAP 0x108 -#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 -#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 -#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 -#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 -#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 -#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 -#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 -#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - -/* - * CPU Sync Barrier - */ - -#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 -#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 - - -/* - * CPU Access Protect - */ - -#define CPU_LOW_PROTECT_ADDRESS_0 0X180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0X188 -#define CPU_LOW_PROTECT_ADDRESS_1 0X190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0X198 -#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8 -#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8 - - -/* - * Snoop Control - */ - -#define SNOOP_BASE_ADDRESS_0 0x380 -#define SNOOP_TOP_ADDRESS_0 0x388 -#define SNOOP_BASE_ADDRESS_1 0x390 -#define SNOOP_TOP_ADDRESS_1 0x398 -#define SNOOP_BASE_ADDRESS_2 0x3a0 -#define SNOOP_TOP_ADDRESS_2 0x3a8 -#define SNOOP_BASE_ADDRESS_3 0x3b0 -#define SNOOP_TOP_ADDRESS_3 0x3b8 - -/* - * CPU Error Report - */ - -#define CPU_ERROR_ADDRESS_LOW 0x070 -#define CPU_ERROR_ADDRESS_HIGH 0x078 -#define CPU_ERROR_DATA_LOW 0x128 -#define CPU_ERROR_DATA_HIGH 0x130 -#define CPU_ERROR_PARITY 0x138 -#define CPU_ERROR_CAUSE 0x140 -#define CPU_ERROR_MASK 0x148 - -/* - * Pslave Debug - */ - -#define X_0_ADDRESS 0x360 -#define X_0_COMMAND_ID 0x368 -#define X_1_ADDRESS 0x370 -#define X_1_COMMAND_ID 0x378 -#define WRITE_DATA_LOW 0x3c0 -#define WRITE_DATA_HIGH 0x3c8 -#define WRITE_BYTE_ENABLE 0X3e0 -#define READ_DATA_LOW 0x3d0 -#define READ_DATA_HIGH 0x3d8 -#define READ_ID 0x3e8 - - -/* - * SDRAM and Device Address Space - */ - - -/* - * SDRAM Configuration - */ - -#define SDRAM_CONFIGURATION 0x448 -#define SDRAM_OPERATION_MODE 0x474 -#define SDRAM_ADDRESS_DECODE 0x47C -#define SDRAM_TIMING_PARAMETERS 0x4b4 -#define SDRAM_UMA_CONTROL 0x4a4 -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac -#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 - - -/* - * SDRAM Parameters - */ - -#define SDRAM_BANK0PARAMETERS 0x44C -#define SDRAM_BANK1PARAMETERS 0x450 -#define SDRAM_BANK2PARAMETERS 0x454 -#define SDRAM_BANK3PARAMETERS 0x458 - - -/* - * SDRAM Error Report - */ - -#define SDRAM_ERROR_DATA_LOW 0x484 -#define SDRAM_ERROR_DATA_HIGH 0x480 -#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 -#define SDRAM_RECEIVED_ECC 0x488 -#define SDRAM_CALCULATED_ECC 0x48c -#define SDRAM_ECC_CONTROL 0x494 -#define SDRAM_ECC_ERROR_COUNTER 0x498 - - -/* - * SDunit Debug (for internal use) - */ - -#define X0_ADDRESS 0x500 -#define X0_COMMAND_AND_ID 0x504 -#define X0_WRITE_DATA_LOW 0x508 -#define X0_WRITE_DATA_HIGH 0x50c -#define X0_WRITE_BYTE_ENABLE 0x518 -#define X0_READ_DATA_LOW 0x510 -#define X0_READ_DATA_HIGH 0x514 -#define X0_READ_ID 0x51c -#define X1_ADDRESS 0x520 -#define X1_COMMAND_AND_ID 0x524 -#define X1_WRITE_DATA_LOW 0x528 -#define X1_WRITE_DATA_HIGH 0x52c -#define X1_WRITE_BYTE_ENABLE 0x538 -#define X1_READ_DATA_LOW 0x530 -#define X1_READ_DATA_HIGH 0x534 -#define X1_READ_ID 0x53c -#define X0_SNOOP_ADDRESS 0x540 -#define X0_SNOOP_COMMAND 0x544 -#define X1_SNOOP_ADDRESS 0x548 -#define X1_SNOOP_COMMAND 0x54c - - -/* - * Device Parameters - */ - -#define DEVICE_BANK0PARAMETERS 0x45c -#define DEVICE_BANK1PARAMETERS 0x460 -#define DEVICE_BANK2PARAMETERS 0x464 -#define DEVICE_BANK3PARAMETERS 0x468 -#define DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define DEVICE_CONTROL 0x4c0 -#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 - - -/* - * Device Interrupt - */ - -#define DEVICE_INTERRUPT_CAUSE 0x4d0 -#define DEVICE_INTERRUPT_MASK 0x4d4 -#define DEVICE_ERROR_ADDRESS 0x4d8 - -/* - * DMA Record - */ - -#define CHANNEL0_DMA_BYTE_COUNT 0x800 -#define CHANNEL1_DMA_BYTE_COUNT 0x804 -#define CHANNEL2_DMA_BYTE_COUNT 0x808 -#define CHANNEL3_DMA_BYTE_COUNT 0x80C -#define CHANNEL4_DMA_BYTE_COUNT 0x900 -#define CHANNEL5_DMA_BYTE_COUNT 0x904 -#define CHANNEL6_DMA_BYTE_COUNT 0x908 -#define CHANNEL7_DMA_BYTE_COUNT 0x90C -#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 -#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 -#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 -#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C -#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 -#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 -#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 -#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C -#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 -#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 -#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 -#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C -#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 -#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 -#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 -#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C -#define CHANNEL0NEXT_RECORD_POINTER 0x830 -#define CHANNEL1NEXT_RECORD_POINTER 0x834 -#define CHANNEL2NEXT_RECORD_POINTER 0x838 -#define CHANNEL3NEXT_RECORD_POINTER 0x83C -#define CHANNEL4NEXT_RECORD_POINTER 0x930 -#define CHANNEL5NEXT_RECORD_POINTER 0x934 -#define CHANNEL6NEXT_RECORD_POINTER 0x938 -#define CHANNEL7NEXT_RECORD_POINTER 0x93C -#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 -#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 -#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 -#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C -#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 -#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 -#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 -#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C -#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 -#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 -#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 -#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c -#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 -#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 -#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 -#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c -#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 -#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 -#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 -#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac -#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 -#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 -#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 -#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac -#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 -#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 -#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 -#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc -#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 -#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 -#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 -#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc - -/* - * DMA Channel Control - */ - -#define CHANNEL0CONTROL 0x840 -#define CHANNEL0CONTROL_HIGH 0x880 - -#define CHANNEL1CONTROL 0x844 -#define CHANNEL1CONTROL_HIGH 0x884 - -#define CHANNEL2CONTROL 0x848 -#define CHANNEL2CONTROL_HIGH 0x888 - -#define CHANNEL3CONTROL 0x84C -#define CHANNEL3CONTROL_HIGH 0x88C - -#define CHANNEL4CONTROL 0x940 -#define CHANNEL4CONTROL_HIGH 0x980 - -#define CHANNEL5CONTROL 0x944 -#define CHANNEL5CONTROL_HIGH 0x984 - -#define CHANNEL6CONTROL 0x948 -#define CHANNEL6CONTROL_HIGH 0x988 - -#define CHANNEL7CONTROL 0x94C -#define CHANNEL7CONTROL_HIGH 0x98C - - -/* - * DMA Arbiter - */ - -#define ARBITER_CONTROL_0_3 0x860 -#define ARBITER_CONTROL_4_7 0x960 - - -/* - * DMA Interrupt - */ - -#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 -#define CHANELS0_3_INTERRUPT_MASK 0x8c4 -#define CHANELS0_3_ERROR_ADDRESS 0x8c8 -#define CHANELS0_3_ERROR_SELECT 0x8cc -#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 -#define CHANELS4_7_INTERRUPT_MASK 0x9c4 -#define CHANELS4_7_ERROR_ADDRESS 0x9c8 -#define CHANELS4_7_ERROR_SELECT 0x9cc - - -/* - * DMA Debug (for internal use) - */ - -#define DMA_X0_ADDRESS 0x8e0 -#define DMA_X0_COMMAND_AND_ID 0x8e4 -#define DMA_X0_WRITE_DATA_LOW 0x8e8 -#define DMA_X0_WRITE_DATA_HIGH 0x8ec -#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 -#define DMA_X0_READ_DATA_LOW 0x8f0 -#define DMA_X0_READ_DATA_HIGH 0x8f4 -#define DMA_X0_READ_ID 0x8fc -#define DMA_X1_ADDRESS 0x9e0 -#define DMA_X1_COMMAND_AND_ID 0x9e4 -#define DMA_X1_WRITE_DATA_LOW 0x9e8 -#define DMA_X1_WRITE_DATA_HIGH 0x9ec -#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 -#define DMA_X1_READ_DATA_LOW 0x9f0 -#define DMA_X1_READ_DATA_HIGH 0x9f4 -#define DMA_X1_READ_ID 0x9fc - -/* - * Timer_Counter - */ - -#define TIMER_COUNTER0 0x850 -#define TIMER_COUNTER1 0x854 -#define TIMER_COUNTER2 0x858 -#define TIMER_COUNTER3 0x85C -#define TIMER_COUNTER_0_3_CONTROL 0x864 -#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c -#define TIMER_COUNTER4 0x950 -#define TIMER_COUNTER5 0x954 -#define TIMER_COUNTER6 0x958 -#define TIMER_COUNTER7 0x95C -#define TIMER_COUNTER_4_7_CONTROL 0x964 -#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 -#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c - -/* - * PCI Slave Address Decoding - */ - -#define PCI_0SCS_0_BANK_SIZE 0xc08 -#define PCI_1SCS_0_BANK_SIZE 0xc88 -#define PCI_0SCS_1_BANK_SIZE 0xd08 -#define PCI_1SCS_1_BANK_SIZE 0xd88 -#define PCI_0SCS_2_BANK_SIZE 0xc0c -#define PCI_1SCS_2_BANK_SIZE 0xc8c -#define PCI_0SCS_3_BANK_SIZE 0xd0c -#define PCI_1SCS_3_BANK_SIZE 0xd8c -#define PCI_0CS_0_BANK_SIZE 0xc10 -#define PCI_1CS_0_BANK_SIZE 0xc90 -#define PCI_0CS_1_BANK_SIZE 0xd10 -#define PCI_1CS_1_BANK_SIZE 0xd90 -#define PCI_0CS_2_BANK_SIZE 0xd18 -#define PCI_1CS_2_BANK_SIZE 0xd98 -#define PCI_0CS_3_BANK_SIZE 0xc14 -#define PCI_1CS_3_BANK_SIZE 0xc94 -#define PCI_0CS_BOOT_BANK_SIZE 0xd14 -#define PCI_1CS_BOOT_BANK_SIZE 0xd94 -#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c -#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c -#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 -#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 -#define PCI_0P2P_I_O_BAR_SIZE 0xd24 -#define PCI_1P2P_I_O_BAR_SIZE 0xda4 -#define PCI_0CPU_BAR_SIZE 0xd28 -#define PCI_1CPU_BAR_SIZE 0xda8 -#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 -#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 -#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 -#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 -#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 -#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 -#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c -#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c -#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 -#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 -#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 -#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 -#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 -#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 -#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c -#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c -#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 -#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 -#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 -#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 -#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 -#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 -#define PCI_0DAC_CPU_BAR_SIZE 0xe2c -#define PCI_1DAC_CPU_BAR_SIZE 0xeac -#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c -#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac -#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c -#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc -#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 -#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 -#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 -#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 -#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c -#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc -#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c -#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc -#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 -#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 -#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 -#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 -#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 -#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 -#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 -#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 -#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 -#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 -#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c -#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec -#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 -#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 -#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 -#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 -#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 -#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 -#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 -#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 -#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c -#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c -#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 -#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 -#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 -#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 -#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 -#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 -#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c -#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c -#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 -#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 -#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 -#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 -#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 -#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 -#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c -#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc - -/* - * PCI Control - */ - -#define PCI_0COMMAND 0xc00 -#define PCI_1COMMAND 0xc80 -#define PCI_0MODE 0xd00 -#define PCI_1MODE 0xd80 -#define PCI_0TIMEOUT_RETRY 0xc04 -#define PCI_1TIMEOUT_RETRY 0xc84 -#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 -#define MSI_0TRIGGER_TIMER 0xc38 -#define MSI_1TRIGGER_TIMER 0xcb8 -#define PCI_0ARBITER_CONTROL 0x1d00 -#define PCI_1ARBITER_CONTROL 0x1d80 -/* changing untill here */ -#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c -#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 -#define PCI_0P2P_CONFIGURATION 0x1d14 -#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10 -#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20 -#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30 -#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40 -#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50 -#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60 -#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 -#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70 -#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 -#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 -#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c -#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 -#define PCI_1P2P_CONFIGURATION 0x1d94 -#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90 -#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0 -#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0 -#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0 -#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0 -#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0 -#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 -#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0 -#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 -#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 - -/* - * PCI Snoop Control - */ - -#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 -#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 -#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 -#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 -#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 -#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 -#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 -#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 -#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 -#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 -#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 -#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 -#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 -#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 -#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 -#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 -#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 -#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 -#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 -#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 -#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 -#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 -#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 -#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 - -/* - * PCI Configuration Address - */ - -#define PCI_0CONFIGURATION_ADDRESS 0xcf8 -#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc -#define PCI_1CONFIGURATION_ADDRESS 0xc78 -#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c -#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 -#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 - -/* - * PCI Error Report - */ - -#define PCI_0SERR_MASK 0xc28 -#define PCI_0ERROR_ADDRESS_LOW 0x1d40 -#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 -#define PCI_0ERROR_DATA_LOW 0x1d48 -#define PCI_0ERROR_DATA_HIGH 0x1d4c -#define PCI_0ERROR_COMMAND 0x1d50 -#define PCI_0ERROR_CAUSE 0x1d58 -#define PCI_0ERROR_MASK 0x1d5c - -#define PCI_1SERR_MASK 0xca8 -#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 -#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 -#define PCI_1ERROR_DATA_LOW 0x1dc8 -#define PCI_1ERROR_DATA_HIGH 0x1dcc -#define PCI_1ERROR_COMMAND 0x1dd0 -#define PCI_1ERROR_CAUSE 0x1dd8 -#define PCI_1ERROR_MASK 0x1ddc - - -/* - * Lslave Debug (for internal use) - */ - -#define L_SLAVE_X0_ADDRESS 0x1d20 -#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 -#define L_SLAVE_X1_ADDRESS 0x1d28 -#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c -#define L_SLAVE_WRITE_DATA_LOW 0x1d30 -#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 -#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 -#define L_SLAVE_READ_DATA_LOW 0x1d38 -#define L_SLAVE_READ_DATA_HIGH 0x1d3c -#define L_SLAVE_READ_ID 0x1d64 - -#if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */ - -/* - * PCI Configuration Function 0 - */ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0X04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/* - * PCI Configuration Function 1 - */ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/* - * PCI Configuration Function 2 - */ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 -#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 -#define PCI_CPU_BASE_ADDRESS 0x21c - -/* - * PCI Configuration Function 4 - */ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/* - * PCI Configuration Function 5 - */ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/* - * PCI Configuration Function 6 - */ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/* - * PCI Configuration Function 7 - */ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 -#endif - -/* - * Interrupts - */ - -#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 -#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 -#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c -#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c -#define CPU_SELECT_CAUSE_REGISTER 0xc70 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 -#define PCI_0SELECT_CAUSE 0xc74 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 -#define PCI_1SELECT_CAUSE 0xcf4 -#define CPU_INT_0_MASK 0xe60 -#define CPU_INT_1_MASK 0xe64 -#define CPU_INT_2_MASK 0xe68 -#define CPU_INT_3_MASK 0xe6c - -/* - * I20 Support registers - */ - -#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C -#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC - -#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090 -#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094 -#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098 -#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C -#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8 -#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4 -#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C - -#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C -#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44 -#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC - -#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90 -#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94 -#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98 -#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C -#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8 -#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4 -#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C - -/* - * Communication Unit Registers - */ - -#define ETHERNET_0_ADDRESS_CONTROL_LOW -#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 -#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 -#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c -#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 -#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 -#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 -#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 -#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 -#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 -#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c -#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 -#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 -#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 -#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 -#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 -#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 -#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c -#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 -#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 -#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 -#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 -#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 -#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 -#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c -#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 -#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4 -#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 -#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 -#define SERIAL_INIT_LAST_DATA 0xf324 -#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 -#define COMM_UNIT_ARBITER_CONTROL 0xf300 -#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 -#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 -#define COMM_UNIT_INTERRUPT_MASK 0xf314 -#define COMM_UNIT_ERROR_ADDRESS 0xf314 - -/* - * Cunit Debug (for internal use) - */ - -#define CUNIT_ADDRESS 0xf340 -#define CUNIT_COMMAND_AND_ID 0xf344 -#define CUNIT_WRITE_DATA_LOW 0xf348 -#define CUNIT_WRITE_DATA_HIGH 0xf34c -#define CUNIT_WRITE_BYTE_ENABLE 0xf358 -#define CUNIT_READ_DATA_LOW 0xf350 -#define CUNIT_READ_DATA_HIGH 0xf354 -#define CUNIT_READ_ID 0xf35c - -/* - * Fast Ethernet Unit Registers - */ - -/* Ethernet */ - -#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 -#define ETHERNET_SMI_REGISTER 0x2010 - -/* Ethernet 0 */ - -#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 -#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 -#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 -#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 -#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 -#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 -#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 -#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 -#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 -#define ETHERNET0_MIB_COUNTER_BASE 0x2500 - -/* Ethernet 1 */ - -#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 -#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 -#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 -#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 -#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 -#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 -#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 -#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 -#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 -#define ETHERNET1_MIB_COUNTER_BASE 0x2900 - -/* Ethernet 2 */ - -#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 -#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 -#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 -#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 -#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 -#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 -#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 -#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 -#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 -#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 - -/* - * SDMA Registers - */ - -#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 -#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 -#define CHANNEL0_COMMAND_REGISTER 0x4008 -#define CHANNEL0_RX_CMD_STATUS 0x4800 -#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 -#define CHANNEL0_RX_BUFFER_POINTER 0x4808 -#define CHANNEL0_RX_NEXT_POINTER 0x480c -#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 -#define CHANNEL0_TX_CMD_STATUS 0x4C00 -#define CHANNEL0_TX_PACKET_SIZE 0x4C04 -#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 -#define CHANNEL0_TX_NEXT_POINTER 0x4C0c -#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 -#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 -#define CHANNEL1_CONFIGURATION_REGISTER 0x6000 -#define CHANNEL1_COMMAND_REGISTER 0x6008 -#define CHANNEL1_RX_CMD_STATUS 0x6800 -#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804 -#define CHANNEL1_RX_BUFFER_POINTER 0x6808 -#define CHANNEL1_RX_NEXT_POINTER 0x680c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL1_TX_CMD_STATUS 0x6C00 -#define CHANNEL1_TX_PACKET_SIZE 0x6C04 -#define CHANNEL1_TX_BUFFER_POINTER 0x6C08 -#define CHANNEL1_TX_NEXT_POINTER 0x6C0c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 -#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 - -/* SDMA Interrupt */ - -#define SDMA_CAUSE 0xb820 -#define SDMA_MASK 0xb8a0 - - -/* - * Baude Rate Generators Registers - */ - -/* BRG 0 */ - -#define BRG0_CONFIGURATION_REGISTER 0xb200 -#define BRG0_BAUDE_TUNING_REGISTER 0xb204 - -/* BRG 1 */ - -#define BRG1_CONFIGURATION_REGISTER 0xb208 -#define BRG1_BAUDE_TUNING_REGISTER 0xb20c - -/* BRG 2 */ - -#define BRG2_CONFIGURATION_REGISTER 0xb210 -#define BRG2_BAUDE_TUNING_REGISTER 0xb214 - -/* BRG Interrupts */ - -#define BRG_CAUSE_REGISTER 0xb834 -#define BRG_MASK_REGISTER 0xb8b4 - -/* MISC */ - -#define MAIN_ROUTING_REGISTER 0xb400 -#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 -#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 -#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c -#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 -#define WATCHDOG_VALUE_REGISTER 0xb414 - - -/* - * Flex TDM Registers - */ - -/* FTDM Port */ - -#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 -#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 -#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 -#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c -#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 -#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 -#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 - -/* FTDM Interrupts */ - -#define FTDM_CAUSE_REGISTER 0xb830 -#define FTDM_MASK_REGISTER 0xb8b0 - - -/* - * GPP Interface Registers - */ - -#define GPP_IO_CONTROL 0xf100 -#define GPP_LEVEL_CONTROL 0xf110 -#define GPP_VALUE 0xf104 -#define GPP_INTERRUPT_CAUSE 0xf108 -#define GPP_INTERRUPT_MASK 0xf10c - -#define MPP_CONTROL0 0xf000 -#define MPP_CONTROL1 0xf004 -#define MPP_CONTROL2 0xf008 -#define MPP_CONTROL3 0xf00c -#define DEBUG_PORT_MULTIPLEX 0xf014 -#define SERIAL_PORT_MULTIPLEX 0xf010 - -/* - * I2C Registers - */ - -#define I2C_SLAVE_ADDRESS 0xc000 -#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 -#define I2C_DATA 0xc004 -#define I2C_CONTROL 0xc008 -#define I2C_STATUS_BAUDE_RATE 0xc00C -#define I2C_SOFT_RESET 0xc01c - -/* - * MPSC Registers - */ - -/* - * MPSC0 - */ - -#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 -#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 -#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 -#define CHANNEL0_REGISTER1 0x800c -#define CHANNEL0_REGISTER2 0x8010 -#define CHANNEL0_REGISTER3 0x8014 -#define CHANNEL0_REGISTER4 0x8018 -#define CHANNEL0_REGISTER5 0x801c -#define CHANNEL0_REGISTER6 0x8020 -#define CHANNEL0_REGISTER7 0x8024 -#define CHANNEL0_REGISTER8 0x8028 -#define CHANNEL0_REGISTER9 0x802c -#define CHANNEL0_REGISTER10 0x8030 -#define CHANNEL0_REGISTER11 0x8034 - -/* - * MPSC1 - */ - -#define MPSC1_MAIN_CONFIGURATION_LOW 0x9000 -#define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004 -#define MPSC1_PROTOCOL_CONFIGURATION 0x9008 -#define CHANNEL1_REGISTER1 0x900c -#define CHANNEL1_REGISTER2 0x9010 -#define CHANNEL1_REGISTER3 0x9014 -#define CHANNEL1_REGISTER4 0x9018 -#define CHANNEL1_REGISTER5 0x901c -#define CHANNEL1_REGISTER6 0x9020 -#define CHANNEL1_REGISTER7 0x9024 -#define CHANNEL1_REGISTER8 0x9028 -#define CHANNEL1_REGISTER9 0x902c -#define CHANNEL1_REGISTER10 0x9030 -#define CHANNEL1_REGISTER11 0x9034 - -/* - * MPSCs Interupts - */ - -#define MPSC0_CAUSE 0xb804 -#define MPSC0_MASK 0xb884 -#define MPSC1_CAUSE 0xb80c -#define MPSC1_MASK 0xb88c - -#endif /* __ASM_MIPS_MV64240_H */ diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index d9119f43f9aa..6a5fa32f615b 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org> + * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org> * Copyright (C) MIPS Technologies, Inc. * written by Ralf Baechle <ralf@linux-mips.org> */ @@ -23,6 +23,11 @@ static inline void name(void) \ __asm__ __volatile__ (#name); \ } +/* + * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. + */ +extern void mips_ihb(void); + #endif ASMMACRO(_ssnop, @@ -167,6 +172,7 @@ ASMMACRO(tlb_probe_hazard, nop; nop; nop ) ASMMACRO(irq_enable_hazard, + _ssnop; _ssnop; _ssnop; ) ASMMACRO(irq_disable_hazard, nop; nop; nop diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 92ec2618560c..7ba92890ea13 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -178,6 +178,11 @@ extern void __iounmap(const volatile void __iomem *addr); static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, unsigned long flags) { + void __iomem *addr = plat_ioremap(offset, size, flags); + + if (addr) + return addr; + #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) if (cpu_has_64bit_addresses) { @@ -207,7 +212,8 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, */ if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && flags == _CACHE_UNCACHED) - return (void __iomem *)CKSEG1ADDR(phys_addr); + return (void __iomem *) + (unsigned long)CKSEG1ADDR(phys_addr); } return __ioremap(offset, size, flags); @@ -282,6 +288,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, static inline void iounmap(const volatile void __iomem *addr) { + if (plat_iounmap(addr)) + return; + #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) if (cpu_has_64bit_addresses || diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h index 92f6c36aac4d..5097cbf183a9 100644 --- a/include/asm-mips/ioctls.h +++ b/include/asm-mips/ioctls.h @@ -77,6 +77,10 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x7416 /* Return the session ID of FD */ +#define TCGETS2 _IOR('T',0x2A, struct termios2) +#define TCSETS2 _IOW('T',0x2B, struct termios2) +#define TCSETSW2 _IOW('T',0x2C, struct termios2) +#define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 3ca6a076124d..2cb52cf8bd4e 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -25,6 +25,29 @@ static inline int irq_canonicalize(int irq) #endif #ifdef CONFIG_MIPS_MT_SMTC + +struct irqaction; + +extern unsigned long irq_hwmask[]; +extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, + unsigned long hwmask); + +static inline void smtc_im_ack_irq(unsigned int irq) +{ + if (irq_hwmask[irq] & ST0_IM) + set_c0_status(irq_hwmask[irq] & ST0_IM); +} + +#else + +static inline void smtc_im_ack_irq(unsigned int irq) +{ +} + +#endif /* CONFIG_MIPS_MT_SMTC */ + +#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP + /* * Clear interrupt mask handling "backstop" if irq_hwmask * entry so indicates. This implies that the ack() or end() @@ -38,6 +61,7 @@ do { \ ~(irq_hwmask[irq] & 0x0000ff00)); \ } while (0) #else + #define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) #endif @@ -60,14 +84,6 @@ do { \ extern void arch_init_irq(void); extern void spurious_interrupt(void); -#ifdef CONFIG_MIPS_MT_SMTC -struct irqaction; - -extern unsigned long irq_hwmask[]; -extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, - unsigned long hwmask); -#endif /* CONFIG_MIPS_MT_SMTC */ - extern int allocate_irqno(void); extern void alloc_legacy_irqno(void); extern void free_irqno(unsigned int irq); diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h index 958e29706e2d..b2dc35f56181 100644 --- a/include/asm-mips/jmr3927/jmr3927.h +++ b/include/asm-mips/jmr3927/jmr3927.h @@ -13,6 +13,7 @@ #include <asm/jmr3927/tx3927.h> #include <asm/addrspace.h> #include <asm/system.h> +#include <asm/txx9irq.h> /* CS */ #define JMR3927_ROMCE0 0x1fc00000 /* 4M */ @@ -115,7 +116,7 @@ #define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ #define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ -#define JMR3927_IRQ_IRC 16 +#define JMR3927_IRQ_IRC TXX9_IRQ_BASE #define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) #define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h index 0b9073bfb759..4be2f25f70dd 100644 --- a/include/asm-mips/jmr3927/tx3927.h +++ b/include/asm-mips/jmr3927/tx3927.h @@ -50,21 +50,6 @@ struct tx3927_dma_reg { volatile unsigned long unused0; }; -struct tx3927_irc_reg { - volatile unsigned long cer; - volatile unsigned long cr[2]; - volatile unsigned long unused0; - volatile unsigned long ilr[8]; - volatile unsigned long unused1[4]; - volatile unsigned long imr; - volatile unsigned long unused2[7]; - volatile unsigned long scr; - volatile unsigned long unused3[7]; - volatile unsigned long ssr; - volatile unsigned long unused4[7]; - volatile unsigned long csr; -}; - #include <asm/byteorder.h> #ifdef __BIG_ENDIAN @@ -225,26 +210,6 @@ struct tx3927_ccfg_reg { /* * IRC */ -#define TX3927_IR_MAX_LEVEL 7 - -/* IRCER : Int. Control Enable */ -#define TX3927_IRCER_ICE 0x00000001 - -/* IRCR : Int. Control */ -#define TX3927_IRCR_LOW 0x00000000 -#define TX3927_IRCR_HIGH 0x00000001 -#define TX3927_IRCR_DOWN 0x00000002 -#define TX3927_IRCR_UP 0x00000003 - -/* IRSCR : Int. Status Control */ -#define TX3927_IRSCR_EIClrE 0x00000100 -#define TX3927_IRSCR_EIClr_MASK 0x0000000f - -/* IRCSR : Int. Current Status */ -#define TX3927_IRCSR_IF 0x00010000 -#define TX3927_IRCSR_ILV_MASK 0x00000700 -#define TX3927_IRCSR_IVL_MASK 0x0000001f - #define TX3927_IR_INT0 0 #define TX3927_IR_INT1 1 #define TX3927_IR_INT2 2 @@ -347,7 +312,6 @@ struct tx3927_ccfg_reg { #define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) #define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) #define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) -#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG) #define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) #define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) #define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h deleted file mode 100644 index edcd7544b358..000000000000 --- a/include/asm-mips/lasat/ds1603.h +++ /dev/null @@ -1,18 +0,0 @@ -#include <asm/addrspace.h> - -/* Lasat 100 */ -#define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) -#define DS1603_RST_100 (1 << 2) -#define DS1603_CLK_100 (1 << 0) -#define DS1603_DATA_SHIFT_100 1 -#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) - -/* Lasat 200 */ -#define DS1603_REG_200 (KSEG1ADDR(0x11000000)) -#define DS1603_RST_200 (1 << 3) -#define DS1603_CLK_200 (1 << 4) -#define DS1603_DATA_200 (1 << 5) - -#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) -#define DS1603_DATA_READ_SHIFT_200 9 -#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h deleted file mode 100644 index 7b53edd5cd5f..000000000000 --- a/include/asm-mips/lasat/eeprom.h +++ /dev/null @@ -1,17 +0,0 @@ -#include <asm/addrspace.h> - -/* lasat 100 */ -#define AT93C_REG_100 KSEG1ADDR(0x1c810000) -#define AT93C_RDATA_REG_100 AT93C_REG_100 -#define AT93C_RDATA_SHIFT_100 4 -#define AT93C_WDATA_SHIFT_100 4 -#define AT93C_CS_M_100 ( 1 << 5 ) -#define AT93C_CLK_M_100 ( 1 << 3 ) - -/* lasat 200 */ -#define AT93C_REG_200 KSEG1ADDR(0x11000000) -#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) -#define AT93C_RDATA_SHIFT_200 8 -#define AT93C_WDATA_SHIFT_200 2 -#define AT93C_CS_M_200 ( 1 << 0 ) -#define AT93C_CLK_M_200 ( 1 << 1 ) diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h deleted file mode 100644 index f5589f31a197..000000000000 --- a/include/asm-mips/lasat/head.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Image header stuff - */ -#ifndef _HEAD_H -#define _HEAD_H - -#define LASAT_K_MAGIC0_VAL 0xfedeabba -#define LASAT_K_MAGIC1_VAL 0x00bedead - -#ifndef _LANGUAGE_ASSEMBLY -#include <linux/types.h> -struct bootloader_header { - u32 magic[2]; - u32 version; - u32 image_start; - u32 image_size; - u32 kernel_start; - u32 kernel_entry; -}; -#endif - -#endif /* _HEAD_H */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h deleted file mode 100644 index 42077e367a5b..000000000000 --- a/include/asm-mips/lasat/lasat.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * lasat.h - * - * Thomas Horsten <thh@lasat.com> - * Copyright (C) 2000 LASAT Networks A/S. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Configuration for LASAT boards, loads the appropriate include files. - */ -#ifndef _LASAT_H -#define _LASAT_H - -#ifndef _LANGUAGE_ASSEMBLY - -extern struct lasat_misc { - volatile u32 *reset_reg; - volatile u32 *flash_wp_reg; - u32 flash_wp_bit; -} *lasat_misc; - -enum lasat_mtdparts { - LASAT_MTD_BOOTLOADER, - LASAT_MTD_SERVICE, - LASAT_MTD_NORMAL, - LASAT_MTD_CONFIG, - LASAT_MTD_FS, - LASAT_MTD_LAST -}; - -/* - * The format of the data record in the EEPROM. - * See Documentation/LASAT/eeprom.txt for a detailed description - * of the fields in this struct, and the LASAT Hardware Configuration - * field specification for a detailed description of the config - * field. - */ -#include <linux/types.h> - -#define LASAT_EEPROM_VERSION 7 -struct lasat_eeprom_struct { - unsigned int version; - unsigned int cfg[3]; - unsigned char hwaddr[6]; - unsigned char print_partno[12]; - unsigned char term0; - unsigned char print_serial[14]; - unsigned char term1; - unsigned char prod_partno[12]; - unsigned char term2; - unsigned char prod_serial[14]; - unsigned char term3; - unsigned char passwd_hash[16]; - unsigned char pwdnull; - unsigned char vendid; - unsigned char ts_ref; - unsigned char ts_signoff; - unsigned char reserved[11]; - unsigned char debugaccess; - unsigned short prid; - unsigned int serviceflag; - unsigned int ipaddr; - unsigned int netmask; - unsigned int crc32; -}; - -struct lasat_eeprom_struct_pre7 { - unsigned int version; - unsigned int flags[3]; - unsigned char hwaddr0[6]; - unsigned char hwaddr1[6]; - unsigned char print_partno[9]; - unsigned char term0; - unsigned char print_serial[14]; - unsigned char term1; - unsigned char prod_partno[9]; - unsigned char term2; - unsigned char prod_serial[14]; - unsigned char term3; - unsigned char passwd_hash[24]; - unsigned char pwdnull; - unsigned char vendor; - unsigned char ts_ref; - unsigned char ts_signoff; - unsigned char reserved[6]; - unsigned int writecount; - unsigned int ipaddr; - unsigned int netmask; - unsigned int crc32; -}; - -/* Configuration descriptor encoding - see the doc for details */ - -#define LASAT_W0_DSCTYPE(v) ( ( (v) ) & 0xf ) -#define LASAT_W0_BMID(v) ( ( (v) >> 0x04 ) & 0xf ) -#define LASAT_W0_CPUTYPE(v) ( ( (v) >> 0x08 ) & 0xf ) -#define LASAT_W0_BUSSPEED(v) ( ( (v) >> 0x0c ) & 0xf ) -#define LASAT_W0_CPUCLK(v) ( ( (v) >> 0x10 ) & 0xf ) -#define LASAT_W0_SDRAMBANKSZ(v) ( ( (v) >> 0x14 ) & 0xf ) -#define LASAT_W0_SDRAMBANKS(v) ( ( (v) >> 0x18 ) & 0xf ) -#define LASAT_W0_L2CACHE(v) ( ( (v) >> 0x1c ) & 0xf ) - -#define LASAT_W1_EDHAC(v) ( ( (v) ) & 0xf ) -#define LASAT_W1_HIFN(v) ( ( (v) >> 0x04 ) & 0x1 ) -#define LASAT_W1_ISDN(v) ( ( (v) >> 0x05 ) & 0x1 ) -#define LASAT_W1_IDE(v) ( ( (v) >> 0x06 ) & 0x1 ) -#define LASAT_W1_HDLC(v) ( ( (v) >> 0x07 ) & 0x1 ) -#define LASAT_W1_USVERSION(v) ( ( (v) >> 0x08 ) & 0x1 ) -#define LASAT_W1_4MACS(v) ( ( (v) >> 0x09 ) & 0x1 ) -#define LASAT_W1_EXTSERIAL(v) ( ( (v) >> 0x0a ) & 0x1 ) -#define LASAT_W1_FLASHSIZE(v) ( ( (v) >> 0x0c ) & 0xf ) -#define LASAT_W1_PCISLOTS(v) ( ( (v) >> 0x10 ) & 0xf ) -#define LASAT_W1_PCI1OPT(v) ( ( (v) >> 0x14 ) & 0xf ) -#define LASAT_W1_PCI2OPT(v) ( ( (v) >> 0x18 ) & 0xf ) -#define LASAT_W1_PCI3OPT(v) ( ( (v) >> 0x1c ) & 0xf ) - -/* Routines specific to LASAT boards */ - -#define LASAT_BMID_MASQUERADE2 0 -#define LASAT_BMID_MASQUERADEPRO 1 -#define LASAT_BMID_SAFEPIPE25 2 -#define LASAT_BMID_SAFEPIPE50 3 -#define LASAT_BMID_SAFEPIPE100 4 -#define LASAT_BMID_SAFEPIPE5000 5 -#define LASAT_BMID_SAFEPIPE7000 6 -#define LASAT_BMID_SAFEPIPE1000 7 -//#define LASAT_BMID_SAFEPIPE30 7 -//#define LASAT_BMID_SAFEPIPE5100 8 -//#define LASAT_BMID_SAFEPIPE7100 9 -#define LASAT_BMID_UNKNOWN 0xf -#define LASAT_MAX_BMID_NAMES 9 // no larger than 15! - -#define LASAT_HAS_EDHAC ( 1 << 0 ) -#define LASAT_EDHAC_FAST ( 1 << 1 ) -#define LASAT_HAS_EADI ( 1 << 2 ) -#define LASAT_HAS_HIFN ( 1 << 3 ) -#define LASAT_HAS_ISDN ( 1 << 4 ) -#define LASAT_HAS_LEASEDLINE_IF ( 1 << 5 ) -#define LASAT_HAS_HDC ( 1 << 6 ) - -#define LASAT_PRID_MASQUERADE2 0 -#define LASAT_PRID_MASQUERADEPRO 1 -#define LASAT_PRID_SAFEPIPE25 2 -#define LASAT_PRID_SAFEPIPE50 3 -#define LASAT_PRID_SAFEPIPE100 4 -#define LASAT_PRID_SAFEPIPE5000 5 -#define LASAT_PRID_SAFEPIPE7000 6 -#define LASAT_PRID_SAFEPIPE30 7 -#define LASAT_PRID_SAFEPIPE5100 8 -#define LASAT_PRID_SAFEPIPE7100 9 - -#define LASAT_PRID_SAFEPIPE1110 10 -#define LASAT_PRID_SAFEPIPE3020 11 -#define LASAT_PRID_SAFEPIPE3030 12 -#define LASAT_PRID_SAFEPIPE5020 13 -#define LASAT_PRID_SAFEPIPE5030 14 -#define LASAT_PRID_SAFEPIPE1120 15 -#define LASAT_PRID_SAFEPIPE1130 16 -#define LASAT_PRID_SAFEPIPE6010 17 -#define LASAT_PRID_SAFEPIPE6110 18 -#define LASAT_PRID_SAFEPIPE6210 19 -#define LASAT_PRID_SAFEPIPE1020 20 -#define LASAT_PRID_SAFEPIPE1040 21 -#define LASAT_PRID_SAFEPIPE1060 22 - -struct lasat_info { - unsigned int li_cpu_hz; - unsigned int li_bus_hz; - unsigned int li_bmid; - unsigned int li_memsize; - unsigned int li_flash_size; - unsigned int li_prid; - unsigned char li_bmstr[16]; - unsigned char li_namestr[32]; - unsigned char li_typestr[16]; - /* Info on the Flash layout */ - unsigned int li_flash_base; - unsigned long li_flashpart_base[LASAT_MTD_LAST]; - unsigned long li_flashpart_size[LASAT_MTD_LAST]; - struct lasat_eeprom_struct li_eeprom_info; - unsigned int li_eeprom_upgrade_version; - unsigned int li_debugaccess; -}; - -extern struct lasat_info lasat_board_info; - -static inline unsigned long lasat_flash_partition_start(int partno) -{ - if (partno < 0 || partno >= LASAT_MTD_LAST) - return 0; - - return lasat_board_info.li_flashpart_base[partno]; -} - -static inline unsigned long lasat_flash_partition_size(int partno) -{ - if (partno < 0 || partno >= LASAT_MTD_LAST) - return 0; - - return lasat_board_info.li_flashpart_size[partno]; -} - -/* Called from setup() to initialize the global board_info struct */ -extern int lasat_init_board_info(void); - -/* Write the modified EEPROM info struct */ -extern void lasat_write_eeprom_info(void); - -#define N_MACHTYPES 2 -/* for calibration of delays */ - -/* the lasat_ndelay function is necessary because it is used at an - * early stage of the boot process where ndelay is not calibrated. - * It is used for the bit-banging rtc and eeprom drivers */ - -#include <asm/delay.h> -/* calculating with the slowest board with 100 MHz clock */ -#define LASAT_100_DIVIDER 20 -/* All 200's run at 250 MHz clock */ -#define LASAT_200_DIVIDER 8 - -extern unsigned int lasat_ndelay_divider; - -static inline void lasat_ndelay(unsigned int ns) -{ - __delay(ns / lasat_ndelay_divider); -} - -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ - -#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef -#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba - -/* Lasat 100 boards */ -#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) - -/* Lasat 200 boards */ -#define Vrc5074_PHYS_BASE 0x1fa00000 -#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) -#define PCI_WINDOW1 0x1a000000 - -#endif /* _LASAT_H */ diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h deleted file mode 100644 index 065474feeccc..000000000000 --- a/include/asm-mips/lasat/lasatint.h +++ /dev/null @@ -1,12 +0,0 @@ -#define LASATINT_END 16 - -/* lasat 100 */ -#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) -#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) -#define LASATINT_MASK_SHIFT_100 0 - -/* lasat 200 */ -#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) -#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) -#define LASATINT_MASK_SHIFT_200 16 - diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h deleted file mode 100644 index 42a492edc40e..000000000000 --- a/include/asm-mips/lasat/picvue.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Lasat 100 */ -#define PVC_REG_100 KSEG1ADDR(0x1c820000) -#define PVC_DATA_SHIFT_100 0 -#define PVC_DATA_M_100 0xFF -#define PVC_E_100 (1 << 8) -#define PVC_RW_100 (1 << 9) -#define PVC_RS_100 (1 << 10) - -/* Lasat 200 */ -#define PVC_REG_200 KSEG1ADDR(0x11000000) -#define PVC_DATA_SHIFT_200 24 -#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) -#define PVC_E_200 (1 << 16) -#define PVC_RW_200 (1 << 17) -#define PVC_RS_200 (1 << 18) diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h deleted file mode 100644 index 9e88c7669c7a..000000000000 --- a/include/asm-mips/lasat/serial.h +++ /dev/null @@ -1,13 +0,0 @@ -#include <asm/lasat/lasat.h> - -/* Lasat 100 boards serial configuration */ -#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) -#define LASAT_UART_REGS_BASE_100 0x1c8b0000 -#define LASAT_UART_REGS_SHIFT_100 2 -#define LASATINT_UART_100 8 - -/* * LASAT 200 boards serial configuration */ -#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) -#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) -#define LASAT_UART_REGS_SHIFT_200 3 -#define LASATINT_UART_200 13 diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h index ed882c88e0ca..f9a5ce5c9af1 100644 --- a/include/asm-mips/local.h +++ b/include/asm-mips/local.h @@ -4,6 +4,7 @@ #include <linux/percpu.h> #include <linux/bitops.h> #include <asm/atomic.h> +#include <asm/cmpxchg.h> #include <asm/war.h> typedef struct @@ -114,68 +115,6 @@ static __inline__ long local_sub_return(long i, local_t * l) return result; } -/* - * local_sub_if_positive - conditionally subtract integer from atomic variable - * @i: integer value to subtract - * @l: pointer of type local_t - * - * Atomically test @l and subtract @i if @l is greater or equal than @i. - * The function returns the old value of @l minus @i. - */ -static __inline__ long local_sub_if_positive(long i, local_t * l) -{ - unsigned long result; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_sub_if_positive\n" - " dsubu %0, %1, %3 \n" - " bltz %0, 1f \n" - __SC "%0, %2 \n" - " .set noreorder \n" - " beqzl %0, 1b \n" - " dsubu %0, %1, %3 \n" - " .set reorder \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else if (cpu_has_llsc) { - unsigned long temp; - - __asm__ __volatile__( - " .set mips3 \n" - "1:" __LL "%1, %2 # local_sub_if_positive\n" - " dsubu %0, %1, %3 \n" - " bltz %0, 1f \n" - __SC "%0, %2 \n" - " .set noreorder \n" - " beqz %0, 1b \n" - " dsubu %0, %1, %3 \n" - " .set reorder \n" - "1: \n" - " .set mips0 \n" - : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) - : "Ir" (i), "m" (l->a.counter) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - result = l->a.counter; - result -= i; - if (result >= 0) - l->a.counter = result; - local_irq_restore(flags); - } - - return result; -} - #define local_cmpxchg(l, o, n) \ ((long)cmpxchg_local(&((l)->a.counter), (o), (n))) #define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n))) @@ -234,12 +173,6 @@ static __inline__ long local_sub_if_positive(long i, local_t * l) #define local_dec_and_test(l) (local_sub_return(1, (l)) == 0) /* - * local_dec_if_positive - decrement by 1 if old value positive - * @l: pointer of type local_t - */ -#define local_dec_if_positive(l) local_sub_if_positive(1, l) - -/* * local_add_negative - add and test if negative * @l: pointer of type local_t * @i: integer value to add diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h deleted file mode 100644 index 27911e054ffc..000000000000 --- a/include/asm-mips/mach-au1x00/au1xxx_gpio.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __AU1XXX_GPIO_H -#define __AU1XXX_GPIO_H - -void au1xxx_gpio1_set_inputs(void); -void au1xxx_gpio_tristate(int signal); -void au1xxx_gpio_write(int signal, int value); -int au1xxx_gpio_read(int signal); - -typedef volatile struct -{ - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; - -} AU1X00_GPIO2; - -#endif //__AU1XXX_GPIO_H diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h index 8fcae21adbd5..4663e8b415c9 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -88,26 +88,26 @@ static const struct drive_list_entry dma_white_list [] = { /* * Hitachi */ - { "HITACHI_DK14FA-20" , "ALL" }, - { "HTS726060M9AT00" , "ALL" }, + { "HITACHI_DK14FA-20" , NULL }, + { "HTS726060M9AT00" , NULL }, /* * Maxtor */ - { "Maxtor 6E040L0" , "ALL" }, - { "Maxtor 6Y080P0" , "ALL" }, - { "Maxtor 6Y160P0" , "ALL" }, + { "Maxtor 6E040L0" , NULL }, + { "Maxtor 6Y080P0" , NULL }, + { "Maxtor 6Y160P0" , NULL }, /* * Seagate */ - { "ST3120026A" , "ALL" }, - { "ST320014A" , "ALL" }, - { "ST94011A" , "ALL" }, - { "ST340016A" , "ALL" }, + { "ST3120026A" , NULL }, + { "ST320014A" , NULL }, + { "ST94011A" , NULL }, + { "ST340016A" , NULL }, /* * Western Digital */ - { "WDC WD400UE-00HCT0" , "ALL" }, - { "WDC WD400JB-00JJC0" , "ALL" }, + { "WDC WD400UE-00HCT0" , NULL }, + { "WDC WD400JB-00JJC0" , NULL }, { NULL , NULL } }; @@ -116,9 +116,9 @@ static const struct drive_list_entry dma_black_list [] = { /* * Western Digital */ - { "WDC WD100EB-00CGH0" , "ALL" }, - { "WDC WD200BB-00AUA1" , "ALL" }, - { "WDC AC24300L" , "ALL" }, + { "WDC WD100EB-00CGH0" , NULL }, + { "WDC WD200BB-00AUA1" , NULL }, + { "WDC AC24300L" , NULL }, { NULL , NULL } }; #endif diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h index 098fca4289bb..364cea2dc71f 100644 --- a/include/asm-mips/mach-au1x00/ioremap.h +++ b/include/asm-mips/mach-au1x00/ioremap.h @@ -28,4 +28,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) return __fixup_bigphys_addr(phys_addr, size); } +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} + #endif /* __ASM_MACH_AU1X00_IOREMAP_H */ diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 684a501c04cf..9c9d2b998ca4 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -30,7 +30,6 @@ #define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE #define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) -#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ #define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) #define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) #define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) @@ -71,10 +70,6 @@ extern int cobalt_board_id; -#define PCI_CFG_SET(devfn,where) \ - GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \ - (PCI_FUNC (devfn) << 8) | (where))) - #define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) # define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ # define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h index c6dfa59d1986..d38f069d9e95 100644 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H @@ -46,6 +46,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h deleted file mode 100644 index 7e272ce57ea3..000000000000 --- a/include/asm-mips/mach-ev64120/mach-gt64120.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H -#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H - -/* - * GT64120 config space base address - */ -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -/* - * Duart I/O ports. - */ -#define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20) -#define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00) - - -/* - * EV64120 interrupt controller register base. - */ -#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) - -/* - * EV64120 UART register base. - */ -#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) -#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) -#define EV64120_BASE_BAUD ( 3686400 / 16 ) -#define EV64120_UART_IRQ 6 - -/* - * PCI interrupts will come in on either the INTA or INTD interrups lines, - * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our - * boards, they all either come in on IntD or they all come in on IntA, they - * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the - * "requested" interrupt numbers and go through the list whenever we get an - * IntA/D. - * - * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and - * INTD is 11. - */ -#define GT_TIMER 4 -#define GT_INTA 2 -#define GT_INTD 5 - -#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */ diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index 0d31854222f9..07f4322c235d 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -4,6 +4,7 @@ * for more details. * * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H @@ -27,6 +28,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h index 6eba2e576aaa..a77128362a7d 100644 --- a/include/asm-mips/mach-generic/ide.h +++ b/include/asm-mips/mach-generic/ide.h @@ -33,13 +33,24 @@ static __inline__ int ide_probe_legacy(void) { #ifdef CONFIG_PCI struct pci_dev *dev; - if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL || - (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) { - pci_dev_put(dev); - - return 1; - } + /* + * This can be called on the ide_setup() path, super-early in + * boot. But the down_read() will enable local interrupts, + * which can cause some machines to crash. So here we detect + * and flag that situation and bail out early. + */ + if (no_pci_devices()) + return 0; + dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL); + if (dev) + goto found; + dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); + if (dev) + goto found; return 0; +found: + pci_dev_put(dev); + return 1; #elif defined(CONFIG_EISA) || defined(CONFIG_ISA) return 1; #else @@ -49,48 +60,42 @@ static __inline__ int ide_probe_legacy(void) static __inline__ int ide_default_irq(unsigned long base) { - if (ide_probe_legacy()) - switch (base) { - case 0x1f0: - return 14; - case 0x170: - return 15; - case 0x1e8: - return 11; - case 0x168: - return 10; - case 0x1e0: - return 8; - case 0x160: - return 12; + switch (base) { + case 0x1f0: return 14; + case 0x170: return 15; + case 0x1e8: return 11; + case 0x168: return 10; + case 0x1e0: return 8; + case 0x160: return 12; default: return 0; - } - else - return 0; + } } static __inline__ unsigned long ide_default_io_base(int index) { - if (ide_probe_legacy()) + if (!ide_probe_legacy()) + return 0; + /* + * If PCI is present then it is not safe to poke around + * the other legacy IDE ports. Only 0x1f0 and 0x170 are + * defined compatibility mode ports for PCI. A user can + * override this using ide= but we must default safe. + */ + if (no_pci_devices()) { switch (index) { - case 0: - return 0x1f0; - case 1: - return 0x170; - case 2: - return 0x1e8; - case 3: - return 0x168; - case 4: - return 0x1e0; - case 5: - return 0x160; - default: - return 0; + case 2: return 0x1e8; + case 3: return 0x168; + case 4: return 0x1e0; + case 5: return 0x160; } - else + } + switch (index) { + case 0: return 0x1f0; + case 1: return 0x170; + default: return 0; + } } #define IDE_ARCH_OBSOLETE_INIT diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h index 9b64ff6e485d..b379938d47f0 100644 --- a/include/asm-mips/mach-generic/ioremap.h +++ b/include/asm-mips/mach-generic/ioremap.h @@ -20,4 +20,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) return phys_addr; } +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} + #endif /* __ASM_MACH_GENERIC_IOREMAP_H */ diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h index 0ae9997bc9a8..c9fa4b14968d 100644 --- a/include/asm-mips/mach-generic/spaces.h +++ b/include/asm-mips/mach-generic/spaces.h @@ -10,38 +10,54 @@ #ifndef _ASM_MACH_GENERIC_SPACES_H #define _ASM_MACH_GENERIC_SPACES_H +#include <linux/const.h> + +/* + * This gives the physical RAM offset. + */ +#ifndef PHYS_OFFSET +#define PHYS_OFFSET _AC(0, UL) +#endif #ifdef CONFIG_32BIT -#define CAC_BASE 0x80000000 -#define IO_BASE 0xa0000000 -#define UNCAC_BASE 0xa0000000 -#define MAP_BASE 0xc0000000 +#define CAC_BASE _AC(0x80000000, UL) +#define IO_BASE _AC(0xa0000000, UL) +#define UNCAC_BASE _AC(0xa0000000, UL) -/* - * This handles the memory map. - * We handle pages at KSEG0 for kernels with 32 bit address space. - */ -#define PAGE_OFFSET 0x80000000UL +#ifndef MAP_BASE +#define MAP_BASE _AC(0xc0000000, UL) +#endif /* * Memory above this physical address will be considered highmem. */ #ifndef HIGHMEM_START -#define HIGHMEM_START 0x20000000UL +#define HIGHMEM_START _AC(0x20000000, UL) #endif #endif /* CONFIG_32BIT */ #ifdef CONFIG_64BIT -/* - * This handles the memory map. - */ +#ifndef CAC_BASE #ifdef CONFIG_DMA_NONCOHERENT -#define PAGE_OFFSET 0x9800000000000000UL +#define CAC_BASE _AC(0x9800000000000000, UL) #else -#define PAGE_OFFSET 0xa800000000000000UL +#define CAC_BASE _AC(0xa800000000000000, UL) +#endif +#endif + +#ifndef IO_BASE +#define IO_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef UNCAC_BASE +#define UNCAC_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef MAP_BASE +#define MAP_BASE _AC(0xc000000000000000, UL) #endif /* @@ -50,22 +66,20 @@ * in the distant future. Nobody will care for a few years :-) */ #ifndef HIGHMEM_START -#define HIGHMEM_START (1UL << 59UL) +#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) #endif -#ifdef CONFIG_DMA_NONCOHERENT -#define CAC_BASE 0x9800000000000000UL -#else -#define CAC_BASE 0xa800000000000000UL -#endif -#define IO_BASE 0x9000000000000000UL -#define UNCAC_BASE 0x9000000000000000UL -#define MAP_BASE 0xc000000000000000UL - #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) #endif /* CONFIG_64BIT */ +/* + * This handles the memory map. + */ +#ifndef PAGE_OFFSET +#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) +#endif + #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h index f7c5dc8a5336..9c8735158da1 100644 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 Ralf Baechle + * Copyright (C) 2003, 07 Ralf Baechle */ #ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H @@ -30,6 +30,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h index ab20c026fd19..7f9fa6f66059 100644 --- a/include/asm-mips/mach-ip22/spaces.h +++ b/include/asm-mips/mach-ip22/spaces.h @@ -11,44 +11,17 @@ #define _ASM_MACH_IP22_SPACES_H -#ifdef CONFIG_32BIT - -#define CAC_BASE 0x80000000 -#define IO_BASE 0xa0000000 -#define UNCAC_BASE 0xa0000000 -#define MAP_BASE 0xc0000000 - -/* - * This handles the memory map. - * We handle pages at KSEG0 for kernels with 32 bit address space. - */ -#define PAGE_OFFSET 0x80000000UL - -/* - * Memory above this physical address will be considered highmem. - */ -#ifndef HIGHMEM_START -#define HIGHMEM_START 0x20000000UL -#endif - -#endif /* CONFIG_32BIT */ - #ifdef CONFIG_64BIT -#define PAGE_OFFSET 0xffffffff80000000UL -#ifndef HIGHMEM_START -#define HIGHMEM_START (1UL << 59UL) -#endif +#define PAGE_OFFSET 0xffffffff80000000UL #define CAC_BASE 0xffffffff80000000 #define IO_BASE 0xffffffffa0000000 #define UNCAC_BASE 0xffffffffa0000000 #define MAP_BASE 0xc000000000000000 -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) - #endif /* CONFIG_64BIT */ +#include <asm/mach-generic/spaces.h> + #endif /* __ASM_MACH_IP22_SPACES_H */ diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h index a071974b67bb..fe076380c189 100644 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 Ralf Baechle + * Copyright (C) 2003, 07 Ralf Baechle */ #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H @@ -27,6 +27,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 #define cpu_icache_snoops_remote_store 1 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h index 45e61785ef42..b18802a0b17e 100644 --- a/include/asm-mips/mach-ip27/spaces.h +++ b/include/asm-mips/mach-ip27/spaces.h @@ -14,22 +14,17 @@ * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects * uncached memory addressing. */ -#define CAC_BASE 0xa800000000000000 #define HSPEC_BASE 0x9000000000000000 #define IO_BASE 0x9200000000000000 #define MSPEC_BASE 0x9400000000000000 #define UNCAC_BASE 0x9600000000000000 -#define MAP_BASE 0xc000000000000000 -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) #define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) -#define PAGE_OFFSET CAC_BASE - #define HIGHMEM_START (~0UL) +#include <asm/mach-generic/spaces.h> + #endif /* _ASM_MACH_IP27_SPACES_H */ diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index 2a3de092bf13..6782fccebe8d 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 2005 Ilya A. Volynets-Evenbakh - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H @@ -38,6 +38,8 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 #define cpu_has_4k_cache 1 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_mips32r1 0 diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h deleted file mode 100644 index 44abe5c02389..000000000000 --- a/include/asm-mips/mach-ip32/spaces.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03, 04, 05 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_MACH_IP32_SPACES_H -#define _ASM_MACH_IP32_SPACES_H - -/* - * Memory above this physical address will be considered highmem. - * Fixme: 59 bits is a fictive number and makes assumptions about processors - * in the distant future. Nobody will care for a few years :-) - */ -#ifndef HIGHMEM_START -#define HIGHMEM_START (1UL << 59UL) -#endif - -#define CAC_BASE 0x9800000000000000UL -#define IO_BASE 0x9000000000000000UL -#define UNCAC_BASE 0x9000000000000000UL -#define MAP_BASE 0xc000000000000000UL - -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) - -/* - * This handles the memory map. - */ -#define PAGE_OFFSET CAC_BASE - -#endif /* __ASM_MACH_IP32_SPACES_H */ diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h deleted file mode 100644 index 1a9ad45cc135..000000000000 --- a/include/asm-mips/mach-lasat/mach-gt64120.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H -#define _ASM_GT64120_LASAT_GT64120_DEP_H - -/* - * GT64120 config space base address on Lasat 100 - */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) - -/* - * PCI Bus allocation - * - * (Guessing ...) - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-ocelot/mach-gt64120.h b/include/asm-mips/mach-ocelot/mach-gt64120.h deleted file mode 100644 index a62ecb53c751..000000000000 --- a/include/asm-mips/mach-ocelot/mach-gt64120.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H -#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H - -/* - * PCI address allocation - */ -#define GT_PCI_MEM_BASE (0x22000000UL) -#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE -#define GT_PCI_IO_BASE (0x20000000UL) -#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE - -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* - * GT timer irq - */ -#define GT_TIMER 6 - -#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h deleted file mode 100644 index 57a12ded0613..000000000000 --- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * Copyright (C) 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H - -/* - * Momentum Ocelot-3 is based on Rm7900 processor which - * is based on the E9000 core. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h index 529445dacedb..d2daaed235d5 100644 --- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h +++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 Ralf Baechle + * Copyright (C) 2003, 07 Ralf Baechle */ #ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H @@ -24,6 +24,7 @@ #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 0 diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h index 7e07283140a3..ccf543363537 100644 --- a/include/asm-mips/mach-rm/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) * * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors. */ @@ -32,6 +32,8 @@ #define cpu_has_dsp 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index a25968f277a2..63d5bf649af1 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H @@ -26,6 +26,8 @@ #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h deleted file mode 100644 index 779b02205737..000000000000 --- a/include/asm-mips/mach-sim/cpu-feature-overrides.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Chris Dearman - */ -#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H - - -/* - * CPU feature overrides for MIPS boards - */ -#ifdef CONFIG_CPU_MIPS32 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -#define cpu_has_fpu 0 -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#define cpu_has_llsc 1 -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#endif - -#ifdef CONFIG_CPU_MIPS64 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#define cpu_has_llsc 1 -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#endif - -#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h index 42cebb7ce7a6..470e5e9e10d6 100644 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) */ #ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H @@ -26,6 +26,8 @@ #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 #define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h deleted file mode 100644 index b6144bafc565..000000000000 --- a/include/asm-mips/marvell.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MARVELL_H -#define __ASM_MIPS_MARVELL_H - -#include <linux/pci.h> - -#include <asm/byteorder.h> - -extern unsigned long marvell_base; - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ -#define __MV_READ(ofs) \ - (*(volatile u32 *)(marvell_base+(ofs))) -#define __MV_WRITE(ofs, data) \ - do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0) - -#define MV_READ(ofs) le32_to_cpu(__MV_READ(ofs)) -#define MV_WRITE(ofs, data) __MV_WRITE(ofs, cpu_to_le32(data)) - -#define MV_READ_16(ofs) \ - le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs))) -#define MV_WRITE_16(ofs, data) \ - *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data) - -#define MV_READ_8(ofs) \ - *(volatile u8 *)(marvell_base+(ofs)) -#define MV_WRITE_8(ofs, data) \ - *(volatile u8 *)(marvell_base+(ofs)) = data - -#define MV_SET_REG_BITS(ofs, bits) \ - (*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits)) -#define MV_RESET_REG_BITS(ofs, bits) \ - (*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits)) - -extern struct pci_ops mv_pci_ops; - -struct mv_pci_controller { - struct pci_controller pcic; - - /* - * GT-64240/MV-64340 specific, per host bus information - */ - unsigned long config_addr; - unsigned long config_vreg; -}; - -extern void ll_mv64340_irq(void); -extern void mv64340_irq_init(unsigned int base); - -#endif /* __ASM_MIPS_MARVELL_H */ diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h index cd7125610100..dc3fc32eedd8 100644 --- a/include/asm-mips/mips-boards/bonito64.h +++ b/include/asm-mips/mips-boards/bonito64.h @@ -26,7 +26,12 @@ /* offsets from base register */ #define BONITO(x) (x) -#else /* !__ASSEMBLY__ */ +#elif defined(CONFIG_LEMOTE_FULONG) + +#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) +#define BONITO_IRQ_BASE 32 + +#else /* * Algorithmics Bonito64 system controller register base. diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index c8ebcc3e1267..d58977483534 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -67,6 +67,7 @@ #define MIPS_REVISION_CORID_CORE_FPGAR2 8 #define MIPS_REVISION_CORID_CORE_FPGA3 9 #define MIPS_REVISION_CORID_CORE_24K 10 +#define MIPS_REVISION_CORID_CORE_FPGA4 11 /**** Artificial corid defines ****/ /* diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h index 8045abc78d0f..ac7935203f89 100644 --- a/include/asm-mips/mips_mt.h +++ b/include/asm-mips/mips_mt.h @@ -8,6 +8,12 @@ #include <linux/cpumask.h> +/* + * How many VPEs and TCs is Linux allowed to use? 0 means no limit. + */ +extern int tclimit; +extern int vpelimit; + extern cpumask_t mt_fpu_cpumask; extern unsigned long mt_fpemul_threshold; diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 89c81922d47c..18f47f1e8cd5 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -7,7 +7,7 @@ * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2000, 07 MIPS Technologies, Inc. * Copyright (C) 2003, 2004 Maciej W. Rozycki */ #ifndef _ASM_MIPSREGS_H @@ -15,6 +15,7 @@ #include <linux/linkage.h> #include <asm/hazards.h> +#include <asm/war.h> /* * The following macros are especially useful for __asm__ @@ -533,9 +534,13 @@ #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF7_WII (_ULCAST_(1) << 31) +#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) + + /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ @@ -702,10 +707,10 @@ do { \ */ #define __read_64bit_c0_split(source, sel) \ ({ \ - unsigned long long val; \ - unsigned long flags; \ + unsigned long long __val; \ + unsigned long __flags; \ \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -714,7 +719,7 @@ do { \ "dsrl\t%M0, %M0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ - : "=r" (val)); \ + : "=r" (__val)); \ else \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -723,17 +728,17 @@ do { \ "dsrl\t%M0, %M0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ + : "=r" (__val)); \ + local_irq_restore(__flags); \ \ - val; \ + __val; \ }) #define __write_64bit_c0_split(source, sel, val) \ do { \ - unsigned long flags; \ + unsigned long __flags; \ \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -754,7 +759,7 @@ do { \ "dmtc0\t%L0, " #source ", " #sel "\n\t" \ ".set\tmips0" \ : : "r" (val)); \ - local_irq_restore(flags); \ + local_irq_restore(__flags); \ } while (0) #define read_c0_index() __read_32bit_c0_register($0, 0) @@ -772,6 +777,9 @@ do { \ #define read_c0_context() __read_ulong_c0_register($4, 0) #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) +#define read_c0_userlocal() __read_ulong_c0_register($4, 2) +#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) + #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) @@ -1294,10 +1302,39 @@ static inline void tlb_probe(void) static inline void tlb_read(void) { +#if MIPS34K_MISSED_ITLB_WAR + int res = 0; + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41610001 # dvpe $1 \n" + " move %0, $1 \n" + " ehb \n" + " .set pop \n" + : "=r" (res)); + + instruction_hazard(); +#endif + __asm__ __volatile__( ".set noreorder\n\t" "tlbr\n\t" ".set reorder"); + +#if MIPS34K_MISSED_ITLB_WAR + if ((res & _ULCAST_(1))) + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41600021 # evpe \n" + " ehb \n" + " .set pop \n"); +#endif } static inline void tlb_write_indexed(void) diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index c5ef324fd69f..de6d09ebbd80 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "RM9000 " #elif defined CONFIG_CPU_SB1 #define MODULE_PROC_FAMILY "SB1 " +#elif defined CONFIG_CPU_LOONGSON2 +#define MODULE_PROC_FAMILY "LOONGSON2 " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h deleted file mode 100644 index c3ca959aa4d9..000000000000 --- a/include/asm-mips/nile4.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * This file is based on the following documentation: - * - * NEC Vrc 5074 System Controller Data Sheet, June 1998 - */ - -#ifndef _ASM_NILE4_H -#define _ASM_NILE4_H - -#define NILE4_BASE 0xbfa00000 -#define NILE4_SIZE 0x00200000 /* 2 MB */ - - - /* - * Physical Device Address Registers (PDARs) - */ - -#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ -#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ -#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ -#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ -#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ -#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ -#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ -#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ -#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ -#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ -#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ -#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ - /* [R/W] */ -#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ - - - /* - * CPU Interface Registers - */ - -#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ -#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ -#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ -#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ - /* Enable [R/W] */ -#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ -#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ - - - /* - * Memory-Interface Registers - */ - -#define NILE4_MEMCTRL 0x00C0 /* Memory Control */ -#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ -#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ - - - /* - * PCI-Bus Registers - */ - -#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ -#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ -#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ -#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ -#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ - - - /* - * Local-Bus Registers - */ - -#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ -#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ -#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ -#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ -#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ -#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ -#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ -#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ -#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ - /* Enables [R/W] */ -#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ -#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ - - - /* - * DMA Registers - */ - -#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ -#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ -#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ -#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ -#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ -#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ - - - /* - * Timer Registers - */ - -#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ -#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ -#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ -#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ -#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ -#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ -#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ -#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ - - - /* - * PCI Configuration Space Registers - */ - -#define NILE4_PCI_BASE 0x0200 - -#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ -#define NILE4_DID 0x0202 /* PCI Device ID [R] */ -#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ -#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ -#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ -#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ -#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ -#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ -#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ -#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ -#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ -#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ -#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ -#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ - /* (unimplemented) */ -#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ -#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ -#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ - /* (unimplemented) */ -#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ -#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ -#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ -#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ -#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ -#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ -#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ -#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ -#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ -#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ -#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ -#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ - - - /* - * Serial-Port Registers - */ - -#define NILE4_UART_BASE 0x0300 - -#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ -#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ -#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ -#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ -#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ -#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ -#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ -#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ -#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ -#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ -#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ -#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ - -#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ - - - /* - * Interrupt Lines - */ - -#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ -#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ -#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ -#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ -#define NILE4_INT_UART 4 /* UART Interrupt */ -#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ -#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ -#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ -#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ -#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ -#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ -#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ -#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ -#define NILE4_INT_RESV 13 /* Reserved */ -#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ -#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ - - - /* - * Nile 4 Register Access - */ - -static inline void nile4_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void nile4_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u32 nile4_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - -static inline void nile4_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u16 nile4_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - -static inline void nile4_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u8 nile4_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - - - /* - * Physical Device Address Registers - */ - -extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int visible); - - - /* - * PCI Master Registers - */ - -#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ -#define NILE4_PCICMD_IO 1 /* PCI I/O Space */ -#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ -#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ - - - /* - * PCI Address Spaces - * - * Note that these are multiplexed using PCIINIT[01]! - */ - -#define NILE4_PCI_IO_BASE 0xa6000000 -#define NILE4_PCI_MEM_BASE 0xa8000000 -#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE -#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE - - -extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); - - - /* - * Interrupt Programming - */ - -#define NUM_I8259_INTERRUPTS 16 -#define NUM_NILE4_INTERRUPTS 16 - -#define IRQ_I8259_CASCADE NILE4_INT_INTE -#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) -#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) -#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) - -extern void nile4_map_irq(int nile4_irq, int cpu_irq); -extern void nile4_map_irq_all(int cpu_irq); -extern void nile4_enable_irq(unsigned int nile4_irq); -extern void nile4_disable_irq(unsigned int nile4_irq); -extern void nile4_disable_irq_all(void); -extern u16 nile4_get_irq_stat(int cpu_irq); -extern void nile4_enable_irq_output(int cpu_irq); -extern void nile4_disable_irq_output(int cpu_irq); -extern void nile4_set_pci_irq_polarity(int pci_irq, int high); -extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); -extern void nile4_clear_irq(int nile4_irq); -extern void nile4_clear_irq_mask(u32 mask); -extern u8 nile4_i8259_iack(void); -extern void nile4_dump_irq_status(void); /* Debug */ - -#endif - diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 5c3239dad0f2..e3301e54d559 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -34,12 +34,8 @@ #ifndef __ASSEMBLY__ -/* - * This gives the physical RAM offset. - */ -#ifndef PHYS_OFFSET -#define PHYS_OFFSET 0UL -#endif +#include <linux/pfn.h> +#include <asm/io.h> /* * It's normally defined only for FLATMEM config but it's @@ -48,9 +44,6 @@ */ #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) -#include <linux/pfn.h> -#include <asm/io.h> - extern void clear_page(void * page); extern void copy_page(void * to, void * from); @@ -149,12 +142,16 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* * __pa()/__va() should be used only during mem init. */ -#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) -#define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0) +#ifdef CONFIG_64BIT +#define __pa(x) \ +({ \ + unsigned long __x = (unsigned long)(x); \ + __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x); \ +}) #else -#define __pa_page_offset(x) PAGE_OFFSET +#define __pa(x) \ + ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif -#define __pa(x) ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET) #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 3eea3ba0fca5..4fcc185cb2d1 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -56,7 +56,7 @@ extern void register_pci_controller(struct pci_controller *hose); /* * board supplied pci irq fixup routine */ -extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin); +extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); /* Can be used to override the logic in pci_scan_bus for skipping @@ -121,20 +121,6 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; #endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, - struct page *page, unsigned long offset, int direction); -extern struct page *pci_dac_dma_to_page(struct pci_dev *pdev, - dma64_addr_t dma_addr); -extern unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, - dma64_addr_t dma_addr); -extern void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction); -extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction); - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -181,10 +167,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) /* implement the pci_ DMA API in terms of the generic device dma_ one */ #include <asm-generic/pci-dma-compat.h> -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - /* Do platform specific device initialization at pci_enable_device() time */ extern int pcibios_plat_dev_init(struct pci_dev *dev); diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index 2fbd47eba32d..59c865deb0c7 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, */ /* PGDIR_SHIFT determines what a third-level page table entry can map */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PGDIR_SHIFT 21 -#else -#define PGDIR_SHIFT 22 -#endif +#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -55,17 +51,11 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, * Entries per page directory level: we use two-level, so * we don't really have any PUD/PMD directory physically. */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PGD_ORDER 1 +#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2) +#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0) #define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 1 #define PTE_ORDER 0 -#else -#define PGD_ORDER 0 -#define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 1 -#define PTE_ORDER 0 -#endif #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 27d77d981937..d2ee28156743 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -168,19 +168,21 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt #define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0) #endif -#define PGD_T_LOG2 ffz(~sizeof(pgd_t)) -#define PMD_T_LOG2 ffz(~sizeof(pmd_t)) -#define PTE_T_LOG2 ffz(~sizeof(pte_t)) +#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1) +#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1) +#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1) -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; +/* + * We used to declare this array with size but gcc 3.3 and older are not able + * to find that this expression is a constant, so the size is dropped. + */ +extern pgd_t swapper_pg_dir[]; /* * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -static inline int pte_user(pte_t pte) { BUG(); return 0; } #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) -static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; } static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } @@ -193,13 +195,6 @@ static inline pte_t pte_wrprotect(pte_t pte) return pte; } -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); - pte.pte_high &= ~_PAGE_SILENT_READ; - return pte; -} - static inline pte_t pte_mkclean(pte_t pte) { pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); @@ -224,16 +219,6 @@ static inline pte_t pte_mkwrite(pte_t pte) return pte; } -static inline pte_t pte_mkread(pte_t pte) -{ - pte.pte_low |= _PAGE_READ; - if (pte.pte_low & _PAGE_ACCESSED) { - pte.pte_low |= _PAGE_SILENT_READ; - pte.pte_high |= _PAGE_SILENT_READ; - } - return pte; -} - static inline pte_t pte_mkdirty(pte_t pte) { pte.pte_low |= _PAGE_MODIFIED; @@ -253,7 +238,6 @@ static inline pte_t pte_mkyoung(pte_t pte) return pte; } #else -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } @@ -265,12 +249,6 @@ static inline pte_t pte_wrprotect(pte_t pte) return pte; } -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); - return pte; -} - static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); @@ -291,14 +269,6 @@ static inline pte_t pte_mkwrite(pte_t pte) return pte; } -static inline pte_t pte_mkread(pte_t pte) -{ - pte_val(pte) |= _PAGE_READ; - if (pte_val(pte) & _PAGE_ACCESSED) - pte_val(pte) |= _PAGE_SILENT_READ; - return pte; -} - static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_MODIFIED; diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h index 260f3448ccf1..6ad519189ce2 100644 --- a/include/asm-mips/pmon.h +++ b/include/asm-mips/pmon.h @@ -22,7 +22,7 @@ struct callvectors { char* (*gets) (char*); union { int (*smpfork) (unsigned long cp, char *sp); - int (*cpustart) (long, long, long, long); + int (*cpustart) (long, void (*)(void), void *, long); } _s; int (*semlock) (int sem); void (*semunlock) (int sem); diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 5f80ba71ab92..83bc94534084 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -62,8 +62,9 @@ extern unsigned int vced_count, vcei_count; * This decides where the kernel will search for a free chunk of vm * space during mmap's. */ -#define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \ - PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) +#define TASK_UNMAPPED_BASE \ + (test_thread_flag(TIF_32BIT_ADDR) ? \ + PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) #endif #define NUM_FPU_REGS 32 @@ -82,10 +83,6 @@ struct mips_fpu_struct { unsigned int fcr31; }; -#define INIT_FPU { \ - {0,} \ -} - #define NUM_DSP_REGS 6 typedef __u32 dspreg_t; @@ -95,8 +92,6 @@ struct mips_dsp_state { unsigned int dspcontrol; }; -#define INIT_DSP {{0,},} - #define INIT_CPUMASK { \ {0,} \ } @@ -138,58 +133,65 @@ struct thread_struct { unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; unsigned long trap_no; -#define MF_FIXADE 1 /* Fix address errors in software */ -#define MF_LOGADE 2 /* Log address errors to syslog */ -#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */ -#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */ -#define MF_FPUBOUND 0x10 /* thread bound to FPU-full CPU set */ - unsigned long mflags; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; struct mips_abi *abi; }; -#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_N32 MF_32BIT_ADDR -#define MF_N64 0 - #ifdef CONFIG_MIPS_MT_FPAFF -#define FPAFF_INIT 0, INIT_CPUMASK, +#define FPAFF_INIT \ + .emulated_fp = 0, \ + .user_cpus_allowed = INIT_CPUMASK, #else #define FPAFF_INIT #endif /* CONFIG_MIPS_MT_FPAFF */ -#define INIT_THREAD { \ - /* \ - * saved main processor registers \ - */ \ - 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, \ - /* \ - * saved cp0 stuff \ - */ \ - 0, \ - /* \ - * saved fpu/fpu emulator stuff \ - */ \ - INIT_FPU, \ - /* \ - * fpu affinity state (null if not FPAFF) \ - */ \ - FPAFF_INIT \ - /* \ - * saved dsp/dsp emulator stuff \ - */ \ - INIT_DSP, \ - /* \ - * Other stuff associated with the process \ - */ \ - 0, 0, 0, 0, \ - /* \ - * For now the default is to fix address errors \ - */ \ - MF_FIXADE, 0, 0 \ +#define INIT_THREAD { \ + /* \ + * Saved main processor registers \ + */ \ + .reg16 = 0, \ + .reg17 = 0, \ + .reg18 = 0, \ + .reg19 = 0, \ + .reg20 = 0, \ + .reg21 = 0, \ + .reg22 = 0, \ + .reg23 = 0, \ + .reg29 = 0, \ + .reg30 = 0, \ + .reg31 = 0, \ + /* \ + * Saved cp0 stuff \ + */ \ + .cp0_status = 0, \ + /* \ + * Saved FPU/FPU emulator stuff \ + */ \ + .fpu = { \ + .fpr = {0,}, \ + .fcr31 = 0, \ + }, \ + /* \ + * FPU affinity state (null if not FPAFF) \ + */ \ + FPAFF_INIT \ + /* \ + * Saved DSP stuff \ + */ \ + .dsp = { \ + .dspr = {0, }, \ + .dspcontrol = 0, \ + }, \ + /* \ + * Other stuff associated with the process \ + */ \ + .cp0_badvaddr = 0, \ + .cp0_baduaddr = 0, \ + .error_code = 0, \ + .trap_no = 0, \ + .irix_trampoline = 0, \ + .irix_oldctx = 0, \ } struct task_struct; @@ -237,7 +239,7 @@ unsigned long get_wchan(struct task_struct *p); #define ARCH_HAS_PREFETCH -extern inline void prefetch(const void *addr) +static inline void prefetch(const void *addr) { __asm__ __volatile__( " .set mips4 \n" diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h deleted file mode 100644 index 82ad401c7dca..000000000000 --- a/include/asm-mips/rtc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * include/asm-mips/rtc.h - * - * (Really an interface for drivers/char/genrtc.c) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Please read the COPYING file for all license details. - */ - -#ifndef _MIPS_RTC_H -#define _MIPS_RTC_H - -#ifdef __KERNEL__ - -#include <linux/rtc.h> -#include <asm/time.h> - -#define RTC_PIE 0x40 /* periodic interrupt enable */ -#define RTC_AIE 0x20 /* alarm interrupt enable */ -#define RTC_UIE 0x10 /* update-finished interrupt enable */ - -/* some dummy definitions */ -#define RTC_BATT_BAD 0x100 /* battery bad */ -#define RTC_SQWE 0x08 /* enable square-wave output */ -#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -static inline unsigned int get_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - - nowtime = rtc_mips_get_time(); - to_tm(nowtime, time); - time->tm_year -= 1900; - - return RTC_24H; -} - -static inline int set_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - int ret; - - nowtime = mktime(time->tm_year+1900, time->tm_mon+1, - time->tm_mday, time->tm_hour, time->tm_min, - time->tm_sec); - ret = rtc_mips_set_time(nowtime); - - return ret; -} - -static inline unsigned int get_rtc_ss(void) -{ - struct rtc_time h; - - get_rtc_time(&h); - return h.tm_sec; -} - -static inline int get_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} - -static inline int set_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} -#endif -#endif diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index ce51213d84f9..c07ebd8eb9e7 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -19,159 +19,4 @@ */ #define BASE_BAUD (1843200 / 16) -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#ifdef CONFIG_MACH_JAZZ -#include <asm/jazz.h> - -#ifndef CONFIG_OLIVETTI_M700 - /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know - exactly which ones ... XXX */ -#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */ -#else -/* but the M700 isn't such a strange beast */ -#define JAZZ_BASE_BAUD BASE_BAUD -#endif - -#define _JAZZ_SERIAL_INIT(int, base) \ - { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \ - .io_type = SERIAL_IO_MEM } -#define JAZZ_SERIAL_PORT_DEFNS \ - _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \ - _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE), -#else -#define JAZZ_SERIAL_PORT_DEFNS -#endif - -/* - * Galileo EV64120 evaluation board - */ -#ifdef CONFIG_MIPS_EV64120 -#include <mach-gt64120.h> -#define EV64120_SERIAL_PORT_DEFNS \ - { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM }, \ - { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM }, -#else -#define EV64120_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT -#define STD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ - { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ - { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ - -#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ -#define STD_SERIAL_PORT_DEFNS -#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ - -#ifdef CONFIG_MOMENCO_OCELOT_3 -#define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) -#define OCELOT_3_SERIAL_IRQ 6 -#define OCELOT_3_SERIAL_BASE (signed)0xfd000020 - -#define _OCELOT_3_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ - io_type: SERIAL_IO_MEM } - -#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ - _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE) -#else -#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_SERIAL1_IRQ 4 -#define OCELOT_SERIAL1_BASE 0xe0001020 - -#define _OCELOT_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM } -#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE) -#else -#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT_C -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_C_SERIAL1_IRQ 80 -#define OCELOT_C_SERIAL1_BASE 0xfd000020 - -#define OCELOT_C_SERIAL2_IRQ 81 -#define OCELOT_C_SERIAL2_BASE 0xfd000000 - -#define _OCELOT_C_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_C_BASE_BAUD, \ - .irq = (int), \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM \ - } -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) -#else -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_DDB5477 -#include <asm/ddb5xxx/ddb5477.h> -#define DDB5477_SERIAL_PORT_DEFNS \ - { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \ - .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \ - .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \ - { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \ - .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \ - .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, -#else -#define DDB5477_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_SGI_IP32 -/* - * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory - * They are initialized in ip32_setup - */ -#define IP32_SERIAL_PORT_DEFNS \ - {},{}, -#else -#define IP32_SERIAL_PORT_DEFNS -#endif /* CONFIG_SGI_IP32 */ - -#define SERIAL_PORT_DFNS \ - DDB5477_SERIAL_PORT_DEFNS \ - EV64120_SERIAL_PORT_DEFNS \ - IP32_SERIAL_PORT_DEFNS \ - JAZZ_SERIAL_PORT_DEFNS \ - STD_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS - #endif /* _ASM_SERIAL_H */ diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h index bda391d3af85..c34d36b6b8c2 100644 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ b/include/asm-mips/sibyte/bcm1480_regs.h @@ -220,17 +220,30 @@ #define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) #define BCM1480_DUART_CHANREG_SPACING 0x100 -#define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \ - + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \ - + (reg)) -#define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg)) - -#define R_BCM1480_DUART_IMRREG(chan) (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING) -#define R_BCM1480_DUART_ISRREG(chan) (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING) - -#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) -#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) -#define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT) +#define A_BCM1480_DUART_CHANREG(chan, reg) \ + (A_BCM1480_DUART(chan) + \ + BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg)) +#define A_BCM1480_DUART_CTRLREG(chan, reg) \ + (A_BCM1480_DUART(chan) + \ + BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) + +#define DUART_IMRISR_SPACING 0x20 +#define DUART_INCHNG_SPACING 0x10 + +#define R_BCM1480_DUART_IMRREG(chan) \ + (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) +#define R_BCM1480_DUART_ISRREG(chan) \ + (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) +#define R_BCM1480_DUART_INCHREG(chan) \ + (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING) + +#define A_BCM1480_DUART_IMRREG(chan) \ + (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) +#define A_BCM1480_DUART_ISRREG(chan) \ + (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan))) + +#define A_BCM1480_DUART_IN_PORT(chan) \ + (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT)) /* * These constants are the absolute addresses. diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index da7c188993c9..220b7e94f1bf 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -272,59 +272,69 @@ ********************************************************************* */ -#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ +#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ #define R_DUART_NUM_PORTS 2 #define A_DUART 0x0010060000 #define DUART_CHANREG_SPACING 0x100 -#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) -#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) + +#define A_DUART_CHANREG(chan, reg) \ + (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) #endif /* 1250 & 112x */ -#define R_DUART_MODE_REG_1 0x100 -#define R_DUART_MODE_REG_2 0x110 -#define R_DUART_STATUS 0x120 -#define R_DUART_CLK_SEL 0x130 -#define R_DUART_CMD 0x150 -#define R_DUART_RX_HOLD 0x160 -#define R_DUART_TX_HOLD 0x170 +#define R_DUART_MODE_REG_1 0x000 +#define R_DUART_MODE_REG_2 0x010 +#define R_DUART_STATUS 0x020 +#define R_DUART_CLK_SEL 0x030 +#define R_DUART_CMD 0x050 +#define R_DUART_RX_HOLD 0x060 +#define R_DUART_TX_HOLD 0x070 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) -#define R_DUART_FULL_CTL 0x140 -#define R_DUART_OPCR_X 0x180 -#define R_DUART_AUXCTL_X 0x190 -#endif /* 1250 PASS2 || 112x PASS1 || 1480*/ +#define R_DUART_FULL_CTL 0x040 +#define R_DUART_OPCR_X 0x080 +#define R_DUART_AUXCTL_X 0x090 +#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ /* * The IMR and ISR can't be addressed with A_DUART_CHANREG, - * so use this macro instead. + * so use these macros instead. */ -#define R_DUART_AUX_CTRL 0x310 -#define R_DUART_ISR_A 0x320 -#define R_DUART_IMR_A 0x330 -#define R_DUART_ISR_B 0x340 -#define R_DUART_IMR_B 0x350 -#define R_DUART_OUT_PORT 0x360 -#define R_DUART_OPCR 0x370 -#define R_DUART_IN_PORT 0x380 +#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ +#define DUART_IMRISR_SPACING 0x20 +#define DUART_INCHNG_SPACING 0x10 -#define R_DUART_SET_OPR 0x3B0 -#define R_DUART_CLEAR_OPR 0x3C0 +#define A_DUART_CTRLREG(reg) \ + (A_DUART + DUART_CHANREG_SPACING * 3 + (reg)) -#define DUART_IMRISR_SPACING 0x20 +#define R_DUART_IMRREG(chan) \ + (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING) +#define R_DUART_ISRREG(chan) \ + (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING) +#define R_DUART_INCHREG(chan) \ + (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING) -#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ -#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) -#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) - -#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) -#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) +#define A_DUART_IMRREG(chan) A_DUART_CTRLREG(R_DUART_IMRREG(chan)) +#define A_DUART_ISRREG(chan) A_DUART_CTRLREG(R_DUART_ISRREG(chan)) +#define A_DUART_INCHREG(chan) A_DUART_CTRLREG(R_DUART_INCHREG(chan)) #endif /* 1250 & 112x */ - +#define R_DUART_AUX_CTRL 0x010 +#define R_DUART_ISR_A 0x020 +#define R_DUART_IMR_A 0x030 +#define R_DUART_ISR_B 0x040 +#define R_DUART_IMR_B 0x050 +#define R_DUART_OUT_PORT 0x060 +#define R_DUART_OPCR 0x070 +#define R_DUART_IN_PORT 0x080 + +#define R_DUART_SET_OPR 0x0B0 +#define R_DUART_CLEAR_OPR 0x0C0 +#define R_DUART_IN_CHNG_A 0x0D0 +#define R_DUART_IN_CHNG_B 0x0E0 /* diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index e87045e62bf0..cf74fedcbef1 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -75,7 +75,8 @@ #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) -#define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ +#define M_DUART_TX_IRQ_SEL_TXRDY 0 +#define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5) #define M_DUART_RX_IRQ_SEL_RXRDY 0 #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) @@ -246,10 +247,13 @@ #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) +#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) + #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) +#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) /* * DUART Channel A Interrupt Status Register (Table 10-17) @@ -262,6 +266,7 @@ #define M_DUART_ISR_RX _SB_MAKEMASK1(1) #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) #define M_DUART_ISR_IN _SB_MAKEMASK1(3) +#define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) /* diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 1608fd71d6f7..13aef6af422c 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -49,13 +49,6 @@ extern struct call_data_struct *call_data; extern cpumask_t phys_cpu_present_map; #define cpu_possible_map phys_cpu_present_map -extern cpumask_t cpu_callout_map; -/* We don't mark CPUs online until __cpu_up(), so we need another measure */ -static inline int num_booting_cpus(void) -{ - return cpus_weight(cpu_callout_map); -} - /* * These are defined by the board-specific code. */ diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h index 44dfa4adecf3..ff3e8936b493 100644 --- a/include/asm-mips/smtc.h +++ b/include/asm-mips/smtc.h @@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t); #define PARKED_INDEX ((unsigned int)0x80000000) +/* + * Define low-level interrupt mask for IPIs, if necessary. + * By default, use SW interrupt 1, which requires no external + * hardware support, but which works only for single-core + * MIPS MT systems. + */ +#ifndef MIPS_CPU_IPI_IRQ +#define MIPS_CPU_IPI_IRQ 1 +#endif + #endif /* _ASM_SMTC_MT_H */ diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index f257509b914f..ddaf36a1e389 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h @@ -146,9 +146,6 @@ extern unsigned int sni_brd_type; #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) -#define SNI_DS1216_A20R_BASE 0xbc081ffc -#define SNI_DS1216_RM200_BASE 0xbcd41ffc - #define SNI_PCIT_INT_REG 0xbfff000c #define SNI_PCIT_INT_START 24 diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index 35e431cd796b..bb897016c491 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h @@ -67,7 +67,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) : "memory"); } - smp_mb(); + smp_llsc_mb(); } static inline void __raw_spin_unlock(raw_spinlock_t *lock) @@ -118,7 +118,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) : "memory"); } - smp_mb(); + smp_llsc_mb(); return res == 0; } @@ -183,7 +183,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) : "memory"); } - smp_mb(); + smp_llsc_mb(); } /* Note the use of sub, not subu which will make the kernel die with an @@ -193,7 +193,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) { unsigned int tmp; - smp_mb(); + smp_llsc_mb(); if (R10000_LLSC_WAR) { __asm__ __volatile__( @@ -262,7 +262,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) : "memory"); } - smp_mb(); + smp_llsc_mb(); } static inline void __raw_write_unlock(raw_rwlock_t *rw) @@ -293,7 +293,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) " .set reorder \n" " beqzl %1, 1b \n" " nop \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " li %2, 1 \n" "2: \n" : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) @@ -310,7 +310,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) " beqz %1, 1b \n" " nop \n" " .set reorder \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " li %2, 1 \n" "2: \n" : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) @@ -336,7 +336,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) " sc %1, %0 \n" " beqzl %1, 1b \n" " nop \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " li %2, 1 \n" " .set reorder \n" "2: \n" @@ -354,7 +354,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) " beqz %1, 3f \n" " li %2, 1 \n" "2: \n" - __WEAK_ORDERING_MB + __WEAK_LLSC_MB " .subsection 2 \n" "3: b 1b \n" " li %2, 0 \n" diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h index 07f873351a86..0bf82818aa53 100644 --- a/include/asm-mips/stacktrace.h +++ b/include/asm-mips/stacktrace.h @@ -9,7 +9,11 @@ extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, unsigned long pc, unsigned long *ra); #else #define raw_show_trace 1 -#define unwind_stack(task, sp, pc, ra) 0 +static inline unsigned long unwind_stack(struct task_struct *task, + unsigned long *sp, unsigned long pc, unsigned long *ra) +{ + return 0; +} #endif static __always_inline void prepare_frametrace(struct pt_regs *regs) diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index bb0b289dbc9e..480b574e2483 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -17,6 +17,7 @@ #include <asm/addrspace.h> #include <asm/barrier.h> +#include <asm/cmpxchg.h> #include <asm/cpu-features.h> #include <asm/dsp.h> #include <asm/war.h> @@ -44,42 +45,34 @@ struct task_struct; * different thread. */ -#define switch_to(prev,next,last) \ +#define __mips_mt_fpaff_switch_to(prev) \ do { \ + struct thread_info *__prev_ti = task_thread_info(prev); \ + \ if (cpu_has_fpu && \ - (prev->thread.mflags & MF_FPUBOUND) && \ - (!(KSTK_STATUS(prev) & ST0_CU1))) { \ - prev->thread.mflags &= ~MF_FPUBOUND; \ + test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ + (!(KSTK_STATUS(prev) & ST0_CU1))) { \ + clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ prev->cpus_allowed = prev->thread.user_cpus_allowed; \ } \ - if (cpu_has_dsp) \ - __save_dsp(prev); \ next->thread.emulated_fp = 0; \ - (last) = resume(prev, next, task_thread_info(next)); \ - if (cpu_has_dsp) \ - __restore_dsp(current); \ } while(0) #else +#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) +#endif + #define switch_to(prev,next,last) \ do { \ + __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ __save_dsp(prev); \ (last) = resume(prev, next, task_thread_info(next)); \ if (cpu_has_dsp) \ __restore_dsp(current); \ + if (cpu_has_userlocal) \ + write_c0_userlocal(task_thread_info(current)->tp_value);\ } while(0) -#endif - -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) { @@ -127,7 +120,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } @@ -175,7 +168,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } @@ -202,266 +195,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define __HAVE_ARCH_CMPXCHG 1 - -static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, - unsigned long new) -{ - __u32 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqz $1, 3f \n" - "2: \n" - " .subsection 2 \n" - "3: b 1b \n" - " .previous \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_mb(); - - return retval; -} - -static inline unsigned long __cmpxchg_u32_local(volatile int * m, - unsigned long old, unsigned long new) -{ - __u32 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: ll %0, %2 # __cmpxchg_u32 \n" - " bne %0, %z3, 2f \n" - " .set mips0 \n" - " move $1, %z4 \n" - " .set mips3 \n" - " sc $1, %1 \n" - " beqz $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - local_irq_restore(flags); /* implies memory barrier */ - } - - return retval; -} - -#ifdef CONFIG_64BIT -static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, - unsigned long new) -{ - __u64 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqz $1, 3f \n" - "2: \n" - " .subsection 2 \n" - "3: b 1b \n" - " .previous \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - raw_local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - raw_local_irq_restore(flags); /* implies memory barrier */ - } - - smp_mb(); - - return retval; -} - -static inline unsigned long __cmpxchg_u64_local(volatile int * m, - unsigned long old, unsigned long new) -{ - __u64 retval; - - if (cpu_has_llsc && R10000_LLSC_WAR) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqzl $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else if (cpu_has_llsc) { - __asm__ __volatile__( - " .set push \n" - " .set noat \n" - " .set mips3 \n" - "1: lld %0, %2 # __cmpxchg_u64 \n" - " bne %0, %z3, 2f \n" - " move $1, %z4 \n" - " scd $1, %1 \n" - " beqz $1, 1b \n" - "2: \n" - " .set pop \n" - : "=&r" (retval), "=R" (*m) - : "R" (*m), "Jr" (old), "Jr" (new) - : "memory"); - } else { - unsigned long flags; - - local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - local_irq_restore(flags); /* implies memory barrier */ - } - - return retval; -} - -#else -extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels( - volatile int * m, unsigned long old, unsigned long new); -#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels -extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels( - volatile int * m, unsigned long old, unsigned long new); -#define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels -#endif - -/* This function doesn't exist, so you'll get a linker error - if something tries to do an invalid cmpxchg(). */ -extern void __cmpxchg_called_with_bad_pointer(void); - -static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32(ptr, old, new); - case 8: - return __cmpxchg_u64(ptr, old, new); - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -static inline unsigned long __cmpxchg_local(volatile void * ptr, - unsigned long old, unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32_local(ptr, old, new); - case 8: - return __cmpxchg_u64_local(ptr, old, new); - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -#define cmpxchg(ptr,old,new) \ - ((__typeof__(*(ptr)))__cmpxchg((ptr), \ - (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) - -#define cmpxchg_local(ptr,old,new) \ - ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \ - (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) - extern void set_handler (unsigned long offset, void *addr, unsigned long len); extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); @@ -480,6 +213,6 @@ extern int stop_a_enabled; */ #define __ARCH_WANT_UNLOCKED_CTXSW -#define arch_align_stack(x) (x) +extern unsigned long arch_align_stack(unsigned long sp); #endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h index 0bbe07b42a07..c83c68444e86 100644 --- a/include/asm-mips/termbits.h +++ b/include/asm-mips/termbits.h @@ -30,6 +30,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ @@ -153,6 +164,7 @@ struct ktermios { #define HUPCL 0002000 /* Hang up on last close. */ #define CLOCAL 0004000 /* Ignore modem status lines. */ #define CBAUDEX 0010000 +#define BOTHER 0010000 #define B57600 0010001 #define B115200 0010002 #define B230400 0010003 @@ -168,9 +180,11 @@ struct ktermios { #define B3000000 0010015 #define B3500000 0010016 #define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CIBAUD 002003600000 /* input baud rate */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ +#define CRTSCTS 020000000000 /* flow control */ + +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ /* c_lflag bits */ #define ISIG 0000001 /* Enable signals. */ diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h index 2ce07f4be369..a275661fa7e1 100644 --- a/include/asm-mips/termios.h +++ b/include/asm-mips/termios.h @@ -122,8 +122,10 @@ struct termio { copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ }) -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) #endif /* defined(__KERNEL__) */ diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index fbcda8204473..b2772df1a1bd 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -46,7 +46,7 @@ struct thread_info { { \ .task = &tsk, \ .exec_domain = &default_exec_domain, \ - .flags = 0, \ + .flags = _TIF_FIXADE, \ .cpu = 0, \ .preempt_count = 1, \ .addr_limit = KERNEL_DS, \ @@ -87,9 +87,8 @@ register struct thread_info *__current_thread_info __asm__("$28"); ({ \ struct thread_info *ret; \ \ - ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \ - if (ret) \ - memset(ret, 0, THREAD_SIZE); \ + ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ + \ ret; \ }) #else @@ -109,20 +108,23 @@ register struct thread_info *__current_thread_info __asm__("$28"); * - pending work-to-be-done flags are in LSW * - other flags in MSW */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */ -#define TIF_SECCOMP 5 /* secure computing */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ +#define TIF_SECCOMP 4 /* secure computing */ #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_MEMDIE 18 #define TIF_FREEZE 19 +#define TIF_FIXADE 20 /* Fix address errors in software */ +#define TIF_LOGADE 21 /* Log address errors to syslog */ +#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ +#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ +#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) @@ -131,6 +133,11 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define _TIF_USEDFPU (1<<TIF_USEDFPU) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) #define _TIF_FREEZE (1<<TIF_FREEZE) +#define _TIF_FIXADE (1<<TIF_FIXADE) +#define _TIF_LOGADE (1<<TIF_LOGADE) +#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) +#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) +#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h index fff7a73e22d0..bb8f5c29c3d9 100644 --- a/include/asm-mips/tlbdebug.h +++ b/include/asm-mips/tlbdebug.h @@ -11,10 +11,6 @@ /* * TLB debugging functions: */ -extern void dump_tlb(int first, int last); extern void dump_tlb_all(void); -extern void dump_tlb_wired(void); -extern void dump_tlb_addr(unsigned long addr); -extern void dump_tlb_nonwired(void); #endif /* __ASM_TLBDEBUG_H */ diff --git a/include/asm-mips/tx3912.h b/include/asm-mips/tx3912.h deleted file mode 100644 index d709d87363d0..000000000000 --- a/include/asm-mips/tx3912.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - * include/asm-mips/tx3912.h - * - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Registers for TMPR3912/05 and PR31700 processors - */ -#ifndef _TX3912_H_ -#define _TX3912_H_ - -/***************************************************************************** - * Clock Subsystem * - * --------------- * - * Chapter 6 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals * - *****************************************************************************/ -#define TX3912_CLK_CTRL 0x01c0 - -/* - * Clock control register values - */ -#define TX3912_CLK_CTRL_CHICLKDIV_MASK 0xff000000 -#define TX3912_CLK_CTRL_ENCLKTEST 0x00800000 -#define TX3912_CLK_CTRL_CLKTESTSELSIB 0x00400000 -#define TX3912_CLK_CTRL_CHIMCLKSEL 0x00200000 -#define TX3912_CLK_CTRL_CHICLKDIR 0x00100000 -#define TX3912_CLK_CTRL_ENCHIMCLK 0x00080000 -#define TX3912_CLK_CTRL_ENVIDCLK 0x00040000 -#define TX3912_CLK_CTRL_ENMBUSCLK 0x00020000 -#define TX3912_CLK_CTRL_ENSPICLK 0x00010000 -#define TX3912_CLK_CTRL_ENTIMERCLK 0x00008000 -#define TX3912_CLK_CTRL_ENFASTTIMERCLK 0x00004000 -#define TX3912_CLK_CTRL_SIBMCLKDIR 0x00002000 -#define TX3912_CLK_CTRL_reserved1 0x00001000 -#define TX3912_CLK_CTRL_ENSIBMCLK 0x00000800 -#define TX3912_CLK_CTRL_SIBMCLKDIV_6 0x00000600 -#define TX3912_CLK_CTRL_SIBMCLKDIV_5 0x00000500 -#define TX3912_CLK_CTRL_SIBMCLKDIV_4 0x00000400 -#define TX3912_CLK_CTRL_SIBMCLKDIV_3 0x00000300 -#define TX3912_CLK_CTRL_SIBMCLKDIV_2 0x00000200 -#define TX3912_CLK_CTRL_SIBMCLKDIV_1 0x00000100 -#define TX3912_CLK_CTRL_CSERSEL 0x00000080 -#define TX3912_CLK_CTRL_CSERDIV_6 0x00000060 -#define TX3912_CLK_CTRL_CSERDIV_5 0x00000050 -#define TX3912_CLK_CTRL_CSERDIV_4 0x00000040 -#define TX3912_CLK_CTRL_CSERDIV_3 0x00000030 -#define TX3912_CLK_CTRL_CSERDIV_2 0x00000020 -#define TX3912_CLK_CTRL_CSERDIV_1 0x00000010 -#define TX3912_CLK_CTRL_ENCSERCLK 0x00000008 -#define TX3912_CLK_CTRL_ENIRCLK 0x00000004 -#define TX3912_CLK_CTRL_ENUARTACLK 0x00000002 -#define TX3912_CLK_CTRL_ENUARTBCLK 0x00000001 - - -/***************************************************************************** - * Interrupt Subsystem * - * ------------------- * - * Chapter 8 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals * - *****************************************************************************/ -#define TX3912_INT1_CLEAR 0x0100 -#define TX3912_INT2_CLEAR 0x0104 -#define TX3912_INT3_CLEAR 0x0108 -#define TX3912_INT4_CLEAR 0x010c -#define TX3912_INT5_CLEAR 0x0110 -#define TX3912_INT1_ENABLE 0x0118 -#define TX3912_INT2_ENABLE 0x011c -#define TX3912_INT3_ENABLE 0x0120 -#define TX3912_INT4_ENABLE 0x0124 -#define TX3912_INT5_ENABLE 0x0128 -#define TX3912_INT6_ENABLE 0x012c -#define TX3912_INT1_STATUS 0x0100 -#define TX3912_INT2_STATUS 0x0104 -#define TX3912_INT3_STATUS 0x0108 -#define TX3912_INT4_STATUS 0x010c -#define TX3912_INT5_STATUS 0x0110 -#define TX3912_INT6_STATUS 0x0114 - -/* - * Interrupt 2 register values - */ -#define TX3912_INT2_UARTARXINT 0x80000000 -#define TX3912_INT2_UARTARXOVERRUNINT 0x40000000 -#define TX3912_INT2_UARTAFRAMEERRINT 0x20000000 -#define TX3912_INT2_UARTABREAKINT 0x10000000 -#define TX3912_INT2_UARTAPARITYINT 0x08000000 -#define TX3912_INT2_UARTATXINT 0x04000000 -#define TX3912_INT2_UARTATXOVERRUNINT 0x02000000 -#define TX3912_INT2_UARTAEMPTYINT 0x01000000 -#define TX3912_INT2_UARTADMAFULLINT 0x00800000 -#define TX3912_INT2_UARTADMAHALFINT 0x00400000 -#define TX3912_INT2_UARTBRXINT 0x00200000 -#define TX3912_INT2_UARTBRXOVERRUNINT 0x00100000 -#define TX3912_INT2_UARTBFRAMEERRINT 0x00080000 -#define TX3912_INT2_UARTBBREAKINT 0x00040000 -#define TX3912_INT2_UARTBPARITYINT 0x00020000 -#define TX3912_INT2_UARTBTXINT 0x00010000 -#define TX3912_INT2_UARTBTXOVERRUNINT 0x00008000 -#define TX3912_INT2_UARTBEMPTYINT 0x00004000 -#define TX3912_INT2_UARTBDMAFULLINT 0x00002000 -#define TX3912_INT2_UARTBDMAHALFINT 0x00001000 -#define TX3912_INT2_UARTA_RX_BITS 0xf8000000 -#define TX3912_INT2_UARTA_TX_BITS 0x07c00000 -#define TX3912_INT2_UARTB_RX_BITS 0x003e0000 -#define TX3912_INT2_UARTB_TX_BITS 0x0001f000 - -/* - * Interrupt 5 register values - */ -#define TX3912_INT5_RTCINT 0x80000000 -#define TX3912_INT5_ALARMINT 0x40000000 -#define TX3912_INT5_PERINT 0x20000000 -#define TX3912_INT5_STPTIMERINT 0x10000000 -#define TX3912_INT5_POSPWRINT 0x08000000 -#define TX3912_INT5_NEGPWRINT 0x04000000 -#define TX3912_INT5_POSPWROKINT 0x02000000 -#define TX3912_INT5_NEGPWROKINT 0x01000000 -#define TX3912_INT5_POSONBUTINT 0x00800000 -#define TX3912_INT5_NEGONBUTINT 0x00400000 -#define TX3912_INT5_SPIBUFAVAILINT 0x00200000 -#define TX3912_INT5_SPIERRINT 0x00100000 -#define TX3912_INT5_SPIRCVINT 0x00080000 -#define TX3912_INT5_SPIEMPTYINT 0x00040000 -#define TX3912_INT5_IRCONSMINT 0x00020000 -#define TX3912_INT5_CARSTINT 0x00010000 -#define TX3912_INT5_POSCARINT 0x00008000 -#define TX3912_INT5_NEGCARINT 0x00004000 -#define TX3912_INT5_IOPOSINT6 0x00002000 -#define TX3912_INT5_IOPOSINT5 0x00001000 -#define TX3912_INT5_IOPOSINT4 0x00000800 -#define TX3912_INT5_IOPOSINT3 0x00000400 -#define TX3912_INT5_IOPOSINT2 0x00000200 -#define TX3912_INT5_IOPOSINT1 0x00000100 -#define TX3912_INT5_IOPOSINT0 0x00000080 -#define TX3912_INT5_IONEGINT6 0x00000040 -#define TX3912_INT5_IONEGINT5 0x00000020 -#define TX3912_INT5_IONEGINT4 0x00000010 -#define TX3912_INT5_IONEGINT3 0x00000008 -#define TX3912_INT5_IONEGINT2 0x00000004 -#define TX3912_INT5_IONEGINT1 0x00000002 -#define TX3912_INT5_IONEGINT0 0x00000001 - -/* - * Interrupt 6 status register values - */ -#define TX3912_INT6_STATUS_IRQHIGH 0x80000000 -#define TX3912_INT6_STATUS_IRQLOW 0x40000000 -#define TX3912_INT6_STATUS_reserved6 0x3fffffc0 -#define TX3912_INT6_STATUS_INTVEC_POSNEGPWROKINT 0x0000003c -#define TX3912_INT6_STATUS_INTVEC_ALARMINT 0x00000038 -#define TX3912_INT6_STATUS_INTVEC_PERINT 0x00000034 -#define TX3912_INT6_STATUS_INTVEC_reserved5 0x00000030 -#define TX3912_INT6_STATUS_INTVEC_UARTARXINT 0x0000002c -#define TX3912_INT6_STATUS_INTVEC_UARTBRXINT 0x00000028 -#define TX3912_INT6_STATUS_INTVEC_reserved4 0x00000024 -#define TX3912_INT6_STATUS_INTVEC_IOPOSINT65 0x00000020 -#define TX3912_INT6_STATUS_INTVEC_reserved3 0x0000001c -#define TX3912_INT6_STATUS_INTVEC_IONEGINT65 0x00000018 -#define TX3912_INT6_STATUS_INTVEC_reserved2 0x00000014 -#define TX3912_INT6_STATUS_INTVEC_SNDDMACNTINT 0x00000010 -#define TX3912_INT6_STATUS_INTVEC_TELDMACNTINT 0x0000000c -#define TX3912_INT6_STATUS_INTVEC_CHIDMACNTINT 0x00000008 -#define TX3912_INT6_STATUS_INTVEC_IOPOSNEGINT0 0x00000004 -#define TX3912_INT6_STATUS_INTVEC_STDHANDLER 0x00000000 -#define TX3912_INT6_STATUS_reserved1 0x00000003 - -/* - * Interrupt 6 enable register values - */ -#define TX3912_INT6_ENABLE_reserved5 0xfff80000 -#define TX3912_INT6_ENABLE_GLOBALEN 0x00040000 -#define TX3912_INT6_ENABLE_IRQPRITEST 0x00020000 -#define TX3912_INT6_ENABLE_IRQTEST 0x00010000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_POSNEGPWROKINT 0x00008000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_ALARMINT 0x00004000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_PERINT 0x00002000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved4 0x00001000 -#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT 0x00000800 -#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTBRXINT 0x00000400 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved3 0x00000200 -#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSINT65 0x00000100 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved2 0x00000080 -#define TX3912_INT6_ENABLE_PRIORITYMASK_IONEGINT65 0x00000040 -#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved1 0x00000020 -#define TX3912_INT6_ENABLE_PRIORITYMASK_SNDDMACNTINT 0x00000010 -#define TX3912_INT6_ENABLE_PRIORITYMASK_TELDMACNTINT 0x00000008 -#define TX3912_INT6_ENABLE_PRIORITYMASK_CHIDMACNTINT 0x00000004 -#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSNEGINT0 0x00000002 -#define TX3912_INT6_ENABLE_PRIORITYMASK_STDHANDLER 0x00000001 -#define TX3912_INT6_ENABLE_HIGH_PRIORITY 0x0000ffff - - -/***************************************************************************** - * Power Subsystem * - * --------------- * - * Chapter 11 in Philips PR31700 User Manual * - * Chapter 12 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_POWER_CTRL 0x01c4 - -/* - * Power control register values - */ -#define TX3912_POWER_CTRL_ONBUTN 0x80000000 -#define TX3912_POWER_CTRL_PWRINT 0x40000000 -#define TX3912_POWER_CTRL_PWROK 0x20000000 -#define TX3912_POWER_CTRL_VIDRF_MASK 0x18000000 -#define TX3912_POWER_CTRL_SLOWBUS 0x04000000 -#define TX3912_POWER_CTRL_DIVMOD 0x02000000 -#define TX3912_POWER_CTRL_reserved2 0x01ff0000 -#define TX3912_POWER_CTRL_STPTIMERVAL_MASK 0x0000f000 -#define TX3912_POWER_CTRL_ENSTPTIMER 0x00000800 -#define TX3912_POWER_CTRL_ENFORCESHUTDWN 0x00000400 -#define TX3912_POWER_CTRL_FORCESHUTDWN 0x00000200 -#define TX3912_POWER_CTRL_FORCESHUTDWNOCC 0x00000100 -#define TX3912_POWER_CTRL_SELC2MS 0x00000080 -#define TX3912_POWER_CTRL_reserved1 0x00000040 -#define TX3912_POWER_CTRL_BPDBVCC3 0x00000020 -#define TX3912_POWER_CTRL_STOPCPU 0x00000010 -#define TX3912_POWER_CTRL_DBNCONBUTN 0x00000008 -#define TX3912_POWER_CTRL_COLDSTART 0x00000004 -#define TX3912_POWER_CTRL_PWRCS 0x00000002 -#define TX3912_POWER_CTRL_VCCON 0x00000001 - - -/***************************************************************************** - * Timer Subsystem * - * --------------- * - * Chapter 14 in Philips PR31700 User Manual * - * Chapter 15 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_RTC_HIGH 0x0140 -#define TX3912_RTC_LOW 0x0144 -#define TX3912_RTC_ALARM_HIGH 0x0148 -#define TX3912_RTC_ALARM_LOW 0x014c -#define TX3912_TIMER_CTRL 0x0150 -#define TX3912_TIMER_PERIOD 0x0154 - -/* - * Timer control register values - */ -#define TX3912_TIMER_CTRL_FREEZEPRE 0x00000080 -#define TX3912_TIMER_CTRL_FREEZERTC 0x00000040 -#define TX3912_TIMER_CTRL_FREEZETIMER 0x00000020 -#define TX3912_TIMER_CTRL_ENPERTIMER 0x00000010 -#define TX3912_TIMER_CTRL_RTCCLEAR 0x00000008 -#define TX3912_TIMER_CTRL_TESTC8MS 0x00000004 -#define TX3912_TIMER_CTRL_ENTESTCLK 0x00000002 -#define TX3912_TIMER_CTRL_ENRTCTST 0x00000001 - -/* - * The periodic timer has granularity of 868 nanoseconds which - * results in a count of (1.152 x 10^6 / 100) in order to achieve - * a 10 millisecond periodic system clock. - */ -#define TX3912_SYS_TIMER_VALUE (1152000/HZ) - - -/***************************************************************************** - * UART Subsystem * - * -------------- * - * Chapter 15 in Philips PR31700 User Manual * - * Chapter 16 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_UARTA_CTRL1 0x00b0 -#define TX3912_UARTA_CTRL2 0x00b4 -#define TX3912_UARTA_DMA_CTRL1 0x00b8 -#define TX3912_UARTA_DMA_CTRL2 0x00bc -#define TX3912_UARTA_DMA_CNT 0x00c0 -#define TX3912_UARTA_DATA 0x00c4 -#define TX3912_UARTB_CTRL1 0x00c8 -#define TX3912_UARTB_CTRL2 0x00cc -#define TX3912_UARTB_DMA_CTRL1 0x00d0 -#define TX3912_UARTB_DMA_CTRL2 0x00d4 -#define TX3912_UARTB_DMA_CNT 0x00d8 -#define TX3912_UARTB_DATA 0x00dc - -/* - * UART Control Register 1 values - */ -#define TX3912_UART_CTRL1_UARTON 0x80000000 -#define TX3912_UART_CTRL1_EMPTY 0x40000000 -#define TX3912_UART_CTRL1_PRXHOLDFULL 0x20000000 -#define TX3912_UART_CTRL1_RXHOLDFULL 0x10000000 -#define TX3912_UART_CTRL1_reserved1 0x0fff0000 -#define TX3912_UART_CTRL1_ENDMARX 0x00008000 -#define TX3912_UART_CTRL1_ENDMATX 0x00004000 -#define TX3912_UART_CTRL1_TESTMODE 0x00002000 -#define TX3912_UART_CTRL1_ENBREAKHALT 0x00001000 -#define TX3912_UART_CTRL1_ENDMATEST 0x00000800 -#define TX3912_UART_CTRL1_ENDMALOOP 0x00000400 -#define TX3912_UART_CTRL1_PULSEOPT1 0x00000200 -#define TX3912_UART_CTRL1_PULSEOPT1 0x00000100 -#define TX3912_UART_CTRL1_DTINVERT 0x00000080 -#define TX3912_UART_CTRL1_DISTXD 0x00000040 -#define TX3912_UART_CTRL1_TWOSTOP 0x00000020 -#define TX3912_UART_CTRL1_LOOPBACK 0x00000010 -#define TX3912_UART_CTRL1_BIT_7 0x00000008 -#define TX3912_UART_CTRL1_EVENPARITY 0x00000004 -#define TX3912_UART_CTRL1_ENPARITY 0x00000002 -#define TX3912_UART_CTRL1_ENUART 0x00000001 - -/* - * UART Control Register 2 values - */ -#define TX3912_UART_CTRL2_B230400 0x0000 /* 0 */ -#define TX3912_UART_CTRL2_B115200 0x0001 /* 1 */ -#define TX3912_UART_CTRL2_B76800 0x0002 /* 2 */ -#define TX3912_UART_CTRL2_B57600 0x0003 /* 3 */ -#define TX3912_UART_CTRL2_B38400 0x0005 /* 5 */ -#define TX3912_UART_CTRL2_B19200 0x000b /* 11 */ -#define TX3912_UART_CTRL2_B9600 0x0016 /* 22 */ -#define TX3912_UART_CTRL2_B4800 0x002f /* 47 */ -#define TX3912_UART_CTRL2_B2400 0x005f /* 95 */ -#define TX3912_UART_CTRL2_B1200 0x00bf /* 191 */ -#define TX3912_UART_CTRL2_B600 0x017f /* 383 */ -#define TX3912_UART_CTRL2_B300 0x02ff /* 767 */ - -/***************************************************************************** - * Video Subsystem * - * --------------- * - * Chapter 16 in Philips PR31700 User Manual * - * Chapter 17 in Toshiba TMPR3905/12 User Manual * - *****************************************************************************/ -#define TX3912_VIDEO_CTRL1 0x0028 -#define TX3912_VIDEO_CTRL2 0x002c -#define TX3912_VIDEO_CTRL3 0x0030 -#define TX3912_VIDEO_CTRL4 0x0034 -#define TX3912_VIDEO_CTRL5 0x0038 -#define TX3912_VIDEO_CTRL6 0x003c -#define TX3912_VIDEO_CTRL7 0x0040 -#define TX3912_VIDEO_CTRL8 0x0044 -#define TX3912_VIDEO_CTRL9 0x0048 -#define TX3912_VIDEO_CTRL10 0x004c -#define TX3912_VIDEO_CTRL11 0x0050 -#define TX3912_VIDEO_CTRL12 0x0054 -#define TX3912_VIDEO_CTRL13 0x0058 -#define TX3912_VIDEO_CTRL14 0x005c - -/* - * Video Control Register 1 values - */ -#define TX3912_VIDEO_CTRL1_LINECNT 0xffc00000 -#define TX3912_VIDEO_CTRL1_LOADDLY 0x00200000 -#define TX3912_VIDEO_CTRL1_BAUDVAL 0x001f0000 -#define TX3912_VIDEO_CTRL1_VIDDONEVAL 0x0000fe00 -#define TX3912_VIDEO_CTRL1_ENFREEZEFRAME 0x00000100 -#define TX3912_VIDEO_CTRL1_BITSEL_MASK 0x000000c0 -#define TX3912_VIDEO_CTRL1_BITSEL_8BIT_COLOR 0x000000c0 -#define TX3912_VIDEO_CTRL1_BITSEL_4BIT_GRAY 0x00000080 -#define TX3912_VIDEO_CTRL1_BITSEL_2BIT_GRAY 0x00000040 -#define TX3912_VIDEO_CTRL1_DISPSPLIT 0x00000020 -#define TX3912_VIDEO_CTRL1_DISP8 0x00000010 -#define TX3912_VIDEO_CTRL1_DFMODE 0x00000008 -#define TX3912_VIDEO_CTRL1_INVVID 0x00000004 -#define TX3912_VIDEO_CTRL1_DISPON 0x00000002 -#define TX3912_VIDEO_CTRL1_ENVID 0x00000001 - -#endif /* _TX3912_H_ */ diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index 94bef03d9635..a60649569c2c 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -50,6 +50,8 @@ #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) -#define RBTX4927_RTL_8019_IRQ (29) +#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) + +int toshiba_rbtx4927_irq_nested(int sw_irq); #endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index de85bd2245f7..4bd4368e188c 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -28,6 +28,7 @@ #define __ASM_TX4927_TX4927_H #include <asm/tx4927/tx4927_mips.h> +#include <asm/txx9irq.h> /* This register naming came from the integrated CPU/controller name TX4927 @@ -421,32 +422,6 @@ #define TX4927_PIO_LIMIT 0xf50f -/* TX4927 Interrupt Controller (32-bit registers) */ -#define TX4927_IRC_BASE 0xf510 -#define TX4927_IRC_IRFLAG0 0xf510 -#define TX4927_IRC_IRFLAG1 0xf514 -#define TX4927_IRC_IRPOL 0xf518 -#define TX4927_IRC_IRRCNT 0xf51c -#define TX4927_IRC_IRMASKINT 0xf520 -#define TX4927_IRC_IRMASKEXT 0xf524 -#define TX4927_IRC_IRDEN 0xf600 -#define TX4927_IRC_IRDM0 0xf604 -#define TX4927_IRC_IRDM1 0xf608 -#define TX4927_IRC_IRLVL0 0xf610 -#define TX4927_IRC_IRLVL1 0xf614 -#define TX4927_IRC_IRLVL2 0xf618 -#define TX4927_IRC_IRLVL3 0xf61c -#define TX4927_IRC_IRLVL4 0xf620 -#define TX4927_IRC_IRLVL5 0xf624 -#define TX4927_IRC_IRLVL6 0xf628 -#define TX4927_IRC_IRLVL7 0xf62c -#define TX4927_IRC_IRMSK 0xf640 -#define TX4927_IRC_IREDC 0xf660 -#define TX4927_IRC_IRPND 0xf680 -#define TX4927_IRC_IRCS 0xf6a0 -#define TX4927_IRC_LIMIT 0xf6ff - - /* TX4927 AC-link controller (32-bit registers) */ #define TX4927_ACLC_BASE 0xf700 #define TX4927_ACLC_ACCTLEN 0xf700 @@ -493,25 +468,11 @@ #define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) +#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - - -#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ -#define MI8259_IRQ_ISA_RAW_END 15 -#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */ -#define TX4927_IRQ_CP0_RAW_END 7 -#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */ -#define TX4927_IRQ_PIC_RAW_END 31 - - -#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ -#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ - -#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */ -#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */ - -#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */ -#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */ +#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) #define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 66c064690f41..f98b2bb719d5 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -48,7 +48,7 @@ #define TX4927_PCI_CLK_ACK 0x04 #define TX4927_PCI_CLK_ACE 0x02 #define TX4927_PCI_CLK_ENDIAN 0x01 -#define TX4927_NR_IRQ_LOCAL (8+16) +#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG #define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ #define TX4927_IR_PCIC 16 @@ -99,21 +99,6 @@ struct tx4927_ccfg_reg { volatile unsigned long long ramp; }; -struct tx4927_irc_reg { - volatile unsigned long cer; - volatile unsigned long cr[2]; - volatile unsigned long unused0; - volatile unsigned long ilr[8]; - volatile unsigned long unused1[4]; - volatile unsigned long imr; - volatile unsigned long unused2[7]; - volatile unsigned long scr; - volatile unsigned long unused3[7]; - volatile unsigned long ssr; - volatile unsigned long unused4[7]; - volatile unsigned long csr; -}; - struct tx4927_pcic_reg { volatile unsigned long pciid; volatile unsigned long pcistatus; @@ -182,11 +167,6 @@ struct tx4927_pcic_reg { #endif /* _LANGUAGE_ASSEMBLY */ -/* IRCSR : Int. Current Status */ -#define TX4927_IRCSR_IF 0x00010000 -#define TX4927_IRCSR_ILV_MASK 0x00000700 -#define TX4927_IRCSR_IVL_MASK 0x0000001f - /* * PCIC */ @@ -278,7 +258,6 @@ struct tx4927_pcic_reg { #define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) #define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) #define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) -#define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG) #endif /* _LANGUAGE_ASSEMBLY */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index 0fbedafdcea8..b14acb575be2 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h @@ -14,6 +14,7 @@ #include <asm/addrspace.h> #include <asm/tx4938/tx4938.h> +#include <asm/txx9irq.h> /* CS */ #define RBTX4938_CE0 0x1c000000 /* 64M */ @@ -105,12 +106,6 @@ #define rbtx4938_pcireset_ptr \ ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) -/* SPI */ -#define RBTX4938_SEEPROM1_CHIPID 0 -#define RBTX4938_SEEPROM2_CHIPID 1 -#define RBTX4938_SEEPROM3_CHIPID 2 -#define RBTX4938_SRTC_CHIPID 3 - /* * IRQ mappings */ @@ -129,21 +124,11 @@ #define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ #define RBTX4938_NR_IRQ_IOC 8 -#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ -#define MI8259_IRQ_ISA_RAW_END 15 -#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */ -#define TX4938_IRQ_CP0_RAW_END 7 -#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */ -#define TX4938_IRQ_PIC_RAW_END 31 - -#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ -#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ +#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) -#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */ -#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */ - -#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */ -#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */ +#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) #define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) #define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) #define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) @@ -198,10 +183,4 @@ #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) #define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) -/* IRCR : Int. Control */ -#define TX4938_IRCR_LOW 0x00000000 -#define TX4938_IRCR_HIGH 0x00000001 -#define TX4938_IRCR_DOWN 0x00000002 -#define TX4938_IRCR_UP 0x00000003 - #endif /* __ASM_TX_BOARDS_RBTX4938_H */ diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h index 0dbbab820a5a..6a60c83e152b 100644 --- a/include/asm-mips/tx4938/spi.h +++ b/include/asm-mips/tx4938/spi.h @@ -14,61 +14,7 @@ #ifndef __ASM_TX_BOARDS_TX4938_SPI_H #define __ASM_TX_BOARDS_TX4938_SPI_H -/* SPI */ -struct spi_dev_desc { - unsigned int baud; - unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */ - unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */ - unsigned int polarity:1; /* 0:High-Active */ - unsigned int phase:1; /* 0:Sample-Then-Shift */ -}; - -extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init; -extern void txx9_spi_irqinit(int irc_irq) __init; -extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc, - unsigned char **inbufs, unsigned int *incounts, - unsigned char **outbufs, unsigned int *outcounts, - int cansleep); -extern int spi_eeprom_write_enable(int chipid, int enable); -extern int spi_eeprom_read_status(int chipid); +extern int spi_eeprom_register(int chipid); extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); -extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len); -extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init; - -#define TXX9_IMCLK (txx9_gbus_clock / 2) - -/* -* SPI -*/ - -/* SPMCR : SPI Master Control */ -#define TXx9_SPMCR_OPMODE 0xc0 -#define TXx9_SPMCR_CONFIG 0x40 -#define TXx9_SPMCR_ACTIVE 0x80 -#define TXx9_SPMCR_SPSTP 0x02 -#define TXx9_SPMCR_BCLR 0x01 - -/* SPCR0 : SPI Status */ -#define TXx9_SPCR0_TXIFL_MASK 0xc000 -#define TXx9_SPCR0_RXIFL_MASK 0x3000 -#define TXx9_SPCR0_SIDIE 0x0800 -#define TXx9_SPCR0_SOEIE 0x0400 -#define TXx9_SPCR0_RBSIE 0x0200 -#define TXx9_SPCR0_TBSIE 0x0100 -#define TXx9_SPCR0_IFSPSE 0x0010 -#define TXx9_SPCR0_SBOS 0x0004 -#define TXx9_SPCR0_SPHA 0x0002 -#define TXx9_SPCR0_SPOL 0x0001 - -/* SPSR : SPI Status */ -#define TXx9_SPSR_TBSI 0x8000 -#define TXx9_SPSR_RBSI 0x4000 -#define TXx9_SPSR_TBS_MASK 0x3800 -#define TXx9_SPSR_RBS_MASK 0x0700 -#define TXx9_SPSR_SPOE 0x0080 -#define TXx9_SPSR_IFSD 0x0008 -#define TXx9_SPSR_SIDLE 0x0004 -#define TXx9_SPSR_STRDY 0x0002 -#define TXx9_SPSR_SRRDY 0x0001 #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h index e25b1a0975cb..afdb19813ca1 100644 --- a/include/asm-mips/tx4938/tx4938.h +++ b/include/asm-mips/tx4938/tx4938.h @@ -272,20 +272,6 @@ struct tx4938_pio_reg { volatile unsigned long maskcpu; volatile unsigned long maskext; }; -struct tx4938_irc_reg { - volatile unsigned long cer; - volatile unsigned long cr[2]; - volatile unsigned long unused0; - volatile unsigned long ilr[8]; - volatile unsigned long unused1[4]; - volatile unsigned long imr; - volatile unsigned long unused2[7]; - volatile unsigned long scr; - volatile unsigned long unused3[7]; - volatile unsigned long ssr; - volatile unsigned long unused4[7]; - volatile unsigned long csr; -}; struct tx4938_ndfmc_reg { endian_def_l2(unused0, dtr); @@ -646,39 +632,12 @@ struct tx4938_ccfg_reg { #define TX4938_DMA_CSR_DESERR 0x00000002 #define TX4938_DMA_CSR_SORERR 0x00000001 -/* TX4938 Interrupt Controller (32-bit registers) */ -#define TX4938_IRC_BASE 0xf510 -#define TX4938_IRC_IRFLAG0 0xf510 -#define TX4938_IRC_IRFLAG1 0xf514 -#define TX4938_IRC_IRPOL 0xf518 -#define TX4938_IRC_IRRCNT 0xf51c -#define TX4938_IRC_IRMASKINT 0xf520 -#define TX4938_IRC_IRMASKEXT 0xf524 -#define TX4938_IRC_IRDEN 0xf600 -#define TX4938_IRC_IRDM0 0xf604 -#define TX4938_IRC_IRDM1 0xf608 -#define TX4938_IRC_IRLVL0 0xf610 -#define TX4938_IRC_IRLVL1 0xf614 -#define TX4938_IRC_IRLVL2 0xf618 -#define TX4938_IRC_IRLVL3 0xf61c -#define TX4938_IRC_IRLVL4 0xf620 -#define TX4938_IRC_IRLVL5 0xf624 -#define TX4938_IRC_IRLVL6 0xf628 -#define TX4938_IRC_IRLVL7 0xf62c -#define TX4938_IRC_IRMSK 0xf640 -#define TX4938_IRC_IREDC 0xf660 -#define TX4938_IRC_IRPND 0xf680 -#define TX4938_IRC_IRCS 0xf6a0 -#define TX4938_IRC_LIMIT 0xf6ff - - #ifndef __ASSEMBLY__ #define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) #define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) #define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) #define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) -#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG) #define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) #define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) #define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index ed16de0a6398..fa9a587b3bf1 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -340,16 +340,17 @@ #define __NR_signalfd (__NR_Linux + 317) #define __NR_timerfd (__NR_Linux + 318) #define __NR_eventfd (__NR_Linux + 319) +#define __NR_fallocate (__NR_Linux + 320) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 319 +#define __NR_Linux_syscalls 320 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 319 +#define __NR_O32_Linux_syscalls 320 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -636,16 +637,17 @@ #define __NR_signalfd (__NR_Linux + 276) #define __NR_timerfd (__NR_Linux + 277) #define __NR_eventfd (__NR_Linux + 278) +#define __NR_fallocate (__NR_Linux + 279) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 278 +#define __NR_Linux_syscalls 279 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 278 +#define __NR_64_Linux_syscalls 279 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -936,16 +938,17 @@ #define __NR_signalfd (__NR_Linux + 280) #define __NR_timerfd (__NR_Linux + 281) #define __NR_eventfd (__NR_Linux + 282) +#define __NR_fallocate (__NR_Linux + 283) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 282 +#define __NR_Linux_syscalls 283 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 282 +#define __NR_N32_Linux_syscalls 283 #ifdef __KERNEL__ diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h index 8109cda557dc..0bcdd3a5c256 100644 --- a/include/asm-mips/vr41xx/giu.h +++ b/include/asm-mips/vr41xx/giu.h @@ -20,6 +20,15 @@ #ifndef __NEC_VR41XX_GIU_H #define __NEC_VR41XX_GIU_H +/* + * NEC VR4100 series GIU platform device IDs. + */ +enum { + GPIO_50PINS_PULLUPDOWN, + GPIO_36PINS, + GPIO_48PINS_EDGE_SELECT, +}; + typedef enum { IRQ_TRIGGER_LEVEL, IRQ_TRIGGER_EDGE, diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h index 1fcf6e8082b4..98cdb4096485 100644 --- a/include/asm-mips/vr41xx/siu.h +++ b/include/asm-mips/vr41xx/siu.h @@ -20,6 +20,8 @@ #ifndef __NEC_VR41XX_SIU_H #define __NEC_VR41XX_SIU_H +#define SIU_PORTS_MAX 2 + typedef enum { SIU_INTERFACE_RS232C, SIU_INTERFACE_IRDA, diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index ec0eeebd8802..c0715d0a6b28 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -169,10 +169,9 @@ /* * On the RM9000 there is a problem which makes the CreateDirtyExclusive - * cache operation unusable on SMP systems. + * eache operation unusable on SMP systems. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ - defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) #define RM9000_CDEX_SMP_WAR 1 #endif @@ -182,15 +181,12 @@ * I-cache line worth of instructions being fetched may case spurious * exceptions. */ -#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \ - defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \ - defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \ - defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \ +#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ + defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \ defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif - /* * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. @@ -200,6 +196,14 @@ #endif /* + * 34K core erratum: "Problems Executing the TLBR Instruction" + */ +#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ + defined(CONFIG_PMC_MSP7120_FPGA) +#define MIPS34K_MISSED_ITLB_WAR 1 +#endif + +/* * Workarounds default to off */ #ifndef ICACHE_REFILLS_WORKAROUND_WAR @@ -238,5 +242,8 @@ #ifndef R10000_LLSC_WAR #define R10000_LLSC_WAR 0 #endif +#ifndef MIPS34K_MISSED_ITLB_WAR +#define MIPS34K_MISSED_ITLB_WAR 0 +#endif #endif /* _ASM_WAR_H */ diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h deleted file mode 100644 index 6aa90cae1114..000000000000 --- a/include/asm-mips/watch.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle - */ -#ifndef _ASM_WATCH_H -#define _ASM_WATCH_H - -#include <linux/linkage.h> - -/* - * Types of reference for watch_set() - */ -enum wref_type { - wr_save = 1, - wr_load = 2 -}; - -extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref); -extern asmlinkage void __watch_clear(void); -extern asmlinkage void __watch_reenable(void); - -#define watch_set(addr, ref) \ - if (cpu_has_watch) \ - __watch_set(addr, ref) -#define watch_clear() \ - if (cpu_has_watch) \ - __watch_clear() -#define watch_reenable() \ - if (cpu_has_watch) \ - __watch_reenable() - -#endif /* _ASM_WATCH_H */ |