diff options
Diffstat (limited to 'include/dt-bindings/clock/imx8qxp-clock.h')
| -rw-r--r-- | include/dt-bindings/clock/imx8qxp-clock.h | 70 |
1 files changed, 57 insertions, 13 deletions
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h index 0bdc9ee03d96..96205ba0c158 100644 --- a/include/dt-bindings/clock/imx8qxp-clock.h +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -273,6 +273,7 @@ #define IMX8QXP_MLB_IPG_CLK 244 /* Display controller SS */ +/* DC part1 */ #define IMX8QXP_DC_AXI_EXT_CLK 245 #define IMX8QXP_DC_AXI_INT_CLK 246 #define IMX8QXP_DC_CFG_CLK 247 @@ -301,19 +302,20 @@ #define IMX8QXP_DC0_RTRAM0_CLK 270 #define IMX8QXP_DC0_RTRAM1_CLK 271 +/* MIPI-LVDS part1 */ #define IMX8QXP_MIPI_IPG_CLK 272 -#define IMX8QXP_MIPI_I2C0_DIV 273 -#define IMX8QXP_MIPI_I2C1_DIV 274 -#define IMX8QXP_MIPI_I2C0_CLK 275 -#define IMX8QXP_MIPI_I2C1_CLK 276 -#define IMX8QXP_MIPI_I2C0_IPG_S_CLK 277 -#define IMX8QXP_MIPI_I2C0_IPG_CLK 278 -#define IMX8QXP_MIPI_I2C1_IPG_S_CLK 279 -#define IMX8QXP_MIPI_I2C1_IPG_CLK 280 -#define IMX8QXP_MIPI_PWM_IPG_S_CLK 281 -#define IMX8QXP_MIPI_PWM_IPG_CLK 282 -#define IMX8QXP_MIPI_PWM_32K_CLK 283 -#define IMX8QXP_MIPI_GPIO_IPG_CLK 284 +#define IMX8QXP_MIPI0_I2C0_DIV 273 +#define IMX8QXP_MIPI0_I2C1_DIV 274 +#define IMX8QXP_MIPI0_I2C0_CLK 275 +#define IMX8QXP_MIPI0_I2C1_CLK 276 +#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277 +#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278 +#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279 +#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280 +#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281 +#define IMX8QXP_MIPI0_PWM_IPG_CLK 282 +#define IMX8QXP_MIPI0_PWM_32K_CLK 283 +#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284 #define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285 #define IMX8QXP_IMG_JPEG_ENC_CLK 286 @@ -479,5 +481,47 @@ #define IMX8QXP_AUD_HIFI_CORE_CLK 437 #define IMX8QXP_AUD_OCRAM_IPG 438 -#define IMX8QXP_CLK_END 439 +/* DC part2 */ +#define IMX8QXP_DC0_DISP0_DIV 439 +#define IMX8QXP_DC0_DISP1_DIV 440 +#define IMX8QXP_DC0_BYPASS_0_DIV 441 +#define IMX8QXP_DC0_BYPASS_1_DIV 442 +#define IMX8QXP_DC0_PLL0_DIV 443 +#define IMX8QXP_DC0_PLL1_DIV 444 +#define IMX8QXP_DC0_PLL0_CLK 445 +#define IMX8QXP_DC0_PLL1_CLK 446 + +/* MIPI-LVDS part2 */ +#define IMX8QXP_MIPI0_BYPASS_CLK 447 +#define IMX8QXP_MIPI0_PIXEL_DIV 448 +#define IMX8QXP_MIPI0_PIXEL_CLK 449 +#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450 +#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451 +#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452 +#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453 +#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454 +#define IMX8QXP_MIPI0_LIS_IPG_CLK 455 +#define IMX8QXP_MIPI1_I2C0_DIV 456 +#define IMX8QXP_MIPI1_I2C1_DIV 457 +#define IMX8QXP_MIPI1_I2C0_CLK 458 +#define IMX8QXP_MIPI1_I2C1_CLK 459 +#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 460 +#define IMX8QXP_MIPI1_I2C0_IPG_CLK 461 +#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 462 +#define IMX8QXP_MIPI1_I2C1_IPG_CLK 463 +#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 464 +#define IMX8QXP_MIPI1_PWM_IPG_CLK 465 +#define IMX8QXP_MIPI1_PWM_32K_CLK 466 +#define IMX8QXP_MIPI1_GPIO_IPG_CLK 467 +#define IMX8QXP_MIPI1_BYPASS_CLK 468 +#define IMX8QXP_MIPI1_PIXEL_DIV 469 +#define IMX8QXP_MIPI1_PIXEL_CLK 470 +#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 471 +#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 472 +#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 473 +#define IMX8QXP_MIPI1_LVDS_PHY_DIV 474 +#define IMX8QXP_MIPI1_LVDS_PHY_CLK 475 +#define IMX8QXP_MIPI1_LIS_IPG_CLK 476 + +#define IMX8QXP_CLK_END 477 #endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ |