diff options
Diffstat (limited to 'include')
849 files changed, 48928 insertions, 9350 deletions
diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h index 2b41e47b7d80..2f6ab189fc6f 100644 --- a/include/acpi/acconfig.h +++ b/include/acpi/acconfig.h @@ -64,7 +64,7 @@ /* Version string */ -#define ACPI_CA_VERSION 0x20050309 +#define ACPI_CA_VERSION 0x20050408 /* * OS name, used for the _OS object. The _OS object is essentially obsolete, @@ -130,9 +130,8 @@ #define ACPI_MAX_GPE_BLOCKS 2 #define ACPI_GPE_REGISTER_WIDTH 8 -/* - * Method info (in WALK_STATE), containing local variables and argumetns - */ +/* Method info (in WALK_STATE), containing local variables and argumetns */ + #define ACPI_METHOD_NUM_LOCALS 8 #define ACPI_METHOD_MAX_LOCAL 7 diff --git a/include/acpi/acdebug.h b/include/acpi/acdebug.h index 223b2a506e49..8ba372b0f245 100644 --- a/include/acpi/acdebug.h +++ b/include/acpi/acdebug.h @@ -61,9 +61,7 @@ struct argument_info #define PARAM_LIST(pl) pl - #define DBTEST_OUTPUT_LEVEL(lvl) if (acpi_gbl_db_opt_verbose) - #define VERBOSE_PRINT(fp) DBTEST_OUTPUT_LEVEL(lvl) {\ acpi_os_printf PARAM_LIST(fp);} @@ -71,13 +69,9 @@ struct argument_info #define EX_SINGLE_STEP 2 -/* Prototypes */ - - /* * dbxface - external debugger interfaces */ - acpi_status acpi_db_initialize ( void); @@ -92,20 +86,10 @@ acpi_db_single_step ( union acpi_parse_object *op, u32 op_type); -acpi_status -acpi_db_start_command ( - struct acpi_walk_state *walk_state, - union acpi_parse_object *op); - -void -acpi_db_method_end ( - struct acpi_walk_state *walk_state); - /* * dbcmds - debug commands and output routines */ - acpi_status acpi_db_disassemble_method ( char *name); @@ -177,57 +161,30 @@ acpi_db_find_references ( char *object_arg); void -acpi_db_display_locks (void); - +acpi_db_display_locks ( + void); void acpi_db_display_resources ( char *object_arg); void -acpi_db_display_gpes (void); +acpi_db_display_gpes ( + void); void acpi_db_check_integrity ( void); -acpi_status -acpi_db_integrity_walk ( - acpi_handle obj_handle, - u32 nesting_level, - void *context, - void **return_value); - -acpi_status -acpi_db_walk_and_match_name ( - acpi_handle obj_handle, - u32 nesting_level, - void *context, - void **return_value); - -acpi_status -acpi_db_walk_for_references ( - acpi_handle obj_handle, - u32 nesting_level, - void *context, - void **return_value); - -acpi_status -acpi_db_walk_for_specific_objects ( - acpi_handle obj_handle, - u32 nesting_level, - void *context, - void **return_value); - void acpi_db_generate_gpe ( char *gpe_arg, char *block_arg); + /* * dbdisply - debug display commands */ - void acpi_db_display_method_info ( union acpi_parse_object *op); @@ -271,19 +228,10 @@ acpi_db_display_argument_object ( union acpi_operand_object *obj_desc, struct acpi_walk_state *walk_state); -void -acpi_db_dump_parser_descriptor ( - union acpi_parse_object *op); - -void * -acpi_db_get_pointer ( - void *target); - /* * dbexec - debugger control method execution */ - void acpi_db_execute ( char *name, @@ -296,44 +244,15 @@ acpi_db_create_execution_threads ( char *num_loops_arg, char *method_name_arg); -acpi_status -acpi_db_execute_method ( - struct acpi_db_method_info *info, - struct acpi_buffer *return_obj); - -void -acpi_db_execute_setup ( - struct acpi_db_method_info *info); - -u32 -acpi_db_get_outstanding_allocations ( - void); - -void ACPI_SYSTEM_XFACE -acpi_db_method_thread ( - void *context); - -acpi_status -acpi_db_execution_walk ( - acpi_handle obj_handle, - u32 nesting_level, - void *context, - void **return_value); - /* * dbfileio - Debugger file I/O commands */ - acpi_object_type acpi_db_match_argument ( char *user_argument, struct argument_info *arguments); -acpi_status -ae_local_load_table ( - struct acpi_table_header *table_ptr); - void acpi_db_close_debug_file ( void); @@ -356,16 +275,17 @@ acpi_db_read_table_from_file ( char *filename, struct acpi_table_header **table); + /* * dbhistry - debugger HISTORY command */ - void acpi_db_add_to_history ( char *command_line); void -acpi_db_display_history (void); +acpi_db_display_history ( + void); char * acpi_db_get_from_history ( @@ -375,7 +295,6 @@ acpi_db_get_from_history ( /* * dbinput - user front-end to the AML debugger */ - acpi_status acpi_db_command_dispatch ( char *input_buffer, @@ -386,71 +305,28 @@ void ACPI_SYSTEM_XFACE acpi_db_execute_thread ( void *context); -void -acpi_db_display_help ( - char *help_type); - -char * -acpi_db_get_next_token ( - char *string, - char **next); - -u32 -acpi_db_get_line ( - char *input_buffer); - -u32 -acpi_db_match_command ( - char *user_command); - -void -acpi_db_single_thread ( - void); - /* * dbstats - Generation and display of ACPI table statistics */ - void acpi_db_generate_statistics ( union acpi_parse_object *root, u8 is_method); - acpi_status acpi_db_display_statistics ( char *type_arg); -acpi_status -acpi_db_classify_one_object ( - acpi_handle obj_handle, - u32 nesting_level, - void *context, - void **return_value); - -void -acpi_db_count_namespace_objects ( - void); - -void -acpi_db_enumerate_object ( - union acpi_operand_object *obj_desc); - /* * dbutils - AML debugger utilities */ - void acpi_db_set_output_destination ( u32 where); void -acpi_db_dump_buffer ( - u32 address); - -void acpi_db_dump_object ( union acpi_object *obj_desc, u32 level); @@ -459,14 +335,8 @@ void acpi_db_prep_namestring ( char *name); - -acpi_status -acpi_db_second_pass_parse ( - union acpi_parse_object *root); - struct acpi_namespace_node * acpi_db_local_ns_lookup ( char *name); - #endif /* __ACDEBUG_H__ */ diff --git a/include/acpi/acdisasm.h b/include/acpi/acdisasm.h index 26d907eae6fe..dbfa877121ba 100644 --- a/include/acpi/acdisasm.h +++ b/include/acpi/acdisasm.h @@ -102,58 +102,16 @@ acpi_status (*asl_walk_callback) ( /* * dmwalk */ - -void -acpi_dm_walk_parse_tree ( - union acpi_parse_object *op, - asl_walk_callback descending_callback, - asl_walk_callback ascending_callback, - void *context); - -acpi_status -acpi_dm_descending_op ( - union acpi_parse_object *op, - u32 level, - void *context); - -acpi_status -acpi_dm_ascending_op ( - union acpi_parse_object *op, - u32 level, - void *context); - - -/* - * dmopcode - */ - -void -acpi_dm_validate_name ( - char *name, - union acpi_parse_object *op); - -u32 -acpi_dm_dump_name ( - char *name); - -void -acpi_dm_unicode ( - union acpi_parse_object *op); - void acpi_dm_disassemble ( struct acpi_walk_state *walk_state, union acpi_parse_object *origin, u32 num_opcodes); -void -acpi_dm_namestring ( - char *name); - -void -acpi_dm_display_path ( - union acpi_parse_object *op); +/* + * dmopcode + */ void acpi_dm_disassemble_one_op ( struct acpi_walk_state *walk_state, @@ -165,18 +123,9 @@ acpi_dm_decode_internal_object ( union acpi_operand_object *obj_desc); u32 -acpi_dm_block_type ( - union acpi_parse_object *op); - -u32 acpi_dm_list_type ( union acpi_parse_object *op); -acpi_status -acpi_ps_display_object_pathname ( - struct acpi_walk_state *walk_state, - union acpi_parse_object *op); - void acpi_dm_method_flags ( union acpi_parse_object *op); @@ -197,10 +146,6 @@ void acpi_dm_match_op ( union acpi_parse_object *op); -void -acpi_dm_match_keyword ( - union acpi_parse_object *op); - u8 acpi_dm_comma_if_list_member ( union acpi_parse_object *op); @@ -211,13 +156,25 @@ acpi_dm_comma_if_field_member ( /* - * dmobject + * dmnames */ +u32 +acpi_dm_dump_name ( + char *name); + +acpi_status +acpi_ps_display_object_pathname ( + struct acpi_walk_state *walk_state, + union acpi_parse_object *op); void -acpi_dm_decode_node ( - struct acpi_namespace_node *node); +acpi_dm_namestring ( + char *name); + +/* + * dmobject + */ void acpi_dm_display_internal_object ( union acpi_operand_object *obj_desc, @@ -241,6 +198,16 @@ acpi_dm_dump_method_info ( /* * dmbuffer */ +void +acpi_dm_disasm_byte_list ( + u32 level, + u8 *byte_data, + u32 byte_count); + +void +acpi_dm_byte_list ( + struct acpi_op_walk_info *info, + union acpi_parse_object *op); void acpi_is_eisa_id ( @@ -262,18 +229,6 @@ acpi_dm_is_string_buffer ( /* * dmresrc */ - -void -acpi_dm_disasm_byte_list ( - u32 level, - u8 *byte_data, - u32 byte_count); - -void -acpi_dm_byte_list ( - struct acpi_op_walk_info *info, - union acpi_parse_object *op); - void acpi_dm_resource_descriptor ( struct acpi_op_walk_info *info, @@ -296,19 +251,10 @@ void acpi_dm_decode_attribute ( u8 attribute); + /* * dmresrcl */ - -void -acpi_dm_io_flags ( - u8 flags); - -void -acpi_dm_memory_flags ( - u8 flags, - u8 specific_flags); - void acpi_dm_word_descriptor ( struct asl_word_address_desc *resource, @@ -373,7 +319,6 @@ acpi_dm_vendor_large_descriptor ( /* * dmresrcs */ - void acpi_dm_irq_descriptor ( struct asl_irq_format_desc *resource, @@ -420,7 +365,6 @@ acpi_dm_vendor_small_descriptor ( /* * dmutils */ - void acpi_dm_add_to_external_list ( char *path); diff --git a/include/acpi/acdispat.h b/include/acpi/acdispat.h index 237d63433581..8f5f2f71b1de 100644 --- a/include/acpi/acdispat.h +++ b/include/acpi/acdispat.h @@ -50,40 +50,9 @@ #define NAMEOF_ARG_NTE "__A0" -/* Common interfaces */ - -acpi_status -acpi_ds_obj_stack_push ( - void *object, - struct acpi_walk_state *walk_state); - -acpi_status -acpi_ds_obj_stack_pop ( - u32 pop_count, - struct acpi_walk_state *walk_state); - -#ifdef ACPI_FUTURE_USAGE -void * -acpi_ds_obj_stack_get_value ( - u32 index, - struct acpi_walk_state *walk_state); -#endif - -acpi_status -acpi_ds_obj_stack_pop_object ( - union acpi_operand_object **object, - struct acpi_walk_state *walk_state); - - -/* dsopcode - support for late evaluation */ - -acpi_status -acpi_ds_execute_arguments ( - struct acpi_namespace_node *node, - struct acpi_namespace_node *scope_node, - u32 aml_length, - u8 *aml_start); - +/* + * dsopcode - support for late evaluation + */ acpi_status acpi_ds_get_buffer_field_arguments ( union acpi_operand_object *obj_desc); @@ -101,15 +70,6 @@ acpi_ds_get_package_arguments ( union acpi_operand_object *obj_desc); acpi_status -acpi_ds_init_buffer_field ( - u16 aml_opcode, - union acpi_operand_object *obj_desc, - union acpi_operand_object *buffer_desc, - union acpi_operand_object *offset_desc, - union acpi_operand_object *length_desc, - union acpi_operand_object *result_desc); - -acpi_status acpi_ds_eval_buffer_field_operands ( struct acpi_walk_state *walk_state, union acpi_parse_object *op); @@ -130,9 +90,9 @@ acpi_ds_initialize_region ( acpi_handle obj_handle); -/* dsctrl - Parser/Interpreter interface, control stack routines */ - - +/* + * dsctrl - Parser/Interpreter interface, control stack routines + */ acpi_status acpi_ds_exec_begin_control_op ( struct acpi_walk_state *walk_state, @@ -144,9 +104,9 @@ acpi_ds_exec_end_control_op ( union acpi_parse_object *op); -/* dsexec - Parser/Interpreter interface, method execution callbacks */ - - +/* + * dsexec - Parser/Interpreter interface, method execution callbacks + */ acpi_status acpi_ds_get_predicate_value ( struct acpi_walk_state *walk_state, @@ -162,14 +122,9 @@ acpi_ds_exec_end_op ( struct acpi_walk_state *state); -/* dsfield - Parser/Interpreter interface for AML fields */ - -acpi_status -acpi_ds_get_field_names ( - struct acpi_create_field_info *info, - struct acpi_walk_state *walk_state, - union acpi_parse_object *arg); - +/* + * dsfield - Parser/Interpreter interface for AML fields + */ acpi_status acpi_ds_create_field ( union acpi_parse_object *op, @@ -199,8 +154,9 @@ acpi_ds_init_field_objects ( struct acpi_walk_state *walk_state); -/* dsload - Parser/Interpreter interface, namespace load callbacks */ - +/* + * dsload - Parser/Interpreter interface, namespace load callbacks + */ acpi_status acpi_ds_load1_begin_op ( struct acpi_walk_state *walk_state, @@ -225,9 +181,9 @@ acpi_ds_init_callbacks ( u32 pass_number); -/* dsmthdat - method data (locals/args) */ - - +/* + * dsmthdat - method data (locals/args) + */ acpi_status acpi_ds_store_object_to_local ( u16 opcode, @@ -250,14 +206,6 @@ u8 acpi_ds_is_method_value ( union acpi_operand_object *obj_desc); -#ifdef ACPI_FUTURE_USAGE -acpi_object_type -acpi_ds_method_data_get_type ( - u16 opcode, - u32 index, - struct acpi_walk_state *walk_state); -#endif - acpi_status acpi_ds_method_data_get_value ( u16 opcode, @@ -265,12 +213,6 @@ acpi_ds_method_data_get_value ( struct acpi_walk_state *walk_state, union acpi_operand_object **dest_desc); -void -acpi_ds_method_data_delete_value ( - u16 opcode, - u32 index, - struct acpi_walk_state *walk_state); - acpi_status acpi_ds_method_data_init_args ( union acpi_operand_object **params, @@ -288,16 +230,10 @@ void acpi_ds_method_data_init ( struct acpi_walk_state *walk_state); -acpi_status -acpi_ds_method_data_set_value ( - u16 opcode, - u32 index, - union acpi_operand_object *object, - struct acpi_walk_state *walk_state); - - -/* dsmethod - Parser/Interpreter interface - control method parsing */ +/* + * dsmethod - Parser/Interpreter interface - control method parsing + */ acpi_status acpi_ds_parse_method ( acpi_handle obj_handle); @@ -324,20 +260,18 @@ acpi_ds_begin_method_execution ( struct acpi_namespace_node *calling_method_node); -/* dsobj - Parser/Interpreter interface - object initialization and conversion */ - -acpi_status -acpi_ds_init_one_object ( - acpi_handle obj_handle, - u32 level, - void *context, - void **return_value); - +/* + * dsinit + */ acpi_status acpi_ds_initialize_objects ( struct acpi_table_desc *table_desc, struct acpi_namespace_node *start_node); + +/* + * dsobject - Parser/Interpreter interface - object initialization and conversion + */ acpi_status acpi_ds_build_internal_buffer_obj ( struct acpi_walk_state *walk_state, @@ -353,12 +287,6 @@ acpi_ds_build_internal_package_obj ( union acpi_operand_object **obj_desc); acpi_status -acpi_ds_build_internal_object ( - struct acpi_walk_state *walk_state, - union acpi_parse_object *op, - union acpi_operand_object **obj_desc_ptr); - -acpi_status acpi_ds_init_object_from_op ( struct acpi_walk_state *walk_state, union acpi_parse_object *op, @@ -372,8 +300,9 @@ acpi_ds_create_node ( union acpi_parse_object *op); -/* dsutils - Parser/Interpreter interface utility routines */ - +/* + * dsutils - Parser/Interpreter interface utility routines + */ void acpi_ds_clear_implicit_return ( struct acpi_walk_state *walk_state); @@ -418,7 +347,6 @@ acpi_ds_clear_operands ( /* * dswscope - Scope Stack manipulation */ - acpi_status acpi_ds_scope_stack_push ( struct acpi_namespace_node *node, @@ -435,7 +363,18 @@ acpi_ds_scope_stack_clear ( struct acpi_walk_state *walk_state); -/* dswstate - parser WALK_STATE management routines */ +/* + * dswstate - parser WALK_STATE management routines + */ +acpi_status +acpi_ds_obj_stack_push ( + void *object, + struct acpi_walk_state *walk_state); + +acpi_status +acpi_ds_obj_stack_pop ( + u32 pop_count, + struct acpi_walk_state *walk_state); struct acpi_walk_state * acpi_ds_create_walk_state ( @@ -454,12 +393,6 @@ acpi_ds_init_aml_walk ( struct acpi_parameter_info *info, u32 pass_number); -#ifdef ACPI_FUTURE_USAGE -acpi_status -acpi_ds_obj_stack_delete_all ( - struct acpi_walk_state *walk_state); -#endif - acpi_status acpi_ds_obj_stack_pop_and_delete ( u32 pop_count, @@ -494,20 +427,8 @@ struct acpi_walk_state * acpi_ds_get_current_walk_state ( struct acpi_thread_state *thread); -#ifdef ACPI_ENABLE_OBJECT_CACHE -void -acpi_ds_delete_walk_state_cache ( - void); -#endif - #ifdef ACPI_FUTURE_USAGE acpi_status -acpi_ds_result_insert ( - void *object, - u32 index, - struct acpi_walk_state *walk_state); - -acpi_status acpi_ds_result_remove ( union acpi_operand_object **object, u32 index, @@ -529,4 +450,10 @@ acpi_ds_result_pop_from_bottom ( union acpi_operand_object **object, struct acpi_walk_state *walk_state); +#ifdef ACPI_ENABLE_OBJECT_CACHE +void +acpi_ds_delete_walk_state_cache ( + void); +#endif + #endif /* _ACDISPAT_H_ */ diff --git a/include/acpi/acevents.h b/include/acpi/acevents.h index 2dec083ba1cd..61a27c8c5079 100644 --- a/include/acpi/acevents.h +++ b/include/acpi/acevents.h @@ -45,6 +45,9 @@ #define __ACEVENTS_H__ +/* + * evevent + */ acpi_status acpi_ev_initialize_events ( void); @@ -53,28 +56,14 @@ acpi_status acpi_ev_install_xrupt_handlers ( void); - -/* - * Evfixed - Fixed event handling - */ - -acpi_status -acpi_ev_fixed_event_initialize ( - void); - u32 acpi_ev_fixed_event_detect ( void); -u32 -acpi_ev_fixed_event_dispatch ( - u32 event); - /* - * Evmisc + * evmisc */ - u8 acpi_ev_is_notify_object ( struct acpi_namespace_node *node); @@ -100,24 +89,10 @@ acpi_ev_queue_notify_request ( struct acpi_namespace_node *node, u32 notify_value); -void ACPI_SYSTEM_XFACE -acpi_ev_notify_dispatch ( - void *context); - /* - * Evgpe - GPE handling and dispatch + * evgpe - GPE handling and dispatch */ - -acpi_status -acpi_ev_walk_gpe_list ( - ACPI_GPE_CALLBACK gpe_walk_callback, - u32 flags); - -u8 -acpi_ev_valid_gpe_event ( - struct acpi_gpe_event_info *gpe_event_info); - acpi_status acpi_ev_update_gpe_enable_masks ( struct acpi_gpe_event_info *gpe_event_info, @@ -137,9 +112,23 @@ acpi_ev_get_gpe_event_info ( acpi_handle gpe_device, u32 gpe_number); + +/* + * evgpeblk + */ +u8 +acpi_ev_valid_gpe_event ( + struct acpi_gpe_event_info *gpe_event_info); + acpi_status -acpi_ev_gpe_initialize ( - void); +acpi_ev_walk_gpe_list ( + ACPI_GPE_CALLBACK gpe_walk_callback, + u32 flags); + +acpi_status +acpi_ev_delete_gpe_handlers ( + struct acpi_gpe_xrupt_info *gpe_xrupt_info, + struct acpi_gpe_block_info *gpe_block); acpi_status acpi_ev_create_gpe_block ( @@ -154,11 +143,6 @@ acpi_status acpi_ev_delete_gpe_block ( struct acpi_gpe_block_info *gpe_block); -acpi_status -acpi_ev_delete_gpe_handlers ( - struct acpi_gpe_xrupt_info *gpe_xrupt_info, - struct acpi_gpe_block_info *gpe_block); - u32 acpi_ev_gpe_dispatch ( struct acpi_gpe_event_info *gpe_event_info, @@ -177,10 +161,14 @@ acpi_status acpi_ev_check_for_wake_only_gpe ( struct acpi_gpe_event_info *gpe_event_info); +acpi_status +acpi_ev_gpe_initialize ( + void); + + /* - * Evregion - Address Space handling + * evregion - Address Space handling */ - acpi_status acpi_ev_install_region_handlers ( void); @@ -198,13 +186,6 @@ acpi_ev_address_space_dispatch ( void *value); acpi_status -acpi_ev_install_handler ( - acpi_handle obj_handle, - u32 level, - void *context, - void **return_value); - -acpi_status acpi_ev_attach_region ( union acpi_operand_object *handler_obj, union acpi_operand_object *region_obj, @@ -233,17 +214,10 @@ acpi_ev_execute_reg_method ( union acpi_operand_object *region_obj, u32 function); -acpi_status -acpi_ev_reg_run ( - acpi_handle obj_handle, - u32 level, - void *context, - void **return_value); /* - * Evregini - Region initialization and setup + * evregini - Region initialization and setup */ - acpi_status acpi_ev_system_memory_region_setup ( acpi_handle handle, @@ -293,9 +267,8 @@ acpi_ev_initialize_region ( /* - * Evsci - SCI (System Control Interrupt) handling/dispatch + * evsci - SCI (System Control Interrupt) handling/dispatch */ - u32 ACPI_SYSTEM_XFACE acpi_ev_gpe_xrupt_handler ( void *context); diff --git a/include/acpi/acexcep.h b/include/acpi/acexcep.h index 53f8b50fac1a..60d737b2d70f 100644 --- a/include/acpi/acexcep.h +++ b/include/acpi/acexcep.h @@ -48,7 +48,6 @@ /* * Exceptions returned by external ACPI interfaces */ - #define AE_CODE_ENVIRONMENTAL 0x0000 #define AE_CODE_PROGRAMMER 0x1000 #define AE_CODE_ACPI_TABLES 0x2000 @@ -99,6 +98,7 @@ #define AE_CODE_ENV_MAX 0x001E + /* * Programmer exceptions */ @@ -168,6 +168,7 @@ #define AE_CODE_AML_MAX 0x0021 + /* * Internal exceptions used for control */ @@ -188,6 +189,7 @@ #ifdef DEFINE_ACPI_GLOBALS + /* * String versions of the exception codes above * These strings must match the corresponding defines exactly @@ -304,5 +306,4 @@ char const *acpi_gbl_exception_names_ctrl[] = #endif /* ACPI GLOBALS */ - #endif /* __ACEXCEP_H__ */ diff --git a/include/acpi/acglobal.h b/include/acpi/acglobal.h index c7f387a972cb..4946696088c3 100644 --- a/include/acpi/acglobal.h +++ b/include/acpi/acglobal.h @@ -146,15 +146,15 @@ ACPI_EXTERN struct acpi_table_header *acpi_gbl_DSDT; ACPI_EXTERN FACS_DESCRIPTOR *acpi_gbl_FACS; ACPI_EXTERN struct acpi_common_facs acpi_gbl_common_fACS; /* - * Since there may be multiple SSDTs and PSDTS, a single pointer is not + * Since there may be multiple SSDTs and PSDTs, a single pointer is not * sufficient; Therefore, there isn't one! */ /* - * Handle both ACPI 1.0 and ACPI 2.0 Integer widths - * If we are running a method that exists in a 32-bit ACPI table. - * Use only 32 bits of the Integer for conversion. + * Handle both ACPI 1.0 and ACPI 2.0 Integer widths: + * If we are executing a method that exists in a 32-bit ACPI table, + * use only the lower 32 bits of the (internal) 64-bit Integer. */ ACPI_EXTERN u8 acpi_gbl_integer_bit_width; ACPI_EXTERN u8 acpi_gbl_integer_byte_width; @@ -246,6 +246,7 @@ ACPI_EXTERN acpi_size acpi_gbl_lowest_stack_pointer; ACPI_EXTERN u32 acpi_gbl_deepest_nesting; #endif + /***************************************************************************** * * Interpreter globals @@ -268,6 +269,7 @@ ACPI_EXTERN u8 acpi_gbl_cm_single_step; ACPI_EXTERN union acpi_parse_object *acpi_gbl_parsed_namespace_root; + /***************************************************************************** * * Hardware globals @@ -298,7 +300,6 @@ ACPI_EXTERN acpi_handle acpi_gbl_gpe_lock; * ****************************************************************************/ - ACPI_EXTERN u8 acpi_gbl_db_output_flags; #ifdef ACPI_DISASSEMBLER @@ -353,5 +354,4 @@ ACPI_EXTERN u32 acpi_gbl_size_of_acpi_objects; #endif /* ACPI_DEBUGGER */ - #endif /* __ACGLOBAL_H__ */ diff --git a/include/acpi/achware.h b/include/acpi/achware.h index 28ad1398c159..9d63641b8e7d 100644 --- a/include/acpi/achware.h +++ b/include/acpi/achware.h @@ -46,22 +46,26 @@ /* PM Timer ticks per second (HZ) */ + #define PM_TIMER_FREQUENCY 3579545 +/* Values for the _SST reserved method */ -/* Prototypes */ +#define ACPI_SST_INDICATOR_OFF 0 +#define ACPI_SST_WORKING 1 +#define ACPI_SST_WAKING 2 +#define ACPI_SST_SLEEPING 3 +#define ACPI_SST_SLEEP_CONTEXT 4 -acpi_status -acpi_hw_initialize ( - void); +/* Prototypes */ -acpi_status -acpi_hw_shutdown ( - void); +/* + * hwacpi - high level functions + */ acpi_status -acpi_hw_initialize_system_info ( +acpi_hw_initialize ( void); acpi_status @@ -72,12 +76,10 @@ u32 acpi_hw_get_mode ( void); -u32 -acpi_hw_get_mode_capabilities ( - void); - -/* Register I/O Prototypes */ +/* + * hwregs - ACPI Register I/O + */ struct acpi_bit_register_info * acpi_hw_get_bit_register_info ( u32 register_id); @@ -111,8 +113,9 @@ acpi_hw_clear_acpi_status ( u32 flags); -/* GPE support */ - +/* + * hwgpe - GPE support + */ acpi_status acpi_hw_write_gpe_enable_reg ( struct acpi_gpe_event_info *gpe_event_info); @@ -131,12 +134,12 @@ acpi_hw_clear_gpe_block ( struct acpi_gpe_xrupt_info *gpe_xrupt_info, struct acpi_gpe_block_info *gpe_block); -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE acpi_status acpi_hw_get_gpe_status ( struct acpi_gpe_event_info *gpe_event_info, acpi_event_status *event_status); -#endif +#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_hw_disable_all_gpes ( @@ -155,15 +158,11 @@ acpi_hw_enable_runtime_gpe_block ( struct acpi_gpe_xrupt_info *gpe_xrupt_info, struct acpi_gpe_block_info *gpe_block); -acpi_status -acpi_hw_enable_wakeup_gpe_block ( - struct acpi_gpe_xrupt_info *gpe_xrupt_info, - struct acpi_gpe_block_info *gpe_block); - - -/* ACPI Timer prototypes */ -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE +/* + * hwtimer - ACPI Timer prototypes + */ acpi_status acpi_get_timer_resolution ( u32 *resolution); @@ -177,6 +176,7 @@ acpi_get_timer_duration ( u32 start_ticks, u32 end_ticks, u32 *time_elapsed); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ + #endif /* __ACHWARE_H__ */ diff --git a/include/acpi/acinterp.h b/include/acpi/acinterp.h index c5301f5ffaf4..5c7172477a0f 100644 --- a/include/acpi/acinterp.h +++ b/include/acpi/acinterp.h @@ -48,37 +48,9 @@ #define ACPI_WALK_OPERANDS (&(walk_state->operands [walk_state->num_operands -1])) -acpi_status -acpi_ex_resolve_operands ( - u16 opcode, - union acpi_operand_object **stack_ptr, - struct acpi_walk_state *walk_state); - -acpi_status -acpi_ex_check_object_type ( - acpi_object_type type_needed, - acpi_object_type this_type, - void *object); - -/* - * exxface - External interpreter interfaces - */ - -acpi_status -acpi_ex_load_table ( - acpi_table_type table_id); - -acpi_status -acpi_ex_execute_method ( - struct acpi_namespace_node *method_node, - union acpi_operand_object **params, - union acpi_operand_object **return_obj_desc); - - /* * exconvrt - object conversion */ - acpi_status acpi_ex_convert_to_integer ( union acpi_operand_object *obj_desc, @@ -110,17 +82,10 @@ acpi_ex_convert_to_target_type ( union acpi_operand_object **result_desc, struct acpi_walk_state *walk_state); -u32 -acpi_ex_convert_to_ascii ( - acpi_integer integer, - u16 base, - u8 *string, - u8 max_length); /* * exfield - ACPI AML (p-code) execution - field manipulation */ - acpi_status acpi_ex_common_buffer_setup ( union acpi_operand_object *obj_desc, @@ -128,42 +93,6 @@ acpi_ex_common_buffer_setup ( u32 *datum_count); acpi_status -acpi_ex_extract_from_field ( - union acpi_operand_object *obj_desc, - void *buffer, - u32 buffer_length); - -acpi_status -acpi_ex_insert_into_field ( - union acpi_operand_object *obj_desc, - void *buffer, - u32 buffer_length); - -acpi_status -acpi_ex_setup_region ( - union acpi_operand_object *obj_desc, - u32 field_datum_byte_offset); - -acpi_status -acpi_ex_access_region ( - union acpi_operand_object *obj_desc, - u32 field_datum_byte_offset, - acpi_integer *value, - u32 read_write); - -u8 -acpi_ex_register_overflow ( - union acpi_operand_object *obj_desc, - acpi_integer value); - -acpi_status -acpi_ex_field_datum_io ( - union acpi_operand_object *obj_desc, - u32 field_datum_byte_offset, - acpi_integer *value, - u32 read_write); - -acpi_status acpi_ex_write_with_update_rule ( union acpi_operand_object *obj_desc, acpi_integer mask, @@ -198,28 +127,33 @@ acpi_ex_write_data_to_field ( union acpi_operand_object *obj_desc, union acpi_operand_object **result_desc); + /* - * exmisc - ACPI AML (p-code) execution - specific opcodes + * exfldio - low level field I/O */ - acpi_status -acpi_ex_opcode_3A_0T_0R ( - struct acpi_walk_state *walk_state); +acpi_ex_extract_from_field ( + union acpi_operand_object *obj_desc, + void *buffer, + u32 buffer_length); acpi_status -acpi_ex_opcode_3A_1T_1R ( - struct acpi_walk_state *walk_state); +acpi_ex_insert_into_field ( + union acpi_operand_object *obj_desc, + void *buffer, + u32 buffer_length); acpi_status -acpi_ex_opcode_6A_0T_1R ( - struct acpi_walk_state *walk_state); +acpi_ex_access_region ( + union acpi_operand_object *obj_desc, + u32 field_datum_byte_offset, + acpi_integer *value, + u32 read_write); -u8 -acpi_ex_do_match ( - u32 match_op, - union acpi_operand_object *package_obj, - union acpi_operand_object *match_obj); +/* + * exmisc - misc support routines + */ acpi_status acpi_ex_get_object_reference ( union acpi_operand_object *obj_desc, @@ -227,13 +161,6 @@ acpi_ex_get_object_reference ( struct acpi_walk_state *walk_state); acpi_status -acpi_ex_resolve_multiple ( - struct acpi_walk_state *walk_state, - union acpi_operand_object *operand, - acpi_object_type *return_type, - union acpi_operand_object **return_desc); - -acpi_status acpi_ex_concat_template ( union acpi_operand_object *obj_desc, union acpi_operand_object *obj_desc2, @@ -308,13 +235,6 @@ acpi_ex_create_method ( /* * exconfig - dynamic table load/unload */ - -acpi_status -acpi_ex_add_table ( - struct acpi_table_header *table, - struct acpi_namespace_node *parent_node, - union acpi_operand_object **ddb_handle); - acpi_status acpi_ex_load_op ( union acpi_operand_object *obj_desc, @@ -334,7 +254,6 @@ acpi_ex_unload_table ( /* * exmutex - mutex support */ - acpi_status acpi_ex_acquire_mutex ( union acpi_operand_object *time_desc, @@ -354,15 +273,10 @@ void acpi_ex_unlink_mutex ( union acpi_operand_object *obj_desc); -void -acpi_ex_link_mutex ( - union acpi_operand_object *obj_desc, - struct acpi_thread_state *thread); /* - * exprep - ACPI AML (p-code) execution - prep utilities + * exprep - ACPI AML execution - prep utilities */ - acpi_status acpi_ex_prep_common_field_object ( union acpi_operand_object *obj_desc, @@ -375,10 +289,10 @@ acpi_status acpi_ex_prep_field_value ( struct acpi_create_field_info *info); + /* * exsystem - Interface to OS services */ - acpi_status acpi_ex_system_do_notify_op ( union acpi_operand_object *value, @@ -421,9 +335,8 @@ acpi_ex_system_wait_semaphore ( /* - * exmonadic - ACPI AML (p-code) execution, monadic operators + * exoparg1 - ACPI AML execution, 1 operand */ - acpi_status acpi_ex_opcode_0A_0T_1R ( struct acpi_walk_state *walk_state); @@ -445,9 +358,8 @@ acpi_ex_opcode_1A_1T_0R ( struct acpi_walk_state *walk_state); /* - * exdyadic - ACPI AML (p-code) execution, dyadic operators + * exoparg2 - ACPI AML execution, 2 operands */ - acpi_status acpi_ex_opcode_2A_0T_0R ( struct acpi_walk_state *walk_state); @@ -466,21 +378,56 @@ acpi_ex_opcode_2A_2T_1R ( /* - * exresolv - Object resolution and get value functions + * exoparg3 - ACPI AML execution, 3 operands + */ +acpi_status +acpi_ex_opcode_3A_0T_0R ( + struct acpi_walk_state *walk_state); + +acpi_status +acpi_ex_opcode_3A_1T_1R ( + struct acpi_walk_state *walk_state); + + +/* + * exoparg6 - ACPI AML execution, 6 operands */ +acpi_status +acpi_ex_opcode_6A_0T_1R ( + struct acpi_walk_state *walk_state); + +/* + * exresolv - Object resolution and get value functions + */ acpi_status acpi_ex_resolve_to_value ( union acpi_operand_object **stack_ptr, struct acpi_walk_state *walk_state); acpi_status +acpi_ex_resolve_multiple ( + struct acpi_walk_state *walk_state, + union acpi_operand_object *operand, + acpi_object_type *return_type, + union acpi_operand_object **return_desc); + + +/* + * exresnte - resolve namespace node + */ +acpi_status acpi_ex_resolve_node_to_value ( struct acpi_namespace_node **stack_ptr, struct acpi_walk_state *walk_state); + +/* + * exresop - resolve operand to value + */ acpi_status -acpi_ex_resolve_object_to_value ( +acpi_ex_resolve_operands ( + u16 opcode, union acpi_operand_object **stack_ptr, struct acpi_walk_state *walk_state); @@ -488,7 +435,6 @@ acpi_ex_resolve_object_to_value ( /* * exdump - Interpreter debug output routines */ - void acpi_ex_dump_operand ( union acpi_operand_object *obj_desc, @@ -504,7 +450,7 @@ acpi_ex_dump_operands ( char *module_name, u32 line_number); -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE void acpi_ex_dump_object_descriptor ( union acpi_operand_object *object, @@ -514,46 +460,12 @@ void acpi_ex_dump_node ( struct acpi_namespace_node *node, u32 flags); +#endif /* ACPI_FUTURE_USAGE */ -void -acpi_ex_out_string ( - char *title, - char *value); - -void -acpi_ex_out_pointer ( - char *title, - void *value); - -void -acpi_ex_out_integer ( - char *title, - u32 value); - -void -acpi_ex_out_address ( - char *title, - acpi_physical_address value); -#endif /* ACPI_FUTURE_USAGE */ /* - * exnames - interpreter/scanner name load/execute + * exnames - AML namestring support */ - -char * -acpi_ex_allocate_name_string ( - u32 prefix_count, - u32 num_name_segs); - -u32 -acpi_ex_good_char ( - u32 character); - -acpi_status -acpi_ex_name_segment ( - u8 **in_aml_address, - char *name_string); - acpi_status acpi_ex_get_name_string ( acpi_object_type data_type, @@ -561,16 +473,10 @@ acpi_ex_get_name_string ( char **out_name_string, u32 *out_name_length); -acpi_status -acpi_ex_do_name ( - acpi_object_type data_type, - acpi_interpreter_mode load_exec_mode); - /* * exstore - Object store support */ - acpi_status acpi_ex_store ( union acpi_operand_object *val_desc, @@ -578,12 +484,6 @@ acpi_ex_store ( struct acpi_walk_state *walk_state); acpi_status -acpi_ex_store_object_to_index ( - union acpi_operand_object *val_desc, - union acpi_operand_object *dest_desc, - struct acpi_walk_state *walk_state); - -acpi_status acpi_ex_store_object_to_node ( union acpi_operand_object *source_desc, struct acpi_namespace_node *node, @@ -593,10 +493,10 @@ acpi_ex_store_object_to_node ( #define ACPI_IMPLICIT_CONVERSION TRUE #define ACPI_NO_IMPLICIT_CONVERSION FALSE + /* - * exstoren + * exstoren - resolve/store object */ - acpi_status acpi_ex_resolve_object ( union acpi_operand_object **source_desc_ptr, @@ -612,9 +512,8 @@ acpi_ex_store_object_to_object ( /* - * excopy - object copy + * exstorob - store object - buffer/string */ - acpi_status acpi_ex_store_buffer_to_buffer ( union acpi_operand_object *source_desc, @@ -625,6 +524,10 @@ acpi_ex_store_string_to_string ( union acpi_operand_object *source_desc, union acpi_operand_object *target_desc); + +/* + * excopy - object copy + */ acpi_status acpi_ex_copy_integer_to_index_field ( union acpi_operand_object *source_desc, @@ -645,10 +548,10 @@ acpi_ex_copy_integer_to_buffer_field ( union acpi_operand_object *source_desc, union acpi_operand_object *target_desc); + /* * exutils - interpreter/scanner utilities */ - acpi_status acpi_ex_enter_interpreter ( void); @@ -669,11 +572,6 @@ void acpi_ex_release_global_lock ( u8 locked); -u32 -acpi_ex_digits_needed ( - acpi_integer value, - u32 base); - void acpi_ex_eisa_id_to_string ( u32 numeric_id, @@ -688,7 +586,6 @@ acpi_ex_unsigned_integer_to_string ( /* * exregion - default op_region handlers */ - acpi_status acpi_ex_system_memory_space_handler ( u32 function, diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h index 01d3b4bc0c85..030e641115cb 100644 --- a/include/acpi/aclocal.h +++ b/include/acpi/aclocal.h @@ -72,7 +72,6 @@ typedef u32 acpi_mutex_handle; * * NOTE: any changes here must be reflected in the acpi_gbl_mutex_names table also! */ - #define ACPI_MTX_EXECUTE 0 #define ACPI_MTX_INTERPRETER 1 #define ACPI_MTX_PARSER 2 @@ -151,13 +150,13 @@ typedef u16 acpi_owner_id; #define ACPI_FIELD_DWORD_GRANULARITY 4 #define ACPI_FIELD_QWORD_GRANULARITY 8 + /***************************************************************************** * * Namespace typedefs and structs * ****************************************************************************/ - /* Operational modes of the AML interpreter/scanner */ typedef enum @@ -176,7 +175,6 @@ typedef enum * data_type is used to differentiate between internal descriptors, and MUST * be the first byte in this structure. */ - union acpi_name_union { u32 integer; @@ -415,7 +413,6 @@ struct acpi_field_info * ****************************************************************************/ - #define ACPI_CONTROL_NORMAL 0xC0 #define ACPI_CONTROL_CONDITIONAL_EXECUTING 0xC1 #define ACPI_CONTROL_PREDICATE_EXECUTING 0xC2 @@ -424,6 +421,7 @@ struct acpi_field_info /* Forward declarations */ + struct acpi_walk_state ; struct acpi_obj_mutex; union acpi_parse_object ; @@ -601,7 +599,6 @@ struct acpi_opcode_info u8 type; /* Opcode type */ }; - union acpi_parse_value { acpi_integer integer; /* Integer constant (Up to 64 bits) */ @@ -613,7 +610,6 @@ union acpi_parse_value union acpi_parse_object *arg; /* arguments and contained ops */ }; - #define ACPI_PARSE_COMMON \ u8 data_type; /* To differentiate various internal objs */\ u8 flags; /* Type of Op */\ @@ -691,7 +687,6 @@ struct acpi_parse_obj_asl char parse_op_name[12]; }; - union acpi_parse_object { struct acpi_parse_obj_common common; @@ -834,7 +829,6 @@ struct acpi_bit_register_info * ****************************************************************************/ - /* resource_type values */ #define ACPI_RESOURCE_TYPE_MEMORY_RANGE 0 diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h index fcaced16b16f..09be937d2c39 100644 --- a/include/acpi/acmacros.h +++ b/include/acpi/acmacros.h @@ -539,11 +539,6 @@ #define ACPI_DUMP_ENTRY(a,b) acpi_ns_dump_entry (a,b) - -#ifdef ACPI_FUTURE_USAGE -#define ACPI_DUMP_TABLES(a,b) acpi_ns_dump_tables(a,b) -#endif - #define ACPI_DUMP_PATHNAME(a,b,c,d) acpi_ns_dump_pathname(a,b,c,d) #define ACPI_DUMP_RESOURCE_LIST(a) acpi_rs_dump_resource_list(a) #define ACPI_DUMP_BUFFER(a,b) acpi_ut_dump_buffer((u8 *)a,b,DB_BYTE_DISPLAY,_COMPONENT) @@ -596,11 +591,6 @@ #define ACPI_DUMP_STACK_ENTRY(a) #define ACPI_DUMP_OPERANDS(a,b,c,d,e) #define ACPI_DUMP_ENTRY(a,b) - -#ifdef ACPI_FUTURE_USAGE -#define ACPI_DUMP_TABLES(a,b) -#endif - #define ACPI_DUMP_PATHNAME(a,b,c,d) #define ACPI_DUMP_RESOURCE_LIST(a) #define ACPI_DUMP_BUFFER(a,b) diff --git a/include/acpi/acnames.h b/include/acpi/acnames.h new file mode 100644 index 000000000000..deb7cb06f5f0 --- /dev/null +++ b/include/acpi/acnames.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Name: acnames.h - Global names and strings + * + *****************************************************************************/ + +/* + * Copyright (C) 2000 - 2005, R. Byron Moore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for further + * binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES. + */ + +#ifndef __ACNAMES_H__ +#define __ACNAMES_H__ + +/* Method names - these methods can appear anywhere in the namespace */ + +#define METHOD_NAME__HID "_HID" +#define METHOD_NAME__CID "_CID" +#define METHOD_NAME__UID "_UID" +#define METHOD_NAME__ADR "_ADR" +#define METHOD_NAME__INI "_INI" +#define METHOD_NAME__STA "_STA" +#define METHOD_NAME__REG "_REG" +#define METHOD_NAME__SEG "_SEG" +#define METHOD_NAME__BBN "_BBN" +#define METHOD_NAME__PRT "_PRT" +#define METHOD_NAME__CRS "_CRS" +#define METHOD_NAME__PRS "_PRS" +#define METHOD_NAME__PRW "_PRW" +#define METHOD_NAME__SRS "_SRS" + +/* Method names - these methods must appear at the namespace root */ + +#define METHOD_NAME__BFS "\\_BFS" +#define METHOD_NAME__GTS "\\_GTS" +#define METHOD_NAME__PTS "\\_PTS" +#define METHOD_NAME__SST "\\_SI._SST" +#define METHOD_NAME__WAK "\\_WAK" + +/* Definitions of the predefined namespace names */ + +#define ACPI_UNKNOWN_NAME (u32) 0x3F3F3F3F /* Unknown name is "????" */ +#define ACPI_ROOT_NAME (u32) 0x5F5F5F5C /* Root name is "\___" */ +#define ACPI_SYS_BUS_NAME (u32) 0x5F53425F /* Sys bus name is "_SB_" */ + +#define ACPI_NS_ROOT_PATH "\\" +#define ACPI_NS_SYSTEM_BUS "_SB_" + + +#endif /* __ACNAMES_H__ */ + + diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h index 8b3cdc3566b1..d1b3ce80056f 100644 --- a/include/acpi/acnamesp.h +++ b/include/acpi/acnamesp.h @@ -57,17 +57,6 @@ #define ACPI_NS_NEWSCOPE 1 /* a definition of this type opens a name scope */ #define ACPI_NS_LOCAL 2 /* suppress search of enclosing scopes */ - -/* Definitions of the predefined namespace names */ - -#define ACPI_UNKNOWN_NAME (u32) 0x3F3F3F3F /* Unknown name is "????" */ -#define ACPI_ROOT_NAME (u32) 0x5F5F5F5C /* Root name is "\___" */ -#define ACPI_SYS_BUS_NAME (u32) 0x5F53425F /* Sys bus name is "_SB_" */ - -#define ACPI_NS_ROOT_PATH "\\" -#define ACPI_NS_SYSTEM_BUS "_SB_" - - /* Flags for acpi_ns_lookup, acpi_ns_search_and_enter */ #define ACPI_NS_NO_UPSEARCH 0 @@ -80,10 +69,9 @@ #define ACPI_NS_WALK_NO_UNLOCK FALSE -acpi_status -acpi_ns_load_namespace ( - void); - +/* + * nsinit - Namespace initialization + */ acpi_status acpi_ns_initialize_objects ( void); @@ -93,23 +81,22 @@ acpi_ns_initialize_devices ( void); -/* Namespace init - nsxfinit */ - +/* + * nsload - Namespace loading + */ acpi_status -acpi_ns_init_one_device ( - acpi_handle obj_handle, - u32 nesting_level, - void *context, - void **return_value); +acpi_ns_load_namespace ( + void); acpi_status -acpi_ns_init_one_object ( - acpi_handle obj_handle, - u32 level, - void *context, - void **return_value); +acpi_ns_load_table ( + struct acpi_table_desc *table_desc, + struct acpi_namespace_node *node); +/* + * nswalk - walk the namespace + */ acpi_status acpi_ns_walk_namespace ( acpi_object_type type, @@ -126,37 +113,24 @@ acpi_ns_get_next_node ( struct acpi_namespace_node *parent, struct acpi_namespace_node *child); -void -acpi_ns_delete_namespace_by_owner ( - u16 table_id); - - -/* Namespace loading - nsload */ - -acpi_status -acpi_ns_one_complete_parse ( - u32 pass_number, - struct acpi_table_desc *table_desc); +/* + * nsparse - table parsing + */ acpi_status acpi_ns_parse_table ( struct acpi_table_desc *table_desc, struct acpi_namespace_node *scope); acpi_status -acpi_ns_load_table ( - struct acpi_table_desc *table_desc, - struct acpi_namespace_node *node); - -acpi_status -acpi_ns_load_table_by_type ( - acpi_table_type table_type); +acpi_ns_one_complete_parse ( + u32 pass_number, + struct acpi_table_desc *table_desc); /* - * Top-level namespace access - nsaccess + * nsaccess - Top-level namespace access */ - acpi_status acpi_ns_root_initialize ( void); @@ -173,9 +147,8 @@ acpi_ns_lookup ( /* - * Named object allocation/deallocation - nsalloc + * nsalloc - Named object allocation/deallocation */ - struct acpi_namespace_node * acpi_ns_create_node ( u32 name); @@ -189,6 +162,10 @@ acpi_ns_delete_namespace_subtree ( struct acpi_namespace_node *parent_handle); void +acpi_ns_delete_namespace_by_owner ( + u16 table_id); + +void acpi_ns_detach_object ( struct acpi_namespace_node *node); @@ -201,36 +178,16 @@ acpi_ns_compare_names ( char *name1, char *name2); -void -acpi_ns_remove_reference ( - struct acpi_namespace_node *node); - /* - * Namespace modification - nsmodify + * nsdump - Namespace dump/print utilities */ - -#ifdef ACPI_FUTURE_USAGE -acpi_status -acpi_ns_unload_namespace ( - acpi_handle handle); - -acpi_status -acpi_ns_delete_subtree ( - acpi_handle start_handle); -#endif - - -/* - * Namespace dump/print utilities - nsdump - */ - -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE void acpi_ns_dump_tables ( acpi_handle search_base, u32 max_depth); -#endif +#endif /* ACPI_FUTURE_USAGE */ void acpi_ns_dump_entry ( @@ -249,19 +206,6 @@ acpi_ns_print_pathname ( u32 num_segments, char *pathname); -#ifdef ACPI_FUTURE_USAGE -acpi_status -acpi_ns_dump_one_device ( - acpi_handle obj_handle, - u32 level, - void *context, - void **return_value); - -void -acpi_ns_dump_root_devices ( - void); -#endif /* ACPI_FUTURE_USAGE */ - acpi_status acpi_ns_dump_one_object ( acpi_handle obj_handle, @@ -269,7 +213,7 @@ acpi_ns_dump_one_object ( void *context, void **return_value); -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE void acpi_ns_dump_objects ( acpi_object_type type, @@ -277,13 +221,12 @@ acpi_ns_dump_objects ( u32 max_depth, u32 ownder_id, acpi_handle start_handle); -#endif +#endif /* ACPI_FUTURE_USAGE */ /* - * Namespace evaluation functions - nseval + * nseval - Namespace evaluation functions */ - acpi_status acpi_ns_evaluate_by_handle ( struct acpi_parameter_info *info); @@ -298,40 +241,14 @@ acpi_ns_evaluate_relative ( char *pathname, struct acpi_parameter_info *info); -acpi_status -acpi_ns_execute_control_method ( - struct acpi_parameter_info *info); - -acpi_status -acpi_ns_get_object_value ( - struct acpi_parameter_info *info); - - -/* - * Parent/Child/Peer utility functions - */ - -#ifdef ACPI_FUTURE_USAGE -acpi_name -acpi_ns_find_parent_name ( - struct acpi_namespace_node *node_to_search); -#endif - /* - * Name and Scope manipulation - nsnames + * nsnames - Name and Scope manipulation */ - u32 acpi_ns_opens_scope ( acpi_object_type type); -void -acpi_ns_build_external_path ( - struct acpi_namespace_node *node, - acpi_size size, - char *name_buffer); - char * acpi_ns_get_external_pathname ( struct acpi_namespace_node *node); @@ -363,9 +280,8 @@ acpi_ns_get_pathname_length ( /* - * Object management for namespace nodes - nsobject + * nsobject - Object management for namespace nodes */ - acpi_status acpi_ns_attach_object ( struct acpi_namespace_node *node, @@ -399,9 +315,8 @@ acpi_ns_get_attached_data ( /* - * Namespace searching and entry - nssearch + * nssearch - Namespace searching and entry */ - acpi_status acpi_ns_search_and_enter ( u32 entry_name, @@ -428,17 +343,12 @@ acpi_ns_install_node ( /* - * Utility functions - nsutils + * nsutils - Utility functions */ - u8 acpi_ns_valid_root_prefix ( char prefix); -u8 -acpi_ns_valid_path_separator ( - char sep); - acpi_object_type acpi_ns_get_type ( struct acpi_namespace_node *node); @@ -511,5 +421,4 @@ struct acpi_namespace_node * acpi_ns_get_next_valid_node ( struct acpi_namespace_node *node); - #endif /* __ACNAMESP_H__ */ diff --git a/include/acpi/acobject.h b/include/acpi/acobject.h index 036023a940b2..e079b94e4fce 100644 --- a/include/acpi/acobject.h +++ b/include/acpi/acobject.h @@ -133,6 +133,7 @@ struct acpi_object_integer acpi_integer value; }; + /* * Note: The String and Buffer object must be identical through the Pointer * element. There is code that depends on this. @@ -468,7 +469,6 @@ union acpi_operand_object * *****************************************************************************/ - /* Object descriptor types */ #define ACPI_DESC_TYPE_CACHED 0x01 /* Used only when object is cached */ diff --git a/include/acpi/acopcode.h b/include/acpi/acopcode.h new file mode 100644 index 000000000000..118ecba4cf05 --- /dev/null +++ b/include/acpi/acopcode.h @@ -0,0 +1,325 @@ +/****************************************************************************** + * + * Name: acopcode.h - AML opcode information for the AML parser and interpreter + * + *****************************************************************************/ + +/* + * Copyright (C) 2000 - 2005, R. Byron Moore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for further + * binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES. + */ + +#ifndef __ACOPCODE_H__ +#define __ACOPCODE_H__ + +#define MAX_EXTENDED_OPCODE 0x88 +#define NUM_EXTENDED_OPCODE (MAX_EXTENDED_OPCODE + 1) +#define MAX_INTERNAL_OPCODE +#define NUM_INTERNAL_OPCODE (MAX_INTERNAL_OPCODE + 1) + +/* Used for non-assigned opcodes */ + +#define _UNK 0x6B + +/* + * Reserved ASCII characters. Do not use any of these for + * internal opcodes, since they are used to differentiate + * name strings from AML opcodes + */ +#define _ASC 0x6C +#define _NAM 0x6C +#define _PFX 0x6D + + +/* + * All AML opcodes and the parse-time arguments for each. Used by the AML + * parser Each list is compressed into a 32-bit number and stored in the + * master opcode table (in psopcode.c). + */ +#define ARGP_ACCESSFIELD_OP ARGP_LIST1 (ARGP_NAMESTRING) +#define ARGP_ACQUIRE_OP ARGP_LIST2 (ARGP_SUPERNAME, ARGP_WORDDATA) +#define ARGP_ADD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_ALIAS_OP ARGP_LIST2 (ARGP_NAMESTRING, ARGP_NAME) +#define ARGP_ARG0 ARG_NONE +#define ARGP_ARG1 ARG_NONE +#define ARGP_ARG2 ARG_NONE +#define ARGP_ARG3 ARG_NONE +#define ARGP_ARG4 ARG_NONE +#define ARGP_ARG5 ARG_NONE +#define ARGP_ARG6 ARG_NONE +#define ARGP_BANK_FIELD_OP ARGP_LIST6 (ARGP_PKGLENGTH, ARGP_NAMESTRING, ARGP_NAMESTRING,ARGP_TERMARG, ARGP_BYTEDATA, ARGP_FIELDLIST) +#define ARGP_BIT_AND_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_BIT_NAND_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_BIT_NOR_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_BIT_NOT_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_BIT_OR_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_BIT_XOR_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_BREAK_OP ARG_NONE +#define ARGP_BREAK_POINT_OP ARG_NONE +#define ARGP_BUFFER_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_TERMARG, ARGP_BYTELIST) +#define ARGP_BYTE_OP ARGP_LIST1 (ARGP_BYTEDATA) +#define ARGP_BYTELIST_OP ARGP_LIST1 (ARGP_NAMESTRING) +#define ARGP_CONCAT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_CONCAT_RES_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_COND_REF_OF_OP ARGP_LIST2 (ARGP_SUPERNAME, ARGP_SUPERNAME) +#define ARGP_CONTINUE_OP ARG_NONE +#define ARGP_COPY_OP ARGP_LIST2 (ARGP_SUPERNAME, ARGP_SIMPLENAME) +#define ARGP_CREATE_BIT_FIELD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_NAME) +#define ARGP_CREATE_BYTE_FIELD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_NAME) +#define ARGP_CREATE_DWORD_FIELD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_NAME) +#define ARGP_CREATE_FIELD_OP ARGP_LIST4 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG, ARGP_NAME) +#define ARGP_CREATE_QWORD_FIELD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_NAME) +#define ARGP_CREATE_WORD_FIELD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_NAME) +#define ARGP_DATA_REGION_OP ARGP_LIST4 (ARGP_NAME, ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_DEBUG_OP ARG_NONE +#define ARGP_DECREMENT_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_DEREF_OF_OP ARGP_LIST1 (ARGP_TERMARG) +#define ARGP_DEVICE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_OBJLIST) +#define ARGP_DIVIDE_OP ARGP_LIST4 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET, ARGP_TARGET) +#define ARGP_DWORD_OP ARGP_LIST1 (ARGP_DWORDDATA) +#define ARGP_ELSE_OP ARGP_LIST2 (ARGP_PKGLENGTH, ARGP_TERMLIST) +#define ARGP_EVENT_OP ARGP_LIST1 (ARGP_NAME) +#define ARGP_FATAL_OP ARGP_LIST3 (ARGP_BYTEDATA, ARGP_DWORDDATA, ARGP_TERMARG) +#define ARGP_FIELD_OP ARGP_LIST4 (ARGP_PKGLENGTH, ARGP_NAMESTRING, ARGP_BYTEDATA, ARGP_FIELDLIST) +#define ARGP_FIND_SET_LEFT_BIT_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_FIND_SET_RIGHT_BIT_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_FROM_BCD_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_IF_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_TERMARG, ARGP_TERMLIST) +#define ARGP_INCREMENT_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_INDEX_FIELD_OP ARGP_LIST5 (ARGP_PKGLENGTH, ARGP_NAMESTRING, ARGP_NAMESTRING,ARGP_BYTEDATA, ARGP_FIELDLIST) +#define ARGP_INDEX_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_LAND_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LEQUAL_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LGREATER_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LGREATEREQUAL_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LLESS_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LLESSEQUAL_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LNOT_OP ARGP_LIST1 (ARGP_TERMARG) +#define ARGP_LNOTEQUAL_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LOAD_OP ARGP_LIST2 (ARGP_NAMESTRING, ARGP_SUPERNAME) +#define ARGP_LOAD_TABLE_OP ARGP_LIST6 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_LOCAL0 ARG_NONE +#define ARGP_LOCAL1 ARG_NONE +#define ARGP_LOCAL2 ARG_NONE +#define ARGP_LOCAL3 ARG_NONE +#define ARGP_LOCAL4 ARG_NONE +#define ARGP_LOCAL5 ARG_NONE +#define ARGP_LOCAL6 ARG_NONE +#define ARGP_LOCAL7 ARG_NONE +#define ARGP_LOR_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_MATCH_OP ARGP_LIST6 (ARGP_TERMARG, ARGP_BYTEDATA, ARGP_TERMARG, ARGP_BYTEDATA, ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_METHOD_OP ARGP_LIST4 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_BYTEDATA, ARGP_TERMLIST) +#define ARGP_METHODCALL_OP ARGP_LIST1 (ARGP_NAMESTRING) +#define ARGP_MID_OP ARGP_LIST4 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_MOD_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_MULTIPLY_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_MUTEX_OP ARGP_LIST2 (ARGP_NAME, ARGP_BYTEDATA) +#define ARGP_NAME_OP ARGP_LIST2 (ARGP_NAME, ARGP_DATAOBJ) +#define ARGP_NAMEDFIELD_OP ARGP_LIST1 (ARGP_NAMESTRING) +#define ARGP_NAMEPATH_OP ARGP_LIST1 (ARGP_NAMESTRING) +#define ARGP_NOOP_OP ARG_NONE +#define ARGP_NOTIFY_OP ARGP_LIST2 (ARGP_SUPERNAME, ARGP_TERMARG) +#define ARGP_ONE_OP ARG_NONE +#define ARGP_ONES_OP ARG_NONE +#define ARGP_PACKAGE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_BYTEDATA, ARGP_DATAOBJLIST) +#define ARGP_POWER_RES_OP ARGP_LIST5 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_BYTEDATA, ARGP_WORDDATA, ARGP_OBJLIST) +#define ARGP_PROCESSOR_OP ARGP_LIST6 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_BYTEDATA, ARGP_DWORDDATA, ARGP_BYTEDATA, ARGP_OBJLIST) +#define ARGP_QWORD_OP ARGP_LIST1 (ARGP_QWORDDATA) +#define ARGP_REF_OF_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_REGION_OP ARGP_LIST4 (ARGP_NAME, ARGP_BYTEDATA, ARGP_TERMARG, ARGP_TERMARG) +#define ARGP_RELEASE_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_RESERVEDFIELD_OP ARGP_LIST1 (ARGP_NAMESTRING) +#define ARGP_RESET_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_RETURN_OP ARGP_LIST1 (ARGP_TERMARG) +#define ARGP_REVISION_OP ARG_NONE +#define ARGP_SCOPE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_TERMLIST) +#define ARGP_SHIFT_LEFT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_SHIFT_RIGHT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_SIGNAL_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_SIZE_OF_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_SLEEP_OP ARGP_LIST1 (ARGP_TERMARG) +#define ARGP_STALL_OP ARGP_LIST1 (ARGP_TERMARG) +#define ARGP_STATICSTRING_OP ARGP_LIST1 (ARGP_NAMESTRING) +#define ARGP_STORE_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_SUPERNAME) +#define ARGP_STRING_OP ARGP_LIST1 (ARGP_CHARLIST) +#define ARGP_SUBTRACT_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_THERMAL_ZONE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_NAME, ARGP_OBJLIST) +#define ARGP_TIMER_OP ARG_NONE +#define ARGP_TO_BCD_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_TO_BUFFER_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_TO_DEC_STR_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_TO_HEX_STR_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_TO_INTEGER_OP ARGP_LIST2 (ARGP_TERMARG, ARGP_TARGET) +#define ARGP_TO_STRING_OP ARGP_LIST3 (ARGP_TERMARG, ARGP_TERMARG, ARGP_TARGET) +#define ARGP_TYPE_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_UNLOAD_OP ARGP_LIST1 (ARGP_SUPERNAME) +#define ARGP_VAR_PACKAGE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_TERMARG, ARGP_DATAOBJLIST) +#define ARGP_WAIT_OP ARGP_LIST2 (ARGP_SUPERNAME, ARGP_TERMARG) +#define ARGP_WHILE_OP ARGP_LIST3 (ARGP_PKGLENGTH, ARGP_TERMARG, ARGP_TERMLIST) +#define ARGP_WORD_OP ARGP_LIST1 (ARGP_WORDDATA) +#define ARGP_ZERO_OP ARG_NONE + + +/* + * All AML opcodes and the runtime arguments for each. Used by the AML + * interpreter Each list is compressed into a 32-bit number and stored + * in the master opcode table (in psopcode.c). + * + * (Used by prep_operands procedure and the ASL Compiler) + */ +#define ARGI_ACCESSFIELD_OP ARGI_INVALID_OPCODE +#define ARGI_ACQUIRE_OP ARGI_LIST2 (ARGI_MUTEX, ARGI_INTEGER) +#define ARGI_ADD_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_ALIAS_OP ARGI_INVALID_OPCODE +#define ARGI_ARG0 ARG_NONE +#define ARGI_ARG1 ARG_NONE +#define ARGI_ARG2 ARG_NONE +#define ARGI_ARG3 ARG_NONE +#define ARGI_ARG4 ARG_NONE +#define ARGI_ARG5 ARG_NONE +#define ARGI_ARG6 ARG_NONE +#define ARGI_BANK_FIELD_OP ARGI_INVALID_OPCODE +#define ARGI_BIT_AND_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_BIT_NAND_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_BIT_NOR_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_BIT_NOT_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_BIT_OR_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_BIT_XOR_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_BREAK_OP ARG_NONE +#define ARGI_BREAK_POINT_OP ARG_NONE +#define ARGI_BUFFER_OP ARGI_LIST1 (ARGI_INTEGER) +#define ARGI_BYTE_OP ARGI_INVALID_OPCODE +#define ARGI_BYTELIST_OP ARGI_INVALID_OPCODE +#define ARGI_CONCAT_OP ARGI_LIST3 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA, ARGI_TARGETREF) +#define ARGI_CONCAT_RES_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_BUFFER, ARGI_TARGETREF) +#define ARGI_COND_REF_OF_OP ARGI_LIST2 (ARGI_OBJECT_REF, ARGI_TARGETREF) +#define ARGI_CONTINUE_OP ARGI_INVALID_OPCODE +#define ARGI_COPY_OP ARGI_LIST2 (ARGI_ANYTYPE, ARGI_SIMPLE_TARGET) +#define ARGI_CREATE_BIT_FIELD_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_REFERENCE) +#define ARGI_CREATE_BYTE_FIELD_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_REFERENCE) +#define ARGI_CREATE_DWORD_FIELD_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_REFERENCE) +#define ARGI_CREATE_FIELD_OP ARGI_LIST4 (ARGI_BUFFER, ARGI_INTEGER, ARGI_INTEGER, ARGI_REFERENCE) +#define ARGI_CREATE_QWORD_FIELD_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_REFERENCE) +#define ARGI_CREATE_WORD_FIELD_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_REFERENCE) +#define ARGI_DATA_REGION_OP ARGI_LIST3 (ARGI_STRING, ARGI_STRING, ARGI_STRING) +#define ARGI_DEBUG_OP ARG_NONE +#define ARGI_DECREMENT_OP ARGI_LIST1 (ARGI_INTEGER_REF) +#define ARGI_DEREF_OF_OP ARGI_LIST1 (ARGI_REF_OR_STRING) +#define ARGI_DEVICE_OP ARGI_INVALID_OPCODE +#define ARGI_DIVIDE_OP ARGI_LIST4 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF, ARGI_TARGETREF) +#define ARGI_DWORD_OP ARGI_INVALID_OPCODE +#define ARGI_ELSE_OP ARGI_INVALID_OPCODE +#define ARGI_EVENT_OP ARGI_INVALID_OPCODE +#define ARGI_FATAL_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_INTEGER) +#define ARGI_FIELD_OP ARGI_INVALID_OPCODE +#define ARGI_FIND_SET_LEFT_BIT_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_FIND_SET_RIGHT_BIT_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_FROM_BCD_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_IF_OP ARGI_INVALID_OPCODE +#define ARGI_INCREMENT_OP ARGI_LIST1 (ARGI_INTEGER_REF) +#define ARGI_INDEX_FIELD_OP ARGI_INVALID_OPCODE +#define ARGI_INDEX_OP ARGI_LIST3 (ARGI_COMPLEXOBJ, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_LAND_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_INTEGER) +#define ARGI_LEQUAL_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA) +#define ARGI_LGREATER_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA) +#define ARGI_LGREATEREQUAL_OP ARGI_INVALID_OPCODE +#define ARGI_LLESS_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_COMPUTEDATA) +#define ARGI_LLESSEQUAL_OP ARGI_INVALID_OPCODE +#define ARGI_LNOT_OP ARGI_LIST1 (ARGI_INTEGER) +#define ARGI_LNOTEQUAL_OP ARGI_INVALID_OPCODE +#define ARGI_LOAD_OP ARGI_LIST2 (ARGI_REGION_OR_FIELD,ARGI_TARGETREF) +#define ARGI_LOAD_TABLE_OP ARGI_LIST6 (ARGI_STRING, ARGI_STRING, ARGI_STRING, ARGI_STRING, ARGI_STRING, ARGI_ANYTYPE) +#define ARGI_LOCAL0 ARG_NONE +#define ARGI_LOCAL1 ARG_NONE +#define ARGI_LOCAL2 ARG_NONE +#define ARGI_LOCAL3 ARG_NONE +#define ARGI_LOCAL4 ARG_NONE +#define ARGI_LOCAL5 ARG_NONE +#define ARGI_LOCAL6 ARG_NONE +#define ARGI_LOCAL7 ARG_NONE +#define ARGI_LOR_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_INTEGER) +#define ARGI_MATCH_OP ARGI_LIST6 (ARGI_PACKAGE, ARGI_INTEGER, ARGI_COMPUTEDATA, ARGI_INTEGER,ARGI_COMPUTEDATA,ARGI_INTEGER) +#define ARGI_METHOD_OP ARGI_INVALID_OPCODE +#define ARGI_METHODCALL_OP ARGI_INVALID_OPCODE +#define ARGI_MID_OP ARGI_LIST4 (ARGI_BUFFER_OR_STRING,ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_MOD_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_MULTIPLY_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_MUTEX_OP ARGI_INVALID_OPCODE +#define ARGI_NAME_OP ARGI_INVALID_OPCODE +#define ARGI_NAMEDFIELD_OP ARGI_INVALID_OPCODE +#define ARGI_NAMEPATH_OP ARGI_INVALID_OPCODE +#define ARGI_NOOP_OP ARG_NONE +#define ARGI_NOTIFY_OP ARGI_LIST2 (ARGI_DEVICE_REF, ARGI_INTEGER) +#define ARGI_ONE_OP ARG_NONE +#define ARGI_ONES_OP ARG_NONE +#define ARGI_PACKAGE_OP ARGI_LIST1 (ARGI_INTEGER) +#define ARGI_POWER_RES_OP ARGI_INVALID_OPCODE +#define ARGI_PROCESSOR_OP ARGI_INVALID_OPCODE +#define ARGI_QWORD_OP ARGI_INVALID_OPCODE +#define ARGI_REF_OF_OP ARGI_LIST1 (ARGI_OBJECT_REF) +#define ARGI_REGION_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_INTEGER) +#define ARGI_RELEASE_OP ARGI_LIST1 (ARGI_MUTEX) +#define ARGI_RESERVEDFIELD_OP ARGI_INVALID_OPCODE +#define ARGI_RESET_OP ARGI_LIST1 (ARGI_EVENT) +#define ARGI_RETURN_OP ARGI_INVALID_OPCODE +#define ARGI_REVISION_OP ARG_NONE +#define ARGI_SCOPE_OP ARGI_INVALID_OPCODE +#define ARGI_SHIFT_LEFT_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_SHIFT_RIGHT_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_SIGNAL_OP ARGI_LIST1 (ARGI_EVENT) +#define ARGI_SIZE_OF_OP ARGI_LIST1 (ARGI_DATAOBJECT) +#define ARGI_SLEEP_OP ARGI_LIST1 (ARGI_INTEGER) +#define ARGI_STALL_OP ARGI_LIST1 (ARGI_INTEGER) +#define ARGI_STATICSTRING_OP ARGI_INVALID_OPCODE +#define ARGI_STORE_OP ARGI_LIST2 (ARGI_DATAREFOBJ, ARGI_TARGETREF) +#define ARGI_STRING_OP ARGI_INVALID_OPCODE +#define ARGI_SUBTRACT_OP ARGI_LIST3 (ARGI_INTEGER, ARGI_INTEGER, ARGI_TARGETREF) +#define ARGI_THERMAL_ZONE_OP ARGI_INVALID_OPCODE +#define ARGI_TIMER_OP ARG_NONE +#define ARGI_TO_BCD_OP ARGI_LIST2 (ARGI_INTEGER, ARGI_FIXED_TARGET) +#define ARGI_TO_BUFFER_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET) +#define ARGI_TO_DEC_STR_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET) +#define ARGI_TO_HEX_STR_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET) +#define ARGI_TO_INTEGER_OP ARGI_LIST2 (ARGI_COMPUTEDATA,ARGI_FIXED_TARGET) +#define ARGI_TO_STRING_OP ARGI_LIST3 (ARGI_BUFFER, ARGI_INTEGER, ARGI_FIXED_TARGET) +#define ARGI_TYPE_OP ARGI_LIST1 (ARGI_ANYTYPE) +#define ARGI_UNLOAD_OP ARGI_LIST1 (ARGI_DDBHANDLE) +#define ARGI_VAR_PACKAGE_OP ARGI_LIST1 (ARGI_INTEGER) +#define ARGI_WAIT_OP ARGI_LIST2 (ARGI_EVENT, ARGI_INTEGER) +#define ARGI_WHILE_OP ARGI_INVALID_OPCODE +#define ARGI_WORD_OP ARGI_INVALID_OPCODE +#define ARGI_ZERO_OP ARG_NONE + +#endif /* __ACOPCODE_H__ */ diff --git a/include/acpi/acparser.h b/include/acpi/acparser.h index c0395ef2b0d0..698276571818 100644 --- a/include/acpi/acparser.h +++ b/include/acpi/acparser.h @@ -64,8 +64,17 @@ #define ACPI_PARSE_DEFERRED_OP 0x0100 -/* Parser external interfaces */ +/****************************************************************************** + * + * Parser interfaces + * + *****************************************************************************/ + + +/* + * psxface - Parser external interfaces + */ acpi_status acpi_psx_load_table ( u8 *pcode_addr, @@ -76,23 +85,13 @@ acpi_psx_execute ( struct acpi_parameter_info *info); -/****************************************************************************** - * - * Parser interfaces - * - *****************************************************************************/ - - -/* psargs - Parse AML opcode arguments */ - +/* + * psargs - Parse AML opcode arguments + */ u8 * acpi_ps_get_next_package_end ( struct acpi_parse_state *parser_state); -u32 -acpi_ps_get_next_package_length ( - struct acpi_parse_state *parser_state); - char * acpi_ps_get_next_namestring ( struct acpi_parse_state *parser_state); @@ -110,10 +109,6 @@ acpi_ps_get_next_namepath ( union acpi_parse_object *arg, u8 method_call); -union acpi_parse_object * -acpi_ps_get_next_field ( - struct acpi_parse_state *parser_state); - acpi_status acpi_ps_get_next_arg ( struct acpi_walk_state *walk_state, @@ -122,8 +117,9 @@ acpi_ps_get_next_arg ( union acpi_parse_object **return_arg); -/* psfind */ - +/* + * psfind + */ union acpi_parse_object * acpi_ps_find_name ( union acpi_parse_object *scope, @@ -135,8 +131,9 @@ acpi_ps_get_parent ( union acpi_parse_object *op); -/* psopcode - AML Opcode information */ - +/* + * psopcode - AML Opcode information + */ const struct acpi_opcode_info * acpi_ps_get_opcode_info ( u16 opcode); @@ -146,56 +143,25 @@ acpi_ps_get_opcode_name ( u16 opcode); -/* psparse - top level parsing routines */ - -u32 -acpi_ps_get_opcode_size ( - u32 opcode); - -void -acpi_ps_complete_this_op ( - struct acpi_walk_state *walk_state, - union acpi_parse_object *op); - -acpi_status -acpi_ps_next_parse_state ( - struct acpi_walk_state *walk_state, - union acpi_parse_object *op, - acpi_status callback_status); - -acpi_status -acpi_ps_find_object ( - struct acpi_walk_state *walk_state, - union acpi_parse_object **out_op); - -void -acpi_ps_delete_parse_tree ( - union acpi_parse_object *root); - -acpi_status -acpi_ps_parse_loop ( - struct acpi_walk_state *walk_state); - +/* + * psparse - top level parsing routines + */ acpi_status acpi_ps_parse_aml ( struct acpi_walk_state *walk_state); -acpi_status -acpi_ps_parse_table ( - u8 *aml, - u32 aml_size, - acpi_parse_downwards descending_callback, - acpi_parse_upwards ascending_callback, - union acpi_parse_object **root_object); +u32 +acpi_ps_get_opcode_size ( + u32 opcode); u16 acpi_ps_peek_opcode ( struct acpi_parse_state *state); -/* psscope - Scope stack management routines */ - - +/* + * psscope - Scope stack management routines + */ acpi_status acpi_ps_init_scope ( struct acpi_parse_state *parser_state, @@ -228,8 +194,9 @@ acpi_ps_cleanup_scope ( struct acpi_parse_state *state); -/* pstree - parse tree manipulation routines */ - +/* + * pstree - parse tree manipulation routines + */ void acpi_ps_append_arg( union acpi_parse_object *op, @@ -247,20 +214,17 @@ acpi_ps_get_arg( union acpi_parse_object *op, u32 argn); -#ifdef ACPI_FUTURE_USAGE -union acpi_parse_object * -acpi_ps_get_child ( - union acpi_parse_object *op); - +#ifdef ACPI_FUTURE_USAGE union acpi_parse_object * acpi_ps_get_depth_next ( union acpi_parse_object *origin, union acpi_parse_object *op); -#endif /* ACPI_FUTURE_USAGE */ - +#endif /* ACPI_FUTURE_USAGE */ -/* pswalk - parse tree walk routines */ +/* + * pswalk - parse tree walk routines + */ acpi_status acpi_ps_walk_parsed_aml ( union acpi_parse_object *start_op, @@ -283,9 +247,14 @@ acpi_status acpi_ps_delete_completed_op ( struct acpi_walk_state *walk_state); +void +acpi_ps_delete_parse_tree ( + union acpi_parse_object *root); -/* psutils - parser utilities */ +/* + * psutils - parser utilities + */ union acpi_parse_object * acpi_ps_create_scope_op ( void); @@ -303,12 +272,6 @@ void acpi_ps_free_op ( union acpi_parse_object *op); -#ifdef ACPI_ENABLE_OBJECT_CACHE -void -acpi_ps_delete_parse_cache ( - void); -#endif - u8 acpi_ps_is_leading_char ( u32 c); @@ -317,20 +280,27 @@ u8 acpi_ps_is_prefix_char ( u32 c); -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE u32 acpi_ps_get_name( union acpi_parse_object *op); -#endif +#endif /* ACPI_FUTURE_USAGE */ void acpi_ps_set_name( union acpi_parse_object *op, u32 name); +#ifdef ACPI_ENABLE_OBJECT_CACHE +void +acpi_ps_delete_parse_cache ( + void); +#endif -/* psdump - display parser tree */ +/* + * psdump - display parser tree + */ u32 acpi_ps_sprint_path ( char *buffer_start, diff --git a/include/acpi/acpi.h b/include/acpi/acpi.h index ad53252dd42d..a69d78942040 100644 --- a/include/acpi/acpi.h +++ b/include/acpi/acpi.h @@ -49,6 +49,7 @@ * We put them here because we don't want to duplicate them * in the rest of the source code again and again. */ +#include "acnames.h" /* Global ACPI names and strings */ #include "acconfig.h" /* Configuration constants */ #include "platform/acenv.h" /* Target environment specific items */ #include "actypes.h" /* Fundamental common data types */ diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 9ad142476f33..8d0e1290bc76 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -351,6 +351,27 @@ int acpi_match_ids (struct acpi_device *device, char *ids); int acpi_create_dir(struct acpi_device *); void acpi_remove_dir(struct acpi_device *); + +/* + * Bind physical devices with ACPI devices + */ +#include <linux/device.h> +struct acpi_bus_type { + struct list_head list; + struct bus_type *bus; + /* For general devices under the bus*/ + int (*find_device)(struct device *, acpi_handle*); + /* For bridges, such as PCI root bridge, IDE controller */ + int (*find_bridge)(struct device *, acpi_handle *); +}; +int register_acpi_bus_type(struct acpi_bus_type *); +int unregister_acpi_bus_type(struct acpi_bus_type *); +struct device *acpi_get_physical_device(acpi_handle); +/* helper */ +acpi_handle acpi_get_child(acpi_handle, acpi_integer); +acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); +#define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->firmware_data)) + #endif /*CONFIG_ACPI_BUS*/ #endif /*__ACPI_BUS_H__*/ diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index 4ec722d73381..579fe191b7e7 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -56,8 +56,9 @@ /* ACPI PCI Interrupt Link (pci_link.c) */ int acpi_irq_penalty_init (void); -int acpi_pci_link_get_irq (acpi_handle handle, int index, int *edge_level, +int acpi_pci_link_allocate_irq (acpi_handle handle, int index, int *edge_level, int *active_high_low, char **name); +int acpi_pci_link_free_irq(acpi_handle handle); /* ACPI PCI Interrupt Routing (pci_irq.c) */ @@ -109,5 +110,10 @@ int acpi_ec_ecdt_probe (void); int acpi_processor_set_thermal_limit(acpi_handle handle, int type); +/* -------------------------------------------------------------------------- + Hot Keys + -------------------------------------------------------------------------- */ + +extern int acpi_specific_hotkey_enabled; #endif /*__ACPI_DRIVERS_H__*/ diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index 857c8072eb1e..ea489f235216 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -79,7 +79,6 @@ struct acpi_signal_fatal_info /* * OSL Initialization and shutdown primitives */ - acpi_status acpi_os_initialize ( void); @@ -92,7 +91,6 @@ acpi_os_terminate ( /* * ACPI Table interfaces */ - acpi_status acpi_os_get_root_pointer ( u32 flags, @@ -112,7 +110,6 @@ acpi_os_table_override ( /* * Synchronization primitives */ - acpi_status acpi_os_create_semaphore ( u32 max_units, @@ -156,7 +153,6 @@ acpi_os_release_lock ( /* * Memory allocation and mapping */ - void * acpi_os_allocate ( acpi_size size); @@ -187,7 +183,6 @@ acpi_os_get_physical_address ( /* * Interrupt handlers */ - acpi_status acpi_os_install_interrupt_handler ( u32 gsi, @@ -203,7 +198,6 @@ acpi_os_remove_interrupt_handler ( /* * Threads and Scheduling */ - u32 acpi_os_get_thread_id ( void); @@ -234,7 +228,6 @@ acpi_os_stall ( /* * Platform and hardware-independent I/O interfaces */ - acpi_status acpi_os_read_port ( acpi_io_address address, @@ -251,7 +244,6 @@ acpi_os_write_port ( /* * Platform and hardware-independent physical memory interfaces */ - acpi_status acpi_os_read_memory ( acpi_physical_address address, @@ -270,7 +262,6 @@ acpi_os_write_memory ( * Note: Can't use "Register" as a parameter, changed to "Reg" -- * certain compilers complain. */ - acpi_status acpi_os_read_pci_configuration ( struct acpi_pci_id *pci_id, @@ -288,7 +279,6 @@ acpi_os_write_pci_configuration ( /* * Interim function needed for PCI IRQ routing */ - void acpi_os_derive_pci_id( acpi_handle rhandle, @@ -298,7 +288,6 @@ acpi_os_derive_pci_id( /* * Miscellaneous */ - u8 acpi_os_readable ( void *pointer, @@ -323,7 +312,6 @@ acpi_os_signal ( /* * Debug print routines */ - void ACPI_INTERNAL_VAR_XFACE acpi_os_printf ( const char *format, @@ -339,11 +327,10 @@ acpi_os_redirect_output ( void *destination); +#ifdef ACPI_FUTURE_USAGE /* * Debug input */ - -#ifdef ACPI_FUTURE_USAGE u32 acpi_os_get_line ( char *buffer); @@ -353,7 +340,6 @@ acpi_os_get_line ( /* * Directory manipulation */ - void * acpi_os_open_directory ( char *pathname, @@ -377,7 +363,6 @@ acpi_os_close_directory ( /* * Debug */ - void acpi_os_dbg_assert( void *failed_assertion, @@ -385,5 +370,4 @@ acpi_os_dbg_assert( u32 line_number, char *message); - #endif /* __ACPIOSXF_H__ */ diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 00d78b79652e..f8f619f8e4f8 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -50,10 +50,9 @@ #include "actbl.h" - /* +/* * Global interfaces */ - acpi_status acpi_initialize_subsystem ( void); @@ -106,9 +105,8 @@ acpi_install_initialization_handler ( #endif /* - * ACPI Memory manager + * ACPI Memory managment */ - void * acpi_allocate ( u32 size); @@ -125,7 +123,6 @@ acpi_free ( /* * ACPI table manipulation interfaces */ - acpi_status acpi_find_root_pointer ( u32 flags, @@ -168,7 +165,6 @@ acpi_get_firmware_table ( /* * Namespace and name interfaces */ - acpi_status acpi_walk_namespace ( acpi_object_type type, @@ -218,7 +214,6 @@ acpi_get_data ( /* * Object manipulation and enumeration */ - acpi_status acpi_evaluate_object ( acpi_handle object, @@ -262,7 +257,6 @@ acpi_get_parent ( /* * Event handler interfaces */ - acpi_status acpi_install_fixed_event_handler ( u32 acpi_event, @@ -319,7 +313,6 @@ acpi_install_exception_handler ( /* * Event interfaces */ - acpi_status acpi_acquire_global_lock ( u16 timeout, @@ -404,7 +397,6 @@ acpi_remove_gpe_block ( /* * Resource interfaces */ - typedef acpi_status (*ACPI_WALK_RESOURCE_CALLBACK) ( struct acpi_resource *resource, @@ -448,7 +440,6 @@ acpi_resource_to_address64 ( /* * Hardware (ACPI device) interfaces */ - acpi_status acpi_get_register ( u32 register_id, diff --git a/include/acpi/acresrc.h b/include/acpi/acresrc.h index 93c55ff5c237..ed679264c12c 100644 --- a/include/acpi/acresrc.h +++ b/include/acpi/acresrc.h @@ -48,7 +48,6 @@ /* * Function prototypes called from Acpi* APIs */ - acpi_status acpi_rs_get_prt_method_data ( acpi_handle handle, @@ -60,12 +59,12 @@ acpi_rs_get_crs_method_data ( acpi_handle handle, struct acpi_buffer *ret_buffer); -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE acpi_status acpi_rs_get_prs_method_data ( acpi_handle handle, struct acpi_buffer *ret_buffer); -#endif +#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_rs_get_method_data ( @@ -95,61 +94,9 @@ acpi_rs_create_pci_routing_table ( /* - * Function prototypes called from acpi_rs_create* + * rsdump */ -#ifdef ACPI_FUTURE_USAGE -void -acpi_rs_dump_irq ( - union acpi_resource_data *data); - -void -acpi_rs_dump_address16 ( - union acpi_resource_data *data); - -void -acpi_rs_dump_address32 ( - union acpi_resource_data *data); - -void -acpi_rs_dump_address64 ( - union acpi_resource_data *data); - -void -acpi_rs_dump_dma ( - union acpi_resource_data *data); - -void -acpi_rs_dump_io ( - union acpi_resource_data *data); - -void -acpi_rs_dump_extended_irq ( - union acpi_resource_data *data); - -void -acpi_rs_dump_fixed_io ( - union acpi_resource_data *data); - -void -acpi_rs_dump_fixed_memory32 ( - union acpi_resource_data *data); - -void -acpi_rs_dump_memory24 ( - union acpi_resource_data *data); - -void -acpi_rs_dump_memory32 ( - union acpi_resource_data *data); - -void -acpi_rs_dump_start_depend_fns ( - union acpi_resource_data *data); - -void -acpi_rs_dump_vendor_specific ( - union acpi_resource_data *data); - +#ifdef ACPI_FUTURE_USAGE void acpi_rs_dump_resource_list ( struct acpi_resource *resource); @@ -157,8 +104,12 @@ acpi_rs_dump_resource_list ( void acpi_rs_dump_irq_list ( u8 *route_table); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ + +/* + * rscalc + */ acpi_status acpi_rs_get_byte_stream_start ( u8 *byte_stream_buffer, diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h index c97843f6bcbc..e6b9e36a2eda 100644 --- a/include/acpi/acstruct.h +++ b/include/acpi/acstruct.h @@ -56,7 +56,6 @@ * Walk state - current state of a parse tree walk. Used for both a leisurely stroll through * the tree (for whatever reason), and for control method execution. */ - #define ACPI_NEXT_OP_DOWNWARD 1 #define ACPI_NEXT_OP_UPWARD 2 diff --git a/include/acpi/actables.h b/include/acpi/actables.h index e8f5d4ffd452..39df92e21a0d 100644 --- a/include/acpi/actables.h +++ b/include/acpi/actables.h @@ -50,17 +50,9 @@ #define SIZE_IN_HEADER 0 -#ifdef ACPI_FUTURE_USAGE -acpi_status -acpi_tb_handle_to_object ( - u16 table_id, - struct acpi_table_desc **table_desc); -#endif - /* * tbconvrt - Table conversion routines */ - acpi_status acpi_tb_convert_to_xsdt ( struct acpi_table_desc *table_info); @@ -78,10 +70,10 @@ acpi_tb_get_table_count ( struct rsdp_descriptor *RSDP, struct acpi_table_header *RSDT); + /* * tbget - Table "get" routines */ - acpi_status acpi_tb_get_table ( struct acpi_pointer *address, @@ -99,17 +91,6 @@ acpi_tb_get_table_body ( struct acpi_table_desc *table_info); acpi_status -acpi_tb_get_this_table ( - struct acpi_pointer *address, - struct acpi_table_header *header, - struct acpi_table_desc *table_info); - -acpi_status -acpi_tb_table_override ( - struct acpi_table_header *header, - struct acpi_table_desc *table_info); - -acpi_status acpi_tb_get_table_ptr ( acpi_table_type table_type, u32 instance, @@ -127,36 +108,23 @@ acpi_status acpi_tb_validate_rsdt ( struct acpi_table_header *table_ptr); + +/* + * tbgetall - get multiple required tables + */ acpi_status acpi_tb_get_required_tables ( void); -acpi_status -acpi_tb_get_primary_table ( - struct acpi_pointer *address, - struct acpi_table_desc *table_info); - -acpi_status -acpi_tb_get_secondary_table ( - struct acpi_pointer *address, - acpi_string signature, - struct acpi_table_desc *table_info); /* * tbinstall - Table installation */ - acpi_status acpi_tb_install_table ( struct acpi_table_desc *table_info); acpi_status -acpi_tb_match_signature ( - char *signature, - struct acpi_table_desc *table_info, - u8 search_type); - -acpi_status acpi_tb_recognize_table ( struct acpi_table_desc *table_info, u8 search_type); @@ -170,7 +138,6 @@ acpi_tb_init_table_descriptor ( /* * tbremove - Table removal and deletion */ - void acpi_tb_delete_all_tables ( void); @@ -189,35 +156,23 @@ acpi_tb_uninstall_table ( /* - * tbrsd - RSDP, RSDT utilities + * tbxfroot - RSDP, RSDT utilities */ +acpi_status +acpi_tb_find_table ( + char *signature, + char *oem_id, + char *oem_table_id, + struct acpi_table_header **table_ptr); acpi_status acpi_tb_get_table_rsdt ( void); -u8 * -acpi_tb_scan_memory_for_rsdp ( - u8 *start_address, - u32 length); - -acpi_status -acpi_tb_find_rsdp ( - struct acpi_table_desc *table_info, - u32 flags); - /* * tbutils - common table utilities */ - -acpi_status -acpi_tb_find_table ( - char *signature, - char *oem_id, - char *oem_table_id, - struct acpi_table_header **table_ptr); - acpi_status acpi_tb_verify_table_checksum ( struct acpi_table_header *table_header); @@ -231,5 +186,4 @@ acpi_status acpi_tb_validate_table_header ( struct acpi_table_header *table_header); - #endif /* __ACTABLES_H__ */ diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h index 7eee731112b1..b5cdcca444c8 100644 --- a/include/acpi/actbl.h +++ b/include/acpi/actbl.h @@ -133,7 +133,6 @@ struct acpi_table_header /* ACPI common table header */ #define DUAL_PIC 0 #define MULTIPLE_APIC 1 - /* Master MADT */ struct multiple_apic_table @@ -144,7 +143,6 @@ struct multiple_apic_table u32 reserved1 : 31; }; - /* Values for Type in APIC_HEADER_DEF */ #define APIC_PROCESSOR 0 diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index 7acb550af3eb..3a451dc48ac8 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -478,7 +478,6 @@ typedef u32 acpi_object_type; #define ACPI_TYPE_INVALID 0x1E #define ACPI_TYPE_NOT_FOUND 0xFF - /* * Bitmapped ACPI types. Used internally only */ @@ -803,7 +802,6 @@ struct acpi_system_info /* * Types specific to the OS service interfaces */ - typedef u32 (ACPI_SYSTEM_XFACE *acpi_osd_handler) ( void *context); diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h index 0de26b8f1028..192d0bea3884 100644 --- a/include/acpi/acutils.h +++ b/include/acpi/acutils.h @@ -52,13 +52,6 @@ acpi_status (*acpi_pkg_callback) ( union acpi_generic_state *state, void *context); -acpi_status -acpi_ut_walk_package_tree ( - union acpi_operand_object *source_object, - void *target_object, - acpi_pkg_callback walk_callback, - void *context); - struct acpi_pkg_info { u8 *free_space; @@ -79,37 +72,13 @@ struct acpi_pkg_info #define DB_QWORD_DISPLAY 8 -/* Global initialization interfaces */ - -void -acpi_ut_init_globals ( - void); - -void -acpi_ut_terminate ( - void); - - /* - * ut_init - miscellaneous initialization and shutdown + * utglobal - Global data structures and procedures */ - -acpi_status -acpi_ut_hardware_initialize ( - void); - void -acpi_ut_subsystem_shutdown ( - void); - -acpi_status -acpi_ut_validate_fadt ( +acpi_ut_init_globals ( void); -/* - * ut_global - Global data structures and procedures - */ - #if defined(ACPI_DEBUG_OUTPUT) || defined(ACPI_DEBUGGER) char * @@ -157,9 +126,24 @@ acpi_ut_allocate_owner_id ( /* - * ut_clib - Local implementations of C library functions + * utinit - miscellaneous initialization and shutdown */ +acpi_status +acpi_ut_hardware_initialize ( + void); +void +acpi_ut_subsystem_shutdown ( + void); + +acpi_status +acpi_ut_validate_fadt ( + void); + + +/* + * utclib - Local implementations of C library functions + */ #ifndef ACPI_USE_SYSTEM_CLIBRARY acpi_size @@ -260,10 +244,10 @@ extern const u8 _acpi_ctype[]; #endif /* ACPI_USE_SYSTEM_CLIBRARY */ + /* - * ut_copy - Object construction and conversion interfaces + * utcopy - Object construction and conversion interfaces */ - acpi_status acpi_ut_build_simple_object( union acpi_operand_object *obj, @@ -278,30 +262,11 @@ acpi_ut_build_package_object ( u32 *space_used); acpi_status -acpi_ut_copy_ielement_to_eelement ( - u8 object_type, - union acpi_operand_object *source_object, - union acpi_generic_state *state, - void *context); - -acpi_status -acpi_ut_copy_ielement_to_ielement ( - u8 object_type, - union acpi_operand_object *source_object, - union acpi_generic_state *state, - void *context); - -acpi_status acpi_ut_copy_iobject_to_eobject ( union acpi_operand_object *obj, struct acpi_buffer *ret_buffer); acpi_status -acpi_ut_copy_esimple_to_isimple( - union acpi_object *user_obj, - union acpi_operand_object **return_obj); - -acpi_status acpi_ut_copy_eobject_to_iobject ( union acpi_object *obj, union acpi_operand_object **internal_obj); @@ -312,17 +277,6 @@ acpi_ut_copy_isimple_to_isimple ( union acpi_operand_object *dest_obj); acpi_status -acpi_ut_copy_ipackage_to_ipackage ( - union acpi_operand_object *source_obj, - union acpi_operand_object *dest_obj, - struct acpi_walk_state *walk_state); - -acpi_status -acpi_ut_copy_simple_object ( - union acpi_operand_object *source_desc, - union acpi_operand_object *dest_desc); - -acpi_status acpi_ut_copy_iobject_to_iobject ( union acpi_operand_object *source_desc, union acpi_operand_object **dest_desc, @@ -330,9 +284,8 @@ acpi_ut_copy_iobject_to_iobject ( /* - * ut_create - Object creation + * utcreate - Object creation */ - acpi_status acpi_ut_update_object_reference ( union acpi_operand_object *object, @@ -340,9 +293,8 @@ acpi_ut_update_object_reference ( /* - * ut_debug - Debug interfaces + * utdebug - Debug interfaces */ - void acpi_ut_init_stack_ptr_trace ( void); @@ -440,11 +392,14 @@ acpi_ut_debug_print_raw ( /* - * ut_delete - Object deletion + * utdelete - Object deletion and reference counts */ +void +acpi_ut_add_reference ( + union acpi_operand_object *object); void -acpi_ut_delete_internal_obj ( +acpi_ut_remove_reference ( union acpi_operand_object *object); void @@ -461,25 +416,8 @@ acpi_ut_delete_internal_object_list ( /* - * ut_eval - object evaluation + * uteval - object evaluation */ - -/* Method name strings */ - -#define METHOD_NAME__HID "_HID" -#define METHOD_NAME__CID "_CID" -#define METHOD_NAME__UID "_UID" -#define METHOD_NAME__ADR "_ADR" -#define METHOD_NAME__STA "_STA" -#define METHOD_NAME__REG "_REG" -#define METHOD_NAME__SEG "_SEG" -#define METHOD_NAME__BBN "_BBN" -#define METHOD_NAME__PRT "_PRT" -#define METHOD_NAME__CRS "_CRS" -#define METHOD_NAME__PRS "_PRS" -#define METHOD_NAME__PRW "_PRW" - - acpi_status acpi_ut_osi_implementation ( struct acpi_walk_state *walk_state); @@ -522,39 +460,10 @@ acpi_ut_execute_sxds ( struct acpi_namespace_node *device_node, u8 *highest); -/* - * ut_mutex - mutual exclusion interfaces - */ - -acpi_status -acpi_ut_mutex_initialize ( - void); - -void -acpi_ut_mutex_terminate ( - void); - -acpi_status -acpi_ut_create_mutex ( - acpi_mutex_handle mutex_id); - -acpi_status -acpi_ut_delete_mutex ( - acpi_mutex_handle mutex_id); - -acpi_status -acpi_ut_acquire_mutex ( - acpi_mutex_handle mutex_id); - -acpi_status -acpi_ut_release_mutex ( - acpi_mutex_handle mutex_id); - /* - * ut_object - internal object create/delete/cache routines + * utobject - internal object create/delete/cache routines */ - union acpi_operand_object * acpi_ut_create_internal_object_dbg ( char *module_name, @@ -587,50 +496,15 @@ union acpi_operand_object * acpi_ut_create_string_object ( acpi_size string_size); - -/* - * ut_ref_cnt - Object reference count management - */ - -void -acpi_ut_add_reference ( - union acpi_operand_object *object); - -void -acpi_ut_remove_reference ( - union acpi_operand_object *object); - -/* - * ut_size - Object size routines - */ - -acpi_status -acpi_ut_get_simple_object_size ( - union acpi_operand_object *obj, - acpi_size *obj_length); - -acpi_status -acpi_ut_get_package_object_size ( - union acpi_operand_object *obj, - acpi_size *obj_length); - acpi_status acpi_ut_get_object_size( union acpi_operand_object *obj, acpi_size *obj_length); -acpi_status -acpi_ut_get_element_length ( - u8 object_type, - union acpi_operand_object *source_object, - union acpi_generic_state *state, - void *context); - /* - * ut_state - Generic state creation/cache routines + * utstate - Generic state creation/cache routines */ - void acpi_ut_push_generic_state ( union acpi_generic_state **list_head, @@ -666,14 +540,14 @@ acpi_ut_create_update_state_and_push ( u16 action, union acpi_generic_state **state_list); -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE acpi_status acpi_ut_create_pkg_state_and_push ( void *internal_object, void *external_object, u16 index, union acpi_generic_state **state_list); -#endif +#endif /* ACPI_FUTURE_USAGE */ union acpi_generic_state * acpi_ut_create_control_state ( @@ -693,15 +567,10 @@ acpi_ut_delete_object_cache ( void); #endif + /* - * utmisc + * utmath */ - -void -acpi_ut_print_string ( - char *string, - u8 max_length); - acpi_status acpi_ut_divide ( acpi_integer in_dividend, @@ -716,6 +585,25 @@ acpi_ut_short_divide ( acpi_integer *out_quotient, u32 *out_remainder); +/* + * utmisc + */ +acpi_status +acpi_ut_walk_package_tree ( + union acpi_operand_object *source_object, + void *target_object, + acpi_pkg_callback walk_callback, + void *context); + +char * +acpi_ut_strupr ( + char *src_string); + +void +acpi_ut_print_string ( + char *string, + u8 max_length); + u8 acpi_ut_valid_acpi_name ( u32 name); @@ -734,11 +622,21 @@ acpi_ut_strtoul64 ( #define ACPI_ANY_BASE 0 -#ifdef ACPI_FUTURE_USAGE -char * -acpi_ut_strupr ( - char *src_string); -#endif +acpi_status +acpi_ut_mutex_initialize ( + void); + +void +acpi_ut_mutex_terminate ( + void); + +acpi_status +acpi_ut_acquire_mutex ( + acpi_mutex_handle mutex_id); + +acpi_status +acpi_ut_release_mutex ( + acpi_mutex_handle mutex_id); u8 * acpi_ut_get_resource_end_tag ( @@ -768,9 +666,8 @@ acpi_ut_display_init_pathname ( /* - * Utalloc - memory allocation and object caching + * utalloc - memory allocation and object caching */ - void * acpi_ut_acquire_from_cache ( u32 list_id); @@ -795,9 +692,6 @@ acpi_ut_initialize_buffer ( struct acpi_buffer *buffer, acpi_size required_length); - -/* Memory allocation functions */ - void * acpi_ut_allocate ( acpi_size size, @@ -812,9 +706,7 @@ acpi_ut_callocate ( char *module, u32 line); - #ifdef ACPI_DBG_TRACK_ALLOCATIONS - void * acpi_ut_allocate_and_track ( acpi_size size, @@ -836,34 +728,11 @@ acpi_ut_free_and_track ( char *module, u32 line); -struct acpi_debug_mem_block * -acpi_ut_find_allocation ( - u32 list_id, - void *allocation); - -acpi_status -acpi_ut_track_allocation ( - u32 list_id, - struct acpi_debug_mem_block *address, - acpi_size size, - u8 alloc_type, - u32 component, - char *module, - u32 line); - -acpi_status -acpi_ut_remove_allocation ( - u32 list_id, - struct acpi_debug_mem_block *address, - u32 component, - char *module, - u32 line); - -#ifdef ACPI_FUTURE_USAGE +#ifdef ACPI_FUTURE_USAGE void acpi_ut_dump_allocation_info ( void); -#endif +#endif /* ACPI_FUTURE_USAGE */ void acpi_ut_dump_allocations ( @@ -871,5 +740,4 @@ acpi_ut_dump_allocations ( char *module); #endif - #endif /* _ACUTILS_H */ diff --git a/include/acpi/amlcode.h b/include/acpi/amlcode.h index 2ec538eac58e..55e97ed29190 100644 --- a/include/acpi/amlcode.h +++ b/include/acpi/amlcode.h @@ -146,8 +146,7 @@ /* prefixed opcodes */ -#define AML_EXTOP (u16) 0x005b - +#define AML_EXTOP (u16) 0x005b /* prefix for 2-byte opcodes */ #define AML_MUTEX_OP (u16) 0x5b01 #define AML_EVENT_OP (u16) 0x5b02 @@ -194,7 +193,6 @@ * Use only "Unknown" AML opcodes, don't attempt to use * any valid ACPI ASCII values (A-Z, 0-9, '-') */ - #define AML_INT_NAMEPATH_OP (u16) 0x002d #define AML_INT_NAMEDFIELD_OP (u16) 0x0030 #define AML_INT_RESERVEDFIELD_OP (u16) 0x0031 @@ -214,7 +212,6 @@ * There can be up to 31 unique argument types * Zero is reserved as end-of-list indicator */ - #define ARGP_BYTEDATA 0x01 #define ARGP_BYTELIST 0x02 #define ARGP_CHARLIST 0x03 @@ -295,7 +292,6 @@ /* * opcode groups and types */ - #define OPGRP_NAMED 0x01 #define OPGRP_FIELD 0x02 #define OPGRP_BYTELIST 0x04 @@ -381,6 +377,12 @@ #define AML_TYPE_UNDEFINED 0x19 #define AML_TYPE_BOGUS 0x1A +/* AML Package Length encodings */ + +#define ACPI_AML_PACKAGE_TYPE1 0x40 +#define ACPI_AML_PACKAGE_TYPE2 0x4000 +#define ACPI_AML_PACKAGE_TYPE3 0x400000 +#define ACPI_AML_PACKAGE_TYPE4 0x40000000 /* * Opcode classes diff --git a/include/acpi/pdc_intel.h b/include/acpi/pdc_intel.h new file mode 100644 index 000000000000..fd6730e4e567 --- /dev/null +++ b/include/acpi/pdc_intel.h @@ -0,0 +1,29 @@ + +/* _PDC bit definition for Intel processors */ + +#ifndef __PDC_INTEL_H__ +#define __PDC_INTEL_H__ + +#define ACPI_PDC_P_FFH (0x0001) +#define ACPI_PDC_C_C1_HALT (0x0002) +#define ACPI_PDC_T_FFH (0x0004) +#define ACPI_PDC_SMP_C1PT (0x0008) +#define ACPI_PDC_SMP_C2C3 (0x0010) +#define ACPI_PDC_SMP_P_SWCOORD (0x0020) +#define ACPI_PDC_SMP_C_SWCOORD (0x0040) +#define ACPI_PDC_SMP_T_SWCOORD (0x0080) +#define ACPI_PDC_C_C1_FFH (0x0100) + + +#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \ + ACPI_PDC_C_C1_HALT) + +#define ACPI_PDC_EST_CAPABILITY_SMP_MSR (ACPI_PDC_EST_CAPABILITY_SMP | \ + ACPI_PDC_P_FFH) + +#define ACPI_PDC_C_CAPABILITY_SMP (ACPI_PDC_SMP_C2C3 | \ + ACPI_PDC_SMP_C1PT | \ + ACPI_PDC_C_C1_HALT) + +#endif /* __PDC_INTEL_H__ */ + diff --git a/include/acpi/platform/acenv.h b/include/acpi/platform/acenv.h index 57bf9362335d..adf969efa510 100644 --- a/include/acpi/platform/acenv.h +++ b/include/acpi/platform/acenv.h @@ -198,6 +198,7 @@ #endif #endif /* !DEBUGGER_THREADING */ + /****************************************************************************** * * C library configuration @@ -209,7 +210,6 @@ * Use the standard C library headers. * We want to keep these to a minimum. */ - #ifdef ACPI_USE_STANDARD_HEADERS /* * Use the standard headers from the standard locations @@ -224,14 +224,8 @@ /* * We will be linking to the standard Clib functions */ - #define ACPI_STRSTR(s1,s2) strstr((s1), (s2)) #define ACPI_STRCHR(s1,c) strchr((s1), (c)) - -#ifdef ACPI_FUTURE_USAGE -#define ACPI_STRUPR(s) (void) acpi_ut_strupr ((s)) -#endif - #define ACPI_STRLEN(s) (acpi_size) strlen((s)) #define ACPI_STRCPY(d,s) (void) strcpy((d), (s)) #define ACPI_STRNCPY(d,s,n) (void) strncpy((d), (s), (acpi_size)(n)) @@ -254,14 +248,15 @@ #define ACPI_IS_ALPHA isalpha #define ACPI_IS_ASCII isascii +#else + /****************************************************************************** * * Not using native C library, use local implementations * *****************************************************************************/ -#else -/* + /* * Use local definitions of C library macros and functions * NOTE: The function implementations may not be as efficient * as an inline or assembly code implementation provided by a @@ -278,14 +273,12 @@ typedef char *va_list; /* * Storage alignment properties */ - #define _AUPBND (sizeof (acpi_native_int) - 1) #define _ADNBND (sizeof (acpi_native_int) - 1) /* * Variable argument list macro definitions */ - #define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) #define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) #define va_end(ap) (void) 0 @@ -296,11 +289,6 @@ typedef char *va_list; #define ACPI_STRSTR(s1,s2) acpi_ut_strstr ((s1), (s2)) #define ACPI_STRCHR(s1,c) acpi_ut_strchr ((s1), (c)) - -#ifdef ACPI_FUTURE_USAGE -#define ACPI_STRUPR(s) (void) acpi_ut_strupr ((s)) -#endif - #define ACPI_STRLEN(s) (acpi_size) acpi_ut_strlen ((s)) #define ACPI_STRCPY(d,s) (void) acpi_ut_strcpy ((d), (s)) #define ACPI_STRNCPY(d,s,n) (void) acpi_ut_strncpy ((d), (s), (acpi_size)(n)) diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 2f50a5bb0c78..50cfea4ff6ca 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -4,6 +4,8 @@ #include <linux/kernel.h> #include <linux/config.h> +#include <asm/acpi.h> + #define ACPI_PROCESSOR_BUSY_METRIC 10 #define ACPI_PROCESSOR_MAX_POWER 8 @@ -14,6 +16,8 @@ #define ACPI_PROCESSOR_MAX_THROTTLE 250 /* 25% */ #define ACPI_PROCESSOR_MAX_DUTY_WIDTH 4 +#define ACPI_PDC_REVISION_ID 0x1 + /* Power Management */ struct acpi_processor_cx; @@ -59,6 +63,9 @@ struct acpi_processor_power { u32 bm_activity; int count; struct acpi_processor_cx states[ACPI_PROCESSOR_MAX_POWER]; + + /* the _PDC objects passed by the driver, if any */ + struct acpi_object_list *pdc; }; /* Performance Management */ @@ -82,8 +89,6 @@ struct acpi_processor_px { acpi_integer status; /* success indicator */ }; -#define ACPI_PDC_REVISION_ID 0x1 - struct acpi_processor_performance { unsigned int state; unsigned int platform_limit; @@ -179,7 +184,32 @@ int acpi_processor_notify_smm(struct module *calling_module); extern struct acpi_processor *processors[NR_CPUS]; extern struct acpi_processor_errata errata; +int acpi_processor_set_pdc(struct acpi_processor *pr, + struct acpi_object_list *pdc_in); + +#ifdef ARCH_HAS_POWER_PDC_INIT +void acpi_processor_power_init_pdc(struct acpi_processor_power *pow, + unsigned int cpu); +void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, + unsigned int cpu); +#else +static inline void acpi_processor_power_init_pdc( + struct acpi_processor_power *pow, unsigned int cpu) +{ + pow->pdc = NULL; + return; +} + +static inline void acpi_processor_power_init_bm_check( + struct acpi_processor_flags *flags, unsigned int cpu) +{ + flags->bm_check = 1; + return; +} +#endif + /* in processor_perflib.c */ + #ifdef CONFIG_CPU_FREQ void acpi_processor_ppc_init(void); void acpi_processor_ppc_exit(void); diff --git a/include/asm-alpha/emergency-restart.h b/include/asm-alpha/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-alpha/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-alpha/page.h b/include/asm-alpha/page.h index 0577daffc720..fa0b41b164a7 100644 --- a/include/asm-alpha/page.h +++ b/include/asm-alpha/page.h @@ -63,20 +63,6 @@ typedef unsigned long pgprot_t; #endif /* STRICT_MM_TYPECHECKS */ -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #ifdef USE_48_BIT_KSEG #define PAGE_OFFSET 0xffff800000000000UL #else @@ -112,4 +98,6 @@ extern __inline__ int get_order(unsigned long size) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _ALPHA_PAGE_H */ diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h index b7806aa3785c..f681e675b823 100644 --- a/include/asm-alpha/pci.h +++ b/include/asm-alpha/pci.h @@ -58,7 +58,7 @@ struct pci_controller { extern void pcibios_set_master(struct pci_dev *dev); -extern inline void pcibios_penalize_isa_irq(int irq) +extern inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } @@ -251,6 +251,9 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *, struct resource *); +extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region); + #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h index e139463d9a0e..22b53e369f59 100644 --- a/include/asm-alpha/pgtable.h +++ b/include/asm-alpha/pgtable.h @@ -132,6 +132,10 @@ #define __S110 _PAGE_S(0) #define __S111 _PAGE_S(0) +/* + * pgprot_noncached() is only for infiniband pci support, and a real + * implementation for RAM would be more complicated. + */ #define pgprot_noncached(prot) (prot) /* diff --git a/include/asm-alpha/socket.h b/include/asm-alpha/socket.h index d00259d3dc78..b5193229132a 100644 --- a/include/asm-alpha/socket.h +++ b/include/asm-alpha/socket.h @@ -25,6 +25,8 @@ #define SO_ERROR 0x1007 #define SO_SNDBUF 0x1001 #define SO_RCVBUF 0x1002 +#define SO_SNDBUFFORCE 0x100a +#define SO_RCVBUFFORCE 0x100b #define SO_RCVLOWAT 0x1010 #define SO_SNDLOWAT 0x1011 #define SO_RCVTIMEO 0x1012 diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h index c08ce970ff8c..bdb4d66418f1 100644 --- a/include/asm-alpha/system.h +++ b/include/asm-alpha/system.h @@ -443,22 +443,19 @@ __xchg_u64(volatile long *m, unsigned long val) if something tries to do an invalid xchg(). */ extern void __xchg_called_with_bad_pointer(void); -static inline unsigned long -__xchg(volatile void *ptr, unsigned long x, int size) -{ - switch (size) { - case 1: - return __xchg_u8(ptr, x); - case 2: - return __xchg_u16(ptr, x); - case 4: - return __xchg_u32(ptr, x); - case 8: - return __xchg_u64(ptr, x); - } - __xchg_called_with_bad_pointer(); - return x; -} +#define __xchg(ptr, x, size) \ +({ \ + unsigned long __xchg__res; \ + volatile void *__xchg__ptr = (ptr); \ + switch (size) { \ + case 1: __xchg__res = __xchg_u8(__xchg__ptr, x); break; \ + case 2: __xchg__res = __xchg_u16(__xchg__ptr, x); break; \ + case 4: __xchg__res = __xchg_u32(__xchg__ptr, x); break; \ + case 8: __xchg__res = __xchg_u64(__xchg__ptr, x); break; \ + default: __xchg_called_with_bad_pointer(); __xchg__res = x; \ + } \ + __xchg__res; \ +}) #define xchg(ptr,x) \ ({ \ diff --git a/include/asm-alpha/types.h b/include/asm-alpha/types.h index 43264d219246..f5716139ec89 100644 --- a/include/asm-alpha/types.h +++ b/include/asm-alpha/types.h @@ -56,8 +56,6 @@ typedef unsigned long u64; typedef u64 dma_addr_t; typedef u64 dma64_addr_t; -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _ALPHA_TYPES_H */ diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h index 535bc425f243..ef25b6585119 100644 --- a/include/asm-alpha/unistd.h +++ b/include/asm-alpha/unistd.h @@ -377,8 +377,13 @@ #define __NR_add_key 439 #define __NR_request_key 440 #define __NR_keyctl 441 +#define __NR_ioprio_set 442 +#define __NR_ioprio_get 443 +#define __NR_inotify_init 444 +#define __NR_inotify_add_watch 445 +#define __NR_inotify_rm_watch 446 -#define NR_SYSCALLS 442 +#define NR_SYSCALLS 447 #if defined(__GNUC__) diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h index 2346d454ab9c..7dbc7bbba65d 100644 --- a/include/asm-arm/arch-imx/imxfb.h +++ b/include/asm-arm/arch-imx/imxfb.h @@ -25,6 +25,7 @@ struct imxfb_mach_info { u_int pcr; u_int pwmr; u_int lscr1; + u_int dmacr; u_char * fixed_screen_cpu; dma_addr_t fixed_screen_dma; diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index 7495026e2c18..e350dcb544e8 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h @@ -383,39 +383,45 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) *vaddr++ = inl(io_addr); } -#define __is_io_address(p) (((unsigned long)p >= 0x0) && \ - ((unsigned long)p <= 0x0000ffff)) +#define PIO_OFFSET 0x10000UL +#define PIO_MASK 0x0ffffUL + +#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ + ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) static inline unsigned int -__ixp4xx_ioread8(void __iomem *port) +__ixp4xx_ioread8(void __iomem *addr) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)__ixp4xx_inb((unsigned int)port); + return (unsigned int)__ixp4xx_inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - return (unsigned int)__raw_readb((u32)port); + return (unsigned int)__raw_readb(port); #else - return (unsigned int)__ixp4xx_readb((u32)port); + return (unsigned int)__ixp4xx_readb(port); #endif } static inline void -__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count) +__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_insb(port, vaddr, count); + __ixp4xx_insb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsb((void __iomem *)port, vaddr, count); + __raw_readsb(addr, vaddr, count); #else __ixp4xx_readsb(port, vaddr, count); #endif } static inline unsigned int -__ixp4xx_ioread16(void __iomem *port) +__ixp4xx_ioread16(void __iomem *addr) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)__ixp4xx_inw((unsigned int)port); + return (unsigned int)__ixp4xx_inw(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu(__raw_readw((u32)port)); @@ -425,23 +431,25 @@ __ixp4xx_ioread16(void __iomem *port) } static inline void -__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count) +__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_insw(port, vaddr, count); + __ixp4xx_insw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsw((void __iomem *)port, vaddr, count); + __raw_readsw(addr, vaddr, count); #else __ixp4xx_readsw(port, vaddr, count); #endif } static inline unsigned int -__ixp4xx_ioread32(void __iomem *port) +__ixp4xx_ioread32(void __iomem *addr) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - return (unsigned int)__ixp4xx_inl((unsigned int)port); + return (unsigned int)__ixp4xx_inl(port & PIO_MASK); else { #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu(__raw_readl((u32)port)); @@ -452,90 +460,100 @@ __ixp4xx_ioread32(void __iomem *port) } static inline void -__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count) +__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_insl(port, vaddr, count); + __ixp4xx_insl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsl((void __iomem *)port, vaddr, count); + __raw_readsl(addr, vaddr, count); #else __ixp4xx_readsl(port, vaddr, count); #endif } static inline void -__ixp4xx_iowrite8(u8 value, void __iomem *port) +__ixp4xx_iowrite8(u8 value, void __iomem *addr) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outb(value, (unsigned int)port); + __ixp4xx_outb(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writeb(value, (u32)port); + __raw_writeb(value, port); #else - __ixp4xx_writeb(value, (u32)port); + __ixp4xx_writeb(value, port); #endif } static inline void -__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count) +__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outsb(port, vaddr, count); + __ixp4xx_outsb(port & PIO_MASK, vaddr, count); + else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writesb((void __iomem *)port, vaddr, count); + __raw_writesb(addr, vaddr, count); #else __ixp4xx_writesb(port, vaddr, count); #endif } static inline void -__ixp4xx_iowrite16(u16 value, void __iomem *port) +__ixp4xx_iowrite16(u16 value, void __iomem *addr) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outw(value, (unsigned int)port); + __ixp4xx_outw(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writew(cpu_to_le16(value), (u32)port); + __raw_writew(cpu_to_le16(value), addr); #else - __ixp4xx_writew(value, (u32)port); + __ixp4xx_writew(value, port); #endif } static inline void -__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count) +__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outsw(port, vaddr, count); + __ixp4xx_outsw(port & PIO_MASK, vaddr, count); + else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsw((void __iomem *)port, vaddr, count); + __raw_writesw(addr, vaddr, count); #else __ixp4xx_writesw(port, vaddr, count); #endif } static inline void -__ixp4xx_iowrite32(u32 value, void __iomem *port) +__ixp4xx_iowrite32(u32 value, void __iomem *addr) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outl(value, (unsigned int)port); + __ixp4xx_outl(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writel(cpu_to_le32(value), (u32)port); + __raw_writel(cpu_to_le32(value), port); #else - __ixp4xx_writel(value, (u32)port); + __ixp4xx_writel(value, port); #endif } static inline void -__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count) +__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) { + unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) - __ixp4xx_outsl(port, vaddr, count); + __ixp4xx_outsl(port & PIO_MASK, vaddr, count); + else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsl((void __iomem *)port, vaddr, count); + __raw_writesl(addr, vaddr, count); #else - __ixp4xx_outsl(port, vaddr, count); + __ixp4xx_writesl(port, vaddr, count); #endif } @@ -555,7 +573,7 @@ __ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count) #define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) #define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) -#define ioport_map(port, nr) ((void __iomem*)port) +#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) #define ioport_unmap(addr) #endif // __ASM_ARM_ARCH_IO_H diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index 3a626c03ea26..d13ee7f78c70 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h @@ -83,17 +83,6 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); #define IXP4XX_GPIO_OUT 0x1 #define IXP4XX_GPIO_IN 0x2 -#define IXP4XX_GPIO_INTSTYLE_MASK 0x7C /* Bits [6:2] define interrupt style */ - -/* - * GPIO interrupt types. - */ -#define IXP4XX_GPIO_ACTIVE_HIGH 0x4 /* Default */ -#define IXP4XX_GPIO_ACTIVE_LOW 0x8 -#define IXP4XX_GPIO_RISING_EDGE 0x10 -#define IXP4XX_GPIO_FALLING_EDGE 0x20 -#define IXP4XX_GPIO_TRANSITIONAL 0x40 - /* GPIO signal types */ #define IXP4XX_GPIO_LOW 0 #define IXP4XX_GPIO_HIGH 1 @@ -102,7 +91,13 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); #define IXP4XX_GPIO_CLK_0 14 #define IXP4XX_GPIO_CLK_1 15 -extern void gpio_line_config(u8 line, u32 style); +static inline void gpio_line_config(u8 line, u32 direction) +{ + if (direction == IXP4XX_GPIO_OUT) + *IXP4XX_GPIO_GPOER |= (1 << line); + else + *IXP4XX_GPIO_GPOER &= ~(1 << line); +} static inline void gpio_line_get(u8 line, int *value) { diff --git a/include/asm-arm/arch-ixp4xx/timex.h b/include/asm-arm/arch-ixp4xx/timex.h index 38c9d77d3727..3745e35cc030 100644 --- a/include/asm-arm/arch-ixp4xx/timex.h +++ b/include/asm-arm/arch-ixp4xx/timex.h @@ -7,7 +7,9 @@ /* * We use IXP425 General purpose timer for our timer needs, it runs at - * 66.66... MHz + * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the + * timer register ignores the bottom 2 bits of the LATCH value. */ -#define CLOCK_TICK_RATE (66666666) +#define FREQ 66666666 +#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 51f0fe0ac165..939d9e5020a0 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -818,6 +818,23 @@ #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ +#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ + +#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ +#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ +#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ +#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ +#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ +#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ +#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ +#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ +#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ +#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ +#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ +#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ +#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ +#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ + #define UDCCSN(x) __REG2(0x40600100, (x) << 2) #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ #define UDCCSR0_SA (1 << 7) /* Setup Active */ @@ -1423,6 +1440,7 @@ #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) +#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) @@ -1510,6 +1528,8 @@ #define PSSR_BFS (1 << 1) /* Battery Fault Status */ #define PSSR_SSS (1 << 0) /* Software Sleep Status */ +#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ + #define PCFR_RO (1 << 15) /* RDH Override */ #define PCFR_PO (1 << 14) /* PH Override */ #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ @@ -1517,6 +1537,7 @@ #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ +#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ #define PCFR_DS (1 << 3) /* Deep Sleep Mode */ #define PCFR_FS (1 << 2) /* Float Static Chip Selects */ #define PCFR_FP (1 << 1) /* Float PCMCIA controls */ @@ -1810,6 +1831,11 @@ #define LCCR0_PDD_S 12 #define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ +#define LCCR0_LCDT (1 << 22) /* LCD panel type */ +#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ +#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ +#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ +#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ @@ -2062,7 +2088,10 @@ #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */ #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */ #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */ + #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */ +#define UHCRHDA_NOCP (1 << 12) /* No over current protection */ + #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */ #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */ #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */ diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index e5e938b79acc..16f4c3cc1388 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h @@ -1,7 +1,7 @@ /* linux/include/asm/arch-s3c2410/regs-clock.h * - * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ + * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -17,6 +17,7 @@ * 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA + * 27-Aug-2005 Ben Dooks Add clock-slow info */ #ifndef __ASM_ARM_REGS_CLOCK @@ -74,6 +75,12 @@ #define S3C2410_CLKDIVN_PDIVN (1<<0) #define S3C2410_CLKDIVN_HDIVN (1<<1) +#define S3C2410_CLKSLOW_UCLK_OFF (1<<7) +#define S3C2410_CLKSLOW_MPLL_OFF (1<<5) +#define S3C2410_CLKSLOW_SLOW (1<<4) +#define S3C2410_CLKSLOW_SLOWVAL(x) (x) +#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) + #ifndef __ASSEMBLY__ static inline unsigned int diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h index 385b07d510da..fdd62e8cd6cb 100644 --- a/include/asm-arm/arch-s3c2410/regs-iis.h +++ b/include/asm-arm/arch-s3c2410/regs-iis.h @@ -15,6 +15,9 @@ * 12-03-2004 BJD Updated include protection * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL * 05-04-2005 LCVR Added IISFCON definitions for the S3C2400 + * 18-07-2005 DA Change IISCON_MPLL to IISMOD_MPLL + * Correct IISMOD_256FS and IISMOD_384FS + * Add IISCON_PSCEN */ #ifndef __ASM_ARCH_REGS_IIS_H @@ -22,7 +25,6 @@ #define S3C2410_IISCON (0x00) -#define S3C2440_IISCON_MPLL (1<<9) #define S3C2410_IISCON_LRINDEX (1<<8) #define S3C2410_IISCON_TXFIFORDY (1<<7) #define S3C2410_IISCON_RXFIFORDY (1<<6) @@ -30,10 +32,12 @@ #define S3C2410_IISCON_RXDMAEN (1<<4) #define S3C2410_IISCON_TXIDLE (1<<3) #define S3C2410_IISCON_RXIDLE (1<<2) +#define S3C2410_IISCON_PSCEN (1<<1) #define S3C2410_IISCON_IISEN (1<<0) #define S3C2410_IISMOD (0x04) +#define S3C2440_IISMOD_MPLL (1<<9) #define S3C2410_IISMOD_SLAVE (1<<8) #define S3C2410_IISMOD_NOXFER (0<<6) #define S3C2410_IISMOD_RXMODE (1<<6) @@ -46,8 +50,8 @@ #define S3C2410_IISMOD_8BIT (0<<3) #define S3C2410_IISMOD_16BIT (1<<3) #define S3C2410_IISMOD_BITMASK (1<<3) -#define S3C2410_IISMOD_256FS (0<<1) -#define S3C2410_IISMOD_384FS (1<<1) +#define S3C2410_IISMOD_256FS (0<<2) +#define S3C2410_IISMOD_384FS (1<<2) #define S3C2410_IISMOD_16FS (0<<0) #define S3C2410_IISMOD_32FS (1<<0) #define S3C2410_IISMOD_48FS (2<<0) diff --git a/include/asm-arm/arch-s3c2410/usb-control.h b/include/asm-arm/arch-s3c2410/usb-control.h index 1cc85a096b23..bd43b566db3e 100644 --- a/include/asm-arm/arch-s3c2410/usb-control.h +++ b/include/asm-arm/arch-s3c2410/usb-control.h @@ -12,6 +12,7 @@ * Changelog: * 11-Sep-2004 BJD Created file * 21-Sep-2004 BJD Updated port info + * 09-Aug-2005 BJD Renamed s3c2410_report_oc s3c2410_usb_report_oc */ #ifndef __ASM_ARCH_USBCONTROL_H @@ -35,7 +36,7 @@ struct s3c2410_hcd_info { void (*report_oc)(struct s3c2410_hcd_info *, int ports); }; -static void inline s3c2410_report_oc(struct s3c2410_hcd_info *info, int ports) +static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports) { if (info->report_oc != NULL) { (info->report_oc)(info, ports); diff --git a/include/asm-arm/arch-sa1100/mcp.h b/include/asm-arm/arch-sa1100/mcp.h new file mode 100644 index 000000000000..f58a22755c61 --- /dev/null +++ b/include/asm-arm/arch-sa1100/mcp.h @@ -0,0 +1,21 @@ +/* + * linux/include/asm-arm/arch-sa1100/mcp.h + * + * Copyright (C) 2005 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARM_ARCH_MCP_H +#define __ASM_ARM_ARCH_MCP_H + +#include <linux/types.h> + +struct mcp_plat_data { + u32 mccr0; + u32 mccr1; + unsigned int sclk_rate; +}; + +#endif diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h index 1e7f26bc2e1d..5e6ed0038b2b 100644 --- a/include/asm-arm/arch-shark/io.h +++ b/include/asm-arm/arch-shark/io.h @@ -21,38 +21,8 @@ */ #define __PORT_PCIO(x) (!((x) & 0x80000000)) -/* - * Dynamic IO functions - let the compiler - * optimize the expressions - */ -#define DECLARE_DYN_OUT(fnsuffix,instr) \ -static inline void __out##fnsuffix (unsigned int value, unsigned int port) \ -{ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "tst %2, #0x80000000\n\t" \ - "mov %0, %4\n\t" \ - "addeq %0, %0, %3\n\t" \ - "str" instr " %1, [%0, %2] @ out" #fnsuffix \ - : "=&r" (temp) \ - : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ - : "cc"); \ -} +#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) -#define DECLARE_DYN_IN(sz,fnsuffix,instr) \ -static inline unsigned sz __in##fnsuffix (unsigned int port) \ -{ \ - unsigned long temp, value; \ - __asm__ __volatile__( \ - "tst %2, #0x80000000\n\t" \ - "mov %0, %4\n\t" \ - "addeq %0, %0, %3\n\t" \ - "ldr" instr " %1, [%0, %2] @ in" #fnsuffix \ - : "=&r" (temp), "=r" (value) \ - : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ - : "cc"); \ - return (unsigned sz)value; \ -} static inline unsigned int __ioaddr (unsigned int port) \ { \ @@ -62,123 +32,8 @@ static inline unsigned int __ioaddr (unsigned int port) \ return (unsigned int)(IO_BASE + (port)); \ } -#define DECLARE_IO(sz,fnsuffix,instr) \ - DECLARE_DYN_OUT(fnsuffix,instr) \ - DECLARE_DYN_IN(sz,fnsuffix,instr) - -DECLARE_IO(char,b,"b") -DECLARE_IO(short,w,"h") -DECLARE_IO(long,l,"") - -#undef DECLARE_IO -#undef DECLARE_DYN_OUT -#undef DECLARE_DYN_IN - -/* - * Constant address IO functions - * - * These have to be macros for the 'J' constraint to work - - * +/-4096 immediate operand. - */ -#define __outbc(value,port) \ -({ \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (PCIO_BASE), "Jr" (port)); \ - else \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (IO_BASE), "r" (port)); \ -}) - -#define __inbc(port) \ -({ \ - unsigned char result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" (port)); \ - else \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (IO_BASE), "r" (port)); \ - result; \ -}) - -#define __outwc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" (port)); \ - else \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v|v<<16), "r" (IO_BASE), "r" (port)); \ -}) - -#define __inwc(port) \ -({ \ - unsigned short result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" (port)); \ - else \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (IO_BASE), "r" (port)); \ - result & 0xffff; \ -}) - -#define __outlc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" (port)); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (IO_BASE), "r" (port)); \ -}) - -#define __inlc(port) \ -({ \ - unsigned long result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" (port)); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (IO_BASE), "r" (port)); \ - result; \ -}) - -#define __ioaddrc(port) \ -({ \ - unsigned long addr; \ - if (__PORT_PCIO((port))) \ - addr = PCIO_BASE + (port); \ - else \ - addr = IO_BASE + (port); \ - addr; \ -}) - #define __mem_pci(addr) (addr) -#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) -#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) -#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) -#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) -#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) - /* * Translated address IO functions * diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 4edd4dc40c5b..aad7aad026b3 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -21,8 +21,8 @@ #include <asm/system.h> -#define smp_mb__before_clear_bit() do { } while (0) -#define smp_mb__after_clear_bit() do { } while (0) +#define smp_mb__before_clear_bit() mb() +#define smp_mb__after_clear_bit() mb() /* * These functions are the basis of our bit ops. @@ -229,6 +229,7 @@ extern int _find_next_zero_bit_be(const void * p, int size, int offset); extern int _find_first_bit_be(const unsigned long *p, unsigned size); extern int _find_next_bit_be(const unsigned long *p, int size, int offset); +#ifndef CONFIG_SMP /* * The __* form of bitops are non-atomic and may be reordered. */ @@ -241,6 +242,10 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset); (__builtin_constant_p(nr) ? \ ____atomic_##name(nr, p) : \ _##name##_be(nr,p)) +#else +#define ATOMIC_BITOP_LE(name,nr,p) _##name##_le(nr,p) +#define ATOMIC_BITOP_BE(name,nr,p) _##name##_be(nr,p) +#endif #define NONATOMIC_BITOP(name,nr,p) \ (____nonatomic_##name(nr, p)) diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h index 24d11672eb60..7fb02138f585 100644 --- a/include/asm-arm/bug.h +++ b/include/asm-arm/bug.h @@ -5,7 +5,7 @@ #ifdef CONFIG_BUG #ifdef CONFIG_DEBUG_BUGVERBOSE -extern volatile void __bug(const char *file, int line, void *data); +extern void __bug(const char *file, int line, void *data) __attribute__((noreturn)); /* give file/line information */ #define BUG() __bug(__FILE__, __LINE__, NULL) diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h index ff48022e4720..4679f63688e9 100644 --- a/include/asm-arm/cpu-multi32.h +++ b/include/asm-arm/cpu-multi32.h @@ -31,7 +31,7 @@ extern struct processor { /* * Special stuff for a reset */ - volatile void (*reset)(unsigned long addr); + void (*reset)(unsigned long addr) __attribute__((noreturn)); /* * Idle the processor */ diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h index b5ec5d54665d..6723e67244fa 100644 --- a/include/asm-arm/cpu-single.h +++ b/include/asm-arm/cpu-single.h @@ -41,4 +41,4 @@ extern int cpu_do_idle(void); extern void cpu_dcache_clean_area(void *, int); extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); extern void cpu_set_pte(pte_t *ptep, pte_t pte); -extern volatile void cpu_reset(unsigned long addr); +extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); diff --git a/include/asm-arm/emergency-restart.h b/include/asm-arm/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-arm/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-arm/hardware/gic.h b/include/asm-arm/hardware/gic.h new file mode 100644 index 000000000000..3fa5eb70f64e --- /dev/null +++ b/include/asm-arm/hardware/gic.h @@ -0,0 +1,41 @@ +/* + * linux/include/asm-arm/hardware/gic.h + * + * Copyright (C) 2002 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARM_HARDWARE_GIC_H +#define __ASM_ARM_HARDWARE_GIC_H + +#include <linux/compiler.h> + +#define GIC_CPU_CTRL 0x00 +#define GIC_CPU_PRIMASK 0x04 +#define GIC_CPU_BINPOINT 0x08 +#define GIC_CPU_INTACK 0x0c +#define GIC_CPU_EOI 0x10 +#define GIC_CPU_RUNNINGPRI 0x14 +#define GIC_CPU_HIGHPRI 0x18 + +#define GIC_DIST_CTRL 0x000 +#define GIC_DIST_CTR 0x004 +#define GIC_DIST_ENABLE_SET 0x100 +#define GIC_DIST_ENABLE_CLEAR 0x180 +#define GIC_DIST_PENDING_SET 0x200 +#define GIC_DIST_PENDING_CLEAR 0x280 +#define GIC_DIST_ACTIVE_BIT 0x300 +#define GIC_DIST_PRI 0x400 +#define GIC_DIST_TARGET 0x800 +#define GIC_DIST_CONFIG 0xc00 +#define GIC_DIST_SOFTINT 0xf00 + +#ifndef __ASSEMBLY__ +void gic_dist_init(void __iomem *base); +void gic_cpu_init(void __iomem *base); +void gic_raise_softirq(cpumask_t cpumask, unsigned int irq); +#endif + +#endif diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h index c26298f3891f..f08dc8447913 100644 --- a/include/asm-arm/locks.h +++ b/include/asm-arm/locks.h @@ -28,7 +28,8 @@ " blmi " #fail \ : \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ + smp_mb(); \ }) #define __down_op_ret(ptr,fail) \ @@ -48,12 +49,14 @@ " mov %0, ip" \ : "=&r" (ret) \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ + smp_mb(); \ ret; \ }) #define __up_op(ptr,wake) \ ({ \ + smp_mb(); \ __asm__ __volatile__( \ "@ up_op\n" \ "1: ldrex lr, [%0]\n" \ @@ -61,12 +64,12 @@ " strex ip, lr, [%0]\n" \ " teq ip, #0\n" \ " bne 1b\n" \ -" teq lr, #0\n" \ +" cmp lr, #0\n" \ " movle ip, %0\n" \ " blle " #wake \ : \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ }) /* @@ -92,15 +95,17 @@ " blne " #fail \ : \ : "r" (ptr), "I" (RW_LOCK_BIAS) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ + smp_mb(); \ }) #define __up_op_write(ptr,wake) \ ({ \ + smp_mb(); \ __asm__ __volatile__( \ "@ up_op_read\n" \ "1: ldrex lr, [%0]\n" \ -" add lr, lr, %1\n" \ +" adds lr, lr, %1\n" \ " strex ip, lr, [%0]\n" \ " teq ip, #0\n" \ " bne 1b\n" \ @@ -108,7 +113,7 @@ " blcs " #wake \ : \ : "r" (ptr), "I" (RW_LOCK_BIAS) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ }) #define __down_op_read(ptr,fail) \ @@ -116,6 +121,7 @@ #define __up_op_read(ptr,wake) \ ({ \ + smp_mb(); \ __asm__ __volatile__( \ "@ up_op_read\n" \ "1: ldrex lr, [%0]\n" \ @@ -128,7 +134,7 @@ " bleq " #wake \ : \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ }) #else @@ -148,7 +154,8 @@ " blmi " #fail \ : \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ + smp_mb(); \ }) #define __down_op_ret(ptr,fail) \ @@ -169,12 +176,14 @@ " mov %0, ip" \ : "=&r" (ret) \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ + smp_mb(); \ ret; \ }) #define __up_op(ptr,wake) \ ({ \ + smp_mb(); \ __asm__ __volatile__( \ "@ up_op\n" \ " mrs ip, cpsr\n" \ @@ -188,7 +197,7 @@ " blle " #wake \ : \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ }) /* @@ -215,7 +224,8 @@ " blne " #fail \ : \ : "r" (ptr), "I" (RW_LOCK_BIAS) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ + smp_mb(); \ }) #define __up_op_write(ptr,wake) \ @@ -233,7 +243,8 @@ " blcs " #wake \ : \ : "r" (ptr), "I" (RW_LOCK_BIAS) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ + smp_mb(); \ }) #define __down_op_read(ptr,fail) \ @@ -241,6 +252,7 @@ #define __up_op_read(ptr,wake) \ ({ \ + smp_mb(); \ __asm__ __volatile__( \ "@ up_op_read\n" \ " mrs ip, cpsr\n" \ @@ -254,7 +266,7 @@ " bleq " #wake \ : \ : "r" (ptr), "I" (1) \ - : "ip", "lr", "cc", "memory"); \ + : "ip", "lr", "cc"); \ }) #endif diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h index a43a353f6c7b..0ce6ca588d8c 100644 --- a/include/asm-arm/mach/irq.h +++ b/include/asm-arm/mach/irq.h @@ -42,11 +42,11 @@ struct irqchip { /* * Set the type of the IRQ. */ - int (*type)(unsigned int, unsigned int); + int (*set_type)(unsigned int, unsigned int); /* * Set wakeup-enable on the selected IRQ */ - int (*wake)(unsigned int, unsigned int); + int (*set_wake)(unsigned int, unsigned int); #ifdef CONFIG_SMP /* @@ -92,6 +92,14 @@ struct irqdesc { extern struct irqdesc irq_desc[]; /* + * Helpful inline function for calling irq descriptor handlers. + */ +static inline void desc_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) +{ + desc->handle(irq, desc, regs); +} + +/* * This is internal. Do not use it. */ extern void (*init_arch_irq)(void); diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h index 019c45d75730..4da1d532cbeb 100644 --- a/include/asm-arm/page.h +++ b/include/asm-arm/page.h @@ -163,20 +163,6 @@ typedef unsigned long pgprot_t; /* the upper-most page table pointer */ extern pmd_t *top_pmd; -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #include <asm/memory.h> #endif /* !__ASSEMBLY__ */ @@ -186,4 +172,6 @@ static inline int get_order(unsigned long size) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index e300646fe650..38ea5899a580 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -14,7 +14,7 @@ static inline void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -static inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } @@ -60,6 +60,10 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region); + static inline void pcibios_add_platform_entries(struct pci_dev *dev) { } diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index a9892eb42a23..478c49b56e18 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -188,12 +188,18 @@ extern void __pgd_error(const char *file, int line, unsigned long val); /* * - extended small page/tiny page */ +#define PTE_EXT_XN (1 << 0) /* v6 */ #define PTE_EXT_AP_MASK (3 << 4) +#define PTE_EXT_AP0 (1 << 4) +#define PTE_EXT_AP1 (2 << 4) #define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (1 << 4) -#define PTE_EXT_AP_URO_SRW (2 << 4) -#define PTE_EXT_AP_URW_SRW (3 << 4) +#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) +#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) +#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ +#define PTE_EXT_APX (1 << 9) /* v6 */ +#define PTE_EXT_SHARED (1 << 10) /* v6 */ +#define PTE_EXT_NG (1 << 11) /* v6 */ /* * - small page @@ -224,6 +230,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define L_PTE_WRITE (1 << 5) #define L_PTE_EXEC (1 << 6) #define L_PTE_DIRTY (1 << 7) +#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ +#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index 6c6c60adbbaa..dbb4d859c586 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -23,9 +23,6 @@ #define raw_smp_processor_id() (current_thread_info()->cpu) -extern cpumask_t cpu_present_mask; -#define cpu_possible_map cpu_present_mask - /* * at the moment, there's not a big penalty for changing CPUs * (the >big< penalty is running SMP in the first place) diff --git a/include/asm-arm/socket.h b/include/asm-arm/socket.h index 46d20585d951..3c51da6438c9 100644 --- a/include/asm-arm/socket.h +++ b/include/asm-arm/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h index 182323619caa..1f906d09b688 100644 --- a/include/asm-arm/spinlock.h +++ b/include/asm-arm/spinlock.h @@ -8,9 +8,10 @@ /* * ARMv6 Spin-locking. * - * We (exclusively) read the old value, and decrement it. If it - * hits zero, we may have won the lock, so we try (exclusively) - * storing it. + * We exclusively read the old value. If it is zero, we may have + * won the lock, so we try exclusively storing it. A memory barrier + * is required after we get a lock, and before we release it, because + * V6 CPUs are assumed to have weakly ordered memory. * * Unlocked value: 0 * Locked value: 1 @@ -41,7 +42,9 @@ static inline void _raw_spin_lock(spinlock_t *lock) " bne 1b" : "=&r" (tmp) : "r" (&lock->lock), "r" (1) - : "cc", "memory"); + : "cc"); + + smp_mb(); } static inline int _raw_spin_trylock(spinlock_t *lock) @@ -54,18 +57,25 @@ static inline int _raw_spin_trylock(spinlock_t *lock) " strexeq %0, %2, [%1]" : "=&r" (tmp) : "r" (&lock->lock), "r" (1) - : "cc", "memory"); - - return tmp == 0; + : "cc"); + + if (tmp == 0) { + smp_mb(); + return 1; + } else { + return 0; + } } static inline void _raw_spin_unlock(spinlock_t *lock) { + smp_mb(); + __asm__ __volatile__( " str %1, [%0]" : : "r" (&lock->lock), "r" (0) - : "cc", "memory"); + : "cc"); } /* @@ -79,7 +89,8 @@ typedef struct { } rwlock_t; #define RW_LOCK_UNLOCKED (rwlock_t) { 0 } -#define rwlock_init(x) do { *(x) + RW_LOCK_UNLOCKED; } while (0) +#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while (0) +#define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0) /* * Write locks are easy - we just set bit 31. When unlocking, we can @@ -97,16 +108,40 @@ static inline void _raw_write_lock(rwlock_t *rw) " bne 1b" : "=&r" (tmp) : "r" (&rw->lock), "r" (0x80000000) - : "cc", "memory"); + : "cc"); + + smp_mb(); +} + +static inline int _raw_write_trylock(rwlock_t *rw) +{ + unsigned long tmp; + + __asm__ __volatile__( +"1: ldrex %0, [%1]\n" +" teq %0, #0\n" +" strexeq %0, %2, [%1]" + : "=&r" (tmp) + : "r" (&rw->lock), "r" (0x80000000) + : "cc"); + + if (tmp == 0) { + smp_mb(); + return 1; + } else { + return 0; + } } static inline void _raw_write_unlock(rwlock_t *rw) { + smp_mb(); + __asm__ __volatile__( "str %1, [%0]" : : "r" (&rw->lock), "r" (0) - : "cc", "memory"); + : "cc"); } /* @@ -133,11 +168,17 @@ static inline void _raw_read_lock(rwlock_t *rw) " bmi 1b" : "=&r" (tmp), "=&r" (tmp2) : "r" (&rw->lock) - : "cc", "memory"); + : "cc"); + + smp_mb(); } static inline void _raw_read_unlock(rwlock_t *rw) { + unsigned long tmp, tmp2; + + smp_mb(); + __asm__ __volatile__( "1: ldrex %0, [%2]\n" " sub %0, %0, #1\n" @@ -146,24 +187,9 @@ static inline void _raw_read_unlock(rwlock_t *rw) " bne 1b" : "=&r" (tmp), "=&r" (tmp2) : "r" (&rw->lock) - : "cc", "memory"); + : "cc"); } #define _raw_read_trylock(lock) generic_raw_read_trylock(lock) -static inline int _raw_write_trylock(rwlock_t *rw) -{ - unsigned long tmp; - - __asm__ __volatile__( -"1: ldrex %0, [%1]\n" -" teq %0, #0\n" -" strexeq %0, %2, [%1]" - : "=&r" (tmp) - : "r" (&rw->lock), "r" (0x80000000) - : "cc", "memory"); - - return tmp == 0; -} - #endif /* __ASM_SPINLOCK_H */ diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 2f44b2044214..8efa4ebdcacb 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -139,7 +139,12 @@ extern unsigned int user_debug; #define vectors_high() (0) #endif +#if __LINUX_ARM_ARCH__ >= 6 +#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ + : : "r" (0) : "memory") +#else #define mb() __asm__ __volatile__ ("" : : : "memory") +#endif #define rmb() mb() #define wmb() mb() #define read_barrier_depends() do { } while(0) @@ -323,12 +328,8 @@ do { \ * NOTE that this solution won't work on an SMP system, so explcitly * forbid it here. */ -#ifdef CONFIG_SMP -#error SMP is not supported on SA1100/SA110 -#else #define swp_is_buggy #endif -#endif static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) { @@ -337,35 +338,68 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size #ifdef swp_is_buggy unsigned long flags; #endif +#if __LINUX_ARM_ARCH__ >= 6 + unsigned int tmp; +#endif switch (size) { -#ifdef swp_is_buggy - case 1: - local_irq_save(flags); - ret = *(volatile unsigned char *)ptr; - *(volatile unsigned char *)ptr = x; - local_irq_restore(flags); - break; - - case 4: - local_irq_save(flags); - ret = *(volatile unsigned long *)ptr; - *(volatile unsigned long *)ptr = x; - local_irq_restore(flags); - break; +#if __LINUX_ARM_ARCH__ >= 6 + case 1: + asm volatile("@ __xchg1\n" + "1: ldrexb %0, [%3]\n" + " strexb %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; + case 4: + asm volatile("@ __xchg4\n" + "1: ldrex %0, [%3]\n" + " strex %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#elif defined(swp_is_buggy) +#ifdef CONFIG_SMP +#error SMP is not supported on this platform +#endif + case 1: + local_irq_save(flags); + ret = *(volatile unsigned char *)ptr; + *(volatile unsigned char *)ptr = x; + local_irq_restore(flags); + break; + + case 4: + local_irq_save(flags); + ret = *(volatile unsigned long *)ptr; + *(volatile unsigned long *)ptr = x; + local_irq_restore(flags); + break; #else - case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" - : "=&r" (ret) - : "r" (x), "r" (ptr) - : "memory", "cc"); - break; - case 4: __asm__ __volatile__ ("swp %0, %1, [%2]" - : "=&r" (ret) - : "r" (x), "r" (ptr) - : "memory", "cc"); - break; + case 1: + asm volatile("@ __xchg1\n" + " swpb %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; + case 4: + asm volatile("@ __xchg4\n" + " swp %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; #endif - default: __bad_xchg(ptr, size), ret = 0; + default: + __bad_xchg(ptr, size), ret = 0; + break; } return ret; diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h index f4c92e4c8c02..22992ee0627a 100644 --- a/include/asm-arm/types.h +++ b/include/asm-arm/types.h @@ -52,8 +52,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u32 dma64_addr_t; -typedef unsigned int kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index ace27480886e..278de61224d1 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -295,7 +295,7 @@ #define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) #define __NR_tgkill (__NR_SYSCALL_BASE+268) #define __NR_utimes (__NR_SYSCALL_BASE+269) -#define __NR_fadvise64_64 (__NR_SYSCALL_BASE+270) +#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) #define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) #define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) #define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) @@ -350,6 +350,11 @@ #endif #define __NR_vserver (__NR_SYSCALL_BASE+313) +#define __NR_ioprio_set (__NR_SYSCALL_BASE+314) +#define __NR_ioprio_get (__NR_SYSCALL_BASE+315) +#define __NR_inotify_init (__NR_SYSCALL_BASE+316) +#define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) +#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) /* * The following SWIs are ARM private. @@ -510,7 +515,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6 #define __ARCH_WANT_SYS_TIME #define __ARCH_WANT_SYS_UTIME #define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 #define __ARCH_WANT_SYS_GETPGRP #define __ARCH_WANT_SYS_LLSEEK #define __ARCH_WANT_SYS_NICE diff --git a/include/asm-arm26/emergency-restart.h b/include/asm-arm26/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-arm26/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-arm26/page.h b/include/asm-arm26/page.h index c334079b082b..d3f23ac4d468 100644 --- a/include/asm-arm26/page.h +++ b/include/asm-arm26/page.h @@ -89,20 +89,6 @@ typedef unsigned long pgprot_t; #ifdef __KERNEL__ #ifndef __ASSEMBLY__ -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #include <asm/memory.h> #endif /* !__ASSEMBLY__ */ @@ -112,4 +98,6 @@ static inline int get_order(unsigned long size) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif diff --git a/include/asm-arm26/socket.h b/include/asm-arm26/socket.h index 46d20585d951..3c51da6438c9 100644 --- a/include/asm-arm26/socket.h +++ b/include/asm-arm26/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-arm26/types.h b/include/asm-arm26/types.h index 56cbe573a234..81bd357ada02 100644 --- a/include/asm-arm26/types.h +++ b/include/asm-arm26/types.h @@ -52,8 +52,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u32 dma64_addr_t; -typedef unsigned int kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h new file mode 100644 index 000000000000..6ef5e7d09024 --- /dev/null +++ b/include/asm-cris/arch-v10/atomic.h @@ -0,0 +1,7 @@ +#ifndef __ASM_CRIS_ARCH_ATOMIC__ +#define __ASM_CRIS_ARCH_ATOMIC__ + +#define cris_atomic_save(addr, flags) local_irq_save(flags); +#define cris_atomic_restore(addr, flags) local_irq_restore(flags); + +#endif diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h index 21b7ae8c9bb3..b73f5396e5a6 100644 --- a/include/asm-cris/arch-v10/bitops.h +++ b/include/asm-cris/arch-v10/bitops.h @@ -51,7 +51,7 @@ extern inline unsigned long ffz(unsigned long w) * * Undefined if no bit exists, so code should check against 0 first. */ -extern __inline__ unsigned long __ffs(unsigned long word) +extern inline unsigned long __ffs(unsigned long word) { return cris_swapnwbrlz(~word); } diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h index 9e078b9bc934..ecb9dba6fa4f 100644 --- a/include/asm-cris/arch-v10/dma.h +++ b/include/asm-cris/arch-v10/dma.h @@ -44,3 +44,31 @@ #define USB_RX_DMA_NBR 9 #endif + +enum dma_owner +{ + dma_eth, + dma_ser0, + dma_ser1, /* Async and sync */ + dma_ser2, + dma_ser3, /* Async and sync */ + dma_ata, + dma_par0, + dma_par1, + dma_ext0, + dma_ext1, + dma_int6, + dma_int7, + dma_usb, + dma_scsi0, + dma_scsi1 +}; + +/* Masks used by cris_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR (1<<0) +#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) + +int cris_request_dma(unsigned int dmanr, const char * device_id, + unsigned options, enum dma_owner owner); + +void cris_free_dma(unsigned int dmanr, const char * device_id); diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h index 2a2201ca538e..1c38ee728b17 100644 --- a/include/asm-cris/arch-v10/elf.h +++ b/include/asm-cris/arch-v10/elf.h @@ -1,6 +1,16 @@ #ifndef __ASMCRIS_ARCH_ELF_H #define __ASMCRIS_ARCH_ELF_H +#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + ((x)->e_machine == EM_CRIS \ + && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ + || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) + /* * ELF register definitions.. */ diff --git a/include/asm-cris/arch-v10/ide.h b/include/asm-cris/arch-v10/ide.h new file mode 100644 index 000000000000..8cf2d7cb22ac --- /dev/null +++ b/include/asm-cris/arch-v10/ide.h @@ -0,0 +1,99 @@ +/* + * linux/include/asm-cris/ide.h + * + * Copyright (C) 2000, 2001, 2002 Axis Communications AB + * + * Authors: Bjorn Wesen + * + */ + +/* + * This file contains the ETRAX 100LX specific IDE code. + */ + +#ifndef __ASMCRIS_IDE_H +#define __ASMCRIS_IDE_H + +#ifdef __KERNEL__ + +#include <asm/arch/svinto.h> +#include <asm/io.h> +#include <asm-generic/ide_iops.h> + + +/* ETRAX 100 can support 4 IDE busses on the same pins (serialized) */ + +#define MAX_HWIFS 4 + +extern __inline__ int ide_default_irq(unsigned long base) +{ + /* all IDE busses share the same IRQ, number 4. + * this has the side-effect that ide-probe.c will cluster our 4 interfaces + * together in a hwgroup, and will serialize accesses. this is good, because + * we can't access more than one interface at the same time on ETRAX100. + */ + return 4; +} + +extern __inline__ unsigned long ide_default_io_base(int index) +{ + /* we have no real I/O base address per interface, since all go through the + * same register. but in a bitfield in that register, we have the i/f number. + * so we can use the io_base to remember that bitfield. + */ + static const unsigned long io_bases[MAX_HWIFS] = { + IO_FIELD(R_ATA_CTRL_DATA, sel, 0), + IO_FIELD(R_ATA_CTRL_DATA, sel, 1), + IO_FIELD(R_ATA_CTRL_DATA, sel, 2), + IO_FIELD(R_ATA_CTRL_DATA, sel, 3) + }; + return io_bases[index]; +} + +/* this is called once for each interface, to setup the port addresses. data_port is the result + * of the ide_default_io_base call above. ctrl_port will be 0, but that is don't care for us. + */ + +extern __inline__ void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq) +{ + int i; + + /* fill in ports for ATA addresses 0 to 7 */ + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = data_port | + IO_FIELD(R_ATA_CTRL_DATA, addr, i) | + IO_STATE(R_ATA_CTRL_DATA, cs0, active); + } + + /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */ + + hw->io_ports[IDE_CONTROL_OFFSET] = data_port | + IO_FIELD(R_ATA_CTRL_DATA, addr, 6) | + IO_STATE(R_ATA_CTRL_DATA, cs1, active); + + /* whats this for ? */ + + hw->io_ports[IDE_IRQ_OFFSET] = 0; +} + +extern __inline__ void ide_init_default_hwifs(void) +{ + hw_regs_t hw; + int index; + + for(index = 0; index < MAX_HWIFS; index++) { + ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL); + hw.irq = ide_default_irq(ide_default_io_base(index)); + ide_register_hw(&hw, NULL); + } +} + +/* some configuration options we don't need */ + +#undef SUPPORT_VLB_SYNC +#define SUPPORT_VLB_SYNC 0 + +#endif /* __KERNEL__ */ + +#endif /* __ASMCRIS_IDE_H */ diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h index 0bc38a0313c1..dd39198ec67d 100644 --- a/include/asm-cris/arch-v10/io.h +++ b/include/asm-cris/arch-v10/io.h @@ -6,6 +6,7 @@ /* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ +extern unsigned long gen_config_ii_shadow; extern unsigned long port_g_data_shadow; extern unsigned char port_pa_dir_shadow; extern unsigned char port_pa_data_shadow; diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h new file mode 100644 index 000000000000..d92500080883 --- /dev/null +++ b/include/asm-cris/arch-v10/io_interface_mux.h @@ -0,0 +1,75 @@ +/* IO interface mux allocator for ETRAX100LX. + * Copyright 2004, Axis Communications AB + * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ + */ + + +#ifndef _IO_INTERFACE_MUX_H +#define _IO_INTERFACE_MUX_H + + +/* C.f. ETRAX100LX Designer's Reference 20.9 */ + +/* The order in enum must match the order of interfaces[] in + * io_interface_mux.c */ +enum cris_io_interface { + /* Begin Non-multiplexed interfaces */ + if_eth = 0, + if_serial_0, + /* End Non-multiplexed interfaces */ + if_serial_1, + if_serial_2, + if_serial_3, + if_sync_serial_1, + if_sync_serial_3, + if_shared_ram, + if_shared_ram_w, + if_par_0, + if_par_1, + if_par_w, + if_scsi8_0, + if_scsi8_1, + if_scsi_w, + if_ata, + if_csp, + if_i2c, + if_usb_1, + if_usb_2, + /* GPIO pins */ + if_gpio_grp_a, + if_gpio_grp_b, + if_gpio_grp_c, + if_gpio_grp_d, + if_gpio_grp_e, + if_gpio_grp_f, + if_max_interfaces, + if_unclaimed +}; + +int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); + +void cris_free_io_interface(enum cris_io_interface ioif); + +/* port can be 'a', 'b' or 'g' */ +int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, + const char port, + const unsigned start_bit, + const unsigned stop_bit); + +/* port can be 'a', 'b' or 'g' */ +int cris_io_interface_free_pins(const enum cris_io_interface ioif, + const char port, + const unsigned start_bit, + const unsigned stop_bit); + +int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available)); + +void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available)); + +#endif /* _IO_INTERFACE_MUX_H */ diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h index a2a6e1533ea0..4fa8945b0263 100644 --- a/include/asm-cris/arch-v10/irq.h +++ b/include/asm-cris/arch-v10/irq.h @@ -74,12 +74,9 @@ struct etrax_interrupt_vector { }; extern struct etrax_interrupt_vector *etrax_irv; -void set_int_vector(int n, irqvectptr addr, irqvectptr saddr); +void set_int_vector(int n, irqvectptr addr); void set_break_vector(int n, irqvectptr addr); -#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); -#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); - #define __STR(x) #x #define STR(x) __STR(x) @@ -121,26 +118,17 @@ void set_break_vector(int n, irqvectptr addr); #define BUILD_IRQ(nr,mask) \ void IRQ_NAME(nr); \ -void sIRQ_NAME(nr); \ -void BAD_IRQ_NAME(nr); \ __asm__ ( \ ".text\n\t" \ "IRQ" #nr "_interrupt:\n\t" \ SAVE_ALL \ - "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \ BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ "moveq "#nr",$r10\n\t" \ "move.d $sp,$r11\n\t" \ "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ UNBLOCK_IRQ(mask) \ "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t" \ - "bad_IRQ" #nr "_interrupt:\n\t" \ - "push $r0\n\t" \ - BLOCK_IRQ(mask,nr) \ - "pop $r0\n\t" \ - "reti\n\t" \ - "nop\n"); + "jump ret_from_intr\n\t"); /* This is subtle. The timer interrupt is crucial and it should not be disabled for * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would @@ -159,23 +147,14 @@ __asm__ ( \ #define BUILD_TIMER_IRQ(nr,mask) \ void IRQ_NAME(nr); \ -void sIRQ_NAME(nr); \ -void BAD_IRQ_NAME(nr); \ __asm__ ( \ ".text\n\t" \ "IRQ" #nr "_interrupt:\n\t" \ SAVE_ALL \ - "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \ "moveq "#nr",$r10\n\t" \ "move.d $sp,$r11\n\t" \ "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t" \ - "bad_IRQ" #nr "_interrupt:\n\t" \ - "push $r0\n\t" \ - BLOCK_IRQ(mask,nr) \ - "pop $r0\n\t" \ - "reti\n\t" \ - "nop\n"); + "jump ret_from_intr\n\t"); #endif diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h new file mode 100644 index 000000000000..13f3b971407f --- /dev/null +++ b/include/asm-cris/arch-v10/memmap.h @@ -0,0 +1,22 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h index d18aa00e50bc..df84f1716e6b 100644 --- a/include/asm-cris/arch-v10/mmu.h +++ b/include/asm-cris/arch-v10/mmu.h @@ -7,7 +7,10 @@ /* type used in struct mm to couple an MMU context to an active mm */ -typedef unsigned int mm_context_t; +typedef struct +{ + unsigned int page_id; +} mm_context_t; /* kernel memory segments */ diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h index fcbd77eab281..675b51d85639 100644 --- a/include/asm-cris/arch-v10/offset.h +++ b/include/asm-cris/arch-v10/offset.h @@ -25,7 +25,7 @@ #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ #define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ -#define TASK_pid 133 /* offsetof(struct task_struct, pid) */ +#define TASK_pid 141 /* offsetof(struct task_struct, pid) */ #define LCLONE_VM 256 /* CLONE_VM */ #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h index 9355d8675a58..e23df8dc96e8 100644 --- a/include/asm-cris/arch-v10/processor.h +++ b/include/asm-cris/arch-v10/processor.h @@ -59,4 +59,12 @@ struct thread_struct { wrusp(usp); \ } while(0) +/* Called when handling a kernel bus fault fixup. + * + * After a fixup we do not want to return by restoring the CPU-state + * anymore, so switch frame-types (see ptrace.h) + */ +#define arch_fixup(regs) \ + regs->frametype = CRIS_FRAME_NORMAL; + #endif diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h index 781ca30229a8..6cc35642b8ab 100644 --- a/include/asm-cris/arch-v10/system.h +++ b/include/asm-cris/arch-v10/system.h @@ -11,6 +11,8 @@ extern inline unsigned long rdvr(void) { return vr; } +#define cris_machine_name "cris" + /* read/write the user-mode stackpointer */ extern inline unsigned long rdusp(void) { diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h new file mode 100644 index 000000000000..dba3c285cacd --- /dev/null +++ b/include/asm-cris/arch-v32/arbiter.h @@ -0,0 +1,30 @@ +#ifndef _ASM_CRIS_ARCH_ARBITER_H +#define _ASM_CRIS_ARCH_ARBITER_H + +#define EXT_REGION 0 +#define INT_REGION 1 + +typedef void (watch_callback)(void); + +enum +{ + arbiter_all_dmas = 0x3ff, + arbiter_cpu = 0xc00, + arbiter_all_clients = 0x3fff +}; + +enum +{ + arbiter_all_read = 0x55, + arbiter_all_write = 0xaa, + arbiter_all_accesses = 0xff +}; + +int crisv32_arbiter_allocate_bandwith(int client, int region, + unsigned long bandwidth); +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback* cb); +int crisv32_arbiter_unwatch(int id); + +#endif diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h new file mode 100644 index 000000000000..bbfb7a5ae315 --- /dev/null +++ b/include/asm-cris/arch-v32/atomic.h @@ -0,0 +1,36 @@ +#ifndef __ASM_CRIS_ARCH_ATOMIC__ +#define __ASM_CRIS_ARCH_ATOMIC__ + +#include <asm/system.h> + +extern void cris_spin_unlock(void *l, int val); +extern void cris_spin_lock(void *l); +extern int cris_spin_trylock(void* l); + +#ifndef CONFIG_SMP +#define cris_atomic_save(addr, flags) local_irq_save(flags); +#define cris_atomic_restore(addr, flags) local_irq_restore(flags); +#else + +extern spinlock_t cris_atomic_locks[]; +#define LOCK_COUNT 128 +#define HASH_ADDR(a) (((int)a) & 127) + +#define cris_atomic_save(addr, flags) \ + local_irq_save(flags); \ + cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock); + +#define cris_atomic_restore(addr, flags) \ + { \ + spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ + __asm__ volatile ("move.d %1,%0" \ + : "=m" (lock->lock) \ + : "r" (1) \ + : "memory"); \ + local_irq_restore(flags); \ + } + +#endif + +#endif + diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h new file mode 100644 index 000000000000..e40a58d3b862 --- /dev/null +++ b/include/asm-cris/arch-v32/bitops.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CRIS_ARCH_BITOPS_H +#define _ASM_CRIS_ARCH_BITOPS_H + +/* + * Helper functions for the core of the ff[sz] functions. They compute the + * number of leading zeroes of a bits-in-byte, byte-in-word and + * word-in-dword-swapped number. They differ in that the first function also + * inverts all bits in the input. + */ + +extern inline unsigned long +cris_swapnwbrlz(unsigned long w) +{ + unsigned long res; + + __asm__ __volatile__ ("swapnwbr %0\n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + + return res; +} + +extern inline unsigned long +cris_swapwbrlz(unsigned long w) +{ + unsigned long res; + + __asm__ __volatile__ ("swapwbr %0\n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + + return res; +} + +/* + * Find First Zero in word. Undefined if no zero exist, so the caller should + * check against ~0 first. + */ +extern inline unsigned long +ffz(unsigned long w) +{ + return cris_swapnwbrlz(w); +} + +/* + * Find First Set bit in word. Undefined if no 1 exist, so the caller + * should check against 0 first. + */ +extern inline unsigned long +__ffs(unsigned long w) +{ + return cris_swapnwbrlz(~w); +} + +/* + * Find First Bit that is set. + */ +extern inline unsigned long +kernel_ffs(unsigned long w) +{ + return w ? cris_swapwbrlz (w) + 1 : 0; +} + +#endif /* _ASM_CRIS_ARCH_BITOPS_H */ diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h new file mode 100644 index 000000000000..74846ee6cf99 --- /dev/null +++ b/include/asm-cris/arch-v32/byteorder.h @@ -0,0 +1,20 @@ +#ifndef _ASM_CRIS_ARCH_BYTEORDER_H +#define _ASM_CRIS_ARCH_BYTEORDER_H + +#include <asm/types.h> + +extern __inline__ __const__ __u32 +___arch__swab32(__u32 x) +{ + __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); + return (x); +} + +extern __inline__ __const__ __u16 +___arch__swab16(__u16 x) +{ + __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); + return (x); +} + +#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */ diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h new file mode 100644 index 000000000000..4fed8d62ccc8 --- /dev/null +++ b/include/asm-cris/arch-v32/cache.h @@ -0,0 +1,9 @@ +#ifndef _ASM_CRIS_ARCH_CACHE_H +#define _ASM_CRIS_ARCH_CACHE_H + +/* A cache-line is 32 bytes. */ +#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_SHIFT_MAX 5 + +#endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h new file mode 100644 index 000000000000..a1d6b2a6cc44 --- /dev/null +++ b/include/asm-cris/arch-v32/checksum.h @@ -0,0 +1,29 @@ +#ifndef _ASM_CRIS_ARCH_CHECKSUM_H +#define _ASM_CRIS_ARCH_CHECKSUM_H + +/* + * Check values used in TCP/UDP headers. + * + * The gain of doing this in assembler instead of C, is that C doesn't + * generate carry-additions for the 32-bit components of the + * checksum. Which means it would be necessary to split all those into + * 16-bit components and then add. + */ +extern inline unsigned int +csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, + unsigned short len, unsigned short proto, unsigned int sum) +{ + int res; + + __asm__ __volatile__ ("add.d %2, %0\n\t" + "addc %3, %0\n\t" + "addc %4, %0\n\t" + "addc 0, %0\n\t" + : "=r" (res) + : "0" (sum), "r" (daddr), "r" (saddr), \ + "r" ((ntohs(len) << 16) + (proto << 8))); + + return res; +} + +#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h new file mode 100644 index 000000000000..dfa1f66fb987 --- /dev/null +++ b/include/asm-cris/arch-v32/cryptocop.h @@ -0,0 +1,272 @@ +/* + * The device /dev/cryptocop is accessible using this driver using + * CRYPTOCOP_MAJOR (254) and minor number 0. + */ + +#ifndef CRYPTOCOP_H +#define CRYPTOCOP_H + +#include <linux/uio.h> + + +#define CRYPTOCOP_SESSION_ID_NONE (0) + +typedef unsigned long long int cryptocop_session_id; + +/* cryptocop ioctls */ +#define ETRAXCRYPTOCOP_IOCTYPE (250) + +#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) +#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) +#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) +#define CRYPTOCOP_IO_MAXNR (3) + +typedef enum { + cryptocop_cipher_des = 0, + cryptocop_cipher_3des = 1, + cryptocop_cipher_aes = 2, + cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ + cryptocop_cipher_none +} cryptocop_cipher_type; + +typedef enum { + cryptocop_digest_sha1 = 0, + cryptocop_digest_md5 = 1, + cryptocop_digest_none +} cryptocop_digest_type; + +typedef enum { + cryptocop_csum_le = 0, + cryptocop_csum_be = 1, + cryptocop_csum_none +} cryptocop_csum_type; + +typedef enum { + cryptocop_cipher_mode_ecb = 0, + cryptocop_cipher_mode_cbc, + cryptocop_cipher_mode_none +} cryptocop_cipher_mode; + +typedef enum { + cryptocop_3des_eee = 0, + cryptocop_3des_eed = 1, + cryptocop_3des_ede = 2, + cryptocop_3des_edd = 3, + cryptocop_3des_dee = 4, + cryptocop_3des_ded = 5, + cryptocop_3des_dde = 6, + cryptocop_3des_ddd = 7 +} cryptocop_3des_mode; + +/* Usermode accessible (ioctl) operations. */ +struct strcop_session_op{ + cryptocop_session_id ses_id; + + cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ + + cryptocop_cipher_mode cmode; /* ECB, CBC, none */ + cryptocop_3des_mode des3_mode; + + cryptocop_digest_type digest; /* MD5, SHA1, none */ + + cryptocop_csum_type csum; /* BE, LE, none */ + + unsigned char *key; + size_t keylen; +}; + +#define CRYPTOCOP_CSUM_LENGTH (2) +#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ +#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ +#define CRYPTOCOP_MAX_KEY_LENGTH (32) + +struct strcop_crypto_op{ + cryptocop_session_id ses_id; + + /* Indata. */ + unsigned char *indata; + size_t inlen; /* Total indata length. */ + + /* Cipher configuration. */ + unsigned char do_cipher:1; + unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ + unsigned char cipher_explicit:1; + size_t cipher_start; + size_t cipher_len; + /* cipher_iv is used if do_cipher and cipher_explicit and the cipher + mode is CBC. The length is controlled by the type of cipher, + e.g. DES/3DES 8 octets and AES 16 octets. */ + unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; + /* Outdata. */ + unsigned char *cipher_outdata; + size_t cipher_outlen; + + /* digest configuration. */ + unsigned char do_digest:1; + size_t digest_start; + size_t digest_len; + /* Outdata. The actual length is determined by the type of the digest. */ + unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; + + /* Checksum configuration. */ + unsigned char do_csum:1; + size_t csum_start; + size_t csum_len; + /* Outdata. */ + unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; +}; + + + +#ifdef __KERNEL__ + +/********** The API to use from inside the kernel. ************/ + +#include <asm/arch/hwregs/dma.h> + +typedef enum { + cryptocop_alg_csum = 0, + cryptocop_alg_mem2mem, + cryptocop_alg_md5, + cryptocop_alg_sha1, + cryptocop_alg_des, + cryptocop_alg_3des, + cryptocop_alg_aes, + cryptocop_no_alg, +} cryptocop_algorithm; + +typedef u8 cryptocop_tfrm_id; + + +struct cryptocop_operation; + +typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); + +struct cryptocop_transform_init { + cryptocop_algorithm alg; + /* Keydata for ciphers. */ + unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; + unsigned int keylen; + cryptocop_cipher_mode cipher_mode; + cryptocop_3des_mode tdes_mode; + cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ + + cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ + struct cryptocop_transform_init *next; +}; + + +typedef enum { + cryptocop_source_dma = 0, + cryptocop_source_des, + cryptocop_source_3des, + cryptocop_source_aes, + cryptocop_source_md5, + cryptocop_source_sha1, + cryptocop_source_csum, + cryptocop_source_none, +} cryptocop_source; + + +struct cryptocop_desc_cfg { + cryptocop_tfrm_id tid; + cryptocop_source src; + unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ + struct cryptocop_desc_cfg *next; +}; + +struct cryptocop_desc { + size_t length; + struct cryptocop_desc_cfg *cfg; + struct cryptocop_desc *next; +}; + + +/* Flags for cryptocop_tfrm_cfg */ +#define CRYPTOCOP_NO_FLAG (0x00) +#define CRYPTOCOP_ENCRYPT (0x01) +#define CRYPTOCOP_DECRYPT (0x02) +#define CRYPTOCOP_EXPLICIT_IV (0x04) + +struct cryptocop_tfrm_cfg { + cryptocop_tfrm_id tid; + + unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ + + /* CBC initialisation vector for cihers. */ + u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; + + /* The position in output where to write the transform output. The order + in which the driver writes the output is unspecified, hence if several + transforms write on the same positions in the output the result is + unspecified. */ + size_t inject_ix; + + struct cryptocop_tfrm_cfg *next; +}; + + + +struct cryptocop_dma_list_operation{ + /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in + struct cryptocop_operation must be set for the driver to use them. outlist, + out_data_buf, inlist and in_data_buf must all be physical addresses since they will + be loaded to DMA . */ + dma_descr_data *outlist; /* Out from memory to the co-processor. */ + char *out_data_buf; + dma_descr_data *inlist; /* In from the co-processor to memory. */ + char *in_data_buf; + + cryptocop_3des_mode tdes_mode; + cryptocop_csum_type csum_mode; +}; + + +struct cryptocop_tfrm_operation{ + /* Operation configuration, if not 'use_dmalists' is set. */ + struct cryptocop_tfrm_cfg *tfrm_cfg; + struct cryptocop_desc *desc; + + struct iovec *indata; + size_t incount; + size_t inlen; /* Total inlength. */ + + struct iovec *outdata; + size_t outcount; + size_t outlen; /* Total outlength. */ +}; + + +struct cryptocop_operation { + cryptocop_callback *cb; + void *cb_data; + + cryptocop_session_id sid; + + /* The status of the operation when returned to consumer. */ + int operation_status; /* 0, -EAGAIN */ + + /* Flags */ + unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ + unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ + unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ + + union{ + struct cryptocop_dma_list_operation list_op; + struct cryptocop_tfrm_operation tfrm_op; + }; +}; + + +int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); +int cryptocop_free_session(cryptocop_session_id sid); + +int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); + +int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); + +int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); + +#endif /* __KERNEL__ */ + +#endif /* CRYPTOCOP_H */ diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h new file mode 100644 index 000000000000..f36f7f760e89 --- /dev/null +++ b/include/asm-cris/arch-v32/delay.h @@ -0,0 +1,18 @@ +#ifndef _ASM_CRIS_ARCH_DELAY_H +#define _ASM_CRIS_ARCH_DELAY_H + +extern __inline__ void +__delay(int loops) +{ + __asm__ __volatile__ ( + "move.d %0, $r9\n\t" + "beq 2f\n\t" + "subq 1, $r9\n\t" + "1:\n\t" + "bne 1b\n\t" + "subq 1, $r9\n" + "2:" + : : "g" (loops) : "r9"); +} + +#endif /* _ASM_CRIS_ARCH_DELAY_H */ diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h new file mode 100644 index 000000000000..3674081389fd --- /dev/null +++ b/include/asm-cris/arch-v32/dma.h @@ -0,0 +1,79 @@ +#ifndef _ASM_ARCH_CRIS_DMA_H +#define _ASM_ARCH_CRIS_DMA_H + +/* Defines for using and allocating dma channels. */ + +#define MAX_DMA_CHANNELS 10 + +#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ +#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ + +#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ +#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ + +#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ +#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ + +#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ +#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ + +#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ +#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ + +#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ +#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ + +#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ +#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ + +#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ +#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ + +#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ +#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ + +#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ +#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ + +#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ +#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ + +#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ +#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ + +#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ +#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ + +#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ +#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ + +enum dma_owner +{ + dma_eth0, + dma_eth1, + dma_iop0, + dma_iop1, + dma_ser0, + dma_ser1, + dma_ser2, + dma_ser3, + dma_sser0, + dma_sser1, + dma_ata, + dma_strp, + dma_ext0, + dma_ext1, + dma_ext2, + dma_ext3 +}; + +int crisv32_request_dma(unsigned int dmanr, const char * device_id, + unsigned options, unsigned bandwidth, enum dma_owner owner); +void crisv32_free_dma(unsigned int dmanr); + +/* Masks used by crisv32_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR 1 +#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) +#define DMA_INT_MEM 4 + +#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h new file mode 100644 index 000000000000..1324e505a4d8 --- /dev/null +++ b/include/asm-cris/arch-v32/elf.h @@ -0,0 +1,73 @@ +#ifndef _ASM_CRIS_ELF_H +#define _ASM_CRIS_ELF_H + +#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + ((x)->e_machine == EM_CRIS \ + && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ + || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) + +/* CRISv32 ELF register definitions. */ + +#include <asm/ptrace.h> + +/* Explicitly zero out registers to increase determinism. */ +#define ELF_PLAT_INIT(_r, load_addr) do { \ + (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ + (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ + (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ + (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ + (_r)->acr = 0; \ +} while (0) + +/* + * An executable for which elf_read_implies_exec() returns TRUE will + * have the READ_IMPLIES_EXEC personality flag set automatically. + */ +#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) + +/* + * This is basically a pt_regs with the additional definition + * of the stack pointer since it's needed in a core dump. + * pr_regs is a elf_gregset_t and should be filled according + * to the layout of user_regs_struct. + */ +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + pr_reg[0] = regs->r0; \ + pr_reg[1] = regs->r1; \ + pr_reg[2] = regs->r2; \ + pr_reg[3] = regs->r3; \ + pr_reg[4] = regs->r4; \ + pr_reg[5] = regs->r5; \ + pr_reg[6] = regs->r6; \ + pr_reg[7] = regs->r7; \ + pr_reg[8] = regs->r8; \ + pr_reg[9] = regs->r9; \ + pr_reg[10] = regs->r10; \ + pr_reg[11] = regs->r11; \ + pr_reg[12] = regs->r12; \ + pr_reg[13] = regs->r13; \ + pr_reg[14] = rdusp(); /* SP */ \ + pr_reg[15] = regs->acr; /* ACR */ \ + pr_reg[16] = 0; /* BZ */ \ + pr_reg[17] = rdvr(); /* VR */ \ + pr_reg[18] = 0; /* PID */ \ + pr_reg[19] = regs->srs; /* SRS */ \ + pr_reg[20] = 0; /* WZ */ \ + pr_reg[21] = regs->exs; /* EXS */ \ + pr_reg[22] = regs->eda; /* EDA */ \ + pr_reg[23] = regs->mof; /* MOF */ \ + pr_reg[24] = 0; /* DZ */ \ + pr_reg[25] = 0; /* EBP */ \ + pr_reg[26] = regs->erp; /* ERP */ \ + pr_reg[27] = regs->srp; /* SRP */ \ + pr_reg[28] = 0; /* NRP */ \ + pr_reg[29] = regs->ccs; /* CCS */ \ + pr_reg[30] = rdusp(); /* USP */ \ + pr_reg[31] = regs->spc; /* SPC */ \ + +#endif /* _ASM_CRIS_ELF_H */ diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile new file mode 100644 index 000000000000..c9160f9949a9 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/Makefile @@ -0,0 +1,187 @@ +# $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $ +# Makefile to generate or copy the latest register definitions +# and related datastructures and helpermacros. +# The offical place for these files is at: +RELEASE ?= r1_alfa5 +OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ + +# which is updated on each new release. +INCL_ASMFILES = +INCL_FILES = ata_defs.h +INCL_FILES += bif_core_defs.h +INCL_ASMFILES += bif_core_defs_asm.h +INCL_FILES += bif_slave_defs.h +#INCL_FILES += bif_slave_ext_defs.h +INCL_FILES += config_defs.h +INCL_ASMFILES += config_defs_asm.h +INCL_FILES += cpu_vect.h +#INCL_FILES += cris_defs.h +#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h +INCL_FILES += dma.h +INCL_FILES += dma_defs.h +INCL_FILES += eth_defs.h +INCL_FILES += extmem_defs.h +INCL_FILES += gio_defs.h +INCL_ASMFILES += gio_defs_asm.h +INCL_FILES += intr_vect.h +INCL_FILES += intr_vect_defs.h +INCL_ASMFILES += intr_vect_defs_asm.h +INCL_FILES += marb_bp_defs.h +INCL_FILES += marb_defs.h +INCL_ASMFILES += mmu_defs_asm.h +#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h +#INCL_FILES += par_defs.h # No useful content +INCL_FILES += pinmux_defs.h +INCL_FILES += reg_map.h +INCL_ASMFILES += reg_map_asm.h +INCL_FILES += reg_rdwr.h +INCL_FILES += ser_defs.h +#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h +INCL_FILES += sser_defs.h +INCL_FILES += strcop_defs.h +#INCL_FILES += strcop.h # Where is this? +INCL_FILES += strmux_defs.h +#INCL_FILES += supp_reg.h # Handcrafted instead +INCL_FILES += timer_defs.h + +REGDESC = +REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r +REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r +REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r +#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r +REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r +REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r +REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r +REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r +REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r +REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r +REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r +REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r +#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r +REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r +REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r +REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r +REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r +REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r +#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r + + +BASEDIR = /n/asic/design +DESIGNDIR = /n/asic/projects/guinness/design +RDES2C = /n/asic/bin/rdes2c +RDES2C = /n/asic/design/tools/rdesc/rdes2c +RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr +RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt + +## all - Just print help - you probably want to do 'make gen' +all: help + +# Disable implicit rule that may generate deleted files from RCS/ directory. +%.r: + +%.h: + +## help - This help +help: + @grep '^## ' Makefile + +## gen - Generate include files +gen: $(INCL_FILES) $(INCL_ASMFILES) + +ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r + $(RDES2C) $< +config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r + $(RDES2C) $< +config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r + $(RDES2C) -asm $< +# Can't generate cpu_vect.h yet +#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? +# $(RDES2INTR) $< +cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r + $(RDES2C) $< +$(BASEDIR)/core/dma/sw/dma.h: +dma.h: $(BASEDIR)/core/dma/sw/dma.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r + $(RDES2C) $< +extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r + $(RDES2C) $< +gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r + $(RDES2C) $< +intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r + $(RDES2C) $< +intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r + $(RDES2C) -asm $< +# Can't generate intr_vect.h yet +#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r +# $(RDES2INTR) $< +intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r + $(RDES2C) -asm $< +par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r + $(RDES2C) $< + +# From /n/asic/projects/guinness/design/ +reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap + $(RDES2C) -base 0xb0000000 $^ +reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap + $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ + +reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ + +ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r + $(RDES2C) $< +strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r + $(RDES2C) $< +strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r + $(RDES2C) $< +timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r + $(RDES2C) $< +usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r + $(RDES2C) $< + +## copy - Copy files from official location +copy: + @for HFILE in $(INCL_FILES); do \ + echo " $$HFILE"; \ + cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @for HFILE in $(INCL_ASMFILES); do \ + echo " $$HFILE"; \ + cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done +## ls_official - List official location +ls_official: + (cd $(OFFICIAL_INCDIR); ls -l *.h ) + +## diff_official - Diff current directory with official location +diff_official: + diff . $(OFFICIAL_INCDIR) + +## doc - Generate .axw files from register description. +doc: $(REGDESC) + for RDES in $^; do \ + $(RDES2TXT) $$RDES; \ + done + +.PHONY: axw +## %.axw - Generate the specified .axw file (doesn't work for all files +## due to inconsistent naming ir .r files. +%.axw: axw + @for RDES in $(REGDESC); do \ + if echo "$$RDES" | grep $* ; then \ + $(RDES2TXT) $$RDES; \ + fi \ + done + +.PHONY: clean +## clean - Remove .h files and .axw files. +clean: + rm -rf $(INCL_FILES) *.axw + diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h new file mode 100644 index 000000000000..866191418f9c --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h @@ -0,0 +1,222 @@ +#ifndef __ata_defs_asm_h +#define __ata_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/ata/rtl/ata_regs.r + * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp + * last modfied: Mon Apr 11 16:06:25 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r + * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ctrl0, scope ata, type rw */ +#define reg_ata_rw_ctrl0___pio_hold___lsb 0 +#define reg_ata_rw_ctrl0___pio_hold___width 6 +#define reg_ata_rw_ctrl0___pio_strb___lsb 6 +#define reg_ata_rw_ctrl0___pio_strb___width 6 +#define reg_ata_rw_ctrl0___pio_setup___lsb 12 +#define reg_ata_rw_ctrl0___pio_setup___width 6 +#define reg_ata_rw_ctrl0___dma_hold___lsb 18 +#define reg_ata_rw_ctrl0___dma_hold___width 6 +#define reg_ata_rw_ctrl0___dma_strb___lsb 24 +#define reg_ata_rw_ctrl0___dma_strb___width 6 +#define reg_ata_rw_ctrl0___rst___lsb 30 +#define reg_ata_rw_ctrl0___rst___width 1 +#define reg_ata_rw_ctrl0___rst___bit 30 +#define reg_ata_rw_ctrl0___en___lsb 31 +#define reg_ata_rw_ctrl0___en___width 1 +#define reg_ata_rw_ctrl0___en___bit 31 +#define reg_ata_rw_ctrl0_offset 12 + +/* Register rw_ctrl1, scope ata, type rw */ +#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 +#define reg_ata_rw_ctrl1___udma_tcyc___width 4 +#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 +#define reg_ata_rw_ctrl1___udma_tdvs___width 4 +#define reg_ata_rw_ctrl1_offset 16 + +/* Register rw_ctrl2, scope ata, type rw */ +#define reg_ata_rw_ctrl2___data___lsb 0 +#define reg_ata_rw_ctrl2___data___width 16 +#define reg_ata_rw_ctrl2___dma_size___lsb 19 +#define reg_ata_rw_ctrl2___dma_size___width 1 +#define reg_ata_rw_ctrl2___dma_size___bit 19 +#define reg_ata_rw_ctrl2___multi___lsb 20 +#define reg_ata_rw_ctrl2___multi___width 1 +#define reg_ata_rw_ctrl2___multi___bit 20 +#define reg_ata_rw_ctrl2___hsh___lsb 21 +#define reg_ata_rw_ctrl2___hsh___width 2 +#define reg_ata_rw_ctrl2___trf_mode___lsb 23 +#define reg_ata_rw_ctrl2___trf_mode___width 1 +#define reg_ata_rw_ctrl2___trf_mode___bit 23 +#define reg_ata_rw_ctrl2___rw___lsb 24 +#define reg_ata_rw_ctrl2___rw___width 1 +#define reg_ata_rw_ctrl2___rw___bit 24 +#define reg_ata_rw_ctrl2___addr___lsb 25 +#define reg_ata_rw_ctrl2___addr___width 3 +#define reg_ata_rw_ctrl2___cs0___lsb 28 +#define reg_ata_rw_ctrl2___cs0___width 1 +#define reg_ata_rw_ctrl2___cs0___bit 28 +#define reg_ata_rw_ctrl2___cs1___lsb 29 +#define reg_ata_rw_ctrl2___cs1___width 1 +#define reg_ata_rw_ctrl2___cs1___bit 29 +#define reg_ata_rw_ctrl2___sel___lsb 30 +#define reg_ata_rw_ctrl2___sel___width 2 +#define reg_ata_rw_ctrl2_offset 0 + +/* Register rs_stat_data, scope ata, type rs */ +#define reg_ata_rs_stat_data___data___lsb 0 +#define reg_ata_rs_stat_data___data___width 16 +#define reg_ata_rs_stat_data___dav___lsb 16 +#define reg_ata_rs_stat_data___dav___width 1 +#define reg_ata_rs_stat_data___dav___bit 16 +#define reg_ata_rs_stat_data___busy___lsb 17 +#define reg_ata_rs_stat_data___busy___width 1 +#define reg_ata_rs_stat_data___busy___bit 17 +#define reg_ata_rs_stat_data_offset 4 + +/* Register r_stat_data, scope ata, type r */ +#define reg_ata_r_stat_data___data___lsb 0 +#define reg_ata_r_stat_data___data___width 16 +#define reg_ata_r_stat_data___dav___lsb 16 +#define reg_ata_r_stat_data___dav___width 1 +#define reg_ata_r_stat_data___dav___bit 16 +#define reg_ata_r_stat_data___busy___lsb 17 +#define reg_ata_r_stat_data___busy___width 1 +#define reg_ata_r_stat_data___busy___bit 17 +#define reg_ata_r_stat_data_offset 8 + +/* Register rw_trf_cnt, scope ata, type rw */ +#define reg_ata_rw_trf_cnt___cnt___lsb 0 +#define reg_ata_rw_trf_cnt___cnt___width 17 +#define reg_ata_rw_trf_cnt_offset 20 + +/* Register r_stat_misc, scope ata, type r */ +#define reg_ata_r_stat_misc___crc___lsb 0 +#define reg_ata_r_stat_misc___crc___width 16 +#define reg_ata_r_stat_misc_offset 24 + +/* Register rw_intr_mask, scope ata, type rw */ +#define reg_ata_rw_intr_mask___bus0___lsb 0 +#define reg_ata_rw_intr_mask___bus0___width 1 +#define reg_ata_rw_intr_mask___bus0___bit 0 +#define reg_ata_rw_intr_mask___bus1___lsb 1 +#define reg_ata_rw_intr_mask___bus1___width 1 +#define reg_ata_rw_intr_mask___bus1___bit 1 +#define reg_ata_rw_intr_mask___bus2___lsb 2 +#define reg_ata_rw_intr_mask___bus2___width 1 +#define reg_ata_rw_intr_mask___bus2___bit 2 +#define reg_ata_rw_intr_mask___bus3___lsb 3 +#define reg_ata_rw_intr_mask___bus3___width 1 +#define reg_ata_rw_intr_mask___bus3___bit 3 +#define reg_ata_rw_intr_mask_offset 28 + +/* Register rw_ack_intr, scope ata, type rw */ +#define reg_ata_rw_ack_intr___bus0___lsb 0 +#define reg_ata_rw_ack_intr___bus0___width 1 +#define reg_ata_rw_ack_intr___bus0___bit 0 +#define reg_ata_rw_ack_intr___bus1___lsb 1 +#define reg_ata_rw_ack_intr___bus1___width 1 +#define reg_ata_rw_ack_intr___bus1___bit 1 +#define reg_ata_rw_ack_intr___bus2___lsb 2 +#define reg_ata_rw_ack_intr___bus2___width 1 +#define reg_ata_rw_ack_intr___bus2___bit 2 +#define reg_ata_rw_ack_intr___bus3___lsb 3 +#define reg_ata_rw_ack_intr___bus3___width 1 +#define reg_ata_rw_ack_intr___bus3___bit 3 +#define reg_ata_rw_ack_intr_offset 32 + +/* Register r_intr, scope ata, type r */ +#define reg_ata_r_intr___bus0___lsb 0 +#define reg_ata_r_intr___bus0___width 1 +#define reg_ata_r_intr___bus0___bit 0 +#define reg_ata_r_intr___bus1___lsb 1 +#define reg_ata_r_intr___bus1___width 1 +#define reg_ata_r_intr___bus1___bit 1 +#define reg_ata_r_intr___bus2___lsb 2 +#define reg_ata_r_intr___bus2___width 1 +#define reg_ata_r_intr___bus2___bit 2 +#define reg_ata_r_intr___bus3___lsb 3 +#define reg_ata_r_intr___bus3___width 1 +#define reg_ata_r_intr___bus3___bit 3 +#define reg_ata_r_intr_offset 36 + +/* Register r_masked_intr, scope ata, type r */ +#define reg_ata_r_masked_intr___bus0___lsb 0 +#define reg_ata_r_masked_intr___bus0___width 1 +#define reg_ata_r_masked_intr___bus0___bit 0 +#define reg_ata_r_masked_intr___bus1___lsb 1 +#define reg_ata_r_masked_intr___bus1___width 1 +#define reg_ata_r_masked_intr___bus1___bit 1 +#define reg_ata_r_masked_intr___bus2___lsb 2 +#define reg_ata_r_masked_intr___bus2___width 1 +#define reg_ata_r_masked_intr___bus2___bit 2 +#define reg_ata_r_masked_intr___bus3___lsb 3 +#define reg_ata_r_masked_intr___bus3___width 1 +#define reg_ata_r_masked_intr___bus3___bit 3 +#define reg_ata_r_masked_intr_offset 40 + + +/* Constants */ +#define regk_ata_active 0x00000001 +#define regk_ata_byte 0x00000001 +#define regk_ata_data 0x00000001 +#define regk_ata_dma 0x00000001 +#define regk_ata_inactive 0x00000000 +#define regk_ata_no 0x00000000 +#define regk_ata_nodata 0x00000000 +#define regk_ata_pio 0x00000000 +#define regk_ata_rd 0x00000001 +#define regk_ata_reg 0x00000000 +#define regk_ata_rw_ctrl0_default 0x00000000 +#define regk_ata_rw_ctrl2_default 0x00000000 +#define regk_ata_rw_intr_mask_default 0x00000000 +#define regk_ata_udma 0x00000002 +#define regk_ata_word 0x00000000 +#define regk_ata_wr 0x00000000 +#define regk_ata_yes 0x00000001 +#endif /* __ata_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h new file mode 100644 index 000000000000..c686cb335621 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h @@ -0,0 +1,319 @@ +#ifndef __bif_core_defs_asm_h +#define __bif_core_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp1_cfg___lw___width 6 +#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp1_cfg___ew___width 3 +#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp1_cfg___zw___width 3 +#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp1_cfg___aw___width 2 +#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp1_cfg___dw___width 2 +#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp1_cfg___ewb___width 2 +#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp1_cfg___bw___width 1 +#define reg_bif_core_rw_grp1_cfg___bw___bit 18 +#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp1_cfg___mode___width 1 +#define reg_bif_core_rw_grp1_cfg___mode___bit 21 +#define reg_bif_core_rw_grp1_cfg_offset 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp2_cfg___lw___width 6 +#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp2_cfg___ew___width 3 +#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp2_cfg___zw___width 3 +#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp2_cfg___aw___width 2 +#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp2_cfg___dw___width 2 +#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp2_cfg___ewb___width 2 +#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp2_cfg___bw___width 1 +#define reg_bif_core_rw_grp2_cfg___bw___bit 18 +#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp2_cfg___mode___width 1 +#define reg_bif_core_rw_grp2_cfg___mode___bit 21 +#define reg_bif_core_rw_grp2_cfg_offset 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp3_cfg___lw___width 6 +#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp3_cfg___ew___width 3 +#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp3_cfg___zw___width 3 +#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp3_cfg___aw___width 2 +#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp3_cfg___dw___width 2 +#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp3_cfg___ewb___width 2 +#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp3_cfg___bw___width 1 +#define reg_bif_core_rw_grp3_cfg___bw___bit 18 +#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp3_cfg___mode___width 1 +#define reg_bif_core_rw_grp3_cfg___mode___bit 21 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 +#define reg_bif_core_rw_grp3_cfg_offset 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp4_cfg___lw___width 6 +#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp4_cfg___ew___width 3 +#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp4_cfg___zw___width 3 +#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp4_cfg___aw___width 2 +#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp4_cfg___dw___width 2 +#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp4_cfg___ewb___width 2 +#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp4_cfg___bw___width 1 +#define reg_bif_core_rw_grp4_cfg___bw___bit 18 +#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp4_cfg___mode___width 1 +#define reg_bif_core_rw_grp4_cfg___mode___bit 21 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 +#define reg_bif_core_rw_grp4_cfg_offset 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_timing___cl___lsb 0 +#define reg_bif_core_rw_sdram_timing___cl___width 3 +#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 +#define reg_bif_core_rw_sdram_timing___rcd___width 3 +#define reg_bif_core_rw_sdram_timing___rp___lsb 6 +#define reg_bif_core_rw_sdram_timing___rp___width 3 +#define reg_bif_core_rw_sdram_timing___rc___lsb 9 +#define reg_bif_core_rw_sdram_timing___rc___width 2 +#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 +#define reg_bif_core_rw_sdram_timing___dpl___width 2 +#define reg_bif_core_rw_sdram_timing___pde___lsb 13 +#define reg_bif_core_rw_sdram_timing___pde___width 1 +#define reg_bif_core_rw_sdram_timing___pde___bit 13 +#define reg_bif_core_rw_sdram_timing___ref___lsb 14 +#define reg_bif_core_rw_sdram_timing___ref___width 2 +#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 +#define reg_bif_core_rw_sdram_timing___cpd___width 1 +#define reg_bif_core_rw_sdram_timing___cpd___bit 16 +#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 +#define reg_bif_core_rw_sdram_timing___sdcke___width 1 +#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 +#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 +#define reg_bif_core_rw_sdram_timing___sdclk___width 1 +#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 +#define reg_bif_core_rw_sdram_timing_offset 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 +#define reg_bif_core_rw_sdram_cmd___cmd___width 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 +#define reg_bif_core_rw_sdram_cmd_offset 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 +#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_rs_sdram_ref_stat_offset 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_r_sdram_ref_stat___ok___width 1 +#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_r_sdram_ref_stat_offset 36 + + +/* Constants */ +#define regk_bif_core_bank2 0x00000000 +#define regk_bif_core_bank4 0x00000001 +#define regk_bif_core_bit10 0x0000000a +#define regk_bif_core_bit11 0x0000000b +#define regk_bif_core_bit12 0x0000000c +#define regk_bif_core_bit13 0x0000000d +#define regk_bif_core_bit14 0x0000000e +#define regk_bif_core_bit15 0x0000000f +#define regk_bif_core_bit16 0x00000010 +#define regk_bif_core_bit17 0x00000011 +#define regk_bif_core_bit18 0x00000012 +#define regk_bif_core_bit19 0x00000013 +#define regk_bif_core_bit20 0x00000014 +#define regk_bif_core_bit21 0x00000015 +#define regk_bif_core_bit22 0x00000016 +#define regk_bif_core_bit23 0x00000017 +#define regk_bif_core_bit24 0x00000018 +#define regk_bif_core_bit25 0x00000019 +#define regk_bif_core_bit26 0x0000001a +#define regk_bif_core_bit27 0x0000001b +#define regk_bif_core_bit28 0x0000001c +#define regk_bif_core_bit29 0x0000001d +#define regk_bif_core_bit9 0x00000009 +#define regk_bif_core_bw16 0x00000001 +#define regk_bif_core_bw32 0x00000000 +#define regk_bif_core_bwe 0x00000000 +#define regk_bif_core_cwe 0x00000001 +#define regk_bif_core_e15us 0x00000001 +#define regk_bif_core_e7800ns 0x00000002 +#define regk_bif_core_grp0 0x00000000 +#define regk_bif_core_grp1 0x00000001 +#define regk_bif_core_mrs 0x00000003 +#define regk_bif_core_no 0x00000000 +#define regk_bif_core_none 0x00000000 +#define regk_bif_core_nop 0x00000000 +#define regk_bif_core_off 0x00000000 +#define regk_bif_core_pre 0x00000002 +#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rd 0x00000002 +#define regk_bif_core_ref 0x00000001 +#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rw_grp1_cfg_default 0x000006cf +#define regk_bif_core_rw_grp2_cfg_default 0x000006cf +#define regk_bif_core_rw_grp3_cfg_default 0x000006cf +#define regk_bif_core_rw_grp4_cfg_default 0x000006cf +#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 +#define regk_bif_core_slf 0x00000004 +#define regk_bif_core_wr 0x00000001 +#define regk_bif_core_yes 0x00000001 +#endif /* __bif_core_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h new file mode 100644 index 000000000000..71532aa18168 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h @@ -0,0 +1,495 @@ +#ifndef __bif_dma_defs_asm_h +#define __bif_dma_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch0_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch0_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 +#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 +#define reg_bif_dma_rw_ch0_ctrl_offset 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch0_addr___addr___width 32 +#define reg_bif_dma_rw_ch0_addr_offset 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_start___run___lsb 0 +#define reg_bif_dma_rw_ch0_start___run___width 1 +#define reg_bif_dma_rw_ch0_start___run___bit 0 +#define reg_bif_dma_rw_ch0_start_offset 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch0_cnt_offset 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch0_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch0_stat___cnt___width 16 +#define reg_bif_dma_r_ch0_stat___run___lsb 31 +#define reg_bif_dma_r_ch0_stat___run___width 1 +#define reg_bif_dma_r_ch0_stat___run___bit 31 +#define reg_bif_dma_r_ch0_stat_offset 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch1_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch1_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 +#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch1_ctrl_offset 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch1_addr___addr___width 32 +#define reg_bif_dma_rw_ch1_addr_offset 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_start___run___lsb 0 +#define reg_bif_dma_rw_ch1_start___run___width 1 +#define reg_bif_dma_rw_ch1_start___run___bit 0 +#define reg_bif_dma_rw_ch1_start_offset 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch1_cnt_offset 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch1_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch1_stat___cnt___width 16 +#define reg_bif_dma_r_ch1_stat___run___lsb 31 +#define reg_bif_dma_r_ch1_stat___run___width 1 +#define reg_bif_dma_r_ch1_stat___run___bit 31 +#define reg_bif_dma_r_ch1_stat_offset 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch2_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch2_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 +#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 +#define reg_bif_dma_rw_ch2_ctrl_offset 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch2_addr___addr___width 32 +#define reg_bif_dma_rw_ch2_addr_offset 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_start___run___lsb 0 +#define reg_bif_dma_rw_ch2_start___run___width 1 +#define reg_bif_dma_rw_ch2_start___run___bit 0 +#define reg_bif_dma_rw_ch2_start_offset 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch2_cnt_offset 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch2_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch2_stat___cnt___width 16 +#define reg_bif_dma_r_ch2_stat___run___lsb 31 +#define reg_bif_dma_r_ch2_stat___run___width 1 +#define reg_bif_dma_r_ch2_stat___run___bit 31 +#define reg_bif_dma_r_ch2_stat_offset 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch3_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch3_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 +#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch3_ctrl_offset 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch3_addr___addr___width 32 +#define reg_bif_dma_rw_ch3_addr_offset 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_start___run___lsb 0 +#define reg_bif_dma_rw_ch3_start___run___width 1 +#define reg_bif_dma_rw_ch3_start___run___bit 0 +#define reg_bif_dma_rw_ch3_start_offset 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch3_cnt_offset 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch3_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch3_stat___cnt___width 16 +#define reg_bif_dma_r_ch3_stat___run___lsb 31 +#define reg_bif_dma_r_ch3_stat___run___width 1 +#define reg_bif_dma_r_ch3_stat___run___bit 31 +#define reg_bif_dma_r_ch3_stat_offset 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 +#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 +#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 +#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 +#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 +#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 +#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 +#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 +#define reg_bif_dma_rw_intr_mask_offset 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 +#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 +#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 +#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 +#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 +#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 +#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 +#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 +#define reg_bif_dma_rw_ack_intr_offset 132 + +/* Register r_intr, scope bif_dma, type r */ +#define reg_bif_dma_r_intr___ext_dma0___lsb 0 +#define reg_bif_dma_r_intr___ext_dma0___width 1 +#define reg_bif_dma_r_intr___ext_dma0___bit 0 +#define reg_bif_dma_r_intr___ext_dma1___lsb 1 +#define reg_bif_dma_r_intr___ext_dma1___width 1 +#define reg_bif_dma_r_intr___ext_dma1___bit 1 +#define reg_bif_dma_r_intr___ext_dma2___lsb 2 +#define reg_bif_dma_r_intr___ext_dma2___width 1 +#define reg_bif_dma_r_intr___ext_dma2___bit 2 +#define reg_bif_dma_r_intr___ext_dma3___lsb 3 +#define reg_bif_dma_r_intr___ext_dma3___width 1 +#define reg_bif_dma_r_intr___ext_dma3___bit 3 +#define reg_bif_dma_r_intr_offset 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 +#define reg_bif_dma_r_masked_intr___ext_dma0___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 +#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 +#define reg_bif_dma_r_masked_intr___ext_dma1___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 +#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 +#define reg_bif_dma_r_masked_intr___ext_dma2___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 +#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 +#define reg_bif_dma_r_masked_intr___ext_dma3___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 +#define reg_bif_dma_r_masked_intr_offset 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin0_cfg_offset 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin1_cfg_offset 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin2_cfg_offset 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin3_cfg_offset 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin4_cfg_offset 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin5_cfg_offset 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin6_cfg_offset 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin7_cfg_offset 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_pin_stat___pin0___lsb 0 +#define reg_bif_dma_r_pin_stat___pin0___width 1 +#define reg_bif_dma_r_pin_stat___pin0___bit 0 +#define reg_bif_dma_r_pin_stat___pin1___lsb 1 +#define reg_bif_dma_r_pin_stat___pin1___width 1 +#define reg_bif_dma_r_pin_stat___pin1___bit 1 +#define reg_bif_dma_r_pin_stat___pin2___lsb 2 +#define reg_bif_dma_r_pin_stat___pin2___width 1 +#define reg_bif_dma_r_pin_stat___pin2___bit 2 +#define reg_bif_dma_r_pin_stat___pin3___lsb 3 +#define reg_bif_dma_r_pin_stat___pin3___width 1 +#define reg_bif_dma_r_pin_stat___pin3___bit 3 +#define reg_bif_dma_r_pin_stat___pin4___lsb 4 +#define reg_bif_dma_r_pin_stat___pin4___width 1 +#define reg_bif_dma_r_pin_stat___pin4___bit 4 +#define reg_bif_dma_r_pin_stat___pin5___lsb 5 +#define reg_bif_dma_r_pin_stat___pin5___width 1 +#define reg_bif_dma_r_pin_stat___pin5___bit 5 +#define reg_bif_dma_r_pin_stat___pin6___lsb 6 +#define reg_bif_dma_r_pin_stat___pin6___width 1 +#define reg_bif_dma_r_pin_stat___pin6___bit 6 +#define reg_bif_dma_r_pin_stat___pin7___lsb 7 +#define reg_bif_dma_r_pin_stat___pin7___width 1 +#define reg_bif_dma_r_pin_stat___pin7___bit 7 +#define reg_bif_dma_r_pin_stat_offset 192 + + +/* Constants */ +#define regk_bif_dma_as_master 0x00000001 +#define regk_bif_dma_as_slave 0x00000001 +#define regk_bif_dma_burst1 0x00000000 +#define regk_bif_dma_burst8 0x00000001 +#define regk_bif_dma_bw16 0x00000001 +#define regk_bif_dma_bw32 0x00000002 +#define regk_bif_dma_bw8 0x00000000 +#define regk_bif_dma_dack 0x00000006 +#define regk_bif_dma_dack_inv 0x00000007 +#define regk_bif_dma_force 0x00000001 +#define regk_bif_dma_hi 0x00000003 +#define regk_bif_dma_inv 0x00000003 +#define regk_bif_dma_lo 0x00000002 +#define regk_bif_dma_master 0x00000001 +#define regk_bif_dma_no 0x00000000 +#define regk_bif_dma_norm 0x00000002 +#define regk_bif_dma_off 0x00000000 +#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch0_start_default 0x00000000 +#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch1_start_default 0x00000000 +#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch2_start_default 0x00000000 +#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch3_start_default 0x00000000 +#define regk_bif_dma_rw_intr_mask_default 0x00000000 +#define regk_bif_dma_rw_pin0_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin1_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin2_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin3_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin4_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin5_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin6_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin7_cfg_default 0x00000000 +#define regk_bif_dma_slave 0x00000002 +#define regk_bif_dma_sreq 0x00000006 +#define regk_bif_dma_sreq_inv 0x00000007 +#define regk_bif_dma_tc 0x00000004 +#define regk_bif_dma_tc_inv 0x00000005 +#define regk_bif_dma_yes 0x00000001 +#endif /* __bif_dma_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h new file mode 100644 index 000000000000..031f33a365bb --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_asm_h +#define __bif_slave_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 +#define reg_bif_slave_rw_slave_cfg___slave_id___width 3 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 +#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 +#define reg_bif_slave_rw_slave_cfg___loopback___width 1 +#define reg_bif_slave_rw_slave_cfg___loopback___bit 5 +#define reg_bif_slave_rw_slave_cfg___dis___lsb 6 +#define reg_bif_slave_rw_slave_cfg___dis___width 1 +#define reg_bif_slave_rw_slave_cfg___dis___bit 6 +#define reg_bif_slave_rw_slave_cfg_offset 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 +#define reg_bif_slave_r_slave_mode___ch0_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 +#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 +#define reg_bif_slave_r_slave_mode___ch1_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 +#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 +#define reg_bif_slave_r_slave_mode___ch2_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 +#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 +#define reg_bif_slave_r_slave_mode___ch3_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 +#define reg_bif_slave_r_slave_mode_offset 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch0_cfg_offset 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch1_cfg_offset 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch2_cfg_offset 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch3_cfg_offset 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 +#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 +#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 +#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 +#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 +#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 +#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 +#define reg_bif_slave_rw_arb_cfg___release___lsb 7 +#define reg_bif_slave_rw_arb_cfg___release___width 2 +#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 +#define reg_bif_slave_rw_arb_cfg___acquire___width 1 +#define reg_bif_slave_rw_arb_cfg___acquire___bit 9 +#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 +#define reg_bif_slave_rw_arb_cfg___settle_time___width 2 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 +#define reg_bif_slave_rw_arb_cfg_offset 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +#define reg_bif_slave_r_arb_stat___init_mode___lsb 0 +#define reg_bif_slave_r_arb_stat___init_mode___width 1 +#define reg_bif_slave_r_arb_stat___init_mode___bit 0 +#define reg_bif_slave_r_arb_stat___mode___lsb 1 +#define reg_bif_slave_r_arb_stat___mode___width 1 +#define reg_bif_slave_r_arb_stat___mode___bit 1 +#define reg_bif_slave_r_arb_stat___brin___lsb 2 +#define reg_bif_slave_r_arb_stat___brin___width 1 +#define reg_bif_slave_r_arb_stat___brin___bit 2 +#define reg_bif_slave_r_arb_stat___brout___lsb 3 +#define reg_bif_slave_r_arb_stat___brout___width 1 +#define reg_bif_slave_r_arb_stat___brout___bit 3 +#define reg_bif_slave_r_arb_stat___bg___lsb 4 +#define reg_bif_slave_r_arb_stat___bg___width 1 +#define reg_bif_slave_r_arb_stat___bg___bit 4 +#define reg_bif_slave_r_arb_stat_offset 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 +#define reg_bif_slave_rw_intr_mask___bus_release___width 1 +#define reg_bif_slave_rw_intr_mask___bus_release___bit 0 +#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 +#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 +#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 +#define reg_bif_slave_rw_intr_mask_offset 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 +#define reg_bif_slave_rw_ack_intr___bus_release___width 1 +#define reg_bif_slave_rw_ack_intr___bus_release___bit 0 +#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 +#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 +#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 +#define reg_bif_slave_rw_ack_intr_offset 68 + +/* Register r_intr, scope bif_slave, type r */ +#define reg_bif_slave_r_intr___bus_release___lsb 0 +#define reg_bif_slave_r_intr___bus_release___width 1 +#define reg_bif_slave_r_intr___bus_release___bit 0 +#define reg_bif_slave_r_intr___bus_acquire___lsb 1 +#define reg_bif_slave_r_intr___bus_acquire___width 1 +#define reg_bif_slave_r_intr___bus_acquire___bit 1 +#define reg_bif_slave_r_intr_offset 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +#define reg_bif_slave_r_masked_intr___bus_release___lsb 0 +#define reg_bif_slave_r_masked_intr___bus_release___width 1 +#define reg_bif_slave_r_masked_intr___bus_release___bit 0 +#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 +#define reg_bif_slave_r_masked_intr___bus_acquire___width 1 +#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 +#define reg_bif_slave_r_masked_intr_offset 76 + + +/* Constants */ +#define regk_bif_slave_active_hi 0x00000003 +#define regk_bif_slave_active_lo 0x00000002 +#define regk_bif_slave_addr 0x00000000 +#define regk_bif_slave_always 0x00000001 +#define regk_bif_slave_at_idle 0x00000002 +#define regk_bif_slave_burst_end 0x00000003 +#define regk_bif_slave_dma 0x00000001 +#define regk_bif_slave_hi 0x00000003 +#define regk_bif_slave_inv 0x00000001 +#define regk_bif_slave_lo 0x00000002 +#define regk_bif_slave_local 0x00000001 +#define regk_bif_slave_master 0x00000000 +#define regk_bif_slave_mode_reg 0x00000001 +#define regk_bif_slave_no 0x00000000 +#define regk_bif_slave_norm 0x00000000 +#define regk_bif_slave_on_access 0x00000000 +#define regk_bif_slave_rw_arb_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch0_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch1_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch2_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch3_cfg_default 0x00000000 +#define regk_bif_slave_rw_intr_mask_default 0x00000000 +#define regk_bif_slave_rw_slave_cfg_default 0x00000000 +#define regk_bif_slave_shared 0x00000000 +#define regk_bif_slave_slave 0x00000001 +#define regk_bif_slave_t0ns 0x00000003 +#define regk_bif_slave_t10ns 0x00000002 +#define regk_bif_slave_t20ns 0x00000003 +#define regk_bif_slave_t30ns 0x00000002 +#define regk_bif_slave_t40ns 0x00000001 +#define regk_bif_slave_t50ns 0x00000000 +#define regk_bif_slave_yes 0x00000001 +#define regk_bif_slave_z 0x00000004 +#endif /* __bif_slave_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h new file mode 100644 index 000000000000..e98476332e1f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h @@ -0,0 +1,131 @@ +#ifndef __config_defs_asm_h +#define __config_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r + * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope config, type r */ +#define reg_config_r_bootsel___boot_mode___lsb 0 +#define reg_config_r_bootsel___boot_mode___width 3 +#define reg_config_r_bootsel___full_duplex___lsb 3 +#define reg_config_r_bootsel___full_duplex___width 1 +#define reg_config_r_bootsel___full_duplex___bit 3 +#define reg_config_r_bootsel___user___lsb 4 +#define reg_config_r_bootsel___user___width 1 +#define reg_config_r_bootsel___user___bit 4 +#define reg_config_r_bootsel___pll___lsb 5 +#define reg_config_r_bootsel___pll___width 1 +#define reg_config_r_bootsel___pll___bit 5 +#define reg_config_r_bootsel___flash_bw___lsb 6 +#define reg_config_r_bootsel___flash_bw___width 1 +#define reg_config_r_bootsel___flash_bw___bit 6 +#define reg_config_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +#define reg_config_rw_clk_ctrl___pll___lsb 0 +#define reg_config_rw_clk_ctrl___pll___width 1 +#define reg_config_rw_clk_ctrl___pll___bit 0 +#define reg_config_rw_clk_ctrl___cpu___lsb 1 +#define reg_config_rw_clk_ctrl___cpu___width 1 +#define reg_config_rw_clk_ctrl___cpu___bit 1 +#define reg_config_rw_clk_ctrl___iop___lsb 2 +#define reg_config_rw_clk_ctrl___iop___width 1 +#define reg_config_rw_clk_ctrl___iop___bit 2 +#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 +#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 +#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 +#define reg_config_rw_clk_ctrl___dma23___lsb 4 +#define reg_config_rw_clk_ctrl___dma23___width 1 +#define reg_config_rw_clk_ctrl___dma23___bit 4 +#define reg_config_rw_clk_ctrl___dma45___lsb 5 +#define reg_config_rw_clk_ctrl___dma45___width 1 +#define reg_config_rw_clk_ctrl___dma45___bit 5 +#define reg_config_rw_clk_ctrl___dma67___lsb 6 +#define reg_config_rw_clk_ctrl___dma67___width 1 +#define reg_config_rw_clk_ctrl___dma67___bit 6 +#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 +#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 +#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 +#define reg_config_rw_clk_ctrl___bif___lsb 8 +#define reg_config_rw_clk_ctrl___bif___width 1 +#define reg_config_rw_clk_ctrl___bif___bit 8 +#define reg_config_rw_clk_ctrl___fix_io___lsb 9 +#define reg_config_rw_clk_ctrl___fix_io___width 1 +#define reg_config_rw_clk_ctrl___fix_io___bit 9 +#define reg_config_rw_clk_ctrl_offset 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 +#define reg_config_rw_pad_ctrl___usb_susp___width 1 +#define reg_config_rw_pad_ctrl___usb_susp___bit 0 +#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 +#define reg_config_rw_pad_ctrl___phyrst_n___width 1 +#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 +#define reg_config_rw_pad_ctrl_offset 8 + + +/* Constants */ +#define regk_config_bw16 0x00000000 +#define regk_config_bw32 0x00000001 +#define regk_config_master 0x00000005 +#define regk_config_nand 0x00000003 +#define regk_config_net_rx 0x00000001 +#define regk_config_net_tx_rx 0x00000002 +#define regk_config_no 0x00000000 +#define regk_config_none 0x00000007 +#define regk_config_nor 0x00000000 +#define regk_config_rw_clk_ctrl_default 0x00000002 +#define regk_config_rw_pad_ctrl_default 0x00000000 +#define regk_config_ser 0x00000004 +#define regk_config_slave 0x00000006 +#define regk_config_yes 0x00000001 +#endif /* __config_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h new file mode 100644 index 000000000000..8370aee8a14a --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/crisp/doc/cpu_vect.r +version . */ + +#ifndef _______INST_CRISP_DOC_CPU_VECT_R +#define _______INST_CRISP_DOC_CPU_VECT_R +#define NMI_INTR_VECT 0x00 +#define RESERVED_1_INTR_VECT 0x01 +#define RESERVED_2_INTR_VECT 0x02 +#define SINGLE_STEP_INTR_VECT 0x03 +#define INSTR_TLB_REFILL_INTR_VECT 0x04 +#define INSTR_TLB_INV_INTR_VECT 0x05 +#define INSTR_TLB_ACC_INTR_VECT 0x06 +#define TLB_EX_INTR_VECT 0x07 +#define DATA_TLB_REFILL_INTR_VECT 0x08 +#define DATA_TLB_INV_INTR_VECT 0x09 +#define DATA_TLB_ACC_INTR_VECT 0x0a +#define DATA_TLB_WE_INTR_VECT 0x0b +#define HW_BP_INTR_VECT 0x0c +#define RESERVED_D_INTR_VECT 0x0d +#define RESERVED_E_INTR_VECT 0x0e +#define RESERVED_F_INTR_VECT 0x0f +#define BREAK_0_INTR_VECT 0x10 +#define BREAK_1_INTR_VECT 0x11 +#define BREAK_2_INTR_VECT 0x12 +#define BREAK_3_INTR_VECT 0x13 +#define BREAK_4_INTR_VECT 0x14 +#define BREAK_5_INTR_VECT 0x15 +#define BREAK_6_INTR_VECT 0x16 +#define BREAK_7_INTR_VECT 0x17 +#define BREAK_8_INTR_VECT 0x18 +#define BREAK_9_INTR_VECT 0x19 +#define BREAK_10_INTR_VECT 0x1a +#define BREAK_11_INTR_VECT 0x1b +#define BREAK_12_INTR_VECT 0x1c +#define BREAK_13_INTR_VECT 0x1d +#define BREAK_14_INTR_VECT 0x1e +#define BREAK_15_INTR_VECT 0x1f +#define MULTIPLE_INTR_VECT 0x30 + +#endif diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h new file mode 100644 index 000000000000..7f768db272e2 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h @@ -0,0 +1,114 @@ +#ifndef __cris_defs_asm_h +#define __cris_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/crisp/doc/cris.r + * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp + * last modfied: Mon Apr 11 16:06:39 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r + * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gc_cfg, scope cris, type rw */ +#define reg_cris_rw_gc_cfg___ic___lsb 0 +#define reg_cris_rw_gc_cfg___ic___width 1 +#define reg_cris_rw_gc_cfg___ic___bit 0 +#define reg_cris_rw_gc_cfg___dc___lsb 1 +#define reg_cris_rw_gc_cfg___dc___width 1 +#define reg_cris_rw_gc_cfg___dc___bit 1 +#define reg_cris_rw_gc_cfg___im___lsb 2 +#define reg_cris_rw_gc_cfg___im___width 1 +#define reg_cris_rw_gc_cfg___im___bit 2 +#define reg_cris_rw_gc_cfg___dm___lsb 3 +#define reg_cris_rw_gc_cfg___dm___width 1 +#define reg_cris_rw_gc_cfg___dm___bit 3 +#define reg_cris_rw_gc_cfg___gb___lsb 4 +#define reg_cris_rw_gc_cfg___gb___width 1 +#define reg_cris_rw_gc_cfg___gb___bit 4 +#define reg_cris_rw_gc_cfg___gk___lsb 5 +#define reg_cris_rw_gc_cfg___gk___width 1 +#define reg_cris_rw_gc_cfg___gk___bit 5 +#define reg_cris_rw_gc_cfg___gp___lsb 6 +#define reg_cris_rw_gc_cfg___gp___width 1 +#define reg_cris_rw_gc_cfg___gp___bit 6 +#define reg_cris_rw_gc_cfg_offset 0 + +/* Register rw_gc_ccs, scope cris, type rw */ +#define reg_cris_rw_gc_ccs_offset 4 + +/* Register rw_gc_srs, scope cris, type rw */ +#define reg_cris_rw_gc_srs___srs___lsb 0 +#define reg_cris_rw_gc_srs___srs___width 8 +#define reg_cris_rw_gc_srs_offset 8 + +/* Register rw_gc_nrp, scope cris, type rw */ +#define reg_cris_rw_gc_nrp_offset 12 + +/* Register rw_gc_exs, scope cris, type rw */ +#define reg_cris_rw_gc_exs_offset 16 + +/* Register rw_gc_eda, scope cris, type rw */ +#define reg_cris_rw_gc_eda_offset 20 + +/* Register rw_gc_r0, scope cris, type rw */ +#define reg_cris_rw_gc_r0_offset 32 + +/* Register rw_gc_r1, scope cris, type rw */ +#define reg_cris_rw_gc_r1_offset 36 + +/* Register rw_gc_r2, scope cris, type rw */ +#define reg_cris_rw_gc_r2_offset 40 + +/* Register rw_gc_r3, scope cris, type rw */ +#define reg_cris_rw_gc_r3_offset 44 + + +/* Constants */ +#define regk_cris_no 0x00000000 +#define regk_cris_rw_gc_cfg_default 0x00000000 +#define regk_cris_yes 0x00000001 +#endif /* __cris_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h new file mode 100644 index 000000000000..7d3689a6f80d --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h @@ -0,0 +1,10 @@ +#define RW_GC_CFG 0 +#define RW_GC_CCS 1 +#define RW_GC_SRS 2 +#define RW_GC_NRP 3 +#define RW_GC_EXS 4 +#define RW_GC_EDA 5 +#define RW_GC_R0 8 +#define RW_GC_R1 9 +#define RW_GC_R2 10 +#define RW_GC_R3 11 diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h new file mode 100644 index 000000000000..0cb71bc127ae --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h @@ -0,0 +1,368 @@ +#ifndef __dma_defs_asm_h +#define __dma_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp + * last modfied: Mon Apr 11 16:06:51 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_data, scope dma, type rw */ +#define reg_dma_rw_data_offset 0 + +/* Register rw_data_next, scope dma, type rw */ +#define reg_dma_rw_data_next_offset 4 + +/* Register rw_data_buf, scope dma, type rw */ +#define reg_dma_rw_data_buf_offset 8 + +/* Register rw_data_ctrl, scope dma, type rw */ +#define reg_dma_rw_data_ctrl___eol___lsb 0 +#define reg_dma_rw_data_ctrl___eol___width 1 +#define reg_dma_rw_data_ctrl___eol___bit 0 +#define reg_dma_rw_data_ctrl___out_eop___lsb 3 +#define reg_dma_rw_data_ctrl___out_eop___width 1 +#define reg_dma_rw_data_ctrl___out_eop___bit 3 +#define reg_dma_rw_data_ctrl___intr___lsb 4 +#define reg_dma_rw_data_ctrl___intr___width 1 +#define reg_dma_rw_data_ctrl___intr___bit 4 +#define reg_dma_rw_data_ctrl___wait___lsb 5 +#define reg_dma_rw_data_ctrl___wait___width 1 +#define reg_dma_rw_data_ctrl___wait___bit 5 +#define reg_dma_rw_data_ctrl_offset 12 + +/* Register rw_data_stat, scope dma, type rw */ +#define reg_dma_rw_data_stat___in_eop___lsb 3 +#define reg_dma_rw_data_stat___in_eop___width 1 +#define reg_dma_rw_data_stat___in_eop___bit 3 +#define reg_dma_rw_data_stat_offset 16 + +/* Register rw_data_md, scope dma, type rw */ +#define reg_dma_rw_data_md___md___lsb 0 +#define reg_dma_rw_data_md___md___width 16 +#define reg_dma_rw_data_md_offset 20 + +/* Register rw_data_md_s, scope dma, type rw */ +#define reg_dma_rw_data_md_s___md_s___lsb 0 +#define reg_dma_rw_data_md_s___md_s___width 16 +#define reg_dma_rw_data_md_s_offset 24 + +/* Register rw_data_after, scope dma, type rw */ +#define reg_dma_rw_data_after_offset 28 + +/* Register rw_ctxt, scope dma, type rw */ +#define reg_dma_rw_ctxt_offset 32 + +/* Register rw_ctxt_next, scope dma, type rw */ +#define reg_dma_rw_ctxt_next_offset 36 + +/* Register rw_ctxt_ctrl, scope dma, type rw */ +#define reg_dma_rw_ctxt_ctrl___eol___lsb 0 +#define reg_dma_rw_ctxt_ctrl___eol___width 1 +#define reg_dma_rw_ctxt_ctrl___eol___bit 0 +#define reg_dma_rw_ctxt_ctrl___intr___lsb 4 +#define reg_dma_rw_ctxt_ctrl___intr___width 1 +#define reg_dma_rw_ctxt_ctrl___intr___bit 4 +#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 +#define reg_dma_rw_ctxt_ctrl___store_mode___width 1 +#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 +#define reg_dma_rw_ctxt_ctrl___en___lsb 7 +#define reg_dma_rw_ctxt_ctrl___en___width 1 +#define reg_dma_rw_ctxt_ctrl___en___bit 7 +#define reg_dma_rw_ctxt_ctrl_offset 40 + +/* Register rw_ctxt_stat, scope dma, type rw */ +#define reg_dma_rw_ctxt_stat___dis___lsb 7 +#define reg_dma_rw_ctxt_stat___dis___width 1 +#define reg_dma_rw_ctxt_stat___dis___bit 7 +#define reg_dma_rw_ctxt_stat_offset 44 + +/* Register rw_ctxt_md0, scope dma, type rw */ +#define reg_dma_rw_ctxt_md0___md0___lsb 0 +#define reg_dma_rw_ctxt_md0___md0___width 16 +#define reg_dma_rw_ctxt_md0_offset 48 + +/* Register rw_ctxt_md0_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 +#define reg_dma_rw_ctxt_md0_s___md0_s___width 16 +#define reg_dma_rw_ctxt_md0_s_offset 52 + +/* Register rw_ctxt_md1, scope dma, type rw */ +#define reg_dma_rw_ctxt_md1_offset 56 + +/* Register rw_ctxt_md1_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md1_s_offset 60 + +/* Register rw_ctxt_md2, scope dma, type rw */ +#define reg_dma_rw_ctxt_md2_offset 64 + +/* Register rw_ctxt_md2_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md2_s_offset 68 + +/* Register rw_ctxt_md3, scope dma, type rw */ +#define reg_dma_rw_ctxt_md3_offset 72 + +/* Register rw_ctxt_md3_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md3_s_offset 76 + +/* Register rw_ctxt_md4, scope dma, type rw */ +#define reg_dma_rw_ctxt_md4_offset 80 + +/* Register rw_ctxt_md4_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md4_s_offset 84 + +/* Register rw_saved_data, scope dma, type rw */ +#define reg_dma_rw_saved_data_offset 88 + +/* Register rw_saved_data_buf, scope dma, type rw */ +#define reg_dma_rw_saved_data_buf_offset 92 + +/* Register rw_group, scope dma, type rw */ +#define reg_dma_rw_group_offset 96 + +/* Register rw_group_next, scope dma, type rw */ +#define reg_dma_rw_group_next_offset 100 + +/* Register rw_group_ctrl, scope dma, type rw */ +#define reg_dma_rw_group_ctrl___eol___lsb 0 +#define reg_dma_rw_group_ctrl___eol___width 1 +#define reg_dma_rw_group_ctrl___eol___bit 0 +#define reg_dma_rw_group_ctrl___tol___lsb 1 +#define reg_dma_rw_group_ctrl___tol___width 1 +#define reg_dma_rw_group_ctrl___tol___bit 1 +#define reg_dma_rw_group_ctrl___bol___lsb 2 +#define reg_dma_rw_group_ctrl___bol___width 1 +#define reg_dma_rw_group_ctrl___bol___bit 2 +#define reg_dma_rw_group_ctrl___intr___lsb 4 +#define reg_dma_rw_group_ctrl___intr___width 1 +#define reg_dma_rw_group_ctrl___intr___bit 4 +#define reg_dma_rw_group_ctrl___en___lsb 7 +#define reg_dma_rw_group_ctrl___en___width 1 +#define reg_dma_rw_group_ctrl___en___bit 7 +#define reg_dma_rw_group_ctrl_offset 104 + +/* Register rw_group_stat, scope dma, type rw */ +#define reg_dma_rw_group_stat___dis___lsb 7 +#define reg_dma_rw_group_stat___dis___width 1 +#define reg_dma_rw_group_stat___dis___bit 7 +#define reg_dma_rw_group_stat_offset 108 + +/* Register rw_group_md, scope dma, type rw */ +#define reg_dma_rw_group_md___md___lsb 0 +#define reg_dma_rw_group_md___md___width 16 +#define reg_dma_rw_group_md_offset 112 + +/* Register rw_group_md_s, scope dma, type rw */ +#define reg_dma_rw_group_md_s___md_s___lsb 0 +#define reg_dma_rw_group_md_s___md_s___width 16 +#define reg_dma_rw_group_md_s_offset 116 + +/* Register rw_group_up, scope dma, type rw */ +#define reg_dma_rw_group_up_offset 120 + +/* Register rw_group_down, scope dma, type rw */ +#define reg_dma_rw_group_down_offset 124 + +/* Register rw_cmd, scope dma, type rw */ +#define reg_dma_rw_cmd___cont_data___lsb 0 +#define reg_dma_rw_cmd___cont_data___width 1 +#define reg_dma_rw_cmd___cont_data___bit 0 +#define reg_dma_rw_cmd_offset 128 + +/* Register rw_cfg, scope dma, type rw */ +#define reg_dma_rw_cfg___en___lsb 0 +#define reg_dma_rw_cfg___en___width 1 +#define reg_dma_rw_cfg___en___bit 0 +#define reg_dma_rw_cfg___stop___lsb 1 +#define reg_dma_rw_cfg___stop___width 1 +#define reg_dma_rw_cfg___stop___bit 1 +#define reg_dma_rw_cfg_offset 132 + +/* Register rw_stat, scope dma, type rw */ +#define reg_dma_rw_stat___mode___lsb 0 +#define reg_dma_rw_stat___mode___width 5 +#define reg_dma_rw_stat___list_state___lsb 5 +#define reg_dma_rw_stat___list_state___width 3 +#define reg_dma_rw_stat___stream_cmd_src___lsb 8 +#define reg_dma_rw_stat___stream_cmd_src___width 8 +#define reg_dma_rw_stat___buf___lsb 24 +#define reg_dma_rw_stat___buf___width 8 +#define reg_dma_rw_stat_offset 136 + +/* Register rw_intr_mask, scope dma, type rw */ +#define reg_dma_rw_intr_mask___group___lsb 0 +#define reg_dma_rw_intr_mask___group___width 1 +#define reg_dma_rw_intr_mask___group___bit 0 +#define reg_dma_rw_intr_mask___ctxt___lsb 1 +#define reg_dma_rw_intr_mask___ctxt___width 1 +#define reg_dma_rw_intr_mask___ctxt___bit 1 +#define reg_dma_rw_intr_mask___data___lsb 2 +#define reg_dma_rw_intr_mask___data___width 1 +#define reg_dma_rw_intr_mask___data___bit 2 +#define reg_dma_rw_intr_mask___in_eop___lsb 3 +#define reg_dma_rw_intr_mask___in_eop___width 1 +#define reg_dma_rw_intr_mask___in_eop___bit 3 +#define reg_dma_rw_intr_mask___stream_cmd___lsb 4 +#define reg_dma_rw_intr_mask___stream_cmd___width 1 +#define reg_dma_rw_intr_mask___stream_cmd___bit 4 +#define reg_dma_rw_intr_mask_offset 140 + +/* Register rw_ack_intr, scope dma, type rw */ +#define reg_dma_rw_ack_intr___group___lsb 0 +#define reg_dma_rw_ack_intr___group___width 1 +#define reg_dma_rw_ack_intr___group___bit 0 +#define reg_dma_rw_ack_intr___ctxt___lsb 1 +#define reg_dma_rw_ack_intr___ctxt___width 1 +#define reg_dma_rw_ack_intr___ctxt___bit 1 +#define reg_dma_rw_ack_intr___data___lsb 2 +#define reg_dma_rw_ack_intr___data___width 1 +#define reg_dma_rw_ack_intr___data___bit 2 +#define reg_dma_rw_ack_intr___in_eop___lsb 3 +#define reg_dma_rw_ack_intr___in_eop___width 1 +#define reg_dma_rw_ack_intr___in_eop___bit 3 +#define reg_dma_rw_ack_intr___stream_cmd___lsb 4 +#define reg_dma_rw_ack_intr___stream_cmd___width 1 +#define reg_dma_rw_ack_intr___stream_cmd___bit 4 +#define reg_dma_rw_ack_intr_offset 144 + +/* Register r_intr, scope dma, type r */ +#define reg_dma_r_intr___group___lsb 0 +#define reg_dma_r_intr___group___width 1 +#define reg_dma_r_intr___group___bit 0 +#define reg_dma_r_intr___ctxt___lsb 1 +#define reg_dma_r_intr___ctxt___width 1 +#define reg_dma_r_intr___ctxt___bit 1 +#define reg_dma_r_intr___data___lsb 2 +#define reg_dma_r_intr___data___width 1 +#define reg_dma_r_intr___data___bit 2 +#define reg_dma_r_intr___in_eop___lsb 3 +#define reg_dma_r_intr___in_eop___width 1 +#define reg_dma_r_intr___in_eop___bit 3 +#define reg_dma_r_intr___stream_cmd___lsb 4 +#define reg_dma_r_intr___stream_cmd___width 1 +#define reg_dma_r_intr___stream_cmd___bit 4 +#define reg_dma_r_intr_offset 148 + +/* Register r_masked_intr, scope dma, type r */ +#define reg_dma_r_masked_intr___group___lsb 0 +#define reg_dma_r_masked_intr___group___width 1 +#define reg_dma_r_masked_intr___group___bit 0 +#define reg_dma_r_masked_intr___ctxt___lsb 1 +#define reg_dma_r_masked_intr___ctxt___width 1 +#define reg_dma_r_masked_intr___ctxt___bit 1 +#define reg_dma_r_masked_intr___data___lsb 2 +#define reg_dma_r_masked_intr___data___width 1 +#define reg_dma_r_masked_intr___data___bit 2 +#define reg_dma_r_masked_intr___in_eop___lsb 3 +#define reg_dma_r_masked_intr___in_eop___width 1 +#define reg_dma_r_masked_intr___in_eop___bit 3 +#define reg_dma_r_masked_intr___stream_cmd___lsb 4 +#define reg_dma_r_masked_intr___stream_cmd___width 1 +#define reg_dma_r_masked_intr___stream_cmd___bit 4 +#define reg_dma_r_masked_intr_offset 152 + +/* Register rw_stream_cmd, scope dma, type rw */ +#define reg_dma_rw_stream_cmd___cmd___lsb 0 +#define reg_dma_rw_stream_cmd___cmd___width 10 +#define reg_dma_rw_stream_cmd___n___lsb 16 +#define reg_dma_rw_stream_cmd___n___width 8 +#define reg_dma_rw_stream_cmd___busy___lsb 31 +#define reg_dma_rw_stream_cmd___busy___width 1 +#define reg_dma_rw_stream_cmd___busy___bit 31 +#define reg_dma_rw_stream_cmd_offset 156 + + +/* Constants */ +#define regk_dma_ack_pkt 0x00000100 +#define regk_dma_anytime 0x00000001 +#define regk_dma_array 0x00000008 +#define regk_dma_burst 0x00000020 +#define regk_dma_client 0x00000002 +#define regk_dma_copy_next 0x00000010 +#define regk_dma_copy_up 0x00000020 +#define regk_dma_data_at_eol 0x00000001 +#define regk_dma_dis_c 0x00000010 +#define regk_dma_dis_g 0x00000020 +#define regk_dma_idle 0x00000001 +#define regk_dma_intern 0x00000004 +#define regk_dma_load_c 0x00000200 +#define regk_dma_load_c_n 0x00000280 +#define regk_dma_load_c_next 0x00000240 +#define regk_dma_load_d 0x00000140 +#define regk_dma_load_g 0x00000300 +#define regk_dma_load_g_down 0x000003c0 +#define regk_dma_load_g_next 0x00000340 +#define regk_dma_load_g_up 0x00000380 +#define regk_dma_next_en 0x00000010 +#define regk_dma_next_pkt 0x00000010 +#define regk_dma_no 0x00000000 +#define regk_dma_only_at_wait 0x00000000 +#define regk_dma_restore 0x00000020 +#define regk_dma_rst 0x00000001 +#define regk_dma_running 0x00000004 +#define regk_dma_rw_cfg_default 0x00000000 +#define regk_dma_rw_cmd_default 0x00000000 +#define regk_dma_rw_intr_mask_default 0x00000000 +#define regk_dma_rw_stat_default 0x00000101 +#define regk_dma_rw_stream_cmd_default 0x00000000 +#define regk_dma_save_down 0x00000020 +#define regk_dma_save_up 0x00000020 +#define regk_dma_set_reg 0x00000050 +#define regk_dma_set_w_size1 0x00000190 +#define regk_dma_set_w_size2 0x000001a0 +#define regk_dma_set_w_size4 0x000001c0 +#define regk_dma_stopped 0x00000002 +#define regk_dma_store_c 0x00000002 +#define regk_dma_store_descr 0x00000000 +#define regk_dma_store_g 0x00000004 +#define regk_dma_store_md 0x00000001 +#define regk_dma_sw 0x00000008 +#define regk_dma_update_down 0x00000020 +#define regk_dma_yes 0x00000001 +#endif /* __dma_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h new file mode 100644 index 000000000000..c9f49864831b --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h @@ -0,0 +1,498 @@ +#ifndef __eth_defs_asm_h +#define __eth_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/eth/rtl/eth_regs.r + * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp + * last modfied: Mon Apr 11 16:07:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r + * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ma0_lo, scope eth, type rw */ +#define reg_eth_rw_ma0_lo___addr___lsb 0 +#define reg_eth_rw_ma0_lo___addr___width 32 +#define reg_eth_rw_ma0_lo_offset 0 + +/* Register rw_ma0_hi, scope eth, type rw */ +#define reg_eth_rw_ma0_hi___addr___lsb 0 +#define reg_eth_rw_ma0_hi___addr___width 16 +#define reg_eth_rw_ma0_hi_offset 4 + +/* Register rw_ma1_lo, scope eth, type rw */ +#define reg_eth_rw_ma1_lo___addr___lsb 0 +#define reg_eth_rw_ma1_lo___addr___width 32 +#define reg_eth_rw_ma1_lo_offset 8 + +/* Register rw_ma1_hi, scope eth, type rw */ +#define reg_eth_rw_ma1_hi___addr___lsb 0 +#define reg_eth_rw_ma1_hi___addr___width 16 +#define reg_eth_rw_ma1_hi_offset 12 + +/* Register rw_ga_lo, scope eth, type rw */ +#define reg_eth_rw_ga_lo___table___lsb 0 +#define reg_eth_rw_ga_lo___table___width 32 +#define reg_eth_rw_ga_lo_offset 16 + +/* Register rw_ga_hi, scope eth, type rw */ +#define reg_eth_rw_ga_hi___table___lsb 0 +#define reg_eth_rw_ga_hi___table___width 32 +#define reg_eth_rw_ga_hi_offset 20 + +/* Register rw_gen_ctrl, scope eth, type rw */ +#define reg_eth_rw_gen_ctrl___en___lsb 0 +#define reg_eth_rw_gen_ctrl___en___width 1 +#define reg_eth_rw_gen_ctrl___en___bit 0 +#define reg_eth_rw_gen_ctrl___phy___lsb 1 +#define reg_eth_rw_gen_ctrl___phy___width 2 +#define reg_eth_rw_gen_ctrl___protocol___lsb 3 +#define reg_eth_rw_gen_ctrl___protocol___width 1 +#define reg_eth_rw_gen_ctrl___protocol___bit 3 +#define reg_eth_rw_gen_ctrl___loopback___lsb 4 +#define reg_eth_rw_gen_ctrl___loopback___width 1 +#define reg_eth_rw_gen_ctrl___loopback___bit 4 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 +#define reg_eth_rw_gen_ctrl_offset 24 + +/* Register rw_rec_ctrl, scope eth, type rw */ +#define reg_eth_rw_rec_ctrl___ma0___lsb 0 +#define reg_eth_rw_rec_ctrl___ma0___width 1 +#define reg_eth_rw_rec_ctrl___ma0___bit 0 +#define reg_eth_rw_rec_ctrl___ma1___lsb 1 +#define reg_eth_rw_rec_ctrl___ma1___width 1 +#define reg_eth_rw_rec_ctrl___ma1___bit 1 +#define reg_eth_rw_rec_ctrl___individual___lsb 2 +#define reg_eth_rw_rec_ctrl___individual___width 1 +#define reg_eth_rw_rec_ctrl___individual___bit 2 +#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 +#define reg_eth_rw_rec_ctrl___broadcast___width 1 +#define reg_eth_rw_rec_ctrl___broadcast___bit 3 +#define reg_eth_rw_rec_ctrl___undersize___lsb 4 +#define reg_eth_rw_rec_ctrl___undersize___width 1 +#define reg_eth_rw_rec_ctrl___undersize___bit 4 +#define reg_eth_rw_rec_ctrl___oversize___lsb 5 +#define reg_eth_rw_rec_ctrl___oversize___width 1 +#define reg_eth_rw_rec_ctrl___oversize___bit 5 +#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 +#define reg_eth_rw_rec_ctrl___bad_crc___width 1 +#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 +#define reg_eth_rw_rec_ctrl___duplex___lsb 7 +#define reg_eth_rw_rec_ctrl___duplex___width 1 +#define reg_eth_rw_rec_ctrl___duplex___bit 7 +#define reg_eth_rw_rec_ctrl___max_size___lsb 8 +#define reg_eth_rw_rec_ctrl___max_size___width 1 +#define reg_eth_rw_rec_ctrl___max_size___bit 8 +#define reg_eth_rw_rec_ctrl_offset 28 + +/* Register rw_tr_ctrl, scope eth, type rw */ +#define reg_eth_rw_tr_ctrl___crc___lsb 0 +#define reg_eth_rw_tr_ctrl___crc___width 1 +#define reg_eth_rw_tr_ctrl___crc___bit 0 +#define reg_eth_rw_tr_ctrl___pad___lsb 1 +#define reg_eth_rw_tr_ctrl___pad___width 1 +#define reg_eth_rw_tr_ctrl___pad___bit 1 +#define reg_eth_rw_tr_ctrl___retry___lsb 2 +#define reg_eth_rw_tr_ctrl___retry___width 1 +#define reg_eth_rw_tr_ctrl___retry___bit 2 +#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 +#define reg_eth_rw_tr_ctrl___ignore_col___width 1 +#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 +#define reg_eth_rw_tr_ctrl___cancel___lsb 4 +#define reg_eth_rw_tr_ctrl___cancel___width 1 +#define reg_eth_rw_tr_ctrl___cancel___bit 4 +#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 +#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 +#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 +#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 +#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 +#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 +#define reg_eth_rw_tr_ctrl_offset 32 + +/* Register rw_clr_err, scope eth, type rw */ +#define reg_eth_rw_clr_err___clr___lsb 0 +#define reg_eth_rw_clr_err___clr___width 1 +#define reg_eth_rw_clr_err___clr___bit 0 +#define reg_eth_rw_clr_err_offset 36 + +/* Register rw_mgm_ctrl, scope eth, type rw */ +#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 +#define reg_eth_rw_mgm_ctrl___mdio___width 1 +#define reg_eth_rw_mgm_ctrl___mdio___bit 0 +#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 +#define reg_eth_rw_mgm_ctrl___mdoe___width 1 +#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 +#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 +#define reg_eth_rw_mgm_ctrl___mdc___width 1 +#define reg_eth_rw_mgm_ctrl___mdc___bit 2 +#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 +#define reg_eth_rw_mgm_ctrl___phyclk___width 1 +#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 +#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 +#define reg_eth_rw_mgm_ctrl___txdata___width 4 +#define reg_eth_rw_mgm_ctrl___txen___lsb 8 +#define reg_eth_rw_mgm_ctrl___txen___width 1 +#define reg_eth_rw_mgm_ctrl___txen___bit 8 +#define reg_eth_rw_mgm_ctrl_offset 40 + +/* Register r_stat, scope eth, type r */ +#define reg_eth_r_stat___mdio___lsb 0 +#define reg_eth_r_stat___mdio___width 1 +#define reg_eth_r_stat___mdio___bit 0 +#define reg_eth_r_stat___exc_col___lsb 1 +#define reg_eth_r_stat___exc_col___width 1 +#define reg_eth_r_stat___exc_col___bit 1 +#define reg_eth_r_stat___urun___lsb 2 +#define reg_eth_r_stat___urun___width 1 +#define reg_eth_r_stat___urun___bit 2 +#define reg_eth_r_stat___phyclk___lsb 3 +#define reg_eth_r_stat___phyclk___width 1 +#define reg_eth_r_stat___phyclk___bit 3 +#define reg_eth_r_stat___txdata___lsb 4 +#define reg_eth_r_stat___txdata___width 4 +#define reg_eth_r_stat___txen___lsb 8 +#define reg_eth_r_stat___txen___width 1 +#define reg_eth_r_stat___txen___bit 8 +#define reg_eth_r_stat___col___lsb 9 +#define reg_eth_r_stat___col___width 1 +#define reg_eth_r_stat___col___bit 9 +#define reg_eth_r_stat___crs___lsb 10 +#define reg_eth_r_stat___crs___width 1 +#define reg_eth_r_stat___crs___bit 10 +#define reg_eth_r_stat___txclk___lsb 11 +#define reg_eth_r_stat___txclk___width 1 +#define reg_eth_r_stat___txclk___bit 11 +#define reg_eth_r_stat___rxdata___lsb 12 +#define reg_eth_r_stat___rxdata___width 4 +#define reg_eth_r_stat___rxer___lsb 16 +#define reg_eth_r_stat___rxer___width 1 +#define reg_eth_r_stat___rxer___bit 16 +#define reg_eth_r_stat___rxdv___lsb 17 +#define reg_eth_r_stat___rxdv___width 1 +#define reg_eth_r_stat___rxdv___bit 17 +#define reg_eth_r_stat___rxclk___lsb 18 +#define reg_eth_r_stat___rxclk___width 1 +#define reg_eth_r_stat___rxclk___bit 18 +#define reg_eth_r_stat_offset 44 + +/* Register rs_rec_cnt, scope eth, type rs */ +#define reg_eth_rs_rec_cnt___crc_err___lsb 0 +#define reg_eth_rs_rec_cnt___crc_err___width 8 +#define reg_eth_rs_rec_cnt___align_err___lsb 8 +#define reg_eth_rs_rec_cnt___align_err___width 8 +#define reg_eth_rs_rec_cnt___oversize___lsb 16 +#define reg_eth_rs_rec_cnt___oversize___width 8 +#define reg_eth_rs_rec_cnt___congestion___lsb 24 +#define reg_eth_rs_rec_cnt___congestion___width 8 +#define reg_eth_rs_rec_cnt_offset 48 + +/* Register r_rec_cnt, scope eth, type r */ +#define reg_eth_r_rec_cnt___crc_err___lsb 0 +#define reg_eth_r_rec_cnt___crc_err___width 8 +#define reg_eth_r_rec_cnt___align_err___lsb 8 +#define reg_eth_r_rec_cnt___align_err___width 8 +#define reg_eth_r_rec_cnt___oversize___lsb 16 +#define reg_eth_r_rec_cnt___oversize___width 8 +#define reg_eth_r_rec_cnt___congestion___lsb 24 +#define reg_eth_r_rec_cnt___congestion___width 8 +#define reg_eth_r_rec_cnt_offset 52 + +/* Register rs_tr_cnt, scope eth, type rs */ +#define reg_eth_rs_tr_cnt___single_col___lsb 0 +#define reg_eth_rs_tr_cnt___single_col___width 8 +#define reg_eth_rs_tr_cnt___mult_col___lsb 8 +#define reg_eth_rs_tr_cnt___mult_col___width 8 +#define reg_eth_rs_tr_cnt___late_col___lsb 16 +#define reg_eth_rs_tr_cnt___late_col___width 8 +#define reg_eth_rs_tr_cnt___deferred___lsb 24 +#define reg_eth_rs_tr_cnt___deferred___width 8 +#define reg_eth_rs_tr_cnt_offset 56 + +/* Register r_tr_cnt, scope eth, type r */ +#define reg_eth_r_tr_cnt___single_col___lsb 0 +#define reg_eth_r_tr_cnt___single_col___width 8 +#define reg_eth_r_tr_cnt___mult_col___lsb 8 +#define reg_eth_r_tr_cnt___mult_col___width 8 +#define reg_eth_r_tr_cnt___late_col___lsb 16 +#define reg_eth_r_tr_cnt___late_col___width 8 +#define reg_eth_r_tr_cnt___deferred___lsb 24 +#define reg_eth_r_tr_cnt___deferred___width 8 +#define reg_eth_r_tr_cnt_offset 60 + +/* Register rs_phy_cnt, scope eth, type rs */ +#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 +#define reg_eth_rs_phy_cnt___carrier_loss___width 8 +#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 +#define reg_eth_rs_phy_cnt___sqe_err___width 8 +#define reg_eth_rs_phy_cnt_offset 64 + +/* Register r_phy_cnt, scope eth, type r */ +#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 +#define reg_eth_r_phy_cnt___carrier_loss___width 8 +#define reg_eth_r_phy_cnt___sqe_err___lsb 8 +#define reg_eth_r_phy_cnt___sqe_err___width 8 +#define reg_eth_r_phy_cnt_offset 68 + +/* Register rw_test_ctrl, scope eth, type rw */ +#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 +#define reg_eth_rw_test_ctrl___snmp_inc___width 1 +#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 +#define reg_eth_rw_test_ctrl___snmp___lsb 1 +#define reg_eth_rw_test_ctrl___snmp___width 1 +#define reg_eth_rw_test_ctrl___snmp___bit 1 +#define reg_eth_rw_test_ctrl___backoff___lsb 2 +#define reg_eth_rw_test_ctrl___backoff___width 1 +#define reg_eth_rw_test_ctrl___backoff___bit 2 +#define reg_eth_rw_test_ctrl_offset 72 + +/* Register rw_intr_mask, scope eth, type rw */ +#define reg_eth_rw_intr_mask___crc___lsb 0 +#define reg_eth_rw_intr_mask___crc___width 1 +#define reg_eth_rw_intr_mask___crc___bit 0 +#define reg_eth_rw_intr_mask___align___lsb 1 +#define reg_eth_rw_intr_mask___align___width 1 +#define reg_eth_rw_intr_mask___align___bit 1 +#define reg_eth_rw_intr_mask___oversize___lsb 2 +#define reg_eth_rw_intr_mask___oversize___width 1 +#define reg_eth_rw_intr_mask___oversize___bit 2 +#define reg_eth_rw_intr_mask___congestion___lsb 3 +#define reg_eth_rw_intr_mask___congestion___width 1 +#define reg_eth_rw_intr_mask___congestion___bit 3 +#define reg_eth_rw_intr_mask___single_col___lsb 4 +#define reg_eth_rw_intr_mask___single_col___width 1 +#define reg_eth_rw_intr_mask___single_col___bit 4 +#define reg_eth_rw_intr_mask___mult_col___lsb 5 +#define reg_eth_rw_intr_mask___mult_col___width 1 +#define reg_eth_rw_intr_mask___mult_col___bit 5 +#define reg_eth_rw_intr_mask___late_col___lsb 6 +#define reg_eth_rw_intr_mask___late_col___width 1 +#define reg_eth_rw_intr_mask___late_col___bit 6 +#define reg_eth_rw_intr_mask___deferred___lsb 7 +#define reg_eth_rw_intr_mask___deferred___width 1 +#define reg_eth_rw_intr_mask___deferred___bit 7 +#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 +#define reg_eth_rw_intr_mask___carrier_loss___width 1 +#define reg_eth_rw_intr_mask___carrier_loss___bit 8 +#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 +#define reg_eth_rw_intr_mask___sqe_test_err___width 1 +#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 +#define reg_eth_rw_intr_mask___orun___lsb 10 +#define reg_eth_rw_intr_mask___orun___width 1 +#define reg_eth_rw_intr_mask___orun___bit 10 +#define reg_eth_rw_intr_mask___urun___lsb 11 +#define reg_eth_rw_intr_mask___urun___width 1 +#define reg_eth_rw_intr_mask___urun___bit 11 +#define reg_eth_rw_intr_mask___excessive_col___lsb 12 +#define reg_eth_rw_intr_mask___excessive_col___width 1 +#define reg_eth_rw_intr_mask___excessive_col___bit 12 +#define reg_eth_rw_intr_mask___mdio___lsb 13 +#define reg_eth_rw_intr_mask___mdio___width 1 +#define reg_eth_rw_intr_mask___mdio___bit 13 +#define reg_eth_rw_intr_mask_offset 76 + +/* Register rw_ack_intr, scope eth, type rw */ +#define reg_eth_rw_ack_intr___crc___lsb 0 +#define reg_eth_rw_ack_intr___crc___width 1 +#define reg_eth_rw_ack_intr___crc___bit 0 +#define reg_eth_rw_ack_intr___align___lsb 1 +#define reg_eth_rw_ack_intr___align___width 1 +#define reg_eth_rw_ack_intr___align___bit 1 +#define reg_eth_rw_ack_intr___oversize___lsb 2 +#define reg_eth_rw_ack_intr___oversize___width 1 +#define reg_eth_rw_ack_intr___oversize___bit 2 +#define reg_eth_rw_ack_intr___congestion___lsb 3 +#define reg_eth_rw_ack_intr___congestion___width 1 +#define reg_eth_rw_ack_intr___congestion___bit 3 +#define reg_eth_rw_ack_intr___single_col___lsb 4 +#define reg_eth_rw_ack_intr___single_col___width 1 +#define reg_eth_rw_ack_intr___single_col___bit 4 +#define reg_eth_rw_ack_intr___mult_col___lsb 5 +#define reg_eth_rw_ack_intr___mult_col___width 1 +#define reg_eth_rw_ack_intr___mult_col___bit 5 +#define reg_eth_rw_ack_intr___late_col___lsb 6 +#define reg_eth_rw_ack_intr___late_col___width 1 +#define reg_eth_rw_ack_intr___late_col___bit 6 +#define reg_eth_rw_ack_intr___deferred___lsb 7 +#define reg_eth_rw_ack_intr___deferred___width 1 +#define reg_eth_rw_ack_intr___deferred___bit 7 +#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 +#define reg_eth_rw_ack_intr___carrier_loss___width 1 +#define reg_eth_rw_ack_intr___carrier_loss___bit 8 +#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 +#define reg_eth_rw_ack_intr___sqe_test_err___width 1 +#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 +#define reg_eth_rw_ack_intr___orun___lsb 10 +#define reg_eth_rw_ack_intr___orun___width 1 +#define reg_eth_rw_ack_intr___orun___bit 10 +#define reg_eth_rw_ack_intr___urun___lsb 11 +#define reg_eth_rw_ack_intr___urun___width 1 +#define reg_eth_rw_ack_intr___urun___bit 11 +#define reg_eth_rw_ack_intr___excessive_col___lsb 12 +#define reg_eth_rw_ack_intr___excessive_col___width 1 +#define reg_eth_rw_ack_intr___excessive_col___bit 12 +#define reg_eth_rw_ack_intr___mdio___lsb 13 +#define reg_eth_rw_ack_intr___mdio___width 1 +#define reg_eth_rw_ack_intr___mdio___bit 13 +#define reg_eth_rw_ack_intr_offset 80 + +/* Register r_intr, scope eth, type r */ +#define reg_eth_r_intr___crc___lsb 0 +#define reg_eth_r_intr___crc___width 1 +#define reg_eth_r_intr___crc___bit 0 +#define reg_eth_r_intr___align___lsb 1 +#define reg_eth_r_intr___align___width 1 +#define reg_eth_r_intr___align___bit 1 +#define reg_eth_r_intr___oversize___lsb 2 +#define reg_eth_r_intr___oversize___width 1 +#define reg_eth_r_intr___oversize___bit 2 +#define reg_eth_r_intr___congestion___lsb 3 +#define reg_eth_r_intr___congestion___width 1 +#define reg_eth_r_intr___congestion___bit 3 +#define reg_eth_r_intr___single_col___lsb 4 +#define reg_eth_r_intr___single_col___width 1 +#define reg_eth_r_intr___single_col___bit 4 +#define reg_eth_r_intr___mult_col___lsb 5 +#define reg_eth_r_intr___mult_col___width 1 +#define reg_eth_r_intr___mult_col___bit 5 +#define reg_eth_r_intr___late_col___lsb 6 +#define reg_eth_r_intr___late_col___width 1 +#define reg_eth_r_intr___late_col___bit 6 +#define reg_eth_r_intr___deferred___lsb 7 +#define reg_eth_r_intr___deferred___width 1 +#define reg_eth_r_intr___deferred___bit 7 +#define reg_eth_r_intr___carrier_loss___lsb 8 +#define reg_eth_r_intr___carrier_loss___width 1 +#define reg_eth_r_intr___carrier_loss___bit 8 +#define reg_eth_r_intr___sqe_test_err___lsb 9 +#define reg_eth_r_intr___sqe_test_err___width 1 +#define reg_eth_r_intr___sqe_test_err___bit 9 +#define reg_eth_r_intr___orun___lsb 10 +#define reg_eth_r_intr___orun___width 1 +#define reg_eth_r_intr___orun___bit 10 +#define reg_eth_r_intr___urun___lsb 11 +#define reg_eth_r_intr___urun___width 1 +#define reg_eth_r_intr___urun___bit 11 +#define reg_eth_r_intr___excessive_col___lsb 12 +#define reg_eth_r_intr___excessive_col___width 1 +#define reg_eth_r_intr___excessive_col___bit 12 +#define reg_eth_r_intr___mdio___lsb 13 +#define reg_eth_r_intr___mdio___width 1 +#define reg_eth_r_intr___mdio___bit 13 +#define reg_eth_r_intr_offset 84 + +/* Register r_masked_intr, scope eth, type r */ +#define reg_eth_r_masked_intr___crc___lsb 0 +#define reg_eth_r_masked_intr___crc___width 1 +#define reg_eth_r_masked_intr___crc___bit 0 +#define reg_eth_r_masked_intr___align___lsb 1 +#define reg_eth_r_masked_intr___align___width 1 +#define reg_eth_r_masked_intr___align___bit 1 +#define reg_eth_r_masked_intr___oversize___lsb 2 +#define reg_eth_r_masked_intr___oversize___width 1 +#define reg_eth_r_masked_intr___oversize___bit 2 +#define reg_eth_r_masked_intr___congestion___lsb 3 +#define reg_eth_r_masked_intr___congestion___width 1 +#define reg_eth_r_masked_intr___congestion___bit 3 +#define reg_eth_r_masked_intr___single_col___lsb 4 +#define reg_eth_r_masked_intr___single_col___width 1 +#define reg_eth_r_masked_intr___single_col___bit 4 +#define reg_eth_r_masked_intr___mult_col___lsb 5 +#define reg_eth_r_masked_intr___mult_col___width 1 +#define reg_eth_r_masked_intr___mult_col___bit 5 +#define reg_eth_r_masked_intr___late_col___lsb 6 +#define reg_eth_r_masked_intr___late_col___width 1 +#define reg_eth_r_masked_intr___late_col___bit 6 +#define reg_eth_r_masked_intr___deferred___lsb 7 +#define reg_eth_r_masked_intr___deferred___width 1 +#define reg_eth_r_masked_intr___deferred___bit 7 +#define reg_eth_r_masked_intr___carrier_loss___lsb 8 +#define reg_eth_r_masked_intr___carrier_loss___width 1 +#define reg_eth_r_masked_intr___carrier_loss___bit 8 +#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 +#define reg_eth_r_masked_intr___sqe_test_err___width 1 +#define reg_eth_r_masked_intr___sqe_test_err___bit 9 +#define reg_eth_r_masked_intr___orun___lsb 10 +#define reg_eth_r_masked_intr___orun___width 1 +#define reg_eth_r_masked_intr___orun___bit 10 +#define reg_eth_r_masked_intr___urun___lsb 11 +#define reg_eth_r_masked_intr___urun___width 1 +#define reg_eth_r_masked_intr___urun___bit 11 +#define reg_eth_r_masked_intr___excessive_col___lsb 12 +#define reg_eth_r_masked_intr___excessive_col___width 1 +#define reg_eth_r_masked_intr___excessive_col___bit 12 +#define reg_eth_r_masked_intr___mdio___lsb 13 +#define reg_eth_r_masked_intr___mdio___width 1 +#define reg_eth_r_masked_intr___mdio___bit 13 +#define reg_eth_r_masked_intr_offset 88 + + +/* Constants */ +#define regk_eth_discard 0x00000000 +#define regk_eth_ether 0x00000000 +#define regk_eth_full 0x00000001 +#define regk_eth_half 0x00000000 +#define regk_eth_hsh 0x00000001 +#define regk_eth_mii 0x00000001 +#define regk_eth_mii_clk 0x00000000 +#define regk_eth_mii_rec 0x00000002 +#define regk_eth_no 0x00000000 +#define regk_eth_rec 0x00000001 +#define regk_eth_rw_ga_hi_default 0x00000000 +#define regk_eth_rw_ga_lo_default 0x00000000 +#define regk_eth_rw_gen_ctrl_default 0x00000000 +#define regk_eth_rw_intr_mask_default 0x00000000 +#define regk_eth_rw_ma0_hi_default 0x00000000 +#define regk_eth_rw_ma0_lo_default 0x00000000 +#define regk_eth_rw_ma1_hi_default 0x00000000 +#define regk_eth_rw_ma1_lo_default 0x00000000 +#define regk_eth_rw_mgm_ctrl_default 0x00000000 +#define regk_eth_rw_test_ctrl_default 0x00000000 +#define regk_eth_size1518 0x00000000 +#define regk_eth_size1522 0x00000001 +#define regk_eth_yes 0x00000001 +#endif /* __eth_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000000..35356bc08629 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 8 +#define reg_gio_rw_pa_dout_offset 0 + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 8 +#define reg_gio_r_pa_din_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 8 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___pa0___lsb 0 +#define reg_gio_rw_intr_cfg___pa0___width 3 +#define reg_gio_rw_intr_cfg___pa1___lsb 3 +#define reg_gio_rw_intr_cfg___pa1___width 3 +#define reg_gio_rw_intr_cfg___pa2___lsb 6 +#define reg_gio_rw_intr_cfg___pa2___width 3 +#define reg_gio_rw_intr_cfg___pa3___lsb 9 +#define reg_gio_rw_intr_cfg___pa3___width 3 +#define reg_gio_rw_intr_cfg___pa4___lsb 12 +#define reg_gio_rw_intr_cfg___pa4___width 3 +#define reg_gio_rw_intr_cfg___pa5___lsb 15 +#define reg_gio_rw_intr_cfg___pa5___width 3 +#define reg_gio_rw_intr_cfg___pa6___lsb 18 +#define reg_gio_rw_intr_cfg___pa6___width 3 +#define reg_gio_rw_intr_cfg___pa7___lsb 21 +#define reg_gio_rw_intr_cfg___pa7___width 3 +#define reg_gio_rw_intr_cfg_offset 12 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___pa0___lsb 0 +#define reg_gio_rw_intr_mask___pa0___width 1 +#define reg_gio_rw_intr_mask___pa0___bit 0 +#define reg_gio_rw_intr_mask___pa1___lsb 1 +#define reg_gio_rw_intr_mask___pa1___width 1 +#define reg_gio_rw_intr_mask___pa1___bit 1 +#define reg_gio_rw_intr_mask___pa2___lsb 2 +#define reg_gio_rw_intr_mask___pa2___width 1 +#define reg_gio_rw_intr_mask___pa2___bit 2 +#define reg_gio_rw_intr_mask___pa3___lsb 3 +#define reg_gio_rw_intr_mask___pa3___width 1 +#define reg_gio_rw_intr_mask___pa3___bit 3 +#define reg_gio_rw_intr_mask___pa4___lsb 4 +#define reg_gio_rw_intr_mask___pa4___width 1 +#define reg_gio_rw_intr_mask___pa4___bit 4 +#define reg_gio_rw_intr_mask___pa5___lsb 5 +#define reg_gio_rw_intr_mask___pa5___width 1 +#define reg_gio_rw_intr_mask___pa5___bit 5 +#define reg_gio_rw_intr_mask___pa6___lsb 6 +#define reg_gio_rw_intr_mask___pa6___width 1 +#define reg_gio_rw_intr_mask___pa6___bit 6 +#define reg_gio_rw_intr_mask___pa7___lsb 7 +#define reg_gio_rw_intr_mask___pa7___width 1 +#define reg_gio_rw_intr_mask___pa7___bit 7 +#define reg_gio_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___pa0___lsb 0 +#define reg_gio_rw_ack_intr___pa0___width 1 +#define reg_gio_rw_ack_intr___pa0___bit 0 +#define reg_gio_rw_ack_intr___pa1___lsb 1 +#define reg_gio_rw_ack_intr___pa1___width 1 +#define reg_gio_rw_ack_intr___pa1___bit 1 +#define reg_gio_rw_ack_intr___pa2___lsb 2 +#define reg_gio_rw_ack_intr___pa2___width 1 +#define reg_gio_rw_ack_intr___pa2___bit 2 +#define reg_gio_rw_ack_intr___pa3___lsb 3 +#define reg_gio_rw_ack_intr___pa3___width 1 +#define reg_gio_rw_ack_intr___pa3___bit 3 +#define reg_gio_rw_ack_intr___pa4___lsb 4 +#define reg_gio_rw_ack_intr___pa4___width 1 +#define reg_gio_rw_ack_intr___pa4___bit 4 +#define reg_gio_rw_ack_intr___pa5___lsb 5 +#define reg_gio_rw_ack_intr___pa5___width 1 +#define reg_gio_rw_ack_intr___pa5___bit 5 +#define reg_gio_rw_ack_intr___pa6___lsb 6 +#define reg_gio_rw_ack_intr___pa6___width 1 +#define reg_gio_rw_ack_intr___pa6___bit 6 +#define reg_gio_rw_ack_intr___pa7___lsb 7 +#define reg_gio_rw_ack_intr___pa7___width 1 +#define reg_gio_rw_ack_intr___pa7___bit 7 +#define reg_gio_rw_ack_intr_offset 20 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___pa0___lsb 0 +#define reg_gio_r_intr___pa0___width 1 +#define reg_gio_r_intr___pa0___bit 0 +#define reg_gio_r_intr___pa1___lsb 1 +#define reg_gio_r_intr___pa1___width 1 +#define reg_gio_r_intr___pa1___bit 1 +#define reg_gio_r_intr___pa2___lsb 2 +#define reg_gio_r_intr___pa2___width 1 +#define reg_gio_r_intr___pa2___bit 2 +#define reg_gio_r_intr___pa3___lsb 3 +#define reg_gio_r_intr___pa3___width 1 +#define reg_gio_r_intr___pa3___bit 3 +#define reg_gio_r_intr___pa4___lsb 4 +#define reg_gio_r_intr___pa4___width 1 +#define reg_gio_r_intr___pa4___bit 4 +#define reg_gio_r_intr___pa5___lsb 5 +#define reg_gio_r_intr___pa5___width 1 +#define reg_gio_r_intr___pa5___bit 5 +#define reg_gio_r_intr___pa6___lsb 6 +#define reg_gio_r_intr___pa6___width 1 +#define reg_gio_r_intr___pa6___bit 6 +#define reg_gio_r_intr___pa7___lsb 7 +#define reg_gio_r_intr___pa7___width 1 +#define reg_gio_r_intr___pa7___bit 7 +#define reg_gio_r_intr_offset 24 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___pa0___lsb 0 +#define reg_gio_r_masked_intr___pa0___width 1 +#define reg_gio_r_masked_intr___pa0___bit 0 +#define reg_gio_r_masked_intr___pa1___lsb 1 +#define reg_gio_r_masked_intr___pa1___width 1 +#define reg_gio_r_masked_intr___pa1___bit 1 +#define reg_gio_r_masked_intr___pa2___lsb 2 +#define reg_gio_r_masked_intr___pa2___width 1 +#define reg_gio_r_masked_intr___pa2___bit 2 +#define reg_gio_r_masked_intr___pa3___lsb 3 +#define reg_gio_r_masked_intr___pa3___width 1 +#define reg_gio_r_masked_intr___pa3___bit 3 +#define reg_gio_r_masked_intr___pa4___lsb 4 +#define reg_gio_r_masked_intr___pa4___width 1 +#define reg_gio_r_masked_intr___pa4___bit 4 +#define reg_gio_r_masked_intr___pa5___lsb 5 +#define reg_gio_r_masked_intr___pa5___width 1 +#define reg_gio_r_masked_intr___pa5___bit 5 +#define reg_gio_r_masked_intr___pa6___lsb 6 +#define reg_gio_r_masked_intr___pa6___width 1 +#define reg_gio_r_masked_intr___pa6___bit 6 +#define reg_gio_r_masked_intr___pa7___lsb 7 +#define reg_gio_r_masked_intr___pa7___width 1 +#define reg_gio_r_masked_intr___pa7___bit 7 +#define reg_gio_r_masked_intr_offset 28 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 18 +#define reg_gio_rw_pb_dout_offset 32 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 18 +#define reg_gio_r_pb_din_offset 36 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 18 +#define reg_gio_rw_pb_oe_offset 40 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 18 +#define reg_gio_rw_pc_dout_offset 48 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 18 +#define reg_gio_r_pc_din_offset 52 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 18 +#define reg_gio_rw_pc_oe_offset 56 + +/* Register rw_pd_dout, scope gio, type rw */ +#define reg_gio_rw_pd_dout___data___lsb 0 +#define reg_gio_rw_pd_dout___data___width 18 +#define reg_gio_rw_pd_dout_offset 64 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 18 +#define reg_gio_r_pd_din_offset 68 + +/* Register rw_pd_oe, scope gio, type rw */ +#define reg_gio_rw_pd_oe___oe___lsb 0 +#define reg_gio_rw_pd_oe___oe___width 18 +#define reg_gio_rw_pd_oe_offset 72 + +/* Register rw_pe_dout, scope gio, type rw */ +#define reg_gio_rw_pe_dout___data___lsb 0 +#define reg_gio_rw_pe_dout___data___width 18 +#define reg_gio_rw_pe_dout_offset 80 + +/* Register r_pe_din, scope gio, type r */ +#define reg_gio_r_pe_din___data___lsb 0 +#define reg_gio_r_pe_din___data___width 18 +#define reg_gio_r_pe_din_offset 84 + +/* Register rw_pe_oe, scope gio, type rw */ +#define reg_gio_rw_pe_oe___oe___lsb 0 +#define reg_gio_rw_pe_oe___oe___width 18 +#define reg_gio_rw_pe_oe_offset 88 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_hi 0x00000001 +#define regk_gio_lo 0x00000002 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_off 0x00000000 +#define regk_gio_posedge 0x00000005 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_pd_oe_default 0x00000000 +#define regk_gio_rw_pe_oe_default 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h new file mode 100644 index 000000000000..c8315905c571 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h @@ -0,0 +1,38 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/intr_vect/rtl/guinness/ivmask.config.r +version . */ + +#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define MEMARB_INTR_VECT 0x31 +#define GEN_IO_INTR_VECT 0x32 +#define IOP0_INTR_VECT 0x33 +#define IOP1_INTR_VECT 0x34 +#define IOP2_INTR_VECT 0x35 +#define IOP3_INTR_VECT 0x36 +#define DMA0_INTR_VECT 0x37 +#define DMA1_INTR_VECT 0x38 +#define DMA2_INTR_VECT 0x39 +#define DMA3_INTR_VECT 0x3a +#define DMA4_INTR_VECT 0x3b +#define DMA5_INTR_VECT 0x3c +#define DMA6_INTR_VECT 0x3d +#define DMA7_INTR_VECT 0x3e +#define DMA8_INTR_VECT 0x3f +#define DMA9_INTR_VECT 0x40 +#define ATA_INTR_VECT 0x41 +#define SSER0_INTR_VECT 0x42 +#define SSER1_INTR_VECT 0x43 +#define SER0_INTR_VECT 0x44 +#define SER1_INTR_VECT 0x45 +#define SER2_INTR_VECT 0x46 +#define SER3_INTR_VECT 0x47 +#define P21_INTR_VECT 0x48 +#define ETH0_INTR_VECT 0x49 +#define ETH1_INTR_VECT 0x4a +#define TIMER_INTR_VECT 0x4b +#define BIF_ARB_INTR_VECT 0x4c +#define BIF_DMA_INTR_VECT 0x4d +#define EXT_INTR_VECT 0x4e + +#endif diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h new file mode 100644 index 000000000000..6df2a433b02d --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h @@ -0,0 +1,355 @@ +#ifndef __intr_vect_defs_asm_h +#define __intr_vect_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp + * last modfied: Mon Apr 11 16:08:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mask, scope intr_vect, type rw */ +#define reg_intr_vect_rw_mask___memarb___lsb 0 +#define reg_intr_vect_rw_mask___memarb___width 1 +#define reg_intr_vect_rw_mask___memarb___bit 0 +#define reg_intr_vect_rw_mask___gen_io___lsb 1 +#define reg_intr_vect_rw_mask___gen_io___width 1 +#define reg_intr_vect_rw_mask___gen_io___bit 1 +#define reg_intr_vect_rw_mask___iop0___lsb 2 +#define reg_intr_vect_rw_mask___iop0___width 1 +#define reg_intr_vect_rw_mask___iop0___bit 2 +#define reg_intr_vect_rw_mask___iop1___lsb 3 +#define reg_intr_vect_rw_mask___iop1___width 1 +#define reg_intr_vect_rw_mask___iop1___bit 3 +#define reg_intr_vect_rw_mask___iop2___lsb 4 +#define reg_intr_vect_rw_mask___iop2___width 1 +#define reg_intr_vect_rw_mask___iop2___bit 4 +#define reg_intr_vect_rw_mask___iop3___lsb 5 +#define reg_intr_vect_rw_mask___iop3___width 1 +#define reg_intr_vect_rw_mask___iop3___bit 5 +#define reg_intr_vect_rw_mask___dma0___lsb 6 +#define reg_intr_vect_rw_mask___dma0___width 1 +#define reg_intr_vect_rw_mask___dma0___bit 6 +#define reg_intr_vect_rw_mask___dma1___lsb 7 +#define reg_intr_vect_rw_mask___dma1___width 1 +#define reg_intr_vect_rw_mask___dma1___bit 7 +#define reg_intr_vect_rw_mask___dma2___lsb 8 +#define reg_intr_vect_rw_mask___dma2___width 1 +#define reg_intr_vect_rw_mask___dma2___bit 8 +#define reg_intr_vect_rw_mask___dma3___lsb 9 +#define reg_intr_vect_rw_mask___dma3___width 1 +#define reg_intr_vect_rw_mask___dma3___bit 9 +#define reg_intr_vect_rw_mask___dma4___lsb 10 +#define reg_intr_vect_rw_mask___dma4___width 1 +#define reg_intr_vect_rw_mask___dma4___bit 10 +#define reg_intr_vect_rw_mask___dma5___lsb 11 +#define reg_intr_vect_rw_mask___dma5___width 1 +#define reg_intr_vect_rw_mask___dma5___bit 11 +#define reg_intr_vect_rw_mask___dma6___lsb 12 +#define reg_intr_vect_rw_mask___dma6___width 1 +#define reg_intr_vect_rw_mask___dma6___bit 12 +#define reg_intr_vect_rw_mask___dma7___lsb 13 +#define reg_intr_vect_rw_mask___dma7___width 1 +#define reg_intr_vect_rw_mask___dma7___bit 13 +#define reg_intr_vect_rw_mask___dma8___lsb 14 +#define reg_intr_vect_rw_mask___dma8___width 1 +#define reg_intr_vect_rw_mask___dma8___bit 14 +#define reg_intr_vect_rw_mask___dma9___lsb 15 +#define reg_intr_vect_rw_mask___dma9___width 1 +#define reg_intr_vect_rw_mask___dma9___bit 15 +#define reg_intr_vect_rw_mask___ata___lsb 16 +#define reg_intr_vect_rw_mask___ata___width 1 +#define reg_intr_vect_rw_mask___ata___bit 16 +#define reg_intr_vect_rw_mask___sser0___lsb 17 +#define reg_intr_vect_rw_mask___sser0___width 1 +#define reg_intr_vect_rw_mask___sser0___bit 17 +#define reg_intr_vect_rw_mask___sser1___lsb 18 +#define reg_intr_vect_rw_mask___sser1___width 1 +#define reg_intr_vect_rw_mask___sser1___bit 18 +#define reg_intr_vect_rw_mask___ser0___lsb 19 +#define reg_intr_vect_rw_mask___ser0___width 1 +#define reg_intr_vect_rw_mask___ser0___bit 19 +#define reg_intr_vect_rw_mask___ser1___lsb 20 +#define reg_intr_vect_rw_mask___ser1___width 1 +#define reg_intr_vect_rw_mask___ser1___bit 20 +#define reg_intr_vect_rw_mask___ser2___lsb 21 +#define reg_intr_vect_rw_mask___ser2___width 1 +#define reg_intr_vect_rw_mask___ser2___bit 21 +#define reg_intr_vect_rw_mask___ser3___lsb 22 +#define reg_intr_vect_rw_mask___ser3___width 1 +#define reg_intr_vect_rw_mask___ser3___bit 22 +#define reg_intr_vect_rw_mask___p21___lsb 23 +#define reg_intr_vect_rw_mask___p21___width 1 +#define reg_intr_vect_rw_mask___p21___bit 23 +#define reg_intr_vect_rw_mask___eth0___lsb 24 +#define reg_intr_vect_rw_mask___eth0___width 1 +#define reg_intr_vect_rw_mask___eth0___bit 24 +#define reg_intr_vect_rw_mask___eth1___lsb 25 +#define reg_intr_vect_rw_mask___eth1___width 1 +#define reg_intr_vect_rw_mask___eth1___bit 25 +#define reg_intr_vect_rw_mask___timer___lsb 26 +#define reg_intr_vect_rw_mask___timer___width 1 +#define reg_intr_vect_rw_mask___timer___bit 26 +#define reg_intr_vect_rw_mask___bif_arb___lsb 27 +#define reg_intr_vect_rw_mask___bif_arb___width 1 +#define reg_intr_vect_rw_mask___bif_arb___bit 27 +#define reg_intr_vect_rw_mask___bif_dma___lsb 28 +#define reg_intr_vect_rw_mask___bif_dma___width 1 +#define reg_intr_vect_rw_mask___bif_dma___bit 28 +#define reg_intr_vect_rw_mask___ext___lsb 29 +#define reg_intr_vect_rw_mask___ext___width 1 +#define reg_intr_vect_rw_mask___ext___bit 29 +#define reg_intr_vect_rw_mask_offset 0 + +/* Register r_vect, scope intr_vect, type r */ +#define reg_intr_vect_r_vect___memarb___lsb 0 +#define reg_intr_vect_r_vect___memarb___width 1 +#define reg_intr_vect_r_vect___memarb___bit 0 +#define reg_intr_vect_r_vect___gen_io___lsb 1 +#define reg_intr_vect_r_vect___gen_io___width 1 +#define reg_intr_vect_r_vect___gen_io___bit 1 +#define reg_intr_vect_r_vect___iop0___lsb 2 +#define reg_intr_vect_r_vect___iop0___width 1 +#define reg_intr_vect_r_vect___iop0___bit 2 +#define reg_intr_vect_r_vect___iop1___lsb 3 +#define reg_intr_vect_r_vect___iop1___width 1 +#define reg_intr_vect_r_vect___iop1___bit 3 +#define reg_intr_vect_r_vect___iop2___lsb 4 +#define reg_intr_vect_r_vect___iop2___width 1 +#define reg_intr_vect_r_vect___iop2___bit 4 +#define reg_intr_vect_r_vect___iop3___lsb 5 +#define reg_intr_vect_r_vect___iop3___width 1 +#define reg_intr_vect_r_vect___iop3___bit 5 +#define reg_intr_vect_r_vect___dma0___lsb 6 +#define reg_intr_vect_r_vect___dma0___width 1 +#define reg_intr_vect_r_vect___dma0___bit 6 +#define reg_intr_vect_r_vect___dma1___lsb 7 +#define reg_intr_vect_r_vect___dma1___width 1 +#define reg_intr_vect_r_vect___dma1___bit 7 +#define reg_intr_vect_r_vect___dma2___lsb 8 +#define reg_intr_vect_r_vect___dma2___width 1 +#define reg_intr_vect_r_vect___dma2___bit 8 +#define reg_intr_vect_r_vect___dma3___lsb 9 +#define reg_intr_vect_r_vect___dma3___width 1 +#define reg_intr_vect_r_vect___dma3___bit 9 +#define reg_intr_vect_r_vect___dma4___lsb 10 +#define reg_intr_vect_r_vect___dma4___width 1 +#define reg_intr_vect_r_vect___dma4___bit 10 +#define reg_intr_vect_r_vect___dma5___lsb 11 +#define reg_intr_vect_r_vect___dma5___width 1 +#define reg_intr_vect_r_vect___dma5___bit 11 +#define reg_intr_vect_r_vect___dma6___lsb 12 +#define reg_intr_vect_r_vect___dma6___width 1 +#define reg_intr_vect_r_vect___dma6___bit 12 +#define reg_intr_vect_r_vect___dma7___lsb 13 +#define reg_intr_vect_r_vect___dma7___width 1 +#define reg_intr_vect_r_vect___dma7___bit 13 +#define reg_intr_vect_r_vect___dma8___lsb 14 +#define reg_intr_vect_r_vect___dma8___width 1 +#define reg_intr_vect_r_vect___dma8___bit 14 +#define reg_intr_vect_r_vect___dma9___lsb 15 +#define reg_intr_vect_r_vect___dma9___width 1 +#define reg_intr_vect_r_vect___dma9___bit 15 +#define reg_intr_vect_r_vect___ata___lsb 16 +#define reg_intr_vect_r_vect___ata___width 1 +#define reg_intr_vect_r_vect___ata___bit 16 +#define reg_intr_vect_r_vect___sser0___lsb 17 +#define reg_intr_vect_r_vect___sser0___width 1 +#define reg_intr_vect_r_vect___sser0___bit 17 +#define reg_intr_vect_r_vect___sser1___lsb 18 +#define reg_intr_vect_r_vect___sser1___width 1 +#define reg_intr_vect_r_vect___sser1___bit 18 +#define reg_intr_vect_r_vect___ser0___lsb 19 +#define reg_intr_vect_r_vect___ser0___width 1 +#define reg_intr_vect_r_vect___ser0___bit 19 +#define reg_intr_vect_r_vect___ser1___lsb 20 +#define reg_intr_vect_r_vect___ser1___width 1 +#define reg_intr_vect_r_vect___ser1___bit 20 +#define reg_intr_vect_r_vect___ser2___lsb 21 +#define reg_intr_vect_r_vect___ser2___width 1 +#define reg_intr_vect_r_vect___ser2___bit 21 +#define reg_intr_vect_r_vect___ser3___lsb 22 +#define reg_intr_vect_r_vect___ser3___width 1 +#define reg_intr_vect_r_vect___ser3___bit 22 +#define reg_intr_vect_r_vect___p21___lsb 23 +#define reg_intr_vect_r_vect___p21___width 1 +#define reg_intr_vect_r_vect___p21___bit 23 +#define reg_intr_vect_r_vect___eth0___lsb 24 +#define reg_intr_vect_r_vect___eth0___width 1 +#define reg_intr_vect_r_vect___eth0___bit 24 +#define reg_intr_vect_r_vect___eth1___lsb 25 +#define reg_intr_vect_r_vect___eth1___width 1 +#define reg_intr_vect_r_vect___eth1___bit 25 +#define reg_intr_vect_r_vect___timer___lsb 26 +#define reg_intr_vect_r_vect___timer___width 1 +#define reg_intr_vect_r_vect___timer___bit 26 +#define reg_intr_vect_r_vect___bif_arb___lsb 27 +#define reg_intr_vect_r_vect___bif_arb___width 1 +#define reg_intr_vect_r_vect___bif_arb___bit 27 +#define reg_intr_vect_r_vect___bif_dma___lsb 28 +#define reg_intr_vect_r_vect___bif_dma___width 1 +#define reg_intr_vect_r_vect___bif_dma___bit 28 +#define reg_intr_vect_r_vect___ext___lsb 29 +#define reg_intr_vect_r_vect___ext___width 1 +#define reg_intr_vect_r_vect___ext___bit 29 +#define reg_intr_vect_r_vect_offset 4 + +/* Register r_masked_vect, scope intr_vect, type r */ +#define reg_intr_vect_r_masked_vect___memarb___lsb 0 +#define reg_intr_vect_r_masked_vect___memarb___width 1 +#define reg_intr_vect_r_masked_vect___memarb___bit 0 +#define reg_intr_vect_r_masked_vect___gen_io___lsb 1 +#define reg_intr_vect_r_masked_vect___gen_io___width 1 +#define reg_intr_vect_r_masked_vect___gen_io___bit 1 +#define reg_intr_vect_r_masked_vect___iop0___lsb 2 +#define reg_intr_vect_r_masked_vect___iop0___width 1 +#define reg_intr_vect_r_masked_vect___iop0___bit 2 +#define reg_intr_vect_r_masked_vect___iop1___lsb 3 +#define reg_intr_vect_r_masked_vect___iop1___width 1 +#define reg_intr_vect_r_masked_vect___iop1___bit 3 +#define reg_intr_vect_r_masked_vect___iop2___lsb 4 +#define reg_intr_vect_r_masked_vect___iop2___width 1 +#define reg_intr_vect_r_masked_vect___iop2___bit 4 +#define reg_intr_vect_r_masked_vect___iop3___lsb 5 +#define reg_intr_vect_r_masked_vect___iop3___width 1 +#define reg_intr_vect_r_masked_vect___iop3___bit 5 +#define reg_intr_vect_r_masked_vect___dma0___lsb 6 +#define reg_intr_vect_r_masked_vect___dma0___width 1 +#define reg_intr_vect_r_masked_vect___dma0___bit 6 +#define reg_intr_vect_r_masked_vect___dma1___lsb 7 +#define reg_intr_vect_r_masked_vect___dma1___width 1 +#define reg_intr_vect_r_masked_vect___dma1___bit 7 +#define reg_intr_vect_r_masked_vect___dma2___lsb 8 +#define reg_intr_vect_r_masked_vect___dma2___width 1 +#define reg_intr_vect_r_masked_vect___dma2___bit 8 +#define reg_intr_vect_r_masked_vect___dma3___lsb 9 +#define reg_intr_vect_r_masked_vect___dma3___width 1 +#define reg_intr_vect_r_masked_vect___dma3___bit 9 +#define reg_intr_vect_r_masked_vect___dma4___lsb 10 +#define reg_intr_vect_r_masked_vect___dma4___width 1 +#define reg_intr_vect_r_masked_vect___dma4___bit 10 +#define reg_intr_vect_r_masked_vect___dma5___lsb 11 +#define reg_intr_vect_r_masked_vect___dma5___width 1 +#define reg_intr_vect_r_masked_vect___dma5___bit 11 +#define reg_intr_vect_r_masked_vect___dma6___lsb 12 +#define reg_intr_vect_r_masked_vect___dma6___width 1 +#define reg_intr_vect_r_masked_vect___dma6___bit 12 +#define reg_intr_vect_r_masked_vect___dma7___lsb 13 +#define reg_intr_vect_r_masked_vect___dma7___width 1 +#define reg_intr_vect_r_masked_vect___dma7___bit 13 +#define reg_intr_vect_r_masked_vect___dma8___lsb 14 +#define reg_intr_vect_r_masked_vect___dma8___width 1 +#define reg_intr_vect_r_masked_vect___dma8___bit 14 +#define reg_intr_vect_r_masked_vect___dma9___lsb 15 +#define reg_intr_vect_r_masked_vect___dma9___width 1 +#define reg_intr_vect_r_masked_vect___dma9___bit 15 +#define reg_intr_vect_r_masked_vect___ata___lsb 16 +#define reg_intr_vect_r_masked_vect___ata___width 1 +#define reg_intr_vect_r_masked_vect___ata___bit 16 +#define reg_intr_vect_r_masked_vect___sser0___lsb 17 +#define reg_intr_vect_r_masked_vect___sser0___width 1 +#define reg_intr_vect_r_masked_vect___sser0___bit 17 +#define reg_intr_vect_r_masked_vect___sser1___lsb 18 +#define reg_intr_vect_r_masked_vect___sser1___width 1 +#define reg_intr_vect_r_masked_vect___sser1___bit 18 +#define reg_intr_vect_r_masked_vect___ser0___lsb 19 +#define reg_intr_vect_r_masked_vect___ser0___width 1 +#define reg_intr_vect_r_masked_vect___ser0___bit 19 +#define reg_intr_vect_r_masked_vect___ser1___lsb 20 +#define reg_intr_vect_r_masked_vect___ser1___width 1 +#define reg_intr_vect_r_masked_vect___ser1___bit 20 +#define reg_intr_vect_r_masked_vect___ser2___lsb 21 +#define reg_intr_vect_r_masked_vect___ser2___width 1 +#define reg_intr_vect_r_masked_vect___ser2___bit 21 +#define reg_intr_vect_r_masked_vect___ser3___lsb 22 +#define reg_intr_vect_r_masked_vect___ser3___width 1 +#define reg_intr_vect_r_masked_vect___ser3___bit 22 +#define reg_intr_vect_r_masked_vect___p21___lsb 23 +#define reg_intr_vect_r_masked_vect___p21___width 1 +#define reg_intr_vect_r_masked_vect___p21___bit 23 +#define reg_intr_vect_r_masked_vect___eth0___lsb 24 +#define reg_intr_vect_r_masked_vect___eth0___width 1 +#define reg_intr_vect_r_masked_vect___eth0___bit 24 +#define reg_intr_vect_r_masked_vect___eth1___lsb 25 +#define reg_intr_vect_r_masked_vect___eth1___width 1 +#define reg_intr_vect_r_masked_vect___eth1___bit 25 +#define reg_intr_vect_r_masked_vect___timer___lsb 26 +#define reg_intr_vect_r_masked_vect___timer___width 1 +#define reg_intr_vect_r_masked_vect___timer___bit 26 +#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 +#define reg_intr_vect_r_masked_vect___bif_arb___width 1 +#define reg_intr_vect_r_masked_vect___bif_arb___bit 27 +#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 +#define reg_intr_vect_r_masked_vect___bif_dma___width 1 +#define reg_intr_vect_r_masked_vect___bif_dma___bit 28 +#define reg_intr_vect_r_masked_vect___ext___lsb 29 +#define reg_intr_vect_r_masked_vect___ext___width 1 +#define reg_intr_vect_r_masked_vect___ext___bit 29 +#define reg_intr_vect_r_masked_vect_offset 8 + +/* Register r_nmi, scope intr_vect, type r */ +#define reg_intr_vect_r_nmi___ext___lsb 0 +#define reg_intr_vect_r_nmi___ext___width 1 +#define reg_intr_vect_r_nmi___ext___bit 0 +#define reg_intr_vect_r_nmi___watchdog___lsb 1 +#define reg_intr_vect_r_nmi___watchdog___width 1 +#define reg_intr_vect_r_nmi___watchdog___bit 1 +#define reg_intr_vect_r_nmi_offset 12 + +/* Register r_guru, scope intr_vect, type r */ +#define reg_intr_vect_r_guru___jtag___lsb 0 +#define reg_intr_vect_r_guru___jtag___width 1 +#define reg_intr_vect_r_guru___jtag___bit 0 +#define reg_intr_vect_r_guru_offset 16 + + +/* Constants */ +#define regk_intr_vect_off 0x00000000 +#define regk_intr_vect_on 0x00000001 +#define regk_intr_vect_rw_mask_default 0x00000000 +#endif /* __intr_vect_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h new file mode 100644 index 000000000000..0c8084054840 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h @@ -0,0 +1,69 @@ +#ifndef __irq_nmi_defs_asm_h +#define __irq_nmi_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../mod/irq_nmi.r + * id: <not found> + * last modfied: Thu Jan 22 09:22:43 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r + * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cmd, scope irq_nmi, type rw */ +#define reg_irq_nmi_rw_cmd___delay___lsb 0 +#define reg_irq_nmi_rw_cmd___delay___width 16 +#define reg_irq_nmi_rw_cmd___op___lsb 16 +#define reg_irq_nmi_rw_cmd___op___width 2 +#define reg_irq_nmi_rw_cmd_offset 0 + + +/* Constants */ +#define regk_irq_nmi_ack_irq 0x00000002 +#define regk_irq_nmi_ack_nmi 0x00000003 +#define regk_irq_nmi_irq 0x00000000 +#define regk_irq_nmi_nmi 0x00000001 +#endif /* __irq_nmi_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h new file mode 100644 index 000000000000..45400eb8d389 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h @@ -0,0 +1,579 @@ +#ifndef __marb_defs_asm_h +#define __marb_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +#define reg_marb_rw_int_slots___owner___lsb 0 +#define reg_marb_rw_int_slots___owner___width 4 +#define reg_marb_rw_int_slots_offset 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +#define reg_marb_rw_ext_slots___owner___lsb 0 +#define reg_marb_rw_ext_slots___owner___width 4 +#define reg_marb_rw_ext_slots_offset 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +#define reg_marb_rw_regs_slots___owner___lsb 0 +#define reg_marb_rw_regs_slots___owner___width 4 +#define reg_marb_rw_regs_slots_offset 512 + +/* Register rw_intr_mask, scope marb, type rw */ +#define reg_marb_rw_intr_mask___bp0___lsb 0 +#define reg_marb_rw_intr_mask___bp0___width 1 +#define reg_marb_rw_intr_mask___bp0___bit 0 +#define reg_marb_rw_intr_mask___bp1___lsb 1 +#define reg_marb_rw_intr_mask___bp1___width 1 +#define reg_marb_rw_intr_mask___bp1___bit 1 +#define reg_marb_rw_intr_mask___bp2___lsb 2 +#define reg_marb_rw_intr_mask___bp2___width 1 +#define reg_marb_rw_intr_mask___bp2___bit 2 +#define reg_marb_rw_intr_mask___bp3___lsb 3 +#define reg_marb_rw_intr_mask___bp3___width 1 +#define reg_marb_rw_intr_mask___bp3___bit 3 +#define reg_marb_rw_intr_mask_offset 528 + +/* Register rw_ack_intr, scope marb, type rw */ +#define reg_marb_rw_ack_intr___bp0___lsb 0 +#define reg_marb_rw_ack_intr___bp0___width 1 +#define reg_marb_rw_ack_intr___bp0___bit 0 +#define reg_marb_rw_ack_intr___bp1___lsb 1 +#define reg_marb_rw_ack_intr___bp1___width 1 +#define reg_marb_rw_ack_intr___bp1___bit 1 +#define reg_marb_rw_ack_intr___bp2___lsb 2 +#define reg_marb_rw_ack_intr___bp2___width 1 +#define reg_marb_rw_ack_intr___bp2___bit 2 +#define reg_marb_rw_ack_intr___bp3___lsb 3 +#define reg_marb_rw_ack_intr___bp3___width 1 +#define reg_marb_rw_ack_intr___bp3___bit 3 +#define reg_marb_rw_ack_intr_offset 532 + +/* Register r_intr, scope marb, type r */ +#define reg_marb_r_intr___bp0___lsb 0 +#define reg_marb_r_intr___bp0___width 1 +#define reg_marb_r_intr___bp0___bit 0 +#define reg_marb_r_intr___bp1___lsb 1 +#define reg_marb_r_intr___bp1___width 1 +#define reg_marb_r_intr___bp1___bit 1 +#define reg_marb_r_intr___bp2___lsb 2 +#define reg_marb_r_intr___bp2___width 1 +#define reg_marb_r_intr___bp2___bit 2 +#define reg_marb_r_intr___bp3___lsb 3 +#define reg_marb_r_intr___bp3___width 1 +#define reg_marb_r_intr___bp3___bit 3 +#define reg_marb_r_intr_offset 536 + +/* Register r_masked_intr, scope marb, type r */ +#define reg_marb_r_masked_intr___bp0___lsb 0 +#define reg_marb_r_masked_intr___bp0___width 1 +#define reg_marb_r_masked_intr___bp0___bit 0 +#define reg_marb_r_masked_intr___bp1___lsb 1 +#define reg_marb_r_masked_intr___bp1___width 1 +#define reg_marb_r_masked_intr___bp1___bit 1 +#define reg_marb_r_masked_intr___bp2___lsb 2 +#define reg_marb_r_masked_intr___bp2___width 1 +#define reg_marb_r_masked_intr___bp2___bit 2 +#define reg_marb_r_masked_intr___bp3___lsb 3 +#define reg_marb_r_masked_intr___bp3___width 1 +#define reg_marb_r_masked_intr___bp3___bit 3 +#define reg_marb_r_masked_intr_offset 540 + +/* Register rw_stop_mask, scope marb, type rw */ +#define reg_marb_rw_stop_mask___dma0___lsb 0 +#define reg_marb_rw_stop_mask___dma0___width 1 +#define reg_marb_rw_stop_mask___dma0___bit 0 +#define reg_marb_rw_stop_mask___dma1___lsb 1 +#define reg_marb_rw_stop_mask___dma1___width 1 +#define reg_marb_rw_stop_mask___dma1___bit 1 +#define reg_marb_rw_stop_mask___dma2___lsb 2 +#define reg_marb_rw_stop_mask___dma2___width 1 +#define reg_marb_rw_stop_mask___dma2___bit 2 +#define reg_marb_rw_stop_mask___dma3___lsb 3 +#define reg_marb_rw_stop_mask___dma3___width 1 +#define reg_marb_rw_stop_mask___dma3___bit 3 +#define reg_marb_rw_stop_mask___dma4___lsb 4 +#define reg_marb_rw_stop_mask___dma4___width 1 +#define reg_marb_rw_stop_mask___dma4___bit 4 +#define reg_marb_rw_stop_mask___dma5___lsb 5 +#define reg_marb_rw_stop_mask___dma5___width 1 +#define reg_marb_rw_stop_mask___dma5___bit 5 +#define reg_marb_rw_stop_mask___dma6___lsb 6 +#define reg_marb_rw_stop_mask___dma6___width 1 +#define reg_marb_rw_stop_mask___dma6___bit 6 +#define reg_marb_rw_stop_mask___dma7___lsb 7 +#define reg_marb_rw_stop_mask___dma7___width 1 +#define reg_marb_rw_stop_mask___dma7___bit 7 +#define reg_marb_rw_stop_mask___dma8___lsb 8 +#define reg_marb_rw_stop_mask___dma8___width 1 +#define reg_marb_rw_stop_mask___dma8___bit 8 +#define reg_marb_rw_stop_mask___dma9___lsb 9 +#define reg_marb_rw_stop_mask___dma9___width 1 +#define reg_marb_rw_stop_mask___dma9___bit 9 +#define reg_marb_rw_stop_mask___cpui___lsb 10 +#define reg_marb_rw_stop_mask___cpui___width 1 +#define reg_marb_rw_stop_mask___cpui___bit 10 +#define reg_marb_rw_stop_mask___cpud___lsb 11 +#define reg_marb_rw_stop_mask___cpud___width 1 +#define reg_marb_rw_stop_mask___cpud___bit 11 +#define reg_marb_rw_stop_mask___iop___lsb 12 +#define reg_marb_rw_stop_mask___iop___width 1 +#define reg_marb_rw_stop_mask___iop___bit 12 +#define reg_marb_rw_stop_mask___slave___lsb 13 +#define reg_marb_rw_stop_mask___slave___width 1 +#define reg_marb_rw_stop_mask___slave___bit 13 +#define reg_marb_rw_stop_mask_offset 544 + +/* Register r_stopped, scope marb, type r */ +#define reg_marb_r_stopped___dma0___lsb 0 +#define reg_marb_r_stopped___dma0___width 1 +#define reg_marb_r_stopped___dma0___bit 0 +#define reg_marb_r_stopped___dma1___lsb 1 +#define reg_marb_r_stopped___dma1___width 1 +#define reg_marb_r_stopped___dma1___bit 1 +#define reg_marb_r_stopped___dma2___lsb 2 +#define reg_marb_r_stopped___dma2___width 1 +#define reg_marb_r_stopped___dma2___bit 2 +#define reg_marb_r_stopped___dma3___lsb 3 +#define reg_marb_r_stopped___dma3___width 1 +#define reg_marb_r_stopped___dma3___bit 3 +#define reg_marb_r_stopped___dma4___lsb 4 +#define reg_marb_r_stopped___dma4___width 1 +#define reg_marb_r_stopped___dma4___bit 4 +#define reg_marb_r_stopped___dma5___lsb 5 +#define reg_marb_r_stopped___dma5___width 1 +#define reg_marb_r_stopped___dma5___bit 5 +#define reg_marb_r_stopped___dma6___lsb 6 +#define reg_marb_r_stopped___dma6___width 1 +#define reg_marb_r_stopped___dma6___bit 6 +#define reg_marb_r_stopped___dma7___lsb 7 +#define reg_marb_r_stopped___dma7___width 1 +#define reg_marb_r_stopped___dma7___bit 7 +#define reg_marb_r_stopped___dma8___lsb 8 +#define reg_marb_r_stopped___dma8___width 1 +#define reg_marb_r_stopped___dma8___bit 8 +#define reg_marb_r_stopped___dma9___lsb 9 +#define reg_marb_r_stopped___dma9___width 1 +#define reg_marb_r_stopped___dma9___bit 9 +#define reg_marb_r_stopped___cpui___lsb 10 +#define reg_marb_r_stopped___cpui___width 1 +#define reg_marb_r_stopped___cpui___bit 10 +#define reg_marb_r_stopped___cpud___lsb 11 +#define reg_marb_r_stopped___cpud___width 1 +#define reg_marb_r_stopped___cpud___bit 11 +#define reg_marb_r_stopped___iop___lsb 12 +#define reg_marb_r_stopped___iop___width 1 +#define reg_marb_r_stopped___iop___bit 12 +#define reg_marb_r_stopped___slave___lsb 13 +#define reg_marb_r_stopped___slave___width 1 +#define reg_marb_r_stopped___slave___bit 13 +#define reg_marb_r_stopped_offset 548 + +/* Register rw_no_snoop, scope marb, type rw */ +#define reg_marb_rw_no_snoop___dma0___lsb 0 +#define reg_marb_rw_no_snoop___dma0___width 1 +#define reg_marb_rw_no_snoop___dma0___bit 0 +#define reg_marb_rw_no_snoop___dma1___lsb 1 +#define reg_marb_rw_no_snoop___dma1___width 1 +#define reg_marb_rw_no_snoop___dma1___bit 1 +#define reg_marb_rw_no_snoop___dma2___lsb 2 +#define reg_marb_rw_no_snoop___dma2___width 1 +#define reg_marb_rw_no_snoop___dma2___bit 2 +#define reg_marb_rw_no_snoop___dma3___lsb 3 +#define reg_marb_rw_no_snoop___dma3___width 1 +#define reg_marb_rw_no_snoop___dma3___bit 3 +#define reg_marb_rw_no_snoop___dma4___lsb 4 +#define reg_marb_rw_no_snoop___dma4___width 1 +#define reg_marb_rw_no_snoop___dma4___bit 4 +#define reg_marb_rw_no_snoop___dma5___lsb 5 +#define reg_marb_rw_no_snoop___dma5___width 1 +#define reg_marb_rw_no_snoop___dma5___bit 5 +#define reg_marb_rw_no_snoop___dma6___lsb 6 +#define reg_marb_rw_no_snoop___dma6___width 1 +#define reg_marb_rw_no_snoop___dma6___bit 6 +#define reg_marb_rw_no_snoop___dma7___lsb 7 +#define reg_marb_rw_no_snoop___dma7___width 1 +#define reg_marb_rw_no_snoop___dma7___bit 7 +#define reg_marb_rw_no_snoop___dma8___lsb 8 +#define reg_marb_rw_no_snoop___dma8___width 1 +#define reg_marb_rw_no_snoop___dma8___bit 8 +#define reg_marb_rw_no_snoop___dma9___lsb 9 +#define reg_marb_rw_no_snoop___dma9___width 1 +#define reg_marb_rw_no_snoop___dma9___bit 9 +#define reg_marb_rw_no_snoop___cpui___lsb 10 +#define reg_marb_rw_no_snoop___cpui___width 1 +#define reg_marb_rw_no_snoop___cpui___bit 10 +#define reg_marb_rw_no_snoop___cpud___lsb 11 +#define reg_marb_rw_no_snoop___cpud___width 1 +#define reg_marb_rw_no_snoop___cpud___bit 11 +#define reg_marb_rw_no_snoop___iop___lsb 12 +#define reg_marb_rw_no_snoop___iop___width 1 +#define reg_marb_rw_no_snoop___iop___bit 12 +#define reg_marb_rw_no_snoop___slave___lsb 13 +#define reg_marb_rw_no_snoop___slave___width 1 +#define reg_marb_rw_no_snoop___slave___bit 13 +#define reg_marb_rw_no_snoop_offset 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +#define reg_marb_rw_no_snoop_rq___cpui___lsb 10 +#define reg_marb_rw_no_snoop_rq___cpui___width 1 +#define reg_marb_rw_no_snoop_rq___cpui___bit 10 +#define reg_marb_rw_no_snoop_rq___cpud___lsb 11 +#define reg_marb_rw_no_snoop_rq___cpud___width 1 +#define reg_marb_rw_no_snoop_rq___cpud___bit 11 +#define reg_marb_rw_no_snoop_rq_offset 836 + + +/* Constants */ +#define regk_marb_cpud 0x0000000b +#define regk_marb_cpui 0x0000000a +#define regk_marb_dma0 0x00000000 +#define regk_marb_dma1 0x00000001 +#define regk_marb_dma2 0x00000002 +#define regk_marb_dma3 0x00000003 +#define regk_marb_dma4 0x00000004 +#define regk_marb_dma5 0x00000005 +#define regk_marb_dma6 0x00000006 +#define regk_marb_dma7 0x00000007 +#define regk_marb_dma8 0x00000008 +#define regk_marb_dma9 0x00000009 +#define regk_marb_iop 0x0000000c +#define regk_marb_no 0x00000000 +#define regk_marb_r_stopped_default 0x00000000 +#define regk_marb_rw_ext_slots_default 0x00000000 +#define regk_marb_rw_ext_slots_size 0x00000040 +#define regk_marb_rw_int_slots_default 0x00000000 +#define regk_marb_rw_int_slots_size 0x00000040 +#define regk_marb_rw_intr_mask_default 0x00000000 +#define regk_marb_rw_no_snoop_default 0x00000000 +#define regk_marb_rw_no_snoop_rq_default 0x00000000 +#define regk_marb_rw_regs_slots_default 0x00000000 +#define regk_marb_rw_regs_slots_size 0x00000004 +#define regk_marb_rw_stop_mask_default 0x00000000 +#define regk_marb_slave 0x0000000d +#define regk_marb_yes 0x00000001 +#endif /* __marb_defs_asm_h */ +#ifndef __marb_bp_defs_asm_h +#define __marb_bp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_first_addr, scope marb_bp, type rw */ +#define reg_marb_bp_rw_first_addr_offset 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +#define reg_marb_bp_rw_last_addr_offset 4 + +/* Register rw_op, scope marb_bp, type rw */ +#define reg_marb_bp_rw_op___rd___lsb 0 +#define reg_marb_bp_rw_op___rd___width 1 +#define reg_marb_bp_rw_op___rd___bit 0 +#define reg_marb_bp_rw_op___wr___lsb 1 +#define reg_marb_bp_rw_op___wr___width 1 +#define reg_marb_bp_rw_op___wr___bit 1 +#define reg_marb_bp_rw_op___rd_excl___lsb 2 +#define reg_marb_bp_rw_op___rd_excl___width 1 +#define reg_marb_bp_rw_op___rd_excl___bit 2 +#define reg_marb_bp_rw_op___pri_wr___lsb 3 +#define reg_marb_bp_rw_op___pri_wr___width 1 +#define reg_marb_bp_rw_op___pri_wr___bit 3 +#define reg_marb_bp_rw_op___us_rd___lsb 4 +#define reg_marb_bp_rw_op___us_rd___width 1 +#define reg_marb_bp_rw_op___us_rd___bit 4 +#define reg_marb_bp_rw_op___us_wr___lsb 5 +#define reg_marb_bp_rw_op___us_wr___width 1 +#define reg_marb_bp_rw_op___us_wr___bit 5 +#define reg_marb_bp_rw_op___us_rd_excl___lsb 6 +#define reg_marb_bp_rw_op___us_rd_excl___width 1 +#define reg_marb_bp_rw_op___us_rd_excl___bit 6 +#define reg_marb_bp_rw_op___us_pri_wr___lsb 7 +#define reg_marb_bp_rw_op___us_pri_wr___width 1 +#define reg_marb_bp_rw_op___us_pri_wr___bit 7 +#define reg_marb_bp_rw_op_offset 8 + +/* Register rw_clients, scope marb_bp, type rw */ +#define reg_marb_bp_rw_clients___dma0___lsb 0 +#define reg_marb_bp_rw_clients___dma0___width 1 +#define reg_marb_bp_rw_clients___dma0___bit 0 +#define reg_marb_bp_rw_clients___dma1___lsb 1 +#define reg_marb_bp_rw_clients___dma1___width 1 +#define reg_marb_bp_rw_clients___dma1___bit 1 +#define reg_marb_bp_rw_clients___dma2___lsb 2 +#define reg_marb_bp_rw_clients___dma2___width 1 +#define reg_marb_bp_rw_clients___dma2___bit 2 +#define reg_marb_bp_rw_clients___dma3___lsb 3 +#define reg_marb_bp_rw_clients___dma3___width 1 +#define reg_marb_bp_rw_clients___dma3___bit 3 +#define reg_marb_bp_rw_clients___dma4___lsb 4 +#define reg_marb_bp_rw_clients___dma4___width 1 +#define reg_marb_bp_rw_clients___dma4___bit 4 +#define reg_marb_bp_rw_clients___dma5___lsb 5 +#define reg_marb_bp_rw_clients___dma5___width 1 +#define reg_marb_bp_rw_clients___dma5___bit 5 +#define reg_marb_bp_rw_clients___dma6___lsb 6 +#define reg_marb_bp_rw_clients___dma6___width 1 +#define reg_marb_bp_rw_clients___dma6___bit 6 +#define reg_marb_bp_rw_clients___dma7___lsb 7 +#define reg_marb_bp_rw_clients___dma7___width 1 +#define reg_marb_bp_rw_clients___dma7___bit 7 +#define reg_marb_bp_rw_clients___dma8___lsb 8 +#define reg_marb_bp_rw_clients___dma8___width 1 +#define reg_marb_bp_rw_clients___dma8___bit 8 +#define reg_marb_bp_rw_clients___dma9___lsb 9 +#define reg_marb_bp_rw_clients___dma9___width 1 +#define reg_marb_bp_rw_clients___dma9___bit 9 +#define reg_marb_bp_rw_clients___cpui___lsb 10 +#define reg_marb_bp_rw_clients___cpui___width 1 +#define reg_marb_bp_rw_clients___cpui___bit 10 +#define reg_marb_bp_rw_clients___cpud___lsb 11 +#define reg_marb_bp_rw_clients___cpud___width 1 +#define reg_marb_bp_rw_clients___cpud___bit 11 +#define reg_marb_bp_rw_clients___iop___lsb 12 +#define reg_marb_bp_rw_clients___iop___width 1 +#define reg_marb_bp_rw_clients___iop___bit 12 +#define reg_marb_bp_rw_clients___slave___lsb 13 +#define reg_marb_bp_rw_clients___slave___width 1 +#define reg_marb_bp_rw_clients___slave___bit 13 +#define reg_marb_bp_rw_clients_offset 12 + +/* Register rw_options, scope marb_bp, type rw */ +#define reg_marb_bp_rw_options___wrap___lsb 0 +#define reg_marb_bp_rw_options___wrap___width 1 +#define reg_marb_bp_rw_options___wrap___bit 0 +#define reg_marb_bp_rw_options_offset 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_addr_offset 20 + +/* Register r_brk_op, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_op___rd___lsb 0 +#define reg_marb_bp_r_brk_op___rd___width 1 +#define reg_marb_bp_r_brk_op___rd___bit 0 +#define reg_marb_bp_r_brk_op___wr___lsb 1 +#define reg_marb_bp_r_brk_op___wr___width 1 +#define reg_marb_bp_r_brk_op___wr___bit 1 +#define reg_marb_bp_r_brk_op___rd_excl___lsb 2 +#define reg_marb_bp_r_brk_op___rd_excl___width 1 +#define reg_marb_bp_r_brk_op___rd_excl___bit 2 +#define reg_marb_bp_r_brk_op___pri_wr___lsb 3 +#define reg_marb_bp_r_brk_op___pri_wr___width 1 +#define reg_marb_bp_r_brk_op___pri_wr___bit 3 +#define reg_marb_bp_r_brk_op___us_rd___lsb 4 +#define reg_marb_bp_r_brk_op___us_rd___width 1 +#define reg_marb_bp_r_brk_op___us_rd___bit 4 +#define reg_marb_bp_r_brk_op___us_wr___lsb 5 +#define reg_marb_bp_r_brk_op___us_wr___width 1 +#define reg_marb_bp_r_brk_op___us_wr___bit 5 +#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 +#define reg_marb_bp_r_brk_op___us_rd_excl___width 1 +#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 +#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 +#define reg_marb_bp_r_brk_op___us_pri_wr___width 1 +#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 +#define reg_marb_bp_r_brk_op_offset 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_clients___dma0___lsb 0 +#define reg_marb_bp_r_brk_clients___dma0___width 1 +#define reg_marb_bp_r_brk_clients___dma0___bit 0 +#define reg_marb_bp_r_brk_clients___dma1___lsb 1 +#define reg_marb_bp_r_brk_clients___dma1___width 1 +#define reg_marb_bp_r_brk_clients___dma1___bit 1 +#define reg_marb_bp_r_brk_clients___dma2___lsb 2 +#define reg_marb_bp_r_brk_clients___dma2___width 1 +#define reg_marb_bp_r_brk_clients___dma2___bit 2 +#define reg_marb_bp_r_brk_clients___dma3___lsb 3 +#define reg_marb_bp_r_brk_clients___dma3___width 1 +#define reg_marb_bp_r_brk_clients___dma3___bit 3 +#define reg_marb_bp_r_brk_clients___dma4___lsb 4 +#define reg_marb_bp_r_brk_clients___dma4___width 1 +#define reg_marb_bp_r_brk_clients___dma4___bit 4 +#define reg_marb_bp_r_brk_clients___dma5___lsb 5 +#define reg_marb_bp_r_brk_clients___dma5___width 1 +#define reg_marb_bp_r_brk_clients___dma5___bit 5 +#define reg_marb_bp_r_brk_clients___dma6___lsb 6 +#define reg_marb_bp_r_brk_clients___dma6___width 1 +#define reg_marb_bp_r_brk_clients___dma6___bit 6 +#define reg_marb_bp_r_brk_clients___dma7___lsb 7 +#define reg_marb_bp_r_brk_clients___dma7___width 1 +#define reg_marb_bp_r_brk_clients___dma7___bit 7 +#define reg_marb_bp_r_brk_clients___dma8___lsb 8 +#define reg_marb_bp_r_brk_clients___dma8___width 1 +#define reg_marb_bp_r_brk_clients___dma8___bit 8 +#define reg_marb_bp_r_brk_clients___dma9___lsb 9 +#define reg_marb_bp_r_brk_clients___dma9___width 1 +#define reg_marb_bp_r_brk_clients___dma9___bit 9 +#define reg_marb_bp_r_brk_clients___cpui___lsb 10 +#define reg_marb_bp_r_brk_clients___cpui___width 1 +#define reg_marb_bp_r_brk_clients___cpui___bit 10 +#define reg_marb_bp_r_brk_clients___cpud___lsb 11 +#define reg_marb_bp_r_brk_clients___cpud___width 1 +#define reg_marb_bp_r_brk_clients___cpud___bit 11 +#define reg_marb_bp_r_brk_clients___iop___lsb 12 +#define reg_marb_bp_r_brk_clients___iop___width 1 +#define reg_marb_bp_r_brk_clients___iop___bit 12 +#define reg_marb_bp_r_brk_clients___slave___lsb 13 +#define reg_marb_bp_r_brk_clients___slave___width 1 +#define reg_marb_bp_r_brk_clients___slave___bit 13 +#define reg_marb_bp_r_brk_clients_offset 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_first_client___dma0___lsb 0 +#define reg_marb_bp_r_brk_first_client___dma0___width 1 +#define reg_marb_bp_r_brk_first_client___dma0___bit 0 +#define reg_marb_bp_r_brk_first_client___dma1___lsb 1 +#define reg_marb_bp_r_brk_first_client___dma1___width 1 +#define reg_marb_bp_r_brk_first_client___dma1___bit 1 +#define reg_marb_bp_r_brk_first_client___dma2___lsb 2 +#define reg_marb_bp_r_brk_first_client___dma2___width 1 +#define reg_marb_bp_r_brk_first_client___dma2___bit 2 +#define reg_marb_bp_r_brk_first_client___dma3___lsb 3 +#define reg_marb_bp_r_brk_first_client___dma3___width 1 +#define reg_marb_bp_r_brk_first_client___dma3___bit 3 +#define reg_marb_bp_r_brk_first_client___dma4___lsb 4 +#define reg_marb_bp_r_brk_first_client___dma4___width 1 +#define reg_marb_bp_r_brk_first_client___dma4___bit 4 +#define reg_marb_bp_r_brk_first_client___dma5___lsb 5 +#define reg_marb_bp_r_brk_first_client___dma5___width 1 +#define reg_marb_bp_r_brk_first_client___dma5___bit 5 +#define reg_marb_bp_r_brk_first_client___dma6___lsb 6 +#define reg_marb_bp_r_brk_first_client___dma6___width 1 +#define reg_marb_bp_r_brk_first_client___dma6___bit 6 +#define reg_marb_bp_r_brk_first_client___dma7___lsb 7 +#define reg_marb_bp_r_brk_first_client___dma7___width 1 +#define reg_marb_bp_r_brk_first_client___dma7___bit 7 +#define reg_marb_bp_r_brk_first_client___dma8___lsb 8 +#define reg_marb_bp_r_brk_first_client___dma8___width 1 +#define reg_marb_bp_r_brk_first_client___dma8___bit 8 +#define reg_marb_bp_r_brk_first_client___dma9___lsb 9 +#define reg_marb_bp_r_brk_first_client___dma9___width 1 +#define reg_marb_bp_r_brk_first_client___dma9___bit 9 +#define reg_marb_bp_r_brk_first_client___cpui___lsb 10 +#define reg_marb_bp_r_brk_first_client___cpui___width 1 +#define reg_marb_bp_r_brk_first_client___cpui___bit 10 +#define reg_marb_bp_r_brk_first_client___cpud___lsb 11 +#define reg_marb_bp_r_brk_first_client___cpud___width 1 +#define reg_marb_bp_r_brk_first_client___cpud___bit 11 +#define reg_marb_bp_r_brk_first_client___iop___lsb 12 +#define reg_marb_bp_r_brk_first_client___iop___width 1 +#define reg_marb_bp_r_brk_first_client___iop___bit 12 +#define reg_marb_bp_r_brk_first_client___slave___lsb 13 +#define reg_marb_bp_r_brk_first_client___slave___width 1 +#define reg_marb_bp_r_brk_first_client___slave___bit 13 +#define reg_marb_bp_r_brk_first_client_offset 32 + +/* Register r_brk_size, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_size_offset 36 + +/* Register rw_ack, scope marb_bp, type rw */ +#define reg_marb_bp_rw_ack_offset 40 + + +/* Constants */ +#define regk_marb_bp_no 0x00000000 +#define regk_marb_bp_rw_op_default 0x00000000 +#define regk_marb_bp_rw_options_default 0x00000000 +#define regk_marb_bp_yes 0x00000001 +#endif /* __marb_bp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h new file mode 100644 index 000000000000..505b7a16d878 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h @@ -0,0 +1,212 @@ +#ifndef __mmu_defs_asm_h +#define __mmu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/mmu/doc/mmu_regs.r + * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp + * last modfied: Mon Apr 11 17:03:20 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r + * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mm_cfg, scope mmu, type rw */ +#define reg_mmu_rw_mm_cfg___seg_0___lsb 0 +#define reg_mmu_rw_mm_cfg___seg_0___width 1 +#define reg_mmu_rw_mm_cfg___seg_0___bit 0 +#define reg_mmu_rw_mm_cfg___seg_1___lsb 1 +#define reg_mmu_rw_mm_cfg___seg_1___width 1 +#define reg_mmu_rw_mm_cfg___seg_1___bit 1 +#define reg_mmu_rw_mm_cfg___seg_2___lsb 2 +#define reg_mmu_rw_mm_cfg___seg_2___width 1 +#define reg_mmu_rw_mm_cfg___seg_2___bit 2 +#define reg_mmu_rw_mm_cfg___seg_3___lsb 3 +#define reg_mmu_rw_mm_cfg___seg_3___width 1 +#define reg_mmu_rw_mm_cfg___seg_3___bit 3 +#define reg_mmu_rw_mm_cfg___seg_4___lsb 4 +#define reg_mmu_rw_mm_cfg___seg_4___width 1 +#define reg_mmu_rw_mm_cfg___seg_4___bit 4 +#define reg_mmu_rw_mm_cfg___seg_5___lsb 5 +#define reg_mmu_rw_mm_cfg___seg_5___width 1 +#define reg_mmu_rw_mm_cfg___seg_5___bit 5 +#define reg_mmu_rw_mm_cfg___seg_6___lsb 6 +#define reg_mmu_rw_mm_cfg___seg_6___width 1 +#define reg_mmu_rw_mm_cfg___seg_6___bit 6 +#define reg_mmu_rw_mm_cfg___seg_7___lsb 7 +#define reg_mmu_rw_mm_cfg___seg_7___width 1 +#define reg_mmu_rw_mm_cfg___seg_7___bit 7 +#define reg_mmu_rw_mm_cfg___seg_8___lsb 8 +#define reg_mmu_rw_mm_cfg___seg_8___width 1 +#define reg_mmu_rw_mm_cfg___seg_8___bit 8 +#define reg_mmu_rw_mm_cfg___seg_9___lsb 9 +#define reg_mmu_rw_mm_cfg___seg_9___width 1 +#define reg_mmu_rw_mm_cfg___seg_9___bit 9 +#define reg_mmu_rw_mm_cfg___seg_a___lsb 10 +#define reg_mmu_rw_mm_cfg___seg_a___width 1 +#define reg_mmu_rw_mm_cfg___seg_a___bit 10 +#define reg_mmu_rw_mm_cfg___seg_b___lsb 11 +#define reg_mmu_rw_mm_cfg___seg_b___width 1 +#define reg_mmu_rw_mm_cfg___seg_b___bit 11 +#define reg_mmu_rw_mm_cfg___seg_c___lsb 12 +#define reg_mmu_rw_mm_cfg___seg_c___width 1 +#define reg_mmu_rw_mm_cfg___seg_c___bit 12 +#define reg_mmu_rw_mm_cfg___seg_d___lsb 13 +#define reg_mmu_rw_mm_cfg___seg_d___width 1 +#define reg_mmu_rw_mm_cfg___seg_d___bit 13 +#define reg_mmu_rw_mm_cfg___seg_e___lsb 14 +#define reg_mmu_rw_mm_cfg___seg_e___width 1 +#define reg_mmu_rw_mm_cfg___seg_e___bit 14 +#define reg_mmu_rw_mm_cfg___seg_f___lsb 15 +#define reg_mmu_rw_mm_cfg___seg_f___width 1 +#define reg_mmu_rw_mm_cfg___seg_f___bit 15 +#define reg_mmu_rw_mm_cfg___inv___lsb 16 +#define reg_mmu_rw_mm_cfg___inv___width 1 +#define reg_mmu_rw_mm_cfg___inv___bit 16 +#define reg_mmu_rw_mm_cfg___ex___lsb 17 +#define reg_mmu_rw_mm_cfg___ex___width 1 +#define reg_mmu_rw_mm_cfg___ex___bit 17 +#define reg_mmu_rw_mm_cfg___acc___lsb 18 +#define reg_mmu_rw_mm_cfg___acc___width 1 +#define reg_mmu_rw_mm_cfg___acc___bit 18 +#define reg_mmu_rw_mm_cfg___we___lsb 19 +#define reg_mmu_rw_mm_cfg___we___width 1 +#define reg_mmu_rw_mm_cfg___we___bit 19 +#define reg_mmu_rw_mm_cfg_offset 0 + +/* Register rw_mm_kbase_lo, scope mmu, type rw */ +#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 +#define reg_mmu_rw_mm_kbase_lo___base_0___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 +#define reg_mmu_rw_mm_kbase_lo___base_1___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 +#define reg_mmu_rw_mm_kbase_lo___base_2___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 +#define reg_mmu_rw_mm_kbase_lo___base_3___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 +#define reg_mmu_rw_mm_kbase_lo___base_4___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 +#define reg_mmu_rw_mm_kbase_lo___base_5___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 +#define reg_mmu_rw_mm_kbase_lo___base_6___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 +#define reg_mmu_rw_mm_kbase_lo___base_7___width 4 +#define reg_mmu_rw_mm_kbase_lo_offset 4 + +/* Register rw_mm_kbase_hi, scope mmu, type rw */ +#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 +#define reg_mmu_rw_mm_kbase_hi___base_8___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 +#define reg_mmu_rw_mm_kbase_hi___base_9___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 +#define reg_mmu_rw_mm_kbase_hi___base_a___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 +#define reg_mmu_rw_mm_kbase_hi___base_b___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 +#define reg_mmu_rw_mm_kbase_hi___base_c___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 +#define reg_mmu_rw_mm_kbase_hi___base_d___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 +#define reg_mmu_rw_mm_kbase_hi___base_e___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 +#define reg_mmu_rw_mm_kbase_hi___base_f___width 4 +#define reg_mmu_rw_mm_kbase_hi_offset 8 + +/* Register r_mm_cause, scope mmu, type r */ +#define reg_mmu_r_mm_cause___pid___lsb 0 +#define reg_mmu_r_mm_cause___pid___width 8 +#define reg_mmu_r_mm_cause___op___lsb 8 +#define reg_mmu_r_mm_cause___op___width 2 +#define reg_mmu_r_mm_cause___vpn___lsb 13 +#define reg_mmu_r_mm_cause___vpn___width 19 +#define reg_mmu_r_mm_cause_offset 12 + +/* Register rw_mm_tlb_sel, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 +#define reg_mmu_rw_mm_tlb_sel___idx___width 4 +#define reg_mmu_rw_mm_tlb_sel___set___lsb 4 +#define reg_mmu_rw_mm_tlb_sel___set___width 2 +#define reg_mmu_rw_mm_tlb_sel_offset 16 + +/* Register rw_mm_tlb_lo, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_lo___x___lsb 0 +#define reg_mmu_rw_mm_tlb_lo___x___width 1 +#define reg_mmu_rw_mm_tlb_lo___x___bit 0 +#define reg_mmu_rw_mm_tlb_lo___w___lsb 1 +#define reg_mmu_rw_mm_tlb_lo___w___width 1 +#define reg_mmu_rw_mm_tlb_lo___w___bit 1 +#define reg_mmu_rw_mm_tlb_lo___k___lsb 2 +#define reg_mmu_rw_mm_tlb_lo___k___width 1 +#define reg_mmu_rw_mm_tlb_lo___k___bit 2 +#define reg_mmu_rw_mm_tlb_lo___v___lsb 3 +#define reg_mmu_rw_mm_tlb_lo___v___width 1 +#define reg_mmu_rw_mm_tlb_lo___v___bit 3 +#define reg_mmu_rw_mm_tlb_lo___g___lsb 4 +#define reg_mmu_rw_mm_tlb_lo___g___width 1 +#define reg_mmu_rw_mm_tlb_lo___g___bit 4 +#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 +#define reg_mmu_rw_mm_tlb_lo___pfn___width 19 +#define reg_mmu_rw_mm_tlb_lo_offset 20 + +/* Register rw_mm_tlb_hi, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 +#define reg_mmu_rw_mm_tlb_hi___pid___width 8 +#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 +#define reg_mmu_rw_mm_tlb_hi___vpn___width 19 +#define reg_mmu_rw_mm_tlb_hi_offset 24 + + +/* Constants */ +#define regk_mmu_execute 0x00000000 +#define regk_mmu_flush 0x00000003 +#define regk_mmu_linear 0x00000001 +#define regk_mmu_no 0x00000000 +#define regk_mmu_off 0x00000000 +#define regk_mmu_on 0x00000001 +#define regk_mmu_page 0x00000000 +#define regk_mmu_read 0x00000001 +#define regk_mmu_write 0x00000002 +#define regk_mmu_yes 0x00000001 +#endif /* __mmu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h new file mode 100644 index 000000000000..339500bf3bc0 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h @@ -0,0 +1,7 @@ +#define RW_MM_CFG 0 +#define RW_MM_KBASE_LO 1 +#define RW_MM_KBASE_HI 2 +#define R_MM_CAUSE 3 +#define RW_MM_TLB_SEL 4 +#define RW_MM_TLB_LO 5 +#define RW_MM_TLB_HI 6 diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 000000000000..13c725e4c774 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h @@ -0,0 +1,632 @@ +#ifndef __pinmux_defs_asm_h +#define __pinmux_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_pa___pa0___lsb 0 +#define reg_pinmux_rw_pa___pa0___width 1 +#define reg_pinmux_rw_pa___pa0___bit 0 +#define reg_pinmux_rw_pa___pa1___lsb 1 +#define reg_pinmux_rw_pa___pa1___width 1 +#define reg_pinmux_rw_pa___pa1___bit 1 +#define reg_pinmux_rw_pa___pa2___lsb 2 +#define reg_pinmux_rw_pa___pa2___width 1 +#define reg_pinmux_rw_pa___pa2___bit 2 +#define reg_pinmux_rw_pa___pa3___lsb 3 +#define reg_pinmux_rw_pa___pa3___width 1 +#define reg_pinmux_rw_pa___pa3___bit 3 +#define reg_pinmux_rw_pa___pa4___lsb 4 +#define reg_pinmux_rw_pa___pa4___width 1 +#define reg_pinmux_rw_pa___pa4___bit 4 +#define reg_pinmux_rw_pa___pa5___lsb 5 +#define reg_pinmux_rw_pa___pa5___width 1 +#define reg_pinmux_rw_pa___pa5___bit 5 +#define reg_pinmux_rw_pa___pa6___lsb 6 +#define reg_pinmux_rw_pa___pa6___width 1 +#define reg_pinmux_rw_pa___pa6___bit 6 +#define reg_pinmux_rw_pa___pa7___lsb 7 +#define reg_pinmux_rw_pa___pa7___width 1 +#define reg_pinmux_rw_pa___pa7___bit 7 +#define reg_pinmux_rw_pa___csp2_n___lsb 8 +#define reg_pinmux_rw_pa___csp2_n___width 1 +#define reg_pinmux_rw_pa___csp2_n___bit 8 +#define reg_pinmux_rw_pa___csp3_n___lsb 9 +#define reg_pinmux_rw_pa___csp3_n___width 1 +#define reg_pinmux_rw_pa___csp3_n___bit 9 +#define reg_pinmux_rw_pa___csp5_n___lsb 10 +#define reg_pinmux_rw_pa___csp5_n___width 1 +#define reg_pinmux_rw_pa___csp5_n___bit 10 +#define reg_pinmux_rw_pa___csp6_n___lsb 11 +#define reg_pinmux_rw_pa___csp6_n___width 1 +#define reg_pinmux_rw_pa___csp6_n___bit 11 +#define reg_pinmux_rw_pa___hsh4___lsb 12 +#define reg_pinmux_rw_pa___hsh4___width 1 +#define reg_pinmux_rw_pa___hsh4___bit 12 +#define reg_pinmux_rw_pa___hsh5___lsb 13 +#define reg_pinmux_rw_pa___hsh5___width 1 +#define reg_pinmux_rw_pa___hsh5___bit 13 +#define reg_pinmux_rw_pa___hsh6___lsb 14 +#define reg_pinmux_rw_pa___hsh6___width 1 +#define reg_pinmux_rw_pa___hsh6___bit 14 +#define reg_pinmux_rw_pa___hsh7___lsb 15 +#define reg_pinmux_rw_pa___hsh7___width 1 +#define reg_pinmux_rw_pa___hsh7___bit 15 +#define reg_pinmux_rw_pa_offset 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +#define reg_pinmux_rw_hwprot___ser1___lsb 0 +#define reg_pinmux_rw_hwprot___ser1___width 1 +#define reg_pinmux_rw_hwprot___ser1___bit 0 +#define reg_pinmux_rw_hwprot___ser2___lsb 1 +#define reg_pinmux_rw_hwprot___ser2___width 1 +#define reg_pinmux_rw_hwprot___ser2___bit 1 +#define reg_pinmux_rw_hwprot___ser3___lsb 2 +#define reg_pinmux_rw_hwprot___ser3___width 1 +#define reg_pinmux_rw_hwprot___ser3___bit 2 +#define reg_pinmux_rw_hwprot___sser0___lsb 3 +#define reg_pinmux_rw_hwprot___sser0___width 1 +#define reg_pinmux_rw_hwprot___sser0___bit 3 +#define reg_pinmux_rw_hwprot___sser1___lsb 4 +#define reg_pinmux_rw_hwprot___sser1___width 1 +#define reg_pinmux_rw_hwprot___sser1___bit 4 +#define reg_pinmux_rw_hwprot___ata0___lsb 5 +#define reg_pinmux_rw_hwprot___ata0___width 1 +#define reg_pinmux_rw_hwprot___ata0___bit 5 +#define reg_pinmux_rw_hwprot___ata1___lsb 6 +#define reg_pinmux_rw_hwprot___ata1___width 1 +#define reg_pinmux_rw_hwprot___ata1___bit 6 +#define reg_pinmux_rw_hwprot___ata2___lsb 7 +#define reg_pinmux_rw_hwprot___ata2___width 1 +#define reg_pinmux_rw_hwprot___ata2___bit 7 +#define reg_pinmux_rw_hwprot___ata3___lsb 8 +#define reg_pinmux_rw_hwprot___ata3___width 1 +#define reg_pinmux_rw_hwprot___ata3___bit 8 +#define reg_pinmux_rw_hwprot___ata___lsb 9 +#define reg_pinmux_rw_hwprot___ata___width 1 +#define reg_pinmux_rw_hwprot___ata___bit 9 +#define reg_pinmux_rw_hwprot___eth1___lsb 10 +#define reg_pinmux_rw_hwprot___eth1___width 1 +#define reg_pinmux_rw_hwprot___eth1___bit 10 +#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 +#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 +#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 +#define reg_pinmux_rw_hwprot___timer___lsb 12 +#define reg_pinmux_rw_hwprot___timer___width 1 +#define reg_pinmux_rw_hwprot___timer___bit 12 +#define reg_pinmux_rw_hwprot___p21___lsb 13 +#define reg_pinmux_rw_hwprot___p21___width 1 +#define reg_pinmux_rw_hwprot___p21___bit 13 +#define reg_pinmux_rw_hwprot_offset 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_gio___pb0___lsb 0 +#define reg_pinmux_rw_pb_gio___pb0___width 1 +#define reg_pinmux_rw_pb_gio___pb0___bit 0 +#define reg_pinmux_rw_pb_gio___pb1___lsb 1 +#define reg_pinmux_rw_pb_gio___pb1___width 1 +#define reg_pinmux_rw_pb_gio___pb1___bit 1 +#define reg_pinmux_rw_pb_gio___pb2___lsb 2 +#define reg_pinmux_rw_pb_gio___pb2___width 1 +#define reg_pinmux_rw_pb_gio___pb2___bit 2 +#define reg_pinmux_rw_pb_gio___pb3___lsb 3 +#define reg_pinmux_rw_pb_gio___pb3___width 1 +#define reg_pinmux_rw_pb_gio___pb3___bit 3 +#define reg_pinmux_rw_pb_gio___pb4___lsb 4 +#define reg_pinmux_rw_pb_gio___pb4___width 1 +#define reg_pinmux_rw_pb_gio___pb4___bit 4 +#define reg_pinmux_rw_pb_gio___pb5___lsb 5 +#define reg_pinmux_rw_pb_gio___pb5___width 1 +#define reg_pinmux_rw_pb_gio___pb5___bit 5 +#define reg_pinmux_rw_pb_gio___pb6___lsb 6 +#define reg_pinmux_rw_pb_gio___pb6___width 1 +#define reg_pinmux_rw_pb_gio___pb6___bit 6 +#define reg_pinmux_rw_pb_gio___pb7___lsb 7 +#define reg_pinmux_rw_pb_gio___pb7___width 1 +#define reg_pinmux_rw_pb_gio___pb7___bit 7 +#define reg_pinmux_rw_pb_gio___pb8___lsb 8 +#define reg_pinmux_rw_pb_gio___pb8___width 1 +#define reg_pinmux_rw_pb_gio___pb8___bit 8 +#define reg_pinmux_rw_pb_gio___pb9___lsb 9 +#define reg_pinmux_rw_pb_gio___pb9___width 1 +#define reg_pinmux_rw_pb_gio___pb9___bit 9 +#define reg_pinmux_rw_pb_gio___pb10___lsb 10 +#define reg_pinmux_rw_pb_gio___pb10___width 1 +#define reg_pinmux_rw_pb_gio___pb10___bit 10 +#define reg_pinmux_rw_pb_gio___pb11___lsb 11 +#define reg_pinmux_rw_pb_gio___pb11___width 1 +#define reg_pinmux_rw_pb_gio___pb11___bit 11 +#define reg_pinmux_rw_pb_gio___pb12___lsb 12 +#define reg_pinmux_rw_pb_gio___pb12___width 1 +#define reg_pinmux_rw_pb_gio___pb12___bit 12 +#define reg_pinmux_rw_pb_gio___pb13___lsb 13 +#define reg_pinmux_rw_pb_gio___pb13___width 1 +#define reg_pinmux_rw_pb_gio___pb13___bit 13 +#define reg_pinmux_rw_pb_gio___pb14___lsb 14 +#define reg_pinmux_rw_pb_gio___pb14___width 1 +#define reg_pinmux_rw_pb_gio___pb14___bit 14 +#define reg_pinmux_rw_pb_gio___pb15___lsb 15 +#define reg_pinmux_rw_pb_gio___pb15___width 1 +#define reg_pinmux_rw_pb_gio___pb15___bit 15 +#define reg_pinmux_rw_pb_gio___pb16___lsb 16 +#define reg_pinmux_rw_pb_gio___pb16___width 1 +#define reg_pinmux_rw_pb_gio___pb16___bit 16 +#define reg_pinmux_rw_pb_gio___pb17___lsb 17 +#define reg_pinmux_rw_pb_gio___pb17___width 1 +#define reg_pinmux_rw_pb_gio___pb17___bit 17 +#define reg_pinmux_rw_pb_gio_offset 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_iop___pb0___lsb 0 +#define reg_pinmux_rw_pb_iop___pb0___width 1 +#define reg_pinmux_rw_pb_iop___pb0___bit 0 +#define reg_pinmux_rw_pb_iop___pb1___lsb 1 +#define reg_pinmux_rw_pb_iop___pb1___width 1 +#define reg_pinmux_rw_pb_iop___pb1___bit 1 +#define reg_pinmux_rw_pb_iop___pb2___lsb 2 +#define reg_pinmux_rw_pb_iop___pb2___width 1 +#define reg_pinmux_rw_pb_iop___pb2___bit 2 +#define reg_pinmux_rw_pb_iop___pb3___lsb 3 +#define reg_pinmux_rw_pb_iop___pb3___width 1 +#define reg_pinmux_rw_pb_iop___pb3___bit 3 +#define reg_pinmux_rw_pb_iop___pb4___lsb 4 +#define reg_pinmux_rw_pb_iop___pb4___width 1 +#define reg_pinmux_rw_pb_iop___pb4___bit 4 +#define reg_pinmux_rw_pb_iop___pb5___lsb 5 +#define reg_pinmux_rw_pb_iop___pb5___width 1 +#define reg_pinmux_rw_pb_iop___pb5___bit 5 +#define reg_pinmux_rw_pb_iop___pb6___lsb 6 +#define reg_pinmux_rw_pb_iop___pb6___width 1 +#define reg_pinmux_rw_pb_iop___pb6___bit 6 +#define reg_pinmux_rw_pb_iop___pb7___lsb 7 +#define reg_pinmux_rw_pb_iop___pb7___width 1 +#define reg_pinmux_rw_pb_iop___pb7___bit 7 +#define reg_pinmux_rw_pb_iop___pb8___lsb 8 +#define reg_pinmux_rw_pb_iop___pb8___width 1 +#define reg_pinmux_rw_pb_iop___pb8___bit 8 +#define reg_pinmux_rw_pb_iop___pb9___lsb 9 +#define reg_pinmux_rw_pb_iop___pb9___width 1 +#define reg_pinmux_rw_pb_iop___pb9___bit 9 +#define reg_pinmux_rw_pb_iop___pb10___lsb 10 +#define reg_pinmux_rw_pb_iop___pb10___width 1 +#define reg_pinmux_rw_pb_iop___pb10___bit 10 +#define reg_pinmux_rw_pb_iop___pb11___lsb 11 +#define reg_pinmux_rw_pb_iop___pb11___width 1 +#define reg_pinmux_rw_pb_iop___pb11___bit 11 +#define reg_pinmux_rw_pb_iop___pb12___lsb 12 +#define reg_pinmux_rw_pb_iop___pb12___width 1 +#define reg_pinmux_rw_pb_iop___pb12___bit 12 +#define reg_pinmux_rw_pb_iop___pb13___lsb 13 +#define reg_pinmux_rw_pb_iop___pb13___width 1 +#define reg_pinmux_rw_pb_iop___pb13___bit 13 +#define reg_pinmux_rw_pb_iop___pb14___lsb 14 +#define reg_pinmux_rw_pb_iop___pb14___width 1 +#define reg_pinmux_rw_pb_iop___pb14___bit 14 +#define reg_pinmux_rw_pb_iop___pb15___lsb 15 +#define reg_pinmux_rw_pb_iop___pb15___width 1 +#define reg_pinmux_rw_pb_iop___pb15___bit 15 +#define reg_pinmux_rw_pb_iop___pb16___lsb 16 +#define reg_pinmux_rw_pb_iop___pb16___width 1 +#define reg_pinmux_rw_pb_iop___pb16___bit 16 +#define reg_pinmux_rw_pb_iop___pb17___lsb 17 +#define reg_pinmux_rw_pb_iop___pb17___width 1 +#define reg_pinmux_rw_pb_iop___pb17___bit 17 +#define reg_pinmux_rw_pb_iop_offset 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_gio___pc0___lsb 0 +#define reg_pinmux_rw_pc_gio___pc0___width 1 +#define reg_pinmux_rw_pc_gio___pc0___bit 0 +#define reg_pinmux_rw_pc_gio___pc1___lsb 1 +#define reg_pinmux_rw_pc_gio___pc1___width 1 +#define reg_pinmux_rw_pc_gio___pc1___bit 1 +#define reg_pinmux_rw_pc_gio___pc2___lsb 2 +#define reg_pinmux_rw_pc_gio___pc2___width 1 +#define reg_pinmux_rw_pc_gio___pc2___bit 2 +#define reg_pinmux_rw_pc_gio___pc3___lsb 3 +#define reg_pinmux_rw_pc_gio___pc3___width 1 +#define reg_pinmux_rw_pc_gio___pc3___bit 3 +#define reg_pinmux_rw_pc_gio___pc4___lsb 4 +#define reg_pinmux_rw_pc_gio___pc4___width 1 +#define reg_pinmux_rw_pc_gio___pc4___bit 4 +#define reg_pinmux_rw_pc_gio___pc5___lsb 5 +#define reg_pinmux_rw_pc_gio___pc5___width 1 +#define reg_pinmux_rw_pc_gio___pc5___bit 5 +#define reg_pinmux_rw_pc_gio___pc6___lsb 6 +#define reg_pinmux_rw_pc_gio___pc6___width 1 +#define reg_pinmux_rw_pc_gio___pc6___bit 6 +#define reg_pinmux_rw_pc_gio___pc7___lsb 7 +#define reg_pinmux_rw_pc_gio___pc7___width 1 +#define reg_pinmux_rw_pc_gio___pc7___bit 7 +#define reg_pinmux_rw_pc_gio___pc8___lsb 8 +#define reg_pinmux_rw_pc_gio___pc8___width 1 +#define reg_pinmux_rw_pc_gio___pc8___bit 8 +#define reg_pinmux_rw_pc_gio___pc9___lsb 9 +#define reg_pinmux_rw_pc_gio___pc9___width 1 +#define reg_pinmux_rw_pc_gio___pc9___bit 9 +#define reg_pinmux_rw_pc_gio___pc10___lsb 10 +#define reg_pinmux_rw_pc_gio___pc10___width 1 +#define reg_pinmux_rw_pc_gio___pc10___bit 10 +#define reg_pinmux_rw_pc_gio___pc11___lsb 11 +#define reg_pinmux_rw_pc_gio___pc11___width 1 +#define reg_pinmux_rw_pc_gio___pc11___bit 11 +#define reg_pinmux_rw_pc_gio___pc12___lsb 12 +#define reg_pinmux_rw_pc_gio___pc12___width 1 +#define reg_pinmux_rw_pc_gio___pc12___bit 12 +#define reg_pinmux_rw_pc_gio___pc13___lsb 13 +#define reg_pinmux_rw_pc_gio___pc13___width 1 +#define reg_pinmux_rw_pc_gio___pc13___bit 13 +#define reg_pinmux_rw_pc_gio___pc14___lsb 14 +#define reg_pinmux_rw_pc_gio___pc14___width 1 +#define reg_pinmux_rw_pc_gio___pc14___bit 14 +#define reg_pinmux_rw_pc_gio___pc15___lsb 15 +#define reg_pinmux_rw_pc_gio___pc15___width 1 +#define reg_pinmux_rw_pc_gio___pc15___bit 15 +#define reg_pinmux_rw_pc_gio___pc16___lsb 16 +#define reg_pinmux_rw_pc_gio___pc16___width 1 +#define reg_pinmux_rw_pc_gio___pc16___bit 16 +#define reg_pinmux_rw_pc_gio___pc17___lsb 17 +#define reg_pinmux_rw_pc_gio___pc17___width 1 +#define reg_pinmux_rw_pc_gio___pc17___bit 17 +#define reg_pinmux_rw_pc_gio_offset 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_iop___pc0___lsb 0 +#define reg_pinmux_rw_pc_iop___pc0___width 1 +#define reg_pinmux_rw_pc_iop___pc0___bit 0 +#define reg_pinmux_rw_pc_iop___pc1___lsb 1 +#define reg_pinmux_rw_pc_iop___pc1___width 1 +#define reg_pinmux_rw_pc_iop___pc1___bit 1 +#define reg_pinmux_rw_pc_iop___pc2___lsb 2 +#define reg_pinmux_rw_pc_iop___pc2___width 1 +#define reg_pinmux_rw_pc_iop___pc2___bit 2 +#define reg_pinmux_rw_pc_iop___pc3___lsb 3 +#define reg_pinmux_rw_pc_iop___pc3___width 1 +#define reg_pinmux_rw_pc_iop___pc3___bit 3 +#define reg_pinmux_rw_pc_iop___pc4___lsb 4 +#define reg_pinmux_rw_pc_iop___pc4___width 1 +#define reg_pinmux_rw_pc_iop___pc4___bit 4 +#define reg_pinmux_rw_pc_iop___pc5___lsb 5 +#define reg_pinmux_rw_pc_iop___pc5___width 1 +#define reg_pinmux_rw_pc_iop___pc5___bit 5 +#define reg_pinmux_rw_pc_iop___pc6___lsb 6 +#define reg_pinmux_rw_pc_iop___pc6___width 1 +#define reg_pinmux_rw_pc_iop___pc6___bit 6 +#define reg_pinmux_rw_pc_iop___pc7___lsb 7 +#define reg_pinmux_rw_pc_iop___pc7___width 1 +#define reg_pinmux_rw_pc_iop___pc7___bit 7 +#define reg_pinmux_rw_pc_iop___pc8___lsb 8 +#define reg_pinmux_rw_pc_iop___pc8___width 1 +#define reg_pinmux_rw_pc_iop___pc8___bit 8 +#define reg_pinmux_rw_pc_iop___pc9___lsb 9 +#define reg_pinmux_rw_pc_iop___pc9___width 1 +#define reg_pinmux_rw_pc_iop___pc9___bit 9 +#define reg_pinmux_rw_pc_iop___pc10___lsb 10 +#define reg_pinmux_rw_pc_iop___pc10___width 1 +#define reg_pinmux_rw_pc_iop___pc10___bit 10 +#define reg_pinmux_rw_pc_iop___pc11___lsb 11 +#define reg_pinmux_rw_pc_iop___pc11___width 1 +#define reg_pinmux_rw_pc_iop___pc11___bit 11 +#define reg_pinmux_rw_pc_iop___pc12___lsb 12 +#define reg_pinmux_rw_pc_iop___pc12___width 1 +#define reg_pinmux_rw_pc_iop___pc12___bit 12 +#define reg_pinmux_rw_pc_iop___pc13___lsb 13 +#define reg_pinmux_rw_pc_iop___pc13___width 1 +#define reg_pinmux_rw_pc_iop___pc13___bit 13 +#define reg_pinmux_rw_pc_iop___pc14___lsb 14 +#define reg_pinmux_rw_pc_iop___pc14___width 1 +#define reg_pinmux_rw_pc_iop___pc14___bit 14 +#define reg_pinmux_rw_pc_iop___pc15___lsb 15 +#define reg_pinmux_rw_pc_iop___pc15___width 1 +#define reg_pinmux_rw_pc_iop___pc15___bit 15 +#define reg_pinmux_rw_pc_iop___pc16___lsb 16 +#define reg_pinmux_rw_pc_iop___pc16___width 1 +#define reg_pinmux_rw_pc_iop___pc16___bit 16 +#define reg_pinmux_rw_pc_iop___pc17___lsb 17 +#define reg_pinmux_rw_pc_iop___pc17___width 1 +#define reg_pinmux_rw_pc_iop___pc17___bit 17 +#define reg_pinmux_rw_pc_iop_offset 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_gio___pd0___lsb 0 +#define reg_pinmux_rw_pd_gio___pd0___width 1 +#define reg_pinmux_rw_pd_gio___pd0___bit 0 +#define reg_pinmux_rw_pd_gio___pd1___lsb 1 +#define reg_pinmux_rw_pd_gio___pd1___width 1 +#define reg_pinmux_rw_pd_gio___pd1___bit 1 +#define reg_pinmux_rw_pd_gio___pd2___lsb 2 +#define reg_pinmux_rw_pd_gio___pd2___width 1 +#define reg_pinmux_rw_pd_gio___pd2___bit 2 +#define reg_pinmux_rw_pd_gio___pd3___lsb 3 +#define reg_pinmux_rw_pd_gio___pd3___width 1 +#define reg_pinmux_rw_pd_gio___pd3___bit 3 +#define reg_pinmux_rw_pd_gio___pd4___lsb 4 +#define reg_pinmux_rw_pd_gio___pd4___width 1 +#define reg_pinmux_rw_pd_gio___pd4___bit 4 +#define reg_pinmux_rw_pd_gio___pd5___lsb 5 +#define reg_pinmux_rw_pd_gio___pd5___width 1 +#define reg_pinmux_rw_pd_gio___pd5___bit 5 +#define reg_pinmux_rw_pd_gio___pd6___lsb 6 +#define reg_pinmux_rw_pd_gio___pd6___width 1 +#define reg_pinmux_rw_pd_gio___pd6___bit 6 +#define reg_pinmux_rw_pd_gio___pd7___lsb 7 +#define reg_pinmux_rw_pd_gio___pd7___width 1 +#define reg_pinmux_rw_pd_gio___pd7___bit 7 +#define reg_pinmux_rw_pd_gio___pd8___lsb 8 +#define reg_pinmux_rw_pd_gio___pd8___width 1 +#define reg_pinmux_rw_pd_gio___pd8___bit 8 +#define reg_pinmux_rw_pd_gio___pd9___lsb 9 +#define reg_pinmux_rw_pd_gio___pd9___width 1 +#define reg_pinmux_rw_pd_gio___pd9___bit 9 +#define reg_pinmux_rw_pd_gio___pd10___lsb 10 +#define reg_pinmux_rw_pd_gio___pd10___width 1 +#define reg_pinmux_rw_pd_gio___pd10___bit 10 +#define reg_pinmux_rw_pd_gio___pd11___lsb 11 +#define reg_pinmux_rw_pd_gio___pd11___width 1 +#define reg_pinmux_rw_pd_gio___pd11___bit 11 +#define reg_pinmux_rw_pd_gio___pd12___lsb 12 +#define reg_pinmux_rw_pd_gio___pd12___width 1 +#define reg_pinmux_rw_pd_gio___pd12___bit 12 +#define reg_pinmux_rw_pd_gio___pd13___lsb 13 +#define reg_pinmux_rw_pd_gio___pd13___width 1 +#define reg_pinmux_rw_pd_gio___pd13___bit 13 +#define reg_pinmux_rw_pd_gio___pd14___lsb 14 +#define reg_pinmux_rw_pd_gio___pd14___width 1 +#define reg_pinmux_rw_pd_gio___pd14___bit 14 +#define reg_pinmux_rw_pd_gio___pd15___lsb 15 +#define reg_pinmux_rw_pd_gio___pd15___width 1 +#define reg_pinmux_rw_pd_gio___pd15___bit 15 +#define reg_pinmux_rw_pd_gio___pd16___lsb 16 +#define reg_pinmux_rw_pd_gio___pd16___width 1 +#define reg_pinmux_rw_pd_gio___pd16___bit 16 +#define reg_pinmux_rw_pd_gio___pd17___lsb 17 +#define reg_pinmux_rw_pd_gio___pd17___width 1 +#define reg_pinmux_rw_pd_gio___pd17___bit 17 +#define reg_pinmux_rw_pd_gio_offset 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_iop___pd0___lsb 0 +#define reg_pinmux_rw_pd_iop___pd0___width 1 +#define reg_pinmux_rw_pd_iop___pd0___bit 0 +#define reg_pinmux_rw_pd_iop___pd1___lsb 1 +#define reg_pinmux_rw_pd_iop___pd1___width 1 +#define reg_pinmux_rw_pd_iop___pd1___bit 1 +#define reg_pinmux_rw_pd_iop___pd2___lsb 2 +#define reg_pinmux_rw_pd_iop___pd2___width 1 +#define reg_pinmux_rw_pd_iop___pd2___bit 2 +#define reg_pinmux_rw_pd_iop___pd3___lsb 3 +#define reg_pinmux_rw_pd_iop___pd3___width 1 +#define reg_pinmux_rw_pd_iop___pd3___bit 3 +#define reg_pinmux_rw_pd_iop___pd4___lsb 4 +#define reg_pinmux_rw_pd_iop___pd4___width 1 +#define reg_pinmux_rw_pd_iop___pd4___bit 4 +#define reg_pinmux_rw_pd_iop___pd5___lsb 5 +#define reg_pinmux_rw_pd_iop___pd5___width 1 +#define reg_pinmux_rw_pd_iop___pd5___bit 5 +#define reg_pinmux_rw_pd_iop___pd6___lsb 6 +#define reg_pinmux_rw_pd_iop___pd6___width 1 +#define reg_pinmux_rw_pd_iop___pd6___bit 6 +#define reg_pinmux_rw_pd_iop___pd7___lsb 7 +#define reg_pinmux_rw_pd_iop___pd7___width 1 +#define reg_pinmux_rw_pd_iop___pd7___bit 7 +#define reg_pinmux_rw_pd_iop___pd8___lsb 8 +#define reg_pinmux_rw_pd_iop___pd8___width 1 +#define reg_pinmux_rw_pd_iop___pd8___bit 8 +#define reg_pinmux_rw_pd_iop___pd9___lsb 9 +#define reg_pinmux_rw_pd_iop___pd9___width 1 +#define reg_pinmux_rw_pd_iop___pd9___bit 9 +#define reg_pinmux_rw_pd_iop___pd10___lsb 10 +#define reg_pinmux_rw_pd_iop___pd10___width 1 +#define reg_pinmux_rw_pd_iop___pd10___bit 10 +#define reg_pinmux_rw_pd_iop___pd11___lsb 11 +#define reg_pinmux_rw_pd_iop___pd11___width 1 +#define reg_pinmux_rw_pd_iop___pd11___bit 11 +#define reg_pinmux_rw_pd_iop___pd12___lsb 12 +#define reg_pinmux_rw_pd_iop___pd12___width 1 +#define reg_pinmux_rw_pd_iop___pd12___bit 12 +#define reg_pinmux_rw_pd_iop___pd13___lsb 13 +#define reg_pinmux_rw_pd_iop___pd13___width 1 +#define reg_pinmux_rw_pd_iop___pd13___bit 13 +#define reg_pinmux_rw_pd_iop___pd14___lsb 14 +#define reg_pinmux_rw_pd_iop___pd14___width 1 +#define reg_pinmux_rw_pd_iop___pd14___bit 14 +#define reg_pinmux_rw_pd_iop___pd15___lsb 15 +#define reg_pinmux_rw_pd_iop___pd15___width 1 +#define reg_pinmux_rw_pd_iop___pd15___bit 15 +#define reg_pinmux_rw_pd_iop___pd16___lsb 16 +#define reg_pinmux_rw_pd_iop___pd16___width 1 +#define reg_pinmux_rw_pd_iop___pd16___bit 16 +#define reg_pinmux_rw_pd_iop___pd17___lsb 17 +#define reg_pinmux_rw_pd_iop___pd17___width 1 +#define reg_pinmux_rw_pd_iop___pd17___bit 17 +#define reg_pinmux_rw_pd_iop_offset 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_gio___pe0___lsb 0 +#define reg_pinmux_rw_pe_gio___pe0___width 1 +#define reg_pinmux_rw_pe_gio___pe0___bit 0 +#define reg_pinmux_rw_pe_gio___pe1___lsb 1 +#define reg_pinmux_rw_pe_gio___pe1___width 1 +#define reg_pinmux_rw_pe_gio___pe1___bit 1 +#define reg_pinmux_rw_pe_gio___pe2___lsb 2 +#define reg_pinmux_rw_pe_gio___pe2___width 1 +#define reg_pinmux_rw_pe_gio___pe2___bit 2 +#define reg_pinmux_rw_pe_gio___pe3___lsb 3 +#define reg_pinmux_rw_pe_gio___pe3___width 1 +#define reg_pinmux_rw_pe_gio___pe3___bit 3 +#define reg_pinmux_rw_pe_gio___pe4___lsb 4 +#define reg_pinmux_rw_pe_gio___pe4___width 1 +#define reg_pinmux_rw_pe_gio___pe4___bit 4 +#define reg_pinmux_rw_pe_gio___pe5___lsb 5 +#define reg_pinmux_rw_pe_gio___pe5___width 1 +#define reg_pinmux_rw_pe_gio___pe5___bit 5 +#define reg_pinmux_rw_pe_gio___pe6___lsb 6 +#define reg_pinmux_rw_pe_gio___pe6___width 1 +#define reg_pinmux_rw_pe_gio___pe6___bit 6 +#define reg_pinmux_rw_pe_gio___pe7___lsb 7 +#define reg_pinmux_rw_pe_gio___pe7___width 1 +#define reg_pinmux_rw_pe_gio___pe7___bit 7 +#define reg_pinmux_rw_pe_gio___pe8___lsb 8 +#define reg_pinmux_rw_pe_gio___pe8___width 1 +#define reg_pinmux_rw_pe_gio___pe8___bit 8 +#define reg_pinmux_rw_pe_gio___pe9___lsb 9 +#define reg_pinmux_rw_pe_gio___pe9___width 1 +#define reg_pinmux_rw_pe_gio___pe9___bit 9 +#define reg_pinmux_rw_pe_gio___pe10___lsb 10 +#define reg_pinmux_rw_pe_gio___pe10___width 1 +#define reg_pinmux_rw_pe_gio___pe10___bit 10 +#define reg_pinmux_rw_pe_gio___pe11___lsb 11 +#define reg_pinmux_rw_pe_gio___pe11___width 1 +#define reg_pinmux_rw_pe_gio___pe11___bit 11 +#define reg_pinmux_rw_pe_gio___pe12___lsb 12 +#define reg_pinmux_rw_pe_gio___pe12___width 1 +#define reg_pinmux_rw_pe_gio___pe12___bit 12 +#define reg_pinmux_rw_pe_gio___pe13___lsb 13 +#define reg_pinmux_rw_pe_gio___pe13___width 1 +#define reg_pinmux_rw_pe_gio___pe13___bit 13 +#define reg_pinmux_rw_pe_gio___pe14___lsb 14 +#define reg_pinmux_rw_pe_gio___pe14___width 1 +#define reg_pinmux_rw_pe_gio___pe14___bit 14 +#define reg_pinmux_rw_pe_gio___pe15___lsb 15 +#define reg_pinmux_rw_pe_gio___pe15___width 1 +#define reg_pinmux_rw_pe_gio___pe15___bit 15 +#define reg_pinmux_rw_pe_gio___pe16___lsb 16 +#define reg_pinmux_rw_pe_gio___pe16___width 1 +#define reg_pinmux_rw_pe_gio___pe16___bit 16 +#define reg_pinmux_rw_pe_gio___pe17___lsb 17 +#define reg_pinmux_rw_pe_gio___pe17___width 1 +#define reg_pinmux_rw_pe_gio___pe17___bit 17 +#define reg_pinmux_rw_pe_gio_offset 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_iop___pe0___lsb 0 +#define reg_pinmux_rw_pe_iop___pe0___width 1 +#define reg_pinmux_rw_pe_iop___pe0___bit 0 +#define reg_pinmux_rw_pe_iop___pe1___lsb 1 +#define reg_pinmux_rw_pe_iop___pe1___width 1 +#define reg_pinmux_rw_pe_iop___pe1___bit 1 +#define reg_pinmux_rw_pe_iop___pe2___lsb 2 +#define reg_pinmux_rw_pe_iop___pe2___width 1 +#define reg_pinmux_rw_pe_iop___pe2___bit 2 +#define reg_pinmux_rw_pe_iop___pe3___lsb 3 +#define reg_pinmux_rw_pe_iop___pe3___width 1 +#define reg_pinmux_rw_pe_iop___pe3___bit 3 +#define reg_pinmux_rw_pe_iop___pe4___lsb 4 +#define reg_pinmux_rw_pe_iop___pe4___width 1 +#define reg_pinmux_rw_pe_iop___pe4___bit 4 +#define reg_pinmux_rw_pe_iop___pe5___lsb 5 +#define reg_pinmux_rw_pe_iop___pe5___width 1 +#define reg_pinmux_rw_pe_iop___pe5___bit 5 +#define reg_pinmux_rw_pe_iop___pe6___lsb 6 +#define reg_pinmux_rw_pe_iop___pe6___width 1 +#define reg_pinmux_rw_pe_iop___pe6___bit 6 +#define reg_pinmux_rw_pe_iop___pe7___lsb 7 +#define reg_pinmux_rw_pe_iop___pe7___width 1 +#define reg_pinmux_rw_pe_iop___pe7___bit 7 +#define reg_pinmux_rw_pe_iop___pe8___lsb 8 +#define reg_pinmux_rw_pe_iop___pe8___width 1 +#define reg_pinmux_rw_pe_iop___pe8___bit 8 +#define reg_pinmux_rw_pe_iop___pe9___lsb 9 +#define reg_pinmux_rw_pe_iop___pe9___width 1 +#define reg_pinmux_rw_pe_iop___pe9___bit 9 +#define reg_pinmux_rw_pe_iop___pe10___lsb 10 +#define reg_pinmux_rw_pe_iop___pe10___width 1 +#define reg_pinmux_rw_pe_iop___pe10___bit 10 +#define reg_pinmux_rw_pe_iop___pe11___lsb 11 +#define reg_pinmux_rw_pe_iop___pe11___width 1 +#define reg_pinmux_rw_pe_iop___pe11___bit 11 +#define reg_pinmux_rw_pe_iop___pe12___lsb 12 +#define reg_pinmux_rw_pe_iop___pe12___width 1 +#define reg_pinmux_rw_pe_iop___pe12___bit 12 +#define reg_pinmux_rw_pe_iop___pe13___lsb 13 +#define reg_pinmux_rw_pe_iop___pe13___width 1 +#define reg_pinmux_rw_pe_iop___pe13___bit 13 +#define reg_pinmux_rw_pe_iop___pe14___lsb 14 +#define reg_pinmux_rw_pe_iop___pe14___width 1 +#define reg_pinmux_rw_pe_iop___pe14___bit 14 +#define reg_pinmux_rw_pe_iop___pe15___lsb 15 +#define reg_pinmux_rw_pe_iop___pe15___width 1 +#define reg_pinmux_rw_pe_iop___pe15___bit 15 +#define reg_pinmux_rw_pe_iop___pe16___lsb 16 +#define reg_pinmux_rw_pe_iop___pe16___width 1 +#define reg_pinmux_rw_pe_iop___pe16___bit 16 +#define reg_pinmux_rw_pe_iop___pe17___lsb 17 +#define reg_pinmux_rw_pe_iop___pe17___width 1 +#define reg_pinmux_rw_pe_iop___pe17___bit 17 +#define reg_pinmux_rw_pe_iop_offset 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 +#define reg_pinmux_rw_usb_phy___en_usb0___width 1 +#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 +#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 +#define reg_pinmux_rw_usb_phy___en_usb1___width 1 +#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 +#define reg_pinmux_rw_usb_phy_offset 40 + + +/* Constants */ +#define regk_pinmux_no 0x00000000 +#define regk_pinmux_rw_hwprot_default 0x00000000 +#define regk_pinmux_rw_pa_default 0x00000000 +#define regk_pinmux_rw_pb_gio_default 0x00000000 +#define regk_pinmux_rw_pb_iop_default 0x00000000 +#define regk_pinmux_rw_pc_gio_default 0x00000000 +#define regk_pinmux_rw_pc_iop_default 0x00000000 +#define regk_pinmux_rw_pd_gio_default 0x00000000 +#define regk_pinmux_rw_pd_iop_default 0x00000000 +#define regk_pinmux_rw_pe_gio_default 0x00000000 +#define regk_pinmux_rw_pe_iop_default 0x00000000 +#define regk_pinmux_rw_usb_phy_default 0x00000000 +#define regk_pinmux_yes 0x00000001 +#endif /* __pinmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h new file mode 100644 index 000000000000..76959b70cd2c --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h @@ -0,0 +1,96 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: ../../mod/fakereg.rmap + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * last modified: Wed Feb 11 20:53:25 2004 + * file: ../../rtl/global.rmap + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * last modified: Mon Aug 18 17:08:23 2003 + * file: ../../mod/modreg.rmap + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * last modified: Fri Feb 20 16:40:04 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap + * id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +#define regi_artpec_mod 0xb7044000 +#define regi_ata 0xb0032000 +#define regi_ata_mod 0xb7006000 +#define regi_barber 0xb701a000 +#define regi_bif_core 0xb0014000 +#define regi_bif_dma 0xb0016000 +#define regi_bif_slave 0xb0018000 +#define regi_bif_slave_ext 0xac000000 +#define regi_bus_master 0xb703c000 +#define regi_config 0xb003c000 +#define regi_dma0 0xb0000000 +#define regi_dma1 0xb0002000 +#define regi_dma2 0xb0004000 +#define regi_dma3 0xb0006000 +#define regi_dma4 0xb0008000 +#define regi_dma5 0xb000a000 +#define regi_dma6 0xb000c000 +#define regi_dma7 0xb000e000 +#define regi_dma8 0xb0010000 +#define regi_dma9 0xb0012000 +#define regi_eth0 0xb0034000 +#define regi_eth1 0xb0036000 +#define regi_eth_mod 0xb7004000 +#define regi_eth_mod1 0xb701c000 +#define regi_eth_strmod 0xb7008000 +#define regi_eth_strmod1 0xb7032000 +#define regi_ext_dma 0xb703a000 +#define regi_ext_mem 0xb7046000 +#define regi_gen_io 0xb7016000 +#define regi_gio 0xb001a000 +#define regi_hook 0xb7000000 +#define regi_iop 0xb0020000 +#define regi_irq 0xb001c000 +#define regi_irq_nmi 0xb701e000 +#define regi_marb 0xb003e000 +#define regi_marb_bp0 0xb003e240 +#define regi_marb_bp1 0xb003e280 +#define regi_marb_bp2 0xb003e2c0 +#define regi_marb_bp3 0xb003e300 +#define regi_nand_mod 0xb7014000 +#define regi_p21 0xb002e000 +#define regi_p21_mod 0xb7042000 +#define regi_pci_mod 0xb7010000 +#define regi_pin_test 0xb7018000 +#define regi_pinmux 0xb0038000 +#define regi_sdram_chk 0xb703e000 +#define regi_sdram_mod 0xb7012000 +#define regi_ser0 0xb0026000 +#define regi_ser1 0xb0028000 +#define regi_ser2 0xb002a000 +#define regi_ser3 0xb002c000 +#define regi_ser_mod0 0xb7020000 +#define regi_ser_mod1 0xb7022000 +#define regi_ser_mod2 0xb7024000 +#define regi_ser_mod3 0xb7026000 +#define regi_smif_stat 0xb700e000 +#define regi_sser0 0xb0022000 +#define regi_sser1 0xb0024000 +#define regi_sser_mod0 0xb700a000 +#define regi_sser_mod1 0xb700c000 +#define regi_strcop 0xb0030000 +#define regi_strmux 0xb003a000 +#define regi_strmux_tst 0xb7040000 +#define regi_tap 0xb7002000 +#define regi_timer 0xb001e000 +#define regi_timer_mod 0xb7034000 +#define regi_trace 0xb0040000 +#define regi_usb0 0xb7028000 +#define regi_usb1 0xb702a000 +#define regi_usb2 0xb702c000 +#define regi_usb3 0xb702e000 +#define regi_usb_dev 0xb7030000 +#define regi_utmi_mod0 0xb7036000 +#define regi_utmi_mod1 0xb7038000 +#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h new file mode 100644 index 000000000000..10246f49fb28 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h @@ -0,0 +1,142 @@ +#ifndef __rt_trace_defs_asm_h +#define __rt_trace_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/rt_trace/rtl/rt_regs.r + * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp + * last modfied: Mon Apr 11 16:09:14 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r + * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope rt_trace, type rw */ +#define reg_rt_trace_rw_cfg___en___lsb 0 +#define reg_rt_trace_rw_cfg___en___width 1 +#define reg_rt_trace_rw_cfg___en___bit 0 +#define reg_rt_trace_rw_cfg___mode___lsb 1 +#define reg_rt_trace_rw_cfg___mode___width 1 +#define reg_rt_trace_rw_cfg___mode___bit 1 +#define reg_rt_trace_rw_cfg___owner___lsb 2 +#define reg_rt_trace_rw_cfg___owner___width 1 +#define reg_rt_trace_rw_cfg___owner___bit 2 +#define reg_rt_trace_rw_cfg___wp___lsb 3 +#define reg_rt_trace_rw_cfg___wp___width 1 +#define reg_rt_trace_rw_cfg___wp___bit 3 +#define reg_rt_trace_rw_cfg___stall___lsb 4 +#define reg_rt_trace_rw_cfg___stall___width 1 +#define reg_rt_trace_rw_cfg___stall___bit 4 +#define reg_rt_trace_rw_cfg___wp_start___lsb 8 +#define reg_rt_trace_rw_cfg___wp_start___width 7 +#define reg_rt_trace_rw_cfg___wp_stop___lsb 16 +#define reg_rt_trace_rw_cfg___wp_stop___width 7 +#define reg_rt_trace_rw_cfg_offset 0 + +/* Register rw_tap_ctrl, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 +#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 +#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 +#define reg_rt_trace_rw_tap_ctrl_offset 4 + +/* Register r_tap_stat, scope rt_trace, type r */ +#define reg_rt_trace_r_tap_stat___dav___lsb 0 +#define reg_rt_trace_r_tap_stat___dav___width 1 +#define reg_rt_trace_r_tap_stat___dav___bit 0 +#define reg_rt_trace_r_tap_stat___empty___lsb 1 +#define reg_rt_trace_r_tap_stat___empty___width 1 +#define reg_rt_trace_r_tap_stat___empty___bit 1 +#define reg_rt_trace_r_tap_stat_offset 8 + +/* Register rw_tap_data, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_data_offset 12 + +/* Register rw_tap_hdata, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_hdata___op___lsb 0 +#define reg_rt_trace_rw_tap_hdata___op___width 4 +#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 +#define reg_rt_trace_rw_tap_hdata___sub_op___width 4 +#define reg_rt_trace_rw_tap_hdata_offset 16 + +/* Register r_redir, scope rt_trace, type r */ +#define reg_rt_trace_r_redir_offset 20 + + +/* Constants */ +#define regk_rt_trace_brk 0x0000000c +#define regk_rt_trace_dbg 0x00000003 +#define regk_rt_trace_dbgdi 0x00000004 +#define regk_rt_trace_dbgdo 0x00000005 +#define regk_rt_trace_gmode 0x00000000 +#define regk_rt_trace_no 0x00000000 +#define regk_rt_trace_nop 0x00000000 +#define regk_rt_trace_normal 0x00000000 +#define regk_rt_trace_rdmem 0x00000007 +#define regk_rt_trace_rdmemb 0x00000009 +#define regk_rt_trace_rdpreg 0x00000002 +#define regk_rt_trace_rdreg 0x00000001 +#define regk_rt_trace_rdsreg 0x00000003 +#define regk_rt_trace_redir 0x00000006 +#define regk_rt_trace_ret 0x0000000b +#define regk_rt_trace_rw_cfg_default 0x00000000 +#define regk_rt_trace_trcfg 0x00000001 +#define regk_rt_trace_wp 0x00000001 +#define regk_rt_trace_wp0 0x00000001 +#define regk_rt_trace_wp1 0x00000002 +#define regk_rt_trace_wp2 0x00000004 +#define regk_rt_trace_wp3 0x00000008 +#define regk_rt_trace_wp4 0x00000010 +#define regk_rt_trace_wp5 0x00000020 +#define regk_rt_trace_wp6 0x00000040 +#define regk_rt_trace_wrmem 0x00000008 +#define regk_rt_trace_wrmemb 0x0000000a +#define regk_rt_trace_wrpreg 0x00000005 +#define regk_rt_trace_wrreg 0x00000004 +#define regk_rt_trace_wrsreg 0x00000006 +#define regk_rt_trace_yes 0x00000001 +#endif /* __rt_trace_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h new file mode 100644 index 000000000000..4a2808bdf390 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h @@ -0,0 +1,359 @@ +#ifndef __ser_defs_asm_h +#define __ser_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/ser/rtl/ser_regs.r + * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp + * last modfied: Mon Apr 11 16:09:21 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r + * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tr_ctrl, scope ser, type rw */ +#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 +#define reg_ser_rw_tr_ctrl___base_freq___width 3 +#define reg_ser_rw_tr_ctrl___en___lsb 3 +#define reg_ser_rw_tr_ctrl___en___width 1 +#define reg_ser_rw_tr_ctrl___en___bit 3 +#define reg_ser_rw_tr_ctrl___par___lsb 4 +#define reg_ser_rw_tr_ctrl___par___width 2 +#define reg_ser_rw_tr_ctrl___par_en___lsb 6 +#define reg_ser_rw_tr_ctrl___par_en___width 1 +#define reg_ser_rw_tr_ctrl___par_en___bit 6 +#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 +#define reg_ser_rw_tr_ctrl___data_bits___width 1 +#define reg_ser_rw_tr_ctrl___data_bits___bit 7 +#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 +#define reg_ser_rw_tr_ctrl___stop_bits___width 1 +#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 +#define reg_ser_rw_tr_ctrl___stop___lsb 9 +#define reg_ser_rw_tr_ctrl___stop___width 1 +#define reg_ser_rw_tr_ctrl___stop___bit 9 +#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 +#define reg_ser_rw_tr_ctrl___rts_delay___width 3 +#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 +#define reg_ser_rw_tr_ctrl___rts_setup___width 1 +#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 +#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 +#define reg_ser_rw_tr_ctrl___auto_rts___width 1 +#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 +#define reg_ser_rw_tr_ctrl___txd___lsb 15 +#define reg_ser_rw_tr_ctrl___txd___width 1 +#define reg_ser_rw_tr_ctrl___txd___bit 15 +#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 +#define reg_ser_rw_tr_ctrl___auto_cts___width 1 +#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 +#define reg_ser_rw_tr_ctrl_offset 0 + +/* Register rw_tr_dma_en, scope ser, type rw */ +#define reg_ser_rw_tr_dma_en___en___lsb 0 +#define reg_ser_rw_tr_dma_en___en___width 1 +#define reg_ser_rw_tr_dma_en___en___bit 0 +#define reg_ser_rw_tr_dma_en_offset 4 + +/* Register rw_rec_ctrl, scope ser, type rw */ +#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 +#define reg_ser_rw_rec_ctrl___base_freq___width 3 +#define reg_ser_rw_rec_ctrl___en___lsb 3 +#define reg_ser_rw_rec_ctrl___en___width 1 +#define reg_ser_rw_rec_ctrl___en___bit 3 +#define reg_ser_rw_rec_ctrl___par___lsb 4 +#define reg_ser_rw_rec_ctrl___par___width 2 +#define reg_ser_rw_rec_ctrl___par_en___lsb 6 +#define reg_ser_rw_rec_ctrl___par_en___width 1 +#define reg_ser_rw_rec_ctrl___par_en___bit 6 +#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 +#define reg_ser_rw_rec_ctrl___data_bits___width 1 +#define reg_ser_rw_rec_ctrl___data_bits___bit 7 +#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 +#define reg_ser_rw_rec_ctrl___dma_mode___width 1 +#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 +#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 +#define reg_ser_rw_rec_ctrl___dma_err___width 1 +#define reg_ser_rw_rec_ctrl___dma_err___bit 9 +#define reg_ser_rw_rec_ctrl___sampling___lsb 10 +#define reg_ser_rw_rec_ctrl___sampling___width 1 +#define reg_ser_rw_rec_ctrl___sampling___bit 10 +#define reg_ser_rw_rec_ctrl___timeout___lsb 11 +#define reg_ser_rw_rec_ctrl___timeout___width 3 +#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 +#define reg_ser_rw_rec_ctrl___auto_eop___width 1 +#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 +#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 +#define reg_ser_rw_rec_ctrl___half_duplex___width 1 +#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 +#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 +#define reg_ser_rw_rec_ctrl___rts_n___width 1 +#define reg_ser_rw_rec_ctrl___rts_n___bit 16 +#define reg_ser_rw_rec_ctrl___loopback___lsb 17 +#define reg_ser_rw_rec_ctrl___loopback___width 1 +#define reg_ser_rw_rec_ctrl___loopback___bit 17 +#define reg_ser_rw_rec_ctrl_offset 8 + +/* Register rw_tr_baud_div, scope ser, type rw */ +#define reg_ser_rw_tr_baud_div___div___lsb 0 +#define reg_ser_rw_tr_baud_div___div___width 16 +#define reg_ser_rw_tr_baud_div_offset 12 + +/* Register rw_rec_baud_div, scope ser, type rw */ +#define reg_ser_rw_rec_baud_div___div___lsb 0 +#define reg_ser_rw_rec_baud_div___div___width 16 +#define reg_ser_rw_rec_baud_div_offset 16 + +/* Register rw_xoff, scope ser, type rw */ +#define reg_ser_rw_xoff___chr___lsb 0 +#define reg_ser_rw_xoff___chr___width 8 +#define reg_ser_rw_xoff___automatic___lsb 8 +#define reg_ser_rw_xoff___automatic___width 1 +#define reg_ser_rw_xoff___automatic___bit 8 +#define reg_ser_rw_xoff_offset 20 + +/* Register rw_xoff_clr, scope ser, type rw */ +#define reg_ser_rw_xoff_clr___clr___lsb 0 +#define reg_ser_rw_xoff_clr___clr___width 1 +#define reg_ser_rw_xoff_clr___clr___bit 0 +#define reg_ser_rw_xoff_clr_offset 24 + +/* Register rw_dout, scope ser, type rw */ +#define reg_ser_rw_dout___data___lsb 0 +#define reg_ser_rw_dout___data___width 8 +#define reg_ser_rw_dout_offset 28 + +/* Register rs_stat_din, scope ser, type rs */ +#define reg_ser_rs_stat_din___data___lsb 0 +#define reg_ser_rs_stat_din___data___width 8 +#define reg_ser_rs_stat_din___dav___lsb 16 +#define reg_ser_rs_stat_din___dav___width 1 +#define reg_ser_rs_stat_din___dav___bit 16 +#define reg_ser_rs_stat_din___framing_err___lsb 17 +#define reg_ser_rs_stat_din___framing_err___width 1 +#define reg_ser_rs_stat_din___framing_err___bit 17 +#define reg_ser_rs_stat_din___par_err___lsb 18 +#define reg_ser_rs_stat_din___par_err___width 1 +#define reg_ser_rs_stat_din___par_err___bit 18 +#define reg_ser_rs_stat_din___orun___lsb 19 +#define reg_ser_rs_stat_din___orun___width 1 +#define reg_ser_rs_stat_din___orun___bit 19 +#define reg_ser_rs_stat_din___rec_err___lsb 20 +#define reg_ser_rs_stat_din___rec_err___width 1 +#define reg_ser_rs_stat_din___rec_err___bit 20 +#define reg_ser_rs_stat_din___rxd___lsb 21 +#define reg_ser_rs_stat_din___rxd___width 1 +#define reg_ser_rs_stat_din___rxd___bit 21 +#define reg_ser_rs_stat_din___tr_idle___lsb 22 +#define reg_ser_rs_stat_din___tr_idle___width 1 +#define reg_ser_rs_stat_din___tr_idle___bit 22 +#define reg_ser_rs_stat_din___tr_empty___lsb 23 +#define reg_ser_rs_stat_din___tr_empty___width 1 +#define reg_ser_rs_stat_din___tr_empty___bit 23 +#define reg_ser_rs_stat_din___tr_rdy___lsb 24 +#define reg_ser_rs_stat_din___tr_rdy___width 1 +#define reg_ser_rs_stat_din___tr_rdy___bit 24 +#define reg_ser_rs_stat_din___cts_n___lsb 25 +#define reg_ser_rs_stat_din___cts_n___width 1 +#define reg_ser_rs_stat_din___cts_n___bit 25 +#define reg_ser_rs_stat_din___xoff_detect___lsb 26 +#define reg_ser_rs_stat_din___xoff_detect___width 1 +#define reg_ser_rs_stat_din___xoff_detect___bit 26 +#define reg_ser_rs_stat_din___rts_n___lsb 27 +#define reg_ser_rs_stat_din___rts_n___width 1 +#define reg_ser_rs_stat_din___rts_n___bit 27 +#define reg_ser_rs_stat_din___txd___lsb 28 +#define reg_ser_rs_stat_din___txd___width 1 +#define reg_ser_rs_stat_din___txd___bit 28 +#define reg_ser_rs_stat_din_offset 32 + +/* Register r_stat_din, scope ser, type r */ +#define reg_ser_r_stat_din___data___lsb 0 +#define reg_ser_r_stat_din___data___width 8 +#define reg_ser_r_stat_din___dav___lsb 16 +#define reg_ser_r_stat_din___dav___width 1 +#define reg_ser_r_stat_din___dav___bit 16 +#define reg_ser_r_stat_din___framing_err___lsb 17 +#define reg_ser_r_stat_din___framing_err___width 1 +#define reg_ser_r_stat_din___framing_err___bit 17 +#define reg_ser_r_stat_din___par_err___lsb 18 +#define reg_ser_r_stat_din___par_err___width 1 +#define reg_ser_r_stat_din___par_err___bit 18 +#define reg_ser_r_stat_din___orun___lsb 19 +#define reg_ser_r_stat_din___orun___width 1 +#define reg_ser_r_stat_din___orun___bit 19 +#define reg_ser_r_stat_din___rec_err___lsb 20 +#define reg_ser_r_stat_din___rec_err___width 1 +#define reg_ser_r_stat_din___rec_err___bit 20 +#define reg_ser_r_stat_din___rxd___lsb 21 +#define reg_ser_r_stat_din___rxd___width 1 +#define reg_ser_r_stat_din___rxd___bit 21 +#define reg_ser_r_stat_din___tr_idle___lsb 22 +#define reg_ser_r_stat_din___tr_idle___width 1 +#define reg_ser_r_stat_din___tr_idle___bit 22 +#define reg_ser_r_stat_din___tr_empty___lsb 23 +#define reg_ser_r_stat_din___tr_empty___width 1 +#define reg_ser_r_stat_din___tr_empty___bit 23 +#define reg_ser_r_stat_din___tr_rdy___lsb 24 +#define reg_ser_r_stat_din___tr_rdy___width 1 +#define reg_ser_r_stat_din___tr_rdy___bit 24 +#define reg_ser_r_stat_din___cts_n___lsb 25 +#define reg_ser_r_stat_din___cts_n___width 1 +#define reg_ser_r_stat_din___cts_n___bit 25 +#define reg_ser_r_stat_din___xoff_detect___lsb 26 +#define reg_ser_r_stat_din___xoff_detect___width 1 +#define reg_ser_r_stat_din___xoff_detect___bit 26 +#define reg_ser_r_stat_din___rts_n___lsb 27 +#define reg_ser_r_stat_din___rts_n___width 1 +#define reg_ser_r_stat_din___rts_n___bit 27 +#define reg_ser_r_stat_din___txd___lsb 28 +#define reg_ser_r_stat_din___txd___width 1 +#define reg_ser_r_stat_din___txd___bit 28 +#define reg_ser_r_stat_din_offset 36 + +/* Register rw_rec_eop, scope ser, type rw */ +#define reg_ser_rw_rec_eop___set___lsb 0 +#define reg_ser_rw_rec_eop___set___width 1 +#define reg_ser_rw_rec_eop___set___bit 0 +#define reg_ser_rw_rec_eop_offset 40 + +/* Register rw_intr_mask, scope ser, type rw */ +#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 +#define reg_ser_rw_intr_mask___tr_rdy___width 1 +#define reg_ser_rw_intr_mask___tr_rdy___bit 0 +#define reg_ser_rw_intr_mask___tr_empty___lsb 1 +#define reg_ser_rw_intr_mask___tr_empty___width 1 +#define reg_ser_rw_intr_mask___tr_empty___bit 1 +#define reg_ser_rw_intr_mask___tr_idle___lsb 2 +#define reg_ser_rw_intr_mask___tr_idle___width 1 +#define reg_ser_rw_intr_mask___tr_idle___bit 2 +#define reg_ser_rw_intr_mask___dav___lsb 3 +#define reg_ser_rw_intr_mask___dav___width 1 +#define reg_ser_rw_intr_mask___dav___bit 3 +#define reg_ser_rw_intr_mask_offset 44 + +/* Register rw_ack_intr, scope ser, type rw */ +#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 +#define reg_ser_rw_ack_intr___tr_rdy___width 1 +#define reg_ser_rw_ack_intr___tr_rdy___bit 0 +#define reg_ser_rw_ack_intr___tr_empty___lsb 1 +#define reg_ser_rw_ack_intr___tr_empty___width 1 +#define reg_ser_rw_ack_intr___tr_empty___bit 1 +#define reg_ser_rw_ack_intr___tr_idle___lsb 2 +#define reg_ser_rw_ack_intr___tr_idle___width 1 +#define reg_ser_rw_ack_intr___tr_idle___bit 2 +#define reg_ser_rw_ack_intr___dav___lsb 3 +#define reg_ser_rw_ack_intr___dav___width 1 +#define reg_ser_rw_ack_intr___dav___bit 3 +#define reg_ser_rw_ack_intr_offset 48 + +/* Register r_intr, scope ser, type r */ +#define reg_ser_r_intr___tr_rdy___lsb 0 +#define reg_ser_r_intr___tr_rdy___width 1 +#define reg_ser_r_intr___tr_rdy___bit 0 +#define reg_ser_r_intr___tr_empty___lsb 1 +#define reg_ser_r_intr___tr_empty___width 1 +#define reg_ser_r_intr___tr_empty___bit 1 +#define reg_ser_r_intr___tr_idle___lsb 2 +#define reg_ser_r_intr___tr_idle___width 1 +#define reg_ser_r_intr___tr_idle___bit 2 +#define reg_ser_r_intr___dav___lsb 3 +#define reg_ser_r_intr___dav___width 1 +#define reg_ser_r_intr___dav___bit 3 +#define reg_ser_r_intr_offset 52 + +/* Register r_masked_intr, scope ser, type r */ +#define reg_ser_r_masked_intr___tr_rdy___lsb 0 +#define reg_ser_r_masked_intr___tr_rdy___width 1 +#define reg_ser_r_masked_intr___tr_rdy___bit 0 +#define reg_ser_r_masked_intr___tr_empty___lsb 1 +#define reg_ser_r_masked_intr___tr_empty___width 1 +#define reg_ser_r_masked_intr___tr_empty___bit 1 +#define reg_ser_r_masked_intr___tr_idle___lsb 2 +#define reg_ser_r_masked_intr___tr_idle___width 1 +#define reg_ser_r_masked_intr___tr_idle___bit 2 +#define reg_ser_r_masked_intr___dav___lsb 3 +#define reg_ser_r_masked_intr___dav___width 1 +#define reg_ser_r_masked_intr___dav___bit 3 +#define reg_ser_r_masked_intr_offset 56 + + +/* Constants */ +#define regk_ser_active 0x00000000 +#define regk_ser_bits1 0x00000000 +#define regk_ser_bits2 0x00000001 +#define regk_ser_bits7 0x00000001 +#define regk_ser_bits8 0x00000000 +#define regk_ser_del0_5 0x00000000 +#define regk_ser_del1 0x00000001 +#define regk_ser_del1_5 0x00000002 +#define regk_ser_del2 0x00000003 +#define regk_ser_del2_5 0x00000004 +#define regk_ser_del3 0x00000005 +#define regk_ser_del3_5 0x00000006 +#define regk_ser_del4 0x00000007 +#define regk_ser_even 0x00000000 +#define regk_ser_ext 0x00000001 +#define regk_ser_f100 0x00000007 +#define regk_ser_f29_493 0x00000004 +#define regk_ser_f32 0x00000005 +#define regk_ser_f32_768 0x00000006 +#define regk_ser_ignore 0x00000001 +#define regk_ser_inactive 0x00000001 +#define regk_ser_majority 0x00000001 +#define regk_ser_mark 0x00000002 +#define regk_ser_middle 0x00000000 +#define regk_ser_no 0x00000000 +#define regk_ser_odd 0x00000001 +#define regk_ser_off 0x00000000 +#define regk_ser_rw_intr_mask_default 0x00000000 +#define regk_ser_rw_rec_baud_div_default 0x00000000 +#define regk_ser_rw_rec_ctrl_default 0x00010000 +#define regk_ser_rw_tr_baud_div_default 0x00000000 +#define regk_ser_rw_tr_ctrl_default 0x00008000 +#define regk_ser_rw_tr_dma_en_default 0x00000000 +#define regk_ser_rw_xoff_default 0x00000000 +#define regk_ser_space 0x00000003 +#define regk_ser_stop 0x00000000 +#define regk_ser_yes 0x00000001 +#endif /* __ser_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h new file mode 100644 index 000000000000..27d4d91b3abd --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h @@ -0,0 +1,462 @@ +#ifndef __sser_defs_asm_h +#define __sser_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/syncser/rtl/sser_regs.r + * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp + * last modfied: Mon Apr 11 16:09:48 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r + * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope sser, type rw */ +#define reg_sser_rw_cfg___clk_div___lsb 0 +#define reg_sser_rw_cfg___clk_div___width 16 +#define reg_sser_rw_cfg___base_freq___lsb 16 +#define reg_sser_rw_cfg___base_freq___width 3 +#define reg_sser_rw_cfg___gate_clk___lsb 19 +#define reg_sser_rw_cfg___gate_clk___width 1 +#define reg_sser_rw_cfg___gate_clk___bit 19 +#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 +#define reg_sser_rw_cfg___clkgate_ctrl___width 1 +#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 +#define reg_sser_rw_cfg___clkgate_in___lsb 21 +#define reg_sser_rw_cfg___clkgate_in___width 1 +#define reg_sser_rw_cfg___clkgate_in___bit 21 +#define reg_sser_rw_cfg___clk_dir___lsb 22 +#define reg_sser_rw_cfg___clk_dir___width 1 +#define reg_sser_rw_cfg___clk_dir___bit 22 +#define reg_sser_rw_cfg___clk_od_mode___lsb 23 +#define reg_sser_rw_cfg___clk_od_mode___width 1 +#define reg_sser_rw_cfg___clk_od_mode___bit 23 +#define reg_sser_rw_cfg___out_clk_pol___lsb 24 +#define reg_sser_rw_cfg___out_clk_pol___width 1 +#define reg_sser_rw_cfg___out_clk_pol___bit 24 +#define reg_sser_rw_cfg___out_clk_src___lsb 25 +#define reg_sser_rw_cfg___out_clk_src___width 2 +#define reg_sser_rw_cfg___clk_in_sel___lsb 27 +#define reg_sser_rw_cfg___clk_in_sel___width 1 +#define reg_sser_rw_cfg___clk_in_sel___bit 27 +#define reg_sser_rw_cfg___hold_pol___lsb 28 +#define reg_sser_rw_cfg___hold_pol___width 1 +#define reg_sser_rw_cfg___hold_pol___bit 28 +#define reg_sser_rw_cfg___prepare___lsb 29 +#define reg_sser_rw_cfg___prepare___width 1 +#define reg_sser_rw_cfg___prepare___bit 29 +#define reg_sser_rw_cfg___en___lsb 30 +#define reg_sser_rw_cfg___en___width 1 +#define reg_sser_rw_cfg___en___bit 30 +#define reg_sser_rw_cfg_offset 0 + +/* Register rw_frm_cfg, scope sser, type rw */ +#define reg_sser_rw_frm_cfg___wordrate___lsb 0 +#define reg_sser_rw_frm_cfg___wordrate___width 10 +#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 +#define reg_sser_rw_frm_cfg___rec_delay___width 3 +#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 +#define reg_sser_rw_frm_cfg___tr_delay___width 3 +#define reg_sser_rw_frm_cfg___early_wend___lsb 16 +#define reg_sser_rw_frm_cfg___early_wend___width 1 +#define reg_sser_rw_frm_cfg___early_wend___bit 16 +#define reg_sser_rw_frm_cfg___level___lsb 17 +#define reg_sser_rw_frm_cfg___level___width 2 +#define reg_sser_rw_frm_cfg___type___lsb 19 +#define reg_sser_rw_frm_cfg___type___width 1 +#define reg_sser_rw_frm_cfg___type___bit 19 +#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 +#define reg_sser_rw_frm_cfg___clk_pol___width 1 +#define reg_sser_rw_frm_cfg___clk_pol___bit 20 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 +#define reg_sser_rw_frm_cfg___clk_src___lsb 22 +#define reg_sser_rw_frm_cfg___clk_src___width 1 +#define reg_sser_rw_frm_cfg___clk_src___bit 22 +#define reg_sser_rw_frm_cfg___out_off___lsb 23 +#define reg_sser_rw_frm_cfg___out_off___width 1 +#define reg_sser_rw_frm_cfg___out_off___bit 23 +#define reg_sser_rw_frm_cfg___out_on___lsb 24 +#define reg_sser_rw_frm_cfg___out_on___width 1 +#define reg_sser_rw_frm_cfg___out_on___bit 24 +#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 +#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 +#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 +#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 +#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 +#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 +#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 +#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 +#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 +#define reg_sser_rw_frm_cfg___status_pin_use___width 2 +#define reg_sser_rw_frm_cfg_offset 4 + +/* Register rw_tr_cfg, scope sser, type rw */ +#define reg_sser_rw_tr_cfg___tr_en___lsb 0 +#define reg_sser_rw_tr_cfg___tr_en___width 1 +#define reg_sser_rw_tr_cfg___tr_en___bit 0 +#define reg_sser_rw_tr_cfg___stop___lsb 1 +#define reg_sser_rw_tr_cfg___stop___width 1 +#define reg_sser_rw_tr_cfg___stop___bit 1 +#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 +#define reg_sser_rw_tr_cfg___urun_stop___width 1 +#define reg_sser_rw_tr_cfg___urun_stop___bit 2 +#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 +#define reg_sser_rw_tr_cfg___eop_stop___width 1 +#define reg_sser_rw_tr_cfg___eop_stop___bit 3 +#define reg_sser_rw_tr_cfg___sample_size___lsb 4 +#define reg_sser_rw_tr_cfg___sample_size___width 6 +#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 +#define reg_sser_rw_tr_cfg___sh_dir___width 1 +#define reg_sser_rw_tr_cfg___sh_dir___bit 10 +#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 +#define reg_sser_rw_tr_cfg___clk_pol___width 1 +#define reg_sser_rw_tr_cfg___clk_pol___bit 11 +#define reg_sser_rw_tr_cfg___clk_src___lsb 12 +#define reg_sser_rw_tr_cfg___clk_src___width 1 +#define reg_sser_rw_tr_cfg___clk_src___bit 12 +#define reg_sser_rw_tr_cfg___use_dma___lsb 13 +#define reg_sser_rw_tr_cfg___use_dma___width 1 +#define reg_sser_rw_tr_cfg___use_dma___bit 13 +#define reg_sser_rw_tr_cfg___mode___lsb 14 +#define reg_sser_rw_tr_cfg___mode___width 2 +#define reg_sser_rw_tr_cfg___frm_src___lsb 16 +#define reg_sser_rw_tr_cfg___frm_src___width 1 +#define reg_sser_rw_tr_cfg___frm_src___bit 16 +#define reg_sser_rw_tr_cfg___use60958___lsb 17 +#define reg_sser_rw_tr_cfg___use60958___width 1 +#define reg_sser_rw_tr_cfg___use60958___bit 17 +#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 +#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 +#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 +#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 +#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 +#define reg_sser_rw_tr_cfg___use_md___lsb 21 +#define reg_sser_rw_tr_cfg___use_md___width 1 +#define reg_sser_rw_tr_cfg___use_md___bit 21 +#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 +#define reg_sser_rw_tr_cfg___dual_i2s___width 1 +#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 +#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 +#define reg_sser_rw_tr_cfg___data_pin_use___width 2 +#define reg_sser_rw_tr_cfg___od_mode___lsb 25 +#define reg_sser_rw_tr_cfg___od_mode___width 1 +#define reg_sser_rw_tr_cfg___od_mode___bit 25 +#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 +#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 +#define reg_sser_rw_tr_cfg_offset 8 + +/* Register rw_rec_cfg, scope sser, type rw */ +#define reg_sser_rw_rec_cfg___rec_en___lsb 0 +#define reg_sser_rw_rec_cfg___rec_en___width 1 +#define reg_sser_rw_rec_cfg___rec_en___bit 0 +#define reg_sser_rw_rec_cfg___force_eop___lsb 1 +#define reg_sser_rw_rec_cfg___force_eop___width 1 +#define reg_sser_rw_rec_cfg___force_eop___bit 1 +#define reg_sser_rw_rec_cfg___stop___lsb 2 +#define reg_sser_rw_rec_cfg___stop___width 1 +#define reg_sser_rw_rec_cfg___stop___bit 2 +#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 +#define reg_sser_rw_rec_cfg___orun_stop___width 1 +#define reg_sser_rw_rec_cfg___orun_stop___bit 3 +#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 +#define reg_sser_rw_rec_cfg___eop_stop___width 1 +#define reg_sser_rw_rec_cfg___eop_stop___bit 4 +#define reg_sser_rw_rec_cfg___sample_size___lsb 5 +#define reg_sser_rw_rec_cfg___sample_size___width 6 +#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 +#define reg_sser_rw_rec_cfg___sh_dir___width 1 +#define reg_sser_rw_rec_cfg___sh_dir___bit 11 +#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 +#define reg_sser_rw_rec_cfg___clk_pol___width 1 +#define reg_sser_rw_rec_cfg___clk_pol___bit 12 +#define reg_sser_rw_rec_cfg___clk_src___lsb 13 +#define reg_sser_rw_rec_cfg___clk_src___width 1 +#define reg_sser_rw_rec_cfg___clk_src___bit 13 +#define reg_sser_rw_rec_cfg___use_dma___lsb 14 +#define reg_sser_rw_rec_cfg___use_dma___width 1 +#define reg_sser_rw_rec_cfg___use_dma___bit 14 +#define reg_sser_rw_rec_cfg___mode___lsb 15 +#define reg_sser_rw_rec_cfg___mode___width 2 +#define reg_sser_rw_rec_cfg___frm_src___lsb 17 +#define reg_sser_rw_rec_cfg___frm_src___width 2 +#define reg_sser_rw_rec_cfg___use60958___lsb 19 +#define reg_sser_rw_rec_cfg___use60958___width 1 +#define reg_sser_rw_rec_cfg___use60958___bit 19 +#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 +#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 +#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 +#define reg_sser_rw_rec_cfg___slave2_en___width 1 +#define reg_sser_rw_rec_cfg___slave2_en___bit 25 +#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 +#define reg_sser_rw_rec_cfg___slave3_en___width 1 +#define reg_sser_rw_rec_cfg___slave3_en___bit 26 +#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 +#define reg_sser_rw_rec_cfg___fifo_thr___width 2 +#define reg_sser_rw_rec_cfg_offset 12 + +/* Register rw_tr_data, scope sser, type rw */ +#define reg_sser_rw_tr_data___data___lsb 0 +#define reg_sser_rw_tr_data___data___width 16 +#define reg_sser_rw_tr_data___md___lsb 16 +#define reg_sser_rw_tr_data___md___width 1 +#define reg_sser_rw_tr_data___md___bit 16 +#define reg_sser_rw_tr_data_offset 16 + +/* Register r_rec_data, scope sser, type r */ +#define reg_sser_r_rec_data___data___lsb 0 +#define reg_sser_r_rec_data___data___width 16 +#define reg_sser_r_rec_data___md___lsb 16 +#define reg_sser_r_rec_data___md___width 1 +#define reg_sser_r_rec_data___md___bit 16 +#define reg_sser_r_rec_data___ext_clk___lsb 17 +#define reg_sser_r_rec_data___ext_clk___width 1 +#define reg_sser_r_rec_data___ext_clk___bit 17 +#define reg_sser_r_rec_data___status_in___lsb 18 +#define reg_sser_r_rec_data___status_in___width 1 +#define reg_sser_r_rec_data___status_in___bit 18 +#define reg_sser_r_rec_data___frame_in___lsb 19 +#define reg_sser_r_rec_data___frame_in___width 1 +#define reg_sser_r_rec_data___frame_in___bit 19 +#define reg_sser_r_rec_data___din___lsb 20 +#define reg_sser_r_rec_data___din___width 1 +#define reg_sser_r_rec_data___din___bit 20 +#define reg_sser_r_rec_data___data_in___lsb 21 +#define reg_sser_r_rec_data___data_in___width 1 +#define reg_sser_r_rec_data___data_in___bit 21 +#define reg_sser_r_rec_data___clk_in___lsb 22 +#define reg_sser_r_rec_data___clk_in___width 1 +#define reg_sser_r_rec_data___clk_in___bit 22 +#define reg_sser_r_rec_data_offset 20 + +/* Register rw_extra, scope sser, type rw */ +#define reg_sser_rw_extra___clkoff_cycles___lsb 0 +#define reg_sser_rw_extra___clkoff_cycles___width 20 +#define reg_sser_rw_extra___clkoff_en___lsb 20 +#define reg_sser_rw_extra___clkoff_en___width 1 +#define reg_sser_rw_extra___clkoff_en___bit 20 +#define reg_sser_rw_extra___clkon_en___lsb 21 +#define reg_sser_rw_extra___clkon_en___width 1 +#define reg_sser_rw_extra___clkon_en___bit 21 +#define reg_sser_rw_extra___dout_delay___lsb 22 +#define reg_sser_rw_extra___dout_delay___width 5 +#define reg_sser_rw_extra_offset 24 + +/* Register rw_intr_mask, scope sser, type rw */ +#define reg_sser_rw_intr_mask___trdy___lsb 0 +#define reg_sser_rw_intr_mask___trdy___width 1 +#define reg_sser_rw_intr_mask___trdy___bit 0 +#define reg_sser_rw_intr_mask___rdav___lsb 1 +#define reg_sser_rw_intr_mask___rdav___width 1 +#define reg_sser_rw_intr_mask___rdav___bit 1 +#define reg_sser_rw_intr_mask___tidle___lsb 2 +#define reg_sser_rw_intr_mask___tidle___width 1 +#define reg_sser_rw_intr_mask___tidle___bit 2 +#define reg_sser_rw_intr_mask___rstop___lsb 3 +#define reg_sser_rw_intr_mask___rstop___width 1 +#define reg_sser_rw_intr_mask___rstop___bit 3 +#define reg_sser_rw_intr_mask___urun___lsb 4 +#define reg_sser_rw_intr_mask___urun___width 1 +#define reg_sser_rw_intr_mask___urun___bit 4 +#define reg_sser_rw_intr_mask___orun___lsb 5 +#define reg_sser_rw_intr_mask___orun___width 1 +#define reg_sser_rw_intr_mask___orun___bit 5 +#define reg_sser_rw_intr_mask___md_rec___lsb 6 +#define reg_sser_rw_intr_mask___md_rec___width 1 +#define reg_sser_rw_intr_mask___md_rec___bit 6 +#define reg_sser_rw_intr_mask___md_sent___lsb 7 +#define reg_sser_rw_intr_mask___md_sent___width 1 +#define reg_sser_rw_intr_mask___md_sent___bit 7 +#define reg_sser_rw_intr_mask___r958err___lsb 8 +#define reg_sser_rw_intr_mask___r958err___width 1 +#define reg_sser_rw_intr_mask___r958err___bit 8 +#define reg_sser_rw_intr_mask_offset 28 + +/* Register rw_ack_intr, scope sser, type rw */ +#define reg_sser_rw_ack_intr___trdy___lsb 0 +#define reg_sser_rw_ack_intr___trdy___width 1 +#define reg_sser_rw_ack_intr___trdy___bit 0 +#define reg_sser_rw_ack_intr___rdav___lsb 1 +#define reg_sser_rw_ack_intr___rdav___width 1 +#define reg_sser_rw_ack_intr___rdav___bit 1 +#define reg_sser_rw_ack_intr___tidle___lsb 2 +#define reg_sser_rw_ack_intr___tidle___width 1 +#define reg_sser_rw_ack_intr___tidle___bit 2 +#define reg_sser_rw_ack_intr___rstop___lsb 3 +#define reg_sser_rw_ack_intr___rstop___width 1 +#define reg_sser_rw_ack_intr___rstop___bit 3 +#define reg_sser_rw_ack_intr___urun___lsb 4 +#define reg_sser_rw_ack_intr___urun___width 1 +#define reg_sser_rw_ack_intr___urun___bit 4 +#define reg_sser_rw_ack_intr___orun___lsb 5 +#define reg_sser_rw_ack_intr___orun___width 1 +#define reg_sser_rw_ack_intr___orun___bit 5 +#define reg_sser_rw_ack_intr___md_rec___lsb 6 +#define reg_sser_rw_ack_intr___md_rec___width 1 +#define reg_sser_rw_ack_intr___md_rec___bit 6 +#define reg_sser_rw_ack_intr___md_sent___lsb 7 +#define reg_sser_rw_ack_intr___md_sent___width 1 +#define reg_sser_rw_ack_intr___md_sent___bit 7 +#define reg_sser_rw_ack_intr___r958err___lsb 8 +#define reg_sser_rw_ack_intr___r958err___width 1 +#define reg_sser_rw_ack_intr___r958err___bit 8 +#define reg_sser_rw_ack_intr_offset 32 + +/* Register r_intr, scope sser, type r */ +#define reg_sser_r_intr___trdy___lsb 0 +#define reg_sser_r_intr___trdy___width 1 +#define reg_sser_r_intr___trdy___bit 0 +#define reg_sser_r_intr___rdav___lsb 1 +#define reg_sser_r_intr___rdav___width 1 +#define reg_sser_r_intr___rdav___bit 1 +#define reg_sser_r_intr___tidle___lsb 2 +#define reg_sser_r_intr___tidle___width 1 +#define reg_sser_r_intr___tidle___bit 2 +#define reg_sser_r_intr___rstop___lsb 3 +#define reg_sser_r_intr___rstop___width 1 +#define reg_sser_r_intr___rstop___bit 3 +#define reg_sser_r_intr___urun___lsb 4 +#define reg_sser_r_intr___urun___width 1 +#define reg_sser_r_intr___urun___bit 4 +#define reg_sser_r_intr___orun___lsb 5 +#define reg_sser_r_intr___orun___width 1 +#define reg_sser_r_intr___orun___bit 5 +#define reg_sser_r_intr___md_rec___lsb 6 +#define reg_sser_r_intr___md_rec___width 1 +#define reg_sser_r_intr___md_rec___bit 6 +#define reg_sser_r_intr___md_sent___lsb 7 +#define reg_sser_r_intr___md_sent___width 1 +#define reg_sser_r_intr___md_sent___bit 7 +#define reg_sser_r_intr___r958err___lsb 8 +#define reg_sser_r_intr___r958err___width 1 +#define reg_sser_r_intr___r958err___bit 8 +#define reg_sser_r_intr_offset 36 + +/* Register r_masked_intr, scope sser, type r */ +#define reg_sser_r_masked_intr___trdy___lsb 0 +#define reg_sser_r_masked_intr___trdy___width 1 +#define reg_sser_r_masked_intr___trdy___bit 0 +#define reg_sser_r_masked_intr___rdav___lsb 1 +#define reg_sser_r_masked_intr___rdav___width 1 +#define reg_sser_r_masked_intr___rdav___bit 1 +#define reg_sser_r_masked_intr___tidle___lsb 2 +#define reg_sser_r_masked_intr___tidle___width 1 +#define reg_sser_r_masked_intr___tidle___bit 2 +#define reg_sser_r_masked_intr___rstop___lsb 3 +#define reg_sser_r_masked_intr___rstop___width 1 +#define reg_sser_r_masked_intr___rstop___bit 3 +#define reg_sser_r_masked_intr___urun___lsb 4 +#define reg_sser_r_masked_intr___urun___width 1 +#define reg_sser_r_masked_intr___urun___bit 4 +#define reg_sser_r_masked_intr___orun___lsb 5 +#define reg_sser_r_masked_intr___orun___width 1 +#define reg_sser_r_masked_intr___orun___bit 5 +#define reg_sser_r_masked_intr___md_rec___lsb 6 +#define reg_sser_r_masked_intr___md_rec___width 1 +#define reg_sser_r_masked_intr___md_rec___bit 6 +#define reg_sser_r_masked_intr___md_sent___lsb 7 +#define reg_sser_r_masked_intr___md_sent___width 1 +#define reg_sser_r_masked_intr___md_sent___bit 7 +#define reg_sser_r_masked_intr___r958err___lsb 8 +#define reg_sser_r_masked_intr___r958err___width 1 +#define reg_sser_r_masked_intr___r958err___bit 8 +#define reg_sser_r_masked_intr_offset 40 + + +/* Constants */ +#define regk_sser_both 0x00000002 +#define regk_sser_bulk 0x00000001 +#define regk_sser_clk100 0x00000000 +#define regk_sser_clk_in 0x00000000 +#define regk_sser_const0 0x00000003 +#define regk_sser_dout 0x00000002 +#define regk_sser_edge 0x00000000 +#define regk_sser_ext 0x00000001 +#define regk_sser_ext_clk 0x00000001 +#define regk_sser_f100 0x00000000 +#define regk_sser_f29_493 0x00000004 +#define regk_sser_f32 0x00000005 +#define regk_sser_f32_768 0x00000006 +#define regk_sser_frm 0x00000003 +#define regk_sser_gio0 0x00000000 +#define regk_sser_gio1 0x00000001 +#define regk_sser_hispeed 0x00000001 +#define regk_sser_hold 0x00000002 +#define regk_sser_in 0x00000000 +#define regk_sser_inf 0x00000003 +#define regk_sser_intern 0x00000000 +#define regk_sser_intern_clk 0x00000001 +#define regk_sser_intern_tb 0x00000000 +#define regk_sser_iso 0x00000000 +#define regk_sser_level 0x00000001 +#define regk_sser_lospeed 0x00000000 +#define regk_sser_lsbfirst 0x00000000 +#define regk_sser_msbfirst 0x00000001 +#define regk_sser_neg 0x00000001 +#define regk_sser_neg_lo 0x00000000 +#define regk_sser_no 0x00000000 +#define regk_sser_no_clk 0x00000007 +#define regk_sser_nojitter 0x00000002 +#define regk_sser_out 0x00000001 +#define regk_sser_pos 0x00000000 +#define regk_sser_pos_hi 0x00000001 +#define regk_sser_rec 0x00000000 +#define regk_sser_rw_cfg_default 0x00000000 +#define regk_sser_rw_extra_default 0x00000000 +#define regk_sser_rw_frm_cfg_default 0x00000000 +#define regk_sser_rw_intr_mask_default 0x00000000 +#define regk_sser_rw_rec_cfg_default 0x00000000 +#define regk_sser_rw_tr_cfg_default 0x01800000 +#define regk_sser_rw_tr_data_default 0x00000000 +#define regk_sser_thr16 0x00000001 +#define regk_sser_thr32 0x00000002 +#define regk_sser_thr8 0x00000000 +#define regk_sser_tr 0x00000001 +#define regk_sser_ts_out 0x00000003 +#define regk_sser_tx_bulk 0x00000002 +#define regk_sser_wiresave 0x00000002 +#define regk_sser_yes 0x00000001 +#endif /* __sser_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h new file mode 100644 index 000000000000..55083e6aec93 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h @@ -0,0 +1,84 @@ +#ifndef __strcop_defs_asm_h +#define __strcop_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/strcop/rtl/strcop_regs.r + * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp + * last modfied: Mon Apr 11 16:09:38 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r + * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope strcop, type rw */ +#define reg_strcop_rw_cfg___td3___lsb 0 +#define reg_strcop_rw_cfg___td3___width 1 +#define reg_strcop_rw_cfg___td3___bit 0 +#define reg_strcop_rw_cfg___td2___lsb 1 +#define reg_strcop_rw_cfg___td2___width 1 +#define reg_strcop_rw_cfg___td2___bit 1 +#define reg_strcop_rw_cfg___td1___lsb 2 +#define reg_strcop_rw_cfg___td1___width 1 +#define reg_strcop_rw_cfg___td1___bit 2 +#define reg_strcop_rw_cfg___ipend___lsb 3 +#define reg_strcop_rw_cfg___ipend___width 1 +#define reg_strcop_rw_cfg___ipend___bit 3 +#define reg_strcop_rw_cfg___ignore_sync___lsb 4 +#define reg_strcop_rw_cfg___ignore_sync___width 1 +#define reg_strcop_rw_cfg___ignore_sync___bit 4 +#define reg_strcop_rw_cfg___en___lsb 5 +#define reg_strcop_rw_cfg___en___width 1 +#define reg_strcop_rw_cfg___en___bit 5 +#define reg_strcop_rw_cfg_offset 0 + + +/* Constants */ +#define regk_strcop_big 0x00000001 +#define regk_strcop_d 0x00000001 +#define regk_strcop_e 0x00000000 +#define regk_strcop_little 0x00000000 +#define regk_strcop_rw_cfg_default 0x00000002 +#endif /* __strcop_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h new file mode 100644 index 000000000000..69b299920f71 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h @@ -0,0 +1,100 @@ +#ifndef __strmux_defs_asm_h +#define __strmux_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp + * last modfied: Mon Apr 11 16:09:43 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope strmux, type rw */ +#define reg_strmux_rw_cfg___dma0___lsb 0 +#define reg_strmux_rw_cfg___dma0___width 3 +#define reg_strmux_rw_cfg___dma1___lsb 3 +#define reg_strmux_rw_cfg___dma1___width 3 +#define reg_strmux_rw_cfg___dma2___lsb 6 +#define reg_strmux_rw_cfg___dma2___width 3 +#define reg_strmux_rw_cfg___dma3___lsb 9 +#define reg_strmux_rw_cfg___dma3___width 3 +#define reg_strmux_rw_cfg___dma4___lsb 12 +#define reg_strmux_rw_cfg___dma4___width 3 +#define reg_strmux_rw_cfg___dma5___lsb 15 +#define reg_strmux_rw_cfg___dma5___width 3 +#define reg_strmux_rw_cfg___dma6___lsb 18 +#define reg_strmux_rw_cfg___dma6___width 3 +#define reg_strmux_rw_cfg___dma7___lsb 21 +#define reg_strmux_rw_cfg___dma7___width 3 +#define reg_strmux_rw_cfg___dma8___lsb 24 +#define reg_strmux_rw_cfg___dma8___width 3 +#define reg_strmux_rw_cfg___dma9___lsb 27 +#define reg_strmux_rw_cfg___dma9___width 3 +#define reg_strmux_rw_cfg_offset 0 + + +/* Constants */ +#define regk_strmux_ata 0x00000003 +#define regk_strmux_eth0 0x00000001 +#define regk_strmux_eth1 0x00000004 +#define regk_strmux_ext0 0x00000001 +#define regk_strmux_ext1 0x00000001 +#define regk_strmux_ext2 0x00000001 +#define regk_strmux_ext3 0x00000001 +#define regk_strmux_iop0 0x00000002 +#define regk_strmux_iop1 0x00000001 +#define regk_strmux_off 0x00000000 +#define regk_strmux_p21 0x00000004 +#define regk_strmux_rw_cfg_default 0x00000000 +#define regk_strmux_ser0 0x00000002 +#define regk_strmux_ser1 0x00000002 +#define regk_strmux_ser2 0x00000004 +#define regk_strmux_ser3 0x00000003 +#define regk_strmux_sser0 0x00000003 +#define regk_strmux_sser1 0x00000003 +#define regk_strmux_strcop 0x00000002 +#endif /* __strmux_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000000..43146021fc16 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,229 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h new file mode 100644 index 000000000000..43b6643ff0d3 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/ata_defs.h @@ -0,0 +1,222 @@ +#ifndef __ata_defs_h +#define __ata_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ata/rtl/ata_regs.r + * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp + * last modfied: Mon Apr 11 16:06:25 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r + * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ata */ + +/* Register rw_ctrl0, scope ata, type rw */ +typedef struct { + unsigned int pio_hold : 6; + unsigned int pio_strb : 6; + unsigned int pio_setup : 6; + unsigned int dma_hold : 6; + unsigned int dma_strb : 6; + unsigned int rst : 1; + unsigned int en : 1; +} reg_ata_rw_ctrl0; +#define REG_RD_ADDR_ata_rw_ctrl0 12 +#define REG_WR_ADDR_ata_rw_ctrl0 12 + +/* Register rw_ctrl1, scope ata, type rw */ +typedef struct { + unsigned int udma_tcyc : 4; + unsigned int udma_tdvs : 4; + unsigned int dummy1 : 24; +} reg_ata_rw_ctrl1; +#define REG_RD_ADDR_ata_rw_ctrl1 16 +#define REG_WR_ADDR_ata_rw_ctrl1 16 + +/* Register rw_ctrl2, scope ata, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 3; + unsigned int dma_size : 1; + unsigned int multi : 1; + unsigned int hsh : 2; + unsigned int trf_mode : 1; + unsigned int rw : 1; + unsigned int addr : 3; + unsigned int cs0 : 1; + unsigned int cs1 : 1; + unsigned int sel : 2; +} reg_ata_rw_ctrl2; +#define REG_RD_ADDR_ata_rw_ctrl2 0 +#define REG_WR_ADDR_ata_rw_ctrl2 0 + +/* Register rs_stat_data, scope ata, type rs */ +typedef struct { + unsigned int data : 16; + unsigned int dav : 1; + unsigned int busy : 1; + unsigned int dummy1 : 14; +} reg_ata_rs_stat_data; +#define REG_RD_ADDR_ata_rs_stat_data 4 + +/* Register r_stat_data, scope ata, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dav : 1; + unsigned int busy : 1; + unsigned int dummy1 : 14; +} reg_ata_r_stat_data; +#define REG_RD_ADDR_ata_r_stat_data 8 + +/* Register rw_trf_cnt, scope ata, type rw */ +typedef struct { + unsigned int cnt : 17; + unsigned int dummy1 : 15; +} reg_ata_rw_trf_cnt; +#define REG_RD_ADDR_ata_rw_trf_cnt 20 +#define REG_WR_ADDR_ata_rw_trf_cnt 20 + +/* Register r_stat_misc, scope ata, type r */ +typedef struct { + unsigned int crc : 16; + unsigned int dummy1 : 16; +} reg_ata_r_stat_misc; +#define REG_RD_ADDR_ata_r_stat_misc 24 + +/* Register rw_intr_mask, scope ata, type rw */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_rw_intr_mask; +#define REG_RD_ADDR_ata_rw_intr_mask 28 +#define REG_WR_ADDR_ata_rw_intr_mask 28 + +/* Register rw_ack_intr, scope ata, type rw */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_rw_ack_intr; +#define REG_RD_ADDR_ata_rw_ack_intr 32 +#define REG_WR_ADDR_ata_rw_ack_intr 32 + +/* Register r_intr, scope ata, type r */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_r_intr; +#define REG_RD_ADDR_ata_r_intr 36 + +/* Register r_masked_intr, scope ata, type r */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_r_masked_intr; +#define REG_RD_ADDR_ata_r_masked_intr 40 + + +/* Constants */ +enum { + regk_ata_active = 0x00000001, + regk_ata_byte = 0x00000001, + regk_ata_data = 0x00000001, + regk_ata_dma = 0x00000001, + regk_ata_inactive = 0x00000000, + regk_ata_no = 0x00000000, + regk_ata_nodata = 0x00000000, + regk_ata_pio = 0x00000000, + regk_ata_rd = 0x00000001, + regk_ata_reg = 0x00000000, + regk_ata_rw_ctrl0_default = 0x00000000, + regk_ata_rw_ctrl2_default = 0x00000000, + regk_ata_rw_intr_mask_default = 0x00000000, + regk_ata_udma = 0x00000002, + regk_ata_word = 0x00000000, + regk_ata_wr = 0x00000000, + regk_ata_yes = 0x00000001 +}; +#endif /* __ata_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h new file mode 100644 index 000000000000..a56608b50359 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h @@ -0,0 +1,284 @@ +#ifndef __bif_core_defs_h +#define __bif_core_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_core */ + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp1_cfg; +#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 +#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp2_cfg; +#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 +#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 2; + unsigned int gated_csp0 : 2; + unsigned int gated_csp1 : 2; + unsigned int gated_csp2 : 2; + unsigned int gated_csp3 : 2; +} reg_bif_core_rw_grp3_cfg; +#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 +#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 4; + unsigned int gated_csp4 : 2; + unsigned int gated_csp5 : 2; + unsigned int gated_csp6 : 2; +} reg_bif_core_rw_grp4_cfg; +#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 +#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int grp_sel : 5; + unsigned int dummy1 : 12; +} reg_bif_core_rw_sdram_cfg_grp0; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int dummy1 : 17; +} reg_bif_core_rw_sdram_cfg_grp1; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +typedef struct { + unsigned int cl : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int rc : 2; + unsigned int dpl : 2; + unsigned int pde : 1; + unsigned int ref : 2; + unsigned int cpd : 1; + unsigned int sdcke : 1; + unsigned int sdclk : 1; + unsigned int dummy1 : 13; +} reg_bif_core_rw_sdram_timing; +#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 +#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +typedef struct { + unsigned int cmd : 3; + unsigned int mrs_data : 15; + unsigned int dummy1 : 14; +} reg_bif_core_rw_sdram_cmd; +#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 +#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_rs_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_r_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 + + +/* Constants */ +enum { + regk_bif_core_bank2 = 0x00000000, + regk_bif_core_bank4 = 0x00000001, + regk_bif_core_bit10 = 0x0000000a, + regk_bif_core_bit11 = 0x0000000b, + regk_bif_core_bit12 = 0x0000000c, + regk_bif_core_bit13 = 0x0000000d, + regk_bif_core_bit14 = 0x0000000e, + regk_bif_core_bit15 = 0x0000000f, + regk_bif_core_bit16 = 0x00000010, + regk_bif_core_bit17 = 0x00000011, + regk_bif_core_bit18 = 0x00000012, + regk_bif_core_bit19 = 0x00000013, + regk_bif_core_bit20 = 0x00000014, + regk_bif_core_bit21 = 0x00000015, + regk_bif_core_bit22 = 0x00000016, + regk_bif_core_bit23 = 0x00000017, + regk_bif_core_bit24 = 0x00000018, + regk_bif_core_bit25 = 0x00000019, + regk_bif_core_bit26 = 0x0000001a, + regk_bif_core_bit27 = 0x0000001b, + regk_bif_core_bit28 = 0x0000001c, + regk_bif_core_bit29 = 0x0000001d, + regk_bif_core_bit9 = 0x00000009, + regk_bif_core_bw16 = 0x00000001, + regk_bif_core_bw32 = 0x00000000, + regk_bif_core_bwe = 0x00000000, + regk_bif_core_cwe = 0x00000001, + regk_bif_core_e15us = 0x00000001, + regk_bif_core_e7800ns = 0x00000002, + regk_bif_core_grp0 = 0x00000000, + regk_bif_core_grp1 = 0x00000001, + regk_bif_core_mrs = 0x00000003, + regk_bif_core_no = 0x00000000, + regk_bif_core_none = 0x00000000, + regk_bif_core_nop = 0x00000000, + regk_bif_core_off = 0x00000000, + regk_bif_core_pre = 0x00000002, + regk_bif_core_r_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rd = 0x00000002, + regk_bif_core_ref = 0x00000001, + regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rw_grp1_cfg_default = 0x000006cf, + regk_bif_core_rw_grp2_cfg_default = 0x000006cf, + regk_bif_core_rw_grp3_cfg_default = 0x000006cf, + regk_bif_core_rw_grp4_cfg_default = 0x000006cf, + regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, + regk_bif_core_slf = 0x00000004, + regk_bif_core_wr = 0x00000001, + regk_bif_core_yes = 0x00000001 +}; +#endif /* __bif_core_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h new file mode 100644 index 000000000000..b931c1aab679 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h @@ -0,0 +1,473 @@ +#ifndef __bif_dma_defs_h +#define __bif_dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_dma */ + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch0_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 +#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch0_addr; +#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 +#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch0_start; +#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 +#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch0_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 +#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch0_stat; +#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch1_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 +#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch1_addr; +#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 +#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch1_start; +#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 +#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch1_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 +#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch1_stat; +#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch2_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 +#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch2_addr; +#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 +#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch2_start; +#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 +#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch2_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 +#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch2_stat; +#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch3_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 +#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch3_addr; +#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 +#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch3_start; +#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 +#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch3_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 +#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch3_stat; +#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_intr_mask; +#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 +#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_ack_intr; +#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 +#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 + +/* Register r_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_intr; +#define REG_RD_ADDR_bif_dma_r_intr 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_masked_intr; +#define REG_RD_ADDR_bif_dma_r_masked_intr 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin0_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 +#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin1_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 +#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin2_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 +#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin3_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 +#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin4_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 +#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin5_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 +#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin6_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 +#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin7_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 +#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +typedef struct { + unsigned int pin0 : 1; + unsigned int pin1 : 1; + unsigned int pin2 : 1; + unsigned int pin3 : 1; + unsigned int pin4 : 1; + unsigned int pin5 : 1; + unsigned int pin6 : 1; + unsigned int pin7 : 1; + unsigned int dummy1 : 24; +} reg_bif_dma_r_pin_stat; +#define REG_RD_ADDR_bif_dma_r_pin_stat 192 + + +/* Constants */ +enum { + regk_bif_dma_as_master = 0x00000001, + regk_bif_dma_as_slave = 0x00000001, + regk_bif_dma_burst1 = 0x00000000, + regk_bif_dma_burst8 = 0x00000001, + regk_bif_dma_bw16 = 0x00000001, + regk_bif_dma_bw32 = 0x00000002, + regk_bif_dma_bw8 = 0x00000000, + regk_bif_dma_dack = 0x00000006, + regk_bif_dma_dack_inv = 0x00000007, + regk_bif_dma_force = 0x00000001, + regk_bif_dma_hi = 0x00000003, + regk_bif_dma_inv = 0x00000003, + regk_bif_dma_lo = 0x00000002, + regk_bif_dma_master = 0x00000001, + regk_bif_dma_no = 0x00000000, + regk_bif_dma_norm = 0x00000002, + regk_bif_dma_off = 0x00000000, + regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch0_start_default = 0x00000000, + regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch1_start_default = 0x00000000, + regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch2_start_default = 0x00000000, + regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch3_start_default = 0x00000000, + regk_bif_dma_rw_intr_mask_default = 0x00000000, + regk_bif_dma_rw_pin0_cfg_default = 0x00000000, + regk_bif_dma_rw_pin1_cfg_default = 0x00000000, + regk_bif_dma_rw_pin2_cfg_default = 0x00000000, + regk_bif_dma_rw_pin3_cfg_default = 0x00000000, + regk_bif_dma_rw_pin4_cfg_default = 0x00000000, + regk_bif_dma_rw_pin5_cfg_default = 0x00000000, + regk_bif_dma_rw_pin6_cfg_default = 0x00000000, + regk_bif_dma_rw_pin7_cfg_default = 0x00000000, + regk_bif_dma_slave = 0x00000002, + regk_bif_dma_sreq = 0x00000006, + regk_bif_dma_sreq_inv = 0x00000007, + regk_bif_dma_tc = 0x00000004, + regk_bif_dma_tc_inv = 0x00000005, + regk_bif_dma_yes = 0x00000001 +}; +#endif /* __bif_dma_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h new file mode 100644 index 000000000000..d18fc3c9f569 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_h +#define __bif_slave_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_slave */ + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int slave_id : 3; + unsigned int use_slave_id : 1; + unsigned int boot_rdy : 1; + unsigned int loopback : 1; + unsigned int dis : 1; + unsigned int dummy1 : 25; +} reg_bif_slave_rw_slave_cfg; +#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 +#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +typedef struct { + unsigned int ch0_mode : 1; + unsigned int ch1_mode : 1; + unsigned int ch2_mode : 1; + unsigned int ch3_mode : 1; + unsigned int dummy1 : 28; +} reg_bif_slave_r_slave_mode; +#define REG_RD_ADDR_bif_slave_r_slave_mode 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch0_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 +#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch1_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 +#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch2_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 +#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch3_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 +#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int brin_mode : 1; + unsigned int brout_mode : 3; + unsigned int bg_mode : 3; + unsigned int release : 2; + unsigned int acquire : 1; + unsigned int settle_time : 2; + unsigned int dram_ctrl : 1; + unsigned int dummy1 : 19; +} reg_bif_slave_rw_arb_cfg; +#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 +#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +typedef struct { + unsigned int init_mode : 1; + unsigned int mode : 1; + unsigned int brin : 1; + unsigned int brout : 1; + unsigned int bg : 1; + unsigned int dummy1 : 27; +} reg_bif_slave_r_arb_stat; +#define REG_RD_ADDR_bif_slave_r_arb_stat 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_intr_mask; +#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 +#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_ack_intr; +#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 +#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 + +/* Register r_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_intr; +#define REG_RD_ADDR_bif_slave_r_intr 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_masked_intr; +#define REG_RD_ADDR_bif_slave_r_masked_intr 76 + + +/* Constants */ +enum { + regk_bif_slave_active_hi = 0x00000003, + regk_bif_slave_active_lo = 0x00000002, + regk_bif_slave_addr = 0x00000000, + regk_bif_slave_always = 0x00000001, + regk_bif_slave_at_idle = 0x00000002, + regk_bif_slave_burst_end = 0x00000003, + regk_bif_slave_dma = 0x00000001, + regk_bif_slave_hi = 0x00000003, + regk_bif_slave_inv = 0x00000001, + regk_bif_slave_lo = 0x00000002, + regk_bif_slave_local = 0x00000001, + regk_bif_slave_master = 0x00000000, + regk_bif_slave_mode_reg = 0x00000001, + regk_bif_slave_no = 0x00000000, + regk_bif_slave_norm = 0x00000000, + regk_bif_slave_on_access = 0x00000000, + regk_bif_slave_rw_arb_cfg_default = 0x00000000, + regk_bif_slave_rw_ch0_cfg_default = 0x00000000, + regk_bif_slave_rw_ch1_cfg_default = 0x00000000, + regk_bif_slave_rw_ch2_cfg_default = 0x00000000, + regk_bif_slave_rw_ch3_cfg_default = 0x00000000, + regk_bif_slave_rw_intr_mask_default = 0x00000000, + regk_bif_slave_rw_slave_cfg_default = 0x00000000, + regk_bif_slave_shared = 0x00000000, + regk_bif_slave_slave = 0x00000001, + regk_bif_slave_t0ns = 0x00000003, + regk_bif_slave_t10ns = 0x00000002, + regk_bif_slave_t20ns = 0x00000003, + regk_bif_slave_t30ns = 0x00000002, + regk_bif_slave_t40ns = 0x00000001, + regk_bif_slave_t50ns = 0x00000000, + regk_bif_slave_yes = 0x00000001, + regk_bif_slave_z = 0x00000004 +}; +#endif /* __bif_slave_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h new file mode 100644 index 000000000000..45457a4e3817 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/config_defs.h @@ -0,0 +1,142 @@ +#ifndef __config_defs_h +#define __config_defs_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r + * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope config */ + +/* Register r_bootsel, scope config, type r */ +typedef struct { + unsigned int boot_mode : 3; + unsigned int full_duplex : 1; + unsigned int user : 1; + unsigned int pll : 1; + unsigned int flash_bw : 1; + unsigned int dummy1 : 25; +} reg_config_r_bootsel; +#define REG_RD_ADDR_config_r_bootsel 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop : 1; + unsigned int dma01_eth0 : 1; + unsigned int dma23 : 1; + unsigned int dma45 : 1; + unsigned int dma67 : 1; + unsigned int dma89_strcop : 1; + unsigned int bif : 1; + unsigned int fix_io : 1; + unsigned int dummy1 : 22; +} reg_config_rw_clk_ctrl; +#define REG_RD_ADDR_config_rw_clk_ctrl 4 +#define REG_WR_ADDR_config_rw_clk_ctrl 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +typedef struct { + unsigned int usb_susp : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 30; +} reg_config_rw_pad_ctrl; +#define REG_RD_ADDR_config_rw_pad_ctrl 8 +#define REG_WR_ADDR_config_rw_pad_ctrl 8 + + +/* Constants */ +enum { + regk_config_bw16 = 0x00000000, + regk_config_bw32 = 0x00000001, + regk_config_master = 0x00000005, + regk_config_nand = 0x00000003, + regk_config_net_rx = 0x00000001, + regk_config_net_tx_rx = 0x00000002, + regk_config_no = 0x00000000, + regk_config_none = 0x00000007, + regk_config_nor = 0x00000000, + regk_config_rw_clk_ctrl_default = 0x00000002, + regk_config_rw_pad_ctrl_default = 0x00000000, + regk_config_ser = 0x00000004, + regk_config_slave = 0x00000006, + regk_config_yes = 0x00000001 +}; +#endif /* __config_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h new file mode 100644 index 000000000000..8370aee8a14a --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/cpu_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/crisp/doc/cpu_vect.r +version . */ + +#ifndef _______INST_CRISP_DOC_CPU_VECT_R +#define _______INST_CRISP_DOC_CPU_VECT_R +#define NMI_INTR_VECT 0x00 +#define RESERVED_1_INTR_VECT 0x01 +#define RESERVED_2_INTR_VECT 0x02 +#define SINGLE_STEP_INTR_VECT 0x03 +#define INSTR_TLB_REFILL_INTR_VECT 0x04 +#define INSTR_TLB_INV_INTR_VECT 0x05 +#define INSTR_TLB_ACC_INTR_VECT 0x06 +#define TLB_EX_INTR_VECT 0x07 +#define DATA_TLB_REFILL_INTR_VECT 0x08 +#define DATA_TLB_INV_INTR_VECT 0x09 +#define DATA_TLB_ACC_INTR_VECT 0x0a +#define DATA_TLB_WE_INTR_VECT 0x0b +#define HW_BP_INTR_VECT 0x0c +#define RESERVED_D_INTR_VECT 0x0d +#define RESERVED_E_INTR_VECT 0x0e +#define RESERVED_F_INTR_VECT 0x0f +#define BREAK_0_INTR_VECT 0x10 +#define BREAK_1_INTR_VECT 0x11 +#define BREAK_2_INTR_VECT 0x12 +#define BREAK_3_INTR_VECT 0x13 +#define BREAK_4_INTR_VECT 0x14 +#define BREAK_5_INTR_VECT 0x15 +#define BREAK_6_INTR_VECT 0x16 +#define BREAK_7_INTR_VECT 0x17 +#define BREAK_8_INTR_VECT 0x18 +#define BREAK_9_INTR_VECT 0x19 +#define BREAK_10_INTR_VECT 0x1a +#define BREAK_11_INTR_VECT 0x1b +#define BREAK_12_INTR_VECT 0x1c +#define BREAK_13_INTR_VECT 0x1d +#define BREAK_14_INTR_VECT 0x1e +#define BREAK_15_INTR_VECT 0x1f +#define MULTIPLE_INTR_VECT 0x30 + +#endif diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h new file mode 100644 index 000000000000..c31832d3d6be --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/dma.h @@ -0,0 +1,128 @@ +/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * + * DMA C definitions and help macros + * + */ + +#ifndef dma_h +#define dma_h + +/* registers */ /* Really needed, since both are listed in sw.list? */ +#include "dma_defs.h" + + +/* descriptors */ + +// ------------------------------------------------------------ dma_descr_group +typedef struct dma_descr_group { + struct dma_descr_group *next; + unsigned eol : 1; + unsigned tol : 1; + unsigned bol : 1; + unsigned : 1; + unsigned intr : 1; + unsigned : 2; + unsigned en : 1; + unsigned : 7; + unsigned dis : 1; + unsigned md : 16; + struct dma_descr_group *up; + union { + struct dma_descr_context *context; + struct dma_descr_group *group; + } down; +} dma_descr_group; + +// ---------------------------------------------------------- dma_descr_context +typedef struct dma_descr_context { + struct dma_descr_context *next; + unsigned eol : 1; + unsigned : 3; + unsigned intr : 1; + unsigned : 1; + unsigned store_mode : 1; + unsigned en : 1; + unsigned : 7; + unsigned dis : 1; + unsigned md0 : 16; + unsigned md1; + unsigned md2; + unsigned md3; + unsigned md4; + struct dma_descr_data *saved_data; + char *saved_data_buf; +} dma_descr_context; + +// ------------------------------------------------------------- dma_descr_data +typedef struct dma_descr_data { + struct dma_descr_data *next; + char *buf; + unsigned eol : 1; + unsigned : 2; + unsigned out_eop : 1; + unsigned intr : 1; + unsigned wait : 1; + unsigned : 2; + unsigned : 3; + unsigned in_eop : 1; + unsigned : 4; + unsigned md : 16; + char *after; +} dma_descr_data; + +// --------------------------------------------------------------------- macros + +// enable DMA channel +#define DMA_ENABLE( inst ) \ + do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ + e.en = regk_dma_yes; \ + REG_WR( dma, inst, rw_cfg, e); } while( 0 ) + +// reset DMA channel +#define DMA_RESET( inst ) \ + do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ + r.en = regk_dma_no; \ + REG_WR( dma, inst, rw_cfg, r); } while( 0 ) + +// stop DMA channel +#define DMA_STOP( inst ) \ + do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ + s.stop = regk_dma_yes; \ + REG_WR( dma, inst, rw_cfg, s); } while( 0 ) + +// continue DMA channel operation +#define DMA_CONTINUE( inst ) \ + do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ + c.stop = regk_dma_no; \ + REG_WR( dma, inst, rw_cfg, c); } while( 0 ) + +// give stream command +#define DMA_WR_CMD( inst, cmd_par ) \ + do { reg_dma_rw_stream_cmd r = {0}; \ + do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \ + r.cmd = (cmd_par); \ + REG_WR( dma, inst, rw_stream_cmd, r ); \ + } while( 0 ) + +// load: g,c,d:burst +#define DMA_START_GROUP( inst, group_descr ) \ + do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ + DMA_WR_CMD( inst, regk_dma_load_g ); \ + DMA_WR_CMD( inst, regk_dma_load_c ); \ + DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ + } while( 0 ) + +// load: c,d:burst +#define DMA_START_CONTEXT( inst, ctx_descr ) \ + do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ + DMA_WR_CMD( inst, regk_dma_load_c ); \ + DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ + } while( 0 ) + +// if the DMA is at the end of the data list, the last data descr is reloaded +#define DMA_CONTINUE_DATA( inst ) \ +do { reg_dma_rw_cmd c = {0}; \ + c.cont_data = regk_dma_yes;\ + REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) + +#endif diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h new file mode 100644 index 000000000000..48ac8cef7ebe --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/dma_defs.h @@ -0,0 +1,436 @@ +#ifndef __dma_defs_h +#define __dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp + * last modfied: Mon Apr 11 16:06:51 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope dma */ + +/* Register rw_data, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data; +#define REG_RD_ADDR_dma_rw_data 0 +#define REG_WR_ADDR_dma_rw_data 0 + +/* Register rw_data_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_next; +#define REG_RD_ADDR_dma_rw_data_next 4 +#define REG_WR_ADDR_dma_rw_data_next 4 + +/* Register rw_data_buf, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_buf; +#define REG_RD_ADDR_dma_rw_data_buf 8 +#define REG_WR_ADDR_dma_rw_data_buf 8 + +/* Register rw_data_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int dummy1 : 2; + unsigned int out_eop : 1; + unsigned int intr : 1; + unsigned int wait : 1; + unsigned int dummy2 : 26; +} reg_dma_rw_data_ctrl; +#define REG_RD_ADDR_dma_rw_data_ctrl 12 +#define REG_WR_ADDR_dma_rw_data_ctrl 12 + +/* Register rw_data_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 3; + unsigned int in_eop : 1; + unsigned int dummy2 : 28; +} reg_dma_rw_data_stat; +#define REG_RD_ADDR_dma_rw_data_stat 16 +#define REG_WR_ADDR_dma_rw_data_stat 16 + +/* Register rw_data_md, scope dma, type rw */ +typedef struct { + unsigned int md : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_data_md; +#define REG_RD_ADDR_dma_rw_data_md 20 +#define REG_WR_ADDR_dma_rw_data_md 20 + +/* Register rw_data_md_s, scope dma, type rw */ +typedef struct { + unsigned int md_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_data_md_s; +#define REG_RD_ADDR_dma_rw_data_md_s 24 +#define REG_WR_ADDR_dma_rw_data_md_s 24 + +/* Register rw_data_after, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_after; +#define REG_RD_ADDR_dma_rw_data_after 28 +#define REG_WR_ADDR_dma_rw_data_after 28 + +/* Register rw_ctxt, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt; +#define REG_RD_ADDR_dma_rw_ctxt 32 +#define REG_WR_ADDR_dma_rw_ctxt 32 + +/* Register rw_ctxt_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_next; +#define REG_RD_ADDR_dma_rw_ctxt_next 36 +#define REG_WR_ADDR_dma_rw_ctxt_next 36 + +/* Register rw_ctxt_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int dummy1 : 3; + unsigned int intr : 1; + unsigned int dummy2 : 1; + unsigned int store_mode : 1; + unsigned int en : 1; + unsigned int dummy3 : 24; +} reg_dma_rw_ctxt_ctrl; +#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 +#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 + +/* Register rw_ctxt_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int dis : 1; + unsigned int dummy2 : 24; +} reg_dma_rw_ctxt_stat; +#define REG_RD_ADDR_dma_rw_ctxt_stat 44 +#define REG_WR_ADDR_dma_rw_ctxt_stat 44 + +/* Register rw_ctxt_md0, scope dma, type rw */ +typedef struct { + unsigned int md0 : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_ctxt_md0; +#define REG_RD_ADDR_dma_rw_ctxt_md0 48 +#define REG_WR_ADDR_dma_rw_ctxt_md0 48 + +/* Register rw_ctxt_md0_s, scope dma, type rw */ +typedef struct { + unsigned int md0_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_ctxt_md0_s; +#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 +#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 + +/* Register rw_ctxt_md1, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md1; +#define REG_RD_ADDR_dma_rw_ctxt_md1 56 +#define REG_WR_ADDR_dma_rw_ctxt_md1 56 + +/* Register rw_ctxt_md1_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md1_s; +#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 +#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 + +/* Register rw_ctxt_md2, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md2; +#define REG_RD_ADDR_dma_rw_ctxt_md2 64 +#define REG_WR_ADDR_dma_rw_ctxt_md2 64 + +/* Register rw_ctxt_md2_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md2_s; +#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 +#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 + +/* Register rw_ctxt_md3, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md3; +#define REG_RD_ADDR_dma_rw_ctxt_md3 72 +#define REG_WR_ADDR_dma_rw_ctxt_md3 72 + +/* Register rw_ctxt_md3_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md3_s; +#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 +#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 + +/* Register rw_ctxt_md4, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md4; +#define REG_RD_ADDR_dma_rw_ctxt_md4 80 +#define REG_WR_ADDR_dma_rw_ctxt_md4 80 + +/* Register rw_ctxt_md4_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md4_s; +#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 +#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 + +/* Register rw_saved_data, scope dma, type rw */ +typedef unsigned int reg_dma_rw_saved_data; +#define REG_RD_ADDR_dma_rw_saved_data 88 +#define REG_WR_ADDR_dma_rw_saved_data 88 + +/* Register rw_saved_data_buf, scope dma, type rw */ +typedef unsigned int reg_dma_rw_saved_data_buf; +#define REG_RD_ADDR_dma_rw_saved_data_buf 92 +#define REG_WR_ADDR_dma_rw_saved_data_buf 92 + +/* Register rw_group, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group; +#define REG_RD_ADDR_dma_rw_group 96 +#define REG_WR_ADDR_dma_rw_group 96 + +/* Register rw_group_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_next; +#define REG_RD_ADDR_dma_rw_group_next 100 +#define REG_WR_ADDR_dma_rw_group_next 100 + +/* Register rw_group_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int tol : 1; + unsigned int bol : 1; + unsigned int dummy1 : 1; + unsigned int intr : 1; + unsigned int dummy2 : 2; + unsigned int en : 1; + unsigned int dummy3 : 24; +} reg_dma_rw_group_ctrl; +#define REG_RD_ADDR_dma_rw_group_ctrl 104 +#define REG_WR_ADDR_dma_rw_group_ctrl 104 + +/* Register rw_group_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int dis : 1; + unsigned int dummy2 : 24; +} reg_dma_rw_group_stat; +#define REG_RD_ADDR_dma_rw_group_stat 108 +#define REG_WR_ADDR_dma_rw_group_stat 108 + +/* Register rw_group_md, scope dma, type rw */ +typedef struct { + unsigned int md : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_group_md; +#define REG_RD_ADDR_dma_rw_group_md 112 +#define REG_WR_ADDR_dma_rw_group_md 112 + +/* Register rw_group_md_s, scope dma, type rw */ +typedef struct { + unsigned int md_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_group_md_s; +#define REG_RD_ADDR_dma_rw_group_md_s 116 +#define REG_WR_ADDR_dma_rw_group_md_s 116 + +/* Register rw_group_up, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_up; +#define REG_RD_ADDR_dma_rw_group_up 120 +#define REG_WR_ADDR_dma_rw_group_up 120 + +/* Register rw_group_down, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_down; +#define REG_RD_ADDR_dma_rw_group_down 124 +#define REG_WR_ADDR_dma_rw_group_down 124 + +/* Register rw_cmd, scope dma, type rw */ +typedef struct { + unsigned int cont_data : 1; + unsigned int dummy1 : 31; +} reg_dma_rw_cmd; +#define REG_RD_ADDR_dma_rw_cmd 128 +#define REG_WR_ADDR_dma_rw_cmd 128 + +/* Register rw_cfg, scope dma, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int stop : 1; + unsigned int dummy1 : 30; +} reg_dma_rw_cfg; +#define REG_RD_ADDR_dma_rw_cfg 132 +#define REG_WR_ADDR_dma_rw_cfg 132 + +/* Register rw_stat, scope dma, type rw */ +typedef struct { + unsigned int mode : 5; + unsigned int list_state : 3; + unsigned int stream_cmd_src : 8; + unsigned int dummy1 : 8; + unsigned int buf : 8; +} reg_dma_rw_stat; +#define REG_RD_ADDR_dma_rw_stat 136 +#define REG_WR_ADDR_dma_rw_stat 136 + +/* Register rw_intr_mask, scope dma, type rw */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_rw_intr_mask; +#define REG_RD_ADDR_dma_rw_intr_mask 140 +#define REG_WR_ADDR_dma_rw_intr_mask 140 + +/* Register rw_ack_intr, scope dma, type rw */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_rw_ack_intr; +#define REG_RD_ADDR_dma_rw_ack_intr 144 +#define REG_WR_ADDR_dma_rw_ack_intr 144 + +/* Register r_intr, scope dma, type r */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_r_intr; +#define REG_RD_ADDR_dma_r_intr 148 + +/* Register r_masked_intr, scope dma, type r */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_r_masked_intr; +#define REG_RD_ADDR_dma_r_masked_intr 152 + +/* Register rw_stream_cmd, scope dma, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 7; + unsigned int busy : 1; +} reg_dma_rw_stream_cmd; +#define REG_RD_ADDR_dma_rw_stream_cmd 156 +#define REG_WR_ADDR_dma_rw_stream_cmd 156 + + +/* Constants */ +enum { + regk_dma_ack_pkt = 0x00000100, + regk_dma_anytime = 0x00000001, + regk_dma_array = 0x00000008, + regk_dma_burst = 0x00000020, + regk_dma_client = 0x00000002, + regk_dma_copy_next = 0x00000010, + regk_dma_copy_up = 0x00000020, + regk_dma_data_at_eol = 0x00000001, + regk_dma_dis_c = 0x00000010, + regk_dma_dis_g = 0x00000020, + regk_dma_idle = 0x00000001, + regk_dma_intern = 0x00000004, + regk_dma_load_c = 0x00000200, + regk_dma_load_c_n = 0x00000280, + regk_dma_load_c_next = 0x00000240, + regk_dma_load_d = 0x00000140, + regk_dma_load_g = 0x00000300, + regk_dma_load_g_down = 0x000003c0, + regk_dma_load_g_next = 0x00000340, + regk_dma_load_g_up = 0x00000380, + regk_dma_next_en = 0x00000010, + regk_dma_next_pkt = 0x00000010, + regk_dma_no = 0x00000000, + regk_dma_only_at_wait = 0x00000000, + regk_dma_restore = 0x00000020, + regk_dma_rst = 0x00000001, + regk_dma_running = 0x00000004, + regk_dma_rw_cfg_default = 0x00000000, + regk_dma_rw_cmd_default = 0x00000000, + regk_dma_rw_intr_mask_default = 0x00000000, + regk_dma_rw_stat_default = 0x00000101, + regk_dma_rw_stream_cmd_default = 0x00000000, + regk_dma_save_down = 0x00000020, + regk_dma_save_up = 0x00000020, + regk_dma_set_reg = 0x00000050, + regk_dma_set_w_size1 = 0x00000190, + regk_dma_set_w_size2 = 0x000001a0, + regk_dma_set_w_size4 = 0x000001c0, + regk_dma_stopped = 0x00000002, + regk_dma_store_c = 0x00000002, + regk_dma_store_descr = 0x00000000, + regk_dma_store_g = 0x00000004, + regk_dma_store_md = 0x00000001, + regk_dma_sw = 0x00000008, + regk_dma_update_down = 0x00000020, + regk_dma_yes = 0x00000001 +}; +#endif /* __dma_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h new file mode 100644 index 000000000000..1196d7cc783f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/eth_defs.h @@ -0,0 +1,384 @@ +#ifndef __eth_defs_h +#define __eth_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/eth/rtl/eth_regs.r + * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp + * last modfied: Mon Apr 11 16:07:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r + * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope eth */ + +/* Register rw_ma0_lo, scope eth, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_eth_rw_ma0_lo; +#define REG_RD_ADDR_eth_rw_ma0_lo 0 +#define REG_WR_ADDR_eth_rw_ma0_lo 0 + +/* Register rw_ma0_hi, scope eth, type rw */ +typedef struct { + unsigned int addr : 16; + unsigned int dummy1 : 16; +} reg_eth_rw_ma0_hi; +#define REG_RD_ADDR_eth_rw_ma0_hi 4 +#define REG_WR_ADDR_eth_rw_ma0_hi 4 + +/* Register rw_ma1_lo, scope eth, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_eth_rw_ma1_lo; +#define REG_RD_ADDR_eth_rw_ma1_lo 8 +#define REG_WR_ADDR_eth_rw_ma1_lo 8 + +/* Register rw_ma1_hi, scope eth, type rw */ +typedef struct { + unsigned int addr : 16; + unsigned int dummy1 : 16; +} reg_eth_rw_ma1_hi; +#define REG_RD_ADDR_eth_rw_ma1_hi 12 +#define REG_WR_ADDR_eth_rw_ma1_hi 12 + +/* Register rw_ga_lo, scope eth, type rw */ +typedef struct { + unsigned int table : 32; +} reg_eth_rw_ga_lo; +#define REG_RD_ADDR_eth_rw_ga_lo 16 +#define REG_WR_ADDR_eth_rw_ga_lo 16 + +/* Register rw_ga_hi, scope eth, type rw */ +typedef struct { + unsigned int table : 32; +} reg_eth_rw_ga_hi; +#define REG_RD_ADDR_eth_rw_ga_hi 20 +#define REG_WR_ADDR_eth_rw_ga_hi 20 + +/* Register rw_gen_ctrl, scope eth, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int phy : 2; + unsigned int protocol : 1; + unsigned int loopback : 1; + unsigned int flow_ctrl_dis : 1; + unsigned int dummy1 : 26; +} reg_eth_rw_gen_ctrl; +#define REG_RD_ADDR_eth_rw_gen_ctrl 24 +#define REG_WR_ADDR_eth_rw_gen_ctrl 24 + +/* Register rw_rec_ctrl, scope eth, type rw */ +typedef struct { + unsigned int ma0 : 1; + unsigned int ma1 : 1; + unsigned int individual : 1; + unsigned int broadcast : 1; + unsigned int undersize : 1; + unsigned int oversize : 1; + unsigned int bad_crc : 1; + unsigned int duplex : 1; + unsigned int max_size : 1; + unsigned int dummy1 : 23; +} reg_eth_rw_rec_ctrl; +#define REG_RD_ADDR_eth_rw_rec_ctrl 28 +#define REG_WR_ADDR_eth_rw_rec_ctrl 28 + +/* Register rw_tr_ctrl, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int pad : 1; + unsigned int retry : 1; + unsigned int ignore_col : 1; + unsigned int cancel : 1; + unsigned int hsh_delay : 1; + unsigned int ignore_crs : 1; + unsigned int dummy1 : 25; +} reg_eth_rw_tr_ctrl; +#define REG_RD_ADDR_eth_rw_tr_ctrl 32 +#define REG_WR_ADDR_eth_rw_tr_ctrl 32 + +/* Register rw_clr_err, scope eth, type rw */ +typedef struct { + unsigned int clr : 1; + unsigned int dummy1 : 31; +} reg_eth_rw_clr_err; +#define REG_RD_ADDR_eth_rw_clr_err 36 +#define REG_WR_ADDR_eth_rw_clr_err 36 + +/* Register rw_mgm_ctrl, scope eth, type rw */ +typedef struct { + unsigned int mdio : 1; + unsigned int mdoe : 1; + unsigned int mdc : 1; + unsigned int phyclk : 1; + unsigned int txdata : 4; + unsigned int txen : 1; + unsigned int dummy1 : 23; +} reg_eth_rw_mgm_ctrl; +#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 +#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 + +/* Register r_stat, scope eth, type r */ +typedef struct { + unsigned int mdio : 1; + unsigned int exc_col : 1; + unsigned int urun : 1; + unsigned int phyclk : 1; + unsigned int txdata : 4; + unsigned int txen : 1; + unsigned int col : 1; + unsigned int crs : 1; + unsigned int txclk : 1; + unsigned int rxdata : 4; + unsigned int rxer : 1; + unsigned int rxdv : 1; + unsigned int rxclk : 1; + unsigned int dummy1 : 13; +} reg_eth_r_stat; +#define REG_RD_ADDR_eth_r_stat 44 + +/* Register rs_rec_cnt, scope eth, type rs */ +typedef struct { + unsigned int crc_err : 8; + unsigned int align_err : 8; + unsigned int oversize : 8; + unsigned int congestion : 8; +} reg_eth_rs_rec_cnt; +#define REG_RD_ADDR_eth_rs_rec_cnt 48 + +/* Register r_rec_cnt, scope eth, type r */ +typedef struct { + unsigned int crc_err : 8; + unsigned int align_err : 8; + unsigned int oversize : 8; + unsigned int congestion : 8; +} reg_eth_r_rec_cnt; +#define REG_RD_ADDR_eth_r_rec_cnt 52 + +/* Register rs_tr_cnt, scope eth, type rs */ +typedef struct { + unsigned int single_col : 8; + unsigned int mult_col : 8; + unsigned int late_col : 8; + unsigned int deferred : 8; +} reg_eth_rs_tr_cnt; +#define REG_RD_ADDR_eth_rs_tr_cnt 56 + +/* Register r_tr_cnt, scope eth, type r */ +typedef struct { + unsigned int single_col : 8; + unsigned int mult_col : 8; + unsigned int late_col : 8; + unsigned int deferred : 8; +} reg_eth_r_tr_cnt; +#define REG_RD_ADDR_eth_r_tr_cnt 60 + +/* Register rs_phy_cnt, scope eth, type rs */ +typedef struct { + unsigned int carrier_loss : 8; + unsigned int sqe_err : 8; + unsigned int dummy1 : 16; +} reg_eth_rs_phy_cnt; +#define REG_RD_ADDR_eth_rs_phy_cnt 64 + +/* Register r_phy_cnt, scope eth, type r */ +typedef struct { + unsigned int carrier_loss : 8; + unsigned int sqe_err : 8; + unsigned int dummy1 : 16; +} reg_eth_r_phy_cnt; +#define REG_RD_ADDR_eth_r_phy_cnt 68 + +/* Register rw_test_ctrl, scope eth, type rw */ +typedef struct { + unsigned int snmp_inc : 1; + unsigned int snmp : 1; + unsigned int backoff : 1; + unsigned int dummy1 : 29; +} reg_eth_rw_test_ctrl; +#define REG_RD_ADDR_eth_rw_test_ctrl 72 +#define REG_WR_ADDR_eth_rw_test_ctrl 72 + +/* Register rw_intr_mask, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int excessive_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_rw_intr_mask; +#define REG_RD_ADDR_eth_rw_intr_mask 76 +#define REG_WR_ADDR_eth_rw_intr_mask 76 + +/* Register rw_ack_intr, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int excessive_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_rw_ack_intr; +#define REG_RD_ADDR_eth_rw_ack_intr 80 +#define REG_WR_ADDR_eth_rw_ack_intr 80 + +/* Register r_intr, scope eth, type r */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int excessive_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_r_intr; +#define REG_RD_ADDR_eth_r_intr 84 + +/* Register r_masked_intr, scope eth, type r */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int excessive_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_r_masked_intr; +#define REG_RD_ADDR_eth_r_masked_intr 88 + + +/* Constants */ +enum { + regk_eth_discard = 0x00000000, + regk_eth_ether = 0x00000000, + regk_eth_full = 0x00000001, + regk_eth_half = 0x00000000, + regk_eth_hsh = 0x00000001, + regk_eth_mii = 0x00000001, + regk_eth_mii_clk = 0x00000000, + regk_eth_mii_rec = 0x00000002, + regk_eth_no = 0x00000000, + regk_eth_rec = 0x00000001, + regk_eth_rw_ga_hi_default = 0x00000000, + regk_eth_rw_ga_lo_default = 0x00000000, + regk_eth_rw_gen_ctrl_default = 0x00000000, + regk_eth_rw_intr_mask_default = 0x00000000, + regk_eth_rw_ma0_hi_default = 0x00000000, + regk_eth_rw_ma0_lo_default = 0x00000000, + regk_eth_rw_ma1_hi_default = 0x00000000, + regk_eth_rw_ma1_lo_default = 0x00000000, + regk_eth_rw_mgm_ctrl_default = 0x00000000, + regk_eth_rw_test_ctrl_default = 0x00000000, + regk_eth_size1518 = 0x00000000, + regk_eth_size1522 = 0x00000001, + regk_eth_yes = 0x00000001 +}; +#endif /* __eth_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h new file mode 100644 index 000000000000..c47b5ca48ece --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/extmem_defs.h @@ -0,0 +1,369 @@ +#ifndef __extmem_defs_h +#define __extmem_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ext_mem/mod/extmem_regs.r + * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp + * last modfied: Tue Mar 30 22:26:21 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r + * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope extmem */ + +/* Register rw_cse0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_cse0_cfg; +#define REG_RD_ADDR_extmem_rw_cse0_cfg 0 +#define REG_WR_ADDR_extmem_rw_cse0_cfg 0 + +/* Register rw_cse1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_cse1_cfg; +#define REG_RD_ADDR_extmem_rw_cse1_cfg 4 +#define REG_WR_ADDR_extmem_rw_cse1_cfg 4 + +/* Register rw_csr0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csr0_cfg; +#define REG_RD_ADDR_extmem_rw_csr0_cfg 8 +#define REG_WR_ADDR_extmem_rw_csr0_cfg 8 + +/* Register rw_csr1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csr1_cfg; +#define REG_RD_ADDR_extmem_rw_csr1_cfg 12 +#define REG_WR_ADDR_extmem_rw_csr1_cfg 12 + +/* Register rw_csp0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp0_cfg; +#define REG_RD_ADDR_extmem_rw_csp0_cfg 16 +#define REG_WR_ADDR_extmem_rw_csp0_cfg 16 + +/* Register rw_csp1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp1_cfg; +#define REG_RD_ADDR_extmem_rw_csp1_cfg 20 +#define REG_WR_ADDR_extmem_rw_csp1_cfg 20 + +/* Register rw_csp2_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp2_cfg; +#define REG_RD_ADDR_extmem_rw_csp2_cfg 24 +#define REG_WR_ADDR_extmem_rw_csp2_cfg 24 + +/* Register rw_csp3_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp3_cfg; +#define REG_RD_ADDR_extmem_rw_csp3_cfg 28 +#define REG_WR_ADDR_extmem_rw_csp3_cfg 28 + +/* Register rw_csp4_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp4_cfg; +#define REG_RD_ADDR_extmem_rw_csp4_cfg 32 +#define REG_WR_ADDR_extmem_rw_csp4_cfg 32 + +/* Register rw_csp5_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp5_cfg; +#define REG_RD_ADDR_extmem_rw_csp5_cfg 36 +#define REG_WR_ADDR_extmem_rw_csp5_cfg 36 + +/* Register rw_csp6_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp6_cfg; +#define REG_RD_ADDR_extmem_rw_csp6_cfg 40 +#define REG_WR_ADDR_extmem_rw_csp6_cfg 40 + +/* Register rw_css_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_css_cfg; +#define REG_RD_ADDR_extmem_rw_css_cfg 44 +#define REG_WR_ADDR_extmem_rw_css_cfg 44 + +/* Register rw_status_handle, scope extmem, type rw */ +typedef struct { + unsigned int h : 32; +} reg_extmem_rw_status_handle; +#define REG_RD_ADDR_extmem_rw_status_handle 48 +#define REG_WR_ADDR_extmem_rw_status_handle 48 + +/* Register rw_wait_pin, scope extmem, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 15; + unsigned int start : 1; +} reg_extmem_rw_wait_pin; +#define REG_RD_ADDR_extmem_rw_wait_pin 52 +#define REG_WR_ADDR_extmem_rw_wait_pin 52 + +/* Register rw_gated_csp, scope extmem, type rw */ +typedef struct { + unsigned int dummy1 : 31; + unsigned int en : 1; +} reg_extmem_rw_gated_csp; +#define REG_RD_ADDR_extmem_rw_gated_csp 56 +#define REG_WR_ADDR_extmem_rw_gated_csp 56 + + +/* Constants */ +enum { + regk_extmem_b16 = 0x00000001, + regk_extmem_b32 = 0x00000000, + regk_extmem_bwe = 0x00000000, + regk_extmem_cwe = 0x00000001, + regk_extmem_no = 0x00000000, + regk_extmem_rw_cse0_cfg_default = 0x000006cf, + regk_extmem_rw_cse1_cfg_default = 0x000006cf, + regk_extmem_rw_csp0_cfg_default = 0x000006cf, + regk_extmem_rw_csp1_cfg_default = 0x000006cf, + regk_extmem_rw_csp2_cfg_default = 0x000006cf, + regk_extmem_rw_csp3_cfg_default = 0x000006cf, + regk_extmem_rw_csp4_cfg_default = 0x000006cf, + regk_extmem_rw_csp5_cfg_default = 0x000006cf, + regk_extmem_rw_csp6_cfg_default = 0x000006cf, + regk_extmem_rw_csr0_cfg_default = 0x000006cf, + regk_extmem_rw_csr1_cfg_default = 0x000006cf, + regk_extmem_rw_css_cfg_default = 0x000006cf, + regk_extmem_s128KB = 0x00000000, + regk_extmem_s16MB = 0x00000005, + regk_extmem_s1MB = 0x00000001, + regk_extmem_s2MB = 0x00000002, + regk_extmem_s32MB = 0x00000006, + regk_extmem_s4MB = 0x00000003, + regk_extmem_s64MB = 0x00000007, + regk_extmem_s8MB = 0x00000004, + regk_extmem_yes = 0x00000001 +}; +#endif /* __extmem_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h new file mode 100644 index 000000000000..3e9a0b25366f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/gio_defs.h @@ -0,0 +1,295 @@ +#ifndef __gio_defs_h +#define __gio_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope gio */ + +/* Register rw_pa_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_dout; +#define REG_RD_ADDR_gio_rw_pa_dout 0 +#define REG_WR_ADDR_gio_rw_pa_dout 0 + +/* Register r_pa_din, scope gio, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_r_pa_din; +#define REG_RD_ADDR_gio_r_pa_din 4 + +/* Register rw_pa_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_oe; +#define REG_RD_ADDR_gio_rw_pa_oe 8 +#define REG_WR_ADDR_gio_rw_pa_oe 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 3; + unsigned int pa1 : 3; + unsigned int pa2 : 3; + unsigned int pa3 : 3; + unsigned int pa4 : 3; + unsigned int pa5 : 3; + unsigned int pa6 : 3; + unsigned int pa7 : 3; + unsigned int dummy1 : 8; +} reg_gio_rw_intr_cfg; +#define REG_RD_ADDR_gio_rw_intr_cfg 12 +#define REG_WR_ADDR_gio_rw_intr_cfg 12 + +/* Register rw_intr_mask, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_intr_mask; +#define REG_RD_ADDR_gio_rw_intr_mask 16 +#define REG_WR_ADDR_gio_rw_intr_mask 16 + +/* Register rw_ack_intr, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_ack_intr; +#define REG_RD_ADDR_gio_rw_ack_intr 20 +#define REG_WR_ADDR_gio_rw_ack_intr 20 + +/* Register r_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_intr; +#define REG_RD_ADDR_gio_r_intr 24 + +/* Register r_masked_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_masked_intr; +#define REG_RD_ADDR_gio_r_masked_intr 28 + +/* Register rw_pb_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_dout; +#define REG_RD_ADDR_gio_rw_pb_dout 32 +#define REG_WR_ADDR_gio_rw_pb_dout 32 + +/* Register r_pb_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pb_din; +#define REG_RD_ADDR_gio_r_pb_din 36 + +/* Register rw_pb_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_oe; +#define REG_RD_ADDR_gio_rw_pb_oe 40 +#define REG_WR_ADDR_gio_rw_pb_oe 40 + +/* Register rw_pc_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_dout; +#define REG_RD_ADDR_gio_rw_pc_dout 48 +#define REG_WR_ADDR_gio_rw_pc_dout 48 + +/* Register r_pc_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pc_din; +#define REG_RD_ADDR_gio_r_pc_din 52 + +/* Register rw_pc_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_oe; +#define REG_RD_ADDR_gio_rw_pc_oe 56 +#define REG_WR_ADDR_gio_rw_pc_oe 56 + +/* Register rw_pd_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_dout; +#define REG_RD_ADDR_gio_rw_pd_dout 64 +#define REG_WR_ADDR_gio_rw_pd_dout 64 + +/* Register r_pd_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pd_din; +#define REG_RD_ADDR_gio_r_pd_din 68 + +/* Register rw_pd_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_oe; +#define REG_RD_ADDR_gio_rw_pd_oe 72 +#define REG_WR_ADDR_gio_rw_pd_oe 72 + +/* Register rw_pe_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_dout; +#define REG_RD_ADDR_gio_rw_pe_dout 80 +#define REG_WR_ADDR_gio_rw_pe_dout 80 + +/* Register r_pe_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pe_din; +#define REG_RD_ADDR_gio_r_pe_din 84 + +/* Register rw_pe_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_oe; +#define REG_RD_ADDR_gio_rw_pe_oe 88 +#define REG_WR_ADDR_gio_rw_pe_oe 88 + + +/* Constants */ +enum { + regk_gio_anyedge = 0x00000007, + regk_gio_hi = 0x00000001, + regk_gio_lo = 0x00000002, + regk_gio_negedge = 0x00000006, + regk_gio_no = 0x00000000, + regk_gio_off = 0x00000000, + regk_gio_posedge = 0x00000005, + regk_gio_rw_intr_cfg_default = 0x00000000, + regk_gio_rw_intr_mask_default = 0x00000000, + regk_gio_rw_pa_oe_default = 0x00000000, + regk_gio_rw_pb_oe_default = 0x00000000, + regk_gio_rw_pc_oe_default = 0x00000000, + regk_gio_rw_pd_oe_default = 0x00000000, + regk_gio_rw_pe_oe_default = 0x00000000, + regk_gio_set = 0x00000003, + regk_gio_yes = 0x00000001 +}; +#endif /* __gio_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h new file mode 100644 index 000000000000..5c1b28fb205d --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/intr_vect.h @@ -0,0 +1,39 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/intr_vect/rtl/guinness/ivmask.config.r +version . */ + +#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define MEMARB_INTR_VECT 0x31 +#define GEN_IO_INTR_VECT 0x32 +#define IOP0_INTR_VECT 0x33 +#define IOP1_INTR_VECT 0x34 +#define IOP2_INTR_VECT 0x35 +#define IOP3_INTR_VECT 0x36 +#define DMA0_INTR_VECT 0x37 +#define DMA1_INTR_VECT 0x38 +#define DMA2_INTR_VECT 0x39 +#define DMA3_INTR_VECT 0x3a +#define DMA4_INTR_VECT 0x3b +#define DMA5_INTR_VECT 0x3c +#define DMA6_INTR_VECT 0x3d +#define DMA7_INTR_VECT 0x3e +#define DMA8_INTR_VECT 0x3f +#define DMA9_INTR_VECT 0x40 +#define ATA_INTR_VECT 0x41 +#define SSER0_INTR_VECT 0x42 +#define SSER1_INTR_VECT 0x43 +#define SER0_INTR_VECT 0x44 +#define SER1_INTR_VECT 0x45 +#define SER2_INTR_VECT 0x46 +#define SER3_INTR_VECT 0x47 +#define P21_INTR_VECT 0x48 +#define ETH0_INTR_VECT 0x49 +#define ETH1_INTR_VECT 0x4a +#define TIMER_INTR_VECT 0x4b +#define BIF_ARB_INTR_VECT 0x4c +#define BIF_DMA_INTR_VECT 0x4d +#define EXT_INTR_VECT 0x4e +#define IPI_INTR_VECT 0x4f + +#endif diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h new file mode 100644 index 000000000000..535aaf1b4b52 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h @@ -0,0 +1,225 @@ +#ifndef __intr_vect_defs_h +#define __intr_vect_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp + * last modfied: Mon Apr 11 16:08:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope intr_vect */ + +/* Register rw_mask, scope intr_vect, type rw */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_rw_mask; +#define REG_RD_ADDR_intr_vect_rw_mask 0 +#define REG_WR_ADDR_intr_vect_rw_mask 0 + +/* Register r_vect, scope intr_vect, type r */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_r_vect; +#define REG_RD_ADDR_intr_vect_r_vect 4 + +/* Register r_masked_vect, scope intr_vect, type r */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_r_masked_vect; +#define REG_RD_ADDR_intr_vect_r_masked_vect 8 + +/* Register r_nmi, scope intr_vect, type r */ +typedef struct { + unsigned int ext : 1; + unsigned int watchdog : 1; + unsigned int dummy1 : 30; +} reg_intr_vect_r_nmi; +#define REG_RD_ADDR_intr_vect_r_nmi 12 + +/* Register r_guru, scope intr_vect, type r */ +typedef struct { + unsigned int jtag : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_r_guru; +#define REG_RD_ADDR_intr_vect_r_guru 16 + +/* Register rw_ipi, scope intr_vect, type rw */ +typedef struct +{ + unsigned int vector; +} reg_intr_vect_rw_ipi; +#define REG_RD_ADDR_intr_vect_rw_ipi 20 +#define REG_WR_ADDR_intr_vect_rw_ipi 20 + +/* Constants */ +enum { + regk_intr_vect_off = 0x00000000, + regk_intr_vect_on = 0x00000001, + regk_intr_vect_rw_mask_default = 0x00000000 +}; +#endif /* __intr_vect_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile new file mode 100644 index 000000000000..a90056a095e3 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/Makefile @@ -0,0 +1,146 @@ +# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ +# Makefile to generate or copy the latest register definitions +# and related datastructures and helpermacros. +# The offical place for these files is probably at: +RELEASE ?= r1_alfa5 +IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ + +IOPROCDIR = /n/asic/design/io/io_proc/rtl + +IOPROCINCL_FILES = +IOPROCINCL_FILES2= +IOPROCINCL_FILES += iop_crc_par_defs.h +IOPROCINCL_FILES += iop_dmc_in_defs.h +IOPROCINCL_FILES += iop_dmc_out_defs.h +IOPROCINCL_FILES += iop_fifo_in_defs.h +IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h +IOPROCINCL_FILES += iop_fifo_out_defs.h +IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h +IOPROCINCL_FILES += iop_mpu_defs.h +IOPROCINCL_FILES2+= iop_mpu_macros.h +IOPROCINCL_FILES2+= iop_reg_space.h +IOPROCINCL_FILES += iop_sap_in_defs.h +IOPROCINCL_FILES += iop_sap_out_defs.h +IOPROCINCL_FILES += iop_scrc_in_defs.h +IOPROCINCL_FILES += iop_scrc_out_defs.h +IOPROCINCL_FILES += iop_spu_defs.h +# in guiness/ +IOPROCINCL_FILES += iop_sw_cfg_defs.h +IOPROCINCL_FILES += iop_sw_cpu_defs.h +IOPROCINCL_FILES += iop_sw_mpu_defs.h +IOPROCINCL_FILES += iop_sw_spu_defs.h +# +IOPROCINCL_FILES += iop_timer_grp_defs.h +IOPROCINCL_FILES += iop_trigger_grp_defs.h +# in guiness/ +IOPROCINCL_FILES += iop_version_defs.h + +IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) +IOPROCASMINCL_FILES+= iop_reg_space_asm.h + + +IOPROCREGDESC = +IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r +#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r +IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r +IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r +IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r +IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r +IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r + + +RDES2C = /n/asic/bin/rdes2c +RDES2C = /n/asic/design/tools/rdesc/rdes2c +RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr +RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt + +## all - Just print help - you probably want to do 'make gen' +all: help + +## help - This help +help: + @grep '^## ' Makefile + +## gen - Generate include files +gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) + echo "INCL: $(IOPROCINCL_FILES)" + echo "INCL2: $(IOPROCINCL_FILES2)" + echo "ASMINCL: $(IOPROCASMINCL_FILES)" + +# From the official location... +iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ + +## copy - Copy files from official location +copy: + @echo "## Copying and fixing iop files ##" + @for HFILE in $(IOPROCINCL_FILES); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @for HFILE in $(IOPROCINCL_FILES2); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @echo "## Copying and fixing iop asm files ##" + @for HFILE in $(IOPROCASMINCL_FILES); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ + done + +# I/O processor files: +## iop - Generate I/O processor include files +iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) +iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r + $(RDES2C) $< +iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r + $(RDES2C) $< +%_defs.h: $(IOPROCDIR)/%.r + $(RDES2C) $< +%_defs_asm.h: $(IOPROCDIR)/%.r + $(RDES2C) -asm $< +iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r + $(RDES2C) -asm $< + +## doc - Generate .axw files from register description. +doc: $(IOPROCREGDESC) + for RDES in $^; do \ + $(RDES2TXT) $$RDES; \ + done + +.PHONY: axw +## %.axw - Generate the specified .axw file (doesn't work for all files +## due to inconsistent naming of .r files. +%.axw: axw + @for RDES in $(IOPROCREGDESC); do \ + if echo "$$RDES" | grep $* ; then \ + $(RDES2TXT) $$RDES; \ + fi \ + done + +.PHONY: clean +## clean - Remove .h files and .axw files. +clean: + rm -rf $(IOPROCINCL_FILES) *.axw + +.PHONY: cleandoc +## cleandoc - Remove .axw files. +cleandoc: + rm -rf *.axw + diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h new file mode 100644 index 000000000000..a4b58000c164 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h @@ -0,0 +1,171 @@ +#ifndef __iop_crc_par_defs_asm_h +#define __iop_crc_par_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_crc_par.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r + * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_cfg___mode___lsb 0 +#define reg_iop_crc_par_rw_cfg___mode___width 1 +#define reg_iop_crc_par_rw_cfg___mode___bit 0 +#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 +#define reg_iop_crc_par_rw_cfg___crc_out___width 1 +#define reg_iop_crc_par_rw_cfg___crc_out___bit 1 +#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 +#define reg_iop_crc_par_rw_cfg___rev_out___width 1 +#define reg_iop_crc_par_rw_cfg___rev_out___bit 2 +#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 +#define reg_iop_crc_par_rw_cfg___inv_out___width 1 +#define reg_iop_crc_par_rw_cfg___inv_out___bit 3 +#define reg_iop_crc_par_rw_cfg___trig___lsb 4 +#define reg_iop_crc_par_rw_cfg___trig___width 2 +#define reg_iop_crc_par_rw_cfg___poly___lsb 6 +#define reg_iop_crc_par_rw_cfg___poly___width 3 +#define reg_iop_crc_par_rw_cfg_offset 0 + +/* Register rw_init_crc, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_init_crc_offset 4 + +/* Register rw_correct_crc, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_correct_crc_offset 8 + +/* Register rw_ctrl, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_ctrl___en___lsb 0 +#define reg_iop_crc_par_rw_ctrl___en___width 1 +#define reg_iop_crc_par_rw_ctrl___en___bit 0 +#define reg_iop_crc_par_rw_ctrl_offset 12 + +/* Register rw_set_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 +#define reg_iop_crc_par_rw_set_last___tr_dif___width 1 +#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 +#define reg_iop_crc_par_rw_set_last_offset 16 + +/* Register rw_wr1byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr1byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr1byte___data___width 8 +#define reg_iop_crc_par_rw_wr1byte_offset 20 + +/* Register rw_wr2byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr2byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr2byte___data___width 16 +#define reg_iop_crc_par_rw_wr2byte_offset 24 + +/* Register rw_wr3byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr3byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr3byte___data___width 24 +#define reg_iop_crc_par_rw_wr3byte_offset 28 + +/* Register rw_wr4byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr4byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr4byte___data___width 32 +#define reg_iop_crc_par_rw_wr4byte_offset 32 + +/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr1byte_last___data___width 8 +#define reg_iop_crc_par_rw_wr1byte_last_offset 36 + +/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr2byte_last___data___width 16 +#define reg_iop_crc_par_rw_wr2byte_last_offset 40 + +/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr3byte_last___data___width 24 +#define reg_iop_crc_par_rw_wr3byte_last_offset 44 + +/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr4byte_last___data___width 32 +#define reg_iop_crc_par_rw_wr4byte_last_offset 48 + +/* Register r_stat, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_stat___err___lsb 0 +#define reg_iop_crc_par_r_stat___err___width 1 +#define reg_iop_crc_par_r_stat___err___bit 0 +#define reg_iop_crc_par_r_stat___busy___lsb 1 +#define reg_iop_crc_par_r_stat___busy___width 1 +#define reg_iop_crc_par_r_stat___busy___bit 1 +#define reg_iop_crc_par_r_stat_offset 52 + +/* Register r_sh_reg, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_sh_reg_offset 56 + +/* Register r_crc, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_crc_offset 60 + +/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 +#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 +#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 + + +/* Constants */ +#define regk_iop_crc_par_calc 0x00000001 +#define regk_iop_crc_par_ccitt 0x00000002 +#define regk_iop_crc_par_check 0x00000000 +#define regk_iop_crc_par_crc16 0x00000001 +#define regk_iop_crc_par_crc32 0x00000000 +#define regk_iop_crc_par_crc5 0x00000003 +#define regk_iop_crc_par_crc5_11 0x00000004 +#define regk_iop_crc_par_dif_in 0x00000002 +#define regk_iop_crc_par_hi 0x00000000 +#define regk_iop_crc_par_neg 0x00000002 +#define regk_iop_crc_par_no 0x00000000 +#define regk_iop_crc_par_pos 0x00000001 +#define regk_iop_crc_par_pos_neg 0x00000003 +#define regk_iop_crc_par_rw_cfg_default 0x00000000 +#define regk_iop_crc_par_rw_ctrl_default 0x00000000 +#define regk_iop_crc_par_yes 0x00000001 +#endif /* __iop_crc_par_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h new file mode 100644 index 000000000000..e7d539feccb1 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h @@ -0,0 +1,321 @@ +#ifndef __iop_dmc_in_defs_asm_h +#define __iop_dmc_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_in.r + * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r + * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 +#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 +#define reg_iop_dmc_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 +#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 +#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 +#define reg_iop_dmc_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_stat___dif_en___lsb 0 +#define reg_iop_dmc_in_r_stat___dif_en___width 1 +#define reg_iop_dmc_in_r_stat___dif_en___bit 0 +#define reg_iop_dmc_in_r_stat_offset 8 + +/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 +#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 +#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 +#define reg_iop_dmc_in_rw_stream_cmd___n___width 8 +#define reg_iop_dmc_in_rw_stream_cmd_offset 12 + +/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_wr_data_offset 16 + +/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 + +/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 +#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 +#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 +#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 +#define reg_iop_dmc_in_rw_stream_ctrl_offset 24 + +/* Register r_stream_stat, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 +#define reg_iop_dmc_in_r_stream_stat___sth___width 7 +#define reg_iop_dmc_in_r_stream_stat___full___lsb 16 +#define reg_iop_dmc_in_r_stream_stat___full___width 1 +#define reg_iop_dmc_in_r_stream_stat___full___bit 16 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 +#define reg_iop_dmc_in_r_stream_stat_offset 28 + +/* Register r_data_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_data_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_data_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_data_descr___stat___width 8 +#define reg_iop_dmc_in_r_data_descr___md___lsb 16 +#define reg_iop_dmc_in_r_data_descr___md___width 16 +#define reg_iop_dmc_in_r_data_descr_offset 32 + +/* Register r_ctxt_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 +#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 +#define reg_iop_dmc_in_r_ctxt_descr_offset 36 + +/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 + +/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 + +/* Register r_group_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_group_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_group_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_group_descr___stat___width 8 +#define reg_iop_dmc_in_r_group_descr___md___lsb 16 +#define reg_iop_dmc_in_r_group_descr___md___width 16 +#define reg_iop_dmc_in_r_group_descr_offset 56 + +/* Register rw_data_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_data_descr___md___lsb 16 +#define reg_iop_dmc_in_rw_data_descr___md___width 16 +#define reg_iop_dmc_in_rw_data_descr_offset 60 + +/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 +#define reg_iop_dmc_in_rw_ctxt_descr_offset 64 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 + +/* Register rw_group_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_group_descr___md___lsb 16 +#define reg_iop_dmc_in_rw_group_descr___md___width 16 +#define reg_iop_dmc_in_rw_group_descr_offset 84 + +/* Register rw_intr_mask, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 +#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 +#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 +#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 +#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 +#define reg_iop_dmc_in_rw_intr_mask___sth___width 1 +#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 +#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 +#define reg_iop_dmc_in_rw_intr_mask___full___width 1 +#define reg_iop_dmc_in_rw_intr_mask___full___bit 5 +#define reg_iop_dmc_in_rw_intr_mask_offset 88 + +/* Register rw_ack_intr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 +#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 +#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 +#define reg_iop_dmc_in_rw_ack_intr___sth___width 1 +#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 +#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 +#define reg_iop_dmc_in_rw_ack_intr___full___width 1 +#define reg_iop_dmc_in_rw_ack_intr___full___bit 5 +#define reg_iop_dmc_in_rw_ack_intr_offset 92 + +/* Register r_intr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_intr___data_md___lsb 0 +#define reg_iop_dmc_in_r_intr___data_md___width 1 +#define reg_iop_dmc_in_r_intr___data_md___bit 0 +#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_r_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_r_intr___group_md___lsb 2 +#define reg_iop_dmc_in_r_intr___group_md___width 1 +#define reg_iop_dmc_in_r_intr___group_md___bit 2 +#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_r_intr___sth___lsb 4 +#define reg_iop_dmc_in_r_intr___sth___width 1 +#define reg_iop_dmc_in_r_intr___sth___bit 4 +#define reg_iop_dmc_in_r_intr___full___lsb 5 +#define reg_iop_dmc_in_r_intr___full___width 1 +#define reg_iop_dmc_in_r_intr___full___bit 5 +#define reg_iop_dmc_in_r_intr_offset 96 + +/* Register r_masked_intr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 +#define reg_iop_dmc_in_r_masked_intr___data_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 +#define reg_iop_dmc_in_r_masked_intr___group_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 +#define reg_iop_dmc_in_r_masked_intr___sth___width 1 +#define reg_iop_dmc_in_r_masked_intr___sth___bit 4 +#define reg_iop_dmc_in_r_masked_intr___full___lsb 5 +#define reg_iop_dmc_in_r_masked_intr___full___width 1 +#define reg_iop_dmc_in_r_masked_intr___full___bit 5 +#define reg_iop_dmc_in_r_masked_intr_offset 100 + + +/* Constants */ +#define regk_iop_dmc_in_ack_pkt 0x00000100 +#define regk_iop_dmc_in_array 0x00000008 +#define regk_iop_dmc_in_burst 0x00000020 +#define regk_iop_dmc_in_copy_next 0x00000010 +#define regk_iop_dmc_in_copy_up 0x00000020 +#define regk_iop_dmc_in_dis_c 0x00000010 +#define regk_iop_dmc_in_dis_g 0x00000020 +#define regk_iop_dmc_in_lim1 0x00000000 +#define regk_iop_dmc_in_lim16 0x00000004 +#define regk_iop_dmc_in_lim2 0x00000001 +#define regk_iop_dmc_in_lim32 0x00000005 +#define regk_iop_dmc_in_lim4 0x00000002 +#define regk_iop_dmc_in_lim64 0x00000006 +#define regk_iop_dmc_in_lim8 0x00000003 +#define regk_iop_dmc_in_load_c 0x00000200 +#define regk_iop_dmc_in_load_c_n 0x00000280 +#define regk_iop_dmc_in_load_c_next 0x00000240 +#define regk_iop_dmc_in_load_d 0x00000140 +#define regk_iop_dmc_in_load_g 0x00000300 +#define regk_iop_dmc_in_load_g_down 0x000003c0 +#define regk_iop_dmc_in_load_g_next 0x00000340 +#define regk_iop_dmc_in_load_g_up 0x00000380 +#define regk_iop_dmc_in_next_en 0x00000010 +#define regk_iop_dmc_in_next_pkt 0x00000010 +#define regk_iop_dmc_in_no 0x00000000 +#define regk_iop_dmc_in_restore 0x00000020 +#define regk_iop_dmc_in_rw_cfg_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 +#define regk_iop_dmc_in_rw_data_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_group_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 +#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 +#define regk_iop_dmc_in_save_down 0x00000020 +#define regk_iop_dmc_in_save_up 0x00000020 +#define regk_iop_dmc_in_set_reg 0x00000050 +#define regk_iop_dmc_in_set_w_size1 0x00000190 +#define regk_iop_dmc_in_set_w_size2 0x000001a0 +#define regk_iop_dmc_in_set_w_size4 0x000001c0 +#define regk_iop_dmc_in_store_c 0x00000002 +#define regk_iop_dmc_in_store_descr 0x00000000 +#define regk_iop_dmc_in_store_g 0x00000004 +#define regk_iop_dmc_in_store_md 0x00000001 +#define regk_iop_dmc_in_update_down 0x00000020 +#define regk_iop_dmc_in_yes 0x00000001 +#endif /* __iop_dmc_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h new file mode 100644 index 000000000000..9fe1a8054371 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h @@ -0,0 +1,349 @@ +#ifndef __iop_dmc_out_defs_asm_h +#define __iop_dmc_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_out.r + * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r + * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 +#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 +#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 +#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 +#define reg_iop_dmc_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 +#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 +#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 +#define reg_iop_dmc_out_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 +#define reg_iop_dmc_out_r_stat___dif_en___width 1 +#define reg_iop_dmc_out_r_stat___dif_en___bit 0 +#define reg_iop_dmc_out_r_stat_offset 8 + +/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 +#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 +#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 +#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 +#define reg_iop_dmc_out_rw_stream_cmd_offset 12 + +/* Register rs_stream_data, scope iop_dmc_out, type rs */ +#define reg_iop_dmc_out_rs_stream_data_offset 16 + +/* Register r_stream_data, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stream_data_offset 20 + +/* Register r_stream_stat, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 +#define reg_iop_dmc_out_r_stream_stat___dth___width 7 +#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 +#define reg_iop_dmc_out_r_stream_stat___dv___width 1 +#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 +#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 +#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 +#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 +#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 +#define reg_iop_dmc_out_r_stream_stat___last___width 1 +#define reg_iop_dmc_out_r_stream_stat___last___bit 18 +#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 +#define reg_iop_dmc_out_r_stream_stat___size___width 3 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 +#define reg_iop_dmc_out_r_stream_stat_offset 24 + +/* Register r_data_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_data_descr___stat___width 8 +#define reg_iop_dmc_out_r_data_descr___md___lsb 16 +#define reg_iop_dmc_out_r_data_descr___md___width 16 +#define reg_iop_dmc_out_r_data_descr_offset 28 + +/* Register r_ctxt_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 +#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 +#define reg_iop_dmc_out_r_ctxt_descr_offset 32 + +/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 + +/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 + +/* Register r_group_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_group_descr___stat___width 8 +#define reg_iop_dmc_out_r_group_descr___md___lsb 16 +#define reg_iop_dmc_out_r_group_descr___md___width 16 +#define reg_iop_dmc_out_r_group_descr_offset 52 + +/* Register rw_data_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 +#define reg_iop_dmc_out_rw_data_descr___md___width 16 +#define reg_iop_dmc_out_rw_data_descr_offset 56 + +/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 +#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 + +/* Register rw_group_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 +#define reg_iop_dmc_out_rw_group_descr___md___width 16 +#define reg_iop_dmc_out_rw_group_descr_offset 80 + +/* Register rw_intr_mask, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 +#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 +#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 +#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 +#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 +#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 +#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 +#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 +#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 +#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 +#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 +#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 +#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 +#define reg_iop_dmc_out_rw_intr_mask_offset 84 + +/* Register rw_ack_intr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 +#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 +#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 +#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 +#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 +#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 +#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 +#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 +#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 +#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 +#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_rw_ack_intr_offset 88 + +/* Register r_intr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_intr___data_md___lsb 0 +#define reg_iop_dmc_out_r_intr___data_md___width 1 +#define reg_iop_dmc_out_r_intr___data_md___bit 0 +#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_r_intr___group_md___lsb 2 +#define reg_iop_dmc_out_r_intr___group_md___width 1 +#define reg_iop_dmc_out_r_intr___group_md___bit 2 +#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_r_intr___dth___lsb 4 +#define reg_iop_dmc_out_r_intr___dth___width 1 +#define reg_iop_dmc_out_r_intr___dth___bit 4 +#define reg_iop_dmc_out_r_intr___dv___lsb 5 +#define reg_iop_dmc_out_r_intr___dv___width 1 +#define reg_iop_dmc_out_r_intr___dv___bit 5 +#define reg_iop_dmc_out_r_intr___last_data___lsb 6 +#define reg_iop_dmc_out_r_intr___last_data___width 1 +#define reg_iop_dmc_out_r_intr___last_data___bit 6 +#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_r_intr___trf_lim___width 1 +#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_r_intr_offset 92 + +/* Register r_masked_intr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 +#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 +#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 +#define reg_iop_dmc_out_r_masked_intr___dth___width 1 +#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 +#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 +#define reg_iop_dmc_out_r_masked_intr___dv___width 1 +#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 +#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 +#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 +#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_r_masked_intr_offset 96 + + +/* Constants */ +#define regk_iop_dmc_out_ack_pkt 0x00000100 +#define regk_iop_dmc_out_array 0x00000008 +#define regk_iop_dmc_out_burst 0x00000020 +#define regk_iop_dmc_out_copy_next 0x00000010 +#define regk_iop_dmc_out_copy_up 0x00000020 +#define regk_iop_dmc_out_dis_c 0x00000010 +#define regk_iop_dmc_out_dis_g 0x00000020 +#define regk_iop_dmc_out_lim1 0x00000000 +#define regk_iop_dmc_out_lim16 0x00000004 +#define regk_iop_dmc_out_lim2 0x00000001 +#define regk_iop_dmc_out_lim32 0x00000005 +#define regk_iop_dmc_out_lim4 0x00000002 +#define regk_iop_dmc_out_lim64 0x00000006 +#define regk_iop_dmc_out_lim8 0x00000003 +#define regk_iop_dmc_out_load_c 0x00000200 +#define regk_iop_dmc_out_load_c_n 0x00000280 +#define regk_iop_dmc_out_load_c_next 0x00000240 +#define regk_iop_dmc_out_load_d 0x00000140 +#define regk_iop_dmc_out_load_g 0x00000300 +#define regk_iop_dmc_out_load_g_down 0x000003c0 +#define regk_iop_dmc_out_load_g_next 0x00000340 +#define regk_iop_dmc_out_load_g_up 0x00000380 +#define regk_iop_dmc_out_next_en 0x00000010 +#define regk_iop_dmc_out_next_pkt 0x00000010 +#define regk_iop_dmc_out_no 0x00000000 +#define regk_iop_dmc_out_restore 0x00000020 +#define regk_iop_dmc_out_rw_cfg_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 +#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 +#define regk_iop_dmc_out_save_down 0x00000020 +#define regk_iop_dmc_out_save_up 0x00000020 +#define regk_iop_dmc_out_set_reg 0x00000050 +#define regk_iop_dmc_out_set_w_size1 0x00000190 +#define regk_iop_dmc_out_set_w_size2 0x000001a0 +#define regk_iop_dmc_out_set_w_size4 0x000001c0 +#define regk_iop_dmc_out_store_c 0x00000002 +#define regk_iop_dmc_out_store_descr 0x00000000 +#define regk_iop_dmc_out_store_g 0x00000004 +#define regk_iop_dmc_out_store_md 0x00000001 +#define regk_iop_dmc_out_update_down 0x00000020 +#define regk_iop_dmc_out_yes 0x00000001 +#endif /* __iop_dmc_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h new file mode 100644 index 000000000000..974dee082f9f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h @@ -0,0 +1,234 @@ +#ifndef __iop_fifo_in_defs_asm_h +#define __iop_fifo_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:07 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r + * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 +#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 +#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 +#define reg_iop_fifo_in_rw_cfg___byte_order___width 2 +#define reg_iop_fifo_in_rw_cfg___trig___lsb 5 +#define reg_iop_fifo_in_rw_cfg___trig___width 2 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 +#define reg_iop_fifo_in_rw_cfg___mode___lsb 8 +#define reg_iop_fifo_in_rw_cfg___mode___width 2 +#define reg_iop_fifo_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 +#define reg_iop_fifo_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_in_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_in_r_stat___last___lsb 4 +#define reg_iop_fifo_in_r_stat___last___width 8 +#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_in_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_in_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_in_r_stat_offset 8 + +/* Register rs_rd1byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd1byte___data___width 8 +#define reg_iop_fifo_in_rs_rd1byte_offset 12 + +/* Register r_rd1byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd1byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd1byte___data___width 8 +#define reg_iop_fifo_in_r_rd1byte_offset 16 + +/* Register rs_rd2byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd2byte___data___width 16 +#define reg_iop_fifo_in_rs_rd2byte_offset 20 + +/* Register r_rd2byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd2byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd2byte___data___width 16 +#define reg_iop_fifo_in_r_rd2byte_offset 24 + +/* Register rs_rd3byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd3byte___data___width 24 +#define reg_iop_fifo_in_rs_rd3byte_offset 28 + +/* Register r_rd3byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd3byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd3byte___data___width 24 +#define reg_iop_fifo_in_r_rd3byte_offset 32 + +/* Register rs_rd4byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd4byte___data___width 32 +#define reg_iop_fifo_in_rs_rd4byte_offset 36 + +/* Register r_rd4byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd4byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd4byte___data___width 32 +#define reg_iop_fifo_in_r_rd4byte_offset 40 + +/* Register rw_set_last, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_set_last_offset 44 + +/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 +#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 +#define reg_iop_fifo_in_rw_strb_dif_in_offset 48 + +/* Register rw_intr_mask, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_in_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_in_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 +#define reg_iop_fifo_in_rw_intr_mask___avail___width 1 +#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 +#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_in_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_in_rw_intr_mask_offset 52 + +/* Register rw_ack_intr, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_in_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_in_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 +#define reg_iop_fifo_in_rw_ack_intr___avail___width 1 +#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 +#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_in_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_in_rw_ack_intr_offset 56 + +/* Register r_intr, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_intr___urun___lsb 0 +#define reg_iop_fifo_in_r_intr___urun___width 1 +#define reg_iop_fifo_in_r_intr___urun___bit 0 +#define reg_iop_fifo_in_r_intr___last_data___lsb 1 +#define reg_iop_fifo_in_r_intr___last_data___width 1 +#define reg_iop_fifo_in_r_intr___last_data___bit 1 +#define reg_iop_fifo_in_r_intr___dav___lsb 2 +#define reg_iop_fifo_in_r_intr___dav___width 1 +#define reg_iop_fifo_in_r_intr___dav___bit 2 +#define reg_iop_fifo_in_r_intr___avail___lsb 3 +#define reg_iop_fifo_in_r_intr___avail___width 1 +#define reg_iop_fifo_in_r_intr___avail___bit 3 +#define reg_iop_fifo_in_r_intr___orun___lsb 4 +#define reg_iop_fifo_in_r_intr___orun___width 1 +#define reg_iop_fifo_in_r_intr___orun___bit 4 +#define reg_iop_fifo_in_r_intr_offset 60 + +/* Register r_masked_intr, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_in_r_masked_intr___urun___width 1 +#define reg_iop_fifo_in_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_in_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_in_r_masked_intr___dav___width 1 +#define reg_iop_fifo_in_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 +#define reg_iop_fifo_in_r_masked_intr___avail___width 1 +#define reg_iop_fifo_in_r_masked_intr___avail___bit 3 +#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_in_r_masked_intr___orun___width 1 +#define reg_iop_fifo_in_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_in_r_masked_intr_offset 64 + + +/* Constants */ +#define regk_iop_fifo_in_dif_in 0x00000002 +#define regk_iop_fifo_in_hi 0x00000000 +#define regk_iop_fifo_in_neg 0x00000002 +#define regk_iop_fifo_in_no 0x00000000 +#define regk_iop_fifo_in_order16 0x00000001 +#define regk_iop_fifo_in_order24 0x00000002 +#define regk_iop_fifo_in_order32 0x00000003 +#define regk_iop_fifo_in_order8 0x00000000 +#define regk_iop_fifo_in_pos 0x00000001 +#define regk_iop_fifo_in_pos_neg 0x00000003 +#define regk_iop_fifo_in_rw_cfg_default 0x00000024 +#define regk_iop_fifo_in_rw_ctrl_default 0x00000000 +#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_in_rw_set_last_default 0x00000000 +#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 +#define regk_iop_fifo_in_size16 0x00000002 +#define regk_iop_fifo_in_size24 0x00000001 +#define regk_iop_fifo_in_size32 0x00000000 +#define regk_iop_fifo_in_size8 0x00000003 +#define regk_iop_fifo_in_yes 0x00000001 +#endif /* __iop_fifo_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h new file mode 100644 index 000000000000..e00fab0c9335 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h @@ -0,0 +1,155 @@ +#ifndef __iop_fifo_in_extra_defs_asm_h +#define __iop_fifo_in_extra_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:08 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_wr_data_offset 0 + +/* Register r_stat, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_in_extra_r_stat___last___lsb 4 +#define reg_iop_fifo_in_extra_r_stat___last___width 8 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_in_extra_r_stat_offset 4 + +/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 +#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 +#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 + +/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 + +/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 + +/* Register r_intr, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_r_intr___urun___width 1 +#define reg_iop_fifo_in_extra_r_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_r_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_r_intr___dav___width 1 +#define reg_iop_fifo_in_extra_r_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_r_intr___avail___width 1 +#define reg_iop_fifo_in_extra_r_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_r_intr___orun___width 1 +#define reg_iop_fifo_in_extra_r_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_r_intr_offset 20 + +/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_r_masked_intr_offset 24 + + +/* Constants */ +#define regk_iop_fifo_in_extra_fifo_in 0x00000002 +#define regk_iop_fifo_in_extra_no 0x00000000 +#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_in_extra_yes 0x00000001 +#endif /* __iop_fifo_in_extra_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h new file mode 100644 index 000000000000..9ec5f4a826df --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h @@ -0,0 +1,254 @@ +#ifndef __iop_fifo_out_defs_asm_h +#define __iop_fifo_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:09 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r + * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 +#define reg_iop_fifo_out_rw_cfg___free_lim___width 3 +#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 +#define reg_iop_fifo_out_rw_cfg___byte_order___width 2 +#define reg_iop_fifo_out_rw_cfg___trig___lsb 5 +#define reg_iop_fifo_out_rw_cfg___trig___width 2 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 +#define reg_iop_fifo_out_rw_cfg___mode___lsb 8 +#define reg_iop_fifo_out_rw_cfg___mode___width 2 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 +#define reg_iop_fifo_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 +#define reg_iop_fifo_out_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_out_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_out_r_stat___last___lsb 4 +#define reg_iop_fifo_out_r_stat___last___width 8 +#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_out_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_out_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 +#define reg_iop_fifo_out_r_stat___zero_data_last___width 1 +#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 +#define reg_iop_fifo_out_r_stat_offset 8 + +/* Register rw_wr1byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr1byte___data___width 8 +#define reg_iop_fifo_out_rw_wr1byte_offset 12 + +/* Register rw_wr2byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr2byte___data___width 16 +#define reg_iop_fifo_out_rw_wr2byte_offset 16 + +/* Register rw_wr3byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr3byte___data___width 24 +#define reg_iop_fifo_out_rw_wr3byte_offset 20 + +/* Register rw_wr4byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr4byte___data___width 32 +#define reg_iop_fifo_out_rw_wr4byte_offset 24 + +/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 +#define reg_iop_fifo_out_rw_wr1byte_last_offset 28 + +/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 +#define reg_iop_fifo_out_rw_wr2byte_last_offset 32 + +/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 +#define reg_iop_fifo_out_rw_wr3byte_last_offset 36 + +/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 +#define reg_iop_fifo_out_rw_wr4byte_last_offset 40 + +/* Register rw_set_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_set_last_offset 44 + +/* Register rs_rd_data, scope iop_fifo_out, type rs */ +#define reg_iop_fifo_out_rs_rd_data_offset 48 + +/* Register r_rd_data, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_rd_data_offset 52 + +/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_strb_dif_out_offset 56 + +/* Register rw_intr_mask, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_out_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_out_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 +#define reg_iop_fifo_out_rw_intr_mask___free___width 1 +#define reg_iop_fifo_out_rw_intr_mask___free___bit 3 +#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_out_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_out_rw_intr_mask_offset 60 + +/* Register rw_ack_intr, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_out_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_out_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 +#define reg_iop_fifo_out_rw_ack_intr___free___width 1 +#define reg_iop_fifo_out_rw_ack_intr___free___bit 3 +#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_out_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_out_rw_ack_intr_offset 64 + +/* Register r_intr, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_intr___urun___lsb 0 +#define reg_iop_fifo_out_r_intr___urun___width 1 +#define reg_iop_fifo_out_r_intr___urun___bit 0 +#define reg_iop_fifo_out_r_intr___last_data___lsb 1 +#define reg_iop_fifo_out_r_intr___last_data___width 1 +#define reg_iop_fifo_out_r_intr___last_data___bit 1 +#define reg_iop_fifo_out_r_intr___dav___lsb 2 +#define reg_iop_fifo_out_r_intr___dav___width 1 +#define reg_iop_fifo_out_r_intr___dav___bit 2 +#define reg_iop_fifo_out_r_intr___free___lsb 3 +#define reg_iop_fifo_out_r_intr___free___width 1 +#define reg_iop_fifo_out_r_intr___free___bit 3 +#define reg_iop_fifo_out_r_intr___orun___lsb 4 +#define reg_iop_fifo_out_r_intr___orun___width 1 +#define reg_iop_fifo_out_r_intr___orun___bit 4 +#define reg_iop_fifo_out_r_intr_offset 68 + +/* Register r_masked_intr, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_out_r_masked_intr___urun___width 1 +#define reg_iop_fifo_out_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_out_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_out_r_masked_intr___dav___width 1 +#define reg_iop_fifo_out_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_out_r_masked_intr___free___lsb 3 +#define reg_iop_fifo_out_r_masked_intr___free___width 1 +#define reg_iop_fifo_out_r_masked_intr___free___bit 3 +#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_out_r_masked_intr___orun___width 1 +#define reg_iop_fifo_out_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_out_r_masked_intr_offset 72 + + +/* Constants */ +#define regk_iop_fifo_out_hi 0x00000000 +#define regk_iop_fifo_out_neg 0x00000002 +#define regk_iop_fifo_out_no 0x00000000 +#define regk_iop_fifo_out_order16 0x00000001 +#define regk_iop_fifo_out_order24 0x00000002 +#define regk_iop_fifo_out_order32 0x00000003 +#define regk_iop_fifo_out_order8 0x00000000 +#define regk_iop_fifo_out_pos 0x00000001 +#define regk_iop_fifo_out_pos_neg 0x00000003 +#define regk_iop_fifo_out_rw_cfg_default 0x00000024 +#define regk_iop_fifo_out_rw_ctrl_default 0x00000000 +#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_out_rw_set_last_default 0x00000000 +#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 +#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 +#define regk_iop_fifo_out_size16 0x00000002 +#define regk_iop_fifo_out_size24 0x00000001 +#define regk_iop_fifo_out_size32 0x00000000 +#define regk_iop_fifo_out_size8 0x00000003 +#define regk_iop_fifo_out_yes 0x00000001 +#endif /* __iop_fifo_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h new file mode 100644 index 000000000000..0f84a50cf77c --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h @@ -0,0 +1,158 @@ +#ifndef __iop_fifo_out_extra_defs_asm_h +#define __iop_fifo_out_extra_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:10 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ +#define reg_iop_fifo_out_extra_rs_rd_data_offset 0 + +/* Register r_rd_data, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_rd_data_offset 4 + +/* Register r_stat, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_out_extra_r_stat___last___lsb 4 +#define reg_iop_fifo_out_extra_r_stat___last___width 8 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 +#define reg_iop_fifo_out_extra_r_stat_offset 8 + +/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 + +/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 + +/* Register r_intr, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_r_intr___urun___width 1 +#define reg_iop_fifo_out_extra_r_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_r_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_r_intr___dav___width 1 +#define reg_iop_fifo_out_extra_r_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_r_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_r_intr___free___width 1 +#define reg_iop_fifo_out_extra_r_intr___free___bit 3 +#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_r_intr___orun___width 1 +#define reg_iop_fifo_out_extra_r_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_r_intr_offset 24 + +/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_r_masked_intr_offset 28 + + +/* Constants */ +#define regk_iop_fifo_out_extra_no 0x00000000 +#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_out_extra_yes 0x00000001 +#endif /* __iop_fifo_out_extra_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h new file mode 100644 index 000000000000..80490c82cc29 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h @@ -0,0 +1,177 @@ +#ifndef __iop_mpu_defs_asm_h +#define __iop_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_mpu.r + * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r + * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_mpu_rw_r 4 +/* Register rw_r, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_r_offset 0 + +/* Register rw_ctrl, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_ctrl___en___lsb 0 +#define reg_iop_mpu_rw_ctrl___en___width 1 +#define reg_iop_mpu_rw_ctrl___en___bit 0 +#define reg_iop_mpu_rw_ctrl_offset 128 + +/* Register r_pc, scope iop_mpu, type r */ +#define reg_iop_mpu_r_pc___addr___lsb 0 +#define reg_iop_mpu_r_pc___addr___width 12 +#define reg_iop_mpu_r_pc_offset 132 + +/* Register r_stat, scope iop_mpu, type r */ +#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 +#define reg_iop_mpu_r_stat___instr_reg_busy___width 1 +#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 +#define reg_iop_mpu_r_stat___intr_busy___lsb 1 +#define reg_iop_mpu_r_stat___intr_busy___width 1 +#define reg_iop_mpu_r_stat___intr_busy___bit 1 +#define reg_iop_mpu_r_stat___intr_vect___lsb 2 +#define reg_iop_mpu_r_stat___intr_vect___width 16 +#define reg_iop_mpu_r_stat_offset 136 + +/* Register rw_instr, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_instr_offset 140 + +/* Register rw_immediate, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_immediate_offset 144 + +/* Register r_trace, scope iop_mpu, type r */ +#define reg_iop_mpu_r_trace___intr_vect___lsb 0 +#define reg_iop_mpu_r_trace___intr_vect___width 16 +#define reg_iop_mpu_r_trace___pc___lsb 16 +#define reg_iop_mpu_r_trace___pc___width 12 +#define reg_iop_mpu_r_trace___en___lsb 28 +#define reg_iop_mpu_r_trace___en___width 1 +#define reg_iop_mpu_r_trace___en___bit 28 +#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 +#define reg_iop_mpu_r_trace___instr_reg_busy___width 1 +#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 +#define reg_iop_mpu_r_trace___intr_busy___lsb 30 +#define reg_iop_mpu_r_trace___intr_busy___width 1 +#define reg_iop_mpu_r_trace___intr_busy___bit 30 +#define reg_iop_mpu_r_trace_offset 148 + +/* Register r_wr_stat, scope iop_mpu, type r */ +#define reg_iop_mpu_r_wr_stat___r0___lsb 0 +#define reg_iop_mpu_r_wr_stat___r0___width 1 +#define reg_iop_mpu_r_wr_stat___r0___bit 0 +#define reg_iop_mpu_r_wr_stat___r1___lsb 1 +#define reg_iop_mpu_r_wr_stat___r1___width 1 +#define reg_iop_mpu_r_wr_stat___r1___bit 1 +#define reg_iop_mpu_r_wr_stat___r2___lsb 2 +#define reg_iop_mpu_r_wr_stat___r2___width 1 +#define reg_iop_mpu_r_wr_stat___r2___bit 2 +#define reg_iop_mpu_r_wr_stat___r3___lsb 3 +#define reg_iop_mpu_r_wr_stat___r3___width 1 +#define reg_iop_mpu_r_wr_stat___r3___bit 3 +#define reg_iop_mpu_r_wr_stat___r4___lsb 4 +#define reg_iop_mpu_r_wr_stat___r4___width 1 +#define reg_iop_mpu_r_wr_stat___r4___bit 4 +#define reg_iop_mpu_r_wr_stat___r5___lsb 5 +#define reg_iop_mpu_r_wr_stat___r5___width 1 +#define reg_iop_mpu_r_wr_stat___r5___bit 5 +#define reg_iop_mpu_r_wr_stat___r6___lsb 6 +#define reg_iop_mpu_r_wr_stat___r6___width 1 +#define reg_iop_mpu_r_wr_stat___r6___bit 6 +#define reg_iop_mpu_r_wr_stat___r7___lsb 7 +#define reg_iop_mpu_r_wr_stat___r7___width 1 +#define reg_iop_mpu_r_wr_stat___r7___bit 7 +#define reg_iop_mpu_r_wr_stat___r8___lsb 8 +#define reg_iop_mpu_r_wr_stat___r8___width 1 +#define reg_iop_mpu_r_wr_stat___r8___bit 8 +#define reg_iop_mpu_r_wr_stat___r9___lsb 9 +#define reg_iop_mpu_r_wr_stat___r9___width 1 +#define reg_iop_mpu_r_wr_stat___r9___bit 9 +#define reg_iop_mpu_r_wr_stat___r10___lsb 10 +#define reg_iop_mpu_r_wr_stat___r10___width 1 +#define reg_iop_mpu_r_wr_stat___r10___bit 10 +#define reg_iop_mpu_r_wr_stat___r11___lsb 11 +#define reg_iop_mpu_r_wr_stat___r11___width 1 +#define reg_iop_mpu_r_wr_stat___r11___bit 11 +#define reg_iop_mpu_r_wr_stat___r12___lsb 12 +#define reg_iop_mpu_r_wr_stat___r12___width 1 +#define reg_iop_mpu_r_wr_stat___r12___bit 12 +#define reg_iop_mpu_r_wr_stat___r13___lsb 13 +#define reg_iop_mpu_r_wr_stat___r13___width 1 +#define reg_iop_mpu_r_wr_stat___r13___bit 13 +#define reg_iop_mpu_r_wr_stat___r14___lsb 14 +#define reg_iop_mpu_r_wr_stat___r14___width 1 +#define reg_iop_mpu_r_wr_stat___r14___bit 14 +#define reg_iop_mpu_r_wr_stat___r15___lsb 15 +#define reg_iop_mpu_r_wr_stat___r15___width 1 +#define reg_iop_mpu_r_wr_stat___r15___bit 15 +#define reg_iop_mpu_r_wr_stat_offset 152 + +#define STRIDE_iop_mpu_rw_thread 4 +/* Register rw_thread, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_thread___addr___lsb 0 +#define reg_iop_mpu_rw_thread___addr___width 12 +#define reg_iop_mpu_rw_thread_offset 156 + +#define STRIDE_iop_mpu_rw_intr 4 +/* Register rw_intr, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_intr___addr___lsb 0 +#define reg_iop_mpu_rw_intr___addr___width 12 +#define reg_iop_mpu_rw_intr_offset 196 + + +/* Constants */ +#define regk_iop_mpu_no 0x00000000 +#define regk_iop_mpu_r_pc_default 0x00000000 +#define regk_iop_mpu_rw_ctrl_default 0x00000000 +#define regk_iop_mpu_rw_intr_size 0x00000010 +#define regk_iop_mpu_rw_r_size 0x00000010 +#define regk_iop_mpu_rw_thread_default 0x00000000 +#define regk_iop_mpu_rw_thread_size 0x00000004 +#define regk_iop_mpu_yes 0x00000001 +#endif /* __iop_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 000000000000..a20b8857b4d0 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h @@ -0,0 +1,44 @@ +/* Autogenerated Changes here will be lost! + * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg + */ +#define iop_version 0 +#define iop_fifo_in0_extra 64 +#define iop_fifo_in1_extra 128 +#define iop_fifo_out0_extra 192 +#define iop_fifo_out1_extra 256 +#define iop_trigger_grp0 320 +#define iop_trigger_grp1 384 +#define iop_trigger_grp2 448 +#define iop_trigger_grp3 512 +#define iop_trigger_grp4 576 +#define iop_trigger_grp5 640 +#define iop_trigger_grp6 704 +#define iop_trigger_grp7 768 +#define iop_crc_par0 896 +#define iop_crc_par1 1024 +#define iop_dmc_in0 1152 +#define iop_dmc_in1 1280 +#define iop_dmc_out0 1408 +#define iop_dmc_out1 1536 +#define iop_fifo_in0 1664 +#define iop_fifo_in1 1792 +#define iop_fifo_out0 1920 +#define iop_fifo_out1 2048 +#define iop_scrc_in0 2176 +#define iop_scrc_in1 2304 +#define iop_scrc_out0 2432 +#define iop_scrc_out1 2560 +#define iop_timer_grp0 2688 +#define iop_timer_grp1 2816 +#define iop_timer_grp2 2944 +#define iop_timer_grp3 3072 +#define iop_sap_in 3328 +#define iop_sap_out 3584 +#define iop_spu0 3840 +#define iop_spu1 4096 +#define iop_sw_cfg 4352 +#define iop_sw_cpu 4608 +#define iop_sw_mpu 4864 +#define iop_sw_spu0 5120 +#define iop_sw_spu1 5376 +#define iop_mpu 5632 diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 000000000000..a4a10ff300b3 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h @@ -0,0 +1,182 @@ +#ifndef __iop_sap_in_defs_asm_h +#define __iop_sap_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_in.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r + * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_bus0_sync, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 +#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 +#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 +#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 +#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 +#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 +#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 +#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 +#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 +#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 +#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 +#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 +#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 +#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 +#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 +#define reg_iop_sap_in_rw_bus0_sync_offset 0 + +/* Register rw_bus1_sync, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 +#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 +#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 +#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 +#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 +#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 +#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 +#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 +#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 +#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 +#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 +#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 +#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 +#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 +#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 +#define reg_iop_sap_in_rw_bus1_sync_offset 4 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_gio___sync_sel___width 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_gio___sync_edge___width 2 +#define reg_iop_sap_in_rw_gio___delay___lsb 7 +#define reg_iop_sap_in_rw_gio___delay___width 1 +#define reg_iop_sap_in_rw_gio___delay___bit 7 +#define reg_iop_sap_in_rw_gio___logic___lsb 8 +#define reg_iop_sap_in_rw_gio___logic___width 2 +#define reg_iop_sap_in_rw_gio_offset 8 + + +/* Constants */ +#define regk_iop_sap_in_and 0x00000002 +#define regk_iop_sap_in_ext_clk200 0x00000003 +#define regk_iop_sap_in_gio1 0x00000000 +#define regk_iop_sap_in_gio13 0x00000005 +#define regk_iop_sap_in_gio18 0x00000003 +#define regk_iop_sap_in_gio19 0x00000004 +#define regk_iop_sap_in_gio21 0x00000006 +#define regk_iop_sap_in_gio23 0x00000005 +#define regk_iop_sap_in_gio29 0x00000007 +#define regk_iop_sap_in_gio5 0x00000004 +#define regk_iop_sap_in_gio6 0x00000001 +#define regk_iop_sap_in_gio7 0x00000002 +#define regk_iop_sap_in_inv 0x00000001 +#define regk_iop_sap_in_neg 0x00000002 +#define regk_iop_sap_in_no 0x00000000 +#define regk_iop_sap_in_no_del_ext_clk200 0x00000001 +#define regk_iop_sap_in_none 0x00000000 +#define regk_iop_sap_in_or 0x00000003 +#define regk_iop_sap_in_pos 0x00000001 +#define regk_iop_sap_in_pos_neg 0x00000003 +#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 +#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 +#define regk_iop_sap_in_rw_gio_default 0x00000002 +#define regk_iop_sap_in_rw_gio_size 0x00000020 +#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 +#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 +#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 +#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 +#define regk_iop_sap_in_tmr_clk200 0x00000000 +#define regk_iop_sap_in_two_clk200 0x00000002 +#define regk_iop_sap_in_yes 0x00000001 +#endif /* __iop_sap_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 000000000000..0ec727f92a25 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h @@ -0,0 +1,346 @@ +#ifndef __iop_sap_out_defs_asm_h +#define __iop_sap_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_out.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r + * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 +#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 +#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 +#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 +#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 +#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 +#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 +#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated_offset 0 + +/* Register rw_bus0, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 +#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 +#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 +#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 +#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 +#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 +#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 +#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 +#define reg_iop_sap_out_rw_bus0_offset 4 + +/* Register rw_bus1, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 +#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 +#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 +#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 +#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 +#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 +#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 +#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 +#define reg_iop_sap_out_rw_bus1_offset 8 + +/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 + +/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 + +/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 + +/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 +#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 +#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 +#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 +#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 +#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 +#define reg_iop_sap_out_rw_gio___out_logic___width 1 +#define reg_iop_sap_out_rw_gio___out_logic___bit 10 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 +#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 +#define reg_iop_sap_out_rw_gio___oe_logic___width 2 +#define reg_iop_sap_out_rw_gio_offset 28 + + +/* Constants */ +#define regk_iop_sap_out_and 0x00000002 +#define regk_iop_sap_out_clk0 0x00000000 +#define regk_iop_sap_out_clk1 0x00000001 +#define regk_iop_sap_out_clk12 0x00000002 +#define regk_iop_sap_out_clk2 0x00000002 +#define regk_iop_sap_out_clk200 0x00000001 +#define regk_iop_sap_out_clk3 0x00000003 +#define regk_iop_sap_out_ext 0x00000003 +#define regk_iop_sap_out_gated 0x00000004 +#define regk_iop_sap_out_gio1 0x00000000 +#define regk_iop_sap_out_gio13 0x00000002 +#define regk_iop_sap_out_gio13_clk 0x0000000c +#define regk_iop_sap_out_gio15 0x00000001 +#define regk_iop_sap_out_gio18 0x00000003 +#define regk_iop_sap_out_gio18_clk 0x0000000d +#define regk_iop_sap_out_gio1_clk 0x00000008 +#define regk_iop_sap_out_gio21_clk 0x0000000e +#define regk_iop_sap_out_gio23 0x00000002 +#define regk_iop_sap_out_gio29_clk 0x0000000f +#define regk_iop_sap_out_gio31 0x00000003 +#define regk_iop_sap_out_gio5 0x00000001 +#define regk_iop_sap_out_gio5_clk 0x00000009 +#define regk_iop_sap_out_gio6_clk 0x0000000a +#define regk_iop_sap_out_gio7 0x00000000 +#define regk_iop_sap_out_gio7_clk 0x0000000b +#define regk_iop_sap_out_gio_in13 0x00000001 +#define regk_iop_sap_out_gio_in21 0x00000002 +#define regk_iop_sap_out_gio_in29 0x00000003 +#define regk_iop_sap_out_gio_in5 0x00000000 +#define regk_iop_sap_out_inv 0x00000001 +#define regk_iop_sap_out_nand 0x00000003 +#define regk_iop_sap_out_no 0x00000000 +#define regk_iop_sap_out_none 0x00000000 +#define regk_iop_sap_out_rw_bus0_default 0x00000000 +#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 +#define regk_iop_sap_out_rw_gio_default 0x00000000 +#define regk_iop_sap_out_rw_gio_size 0x00000020 +#define regk_iop_sap_out_spu0_gio0 0x00000002 +#define regk_iop_sap_out_spu0_gio1 0x00000003 +#define regk_iop_sap_out_spu0_gio12 0x00000004 +#define regk_iop_sap_out_spu0_gio13 0x00000004 +#define regk_iop_sap_out_spu0_gio14 0x00000004 +#define regk_iop_sap_out_spu0_gio15 0x00000004 +#define regk_iop_sap_out_spu0_gio2 0x00000002 +#define regk_iop_sap_out_spu0_gio3 0x00000003 +#define regk_iop_sap_out_spu0_gio4 0x00000002 +#define regk_iop_sap_out_spu0_gio5 0x00000003 +#define regk_iop_sap_out_spu0_gio6 0x00000002 +#define regk_iop_sap_out_spu0_gio7 0x00000003 +#define regk_iop_sap_out_spu1_gio0 0x00000005 +#define regk_iop_sap_out_spu1_gio1 0x00000006 +#define regk_iop_sap_out_spu1_gio12 0x00000007 +#define regk_iop_sap_out_spu1_gio13 0x00000007 +#define regk_iop_sap_out_spu1_gio14 0x00000007 +#define regk_iop_sap_out_spu1_gio15 0x00000007 +#define regk_iop_sap_out_spu1_gio2 0x00000005 +#define regk_iop_sap_out_spu1_gio3 0x00000006 +#define regk_iop_sap_out_spu1_gio4 0x00000005 +#define regk_iop_sap_out_spu1_gio5 0x00000006 +#define regk_iop_sap_out_spu1_gio6 0x00000005 +#define regk_iop_sap_out_spu1_gio7 0x00000006 +#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 +#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 +#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 +#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 +#define regk_iop_sap_out_tmr 0x00000005 +#define regk_iop_sap_out_yes 0x00000001 +#endif /* __iop_sap_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h new file mode 100644 index 000000000000..2cf5721597fc --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h @@ -0,0 +1,111 @@ +#ifndef __iop_scrc_in_defs_asm_h +#define __iop_scrc_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_in.r + * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r + * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_cfg___trig___lsb 0 +#define reg_iop_scrc_in_rw_cfg___trig___width 2 +#define reg_iop_scrc_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_scrc_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_scrc_in, type r */ +#define reg_iop_scrc_in_r_stat___err___lsb 0 +#define reg_iop_scrc_in_r_stat___err___width 1 +#define reg_iop_scrc_in_r_stat___err___bit 0 +#define reg_iop_scrc_in_r_stat_offset 8 + +/* Register rw_init_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_init_crc_offset 12 + +/* Register rs_computed_crc, scope iop_scrc_in, type rs */ +#define reg_iop_scrc_in_rs_computed_crc_offset 16 + +/* Register r_computed_crc, scope iop_scrc_in, type r */ +#define reg_iop_scrc_in_r_computed_crc_offset 20 + +/* Register rw_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_crc_offset 24 + +/* Register rw_correct_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_correct_crc_offset 28 + +/* Register rw_wr1bit, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 +#define reg_iop_scrc_in_rw_wr1bit___data___width 2 +#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 +#define reg_iop_scrc_in_rw_wr1bit___last___width 2 +#define reg_iop_scrc_in_rw_wr1bit_offset 32 + + +/* Constants */ +#define regk_iop_scrc_in_dif_in 0x00000002 +#define regk_iop_scrc_in_hi 0x00000000 +#define regk_iop_scrc_in_neg 0x00000002 +#define regk_iop_scrc_in_no 0x00000000 +#define regk_iop_scrc_in_pos 0x00000001 +#define regk_iop_scrc_in_pos_neg 0x00000003 +#define regk_iop_scrc_in_r_computed_crc_default 0x00000000 +#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 +#define regk_iop_scrc_in_rw_cfg_default 0x00000000 +#define regk_iop_scrc_in_rw_ctrl_default 0x00000000 +#define regk_iop_scrc_in_rw_init_crc_default 0x00000000 +#define regk_iop_scrc_in_set0 0x00000000 +#define regk_iop_scrc_in_set1 0x00000001 +#define regk_iop_scrc_in_yes 0x00000001 +#endif /* __iop_scrc_in_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h new file mode 100644 index 000000000000..640a25725f20 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h @@ -0,0 +1,105 @@ +#ifndef __iop_scrc_out_defs_asm_h +#define __iop_scrc_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_out.r + * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r + * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_cfg___trig___lsb 0 +#define reg_iop_scrc_out_rw_cfg___trig___width 2 +#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 +#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 +#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 +#define reg_iop_scrc_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 +#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 +#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 +#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 +#define reg_iop_scrc_out_rw_ctrl___out_src___width 1 +#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 +#define reg_iop_scrc_out_rw_ctrl_offset 4 + +/* Register rw_init_crc, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_init_crc_offset 8 + +/* Register rw_crc, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_crc_offset 12 + +/* Register rw_data, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_data___val___lsb 0 +#define reg_iop_scrc_out_rw_data___val___width 1 +#define reg_iop_scrc_out_rw_data___val___bit 0 +#define reg_iop_scrc_out_rw_data_offset 16 + +/* Register r_computed_crc, scope iop_scrc_out, type r */ +#define reg_iop_scrc_out_r_computed_crc_offset 20 + + +/* Constants */ +#define regk_iop_scrc_out_crc 0x00000001 +#define regk_iop_scrc_out_data 0x00000000 +#define regk_iop_scrc_out_dif 0x00000001 +#define regk_iop_scrc_out_hi 0x00000000 +#define regk_iop_scrc_out_neg 0x00000002 +#define regk_iop_scrc_out_no 0x00000000 +#define regk_iop_scrc_out_pos 0x00000001 +#define regk_iop_scrc_out_pos_neg 0x00000003 +#define regk_iop_scrc_out_reg 0x00000000 +#define regk_iop_scrc_out_rw_cfg_default 0x00000000 +#define regk_iop_scrc_out_rw_crc_default 0x00000000 +#define regk_iop_scrc_out_rw_ctrl_default 0x00000000 +#define regk_iop_scrc_out_rw_data_default 0x00000000 +#define regk_iop_scrc_out_rw_init_crc_default 0x00000000 +#define regk_iop_scrc_out_yes 0x00000001 +#endif /* __iop_scrc_out_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h new file mode 100644 index 000000000000..bb402c1aa761 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h @@ -0,0 +1,573 @@ +#ifndef __iop_spu_defs_asm_h +#define __iop_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_spu.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r + * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_spu_rw_r 4 +/* Register rw_r, scope iop_spu, type rw */ +#define reg_iop_spu_rw_r_offset 0 + +/* Register rw_seq_pc, scope iop_spu, type rw */ +#define reg_iop_spu_rw_seq_pc___addr___lsb 0 +#define reg_iop_spu_rw_seq_pc___addr___width 12 +#define reg_iop_spu_rw_seq_pc_offset 64 + +/* Register rw_fsm_pc, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_pc___addr___lsb 0 +#define reg_iop_spu_rw_fsm_pc___addr___width 12 +#define reg_iop_spu_rw_fsm_pc_offset 68 + +/* Register rw_ctrl, scope iop_spu, type rw */ +#define reg_iop_spu_rw_ctrl___fsm___lsb 0 +#define reg_iop_spu_rw_ctrl___fsm___width 1 +#define reg_iop_spu_rw_ctrl___fsm___bit 0 +#define reg_iop_spu_rw_ctrl___en___lsb 1 +#define reg_iop_spu_rw_ctrl___en___width 1 +#define reg_iop_spu_rw_ctrl___en___bit 1 +#define reg_iop_spu_rw_ctrl_offset 72 + +/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 +#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 +#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 +#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 +#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 +#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 +#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 +#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0_offset 76 + +/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 +#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 +#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 +#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 +#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 +#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 +#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 +#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4_offset 80 + +/* Register rw_gio_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_offset 84 + +/* Register rw_bus0_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_bus0_out_offset 88 + +/* Register rw_bus1_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_bus1_out_offset 92 + +/* Register r_gio_in, scope iop_spu, type r */ +#define reg_iop_spu_r_gio_in_offset 96 + +/* Register r_bus0_in, scope iop_spu, type r */ +#define reg_iop_spu_r_bus0_in_offset 100 + +/* Register r_bus1_in, scope iop_spu, type r */ +#define reg_iop_spu_r_bus1_in_offset 104 + +/* Register rw_gio_out_set, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_set_offset 108 + +/* Register rw_gio_out_clr, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_clr_offset 112 + +/* Register rs_wr_stat, scope iop_spu, type rs */ +#define reg_iop_spu_rs_wr_stat___r0___lsb 0 +#define reg_iop_spu_rs_wr_stat___r0___width 1 +#define reg_iop_spu_rs_wr_stat___r0___bit 0 +#define reg_iop_spu_rs_wr_stat___r1___lsb 1 +#define reg_iop_spu_rs_wr_stat___r1___width 1 +#define reg_iop_spu_rs_wr_stat___r1___bit 1 +#define reg_iop_spu_rs_wr_stat___r2___lsb 2 +#define reg_iop_spu_rs_wr_stat___r2___width 1 +#define reg_iop_spu_rs_wr_stat___r2___bit 2 +#define reg_iop_spu_rs_wr_stat___r3___lsb 3 +#define reg_iop_spu_rs_wr_stat___r3___width 1 +#define reg_iop_spu_rs_wr_stat___r3___bit 3 +#define reg_iop_spu_rs_wr_stat___r4___lsb 4 +#define reg_iop_spu_rs_wr_stat___r4___width 1 +#define reg_iop_spu_rs_wr_stat___r4___bit 4 +#define reg_iop_spu_rs_wr_stat___r5___lsb 5 +#define reg_iop_spu_rs_wr_stat___r5___width 1 +#define reg_iop_spu_rs_wr_stat___r5___bit 5 +#define reg_iop_spu_rs_wr_stat___r6___lsb 6 +#define reg_iop_spu_rs_wr_stat___r6___width 1 +#define reg_iop_spu_rs_wr_stat___r6___bit 6 +#define reg_iop_spu_rs_wr_stat___r7___lsb 7 +#define reg_iop_spu_rs_wr_stat___r7___width 1 +#define reg_iop_spu_rs_wr_stat___r7___bit 7 +#define reg_iop_spu_rs_wr_stat___r8___lsb 8 +#define reg_iop_spu_rs_wr_stat___r8___width 1 +#define reg_iop_spu_rs_wr_stat___r8___bit 8 +#define reg_iop_spu_rs_wr_stat___r9___lsb 9 +#define reg_iop_spu_rs_wr_stat___r9___width 1 +#define reg_iop_spu_rs_wr_stat___r9___bit 9 +#define reg_iop_spu_rs_wr_stat___r10___lsb 10 +#define reg_iop_spu_rs_wr_stat___r10___width 1 +#define reg_iop_spu_rs_wr_stat___r10___bit 10 +#define reg_iop_spu_rs_wr_stat___r11___lsb 11 +#define reg_iop_spu_rs_wr_stat___r11___width 1 +#define reg_iop_spu_rs_wr_stat___r11___bit 11 +#define reg_iop_spu_rs_wr_stat___r12___lsb 12 +#define reg_iop_spu_rs_wr_stat___r12___width 1 +#define reg_iop_spu_rs_wr_stat___r12___bit 12 +#define reg_iop_spu_rs_wr_stat___r13___lsb 13 +#define reg_iop_spu_rs_wr_stat___r13___width 1 +#define reg_iop_spu_rs_wr_stat___r13___bit 13 +#define reg_iop_spu_rs_wr_stat___r14___lsb 14 +#define reg_iop_spu_rs_wr_stat___r14___width 1 +#define reg_iop_spu_rs_wr_stat___r14___bit 14 +#define reg_iop_spu_rs_wr_stat___r15___lsb 15 +#define reg_iop_spu_rs_wr_stat___r15___width 1 +#define reg_iop_spu_rs_wr_stat___r15___bit 15 +#define reg_iop_spu_rs_wr_stat_offset 116 + +/* Register r_wr_stat, scope iop_spu, type r */ +#define reg_iop_spu_r_wr_stat___r0___lsb 0 +#define reg_iop_spu_r_wr_stat___r0___width 1 +#define reg_iop_spu_r_wr_stat___r0___bit 0 +#define reg_iop_spu_r_wr_stat___r1___lsb 1 +#define reg_iop_spu_r_wr_stat___r1___width 1 +#define reg_iop_spu_r_wr_stat___r1___bit 1 +#define reg_iop_spu_r_wr_stat___r2___lsb 2 +#define reg_iop_spu_r_wr_stat___r2___width 1 +#define reg_iop_spu_r_wr_stat___r2___bit 2 +#define reg_iop_spu_r_wr_stat___r3___lsb 3 +#define reg_iop_spu_r_wr_stat___r3___width 1 +#define reg_iop_spu_r_wr_stat___r3___bit 3 +#define reg_iop_spu_r_wr_stat___r4___lsb 4 +#define reg_iop_spu_r_wr_stat___r4___width 1 +#define reg_iop_spu_r_wr_stat___r4___bit 4 +#define reg_iop_spu_r_wr_stat___r5___lsb 5 +#define reg_iop_spu_r_wr_stat___r5___width 1 +#define reg_iop_spu_r_wr_stat___r5___bit 5 +#define reg_iop_spu_r_wr_stat___r6___lsb 6 +#define reg_iop_spu_r_wr_stat___r6___width 1 +#define reg_iop_spu_r_wr_stat___r6___bit 6 +#define reg_iop_spu_r_wr_stat___r7___lsb 7 +#define reg_iop_spu_r_wr_stat___r7___width 1 +#define reg_iop_spu_r_wr_stat___r7___bit 7 +#define reg_iop_spu_r_wr_stat___r8___lsb 8 +#define reg_iop_spu_r_wr_stat___r8___width 1 +#define reg_iop_spu_r_wr_stat___r8___bit 8 +#define reg_iop_spu_r_wr_stat___r9___lsb 9 +#define reg_iop_spu_r_wr_stat___r9___width 1 +#define reg_iop_spu_r_wr_stat___r9___bit 9 +#define reg_iop_spu_r_wr_stat___r10___lsb 10 +#define reg_iop_spu_r_wr_stat___r10___width 1 +#define reg_iop_spu_r_wr_stat___r10___bit 10 +#define reg_iop_spu_r_wr_stat___r11___lsb 11 +#define reg_iop_spu_r_wr_stat___r11___width 1 +#define reg_iop_spu_r_wr_stat___r11___bit 11 +#define reg_iop_spu_r_wr_stat___r12___lsb 12 +#define reg_iop_spu_r_wr_stat___r12___width 1 +#define reg_iop_spu_r_wr_stat___r12___bit 12 +#define reg_iop_spu_r_wr_stat___r13___lsb 13 +#define reg_iop_spu_r_wr_stat___r13___width 1 +#define reg_iop_spu_r_wr_stat___r13___bit 13 +#define reg_iop_spu_r_wr_stat___r14___lsb 14 +#define reg_iop_spu_r_wr_stat___r14___width 1 +#define reg_iop_spu_r_wr_stat___r14___bit 14 +#define reg_iop_spu_r_wr_stat___r15___lsb 15 +#define reg_iop_spu_r_wr_stat___r15___width 1 +#define reg_iop_spu_r_wr_stat___r15___bit 15 +#define reg_iop_spu_r_wr_stat_offset 120 + +/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ +#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 + +/* Register r_stat_in, scope iop_spu, type r */ +#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 +#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 +#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 +#define reg_iop_spu_r_stat_in___fifo_out_last___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 +#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 +#define reg_iop_spu_r_stat_in___fifo_out_all___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 +#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 +#define reg_iop_spu_r_stat_in___dmc_out_all___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 +#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 +#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 +#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 +#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 +#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 +#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 +#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 +#define reg_iop_spu_r_stat_in___dmc_out_last___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 +#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 +#define reg_iop_spu_r_stat_in___pcrc_correct___width 1 +#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 +#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 +#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 +#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 +#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 +#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 +#define reg_iop_spu_r_stat_in___dmc_in_full___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 +#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 +#define reg_iop_spu_r_stat_in___spu_gio_out___width 4 +#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 +#define reg_iop_spu_r_stat_in___sync_clk12___width 1 +#define reg_iop_spu_r_stat_in___sync_clk12___bit 27 +#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 +#define reg_iop_spu_r_stat_in___scrc_out_data___width 1 +#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 +#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 +#define reg_iop_spu_r_stat_in___scrc_in_err___width 1 +#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 +#define reg_iop_spu_r_stat_in___mc_busy___lsb 30 +#define reg_iop_spu_r_stat_in___mc_busy___width 1 +#define reg_iop_spu_r_stat_in___mc_busy___bit 30 +#define reg_iop_spu_r_stat_in___mc_owned___lsb 31 +#define reg_iop_spu_r_stat_in___mc_owned___width 1 +#define reg_iop_spu_r_stat_in___mc_owned___bit 31 +#define reg_iop_spu_r_stat_in_offset 128 + +/* Register r_trigger_in, scope iop_spu, type r */ +#define reg_iop_spu_r_trigger_in_offset 132 + +/* Register r_special_stat, scope iop_spu, type r */ +#define reg_iop_spu_r_special_stat___c_flag___lsb 0 +#define reg_iop_spu_r_special_stat___c_flag___width 1 +#define reg_iop_spu_r_special_stat___c_flag___bit 0 +#define reg_iop_spu_r_special_stat___v_flag___lsb 1 +#define reg_iop_spu_r_special_stat___v_flag___width 1 +#define reg_iop_spu_r_special_stat___v_flag___bit 1 +#define reg_iop_spu_r_special_stat___z_flag___lsb 2 +#define reg_iop_spu_r_special_stat___z_flag___width 1 +#define reg_iop_spu_r_special_stat___z_flag___bit 2 +#define reg_iop_spu_r_special_stat___n_flag___lsb 3 +#define reg_iop_spu_r_special_stat___n_flag___width 1 +#define reg_iop_spu_r_special_stat___n_flag___bit 3 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 +#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 +#define reg_iop_spu_r_special_stat___fsm_in0___width 1 +#define reg_iop_spu_r_special_stat___fsm_in0___bit 8 +#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 +#define reg_iop_spu_r_special_stat___fsm_in1___width 1 +#define reg_iop_spu_r_special_stat___fsm_in1___bit 9 +#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 +#define reg_iop_spu_r_special_stat___fsm_in2___width 1 +#define reg_iop_spu_r_special_stat___fsm_in2___bit 10 +#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 +#define reg_iop_spu_r_special_stat___fsm_in3___width 1 +#define reg_iop_spu_r_special_stat___fsm_in3___bit 11 +#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 +#define reg_iop_spu_r_special_stat___fsm_in4___width 1 +#define reg_iop_spu_r_special_stat___fsm_in4___bit 12 +#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 +#define reg_iop_spu_r_special_stat___fsm_in5___width 1 +#define reg_iop_spu_r_special_stat___fsm_in5___bit 13 +#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 +#define reg_iop_spu_r_special_stat___fsm_in6___width 1 +#define reg_iop_spu_r_special_stat___fsm_in6___bit 14 +#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 +#define reg_iop_spu_r_special_stat___fsm_in7___width 1 +#define reg_iop_spu_r_special_stat___fsm_in7___bit 15 +#define reg_iop_spu_r_special_stat___event0___lsb 16 +#define reg_iop_spu_r_special_stat___event0___width 1 +#define reg_iop_spu_r_special_stat___event0___bit 16 +#define reg_iop_spu_r_special_stat___event1___lsb 17 +#define reg_iop_spu_r_special_stat___event1___width 1 +#define reg_iop_spu_r_special_stat___event1___bit 17 +#define reg_iop_spu_r_special_stat___event2___lsb 18 +#define reg_iop_spu_r_special_stat___event2___width 1 +#define reg_iop_spu_r_special_stat___event2___bit 18 +#define reg_iop_spu_r_special_stat___event3___lsb 19 +#define reg_iop_spu_r_special_stat___event3___width 1 +#define reg_iop_spu_r_special_stat___event3___bit 19 +#define reg_iop_spu_r_special_stat_offset 136 + +/* Register rw_reg_access, scope iop_spu, type rw */ +#define reg_iop_spu_rw_reg_access___addr___lsb 0 +#define reg_iop_spu_rw_reg_access___addr___width 13 +#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 +#define reg_iop_spu_rw_reg_access___imm_hi___width 16 +#define reg_iop_spu_rw_reg_access_offset 140 + +#define STRIDE_iop_spu_rw_event_cfg 4 +/* Register rw_event_cfg, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_cfg___addr___lsb 0 +#define reg_iop_spu_rw_event_cfg___addr___width 12 +#define reg_iop_spu_rw_event_cfg___src___lsb 12 +#define reg_iop_spu_rw_event_cfg___src___width 2 +#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 +#define reg_iop_spu_rw_event_cfg___eq_en___width 1 +#define reg_iop_spu_rw_event_cfg___eq_en___bit 14 +#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 +#define reg_iop_spu_rw_event_cfg___eq_inv___width 1 +#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 +#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 +#define reg_iop_spu_rw_event_cfg___gt_en___width 1 +#define reg_iop_spu_rw_event_cfg___gt_en___bit 16 +#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 +#define reg_iop_spu_rw_event_cfg___gt_inv___width 1 +#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 +#define reg_iop_spu_rw_event_cfg_offset 144 + +#define STRIDE_iop_spu_rw_event_mask 4 +/* Register rw_event_mask, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_mask_offset 160 + +#define STRIDE_iop_spu_rw_event_val 4 +/* Register rw_event_val, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_val_offset 176 + +/* Register rw_event_ret, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_ret___addr___lsb 0 +#define reg_iop_spu_rw_event_ret___addr___width 12 +#define reg_iop_spu_rw_event_ret_offset 192 + +/* Register r_trace, scope iop_spu, type r */ +#define reg_iop_spu_r_trace___fsm___lsb 0 +#define reg_iop_spu_r_trace___fsm___width 1 +#define reg_iop_spu_r_trace___fsm___bit 0 +#define reg_iop_spu_r_trace___en___lsb 1 +#define reg_iop_spu_r_trace___en___width 1 +#define reg_iop_spu_r_trace___en___bit 1 +#define reg_iop_spu_r_trace___c_flag___lsb 2 +#define reg_iop_spu_r_trace___c_flag___width 1 +#define reg_iop_spu_r_trace___c_flag___bit 2 +#define reg_iop_spu_r_trace___v_flag___lsb 3 +#define reg_iop_spu_r_trace___v_flag___width 1 +#define reg_iop_spu_r_trace___v_flag___bit 3 +#define reg_iop_spu_r_trace___z_flag___lsb 4 +#define reg_iop_spu_r_trace___z_flag___width 1 +#define reg_iop_spu_r_trace___z_flag___bit 4 +#define reg_iop_spu_r_trace___n_flag___lsb 5 +#define reg_iop_spu_r_trace___n_flag___width 1 +#define reg_iop_spu_r_trace___n_flag___bit 5 +#define reg_iop_spu_r_trace___seq_addr___lsb 6 +#define reg_iop_spu_r_trace___seq_addr___width 12 +#define reg_iop_spu_r_trace___fsm_addr___lsb 20 +#define reg_iop_spu_r_trace___fsm_addr___width 12 +#define reg_iop_spu_r_trace_offset 196 + +/* Register r_fsm_trace, scope iop_spu, type r */ +#define reg_iop_spu_r_fsm_trace___fsm___lsb 0 +#define reg_iop_spu_r_fsm_trace___fsm___width 1 +#define reg_iop_spu_r_fsm_trace___fsm___bit 0 +#define reg_iop_spu_r_fsm_trace___en___lsb 1 +#define reg_iop_spu_r_fsm_trace___en___width 1 +#define reg_iop_spu_r_fsm_trace___en___bit 1 +#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 +#define reg_iop_spu_r_fsm_trace___tmr_done___width 1 +#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 +#define reg_iop_spu_r_fsm_trace___inp0___lsb 3 +#define reg_iop_spu_r_fsm_trace___inp0___width 1 +#define reg_iop_spu_r_fsm_trace___inp0___bit 3 +#define reg_iop_spu_r_fsm_trace___inp1___lsb 4 +#define reg_iop_spu_r_fsm_trace___inp1___width 1 +#define reg_iop_spu_r_fsm_trace___inp1___bit 4 +#define reg_iop_spu_r_fsm_trace___inp2___lsb 5 +#define reg_iop_spu_r_fsm_trace___inp2___width 1 +#define reg_iop_spu_r_fsm_trace___inp2___bit 5 +#define reg_iop_spu_r_fsm_trace___inp3___lsb 6 +#define reg_iop_spu_r_fsm_trace___inp3___width 1 +#define reg_iop_spu_r_fsm_trace___inp3___bit 6 +#define reg_iop_spu_r_fsm_trace___event0___lsb 7 +#define reg_iop_spu_r_fsm_trace___event0___width 1 +#define reg_iop_spu_r_fsm_trace___event0___bit 7 +#define reg_iop_spu_r_fsm_trace___event1___lsb 8 +#define reg_iop_spu_r_fsm_trace___event1___width 1 +#define reg_iop_spu_r_fsm_trace___event1___bit 8 +#define reg_iop_spu_r_fsm_trace___event2___lsb 9 +#define reg_iop_spu_r_fsm_trace___event2___width 1 +#define reg_iop_spu_r_fsm_trace___event2___bit 9 +#define reg_iop_spu_r_fsm_trace___event3___lsb 10 +#define reg_iop_spu_r_fsm_trace___event3___width 1 +#define reg_iop_spu_r_fsm_trace___event3___bit 10 +#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 +#define reg_iop_spu_r_fsm_trace___gio_out___width 8 +#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 +#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 +#define reg_iop_spu_r_fsm_trace_offset 200 + +#define STRIDE_iop_spu_rw_brp 4 +/* Register rw_brp, scope iop_spu, type rw */ +#define reg_iop_spu_rw_brp___addr___lsb 0 +#define reg_iop_spu_rw_brp___addr___width 12 +#define reg_iop_spu_rw_brp___fsm___lsb 12 +#define reg_iop_spu_rw_brp___fsm___width 1 +#define reg_iop_spu_rw_brp___fsm___bit 12 +#define reg_iop_spu_rw_brp___en___lsb 13 +#define reg_iop_spu_rw_brp___en___width 1 +#define reg_iop_spu_rw_brp___en___bit 13 +#define reg_iop_spu_rw_brp_offset 204 + + +/* Constants */ +#define regk_iop_spu_attn_hi 0x00000005 +#define regk_iop_spu_attn_lo 0x00000005 +#define regk_iop_spu_attn_r0 0x00000000 +#define regk_iop_spu_attn_r1 0x00000001 +#define regk_iop_spu_attn_r10 0x00000002 +#define regk_iop_spu_attn_r11 0x00000003 +#define regk_iop_spu_attn_r12 0x00000004 +#define regk_iop_spu_attn_r13 0x00000005 +#define regk_iop_spu_attn_r14 0x00000006 +#define regk_iop_spu_attn_r15 0x00000007 +#define regk_iop_spu_attn_r2 0x00000002 +#define regk_iop_spu_attn_r3 0x00000003 +#define regk_iop_spu_attn_r4 0x00000004 +#define regk_iop_spu_attn_r5 0x00000005 +#define regk_iop_spu_attn_r6 0x00000006 +#define regk_iop_spu_attn_r7 0x00000007 +#define regk_iop_spu_attn_r8 0x00000000 +#define regk_iop_spu_attn_r9 0x00000001 +#define regk_iop_spu_c 0x00000000 +#define regk_iop_spu_flag 0x00000002 +#define regk_iop_spu_gio_in 0x00000000 +#define regk_iop_spu_gio_out 0x00000005 +#define regk_iop_spu_gio_out0 0x00000008 +#define regk_iop_spu_gio_out1 0x00000009 +#define regk_iop_spu_gio_out2 0x0000000a +#define regk_iop_spu_gio_out3 0x0000000b +#define regk_iop_spu_gio_out4 0x0000000c +#define regk_iop_spu_gio_out5 0x0000000d +#define regk_iop_spu_gio_out6 0x0000000e +#define regk_iop_spu_gio_out7 0x0000000f +#define regk_iop_spu_n 0x00000003 +#define regk_iop_spu_no 0x00000000 +#define regk_iop_spu_r0 0x00000008 +#define regk_iop_spu_r1 0x00000009 +#define regk_iop_spu_r10 0x0000000a +#define regk_iop_spu_r11 0x0000000b +#define regk_iop_spu_r12 0x0000000c +#define regk_iop_spu_r13 0x0000000d +#define regk_iop_spu_r14 0x0000000e +#define regk_iop_spu_r15 0x0000000f +#define regk_iop_spu_r2 0x0000000a +#define regk_iop_spu_r3 0x0000000b +#define regk_iop_spu_r4 0x0000000c +#define regk_iop_spu_r5 0x0000000d +#define regk_iop_spu_r6 0x0000000e +#define regk_iop_spu_r7 0x0000000f +#define regk_iop_spu_r8 0x00000008 +#define regk_iop_spu_r9 0x00000009 +#define regk_iop_spu_reg_hi 0x00000002 +#define regk_iop_spu_reg_lo 0x00000002 +#define regk_iop_spu_rw_brp_default 0x00000000 +#define regk_iop_spu_rw_brp_size 0x00000004 +#define regk_iop_spu_rw_ctrl_default 0x00000000 +#define regk_iop_spu_rw_event_cfg_size 0x00000004 +#define regk_iop_spu_rw_event_mask_size 0x00000004 +#define regk_iop_spu_rw_event_val_size 0x00000004 +#define regk_iop_spu_rw_gio_out_default 0x00000000 +#define regk_iop_spu_rw_r_size 0x00000010 +#define regk_iop_spu_rw_reg_access_default 0x00000000 +#define regk_iop_spu_stat_in 0x00000002 +#define regk_iop_spu_statin_hi 0x00000004 +#define regk_iop_spu_statin_lo 0x00000004 +#define regk_iop_spu_trig 0x00000003 +#define regk_iop_spu_trigger 0x00000006 +#define regk_iop_spu_v 0x00000001 +#define regk_iop_spu_wsts_gioout_spec 0x00000001 +#define regk_iop_spu_xor 0x00000003 +#define regk_iop_spu_xor_bus0_r2_0 0x00000000 +#define regk_iop_spu_xor_bus0m_r2_0 0x00000002 +#define regk_iop_spu_xor_bus1_r3_0 0x00000001 +#define regk_iop_spu_xor_bus1m_r3_0 0x00000003 +#define regk_iop_spu_yes 0x00000001 +#define regk_iop_spu_z 0x00000002 +#endif /* __iop_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 000000000000..3be60f9b024c --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h @@ -0,0 +1,1052 @@ +#ifndef __iop_sw_cfg_defs_asm_h +#define __iop_sw_cfg_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 + +/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 + +/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 + +/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 + +/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 + +/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 + +/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 + +/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 + +/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 + +/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 + +/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 + +/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 + +/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 + +/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 + +/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 + +/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 + +/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 + +/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 + +/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 + +/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 + +/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 + +/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 + +/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 + +/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 + +/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 + +/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_mask_offset 152 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 +#define reg_iop_sw_cfg_rw_pinmapping_offset 160 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 + +/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 +#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 + +/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 +#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 + +/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 + +/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 + +/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 +#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 + +/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 +#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 + + +/* Constants */ +#define regk_iop_sw_cfg_a 0x00000001 +#define regk_iop_sw_cfg_b 0x00000002 +#define regk_iop_sw_cfg_bus0 0x00000000 +#define regk_iop_sw_cfg_bus0_rot16 0x00000004 +#define regk_iop_sw_cfg_bus0_rot24 0x00000006 +#define regk_iop_sw_cfg_bus0_rot8 0x00000002 +#define regk_iop_sw_cfg_bus1 0x00000001 +#define regk_iop_sw_cfg_bus1_rot16 0x00000005 +#define regk_iop_sw_cfg_bus1_rot24 0x00000007 +#define regk_iop_sw_cfg_bus1_rot8 0x00000003 +#define regk_iop_sw_cfg_clk12 0x00000000 +#define regk_iop_sw_cfg_cpu 0x00000000 +#define regk_iop_sw_cfg_dmc0 0x00000000 +#define regk_iop_sw_cfg_dmc1 0x00000001 +#define regk_iop_sw_cfg_gated_clk0 0x00000010 +#define regk_iop_sw_cfg_gated_clk1 0x00000011 +#define regk_iop_sw_cfg_gated_clk2 0x00000012 +#define regk_iop_sw_cfg_gated_clk3 0x00000013 +#define regk_iop_sw_cfg_gio0 0x00000004 +#define regk_iop_sw_cfg_gio1 0x00000001 +#define regk_iop_sw_cfg_gio2 0x00000005 +#define regk_iop_sw_cfg_gio3 0x00000002 +#define regk_iop_sw_cfg_gio4 0x00000006 +#define regk_iop_sw_cfg_gio5 0x00000003 +#define regk_iop_sw_cfg_gio6 0x00000007 +#define regk_iop_sw_cfg_gio7 0x00000004 +#define regk_iop_sw_cfg_gio_in0 0x00000000 +#define regk_iop_sw_cfg_gio_in1 0x00000001 +#define regk_iop_sw_cfg_gio_in10 0x00000002 +#define regk_iop_sw_cfg_gio_in11 0x00000003 +#define regk_iop_sw_cfg_gio_in14 0x00000004 +#define regk_iop_sw_cfg_gio_in15 0x00000005 +#define regk_iop_sw_cfg_gio_in18 0x00000002 +#define regk_iop_sw_cfg_gio_in19 0x00000003 +#define regk_iop_sw_cfg_gio_in20 0x00000004 +#define regk_iop_sw_cfg_gio_in21 0x00000005 +#define regk_iop_sw_cfg_gio_in26 0x00000006 +#define regk_iop_sw_cfg_gio_in27 0x00000007 +#define regk_iop_sw_cfg_gio_in28 0x00000006 +#define regk_iop_sw_cfg_gio_in29 0x00000007 +#define regk_iop_sw_cfg_gio_in4 0x00000000 +#define regk_iop_sw_cfg_gio_in5 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 +#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 +#define regk_iop_sw_cfg_mpu 0x00000001 +#define regk_iop_sw_cfg_none 0x00000000 +#define regk_iop_sw_cfg_par0 0x00000000 +#define regk_iop_sw_cfg_par1 0x00000001 +#define regk_iop_sw_cfg_pdp_out0 0x00000002 +#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 +#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 +#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 +#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 +#define regk_iop_sw_cfg_pdp_out1 0x00000003 +#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 +#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 +#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 +#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 +#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 +#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 +#define regk_iop_sw_cfg_sdp_out0 0x00000008 +#define regk_iop_sw_cfg_sdp_out1 0x00000009 +#define regk_iop_sw_cfg_size16 0x00000002 +#define regk_iop_sw_cfg_size24 0x00000003 +#define regk_iop_sw_cfg_size32 0x00000004 +#define regk_iop_sw_cfg_size8 0x00000001 +#define regk_iop_sw_cfg_spu0 0x00000002 +#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 +#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 +#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 +#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 +#define regk_iop_sw_cfg_spu0_g0 0x0000000e +#define regk_iop_sw_cfg_spu0_g1 0x0000000e +#define regk_iop_sw_cfg_spu0_g2 0x0000000e +#define regk_iop_sw_cfg_spu0_g3 0x0000000e +#define regk_iop_sw_cfg_spu0_g4 0x0000000e +#define regk_iop_sw_cfg_spu0_g5 0x0000000e +#define regk_iop_sw_cfg_spu0_g6 0x0000000e +#define regk_iop_sw_cfg_spu0_g7 0x0000000e +#define regk_iop_sw_cfg_spu0_gio0 0x00000000 +#define regk_iop_sw_cfg_spu0_gio1 0x00000001 +#define regk_iop_sw_cfg_spu0_gio2 0x00000000 +#define regk_iop_sw_cfg_spu0_gio5 0x00000005 +#define regk_iop_sw_cfg_spu0_gio6 0x00000006 +#define regk_iop_sw_cfg_spu0_gio7 0x00000007 +#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 +#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 +#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 +#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 +#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 +#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 +#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 +#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 +#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e +#define regk_iop_sw_cfg_spu1 0x00000003 +#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 +#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 +#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 +#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 +#define regk_iop_sw_cfg_spu1_g0 0x0000000f +#define regk_iop_sw_cfg_spu1_g1 0x0000000f +#define regk_iop_sw_cfg_spu1_g2 0x0000000f +#define regk_iop_sw_cfg_spu1_g3 0x0000000f +#define regk_iop_sw_cfg_spu1_g4 0x0000000f +#define regk_iop_sw_cfg_spu1_g5 0x0000000f +#define regk_iop_sw_cfg_spu1_g6 0x0000000f +#define regk_iop_sw_cfg_spu1_g7 0x0000000f +#define regk_iop_sw_cfg_spu1_gio0 0x00000002 +#define regk_iop_sw_cfg_spu1_gio1 0x00000003 +#define regk_iop_sw_cfg_spu1_gio2 0x00000002 +#define regk_iop_sw_cfg_spu1_gio5 0x00000005 +#define regk_iop_sw_cfg_spu1_gio6 0x00000006 +#define regk_iop_sw_cfg_spu1_gio7 0x00000007 +#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 +#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 +#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 +#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 +#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 +#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 +#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 +#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 +#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f +#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 +#define regk_iop_sw_cfg_timer_grp0 0x00000000 +#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 +#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 +#define regk_iop_sw_cfg_timer_grp1 0x00000000 +#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 +#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 +#define regk_iop_sw_cfg_timer_grp2 0x00000000 +#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 +#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 +#define regk_iop_sw_cfg_timer_grp3 0x00000000 +#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 +#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 +#define regk_iop_sw_cfg_trig0_0 0x00000000 +#define regk_iop_sw_cfg_trig0_1 0x00000000 +#define regk_iop_sw_cfg_trig0_2 0x00000000 +#define regk_iop_sw_cfg_trig0_3 0x00000000 +#define regk_iop_sw_cfg_trig1_0 0x00000000 +#define regk_iop_sw_cfg_trig1_1 0x00000000 +#define regk_iop_sw_cfg_trig1_2 0x00000000 +#define regk_iop_sw_cfg_trig1_3 0x00000000 +#define regk_iop_sw_cfg_trig2_0 0x00000000 +#define regk_iop_sw_cfg_trig2_1 0x00000000 +#define regk_iop_sw_cfg_trig2_2 0x00000000 +#define regk_iop_sw_cfg_trig2_3 0x00000000 +#define regk_iop_sw_cfg_trig3_0 0x00000000 +#define regk_iop_sw_cfg_trig3_1 0x00000000 +#define regk_iop_sw_cfg_trig3_2 0x00000000 +#define regk_iop_sw_cfg_trig3_3 0x00000000 +#define regk_iop_sw_cfg_trig4_0 0x00000001 +#define regk_iop_sw_cfg_trig4_1 0x00000001 +#define regk_iop_sw_cfg_trig4_2 0x00000001 +#define regk_iop_sw_cfg_trig4_3 0x00000001 +#define regk_iop_sw_cfg_trig5_0 0x00000001 +#define regk_iop_sw_cfg_trig5_1 0x00000001 +#define regk_iop_sw_cfg_trig5_2 0x00000001 +#define regk_iop_sw_cfg_trig5_3 0x00000001 +#define regk_iop_sw_cfg_trig6_0 0x00000001 +#define regk_iop_sw_cfg_trig6_1 0x00000001 +#define regk_iop_sw_cfg_trig6_2 0x00000001 +#define regk_iop_sw_cfg_trig6_3 0x00000001 +#define regk_iop_sw_cfg_trig7_0 0x00000001 +#define regk_iop_sw_cfg_trig7_1 0x00000001 +#define regk_iop_sw_cfg_trig7_2 0x00000001 +#define regk_iop_sw_cfg_trig7_3 0x00000001 +#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 000000000000..db347bcba025 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h @@ -0,0 +1,1758 @@ +#ifndef __iop_sw_cpu_defs_asm_h +#define __iop_sw_cpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_cpu_rw_mc_data___val___width 32 +#define reg_iop_sw_cpu_rw_mc_data_offset 4 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_addr_offset 8 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +#define reg_iop_sw_cpu_rs_mc_data_offset 12 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_data_offset 16 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_cpu_r_mc_stat_offset 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 + +/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 + +/* Register r_bus0_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus0_in_offset 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 + +/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 + +/* Register r_bus1_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus1_in_offset 60 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_gio_in_offset 80 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 +#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_r_intr0_offset 92 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_r_masked_intr0_offset 96 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 +#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_r_intr1_offset 108 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_r_masked_intr1_offset 112 + +/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 +#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 + +/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 + +/* Register r_intr2, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_intr2_offset 124 + +/* Register r_masked_intr2, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_masked_intr2_offset 128 + +/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 +#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 + +/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 + +/* Register r_intr3, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 +#define reg_iop_sw_cpu_r_intr3_offset 140 + +/* Register r_masked_intr3, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 +#define reg_iop_sw_cpu_r_masked_intr3_offset 144 + + +/* Constants */ +#define regk_iop_sw_cpu_copy 0x00000000 +#define regk_iop_sw_cpu_no 0x00000000 +#define regk_iop_sw_cpu_rd 0x00000002 +#define regk_iop_sw_cpu_reg_copy 0x00000001 +#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 +#define regk_iop_sw_cpu_wr 0x00000003 +#define regk_iop_sw_cpu_yes 0x00000001 +#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 000000000000..ee7dc0435b59 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h @@ -0,0 +1,1776 @@ +#ifndef __iop_sw_mpu_defs_asm_h +#define __iop_sw_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 +#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_mpu_rw_mc_data___val___width 32 +#define reg_iop_sw_mpu_rw_mc_data_offset 8 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_addr_offset 12 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +#define reg_iop_sw_mpu_rs_mc_data_offset 16 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_data_offset 20 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_mpu_r_mc_stat_offset 24 + +/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 + +/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 + +/* Register r_bus0_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus0_in_offset 44 + +/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 + +/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 + +/* Register r_bus1_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus1_in_offset 64 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_gio_in_offset 84 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_r_cpu_intr_offset 92 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp0_offset 104 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp1_offset 120 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp2_offset 136 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp3_offset 152 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 + + +/* Constants */ +#define regk_iop_sw_mpu_copy 0x00000000 +#define regk_iop_sw_mpu_cpu 0x00000000 +#define regk_iop_sw_mpu_mpu 0x00000001 +#define regk_iop_sw_mpu_no 0x00000000 +#define regk_iop_sw_mpu_nop 0x00000000 +#define regk_iop_sw_mpu_rd 0x00000002 +#define regk_iop_sw_mpu_reg_copy 0x00000001 +#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 +#define regk_iop_sw_mpu_set 0x00000001 +#define regk_iop_sw_mpu_spu0 0x00000002 +#define regk_iop_sw_mpu_spu1 0x00000003 +#define regk_iop_sw_mpu_wr 0x00000003 +#define regk_iop_sw_mpu_yes 0x00000001 +#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 000000000000..0929f144cfa1 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h @@ -0,0 +1,691 @@ +#ifndef __iop_sw_spu_defs_asm_h +#define __iop_sw_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_spu_rw_mc_ctrl_offset 0 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_spu_rw_mc_data___val___width 32 +#define reg_iop_sw_spu_rw_mc_data_offset 4 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_addr_offset 8 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +#define reg_iop_sw_spu_rs_mc_data_offset 12 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_data_offset 16 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_spu_r_mc_stat_offset 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 + +/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 + +/* Register r_bus0_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus0_in_offset 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 + +/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 + +/* Register r_bus1_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus1_in_offset 60 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_set_mask_offset 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_gio_in_offset 80 + +/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 + +/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 + +/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 + +/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 + +/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 + +/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 + +/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 + +/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_cpu_intr_offset 148 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_cpu_intr_offset 152 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 +#define reg_iop_sw_spu_r_hw_intr_offset 156 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_mpu_intr_offset 160 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 +#define reg_iop_sw_spu_r_mpu_intr_offset 164 + + +/* Constants */ +#define regk_iop_sw_spu_copy 0x00000000 +#define regk_iop_sw_spu_no 0x00000000 +#define regk_iop_sw_spu_nop 0x00000000 +#define regk_iop_sw_spu_rd 0x00000002 +#define regk_iop_sw_spu_reg_copy 0x00000001 +#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_spu_set 0x00000001 +#define regk_iop_sw_spu_wr 0x00000003 +#define regk_iop_sw_spu_yes 0x00000001 +#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h new file mode 100644 index 000000000000..7129a9a4bedc --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h @@ -0,0 +1,237 @@ +#ifndef __iop_timer_grp_defs_asm_h +#define __iop_timer_grp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_timer_grp.r + * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r + * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 +#define reg_iop_timer_grp_rw_cfg___clk_src___width 1 +#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 +#define reg_iop_timer_grp_rw_cfg___trig___lsb 1 +#define reg_iop_timer_grp_rw_cfg___trig___width 2 +#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 +#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 +#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 +#define reg_iop_timer_grp_rw_cfg___clk_div___width 8 +#define reg_iop_timer_grp_rw_cfg_offset 0 + +/* Register rw_half_period, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 +#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 +#define reg_iop_timer_grp_rw_half_period_offset 4 + +/* Register rw_half_period_len, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_half_period_len_offset 8 + +#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 +/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 +#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 +#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 +#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 +#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 +#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 +#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 +#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 +#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 +#define reg_iop_timer_grp_rw_tmr_cfg_offset 12 + +#define STRIDE_iop_timer_grp_rw_tmr_len 4 +/* Register rw_tmr_len, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 +#define reg_iop_timer_grp_rw_tmr_len___val___width 16 +#define reg_iop_timer_grp_rw_tmr_len_offset 44 + +/* Register rw_cmd, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_cmd___rst___lsb 0 +#define reg_iop_timer_grp_rw_cmd___rst___width 4 +#define reg_iop_timer_grp_rw_cmd___en___lsb 4 +#define reg_iop_timer_grp_rw_cmd___en___width 4 +#define reg_iop_timer_grp_rw_cmd___dis___lsb 8 +#define reg_iop_timer_grp_rw_cmd___dis___width 4 +#define reg_iop_timer_grp_rw_cmd___strb___lsb 12 +#define reg_iop_timer_grp_rw_cmd___strb___width 4 +#define reg_iop_timer_grp_rw_cmd_offset 60 + +/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 + +#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 +/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ +#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 +#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 +#define reg_iop_timer_grp_rs_tmr_cnt_offset 68 + +#define STRIDE_iop_timer_grp_r_tmr_cnt 8 +/* Register r_tmr_cnt, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 +#define reg_iop_timer_grp_r_tmr_cnt___val___width 16 +#define reg_iop_timer_grp_r_tmr_cnt_offset 72 + +/* Register rw_intr_mask, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 +#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 +#define reg_iop_timer_grp_rw_intr_mask_offset 100 + +/* Register rw_ack_intr, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 +#define reg_iop_timer_grp_rw_ack_intr_offset 104 + +/* Register r_intr, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_r_intr___tmr0___width 1 +#define reg_iop_timer_grp_r_intr___tmr0___bit 0 +#define reg_iop_timer_grp_r_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_r_intr___tmr1___width 1 +#define reg_iop_timer_grp_r_intr___tmr1___bit 1 +#define reg_iop_timer_grp_r_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_r_intr___tmr2___width 1 +#define reg_iop_timer_grp_r_intr___tmr2___bit 2 +#define reg_iop_timer_grp_r_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_r_intr___tmr3___width 1 +#define reg_iop_timer_grp_r_intr___tmr3___bit 3 +#define reg_iop_timer_grp_r_intr_offset 108 + +/* Register r_masked_intr, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 +#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 +#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 +#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 +#define reg_iop_timer_grp_r_masked_intr_offset 112 + + +/* Constants */ +#define regk_iop_timer_grp_clk200 0x00000000 +#define regk_iop_timer_grp_clk_gen 0x00000002 +#define regk_iop_timer_grp_complete 0x00000002 +#define regk_iop_timer_grp_div_clk200 0x00000001 +#define regk_iop_timer_grp_div_clk_gen 0x00000003 +#define regk_iop_timer_grp_ext 0x00000001 +#define regk_iop_timer_grp_hi 0x00000000 +#define regk_iop_timer_grp_long_period 0x00000001 +#define regk_iop_timer_grp_neg 0x00000002 +#define regk_iop_timer_grp_no 0x00000000 +#define regk_iop_timer_grp_once 0x00000003 +#define regk_iop_timer_grp_pause 0x00000001 +#define regk_iop_timer_grp_pos 0x00000001 +#define regk_iop_timer_grp_pos_neg 0x00000003 +#define regk_iop_timer_grp_pulse 0x00000000 +#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 +#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 +#define regk_iop_timer_grp_rw_cfg_default 0x00000002 +#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 +#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 +#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 +#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 +#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 +#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 +#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 +#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 +#define regk_iop_timer_grp_short_period 0x00000000 +#define regk_iop_timer_grp_stop 0x00000000 +#define regk_iop_timer_grp_tmr 0x00000004 +#define regk_iop_timer_grp_toggle 0x00000001 +#define regk_iop_timer_grp_yes 0x00000001 +#endif /* __iop_timer_grp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h new file mode 100644 index 000000000000..1005d9db80dc --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h @@ -0,0 +1,157 @@ +#ifndef __iop_trigger_grp_defs_asm_h +#define __iop_trigger_grp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_trigger_grp_rw_cfg 4 +/* Register rw_cfg, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_cfg___action___lsb 0 +#define reg_iop_trigger_grp_rw_cfg___action___width 2 +#define reg_iop_trigger_grp_rw_cfg___once___lsb 2 +#define reg_iop_trigger_grp_rw_cfg___once___width 1 +#define reg_iop_trigger_grp_rw_cfg___once___bit 2 +#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 +#define reg_iop_trigger_grp_rw_cfg___trig___width 3 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 +#define reg_iop_trigger_grp_rw_cfg_offset 0 + +/* Register rw_cmd, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 +#define reg_iop_trigger_grp_rw_cmd___dis___width 4 +#define reg_iop_trigger_grp_rw_cmd___en___lsb 4 +#define reg_iop_trigger_grp_rw_cmd___en___width 4 +#define reg_iop_trigger_grp_rw_cmd_offset 16 + +/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 +#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 +#define reg_iop_trigger_grp_rw_intr_mask_offset 20 + +/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 +#define reg_iop_trigger_grp_rw_ack_intr_offset 24 + +/* Register r_intr, scope iop_trigger_grp, type r */ +#define reg_iop_trigger_grp_r_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_r_intr___trig0___width 1 +#define reg_iop_trigger_grp_r_intr___trig0___bit 0 +#define reg_iop_trigger_grp_r_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_r_intr___trig1___width 1 +#define reg_iop_trigger_grp_r_intr___trig1___bit 1 +#define reg_iop_trigger_grp_r_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_r_intr___trig2___width 1 +#define reg_iop_trigger_grp_r_intr___trig2___bit 2 +#define reg_iop_trigger_grp_r_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_r_intr___trig3___width 1 +#define reg_iop_trigger_grp_r_intr___trig3___bit 3 +#define reg_iop_trigger_grp_r_intr_offset 28 + +/* Register r_masked_intr, scope iop_trigger_grp, type r */ +#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 +#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 +#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 +#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 +#define reg_iop_trigger_grp_r_masked_intr_offset 32 + + +/* Constants */ +#define regk_iop_trigger_grp_fall 0x00000002 +#define regk_iop_trigger_grp_fall_lo 0x00000006 +#define regk_iop_trigger_grp_no 0x00000000 +#define regk_iop_trigger_grp_off 0x00000000 +#define regk_iop_trigger_grp_pulse 0x00000000 +#define regk_iop_trigger_grp_rise 0x00000001 +#define regk_iop_trigger_grp_rise_fall 0x00000003 +#define regk_iop_trigger_grp_rise_fall_hi 0x00000007 +#define regk_iop_trigger_grp_rise_fall_lo 0x00000004 +#define regk_iop_trigger_grp_rise_hi 0x00000005 +#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 +#define regk_iop_trigger_grp_rw_cfg_size 0x00000004 +#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 +#define regk_iop_trigger_grp_toggle 0x00000003 +#define regk_iop_trigger_grp_yes 0x00000001 +#endif /* __iop_trigger_grp_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 000000000000..e13feb20a7e3 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h @@ -0,0 +1,64 @@ +#ifndef __iop_version_defs_asm_h +#define __iop_version_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_version.r + * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp + * last modfied: Mon Apr 11 16:08:44 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r + * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_version, scope iop_version, type r */ +#define reg_iop_version_r_version___nr___lsb 0 +#define reg_iop_version_r_version___nr___width 8 +#define reg_iop_version_r_version_offset 0 + + +/* Constants */ +#define regk_iop_version_v1_0 0x00000001 +#endif /* __iop_version_defs_asm_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h new file mode 100644 index 000000000000..90e4785b6474 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h @@ -0,0 +1,232 @@ +#ifndef __iop_crc_par_defs_h +#define __iop_crc_par_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_crc_par.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r + * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_crc_par */ + +/* Register rw_cfg, scope iop_crc_par, type rw */ +typedef struct { + unsigned int mode : 1; + unsigned int crc_out : 1; + unsigned int rev_out : 1; + unsigned int inv_out : 1; + unsigned int trig : 2; + unsigned int poly : 3; + unsigned int dummy1 : 23; +} reg_iop_crc_par_rw_cfg; +#define REG_RD_ADDR_iop_crc_par_rw_cfg 0 +#define REG_WR_ADDR_iop_crc_par_rw_cfg 0 + +/* Register rw_init_crc, scope iop_crc_par, type rw */ +typedef unsigned int reg_iop_crc_par_rw_init_crc; +#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 +#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 + +/* Register rw_correct_crc, scope iop_crc_par, type rw */ +typedef unsigned int reg_iop_crc_par_rw_correct_crc; +#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 +#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 + +/* Register rw_ctrl, scope iop_crc_par, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_iop_crc_par_rw_ctrl; +#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 +#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 + +/* Register rw_set_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int tr_dif : 1; + unsigned int dummy1 : 31; +} reg_iop_crc_par_rw_set_last; +#define REG_RD_ADDR_iop_crc_par_rw_set_last 16 +#define REG_WR_ADDR_iop_crc_par_rw_set_last 16 + +/* Register rw_wr1byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_crc_par_rw_wr1byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 +#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 + +/* Register rw_wr2byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_crc_par_rw_wr2byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 +#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 + +/* Register rw_wr3byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_crc_par_rw_wr3byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 +#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 + +/* Register rw_wr4byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_crc_par_rw_wr4byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 +#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 + +/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_crc_par_rw_wr1byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 +#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 + +/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_crc_par_rw_wr2byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 +#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 + +/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_crc_par_rw_wr3byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 +#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 + +/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_crc_par_rw_wr4byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 +#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 + +/* Register r_stat, scope iop_crc_par, type r */ +typedef struct { + unsigned int err : 1; + unsigned int busy : 1; + unsigned int dummy1 : 30; +} reg_iop_crc_par_r_stat; +#define REG_RD_ADDR_iop_crc_par_r_stat 52 + +/* Register r_sh_reg, scope iop_crc_par, type r */ +typedef unsigned int reg_iop_crc_par_r_sh_reg; +#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 + +/* Register r_crc, scope iop_crc_par, type r */ +typedef unsigned int reg_iop_crc_par_r_crc; +#define REG_RD_ADDR_iop_crc_par_r_crc 60 + +/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_crc_par_rw_strb_rec_dif_in; +#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 +#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 + + +/* Constants */ +enum { + regk_iop_crc_par_calc = 0x00000001, + regk_iop_crc_par_ccitt = 0x00000002, + regk_iop_crc_par_check = 0x00000000, + regk_iop_crc_par_crc16 = 0x00000001, + regk_iop_crc_par_crc32 = 0x00000000, + regk_iop_crc_par_crc5 = 0x00000003, + regk_iop_crc_par_crc5_11 = 0x00000004, + regk_iop_crc_par_dif_in = 0x00000002, + regk_iop_crc_par_hi = 0x00000000, + regk_iop_crc_par_neg = 0x00000002, + regk_iop_crc_par_no = 0x00000000, + regk_iop_crc_par_pos = 0x00000001, + regk_iop_crc_par_pos_neg = 0x00000003, + regk_iop_crc_par_rw_cfg_default = 0x00000000, + regk_iop_crc_par_rw_ctrl_default = 0x00000000, + regk_iop_crc_par_yes = 0x00000001 +}; +#endif /* __iop_crc_par_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h new file mode 100644 index 000000000000..76aec6e37f3e --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h @@ -0,0 +1,325 @@ +#ifndef __iop_dmc_in_defs_h +#define __iop_dmc_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_in.r + * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r + * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_dmc_in */ + +/* Register rw_cfg, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int sth_intr : 3; + unsigned int last_dis_dif : 1; + unsigned int dummy1 : 28; +} reg_iop_dmc_in_rw_cfg; +#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 +#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dif_dis : 1; + unsigned int stream_clr : 1; + unsigned int dummy1 : 29; +} reg_iop_dmc_in_rw_ctrl; +#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 + +/* Register r_stat, scope iop_dmc_in, type r */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dummy1 : 31; +} reg_iop_dmc_in_r_stat; +#define REG_RD_ADDR_iop_dmc_in_r_stat 8 + +/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 8; +} reg_iop_dmc_in_rw_stream_cmd; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 + +/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 + +/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 + +/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int eop : 1; + unsigned int wait : 1; + unsigned int keep_md : 1; + unsigned int size : 3; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_stream_ctrl; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 + +/* Register r_stream_stat, scope iop_dmc_in, type r */ +typedef struct { + unsigned int sth : 7; + unsigned int dummy1 : 9; + unsigned int full : 1; + unsigned int last_pkt : 1; + unsigned int data_md_valid : 1; + unsigned int ctxt_md_valid : 1; + unsigned int group_md_valid : 1; + unsigned int stream_busy : 1; + unsigned int cmd_rdy : 1; + unsigned int dummy2 : 9; +} reg_iop_dmc_in_r_stream_stat; +#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 + +/* Register r_data_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_in_r_data_descr; +#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 + +/* Register r_ctxt_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md0 : 16; +} reg_iop_dmc_in_r_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 + +/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ +typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 + +/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ +typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 + +/* Register r_group_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_in_r_group_descr; +#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 + +/* Register rw_data_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_in_rw_data_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 +#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 + +/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md0 : 16; +} reg_iop_dmc_in_rw_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 + +/* Register rw_group_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_in_rw_group_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 +#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 + +/* Register rw_intr_mask, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_intr_mask; +#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 +#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 + +/* Register rw_ack_intr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_ack_intr; +#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 +#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 + +/* Register r_intr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_r_intr; +#define REG_RD_ADDR_iop_dmc_in_r_intr 96 + +/* Register r_masked_intr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_r_masked_intr; +#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 + + +/* Constants */ +enum { + regk_iop_dmc_in_ack_pkt = 0x00000100, + regk_iop_dmc_in_array = 0x00000008, + regk_iop_dmc_in_burst = 0x00000020, + regk_iop_dmc_in_copy_next = 0x00000010, + regk_iop_dmc_in_copy_up = 0x00000020, + regk_iop_dmc_in_dis_c = 0x00000010, + regk_iop_dmc_in_dis_g = 0x00000020, + regk_iop_dmc_in_lim1 = 0x00000000, + regk_iop_dmc_in_lim16 = 0x00000004, + regk_iop_dmc_in_lim2 = 0x00000001, + regk_iop_dmc_in_lim32 = 0x00000005, + regk_iop_dmc_in_lim4 = 0x00000002, + regk_iop_dmc_in_lim64 = 0x00000006, + regk_iop_dmc_in_lim8 = 0x00000003, + regk_iop_dmc_in_load_c = 0x00000200, + regk_iop_dmc_in_load_c_n = 0x00000280, + regk_iop_dmc_in_load_c_next = 0x00000240, + regk_iop_dmc_in_load_d = 0x00000140, + regk_iop_dmc_in_load_g = 0x00000300, + regk_iop_dmc_in_load_g_down = 0x000003c0, + regk_iop_dmc_in_load_g_next = 0x00000340, + regk_iop_dmc_in_load_g_up = 0x00000380, + regk_iop_dmc_in_next_en = 0x00000010, + regk_iop_dmc_in_next_pkt = 0x00000010, + regk_iop_dmc_in_no = 0x00000000, + regk_iop_dmc_in_restore = 0x00000020, + regk_iop_dmc_in_rw_cfg_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, + regk_iop_dmc_in_rw_data_descr_default = 0x00000000, + regk_iop_dmc_in_rw_group_descr_default = 0x00000000, + regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, + regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, + regk_iop_dmc_in_save_down = 0x00000020, + regk_iop_dmc_in_save_up = 0x00000020, + regk_iop_dmc_in_set_reg = 0x00000050, + regk_iop_dmc_in_set_w_size1 = 0x00000190, + regk_iop_dmc_in_set_w_size2 = 0x000001a0, + regk_iop_dmc_in_set_w_size4 = 0x000001c0, + regk_iop_dmc_in_store_c = 0x00000002, + regk_iop_dmc_in_store_descr = 0x00000000, + regk_iop_dmc_in_store_g = 0x00000004, + regk_iop_dmc_in_store_md = 0x00000001, + regk_iop_dmc_in_update_down = 0x00000020, + regk_iop_dmc_in_yes = 0x00000001 +}; +#endif /* __iop_dmc_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h new file mode 100644 index 000000000000..938a0d4c4604 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h @@ -0,0 +1,326 @@ +#ifndef __iop_dmc_out_defs_h +#define __iop_dmc_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_out.r + * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r + * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_dmc_out */ + +/* Register rw_cfg, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int trf_lim : 16; + unsigned int last_at_trf_lim : 1; + unsigned int dth_intr : 3; + unsigned int dummy1 : 12; +} reg_iop_dmc_out_rw_cfg; +#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 +#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dif_dis : 1; + unsigned int dummy1 : 30; +} reg_iop_dmc_out_rw_ctrl; +#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 + +/* Register r_stat, scope iop_dmc_out, type r */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dummy1 : 31; +} reg_iop_dmc_out_r_stat; +#define REG_RD_ADDR_iop_dmc_out_r_stat 8 + +/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 8; +} reg_iop_dmc_out_rw_stream_cmd; +#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 +#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 + +/* Register rs_stream_data, scope iop_dmc_out, type rs */ +typedef unsigned int reg_iop_dmc_out_rs_stream_data; +#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 + +/* Register r_stream_data, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_stream_data; +#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 + +/* Register r_stream_stat, scope iop_dmc_out, type r */ +typedef struct { + unsigned int dth : 7; + unsigned int dummy1 : 9; + unsigned int dv : 1; + unsigned int all_avail : 1; + unsigned int last : 1; + unsigned int size : 3; + unsigned int data_md_valid : 1; + unsigned int ctxt_md_valid : 1; + unsigned int group_md_valid : 1; + unsigned int stream_busy : 1; + unsigned int cmd_rdy : 1; + unsigned int cmd_rq : 1; + unsigned int dummy2 : 4; +} reg_iop_dmc_out_r_stream_stat; +#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 + +/* Register r_data_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_out_r_data_descr; +#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 + +/* Register r_ctxt_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md0 : 16; +} reg_iop_dmc_out_r_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 + +/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 + +/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 + +/* Register r_group_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_out_r_group_descr; +#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 + +/* Register rw_data_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_out_rw_data_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 +#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 + +/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md0 : 16; +} reg_iop_dmc_out_rw_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ +typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ +typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 + +/* Register rw_group_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_out_rw_group_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 +#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 + +/* Register rw_intr_mask, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_rw_intr_mask; +#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 +#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 + +/* Register rw_ack_intr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_rw_ack_intr; +#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 +#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 + +/* Register r_intr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_r_intr; +#define REG_RD_ADDR_iop_dmc_out_r_intr 92 + +/* Register r_masked_intr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_r_masked_intr; +#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 + + +/* Constants */ +enum { + regk_iop_dmc_out_ack_pkt = 0x00000100, + regk_iop_dmc_out_array = 0x00000008, + regk_iop_dmc_out_burst = 0x00000020, + regk_iop_dmc_out_copy_next = 0x00000010, + regk_iop_dmc_out_copy_up = 0x00000020, + regk_iop_dmc_out_dis_c = 0x00000010, + regk_iop_dmc_out_dis_g = 0x00000020, + regk_iop_dmc_out_lim1 = 0x00000000, + regk_iop_dmc_out_lim16 = 0x00000004, + regk_iop_dmc_out_lim2 = 0x00000001, + regk_iop_dmc_out_lim32 = 0x00000005, + regk_iop_dmc_out_lim4 = 0x00000002, + regk_iop_dmc_out_lim64 = 0x00000006, + regk_iop_dmc_out_lim8 = 0x00000003, + regk_iop_dmc_out_load_c = 0x00000200, + regk_iop_dmc_out_load_c_n = 0x00000280, + regk_iop_dmc_out_load_c_next = 0x00000240, + regk_iop_dmc_out_load_d = 0x00000140, + regk_iop_dmc_out_load_g = 0x00000300, + regk_iop_dmc_out_load_g_down = 0x000003c0, + regk_iop_dmc_out_load_g_next = 0x00000340, + regk_iop_dmc_out_load_g_up = 0x00000380, + regk_iop_dmc_out_next_en = 0x00000010, + regk_iop_dmc_out_next_pkt = 0x00000010, + regk_iop_dmc_out_no = 0x00000000, + regk_iop_dmc_out_restore = 0x00000020, + regk_iop_dmc_out_rw_cfg_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, + regk_iop_dmc_out_rw_data_descr_default = 0x00000000, + regk_iop_dmc_out_rw_group_descr_default = 0x00000000, + regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, + regk_iop_dmc_out_save_down = 0x00000020, + regk_iop_dmc_out_save_up = 0x00000020, + regk_iop_dmc_out_set_reg = 0x00000050, + regk_iop_dmc_out_set_w_size1 = 0x00000190, + regk_iop_dmc_out_set_w_size2 = 0x000001a0, + regk_iop_dmc_out_set_w_size4 = 0x000001c0, + regk_iop_dmc_out_store_c = 0x00000002, + regk_iop_dmc_out_store_descr = 0x00000000, + regk_iop_dmc_out_store_g = 0x00000004, + regk_iop_dmc_out_store_md = 0x00000001, + regk_iop_dmc_out_update_down = 0x00000020, + regk_iop_dmc_out_yes = 0x00000001 +}; +#endif /* __iop_dmc_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h new file mode 100644 index 000000000000..e0c982b263fa --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h @@ -0,0 +1,255 @@ +#ifndef __iop_fifo_in_defs_h +#define __iop_fifo_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:07 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r + * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_in */ + +/* Register rw_cfg, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int avail_lim : 3; + unsigned int byte_order : 2; + unsigned int trig : 2; + unsigned int last_dis_dif_in : 1; + unsigned int mode : 2; + unsigned int dummy1 : 22; +} reg_iop_fifo_in_rw_cfg; +#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 +#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_rw_ctrl; +#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 + +/* Register r_stat, scope iop_fifo_in, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 18; +} reg_iop_fifo_in_r_stat; +#define REG_RD_ADDR_iop_fifo_in_r_stat 8 + +/* Register rs_rd1byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_in_rs_rd1byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 + +/* Register r_rd1byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_in_r_rd1byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 + +/* Register rs_rd2byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_in_rs_rd2byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 + +/* Register r_rd2byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_in_r_rd2byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 + +/* Register rs_rd3byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_in_rs_rd3byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 + +/* Register r_rd3byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_in_r_rd3byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 + +/* Register rs_rd4byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_in_rs_rd4byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 + +/* Register r_rd4byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_in_r_rd4byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 + +/* Register rw_set_last, scope iop_fifo_in, type rw */ +typedef unsigned int reg_iop_fifo_in_rw_set_last; +#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 +#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 + +/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_rw_strb_dif_in; +#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 +#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 + +/* Register rw_intr_mask, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 +#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 + +/* Register rw_ack_intr, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 +#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 + +/* Register r_intr, scope iop_fifo_in, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_r_intr; +#define REG_RD_ADDR_iop_fifo_in_r_intr 60 + +/* Register r_masked_intr, scope iop_fifo_in, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 + + +/* Constants */ +enum { + regk_iop_fifo_in_dif_in = 0x00000002, + regk_iop_fifo_in_hi = 0x00000000, + regk_iop_fifo_in_neg = 0x00000002, + regk_iop_fifo_in_no = 0x00000000, + regk_iop_fifo_in_order16 = 0x00000001, + regk_iop_fifo_in_order24 = 0x00000002, + regk_iop_fifo_in_order32 = 0x00000003, + regk_iop_fifo_in_order8 = 0x00000000, + regk_iop_fifo_in_pos = 0x00000001, + regk_iop_fifo_in_pos_neg = 0x00000003, + regk_iop_fifo_in_rw_cfg_default = 0x00000024, + regk_iop_fifo_in_rw_ctrl_default = 0x00000000, + regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_in_rw_set_last_default = 0x00000000, + regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, + regk_iop_fifo_in_size16 = 0x00000002, + regk_iop_fifo_in_size24 = 0x00000001, + regk_iop_fifo_in_size32 = 0x00000000, + regk_iop_fifo_in_size8 = 0x00000003, + regk_iop_fifo_in_yes = 0x00000001 +}; +#endif /* __iop_fifo_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h new file mode 100644 index 000000000000..798ac95870e9 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h @@ -0,0 +1,164 @@ +#ifndef __iop_fifo_in_extra_defs_h +#define __iop_fifo_in_extra_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:08 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_in_extra */ + +/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ +typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 + +/* Register r_stat, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 18; +} reg_iop_fifo_in_extra_r_stat; +#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 + +/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_extra_rw_strb_dif_in; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 + +/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 + +/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 + +/* Register r_intr, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_r_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 + +/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 + + +/* Constants */ +enum { + regk_iop_fifo_in_extra_fifo_in = 0x00000002, + regk_iop_fifo_in_extra_no = 0x00000000, + regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_in_extra_yes = 0x00000001 +}; +#endif /* __iop_fifo_in_extra_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h new file mode 100644 index 000000000000..833e10f02526 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h @@ -0,0 +1,278 @@ +#ifndef __iop_fifo_out_defs_h +#define __iop_fifo_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:09 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r + * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_out */ + +/* Register rw_cfg, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int free_lim : 3; + unsigned int byte_order : 2; + unsigned int trig : 2; + unsigned int last_dis_dif_in : 1; + unsigned int mode : 2; + unsigned int delay_out_last : 1; + unsigned int last_dis_dif_out : 1; + unsigned int dummy1 : 20; +} reg_iop_fifo_out_rw_cfg; +#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 +#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 30; +} reg_iop_fifo_out_rw_ctrl; +#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 + +/* Register r_stat, scope iop_fifo_out, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int zero_data_last : 1; + unsigned int dummy1 : 17; +} reg_iop_fifo_out_r_stat; +#define REG_RD_ADDR_iop_fifo_out_r_stat 8 + +/* Register rw_wr1byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_out_rw_wr1byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 +#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 + +/* Register rw_wr2byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_out_rw_wr2byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 +#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 + +/* Register rw_wr3byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_out_rw_wr3byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 +#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 + +/* Register rw_wr4byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_out_rw_wr4byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 +#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 + +/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_out_rw_wr1byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 +#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 + +/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_out_rw_wr2byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 +#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 + +/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_out_rw_wr3byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 +#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 + +/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_out_rw_wr4byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 +#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 + +/* Register rw_set_last, scope iop_fifo_out, type rw */ +typedef unsigned int reg_iop_fifo_out_rw_set_last; +#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 +#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 + +/* Register rs_rd_data, scope iop_fifo_out, type rs */ +typedef unsigned int reg_iop_fifo_out_rs_rd_data; +#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 + +/* Register r_rd_data, scope iop_fifo_out, type r */ +typedef unsigned int reg_iop_fifo_out_r_rd_data; +#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 + +/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ +typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; +#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 +#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 + +/* Register rw_intr_mask, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 +#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 + +/* Register rw_ack_intr, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 +#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 + +/* Register r_intr, scope iop_fifo_out, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_r_intr; +#define REG_RD_ADDR_iop_fifo_out_r_intr 68 + +/* Register r_masked_intr, scope iop_fifo_out, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 + + +/* Constants */ +enum { + regk_iop_fifo_out_hi = 0x00000000, + regk_iop_fifo_out_neg = 0x00000002, + regk_iop_fifo_out_no = 0x00000000, + regk_iop_fifo_out_order16 = 0x00000001, + regk_iop_fifo_out_order24 = 0x00000002, + regk_iop_fifo_out_order32 = 0x00000003, + regk_iop_fifo_out_order8 = 0x00000000, + regk_iop_fifo_out_pos = 0x00000001, + regk_iop_fifo_out_pos_neg = 0x00000003, + regk_iop_fifo_out_rw_cfg_default = 0x00000024, + regk_iop_fifo_out_rw_ctrl_default = 0x00000000, + regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_out_rw_set_last_default = 0x00000000, + regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, + regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, + regk_iop_fifo_out_size16 = 0x00000002, + regk_iop_fifo_out_size24 = 0x00000001, + regk_iop_fifo_out_size32 = 0x00000000, + regk_iop_fifo_out_size8 = 0x00000003, + regk_iop_fifo_out_yes = 0x00000001 +}; +#endif /* __iop_fifo_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h new file mode 100644 index 000000000000..4a840aae84ee --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h @@ -0,0 +1,164 @@ +#ifndef __iop_fifo_out_extra_defs_h +#define __iop_fifo_out_extra_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:10 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_out_extra */ + +/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ +typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; +#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 + +/* Register r_rd_data, scope iop_fifo_out_extra, type r */ +typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; +#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 + +/* Register r_stat, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int zero_data_last : 1; + unsigned int dummy1 : 17; +} reg_iop_fifo_out_extra_r_stat; +#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 + +/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ +typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 + +/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 + +/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 + +/* Register r_intr, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_r_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 + +/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 + + +/* Constants */ +enum { + regk_iop_fifo_out_extra_no = 0x00000000, + regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_out_extra_yes = 0x00000001 +}; +#endif /* __iop_fifo_out_extra_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h new file mode 100644 index 000000000000..c2b0ba1be60f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h @@ -0,0 +1,190 @@ +#ifndef __iop_mpu_defs_h +#define __iop_mpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_mpu.r + * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r + * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_mpu */ + +#define STRIDE_iop_mpu_rw_r 4 +/* Register rw_r, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_r; +#define REG_RD_ADDR_iop_mpu_rw_r 0 +#define REG_WR_ADDR_iop_mpu_rw_r 0 + +/* Register rw_ctrl, scope iop_mpu, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_iop_mpu_rw_ctrl; +#define REG_RD_ADDR_iop_mpu_rw_ctrl 128 +#define REG_WR_ADDR_iop_mpu_rw_ctrl 128 + +/* Register r_pc, scope iop_mpu, type r */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_r_pc; +#define REG_RD_ADDR_iop_mpu_r_pc 132 + +/* Register r_stat, scope iop_mpu, type r */ +typedef struct { + unsigned int instr_reg_busy : 1; + unsigned int intr_busy : 1; + unsigned int intr_vect : 16; + unsigned int dummy1 : 14; +} reg_iop_mpu_r_stat; +#define REG_RD_ADDR_iop_mpu_r_stat 136 + +/* Register rw_instr, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_instr; +#define REG_RD_ADDR_iop_mpu_rw_instr 140 +#define REG_WR_ADDR_iop_mpu_rw_instr 140 + +/* Register rw_immediate, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_immediate; +#define REG_RD_ADDR_iop_mpu_rw_immediate 144 +#define REG_WR_ADDR_iop_mpu_rw_immediate 144 + +/* Register r_trace, scope iop_mpu, type r */ +typedef struct { + unsigned int intr_vect : 16; + unsigned int pc : 12; + unsigned int en : 1; + unsigned int instr_reg_busy : 1; + unsigned int intr_busy : 1; + unsigned int dummy1 : 1; +} reg_iop_mpu_r_trace; +#define REG_RD_ADDR_iop_mpu_r_trace 148 + +/* Register r_wr_stat, scope iop_mpu, type r */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_mpu_r_wr_stat; +#define REG_RD_ADDR_iop_mpu_r_wr_stat 152 + +#define STRIDE_iop_mpu_rw_thread 4 +/* Register rw_thread, scope iop_mpu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_rw_thread; +#define REG_RD_ADDR_iop_mpu_rw_thread 156 +#define REG_WR_ADDR_iop_mpu_rw_thread 156 + +#define STRIDE_iop_mpu_rw_intr 4 +/* Register rw_intr, scope iop_mpu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_rw_intr; +#define REG_RD_ADDR_iop_mpu_rw_intr 196 +#define REG_WR_ADDR_iop_mpu_rw_intr 196 + + +/* Constants */ +enum { + regk_iop_mpu_no = 0x00000000, + regk_iop_mpu_r_pc_default = 0x00000000, + regk_iop_mpu_rw_ctrl_default = 0x00000000, + regk_iop_mpu_rw_intr_size = 0x00000010, + regk_iop_mpu_rw_r_size = 0x00000010, + regk_iop_mpu_rw_thread_default = 0x00000000, + regk_iop_mpu_rw_thread_size = 0x00000004, + regk_iop_mpu_yes = 0x00000001 +}; +#endif /* __iop_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h new file mode 100644 index 000000000000..2ec897ced166 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h @@ -0,0 +1,764 @@ +/* ************************************************************************* */ +/* This file is autogenerated by IOPASM Version 1.2 */ +/* DO NOT EDIT THIS FILE - All changes will be lost! */ +/* ************************************************************************* */ + + + +#ifndef __IOP_MPU_MACROS_H__ +#define __IOP_MPU_MACROS_H__ + + +/* ************************************************************************* */ +/* REGISTER DEFINITIONS */ +/* ************************************************************************* */ +#define MPU_R0 (0x0) +#define MPU_R1 (0x1) +#define MPU_R2 (0x2) +#define MPU_R3 (0x3) +#define MPU_R4 (0x4) +#define MPU_R5 (0x5) +#define MPU_R6 (0x6) +#define MPU_R7 (0x7) +#define MPU_R8 (0x8) +#define MPU_R9 (0x9) +#define MPU_R10 (0xa) +#define MPU_R11 (0xb) +#define MPU_R12 (0xc) +#define MPU_R13 (0xd) +#define MPU_R14 (0xe) +#define MPU_R15 (0xf) +#define MPU_PC (0x2) +#define MPU_WSTS (0x3) +#define MPU_JADDR (0x4) +#define MPU_IRP (0x5) +#define MPU_SRP (0x6) +#define MPU_T0 (0x8) +#define MPU_T1 (0x9) +#define MPU_T2 (0xa) +#define MPU_T3 (0xb) +#define MPU_I0 (0x10) +#define MPU_I1 (0x11) +#define MPU_I2 (0x12) +#define MPU_I3 (0x13) +#define MPU_I4 (0x14) +#define MPU_I5 (0x15) +#define MPU_I6 (0x16) +#define MPU_I7 (0x17) +#define MPU_I8 (0x18) +#define MPU_I9 (0x19) +#define MPU_I10 (0x1a) +#define MPU_I11 (0x1b) +#define MPU_I12 (0x1c) +#define MPU_I13 (0x1d) +#define MPU_I14 (0x1e) +#define MPU_I15 (0x1f) +#define MPU_P2 (0x2) +#define MPU_P3 (0x3) +#define MPU_P5 (0x5) +#define MPU_P6 (0x6) +#define MPU_P8 (0x8) +#define MPU_P9 (0x9) +#define MPU_P10 (0xa) +#define MPU_P11 (0xb) +#define MPU_P16 (0x10) +#define MPU_P17 (0x12) +#define MPU_P18 (0x12) +#define MPU_P19 (0x13) +#define MPU_P20 (0x14) +#define MPU_P21 (0x15) +#define MPU_P22 (0x16) +#define MPU_P23 (0x17) +#define MPU_P24 (0x18) +#define MPU_P25 (0x19) +#define MPU_P26 (0x1a) +#define MPU_P27 (0x1b) +#define MPU_P28 (0x1c) +#define MPU_P29 (0x1d) +#define MPU_P30 (0x1e) +#define MPU_P31 (0x1f) +#define MPU_P1 (0x1) +#define MPU_REGA (0x1) + + + +/* ************************************************************************* */ +/* ADDRESS MACROS */ +/* ************************************************************************* */ +#define MK_DWORD_ADDR(ADDR) (ADDR >> 2) +#define MK_BYTE_ADDR(ADDR) (ADDR) + + + +/* ************************************************************************* */ +/* INSTRUCTION MACROS */ +/* ************************************************************************* */ +#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 21)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 21)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_DI() (0x40000001) + +#define MPU_EI() (0x40000003) + +#define MPU_HALT() (0x40000002) + +#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JNT() (0x61000000) + +#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_NOP() (0x40000000) + +#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_RET() (0x63003000) + +#define MPU_RETI() (0x63602800) + +#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ + | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + + +#endif /* end of __IOP_MPU_MACROS_H__ */ +/* End of iop_mpu_macros.h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h new file mode 100644 index 000000000000..756550f5d6cb --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h @@ -0,0 +1,44 @@ +/* Autogenerated Changes here will be lost! + * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg + */ +#define regi_iop_version (regi_iop + 0) +#define regi_iop_fifo_in0_extra (regi_iop + 64) +#define regi_iop_fifo_in1_extra (regi_iop + 128) +#define regi_iop_fifo_out0_extra (regi_iop + 192) +#define regi_iop_fifo_out1_extra (regi_iop + 256) +#define regi_iop_trigger_grp0 (regi_iop + 320) +#define regi_iop_trigger_grp1 (regi_iop + 384) +#define regi_iop_trigger_grp2 (regi_iop + 448) +#define regi_iop_trigger_grp3 (regi_iop + 512) +#define regi_iop_trigger_grp4 (regi_iop + 576) +#define regi_iop_trigger_grp5 (regi_iop + 640) +#define regi_iop_trigger_grp6 (regi_iop + 704) +#define regi_iop_trigger_grp7 (regi_iop + 768) +#define regi_iop_crc_par0 (regi_iop + 896) +#define regi_iop_crc_par1 (regi_iop + 1024) +#define regi_iop_dmc_in0 (regi_iop + 1152) +#define regi_iop_dmc_in1 (regi_iop + 1280) +#define regi_iop_dmc_out0 (regi_iop + 1408) +#define regi_iop_dmc_out1 (regi_iop + 1536) +#define regi_iop_fifo_in0 (regi_iop + 1664) +#define regi_iop_fifo_in1 (regi_iop + 1792) +#define regi_iop_fifo_out0 (regi_iop + 1920) +#define regi_iop_fifo_out1 (regi_iop + 2048) +#define regi_iop_scrc_in0 (regi_iop + 2176) +#define regi_iop_scrc_in1 (regi_iop + 2304) +#define regi_iop_scrc_out0 (regi_iop + 2432) +#define regi_iop_scrc_out1 (regi_iop + 2560) +#define regi_iop_timer_grp0 (regi_iop + 2688) +#define regi_iop_timer_grp1 (regi_iop + 2816) +#define regi_iop_timer_grp2 (regi_iop + 2944) +#define regi_iop_timer_grp3 (regi_iop + 3072) +#define regi_iop_sap_in (regi_iop + 3328) +#define regi_iop_sap_out (regi_iop + 3584) +#define regi_iop_spu0 (regi_iop + 3840) +#define regi_iop_spu1 (regi_iop + 4096) +#define regi_iop_sw_cfg (regi_iop + 4352) +#define regi_iop_sw_cpu (regi_iop + 4608) +#define regi_iop_sw_mpu (regi_iop + 4864) +#define regi_iop_sw_spu0 (regi_iop + 5120) +#define regi_iop_sw_spu1 (regi_iop + 5376) +#define regi_iop_mpu (regi_iop + 5632) diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 000000000000..5548ac10074f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h @@ -0,0 +1,179 @@ +#ifndef __iop_sap_in_defs_h +#define __iop_sap_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_in.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r + * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_in */ + +/* Register rw_bus0_sync, scope iop_sap_in, type rw */ +typedef struct { + unsigned int byte0_sel : 2; + unsigned int byte0_ext_src : 3; + unsigned int byte0_edge : 2; + unsigned int byte0_delay : 1; + unsigned int byte1_sel : 2; + unsigned int byte1_ext_src : 3; + unsigned int byte1_edge : 2; + unsigned int byte1_delay : 1; + unsigned int byte2_sel : 2; + unsigned int byte2_ext_src : 3; + unsigned int byte2_edge : 2; + unsigned int byte2_delay : 1; + unsigned int byte3_sel : 2; + unsigned int byte3_ext_src : 3; + unsigned int byte3_edge : 2; + unsigned int byte3_delay : 1; +} reg_iop_sap_in_rw_bus0_sync; +#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 +#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 + +/* Register rw_bus1_sync, scope iop_sap_in, type rw */ +typedef struct { + unsigned int byte0_sel : 2; + unsigned int byte0_ext_src : 3; + unsigned int byte0_edge : 2; + unsigned int byte0_delay : 1; + unsigned int byte1_sel : 2; + unsigned int byte1_ext_src : 3; + unsigned int byte1_edge : 2; + unsigned int byte1_delay : 1; + unsigned int byte2_sel : 2; + unsigned int byte2_ext_src : 3; + unsigned int byte2_edge : 2; + unsigned int byte2_delay : 1; + unsigned int byte3_sel : 2; + unsigned int byte3_ext_src : 3; + unsigned int byte3_edge : 2; + unsigned int byte3_delay : 1; +} reg_iop_sap_in_rw_bus1_sync; +#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 +#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 1; + unsigned int logic : 2; + unsigned int dummy1 : 22; +} reg_iop_sap_in_rw_gio; +#define REG_RD_ADDR_iop_sap_in_rw_gio 8 +#define REG_WR_ADDR_iop_sap_in_rw_gio 8 + + +/* Constants */ +enum { + regk_iop_sap_in_and = 0x00000002, + regk_iop_sap_in_ext_clk200 = 0x00000003, + regk_iop_sap_in_gio1 = 0x00000000, + regk_iop_sap_in_gio13 = 0x00000005, + regk_iop_sap_in_gio18 = 0x00000003, + regk_iop_sap_in_gio19 = 0x00000004, + regk_iop_sap_in_gio21 = 0x00000006, + regk_iop_sap_in_gio23 = 0x00000005, + regk_iop_sap_in_gio29 = 0x00000007, + regk_iop_sap_in_gio5 = 0x00000004, + regk_iop_sap_in_gio6 = 0x00000001, + regk_iop_sap_in_gio7 = 0x00000002, + regk_iop_sap_in_inv = 0x00000001, + regk_iop_sap_in_neg = 0x00000002, + regk_iop_sap_in_no = 0x00000000, + regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, + regk_iop_sap_in_none = 0x00000000, + regk_iop_sap_in_or = 0x00000003, + regk_iop_sap_in_pos = 0x00000001, + regk_iop_sap_in_pos_neg = 0x00000003, + regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, + regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, + regk_iop_sap_in_rw_gio_default = 0x00000002, + regk_iop_sap_in_rw_gio_size = 0x00000020, + regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, + regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, + regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, + regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, + regk_iop_sap_in_tmr_clk200 = 0x00000000, + regk_iop_sap_in_two_clk200 = 0x00000002, + regk_iop_sap_in_yes = 0x00000001 +}; +#endif /* __iop_sap_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 000000000000..273936996183 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h @@ -0,0 +1,306 @@ +#ifndef __iop_sap_out_defs_h +#define __iop_sap_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_out.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r + * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_out */ + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +typedef struct { + unsigned int clk0_src : 2; + unsigned int clk0_gate_src : 2; + unsigned int clk0_force_src : 3; + unsigned int clk1_src : 2; + unsigned int clk1_gate_src : 2; + unsigned int clk1_force_src : 3; + unsigned int clk2_src : 2; + unsigned int clk2_gate_src : 2; + unsigned int clk2_force_src : 3; + unsigned int clk3_src : 2; + unsigned int clk3_gate_src : 2; + unsigned int clk3_force_src : 3; + unsigned int dummy1 : 4; +} reg_iop_sap_out_rw_gen_gated; +#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 +#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 + +/* Register rw_bus0, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte2_clk_sel : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_bus0; +#define REG_RD_ADDR_iop_sap_out_rw_bus0 4 +#define REG_WR_ADDR_iop_sap_out_rw_bus0 4 + +/* Register rw_bus1, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte2_clk_sel : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_bus1; +#define REG_RD_ADDR_iop_sap_out_rw_bus1 8 +#define REG_WR_ADDR_iop_sap_out_rw_bus1 8 + +/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_clk_ext : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_logic : 2; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_clk_ext : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus0_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 +#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 + +/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 3; + unsigned int byte2_clk_ext : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_logic : 2; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_clk_ext : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus0_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 +#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 + +/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_clk_ext : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_logic : 2; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_clk_ext : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus1_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 +#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 + +/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 3; + unsigned int byte2_clk_ext : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_logic : 2; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_clk_ext : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus1_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 +#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +typedef struct { + unsigned int out_clk_sel : 3; + unsigned int out_clk_ext : 4; + unsigned int out_gated_clk : 2; + unsigned int out_clk_inv : 1; + unsigned int out_logic : 1; + unsigned int oe_clk_sel : 3; + unsigned int oe_clk_ext : 3; + unsigned int oe_gated_clk : 2; + unsigned int oe_clk_inv : 1; + unsigned int oe_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_gio; +#define REG_RD_ADDR_iop_sap_out_rw_gio 28 +#define REG_WR_ADDR_iop_sap_out_rw_gio 28 + + +/* Constants */ +enum { + regk_iop_sap_out_and = 0x00000002, + regk_iop_sap_out_clk0 = 0x00000000, + regk_iop_sap_out_clk1 = 0x00000001, + regk_iop_sap_out_clk12 = 0x00000002, + regk_iop_sap_out_clk2 = 0x00000002, + regk_iop_sap_out_clk200 = 0x00000001, + regk_iop_sap_out_clk3 = 0x00000003, + regk_iop_sap_out_ext = 0x00000003, + regk_iop_sap_out_gated = 0x00000004, + regk_iop_sap_out_gio1 = 0x00000000, + regk_iop_sap_out_gio13 = 0x00000002, + regk_iop_sap_out_gio13_clk = 0x0000000c, + regk_iop_sap_out_gio15 = 0x00000001, + regk_iop_sap_out_gio18 = 0x00000003, + regk_iop_sap_out_gio18_clk = 0x0000000d, + regk_iop_sap_out_gio1_clk = 0x00000008, + regk_iop_sap_out_gio21_clk = 0x0000000e, + regk_iop_sap_out_gio23 = 0x00000002, + regk_iop_sap_out_gio29_clk = 0x0000000f, + regk_iop_sap_out_gio31 = 0x00000003, + regk_iop_sap_out_gio5 = 0x00000001, + regk_iop_sap_out_gio5_clk = 0x00000009, + regk_iop_sap_out_gio6_clk = 0x0000000a, + regk_iop_sap_out_gio7 = 0x00000000, + regk_iop_sap_out_gio7_clk = 0x0000000b, + regk_iop_sap_out_gio_in13 = 0x00000001, + regk_iop_sap_out_gio_in21 = 0x00000002, + regk_iop_sap_out_gio_in29 = 0x00000003, + regk_iop_sap_out_gio_in5 = 0x00000000, + regk_iop_sap_out_inv = 0x00000001, + regk_iop_sap_out_nand = 0x00000003, + regk_iop_sap_out_no = 0x00000000, + regk_iop_sap_out_none = 0x00000000, + regk_iop_sap_out_rw_bus0_default = 0x00000000, + regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus1_default = 0x00000000, + regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_gen_gated_default = 0x00000000, + regk_iop_sap_out_rw_gio_default = 0x00000000, + regk_iop_sap_out_rw_gio_size = 0x00000020, + regk_iop_sap_out_spu0_gio0 = 0x00000002, + regk_iop_sap_out_spu0_gio1 = 0x00000003, + regk_iop_sap_out_spu0_gio12 = 0x00000004, + regk_iop_sap_out_spu0_gio13 = 0x00000004, + regk_iop_sap_out_spu0_gio14 = 0x00000004, + regk_iop_sap_out_spu0_gio15 = 0x00000004, + regk_iop_sap_out_spu0_gio2 = 0x00000002, + regk_iop_sap_out_spu0_gio3 = 0x00000003, + regk_iop_sap_out_spu0_gio4 = 0x00000002, + regk_iop_sap_out_spu0_gio5 = 0x00000003, + regk_iop_sap_out_spu0_gio6 = 0x00000002, + regk_iop_sap_out_spu0_gio7 = 0x00000003, + regk_iop_sap_out_spu1_gio0 = 0x00000005, + regk_iop_sap_out_spu1_gio1 = 0x00000006, + regk_iop_sap_out_spu1_gio12 = 0x00000007, + regk_iop_sap_out_spu1_gio13 = 0x00000007, + regk_iop_sap_out_spu1_gio14 = 0x00000007, + regk_iop_sap_out_spu1_gio15 = 0x00000007, + regk_iop_sap_out_spu1_gio2 = 0x00000005, + regk_iop_sap_out_spu1_gio3 = 0x00000006, + regk_iop_sap_out_spu1_gio4 = 0x00000005, + regk_iop_sap_out_spu1_gio5 = 0x00000006, + regk_iop_sap_out_spu1_gio6 = 0x00000005, + regk_iop_sap_out_spu1_gio7 = 0x00000006, + regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, + regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, + regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, + regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, + regk_iop_sap_out_tmr = 0x00000005, + regk_iop_sap_out_yes = 0x00000001 +}; +#endif /* __iop_sap_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h new file mode 100644 index 000000000000..4f0a9a81e737 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h @@ -0,0 +1,160 @@ +#ifndef __iop_scrc_in_defs_h +#define __iop_scrc_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_in.r + * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r + * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_scrc_in */ + +/* Register rw_cfg, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int trig : 2; + unsigned int dummy1 : 30; +} reg_iop_scrc_in_rw_cfg; +#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 +#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_in_rw_ctrl; +#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 + +/* Register r_stat, scope iop_scrc_in, type r */ +typedef struct { + unsigned int err : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_in_r_stat; +#define REG_RD_ADDR_iop_scrc_in_r_stat 8 + +/* Register rw_init_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_init_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 +#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 + +/* Register rs_computed_crc, scope iop_scrc_in, type rs */ +typedef unsigned int reg_iop_scrc_in_rs_computed_crc; +#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 + +/* Register r_computed_crc, scope iop_scrc_in, type r */ +typedef unsigned int reg_iop_scrc_in_r_computed_crc; +#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 + +/* Register rw_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_crc 24 +#define REG_WR_ADDR_iop_scrc_in_rw_crc 24 + +/* Register rw_correct_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_correct_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 +#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 + +/* Register rw_wr1bit, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int data : 2; + unsigned int last : 2; + unsigned int dummy1 : 28; +} reg_iop_scrc_in_rw_wr1bit; +#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 +#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 + + +/* Constants */ +enum { + regk_iop_scrc_in_dif_in = 0x00000002, + regk_iop_scrc_in_hi = 0x00000000, + regk_iop_scrc_in_neg = 0x00000002, + regk_iop_scrc_in_no = 0x00000000, + regk_iop_scrc_in_pos = 0x00000001, + regk_iop_scrc_in_pos_neg = 0x00000003, + regk_iop_scrc_in_r_computed_crc_default = 0x00000000, + regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, + regk_iop_scrc_in_rw_cfg_default = 0x00000000, + regk_iop_scrc_in_rw_ctrl_default = 0x00000000, + regk_iop_scrc_in_rw_init_crc_default = 0x00000000, + regk_iop_scrc_in_set0 = 0x00000000, + regk_iop_scrc_in_set1 = 0x00000001, + regk_iop_scrc_in_yes = 0x00000001 +}; +#endif /* __iop_scrc_in_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h new file mode 100644 index 000000000000..fd1d6ea1d484 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h @@ -0,0 +1,146 @@ +#ifndef __iop_scrc_out_defs_h +#define __iop_scrc_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_out.r + * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r + * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_scrc_out */ + +/* Register rw_cfg, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int trig : 2; + unsigned int inv_crc : 1; + unsigned int dummy1 : 29; +} reg_iop_scrc_out_rw_cfg; +#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 +#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int strb_src : 1; + unsigned int out_src : 1; + unsigned int dummy1 : 30; +} reg_iop_scrc_out_rw_ctrl; +#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 + +/* Register rw_init_crc, scope iop_scrc_out, type rw */ +typedef unsigned int reg_iop_scrc_out_rw_init_crc; +#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 +#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 + +/* Register rw_crc, scope iop_scrc_out, type rw */ +typedef unsigned int reg_iop_scrc_out_rw_crc; +#define REG_RD_ADDR_iop_scrc_out_rw_crc 12 +#define REG_WR_ADDR_iop_scrc_out_rw_crc 12 + +/* Register rw_data, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int val : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_out_rw_data; +#define REG_RD_ADDR_iop_scrc_out_rw_data 16 +#define REG_WR_ADDR_iop_scrc_out_rw_data 16 + +/* Register r_computed_crc, scope iop_scrc_out, type r */ +typedef unsigned int reg_iop_scrc_out_r_computed_crc; +#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 + + +/* Constants */ +enum { + regk_iop_scrc_out_crc = 0x00000001, + regk_iop_scrc_out_data = 0x00000000, + regk_iop_scrc_out_dif = 0x00000001, + regk_iop_scrc_out_hi = 0x00000000, + regk_iop_scrc_out_neg = 0x00000002, + regk_iop_scrc_out_no = 0x00000000, + regk_iop_scrc_out_pos = 0x00000001, + regk_iop_scrc_out_pos_neg = 0x00000003, + regk_iop_scrc_out_reg = 0x00000000, + regk_iop_scrc_out_rw_cfg_default = 0x00000000, + regk_iop_scrc_out_rw_crc_default = 0x00000000, + regk_iop_scrc_out_rw_ctrl_default = 0x00000000, + regk_iop_scrc_out_rw_data_default = 0x00000000, + regk_iop_scrc_out_rw_init_crc_default = 0x00000000, + regk_iop_scrc_out_yes = 0x00000001 +}; +#endif /* __iop_scrc_out_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h new file mode 100644 index 000000000000..0fda26e2f06f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h @@ -0,0 +1,453 @@ +#ifndef __iop_spu_defs_h +#define __iop_spu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_spu.r + * id: <not found> + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r + * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_spu */ + +#define STRIDE_iop_spu_rw_r 4 +/* Register rw_r, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_r; +#define REG_RD_ADDR_iop_spu_rw_r 0 +#define REG_WR_ADDR_iop_spu_rw_r 0 + +/* Register rw_seq_pc, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_seq_pc; +#define REG_RD_ADDR_iop_spu_rw_seq_pc 64 +#define REG_WR_ADDR_iop_spu_rw_seq_pc 64 + +/* Register rw_fsm_pc, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_fsm_pc; +#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 +#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 + +/* Register rw_ctrl, scope iop_spu, type rw */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_iop_spu_rw_ctrl; +#define REG_RD_ADDR_iop_spu_rw_ctrl 72 +#define REG_WR_ADDR_iop_spu_rw_ctrl 72 + +/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ +typedef struct { + unsigned int val0 : 5; + unsigned int src0 : 3; + unsigned int val1 : 5; + unsigned int src1 : 3; + unsigned int val2 : 5; + unsigned int src2 : 3; + unsigned int val3 : 5; + unsigned int src3 : 3; +} reg_iop_spu_rw_fsm_inputs3_0; +#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 +#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 + +/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ +typedef struct { + unsigned int val4 : 5; + unsigned int src4 : 3; + unsigned int val5 : 5; + unsigned int src5 : 3; + unsigned int val6 : 5; + unsigned int src6 : 3; + unsigned int val7 : 5; + unsigned int src7 : 3; +} reg_iop_spu_rw_fsm_inputs7_4; +#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 +#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 + +/* Register rw_gio_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out; +#define REG_RD_ADDR_iop_spu_rw_gio_out 84 +#define REG_WR_ADDR_iop_spu_rw_gio_out 84 + +/* Register rw_bus0_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_bus0_out; +#define REG_RD_ADDR_iop_spu_rw_bus0_out 88 +#define REG_WR_ADDR_iop_spu_rw_bus0_out 88 + +/* Register rw_bus1_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_bus1_out; +#define REG_RD_ADDR_iop_spu_rw_bus1_out 92 +#define REG_WR_ADDR_iop_spu_rw_bus1_out 92 + +/* Register r_gio_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_gio_in; +#define REG_RD_ADDR_iop_spu_r_gio_in 96 + +/* Register r_bus0_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_bus0_in; +#define REG_RD_ADDR_iop_spu_r_bus0_in 100 + +/* Register r_bus1_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_bus1_in; +#define REG_RD_ADDR_iop_spu_r_bus1_in 104 + +/* Register rw_gio_out_set, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out_set; +#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 +#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 + +/* Register rw_gio_out_clr, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out_clr; +#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 +#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 + +/* Register rs_wr_stat, scope iop_spu, type rs */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_spu_rs_wr_stat; +#define REG_RD_ADDR_iop_spu_rs_wr_stat 116 + +/* Register r_wr_stat, scope iop_spu, type r */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_spu_r_wr_stat; +#define REG_RD_ADDR_iop_spu_r_wr_stat 120 + +/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; +#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 + +/* Register r_stat_in, scope iop_spu, type r */ +typedef struct { + unsigned int timer_grp_lo : 4; + unsigned int fifo_out_last : 1; + unsigned int fifo_out_rdy : 1; + unsigned int fifo_out_all : 1; + unsigned int fifo_in_rdy : 1; + unsigned int dmc_out_all : 1; + unsigned int dmc_out_dth : 1; + unsigned int dmc_out_eop : 1; + unsigned int dmc_out_dv : 1; + unsigned int dmc_out_last : 1; + unsigned int dmc_out_cmd_rq : 1; + unsigned int dmc_out_cmd_rdy : 1; + unsigned int pcrc_correct : 1; + unsigned int timer_grp_hi : 4; + unsigned int dmc_in_sth : 1; + unsigned int dmc_in_full : 1; + unsigned int dmc_in_cmd_rdy : 1; + unsigned int spu_gio_out : 4; + unsigned int sync_clk12 : 1; + unsigned int scrc_out_data : 1; + unsigned int scrc_in_err : 1; + unsigned int mc_busy : 1; + unsigned int mc_owned : 1; +} reg_iop_spu_r_stat_in; +#define REG_RD_ADDR_iop_spu_r_stat_in 128 + +/* Register r_trigger_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_trigger_in; +#define REG_RD_ADDR_iop_spu_r_trigger_in 132 + +/* Register r_special_stat, scope iop_spu, type r */ +typedef struct { + unsigned int c_flag : 1; + unsigned int v_flag : 1; + unsigned int z_flag : 1; + unsigned int n_flag : 1; + unsigned int xor_bus0_r2_0 : 1; + unsigned int xor_bus1_r3_0 : 1; + unsigned int xor_bus0m_r2_0 : 1; + unsigned int xor_bus1m_r3_0 : 1; + unsigned int fsm_in0 : 1; + unsigned int fsm_in1 : 1; + unsigned int fsm_in2 : 1; + unsigned int fsm_in3 : 1; + unsigned int fsm_in4 : 1; + unsigned int fsm_in5 : 1; + unsigned int fsm_in6 : 1; + unsigned int fsm_in7 : 1; + unsigned int event0 : 1; + unsigned int event1 : 1; + unsigned int event2 : 1; + unsigned int event3 : 1; + unsigned int dummy1 : 12; +} reg_iop_spu_r_special_stat; +#define REG_RD_ADDR_iop_spu_r_special_stat 136 + +/* Register rw_reg_access, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 13; + unsigned int dummy1 : 3; + unsigned int imm_hi : 16; +} reg_iop_spu_rw_reg_access; +#define REG_RD_ADDR_iop_spu_rw_reg_access 140 +#define REG_WR_ADDR_iop_spu_rw_reg_access 140 + +#define STRIDE_iop_spu_rw_event_cfg 4 +/* Register rw_event_cfg, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int src : 2; + unsigned int eq_en : 1; + unsigned int eq_inv : 1; + unsigned int gt_en : 1; + unsigned int gt_inv : 1; + unsigned int dummy1 : 14; +} reg_iop_spu_rw_event_cfg; +#define REG_RD_ADDR_iop_spu_rw_event_cfg 144 +#define REG_WR_ADDR_iop_spu_rw_event_cfg 144 + +#define STRIDE_iop_spu_rw_event_mask 4 +/* Register rw_event_mask, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_event_mask; +#define REG_RD_ADDR_iop_spu_rw_event_mask 160 +#define REG_WR_ADDR_iop_spu_rw_event_mask 160 + +#define STRIDE_iop_spu_rw_event_val 4 +/* Register rw_event_val, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_event_val; +#define REG_RD_ADDR_iop_spu_rw_event_val 176 +#define REG_WR_ADDR_iop_spu_rw_event_val 176 + +/* Register rw_event_ret, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_event_ret; +#define REG_RD_ADDR_iop_spu_rw_event_ret 192 +#define REG_WR_ADDR_iop_spu_rw_event_ret 192 + +/* Register r_trace, scope iop_spu, type r */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int c_flag : 1; + unsigned int v_flag : 1; + unsigned int z_flag : 1; + unsigned int n_flag : 1; + unsigned int seq_addr : 12; + unsigned int dummy1 : 2; + unsigned int fsm_addr : 12; +} reg_iop_spu_r_trace; +#define REG_RD_ADDR_iop_spu_r_trace 196 + +/* Register r_fsm_trace, scope iop_spu, type r */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int tmr_done : 1; + unsigned int inp0 : 1; + unsigned int inp1 : 1; + unsigned int inp2 : 1; + unsigned int inp3 : 1; + unsigned int event0 : 1; + unsigned int event1 : 1; + unsigned int event2 : 1; + unsigned int event3 : 1; + unsigned int gio_out : 8; + unsigned int dummy1 : 1; + unsigned int fsm_addr : 12; +} reg_iop_spu_r_fsm_trace; +#define REG_RD_ADDR_iop_spu_r_fsm_trace 200 + +#define STRIDE_iop_spu_rw_brp 4 +/* Register rw_brp, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int dummy1 : 18; +} reg_iop_spu_rw_brp; +#define REG_RD_ADDR_iop_spu_rw_brp 204 +#define REG_WR_ADDR_iop_spu_rw_brp 204 + + +/* Constants */ +enum { + regk_iop_spu_attn_hi = 0x00000005, + regk_iop_spu_attn_lo = 0x00000005, + regk_iop_spu_attn_r0 = 0x00000000, + regk_iop_spu_attn_r1 = 0x00000001, + regk_iop_spu_attn_r10 = 0x00000002, + regk_iop_spu_attn_r11 = 0x00000003, + regk_iop_spu_attn_r12 = 0x00000004, + regk_iop_spu_attn_r13 = 0x00000005, + regk_iop_spu_attn_r14 = 0x00000006, + regk_iop_spu_attn_r15 = 0x00000007, + regk_iop_spu_attn_r2 = 0x00000002, + regk_iop_spu_attn_r3 = 0x00000003, + regk_iop_spu_attn_r4 = 0x00000004, + regk_iop_spu_attn_r5 = 0x00000005, + regk_iop_spu_attn_r6 = 0x00000006, + regk_iop_spu_attn_r7 = 0x00000007, + regk_iop_spu_attn_r8 = 0x00000000, + regk_iop_spu_attn_r9 = 0x00000001, + regk_iop_spu_c = 0x00000000, + regk_iop_spu_flag = 0x00000002, + regk_iop_spu_gio_in = 0x00000000, + regk_iop_spu_gio_out = 0x00000005, + regk_iop_spu_gio_out0 = 0x00000008, + regk_iop_spu_gio_out1 = 0x00000009, + regk_iop_spu_gio_out2 = 0x0000000a, + regk_iop_spu_gio_out3 = 0x0000000b, + regk_iop_spu_gio_out4 = 0x0000000c, + regk_iop_spu_gio_out5 = 0x0000000d, + regk_iop_spu_gio_out6 = 0x0000000e, + regk_iop_spu_gio_out7 = 0x0000000f, + regk_iop_spu_n = 0x00000003, + regk_iop_spu_no = 0x00000000, + regk_iop_spu_r0 = 0x00000008, + regk_iop_spu_r1 = 0x00000009, + regk_iop_spu_r10 = 0x0000000a, + regk_iop_spu_r11 = 0x0000000b, + regk_iop_spu_r12 = 0x0000000c, + regk_iop_spu_r13 = 0x0000000d, + regk_iop_spu_r14 = 0x0000000e, + regk_iop_spu_r15 = 0x0000000f, + regk_iop_spu_r2 = 0x0000000a, + regk_iop_spu_r3 = 0x0000000b, + regk_iop_spu_r4 = 0x0000000c, + regk_iop_spu_r5 = 0x0000000d, + regk_iop_spu_r6 = 0x0000000e, + regk_iop_spu_r7 = 0x0000000f, + regk_iop_spu_r8 = 0x00000008, + regk_iop_spu_r9 = 0x00000009, + regk_iop_spu_reg_hi = 0x00000002, + regk_iop_spu_reg_lo = 0x00000002, + regk_iop_spu_rw_brp_default = 0x00000000, + regk_iop_spu_rw_brp_size = 0x00000004, + regk_iop_spu_rw_ctrl_default = 0x00000000, + regk_iop_spu_rw_event_cfg_size = 0x00000004, + regk_iop_spu_rw_event_mask_size = 0x00000004, + regk_iop_spu_rw_event_val_size = 0x00000004, + regk_iop_spu_rw_gio_out_default = 0x00000000, + regk_iop_spu_rw_r_size = 0x00000010, + regk_iop_spu_rw_reg_access_default = 0x00000000, + regk_iop_spu_stat_in = 0x00000002, + regk_iop_spu_statin_hi = 0x00000004, + regk_iop_spu_statin_lo = 0x00000004, + regk_iop_spu_trig = 0x00000003, + regk_iop_spu_trigger = 0x00000006, + regk_iop_spu_v = 0x00000001, + regk_iop_spu_wsts_gioout_spec = 0x00000001, + regk_iop_spu_xor = 0x00000003, + regk_iop_spu_xor_bus0_r2_0 = 0x00000000, + regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, + regk_iop_spu_xor_bus1_r3_0 = 0x00000001, + regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, + regk_iop_spu_yes = 0x00000001, + regk_iop_spu_z = 0x00000002 +}; +#endif /* __iop_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 000000000000..d7b6d75884d2 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h @@ -0,0 +1,1042 @@ +#ifndef __iop_sw_cfg_defs_h +#define __iop_sw_cfg_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cfg */ + +/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 + +/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 + +/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 + +/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 + +/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 + +/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 + +/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 + +/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 + +/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 + +/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 + +/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 + +/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 + +/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 + +/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 + +/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 + +/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 + +/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 + +/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 + +/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 + +/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 + +/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 + +/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp4_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp5_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp6_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp7_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 + +/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus0_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 + +/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus0_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 + +/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus1_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 + +/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus1_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_byte0 : 2; + unsigned int bus0_byte1 : 2; + unsigned int bus0_byte2 : 2; + unsigned int bus0_byte3 : 2; + unsigned int bus1_byte0 : 2; + unsigned int bus1_byte1 : 2; + unsigned int bus1_byte2 : 2; + unsigned int bus1_byte3 : 2; + unsigned int gio3_0 : 2; + unsigned int gio7_4 : 2; + unsigned int gio11_8 : 2; + unsigned int gio15_12 : 2; + unsigned int gio19_16 : 2; + unsigned int gio23_20 : 2; + unsigned int gio27_24 : 2; + unsigned int gio31_28 : 2; +} reg_iop_sw_cfg_rw_pinmapping; +#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 +#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_lo : 3; + unsigned int bus0_hi : 3; + unsigned int bus0_lo_oe : 3; + unsigned int bus0_hi_oe : 3; + unsigned int bus1_lo : 3; + unsigned int bus1_hi : 3; + unsigned int bus1_lo_oe : 3; + unsigned int bus1_hi_oe : 3; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_bus_out_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio0 : 4; + unsigned int gio0_oe : 2; + unsigned int gio1 : 4; + unsigned int gio1_oe : 2; + unsigned int gio2 : 4; + unsigned int gio2_oe : 2; + unsigned int gio3 : 4; + unsigned int gio3_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio4 : 4; + unsigned int gio4_oe : 2; + unsigned int gio5 : 4; + unsigned int gio5_oe : 2; + unsigned int gio6 : 4; + unsigned int gio6_oe : 2; + unsigned int gio7 : 4; + unsigned int gio7_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio8 : 4; + unsigned int gio8_oe : 2; + unsigned int gio9 : 4; + unsigned int gio9_oe : 2; + unsigned int gio10 : 4; + unsigned int gio10_oe : 2; + unsigned int gio11 : 4; + unsigned int gio11_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio12 : 4; + unsigned int gio12_oe : 2; + unsigned int gio13 : 4; + unsigned int gio13_oe : 2; + unsigned int gio14 : 4; + unsigned int gio14_oe : 2; + unsigned int gio15 : 4; + unsigned int gio15_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio16 : 4; + unsigned int gio16_oe : 2; + unsigned int gio17 : 4; + unsigned int gio17_oe : 2; + unsigned int gio18 : 4; + unsigned int gio18_oe : 2; + unsigned int gio19 : 4; + unsigned int gio19_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio20 : 4; + unsigned int gio20_oe : 2; + unsigned int gio21 : 4; + unsigned int gio21_oe : 2; + unsigned int gio22 : 4; + unsigned int gio22_oe : 2; + unsigned int gio23 : 4; + unsigned int gio23_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio24 : 4; + unsigned int gio24_oe : 2; + unsigned int gio25 : 4; + unsigned int gio25_oe : 2; + unsigned int gio26 : 4; + unsigned int gio26_oe : 2; + unsigned int gio27 : 4; + unsigned int gio27_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio28 : 4; + unsigned int gio28_oe : 2; + unsigned int gio29 : 4; + unsigned int gio29_oe : 2; + unsigned int gio30 : 4; + unsigned int gio30_oe : 2; + unsigned int gio31 : 4; + unsigned int gio31_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 + +/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 2; + unsigned int bus1_in : 2; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_spu0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 + +/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 2; + unsigned int bus1_in : 2; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_spu1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 + +/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 + +/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int grp0_dis : 1; + unsigned int grp0_en : 1; + unsigned int grp1_dis : 1; + unsigned int grp1_en : 1; + unsigned int grp2_dis : 1; + unsigned int grp2_en : 1; + unsigned int grp3_dis : 1; + unsigned int grp3_en : 1; + unsigned int grp4_dis : 1; + unsigned int grp4_en : 1; + unsigned int grp5_dis : 1; + unsigned int grp5_en : 1; + unsigned int grp6_dis : 1; + unsigned int grp6_en : 1; + unsigned int grp7_dis : 1; + unsigned int grp7_en : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_trigger_grps_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 + +/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int dmc0_usr : 1; + unsigned int out_strb : 5; + unsigned int in_src : 3; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int out_src : 1; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_pdp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 + +/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int dmc1_usr : 1; + unsigned int out_strb : 5; + unsigned int in_src : 3; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int out_src : 1; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_pdp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int sdp_out0_strb : 3; + unsigned int sdp_out1_strb : 3; + unsigned int sdp_in0_data : 3; + unsigned int sdp_in0_last : 2; + unsigned int sdp_in0_strb : 3; + unsigned int sdp_in1_data : 3; + unsigned int sdp_in1_last : 2; + unsigned int sdp_in1_strb : 3; + unsigned int dummy1 : 10; +} reg_iop_sw_cfg_rw_sdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 +#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 + + +/* Constants */ +enum { + regk_iop_sw_cfg_a = 0x00000001, + regk_iop_sw_cfg_b = 0x00000002, + regk_iop_sw_cfg_bus0 = 0x00000000, + regk_iop_sw_cfg_bus0_rot16 = 0x00000004, + regk_iop_sw_cfg_bus0_rot24 = 0x00000006, + regk_iop_sw_cfg_bus0_rot8 = 0x00000002, + regk_iop_sw_cfg_bus1 = 0x00000001, + regk_iop_sw_cfg_bus1_rot16 = 0x00000005, + regk_iop_sw_cfg_bus1_rot24 = 0x00000007, + regk_iop_sw_cfg_bus1_rot8 = 0x00000003, + regk_iop_sw_cfg_clk12 = 0x00000000, + regk_iop_sw_cfg_cpu = 0x00000000, + regk_iop_sw_cfg_dmc0 = 0x00000000, + regk_iop_sw_cfg_dmc1 = 0x00000001, + regk_iop_sw_cfg_gated_clk0 = 0x00000010, + regk_iop_sw_cfg_gated_clk1 = 0x00000011, + regk_iop_sw_cfg_gated_clk2 = 0x00000012, + regk_iop_sw_cfg_gated_clk3 = 0x00000013, + regk_iop_sw_cfg_gio0 = 0x00000004, + regk_iop_sw_cfg_gio1 = 0x00000001, + regk_iop_sw_cfg_gio2 = 0x00000005, + regk_iop_sw_cfg_gio3 = 0x00000002, + regk_iop_sw_cfg_gio4 = 0x00000006, + regk_iop_sw_cfg_gio5 = 0x00000003, + regk_iop_sw_cfg_gio6 = 0x00000007, + regk_iop_sw_cfg_gio7 = 0x00000004, + regk_iop_sw_cfg_gio_in0 = 0x00000000, + regk_iop_sw_cfg_gio_in1 = 0x00000001, + regk_iop_sw_cfg_gio_in10 = 0x00000002, + regk_iop_sw_cfg_gio_in11 = 0x00000003, + regk_iop_sw_cfg_gio_in14 = 0x00000004, + regk_iop_sw_cfg_gio_in15 = 0x00000005, + regk_iop_sw_cfg_gio_in18 = 0x00000002, + regk_iop_sw_cfg_gio_in19 = 0x00000003, + regk_iop_sw_cfg_gio_in20 = 0x00000004, + regk_iop_sw_cfg_gio_in21 = 0x00000005, + regk_iop_sw_cfg_gio_in26 = 0x00000006, + regk_iop_sw_cfg_gio_in27 = 0x00000007, + regk_iop_sw_cfg_gio_in28 = 0x00000006, + regk_iop_sw_cfg_gio_in29 = 0x00000007, + regk_iop_sw_cfg_gio_in4 = 0x00000000, + regk_iop_sw_cfg_gio_in5 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, + regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, + regk_iop_sw_cfg_mpu = 0x00000001, + regk_iop_sw_cfg_none = 0x00000000, + regk_iop_sw_cfg_par0 = 0x00000000, + regk_iop_sw_cfg_par1 = 0x00000001, + regk_iop_sw_cfg_pdp_out0 = 0x00000002, + regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, + regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, + regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, + regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, + regk_iop_sw_cfg_pdp_out1 = 0x00000003, + regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, + regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, + regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, + regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, + regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, + regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, + regk_iop_sw_cfg_sdp_out0 = 0x00000008, + regk_iop_sw_cfg_sdp_out1 = 0x00000009, + regk_iop_sw_cfg_size16 = 0x00000002, + regk_iop_sw_cfg_size24 = 0x00000003, + regk_iop_sw_cfg_size32 = 0x00000004, + regk_iop_sw_cfg_size8 = 0x00000001, + regk_iop_sw_cfg_spu0 = 0x00000002, + regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, + regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, + regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, + regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, + regk_iop_sw_cfg_spu0_g0 = 0x0000000e, + regk_iop_sw_cfg_spu0_g1 = 0x0000000e, + regk_iop_sw_cfg_spu0_g2 = 0x0000000e, + regk_iop_sw_cfg_spu0_g3 = 0x0000000e, + regk_iop_sw_cfg_spu0_g4 = 0x0000000e, + regk_iop_sw_cfg_spu0_g5 = 0x0000000e, + regk_iop_sw_cfg_spu0_g6 = 0x0000000e, + regk_iop_sw_cfg_spu0_g7 = 0x0000000e, + regk_iop_sw_cfg_spu0_gio0 = 0x00000000, + regk_iop_sw_cfg_spu0_gio1 = 0x00000001, + regk_iop_sw_cfg_spu0_gio2 = 0x00000000, + regk_iop_sw_cfg_spu0_gio5 = 0x00000005, + regk_iop_sw_cfg_spu0_gio6 = 0x00000006, + regk_iop_sw_cfg_spu0_gio7 = 0x00000007, + regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, + regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, + regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, + regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, + regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, + regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, + regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, + regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, + regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, + regk_iop_sw_cfg_spu1 = 0x00000003, + regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, + regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, + regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, + regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, + regk_iop_sw_cfg_spu1_g0 = 0x0000000f, + regk_iop_sw_cfg_spu1_g1 = 0x0000000f, + regk_iop_sw_cfg_spu1_g2 = 0x0000000f, + regk_iop_sw_cfg_spu1_g3 = 0x0000000f, + regk_iop_sw_cfg_spu1_g4 = 0x0000000f, + regk_iop_sw_cfg_spu1_g5 = 0x0000000f, + regk_iop_sw_cfg_spu1_g6 = 0x0000000f, + regk_iop_sw_cfg_spu1_g7 = 0x0000000f, + regk_iop_sw_cfg_spu1_gio0 = 0x00000002, + regk_iop_sw_cfg_spu1_gio1 = 0x00000003, + regk_iop_sw_cfg_spu1_gio2 = 0x00000002, + regk_iop_sw_cfg_spu1_gio5 = 0x00000005, + regk_iop_sw_cfg_spu1_gio6 = 0x00000006, + regk_iop_sw_cfg_spu1_gio7 = 0x00000007, + regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, + regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, + regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, + regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, + regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, + regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, + regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, + regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, + regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, + regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, + regk_iop_sw_cfg_timer_grp0 = 0x00000000, + regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, + regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, + regk_iop_sw_cfg_timer_grp1 = 0x00000000, + regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, + regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, + regk_iop_sw_cfg_timer_grp2 = 0x00000000, + regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, + regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, + regk_iop_sw_cfg_timer_grp3 = 0x00000000, + regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, + regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, + regk_iop_sw_cfg_trig0_0 = 0x00000000, + regk_iop_sw_cfg_trig0_1 = 0x00000000, + regk_iop_sw_cfg_trig0_2 = 0x00000000, + regk_iop_sw_cfg_trig0_3 = 0x00000000, + regk_iop_sw_cfg_trig1_0 = 0x00000000, + regk_iop_sw_cfg_trig1_1 = 0x00000000, + regk_iop_sw_cfg_trig1_2 = 0x00000000, + regk_iop_sw_cfg_trig1_3 = 0x00000000, + regk_iop_sw_cfg_trig2_0 = 0x00000000, + regk_iop_sw_cfg_trig2_1 = 0x00000000, + regk_iop_sw_cfg_trig2_2 = 0x00000000, + regk_iop_sw_cfg_trig2_3 = 0x00000000, + regk_iop_sw_cfg_trig3_0 = 0x00000000, + regk_iop_sw_cfg_trig3_1 = 0x00000000, + regk_iop_sw_cfg_trig3_2 = 0x00000000, + regk_iop_sw_cfg_trig3_3 = 0x00000000, + regk_iop_sw_cfg_trig4_0 = 0x00000001, + regk_iop_sw_cfg_trig4_1 = 0x00000001, + regk_iop_sw_cfg_trig4_2 = 0x00000001, + regk_iop_sw_cfg_trig4_3 = 0x00000001, + regk_iop_sw_cfg_trig5_0 = 0x00000001, + regk_iop_sw_cfg_trig5_1 = 0x00000001, + regk_iop_sw_cfg_trig5_2 = 0x00000001, + regk_iop_sw_cfg_trig5_3 = 0x00000001, + regk_iop_sw_cfg_trig6_0 = 0x00000001, + regk_iop_sw_cfg_trig6_1 = 0x00000001, + regk_iop_sw_cfg_trig6_2 = 0x00000001, + regk_iop_sw_cfg_trig6_3 = 0x00000001, + regk_iop_sw_cfg_trig7_0 = 0x00000001, + regk_iop_sw_cfg_trig7_1 = 0x00000001, + regk_iop_sw_cfg_trig7_2 = 0x00000001, + regk_iop_sw_cfg_trig7_3 = 0x00000001 +}; +#endif /* __iop_sw_cfg_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 000000000000..5fed844b19e2 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h @@ -0,0 +1,853 @@ +#ifndef __iop_sw_cpu_defs_h +#define __iop_sw_cpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cpu */ + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_cpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +typedef unsigned int reg_iop_sw_cpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_cpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 + +/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 + +/* Register r_bus0_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 + +/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 + +/* Register r_bus1_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_rw_intr0_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_rw_ack_intr0; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_r_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_r_masked_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_rw_intr1_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_rw_ack_intr1; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_r_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_r_masked_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 + +/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_rw_intr2_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 + +/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr2; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 + +/* Register r_intr2, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_intr2; +#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 + +/* Register r_masked_intr2, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_masked_intr2; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 + +/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_rw_intr3_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 + +/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr3; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 + +/* Register r_intr3, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_r_intr3; +#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 + +/* Register r_masked_intr3, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_r_masked_intr3; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 + + +/* Constants */ +enum { + regk_iop_sw_cpu_copy = 0x00000000, + regk_iop_sw_cpu_no = 0x00000000, + regk_iop_sw_cpu_rd = 0x00000002, + regk_iop_sw_cpu_reg_copy = 0x00000001, + regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, + regk_iop_sw_cpu_wr = 0x00000003, + regk_iop_sw_cpu_yes = 0x00000001 +}; +#endif /* __iop_sw_cpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 000000000000..da718f2a8cad --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h @@ -0,0 +1,893 @@ +#ifndef __iop_sw_mpu_defs_h +#define __iop_sw_mpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_mpu */ + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_mpu_rw_sw_cfg_owner; +#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 +#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_mpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +typedef unsigned int reg_iop_sw_mpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_mpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 + +/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 + +/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 + +/* Register r_bus0_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 + +/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 + +/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 + +/* Register r_bus1_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 +#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp0_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp1_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp2_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp3_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 + + +/* Constants */ +enum { + regk_iop_sw_mpu_copy = 0x00000000, + regk_iop_sw_mpu_cpu = 0x00000000, + regk_iop_sw_mpu_mpu = 0x00000001, + regk_iop_sw_mpu_no = 0x00000000, + regk_iop_sw_mpu_nop = 0x00000000, + regk_iop_sw_mpu_rd = 0x00000002, + regk_iop_sw_mpu_reg_copy = 0x00000001, + regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, + regk_iop_sw_mpu_set = 0x00000001, + regk_iop_sw_mpu_spu0 = 0x00000002, + regk_iop_sw_mpu_spu1 = 0x00000003, + regk_iop_sw_mpu_wr = 0x00000003, + regk_iop_sw_mpu_yes = 0x00000001 +}; +#endif /* __iop_sw_mpu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 000000000000..b59dde4bd0d1 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h @@ -0,0 +1,552 @@ +#ifndef __iop_sw_spu_defs_h +#define __iop_sw_spu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: <not found> + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_spu */ + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_spu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +typedef unsigned int reg_iop_sw_spu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +typedef unsigned int reg_iop_sw_spu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mc_data; +#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_spu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 + +/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 + +/* Register r_bus0_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 + +/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 + +/* Register r_bus1_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_gio_in; +#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 + +/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 + +/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 + +/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 + +/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 + +/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 + +/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 + +/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 + +/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 +#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out1 : 1; + unsigned int dmc_in1 : 1; + unsigned int dummy1 : 8; +} reg_iop_sw_spu_r_hw_intr; +#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 +#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int other_spu_intr0 : 1; + unsigned int other_spu_intr1 : 1; + unsigned int other_spu_intr2 : 1; + unsigned int other_spu_intr3 : 1; + unsigned int other_spu_intr4 : 1; + unsigned int other_spu_intr5 : 1; + unsigned int other_spu_intr6 : 1; + unsigned int other_spu_intr7 : 1; + unsigned int other_spu_intr8 : 1; + unsigned int other_spu_intr9 : 1; + unsigned int other_spu_intr10 : 1; + unsigned int other_spu_intr11 : 1; + unsigned int other_spu_intr12 : 1; + unsigned int other_spu_intr13 : 1; + unsigned int other_spu_intr14 : 1; + unsigned int other_spu_intr15 : 1; +} reg_iop_sw_spu_r_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 + + +/* Constants */ +enum { + regk_iop_sw_spu_copy = 0x00000000, + regk_iop_sw_spu_no = 0x00000000, + regk_iop_sw_spu_nop = 0x00000000, + regk_iop_sw_spu_rd = 0x00000002, + regk_iop_sw_spu_reg_copy = 0x00000001, + regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_spu_set = 0x00000001, + regk_iop_sw_spu_wr = 0x00000003, + regk_iop_sw_spu_yes = 0x00000001 +}; +#endif /* __iop_sw_spu_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h new file mode 100644 index 000000000000..c994114f3b51 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h @@ -0,0 +1,249 @@ +#ifndef __iop_timer_grp_defs_h +#define __iop_timer_grp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_timer_grp.r + * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r + * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_timer_grp */ + +/* Register rw_cfg, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int clk_src : 1; + unsigned int trig : 2; + unsigned int clk_gen_div : 8; + unsigned int clk_div : 8; + unsigned int dummy1 : 13; +} reg_iop_timer_grp_rw_cfg; +#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 +#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 + +/* Register rw_half_period, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int quota_lo : 15; + unsigned int quota_hi : 15; + unsigned int quota_hi_sel : 1; + unsigned int dummy1 : 1; +} reg_iop_timer_grp_rw_half_period; +#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 +#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 + +/* Register rw_half_period_len, scope iop_timer_grp, type rw */ +typedef unsigned int reg_iop_timer_grp_rw_half_period_len; +#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 +#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 + +#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 +/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int clk_src : 3; + unsigned int strb : 2; + unsigned int run_mode : 2; + unsigned int out_mode : 1; + unsigned int active_on_tmr : 2; + unsigned int inv : 1; + unsigned int en_by_tmr : 2; + unsigned int dis_by_tmr : 2; + unsigned int en_only_by_reg : 1; + unsigned int dis_only_by_reg : 1; + unsigned int rst_at_en_strb : 1; + unsigned int dummy1 : 14; +} reg_iop_timer_grp_rw_tmr_cfg; +#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 +#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 + +#define STRIDE_iop_timer_grp_rw_tmr_len 4 +/* Register rw_tmr_len, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rw_tmr_len; +#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 +#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 + +/* Register rw_cmd, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int rst : 4; + unsigned int en : 4; + unsigned int dis : 4; + unsigned int strb : 4; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rw_cmd; +#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 +#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 + +/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ +typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; +#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 + +#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 +/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rs_tmr_cnt; +#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 + +#define STRIDE_iop_timer_grp_r_tmr_cnt 8 +/* Register r_tmr_cnt, scope iop_timer_grp, type r */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_r_tmr_cnt; +#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 + +/* Register rw_intr_mask, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_rw_intr_mask; +#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 +#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 + +/* Register rw_ack_intr, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_rw_ack_intr; +#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 +#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 + +/* Register r_intr, scope iop_timer_grp, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_r_intr; +#define REG_RD_ADDR_iop_timer_grp_r_intr 108 + +/* Register r_masked_intr, scope iop_timer_grp, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_r_masked_intr; +#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 + + +/* Constants */ +enum { + regk_iop_timer_grp_clk200 = 0x00000000, + regk_iop_timer_grp_clk_gen = 0x00000002, + regk_iop_timer_grp_complete = 0x00000002, + regk_iop_timer_grp_div_clk200 = 0x00000001, + regk_iop_timer_grp_div_clk_gen = 0x00000003, + regk_iop_timer_grp_ext = 0x00000001, + regk_iop_timer_grp_hi = 0x00000000, + regk_iop_timer_grp_long_period = 0x00000001, + regk_iop_timer_grp_neg = 0x00000002, + regk_iop_timer_grp_no = 0x00000000, + regk_iop_timer_grp_once = 0x00000003, + regk_iop_timer_grp_pause = 0x00000001, + regk_iop_timer_grp_pos = 0x00000001, + regk_iop_timer_grp_pos_neg = 0x00000003, + regk_iop_timer_grp_pulse = 0x00000000, + regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, + regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, + regk_iop_timer_grp_rw_cfg_default = 0x00000002, + regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, + regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, + regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, + regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, + regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, + regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, + regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, + regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, + regk_iop_timer_grp_short_period = 0x00000000, + regk_iop_timer_grp_stop = 0x00000000, + regk_iop_timer_grp_tmr = 0x00000004, + regk_iop_timer_grp_toggle = 0x00000001, + regk_iop_timer_grp_yes = 0x00000001 +}; +#endif /* __iop_timer_grp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h new file mode 100644 index 000000000000..36e44282399d --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h @@ -0,0 +1,170 @@ +#ifndef __iop_trigger_grp_defs_h +#define __iop_trigger_grp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_trigger_grp */ + +#define STRIDE_iop_trigger_grp_rw_cfg 4 +/* Register rw_cfg, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int action : 2; + unsigned int once : 1; + unsigned int trig : 3; + unsigned int en_only_by_reg : 1; + unsigned int dis_only_by_reg : 1; + unsigned int dummy1 : 24; +} reg_iop_trigger_grp_rw_cfg; +#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 +#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 + +/* Register rw_cmd, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int dis : 4; + unsigned int en : 4; + unsigned int dummy1 : 24; +} reg_iop_trigger_grp_rw_cmd; +#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 +#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 + +/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_rw_intr_mask; +#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 +#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 + +/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_rw_ack_intr; +#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 +#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 + +/* Register r_intr, scope iop_trigger_grp, type r */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_r_intr; +#define REG_RD_ADDR_iop_trigger_grp_r_intr 28 + +/* Register r_masked_intr, scope iop_trigger_grp, type r */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_r_masked_intr; +#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 + + +/* Constants */ +enum { + regk_iop_trigger_grp_fall = 0x00000002, + regk_iop_trigger_grp_fall_lo = 0x00000006, + regk_iop_trigger_grp_no = 0x00000000, + regk_iop_trigger_grp_off = 0x00000000, + regk_iop_trigger_grp_pulse = 0x00000000, + regk_iop_trigger_grp_rise = 0x00000001, + regk_iop_trigger_grp_rise_fall = 0x00000003, + regk_iop_trigger_grp_rise_fall_hi = 0x00000007, + regk_iop_trigger_grp_rise_fall_lo = 0x00000004, + regk_iop_trigger_grp_rise_hi = 0x00000005, + regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, + regk_iop_trigger_grp_rw_cfg_size = 0x00000004, + regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, + regk_iop_trigger_grp_toggle = 0x00000003, + regk_iop_trigger_grp_yes = 0x00000001 +}; +#endif /* __iop_trigger_grp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h new file mode 100644 index 000000000000..b8d6a910c71c --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h @@ -0,0 +1,99 @@ +#ifndef __iop_version_defs_h +#define __iop_version_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_version.r + * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp + * last modfied: Mon Apr 11 16:08:44 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r + * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_version */ + +/* Register r_version, scope iop_version, type r */ +typedef struct { + unsigned int nr : 8; + unsigned int dummy1 : 24; +} reg_iop_version_r_version; +#define REG_RD_ADDR_iop_version_r_version 0 + + +/* Constants */ +enum { + regk_iop_version_v1_0 = 0x00000001 +}; +#endif /* __iop_version_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h new file mode 100644 index 000000000000..7b167e3c0572 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h @@ -0,0 +1,104 @@ +#ifndef __irq_nmi_defs_h +#define __irq_nmi_defs_h + +/* + * This file is autogenerated from + * file: ../../mod/irq_nmi.r + * id: <not found> + * last modfied: Thu Jan 22 09:22:43 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r + * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope irq_nmi */ + +/* Register rw_cmd, scope irq_nmi, type rw */ +typedef struct { + unsigned int delay : 16; + unsigned int op : 2; + unsigned int dummy1 : 14; +} reg_irq_nmi_rw_cmd; +#define REG_RD_ADDR_irq_nmi_rw_cmd 0 +#define REG_WR_ADDR_irq_nmi_rw_cmd 0 + + +/* Constants */ +enum { + regk_irq_nmi_ack_irq = 0x00000002, + regk_irq_nmi_ack_nmi = 0x00000003, + regk_irq_nmi_irq = 0x00000000, + regk_irq_nmi_nmi = 0x00000001 +}; +#endif /* __irq_nmi_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h new file mode 100644 index 000000000000..a11fdd3cd907 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h @@ -0,0 +1,205 @@ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Fri Nov 7 15:36:04 2003 + * + * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_break_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_addr; +#define REG_RD_ADDR_marb_bp_r_break_addr 20 + +/* Register r_break_op, scope marb_bp, type r */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_break_op; +#define REG_RD_ADDR_marb_bp_r_break_op 24 + +/* Register r_break_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_clients; +#define REG_RD_ADDR_marb_bp_r_break_clients 28 + +/* Register r_break_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_first_client; +#define REG_RD_ADDR_marb_bp_r_break_first_client 32 + +/* Register r_break_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_size; +#define REG_RD_ADDR_marb_bp_r_break_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h new file mode 100644 index 000000000000..71e8af0bb3a4 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/marb_defs.h @@ -0,0 +1,475 @@ +#ifndef __marb_defs_h +#define __marb_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb */ + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_int_slots; +#define REG_RD_ADDR_marb_rw_int_slots 0 +#define REG_WR_ADDR_marb_rw_int_slots 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_ext_slots; +#define REG_RD_ADDR_marb_rw_ext_slots 256 +#define REG_WR_ADDR_marb_rw_ext_slots 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_regs_slots; +#define REG_RD_ADDR_marb_rw_regs_slots 512 +#define REG_WR_ADDR_marb_rw_regs_slots 512 + +/* Register rw_intr_mask, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_intr_mask; +#define REG_RD_ADDR_marb_rw_intr_mask 528 +#define REG_WR_ADDR_marb_rw_intr_mask 528 + +/* Register rw_ack_intr, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_ack_intr; +#define REG_RD_ADDR_marb_rw_ack_intr 532 +#define REG_WR_ADDR_marb_rw_ack_intr 532 + +/* Register r_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_intr; +#define REG_RD_ADDR_marb_r_intr 536 + +/* Register r_masked_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_masked_intr; +#define REG_RD_ADDR_marb_r_masked_intr 540 + +/* Register rw_stop_mask, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_stop_mask; +#define REG_RD_ADDR_marb_rw_stop_mask 544 +#define REG_WR_ADDR_marb_rw_stop_mask 544 + +/* Register r_stopped, scope marb, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_r_stopped; +#define REG_RD_ADDR_marb_r_stopped 548 + +/* Register rw_no_snoop, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_no_snoop; +#define REG_RD_ADDR_marb_rw_no_snoop 832 +#define REG_WR_ADDR_marb_rw_no_snoop 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +typedef struct { + unsigned int dummy1 : 10; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 20; +} reg_marb_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 +#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 + + +/* Constants */ +enum { + regk_marb_cpud = 0x0000000b, + regk_marb_cpui = 0x0000000a, + regk_marb_dma0 = 0x00000000, + regk_marb_dma1 = 0x00000001, + regk_marb_dma2 = 0x00000002, + regk_marb_dma3 = 0x00000003, + regk_marb_dma4 = 0x00000004, + regk_marb_dma5 = 0x00000005, + regk_marb_dma6 = 0x00000006, + regk_marb_dma7 = 0x00000007, + regk_marb_dma8 = 0x00000008, + regk_marb_dma9 = 0x00000009, + regk_marb_iop = 0x0000000c, + regk_marb_no = 0x00000000, + regk_marb_r_stopped_default = 0x00000000, + regk_marb_rw_ext_slots_default = 0x00000000, + regk_marb_rw_ext_slots_size = 0x00000040, + regk_marb_rw_int_slots_default = 0x00000000, + regk_marb_rw_int_slots_size = 0x00000040, + regk_marb_rw_intr_mask_default = 0x00000000, + regk_marb_rw_no_snoop_default = 0x00000000, + regk_marb_rw_no_snoop_rq_default = 0x00000000, + regk_marb_rw_regs_slots_default = 0x00000000, + regk_marb_rw_regs_slots_size = 0x00000004, + regk_marb_rw_stop_mask_default = 0x00000000, + regk_marb_slave = 0x0000000d, + regk_marb_yes = 0x00000001 +}; +#endif /* __marb_defs_h */ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: <not found> + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_brk_op; +#define REG_RD_ADDR_marb_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_size; +#define REG_RD_ADDR_marb_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h new file mode 100644 index 000000000000..9d91c2de1b07 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h @@ -0,0 +1,357 @@ +#ifndef __pinmux_defs_h +#define __pinmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pinmux */ + +/* Register rw_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int csp2_n : 1; + unsigned int csp3_n : 1; + unsigned int csp5_n : 1; + unsigned int csp6_n : 1; + unsigned int hsh4 : 1; + unsigned int hsh5 : 1; + unsigned int hsh6 : 1; + unsigned int hsh7 : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_pa; +#define REG_RD_ADDR_pinmux_rw_pa 0 +#define REG_WR_ADDR_pinmux_rw_pa 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +typedef struct { + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ata0 : 1; + unsigned int ata1 : 1; + unsigned int ata2 : 1; + unsigned int ata3 : 1; + unsigned int ata : 1; + unsigned int eth1 : 1; + unsigned int eth1_mgm : 1; + unsigned int timer : 1; + unsigned int p21 : 1; + unsigned int dummy1 : 18; +} reg_pinmux_rw_hwprot; +#define REG_RD_ADDR_pinmux_rw_hwprot 4 +#define REG_WR_ADDR_pinmux_rw_hwprot 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_gio; +#define REG_RD_ADDR_pinmux_rw_pb_gio 8 +#define REG_WR_ADDR_pinmux_rw_pb_gio 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_iop; +#define REG_RD_ADDR_pinmux_rw_pb_iop 12 +#define REG_WR_ADDR_pinmux_rw_pb_iop 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_gio; +#define REG_RD_ADDR_pinmux_rw_pc_gio 16 +#define REG_WR_ADDR_pinmux_rw_pc_gio 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_iop; +#define REG_RD_ADDR_pinmux_rw_pc_iop 20 +#define REG_WR_ADDR_pinmux_rw_pc_iop 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_gio; +#define REG_RD_ADDR_pinmux_rw_pd_gio 24 +#define REG_WR_ADDR_pinmux_rw_pd_gio 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_iop; +#define REG_RD_ADDR_pinmux_rw_pd_iop 28 +#define REG_WR_ADDR_pinmux_rw_pd_iop 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_gio; +#define REG_RD_ADDR_pinmux_rw_pe_gio 32 +#define REG_WR_ADDR_pinmux_rw_pe_gio 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_iop; +#define REG_RD_ADDR_pinmux_rw_pe_iop 36 +#define REG_WR_ADDR_pinmux_rw_pe_iop 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +typedef struct { + unsigned int en_usb0 : 1; + unsigned int en_usb1 : 1; + unsigned int dummy1 : 30; +} reg_pinmux_rw_usb_phy; +#define REG_RD_ADDR_pinmux_rw_usb_phy 40 +#define REG_WR_ADDR_pinmux_rw_usb_phy 40 + + +/* Constants */ +enum { + regk_pinmux_no = 0x00000000, + regk_pinmux_rw_hwprot_default = 0x00000000, + regk_pinmux_rw_pa_default = 0x00000000, + regk_pinmux_rw_pb_gio_default = 0x00000000, + regk_pinmux_rw_pb_iop_default = 0x00000000, + regk_pinmux_rw_pc_gio_default = 0x00000000, + regk_pinmux_rw_pc_iop_default = 0x00000000, + regk_pinmux_rw_pd_gio_default = 0x00000000, + regk_pinmux_rw_pd_iop_default = 0x00000000, + regk_pinmux_rw_pe_gio_default = 0x00000000, + regk_pinmux_rw_pe_iop_default = 0x00000000, + regk_pinmux_rw_usb_phy_default = 0x00000000, + regk_pinmux_yes = 0x00000001 +}; +#endif /* __pinmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/reg_map.h b/include/asm-cris/arch-v32/hwregs/reg_map.h new file mode 100644 index 000000000000..e31502838ec6 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/reg_map.h @@ -0,0 +1,103 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: ../../mod/fakereg.rmap + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * last modified: Wed Feb 11 20:53:25 2004 + * file: ../../rtl/global.rmap + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * last modified: Mon Aug 18 17:08:23 2003 + * file: ../../mod/modreg.rmap + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * last modified: Fri Feb 20 16:40:04 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap + * id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +typedef enum { + regi_ata = 0xb0032000, + regi_bif_core = 0xb0014000, + regi_bif_dma = 0xb0016000, + regi_bif_slave = 0xb0018000, + regi_config = 0xb003c000, + regi_dma0 = 0xb0000000, + regi_dma1 = 0xb0002000, + regi_dma2 = 0xb0004000, + regi_dma3 = 0xb0006000, + regi_dma4 = 0xb0008000, + regi_dma5 = 0xb000a000, + regi_dma6 = 0xb000c000, + regi_dma7 = 0xb000e000, + regi_dma8 = 0xb0010000, + regi_dma9 = 0xb0012000, + regi_eth0 = 0xb0034000, + regi_eth1 = 0xb0036000, + regi_gio = 0xb001a000, + regi_iop = 0xb0020000, + regi_iop_version = 0xb0020000, + regi_iop_fifo_in0_extra = 0xb0020040, + regi_iop_fifo_in1_extra = 0xb0020080, + regi_iop_fifo_out0_extra = 0xb00200c0, + regi_iop_fifo_out1_extra = 0xb0020100, + regi_iop_trigger_grp0 = 0xb0020140, + regi_iop_trigger_grp1 = 0xb0020180, + regi_iop_trigger_grp2 = 0xb00201c0, + regi_iop_trigger_grp3 = 0xb0020200, + regi_iop_trigger_grp4 = 0xb0020240, + regi_iop_trigger_grp5 = 0xb0020280, + regi_iop_trigger_grp6 = 0xb00202c0, + regi_iop_trigger_grp7 = 0xb0020300, + regi_iop_crc_par0 = 0xb0020380, + regi_iop_crc_par1 = 0xb0020400, + regi_iop_dmc_in0 = 0xb0020480, + regi_iop_dmc_in1 = 0xb0020500, + regi_iop_dmc_out0 = 0xb0020580, + regi_iop_dmc_out1 = 0xb0020600, + regi_iop_fifo_in0 = 0xb0020680, + regi_iop_fifo_in1 = 0xb0020700, + regi_iop_fifo_out0 = 0xb0020780, + regi_iop_fifo_out1 = 0xb0020800, + regi_iop_scrc_in0 = 0xb0020880, + regi_iop_scrc_in1 = 0xb0020900, + regi_iop_scrc_out0 = 0xb0020980, + regi_iop_scrc_out1 = 0xb0020a00, + regi_iop_timer_grp0 = 0xb0020a80, + regi_iop_timer_grp1 = 0xb0020b00, + regi_iop_timer_grp2 = 0xb0020b80, + regi_iop_timer_grp3 = 0xb0020c00, + regi_iop_sap_in = 0xb0020d00, + regi_iop_sap_out = 0xb0020e00, + regi_iop_spu0 = 0xb0020f00, + regi_iop_spu1 = 0xb0021000, + regi_iop_sw_cfg = 0xb0021100, + regi_iop_sw_cpu = 0xb0021200, + regi_iop_sw_mpu = 0xb0021300, + regi_iop_sw_spu0 = 0xb0021400, + regi_iop_sw_spu1 = 0xb0021500, + regi_iop_mpu = 0xb0021600, + regi_irq = 0xb001c000, + regi_irq2 = 0xb005c000, + regi_marb = 0xb003e000, + regi_marb_bp0 = 0xb003e240, + regi_marb_bp1 = 0xb003e280, + regi_marb_bp2 = 0xb003e2c0, + regi_marb_bp3 = 0xb003e300, + regi_pinmux = 0xb0038000, + regi_ser0 = 0xb0026000, + regi_ser1 = 0xb0028000, + regi_ser2 = 0xb002a000, + regi_ser3 = 0xb002c000, + regi_sser0 = 0xb0022000, + regi_sser1 = 0xb0024000, + regi_strcop = 0xb0030000, + regi_strmux = 0xb003a000, + regi_timer = 0xb001e000, + regi_timer2 = 0xb005e000, + regi_trace = 0xb0040000, +} reg_scope_instances; +#endif /* __reg_map_h */ diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h new file mode 100644 index 000000000000..44e60233c68f --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h @@ -0,0 +1,15 @@ +/* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * + * Read/write register macros used by *_defs.h + */ + +#ifndef reg_rdwr_h +#define reg_rdwr_h + + +#define REG_READ(type, addr) *((volatile type *) (addr)) + +#define REG_WRITE(type, addr, val) \ + do { *((volatile type *) (addr)) = (val); } while(0) + +#endif diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h new file mode 100644 index 000000000000..d9f0e924fb23 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h @@ -0,0 +1,173 @@ +#ifndef __rt_trace_defs_h +#define __rt_trace_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/rt_trace/rtl/rt_regs.r + * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp + * last modfied: Mon Apr 11 16:09:14 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r + * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope rt_trace */ + +/* Register rw_cfg, scope rt_trace, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int mode : 1; + unsigned int owner : 1; + unsigned int wp : 1; + unsigned int stall : 1; + unsigned int dummy1 : 3; + unsigned int wp_start : 7; + unsigned int dummy2 : 1; + unsigned int wp_stop : 7; + unsigned int dummy3 : 9; +} reg_rt_trace_rw_cfg; +#define REG_RD_ADDR_rt_trace_rw_cfg 0 +#define REG_WR_ADDR_rt_trace_rw_cfg 0 + +/* Register rw_tap_ctrl, scope rt_trace, type rw */ +typedef struct { + unsigned int ack_data : 1; + unsigned int ack_guru : 1; + unsigned int dummy1 : 30; +} reg_rt_trace_rw_tap_ctrl; +#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 +#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 + +/* Register r_tap_stat, scope rt_trace, type r */ +typedef struct { + unsigned int dav : 1; + unsigned int empty : 1; + unsigned int dummy1 : 30; +} reg_rt_trace_r_tap_stat; +#define REG_RD_ADDR_rt_trace_r_tap_stat 8 + +/* Register rw_tap_data, scope rt_trace, type rw */ +typedef unsigned int reg_rt_trace_rw_tap_data; +#define REG_RD_ADDR_rt_trace_rw_tap_data 12 +#define REG_WR_ADDR_rt_trace_rw_tap_data 12 + +/* Register rw_tap_hdata, scope rt_trace, type rw */ +typedef struct { + unsigned int op : 4; + unsigned int sub_op : 4; + unsigned int dummy1 : 24; +} reg_rt_trace_rw_tap_hdata; +#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 +#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 + +/* Register r_redir, scope rt_trace, type r */ +typedef unsigned int reg_rt_trace_r_redir; +#define REG_RD_ADDR_rt_trace_r_redir 20 + + +/* Constants */ +enum { + regk_rt_trace_brk = 0x0000000c, + regk_rt_trace_dbg = 0x00000003, + regk_rt_trace_dbgdi = 0x00000004, + regk_rt_trace_dbgdo = 0x00000005, + regk_rt_trace_gmode = 0x00000000, + regk_rt_trace_no = 0x00000000, + regk_rt_trace_nop = 0x00000000, + regk_rt_trace_normal = 0x00000000, + regk_rt_trace_rdmem = 0x00000007, + regk_rt_trace_rdmemb = 0x00000009, + regk_rt_trace_rdpreg = 0x00000002, + regk_rt_trace_rdreg = 0x00000001, + regk_rt_trace_rdsreg = 0x00000003, + regk_rt_trace_redir = 0x00000006, + regk_rt_trace_ret = 0x0000000b, + regk_rt_trace_rw_cfg_default = 0x00000000, + regk_rt_trace_trcfg = 0x00000001, + regk_rt_trace_wp = 0x00000001, + regk_rt_trace_wp0 = 0x00000001, + regk_rt_trace_wp1 = 0x00000002, + regk_rt_trace_wp2 = 0x00000004, + regk_rt_trace_wp3 = 0x00000008, + regk_rt_trace_wp4 = 0x00000010, + regk_rt_trace_wp5 = 0x00000020, + regk_rt_trace_wp6 = 0x00000040, + regk_rt_trace_wrmem = 0x00000008, + regk_rt_trace_wrmemb = 0x0000000a, + regk_rt_trace_wrpreg = 0x00000005, + regk_rt_trace_wrreg = 0x00000004, + regk_rt_trace_wrsreg = 0x00000006, + regk_rt_trace_yes = 0x00000001 +}; +#endif /* __rt_trace_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h new file mode 100644 index 000000000000..01c2fab97d43 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/ser_defs.h @@ -0,0 +1,308 @@ +#ifndef __ser_defs_h +#define __ser_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ser/rtl/ser_regs.r + * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp + * last modfied: Mon Apr 11 16:09:21 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r + * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ser */ + +/* Register rw_tr_ctrl, scope ser, type rw */ +typedef struct { + unsigned int base_freq : 3; + unsigned int en : 1; + unsigned int par : 2; + unsigned int par_en : 1; + unsigned int data_bits : 1; + unsigned int stop_bits : 1; + unsigned int stop : 1; + unsigned int rts_delay : 3; + unsigned int rts_setup : 1; + unsigned int auto_rts : 1; + unsigned int txd : 1; + unsigned int auto_cts : 1; + unsigned int dummy1 : 15; +} reg_ser_rw_tr_ctrl; +#define REG_RD_ADDR_ser_rw_tr_ctrl 0 +#define REG_WR_ADDR_ser_rw_tr_ctrl 0 + +/* Register rw_tr_dma_en, scope ser, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_tr_dma_en; +#define REG_RD_ADDR_ser_rw_tr_dma_en 4 +#define REG_WR_ADDR_ser_rw_tr_dma_en 4 + +/* Register rw_rec_ctrl, scope ser, type rw */ +typedef struct { + unsigned int base_freq : 3; + unsigned int en : 1; + unsigned int par : 2; + unsigned int par_en : 1; + unsigned int data_bits : 1; + unsigned int dma_mode : 1; + unsigned int dma_err : 1; + unsigned int sampling : 1; + unsigned int timeout : 3; + unsigned int auto_eop : 1; + unsigned int half_duplex : 1; + unsigned int rts_n : 1; + unsigned int loopback : 1; + unsigned int dummy1 : 14; +} reg_ser_rw_rec_ctrl; +#define REG_RD_ADDR_ser_rw_rec_ctrl 8 +#define REG_WR_ADDR_ser_rw_rec_ctrl 8 + +/* Register rw_tr_baud_div, scope ser, type rw */ +typedef struct { + unsigned int div : 16; + unsigned int dummy1 : 16; +} reg_ser_rw_tr_baud_div; +#define REG_RD_ADDR_ser_rw_tr_baud_div 12 +#define REG_WR_ADDR_ser_rw_tr_baud_div 12 + +/* Register rw_rec_baud_div, scope ser, type rw */ +typedef struct { + unsigned int div : 16; + unsigned int dummy1 : 16; +} reg_ser_rw_rec_baud_div; +#define REG_RD_ADDR_ser_rw_rec_baud_div 16 +#define REG_WR_ADDR_ser_rw_rec_baud_div 16 + +/* Register rw_xoff, scope ser, type rw */ +typedef struct { + unsigned int chr : 8; + unsigned int automatic : 1; + unsigned int dummy1 : 23; +} reg_ser_rw_xoff; +#define REG_RD_ADDR_ser_rw_xoff 20 +#define REG_WR_ADDR_ser_rw_xoff 20 + +/* Register rw_xoff_clr, scope ser, type rw */ +typedef struct { + unsigned int clr : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_xoff_clr; +#define REG_RD_ADDR_ser_rw_xoff_clr 24 +#define REG_WR_ADDR_ser_rw_xoff_clr 24 + +/* Register rw_dout, scope ser, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_ser_rw_dout; +#define REG_RD_ADDR_ser_rw_dout 28 +#define REG_WR_ADDR_ser_rw_dout 28 + +/* Register rs_stat_din, scope ser, type rs */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 8; + unsigned int dav : 1; + unsigned int framing_err : 1; + unsigned int par_err : 1; + unsigned int orun : 1; + unsigned int rec_err : 1; + unsigned int rxd : 1; + unsigned int tr_idle : 1; + unsigned int tr_empty : 1; + unsigned int tr_rdy : 1; + unsigned int cts_n : 1; + unsigned int xoff_detect : 1; + unsigned int rts_n : 1; + unsigned int txd : 1; + unsigned int dummy2 : 3; +} reg_ser_rs_stat_din; +#define REG_RD_ADDR_ser_rs_stat_din 32 + +/* Register r_stat_din, scope ser, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 8; + unsigned int dav : 1; + unsigned int framing_err : 1; + unsigned int par_err : 1; + unsigned int orun : 1; + unsigned int rec_err : 1; + unsigned int rxd : 1; + unsigned int tr_idle : 1; + unsigned int tr_empty : 1; + unsigned int tr_rdy : 1; + unsigned int cts_n : 1; + unsigned int xoff_detect : 1; + unsigned int rts_n : 1; + unsigned int txd : 1; + unsigned int dummy2 : 3; +} reg_ser_r_stat_din; +#define REG_RD_ADDR_ser_r_stat_din 36 + +/* Register rw_rec_eop, scope ser, type rw */ +typedef struct { + unsigned int set : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_rec_eop; +#define REG_RD_ADDR_ser_rw_rec_eop 40 +#define REG_WR_ADDR_ser_rw_rec_eop 40 + +/* Register rw_intr_mask, scope ser, type rw */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_rw_intr_mask; +#define REG_RD_ADDR_ser_rw_intr_mask 44 +#define REG_WR_ADDR_ser_rw_intr_mask 44 + +/* Register rw_ack_intr, scope ser, type rw */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_rw_ack_intr; +#define REG_RD_ADDR_ser_rw_ack_intr 48 +#define REG_WR_ADDR_ser_rw_ack_intr 48 + +/* Register r_intr, scope ser, type r */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_r_intr; +#define REG_RD_ADDR_ser_r_intr 52 + +/* Register r_masked_intr, scope ser, type r */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_r_masked_intr; +#define REG_RD_ADDR_ser_r_masked_intr 56 + + +/* Constants */ +enum { + regk_ser_active = 0x00000000, + regk_ser_bits1 = 0x00000000, + regk_ser_bits2 = 0x00000001, + regk_ser_bits7 = 0x00000001, + regk_ser_bits8 = 0x00000000, + regk_ser_del0_5 = 0x00000000, + regk_ser_del1 = 0x00000001, + regk_ser_del1_5 = 0x00000002, + regk_ser_del2 = 0x00000003, + regk_ser_del2_5 = 0x00000004, + regk_ser_del3 = 0x00000005, + regk_ser_del3_5 = 0x00000006, + regk_ser_del4 = 0x00000007, + regk_ser_even = 0x00000000, + regk_ser_ext = 0x00000001, + regk_ser_f100 = 0x00000007, + regk_ser_f29_493 = 0x00000004, + regk_ser_f32 = 0x00000005, + regk_ser_f32_768 = 0x00000006, + regk_ser_ignore = 0x00000001, + regk_ser_inactive = 0x00000001, + regk_ser_majority = 0x00000001, + regk_ser_mark = 0x00000002, + regk_ser_middle = 0x00000000, + regk_ser_no = 0x00000000, + regk_ser_odd = 0x00000001, + regk_ser_off = 0x00000000, + regk_ser_rw_intr_mask_default = 0x00000000, + regk_ser_rw_rec_baud_div_default = 0x00000000, + regk_ser_rw_rec_ctrl_default = 0x00010000, + regk_ser_rw_tr_baud_div_default = 0x00000000, + regk_ser_rw_tr_ctrl_default = 0x00008000, + regk_ser_rw_tr_dma_en_default = 0x00000000, + regk_ser_rw_xoff_default = 0x00000000, + regk_ser_space = 0x00000003, + regk_ser_stop = 0x00000000, + regk_ser_yes = 0x00000001 +}; +#endif /* __ser_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h new file mode 100644 index 000000000000..8d1dab218b91 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/sser_defs.h @@ -0,0 +1,331 @@ +#ifndef __sser_defs_h +#define __sser_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/syncser/rtl/sser_regs.r + * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp + * last modfied: Mon Apr 11 16:09:48 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r + * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope sser */ + +/* Register rw_cfg, scope sser, type rw */ +typedef struct { + unsigned int clk_div : 16; + unsigned int base_freq : 3; + unsigned int gate_clk : 1; + unsigned int clkgate_ctrl : 1; + unsigned int clkgate_in : 1; + unsigned int clk_dir : 1; + unsigned int clk_od_mode : 1; + unsigned int out_clk_pol : 1; + unsigned int out_clk_src : 2; + unsigned int clk_in_sel : 1; + unsigned int hold_pol : 1; + unsigned int prepare : 1; + unsigned int en : 1; + unsigned int dummy1 : 1; +} reg_sser_rw_cfg; +#define REG_RD_ADDR_sser_rw_cfg 0 +#define REG_WR_ADDR_sser_rw_cfg 0 + +/* Register rw_frm_cfg, scope sser, type rw */ +typedef struct { + unsigned int wordrate : 10; + unsigned int rec_delay : 3; + unsigned int tr_delay : 3; + unsigned int early_wend : 1; + unsigned int level : 2; + unsigned int type : 1; + unsigned int clk_pol : 1; + unsigned int fr_in_rxclk : 1; + unsigned int clk_src : 1; + unsigned int out_off : 1; + unsigned int out_on : 1; + unsigned int frame_pin_dir : 1; + unsigned int frame_pin_use : 2; + unsigned int status_pin_dir : 1; + unsigned int status_pin_use : 2; + unsigned int dummy1 : 1; +} reg_sser_rw_frm_cfg; +#define REG_RD_ADDR_sser_rw_frm_cfg 4 +#define REG_WR_ADDR_sser_rw_frm_cfg 4 + +/* Register rw_tr_cfg, scope sser, type rw */ +typedef struct { + unsigned int tr_en : 1; + unsigned int stop : 1; + unsigned int urun_stop : 1; + unsigned int eop_stop : 1; + unsigned int sample_size : 6; + unsigned int sh_dir : 1; + unsigned int clk_pol : 1; + unsigned int clk_src : 1; + unsigned int use_dma : 1; + unsigned int mode : 2; + unsigned int frm_src : 1; + unsigned int use60958 : 1; + unsigned int iec60958_ckdiv : 2; + unsigned int rate_ctrl : 1; + unsigned int use_md : 1; + unsigned int dual_i2s : 1; + unsigned int data_pin_use : 2; + unsigned int od_mode : 1; + unsigned int bulk_wspace : 2; + unsigned int dummy1 : 4; +} reg_sser_rw_tr_cfg; +#define REG_RD_ADDR_sser_rw_tr_cfg 8 +#define REG_WR_ADDR_sser_rw_tr_cfg 8 + +/* Register rw_rec_cfg, scope sser, type rw */ +typedef struct { + unsigned int rec_en : 1; + unsigned int force_eop : 1; + unsigned int stop : 1; + unsigned int orun_stop : 1; + unsigned int eop_stop : 1; + unsigned int sample_size : 6; + unsigned int sh_dir : 1; + unsigned int clk_pol : 1; + unsigned int clk_src : 1; + unsigned int use_dma : 1; + unsigned int mode : 2; + unsigned int frm_src : 2; + unsigned int use60958 : 1; + unsigned int iec60958_ui_len : 5; + unsigned int slave2_en : 1; + unsigned int slave3_en : 1; + unsigned int fifo_thr : 2; + unsigned int dummy1 : 3; +} reg_sser_rw_rec_cfg; +#define REG_RD_ADDR_sser_rw_rec_cfg 12 +#define REG_WR_ADDR_sser_rw_rec_cfg 12 + +/* Register rw_tr_data, scope sser, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int md : 1; + unsigned int dummy1 : 15; +} reg_sser_rw_tr_data; +#define REG_RD_ADDR_sser_rw_tr_data 16 +#define REG_WR_ADDR_sser_rw_tr_data 16 + +/* Register r_rec_data, scope sser, type r */ +typedef struct { + unsigned int data : 16; + unsigned int md : 1; + unsigned int ext_clk : 1; + unsigned int status_in : 1; + unsigned int frame_in : 1; + unsigned int din : 1; + unsigned int data_in : 1; + unsigned int clk_in : 1; + unsigned int dummy1 : 9; +} reg_sser_r_rec_data; +#define REG_RD_ADDR_sser_r_rec_data 20 + +/* Register rw_extra, scope sser, type rw */ +typedef struct { + unsigned int clkoff_cycles : 20; + unsigned int clkoff_en : 1; + unsigned int clkon_en : 1; + unsigned int dout_delay : 5; + unsigned int dummy1 : 5; +} reg_sser_rw_extra; +#define REG_RD_ADDR_sser_rw_extra 24 +#define REG_WR_ADDR_sser_rw_extra 24 + +/* Register rw_intr_mask, scope sser, type rw */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_rw_intr_mask; +#define REG_RD_ADDR_sser_rw_intr_mask 28 +#define REG_WR_ADDR_sser_rw_intr_mask 28 + +/* Register rw_ack_intr, scope sser, type rw */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_rw_ack_intr; +#define REG_RD_ADDR_sser_rw_ack_intr 32 +#define REG_WR_ADDR_sser_rw_ack_intr 32 + +/* Register r_intr, scope sser, type r */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_r_intr; +#define REG_RD_ADDR_sser_r_intr 36 + +/* Register r_masked_intr, scope sser, type r */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_r_masked_intr; +#define REG_RD_ADDR_sser_r_masked_intr 40 + + +/* Constants */ +enum { + regk_sser_both = 0x00000002, + regk_sser_bulk = 0x00000001, + regk_sser_clk100 = 0x00000000, + regk_sser_clk_in = 0x00000000, + regk_sser_const0 = 0x00000003, + regk_sser_dout = 0x00000002, + regk_sser_edge = 0x00000000, + regk_sser_ext = 0x00000001, + regk_sser_ext_clk = 0x00000001, + regk_sser_f100 = 0x00000000, + regk_sser_f29_493 = 0x00000004, + regk_sser_f32 = 0x00000005, + regk_sser_f32_768 = 0x00000006, + regk_sser_frm = 0x00000003, + regk_sser_gio0 = 0x00000000, + regk_sser_gio1 = 0x00000001, + regk_sser_hispeed = 0x00000001, + regk_sser_hold = 0x00000002, + regk_sser_in = 0x00000000, + regk_sser_inf = 0x00000003, + regk_sser_intern = 0x00000000, + regk_sser_intern_clk = 0x00000001, + regk_sser_intern_tb = 0x00000000, + regk_sser_iso = 0x00000000, + regk_sser_level = 0x00000001, + regk_sser_lospeed = 0x00000000, + regk_sser_lsbfirst = 0x00000000, + regk_sser_msbfirst = 0x00000001, + regk_sser_neg = 0x00000001, + regk_sser_neg_lo = 0x00000000, + regk_sser_no = 0x00000000, + regk_sser_no_clk = 0x00000007, + regk_sser_nojitter = 0x00000002, + regk_sser_out = 0x00000001, + regk_sser_pos = 0x00000000, + regk_sser_pos_hi = 0x00000001, + regk_sser_rec = 0x00000000, + regk_sser_rw_cfg_default = 0x00000000, + regk_sser_rw_extra_default = 0x00000000, + regk_sser_rw_frm_cfg_default = 0x00000000, + regk_sser_rw_intr_mask_default = 0x00000000, + regk_sser_rw_rec_cfg_default = 0x00000000, + regk_sser_rw_tr_cfg_default = 0x01800000, + regk_sser_rw_tr_data_default = 0x00000000, + regk_sser_thr16 = 0x00000001, + regk_sser_thr32 = 0x00000002, + regk_sser_thr8 = 0x00000000, + regk_sser_tr = 0x00000001, + regk_sser_ts_out = 0x00000003, + regk_sser_tx_bulk = 0x00000002, + regk_sser_wiresave = 0x00000002, + regk_sser_yes = 0x00000001 +}; +#endif /* __sser_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h new file mode 100644 index 000000000000..35131ba466f3 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/strcop.h @@ -0,0 +1,57 @@ +// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ + +// Streamcop meta-data configuration structs + +struct strcop_meta_out { + unsigned char csumsel : 3; + unsigned char ciphsel : 3; + unsigned char ciphconf : 2; + unsigned char hashsel : 3; + unsigned char hashconf : 1; + unsigned char hashmode : 1; + unsigned char decrypt : 1; + unsigned char dlkey : 1; + unsigned char cbcmode : 1; +}; + +struct strcop_meta_in { + unsigned char dmasel : 3; + unsigned char sync : 1; + unsigned char res1 : 5; + unsigned char res2; +}; + +// Source definitions + +enum { + src_none = 0, + src_dma = 1, + src_des = 2, + src_sha1 = 3, + src_csum = 4, + src_aes = 5, + src_md5 = 6, + src_res = 7 +}; + +// Cipher definitions + +enum { + ciph_des = 0, + ciph_3des = 1, + ciph_aes = 2 +}; + +// Hash definitions + +enum { + hash_sha1 = 0, + hash_md5 = 1 +}; + +enum { + hash_noiv = 0, + hash_iv = 1 +}; + + diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h new file mode 100644 index 000000000000..bd145a49b2c4 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/strcop_defs.h @@ -0,0 +1,109 @@ +#ifndef __strcop_defs_h +#define __strcop_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/strcop/rtl/strcop_regs.r + * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp + * last modfied: Mon Apr 11 16:09:38 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r + * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strcop */ + +/* Register rw_cfg, scope strcop, type rw */ +typedef struct { + unsigned int td3 : 1; + unsigned int td2 : 1; + unsigned int td1 : 1; + unsigned int ipend : 1; + unsigned int ignore_sync : 1; + unsigned int en : 1; + unsigned int dummy1 : 26; +} reg_strcop_rw_cfg; +#define REG_RD_ADDR_strcop_rw_cfg 0 +#define REG_WR_ADDR_strcop_rw_cfg 0 + + +/* Constants */ +enum { + regk_strcop_big = 0x00000001, + regk_strcop_d = 0x00000001, + regk_strcop_e = 0x00000000, + regk_strcop_little = 0x00000000, + regk_strcop_rw_cfg_default = 0x00000002 +}; +#endif /* __strcop_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h new file mode 100644 index 000000000000..67474855c499 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/strmux_defs.h @@ -0,0 +1,127 @@ +#ifndef __strmux_defs_h +#define __strmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp + * last modfied: Mon Apr 11 16:09:43 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strmux */ + +/* Register rw_cfg, scope strmux, type rw */ +typedef struct { + unsigned int dma0 : 3; + unsigned int dma1 : 3; + unsigned int dma2 : 3; + unsigned int dma3 : 3; + unsigned int dma4 : 3; + unsigned int dma5 : 3; + unsigned int dma6 : 3; + unsigned int dma7 : 3; + unsigned int dma8 : 3; + unsigned int dma9 : 3; + unsigned int dummy1 : 2; +} reg_strmux_rw_cfg; +#define REG_RD_ADDR_strmux_rw_cfg 0 +#define REG_WR_ADDR_strmux_rw_cfg 0 + + +/* Constants */ +enum { + regk_strmux_ata = 0x00000003, + regk_strmux_eth0 = 0x00000001, + regk_strmux_eth1 = 0x00000004, + regk_strmux_ext0 = 0x00000001, + regk_strmux_ext1 = 0x00000001, + regk_strmux_ext2 = 0x00000001, + regk_strmux_ext3 = 0x00000001, + regk_strmux_iop0 = 0x00000002, + regk_strmux_iop1 = 0x00000001, + regk_strmux_off = 0x00000000, + regk_strmux_p21 = 0x00000004, + regk_strmux_rw_cfg_default = 0x00000000, + regk_strmux_ser0 = 0x00000002, + regk_strmux_ser1 = 0x00000002, + regk_strmux_ser2 = 0x00000004, + regk_strmux_ser3 = 0x00000003, + regk_strmux_sser0 = 0x00000003, + regk_strmux_sser1 = 0x00000003, + regk_strmux_strcop = 0x00000002 +}; +#endif /* __strmux_defs_h */ diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h new file mode 100644 index 000000000000..ffe49625ae36 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/supp_reg.h @@ -0,0 +1,78 @@ +#ifndef __SUPP_REG_H__ +#define __SUPP_REG_H__ + +/* Macros for reading and writing support/special registers. */ + +#ifndef STRINGIFYFY +#define STRINGIFYFY(i) #i +#endif + +#ifndef STRINGIFY +#define STRINGIFY(i) STRINGIFYFY(i) +#endif + +#define SPEC_REG_BZ "BZ" +#define SPEC_REG_VR "VR" +#define SPEC_REG_PID "PID" +#define SPEC_REG_SRS "SRS" +#define SPEC_REG_WZ "WZ" +#define SPEC_REG_EXS "EXS" +#define SPEC_REG_EDA "EDA" +#define SPEC_REG_MOF "MOF" +#define SPEC_REG_DZ "DZ" +#define SPEC_REG_EBP "EBP" +#define SPEC_REG_ERP "ERP" +#define SPEC_REG_SRP "SRP" +#define SPEC_REG_NRP "NRP" +#define SPEC_REG_CCS "CCS" +#define SPEC_REG_USP "USP" +#define SPEC_REG_SPC "SPC" + +#define RW_MM_CFG 0 +#define RW_MM_KBASE_LO 1 +#define RW_MM_KBASE_HI 2 +#define RW_MM_CAUSE 3 +#define RW_MM_TLB_SEL 4 +#define RW_MM_TLB_LO 5 +#define RW_MM_TLB_HI 6 +#define RW_MM_TLB_PGD 7 + +#define BANK_GC 0 +#define BANK_IM 1 +#define BANK_DM 2 +#define BANK_BP 3 + +#define RW_GC_CFG 0 +#define RW_GC_CCS 1 +#define RW_GC_SRS 2 +#define RW_GC_NRP 3 +#define RW_GC_EXS 4 +#define RW_GC_R0 8 +#define RW_GC_R1 9 + +#define SPEC_REG_WR(r,v) \ +__asm__ __volatile__ ("move %0, $" r : : "r" (v)); + +#define SPEC_REG_RD(r,v) \ +__asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); + +#define NOP() \ + __asm__ __volatile__ ("nop"); + +#define SUPP_BANK_SEL(b) \ + SPEC_REG_WR(SPEC_REG_SRS,b); \ + NOP(); \ + NOP(); \ + NOP(); + +#define SUPP_REG_WR(r,v) \ +__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + : : "r" (v)); + +#define SUPP_REG_RD(r,v) \ +__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); + +#endif /* __SUPP_REG_H__ */ diff --git a/include/asm-cris/arch-v32/hwregs/timer_defs.h b/include/asm-cris/arch-v32/hwregs/timer_defs.h new file mode 100644 index 000000000000..20c8c89ec076 --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/timer_defs.h @@ -0,0 +1,266 @@ +#ifndef __timer_defs_h +#define __timer_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope timer */ + +/* Register rw_tmr0_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr0_div; +#define REG_RD_ADDR_timer_rw_tmr0_div 0 +#define REG_WR_ADDR_timer_rw_tmr0_div 0 + +/* Register r_tmr0_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr0_data; +#define REG_RD_ADDR_timer_r_tmr0_data 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr0_ctrl; +#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 +#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr1_div; +#define REG_RD_ADDR_timer_rw_tmr1_div 16 +#define REG_WR_ADDR_timer_rw_tmr1_div 16 + +/* Register r_tmr1_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr1_data; +#define REG_RD_ADDR_timer_r_tmr1_data 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr1_ctrl; +#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 +#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 + +/* Register rs_cnt_data, scope timer, type rs */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_rs_cnt_data; +#define REG_RD_ADDR_timer_rs_cnt_data 32 + +/* Register r_cnt_data, scope timer, type r */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_r_cnt_data; +#define REG_RD_ADDR_timer_r_cnt_data 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +typedef struct { + unsigned int clk : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_cnt_cfg; +#define REG_RD_ADDR_timer_rw_cnt_cfg 40 +#define REG_WR_ADDR_timer_rw_cnt_cfg 40 + +/* Register rw_trig, scope timer, type rw */ +typedef unsigned int reg_timer_rw_trig; +#define REG_RD_ADDR_timer_rw_trig 48 +#define REG_WR_ADDR_timer_rw_trig 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_trig_cfg; +#define REG_RD_ADDR_timer_rw_trig_cfg 52 +#define REG_WR_ADDR_timer_rw_trig_cfg 52 + +/* Register r_time, scope timer, type r */ +typedef unsigned int reg_timer_r_time; +#define REG_RD_ADDR_timer_r_time 56 + +/* Register rw_out, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_out; +#define REG_RD_ADDR_timer_rw_out 60 +#define REG_WR_ADDR_timer_rw_out 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int key : 7; + unsigned int dummy1 : 16; +} reg_timer_rw_wd_ctrl; +#define REG_RD_ADDR_timer_rw_wd_ctrl 64 +#define REG_WR_ADDR_timer_rw_wd_ctrl 64 + +/* Register r_wd_stat, scope timer, type r */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int dummy1 : 23; +} reg_timer_r_wd_stat; +#define REG_RD_ADDR_timer_r_wd_stat 68 + +/* Register rw_intr_mask, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_intr_mask; +#define REG_RD_ADDR_timer_rw_intr_mask 72 +#define REG_WR_ADDR_timer_rw_intr_mask 72 + +/* Register rw_ack_intr, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_ack_intr; +#define REG_RD_ADDR_timer_rw_ack_intr 76 +#define REG_WR_ADDR_timer_rw_ack_intr 76 + +/* Register r_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_intr; +#define REG_RD_ADDR_timer_r_intr 80 + +/* Register r_masked_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_masked_intr; +#define REG_RD_ADDR_timer_r_masked_intr 84 + +/* Register rw_test, scope timer, type rw */ +typedef struct { + unsigned int dis : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_timer_rw_test; +#define REG_RD_ADDR_timer_rw_test 88 +#define REG_WR_ADDR_timer_rw_test 88 + + +/* Constants */ +enum { + regk_timer_ext = 0x00000001, + regk_timer_f100 = 0x00000007, + regk_timer_f29_493 = 0x00000004, + regk_timer_f32 = 0x00000005, + regk_timer_f32_768 = 0x00000006, + regk_timer_hold = 0x00000001, + regk_timer_ld = 0x00000000, + regk_timer_no = 0x00000000, + regk_timer_off = 0x00000000, + regk_timer_run = 0x00000002, + regk_timer_rw_cnt_cfg_default = 0x00000000, + regk_timer_rw_intr_mask_default = 0x00000000, + regk_timer_rw_out_default = 0x00000000, + regk_timer_rw_test_default = 0x00000000, + regk_timer_rw_tmr0_ctrl_default = 0x00000000, + regk_timer_rw_tmr1_ctrl_default = 0x00000000, + regk_timer_rw_trig_cfg_default = 0x00000000, + regk_timer_start = 0x00000001, + regk_timer_stop = 0x00000000, + regk_timer_time = 0x00000001, + regk_timer_tmr0 = 0x00000002, + regk_timer_tmr1 = 0x00000003, + regk_timer_yes = 0x00000001 +}; +#endif /* __timer_defs_h */ diff --git a/include/asm-cris/arch-v32/ide.h b/include/asm-cris/arch-v32/ide.h new file mode 100644 index 000000000000..24f5604f566a --- /dev/null +++ b/include/asm-cris/arch-v32/ide.h @@ -0,0 +1,61 @@ +/* + * linux/include/asm-cris/ide.h + * + * Copyright (C) 2000-2004 Axis Communications AB + * + * Authors: Bjorn Wesen, Mikael Starvik + * + */ + +/* + * This file contains the ETRAX FS specific IDE code. + */ + +#ifndef __ASMCRIS_IDE_H +#define __ASMCRIS_IDE_H + +#ifdef __KERNEL__ + +#include <asm/arch/hwregs/intr_vect.h> +#include <asm/arch/hwregs/ata_defs.h> +#include <asm/io.h> +#include <asm-generic/ide_iops.h> + + +/* ETRAX FS can support 4 IDE busses on the same pins (serialized) */ + +#define MAX_HWIFS 4 + +extern __inline__ int ide_default_irq(unsigned long base) +{ + /* all IDE busses share the same IRQ, + * this has the side-effect that ide-probe.c will cluster our 4 interfaces + * together in a hwgroup, and will serialize accesses. this is good, because + * we can't access more than one interface at the same time on ETRAX100. + */ + return ATA_INTR_VECT; +} + +extern __inline__ unsigned long ide_default_io_base(int index) +{ + reg_ata_rw_ctrl2 ctrl2 = {.sel = index}; + /* we have no real I/O base address per interface, since all go through the + * same register. but in a bitfield in that register, we have the i/f number. + * so we can use the io_base to remember that bitfield. + */ + ctrl2.sel = index; + + return REG_TYPE_CONV(unsigned long, reg_ata_rw_ctrl2, ctrl2); +} + +/* some configuration options we don't need */ + +#undef SUPPORT_VLB_SYNC +#define SUPPORT_VLB_SYNC 0 + +#define IDE_ARCH_ACK_INTR +#define ide_ack_intr(hwif) (hwif)->hw.ack_intr(hwif) + +#endif /* __KERNEL__ */ + +#endif /* __ASMCRIS_IDE_H */ diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h new file mode 100644 index 000000000000..c0ada33bf90f --- /dev/null +++ b/include/asm-cris/arch-v32/intmem.h @@ -0,0 +1,9 @@ +#ifndef _ASM_CRIS_INTMEM_H +#define _ASM_CRIS_INTMEM_H + +void* crisv32_intmem_alloc(unsigned size, unsigned align); +void crisv32_intmem_free(void* addr); +void* crisv32_intmem_phys_to_virt(unsigned long addr); +unsigned long crisv32_intmem_virt_to_phys(void *addr); + +#endif /* _ASM_CRIS_ARCH_INTMEM_H */ diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h new file mode 100644 index 000000000000..4c80263ec634 --- /dev/null +++ b/include/asm-cris/arch-v32/io.h @@ -0,0 +1,98 @@ +#ifndef _ASM_ARCH_CRIS_IO_H +#define _ASM_ARCH_CRIS_IO_H + +#include <asm/arch/hwregs/reg_map.h> +#include <asm/arch/hwregs/reg_rdwr.h> +#include <asm/arch/hwregs/gio_defs.h> +#include <linux/config.h> + +enum crisv32_io_dir +{ + crisv32_io_dir_in = 0, + crisv32_io_dir_out = 1 +}; + +struct crisv32_ioport +{ + unsigned long* oe; + unsigned long* data; + unsigned long* data_in; + unsigned int pin_count; +}; + +struct crisv32_iopin +{ + struct crisv32_ioport* port; + int bit; +}; + +extern struct crisv32_ioport crisv32_ioports[]; + +extern struct crisv32_iopin crisv32_led1_green; +extern struct crisv32_iopin crisv32_led1_red; +extern struct crisv32_iopin crisv32_led2_green; +extern struct crisv32_iopin crisv32_led2_red; +extern struct crisv32_iopin crisv32_led3_green; +extern struct crisv32_iopin crisv32_led3_red; + +extern inline void crisv32_io_set(struct crisv32_iopin* iopin, + int val) +{ + if (val) + *iopin->port->data |= iopin->bit; + else + *iopin->port->data &= ~iopin->bit; +} + +extern inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, + enum crisv32_io_dir dir) +{ + if (dir == crisv32_io_dir_in) + *iopin->port->oe &= ~iopin->bit; + else + *iopin->port->oe |= iopin->bit; +} + +extern inline int crisv32_io_rd(struct crisv32_iopin* iopin) +{ + return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); +} + +int crisv32_io_get(struct crisv32_iopin* iopin, + unsigned int port, unsigned int pin); +int crisv32_io_get_name(struct crisv32_iopin* iopin, + char* name); + +#define LED_OFF 0x00 +#define LED_GREEN 0x01 +#define LED_RED 0x02 +#define LED_ORANGE (LED_GREEN | LED_RED) + +#define LED_NETWORK_SET(x) \ + do { \ + LED_NETWORK_SET_G((x) & LED_GREEN); \ + LED_NETWORK_SET_R((x) & LED_RED); \ + } while (0) +#define LED_ACTIVE_SET(x) \ + do { \ + LED_ACTIVE_SET_G((x) & LED_GREEN); \ + LED_ACTIVE_SET_R((x) & LED_RED); \ + } while (0) + +#define LED_NETWORK_SET_G(x) \ + crisv32_io_set(&crisv32_led1_green, !(x)); +#define LED_NETWORK_SET_R(x) \ + crisv32_io_set(&crisv32_led1_red, !(x)); +#define LED_ACTIVE_SET_G(x) \ + crisv32_io_set(&crisv32_led2_green, !(x)); +#define LED_ACTIVE_SET_R(x) \ + crisv32_io_set(&crisv32_led2_red, !(x)); +#define LED_DISK_WRITE(x) \ + do{\ + crisv32_io_set(&crisv32_led3_green, !(x)); \ + crisv32_io_set(&crisv32_led3_red, !(x)); \ + }while(0) +#define LED_DISK_READ(x) \ + crisv32_io_set(&crisv32_led3_green, !(x)); + +#endif diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h new file mode 100644 index 000000000000..d35aa8174c2f --- /dev/null +++ b/include/asm-cris/arch-v32/irq.h @@ -0,0 +1,120 @@ +#ifndef _ASM_ARCH_IRQ_H +#define _ASM_ARCH_IRQ_H + +#include <linux/config.h> +#include "hwregs/intr_vect.h" + +/* Number of non-cpu interrupts. */ +#define NR_IRQS 0x50 /* Exceptions + IRQs */ +#define NR_REAL_IRQS 0x20 /* IRQs */ +#define FIRST_IRQ 0x31 /* Exception number for first IRQ */ + +#ifndef __ASSEMBLY__ +/* Global IRQ vector. */ +typedef void (*irqvectptr)(void); + +struct etrax_interrupt_vector { + irqvectptr v[256]; +}; + +extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ + +void mask_irq(int irq); +void unmask_irq(int irq); + +void set_exception_vector(int n, irqvectptr addr); + +/* Save registers so that they match pt_regs. */ +#define SAVE_ALL \ + "subq 12,$sp\n\t" \ + "move $erp,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $srp,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $ccs,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $spc,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $mof,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $srs,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move.d $acr,[$sp]\n\t" \ + "subq 14*4,$sp\n\t" \ + "movem $r13,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move.d $r10,[$sp]\n" + +#define STR2(x) #x +#define STR(x) STR2(x) + +#define IRQ_NAME2(nr) nr##_interrupt(void) +#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) + +/* + * The reason for setting the S-bit when debugging the kernel is that we want + * hardware breakpoints to remain active while we are in an exception handler. + * Note that we cannot simply copy S1, since we may come here from user-space, + * or any context where the S-bit wasn't set. + */ +#ifdef CONFIG_ETRAX_KGDB +#define KGDB_FIXUP \ + "move $ccs, $r10\n\t" \ + "or.d (1<<9), $r10\n\t" \ + "move $r10, $ccs\n\t" +#else +#define KGDB_FIXUP "" +#endif + +/* + * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock + * and jump to ret_from_intr which is found in entry.S. + * + * The reason for blocking the IRQ is to allow an sti() before the handler, + * which will acknowledge the interrupt, is run. The actual blocking is made + * by crisv32_do_IRQ. + */ +#define BUILD_IRQ(nr, mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + KGDB_FIXUP \ + "move.d "#nr",$r10\n\t" \ + "move.d $sp,$r12\n\t" \ + "jsr crisv32_do_IRQ\n\t" \ + "moveq 1, $r11\n\t" \ + "jump ret_from_intr\n\t" \ + "nop\n\t"); +/* + * This is subtle. The timer interrupt is crucial and it should not be disabled + * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it + * would have been BLOCK'ed, and then softirq's are run before we return here to + * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run + * and the watchdog will kill us. + * + * Furthermore, if a lot of other irq's occur before we return here, the + * multiple_irq handler is run and it prioritizes the timer interrupt. However + * if we had BLOCK'edit here, we would not get the multiple_irq at all. + * + * The non-blocking here is based on the knowledge that the timer interrupt is + * registred as a fast interrupt (SA_INTERRUPT) so that we _know_ there will not + * be an sti() before the timer irq handler is run to acknowledge the interrupt. + */ +#define BUILD_TIMER_IRQ(nr, mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + KGDB_FIXUP \ + "move.d "#nr",$r10\n\t" \ + "move.d $sp,$r12\n\t" \ + "jsr crisv32_do_IRQ\n\t" \ + "moveq 0,$r11\n\t" \ + "jump ret_from_intr\n\t" \ + "nop\n\t"); + +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_ARCH_IRQ_H */ diff --git a/include/asm-cris/arch-v32/juliette.h b/include/asm-cris/arch-v32/juliette.h new file mode 100644 index 000000000000..f1f81725e57b --- /dev/null +++ b/include/asm-cris/arch-v32/juliette.h @@ -0,0 +1,326 @@ +#ifndef _ASM_JULIETTE_H +#define _ASM_JULIETTE_H + +/* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */ + +#define JULIOCTYPE 42 + +/* supported ioctl _IOC_NR's */ + +#define JULSTARTDMA 0x1 /* start a picture asynchronously */ + +/* set parameters */ + +#define SETDEFAULT 0x2 /* CCD/VIDEO/SS1M */ +#define SETPARAMETERS 0x3 /* CCD/VIDEO */ +#define SETSIZE 0x4 /* CCD/VIDEO/SS1M */ +#define SETCOMPRESSION 0x5 /* CCD/VIDEO/SS1M */ +#define SETCOLORLEVEL 0x6 /* CCD/VIDEO */ +#define SETBRIGHTNESS 0x7 /* CCD */ +#define SETROTATION 0x8 /* CCD */ +#define SETTEXT 0x9 /* CCD/VIDEO/SS1M */ +#define SETCLOCK 0xa /* CCD/VIDEO/SS1M */ +#define SETDATE 0xb /* CCD/VIDEO/SS1M */ +#define SETTIMEFORMAT 0xc /* CCD/VIDEO/SS1M */ +#define SETDATEFORMAT 0xd /* VIDEO */ +#define SETTEXTALIGNMENT 0xe /* VIDEO */ +#define SETFPS 0xf /* CCD/VIDEO/SS1M */ +#define SETVGA 0xff /* VIDEO */ +#define SETCOMMENT 0xfe /* CCD/VIDEO */ + +/* get parameters */ + +#define GETDRIVERTYPE 0x10 /* CCD/VIDEO/SS1M */ +#define GETNBROFCAMERAS 0x11 /* CCD/VIDEO/SS1M */ +#define GETPARAMETERS 0x12 /* CCD/VIDEO/SS1M */ +#define GETBUFFERSIZE 0x13 /* CCD/VIDEO/SS1M */ +#define GETVIDEOTYPE 0x14 /* VIDEO/SS1M */ +#define GETVIDEOSIGNAL 0x15 /* VIDEO */ +#define GETMODULATION 0x16 /* VIDEO */ +#define GETDCYVALUES 0xa0 /* CCD /SS1M */ +#define GETDCYWIDTH 0xa1 /* CCD /SS1M */ +#define GETDCYHEIGHT 0xa2 /* CCD /SS1M */ +#define GETSIZE 0xa3 /* CCD/VIDEO */ +#define GETCOMPRESSION 0xa4 /* CCD/VIDEO */ + +/* detect and get parameters */ + +#define DETECTMODULATION 0x17 /* VIDEO */ +#define DETECTVIDEOTYPE 0x18 /* VIDEO */ +#define DETECTVIDEOSIGNAL 0x19 /* VIDEO */ + +/* configure default parameters */ + +#define CONFIGUREDEFAULT 0x20 /* CCD/VIDEO/SS1M */ +#define DEFSIZE 0x21 /* CCD/VIDEO/SS1M */ +#define DEFCOMPRESSION 0x22 /* CCD/VIDEO/SS1M */ +#define DEFCOLORLEVEL 0x23 /* CCD/VIDEO */ +#define DEFBRIGHTNESS 0x24 /* CCD */ +#define DEFROTATION 0x25 /* CCD */ +#define DEFWHITEBALANCE 0x26 /* CCD */ +#define DEFEXPOSURE 0x27 /* CCD */ +#define DEFAUTOEXPWINDOW 0x28 /* CCD */ +#define DEFTEXT 0x29 /* CCD/VIDEO/SS1M */ +#define DEFCLOCK 0x2a /* CCD/VIDEO/SS1M */ +#define DEFDATE 0x2b /* CCD/VIDEO/SS1M */ +#define DEFTIMEFORMAT 0x2c /* CCD/VIDEO/SS1M */ +#define DEFDATEFORMAT 0x2d /* VIDEO */ +#define DEFTEXTALIGNMENT 0x2e /* VIDEO */ +#define DEFFPS 0x2f /* CCD/VIDEO/SS1M */ +#define DEFTEXTSTRING 0x30 /* CCD/VIDEO/SS1M */ +#define DEFHEADERINFO 0x31 /* CCD/VIDEO/SS1M */ +#define DEFWEXAR 0x32 /* CCD */ +#define DEFLINEDELAY 0x33 /* CCD */ +#define DEFDISABLEDVIDEO 0x34 /* VIDEO */ +#define DEFVIDEOTYPE 0x35 /* VIDEO */ +#define DEFMODULATION 0x36 /* VIDEO */ +#define DEFXOFFSET 0x37 /* VIDEO */ +#define DEFYOFFSET 0x38 /* VIDEO */ +#define DEFYCMODE 0x39 /* VIDEO */ +#define DEFVCRMODE 0x3a /* VIDEO */ +#define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */ +#define DEFWCDS 0x3c /* CCD */ +#define DEFVGA 0x3d /* VIDEO */ +#define DEFCOMMENT 0x3e /* CCD/VIDEO */ +#define DEFCOMMENTSIZE 0x3f /* CCD/VIDEO */ +#define DEFCOMMENTTEXT 0x50 /* CCD/VIDEO */ +#define DEFSTOREDCYTEXT 0x51 /* VIDEO */ + + +#define JULABORTDMA 0x70 /* Abort current DMA transfer */ + +/* juliette general i/o port */ + +#define JIO_READBITS 0x40 /* read and return current port bits */ +#define JIO_SETBITS 0x41 /* set bits marked by 1 in the argument */ +#define JIO_CLRBITS 0x42 /* clr bits marked by 1 in the argument */ +#define JIO_READDIR 0x43 /* read direction, 0=input 1=output */ +#define JIO_SETINPUT 0x44 /* set direction, 0=unchanged 1=input + returns current dir */ +#define JIO_SETOUTPUT 0x45 /* set direction, 0=unchanged 1=output + returns current dir */ + +/**** YumYum internal adresses ****/ + +/* Juliette buffer addresses */ + +#define BUFFER1_VIDEO 0x1100 +#define BUFFER2_VIDEO 0x2800 +#define ACDC_BUFF_VIDEO 0x0aaa +#define BUFFER1 0x1700 +#define BUFFER2 0x2b01 +#define ACDC_BUFFER 0x1200 +#define BUFFER1_SS1M 0x1100 +#define BUFFER2_SS1M 0x2800 +#define ACDC_BUFF_SS1M 0x0900 + +/* Juliette parameter memory addresses */ + +#define PA_BUFFER_CNT 0x3f09 /* CCD/VIDEO */ +#define PA_CCD_BUFFER 0x3f10 /* CCD */ +#define PA_VIDEO_BUFFER 0x3f10 /* VIDEO */ +#define PA_DCT_BUFFER 0x3f11 /* CCD/VIDEO */ +#define PA_TEMP 0x3f12 /* CCD/VIDEO */ +#define PA_VIDEOLINE_RD 0x3f13 /* VIDEO */ +#define PA_VIDEOLINE_WR 0x3f14 /* VIDEO */ +#define PA_VI_HDELAY0 0x3f15 /* VIDEO */ +#define PA_VI_VDELAY0 0x3f16 /* VIDEO */ +#define PA_VI_HDELAY1 0x3f17 /* VIDEO */ +#define PA_VI_VDELAY1 0x3f18 /* VIDEO */ +#define PA_VI_HDELAY2 0x3f19 /* VIDEO */ +#define PA_VI_VDELAY2 0x3f1a /* VIDEO */ +#define PA_VI_HDELAY3 0x3f1b /* VIDEO */ +#define PA_VI_VDELAY3 0x3f1c /* VIDEO */ +#define PA_VI_CTRL 0x3f20 /* VIDEO */ +#define PA_JPEG_CTRL 0x3f22 /* CCD/VIDEO */ +#define PA_BUFFER_SIZE 0x3f24 /* CCD/VIDEO */ +#define PA_PAL_NTSC 0x3f25 /* VIDEO */ +#define PA_MACROBLOCKS 0x3f26 /* CCD/VIDEO */ +#define PA_COLOR 0x3f27 /* VIDEO */ +#define PA_MEMCH1CNT2 0x3f28 /* CCD/VIDEO */ +#define PA_MEMCH1CNT3 0x3f29 /* VIDEO */ +#define PA_MEMCH1STR2 0x3f2a /* CCD/VIDEO */ +#define PA_MEMCH1STR3 0x3f2b /* VIDEO */ +#define PA_BUFFERS 0x3f2c /* CCD/VIDEO */ +#define PA_PROGRAM 0x3f2d /* CCD/VIDEO */ +#define PA_ROTATION 0x3f2e /* CCD */ +#define PA_PC 0x3f30 /* CCD/VIDEO */ +#define PA_PC2 0x3f31 /* VIDEO */ +#define PA_ODD_LINE 0x3f32 /* VIDEO */ +#define PA_EXP_DELAY 0x3f34 /* CCD */ +#define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */ +#define PA_DRAM_PTR1_L 0x3f36 /* CCD/VIDEO */ +#define PA_CLPOB_CNT 0x3f37 /* CCD */ +#define PA_DRAM_PTR1_H 0x3f38 /* CCD/VIDEO */ +#define PA_DRAM_PTR2_L 0x3f3a /* VIDEO */ +#define PA_DRAM_PTR2_H 0x3f3c /* VIDEO */ +#define PA_CCD_LINE_CNT 0x3f3f /* CCD */ +#define PA_VIDEO_LINE_CNT 0x3f3f /* VIDEO */ +#define PA_TEXT 0x3f41 /* CCD/VIDEO */ +#define PA_CAMERA_CHANGED 0x3f42 /* VIDEO */ +#define PA_TEXTALIGNMENT 0x3f43 /* VIDEO */ +#define PA_DISABLED 0x3f44 /* VIDEO */ +#define PA_MACROBLOCKTEXT 0x3f45 /* VIDEO */ +#define PA_VGA 0x3f46 /* VIDEO */ +#define PA_ZERO 0x3ffe /* VIDEO */ +#define PA_NULL 0x3fff /* CCD/VIDEO */ + +typedef enum { + jpeg = 0, + dummy = 1 +} request_type; + +typedef enum { + hugesize = 0, + fullsize = 1, + halfsize = 2, + fieldsize = 3 +} size_type; + +typedef enum { + min = 0, + low = 1, + medium = 2, + high = 3, + very_high = 4, + very_low = 5, + q1 = 6, + q2 = 7, + q3 = 8, + q4 = 9, + q5 = 10, + q6 = 11 +} compr_type; + +typedef enum { + deg_0 = 0, + deg_180 = 1, + deg_90 = 2, + deg_270 = 3 +} rotation_type; + +typedef enum { + auto_white = 0, + hold = 1, + fixed_outdoor = 2, + fixed_indoor = 3, + fixed_fluor = 4 +} white_balance_type; + +typedef enum { + auto_exp = 0, + fixed_exp = 1 +} exposure_type; + +typedef enum { + no_window = 0, + center = 1, + top = 2, + lower = 3, + left = 4, + right = 5, + spot = 6, + cw = 7 +} exp_window_type; + +typedef enum { + h_24 = 0, + h_12 = 1, + h_24P = 2 +} hour_type; + +typedef enum { + standard = 0, + YYYY_MM_DD = 1, + Www_Mmm_DD_YYYY = 2, + Www_DD_MM_YYYY = 3 +} date_type; + +typedef enum { + left_align = 0, + center_align = 1, + right_align = 2 +} alignment_type; + +typedef enum { + off = 0, + on = 1, + no = 0, + yes = 1 +} enable_type; + +typedef enum { + disabled = 0, + enabled = 1, + extended = 2 +} comment_type; + +typedef enum { + pal = 0, + ntsc = 1 +} video_type; + +typedef enum { + pal_bghi_ntsc_m = 0, + ntsc_4_43_50hz_pal_4_43_60hz = 1, + pal_n_ntsc_4_43_60hz = 2, + ntsc_n_pal_m = 3, + secam_pal_4_43_60hz = 4 +} modulation_type; + +typedef enum { + cam0 = 0, + cam1 = 1, + cam2 = 2, + cam3 = 3, + quad = 32 +} camera_type; + +typedef enum { + video_driver = 0, + ccd_driver = 1 +} driver_type; + +struct jul_param { + request_type req_type; + size_type size; + compr_type compression; + rotation_type rotation; + int color_level; + int brightness; + white_balance_type white_balance; + exposure_type exposure; + exp_window_type auto_exp_window; + hour_type time_format; + date_type date_format; + alignment_type text_alignment; + enable_type text; + enable_type clock; + enable_type date; + enable_type fps; + enable_type vga; + enable_type comment; +}; + +struct video_param { + enable_type disabled; + modulation_type modulation; + video_type video; + enable_type signal; + enable_type vcr; + int xoffset; + int yoffset; +}; + +/* The juliette_request structure is used during the JULSTARTDMA asynchronous + * picture-taking ioctl call as an argument to specify a buffer which will get + * the final picture. + */ + +struct juliette_request { + char *buf; /* Pointer to the buffer to hold picture data */ + unsigned int buflen; /* Length of the above buffer */ + unsigned int size; /* Resulting length, 0 if the picture is not ready */ +}; + +#endif diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h new file mode 100644 index 000000000000..d29df5644d3e --- /dev/null +++ b/include/asm-cris/arch-v32/memmap.h @@ -0,0 +1,24 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_INTMEM_START (0x38000000) +#define MEM_INTMEM_SIZE (0x00020000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h new file mode 100644 index 000000000000..6bcdc3fdf7dc --- /dev/null +++ b/include/asm-cris/arch-v32/mmu.h @@ -0,0 +1,111 @@ +#ifndef _ASM_CRIS_ARCH_MMU_H +#define _ASM_CRIS_ARCH_MMU_H + +/* MMU context type. */ +typedef struct +{ + unsigned int page_id; +} mm_context_t; + +/* Kernel memory segments. */ +#define KSEG_F 0xf0000000UL +#define KSEG_E 0xe0000000UL +#define KSEG_D 0xd0000000UL +#define KSEG_C 0xc0000000UL +#define KSEG_B 0xb0000000UL +#define KSEG_A 0xa0000000UL +#define KSEG_9 0x90000000UL +#define KSEG_8 0x80000000UL +#define KSEG_7 0x70000000UL +#define KSEG_6 0x60000000UL +#define KSEG_5 0x50000000UL +#define KSEG_4 0x40000000UL +#define KSEG_3 0x30000000UL +#define KSEG_2 0x20000000UL +#define KSEG_1 0x10000000UL +#define KSEG_0 0x00000000UL + +/* + * CRISv32 PTE bits: + * + * Bit: 31-13 12-5 4 3 2 1 0 + * +-----+------+--------+-------+--------+-------+---------+ + * | pfn | zero | global | valid | kernel | write | execute | + * +-----+------+--------+-------+--------+-------+---------+ + */ + +/* + * Defines for accessing the bits. Also define some synonyms for use with + * the software-based defined bits below. + */ +#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ +#define _PAGE_WE (1 << 1) /* Write bit. */ +#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ +#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ +#define _PAGE_VALID (1 << 3) /* Page is valid. */ +#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ +#define _PAGE_GLOBAL (1 << 4) /* Global page. */ + +/* + * The hardware doesn't care about these bits, but the kernel uses them in + * software. + */ +#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ +#define _PAGE_FILE (1 << 6) /* 1=pagecache, 0=swap (when !present) */ +#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ +#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ +#define _PAGE_READ (1 << 8) /* Read enabled. */ +#define _PAGE_WRITE (1 << 9) /* Write enabled. */ + +/* Define some higher level generic page attributes. */ +#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) + +#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED) +#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED | _PAGE_EXECUTE) + +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) + +#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) +#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ + _PAGE_PRESENT | __READABLE) + +#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) + +/* CRISv32 can do page protection for execute. + * Write permissions imply read permissions. + * Note that the numbers are in Execute-Write-Read order! + */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY_EXEC +#define __P101 PAGE_READONLY_EXEC +#define __P110 PAGE_COPY_EXEC +#define __P111 PAGE_COPY_EXEC + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY_EXEC +#define __S101 PAGE_READONLY_EXEC +#define __S110 PAGE_SHARED_EXEC +#define __S111 PAGE_SHARED_EXEC + +#define PTE_FILE_MAX_BITS 25 + +#endif /* _ASM_CRIS_ARCH_MMU_H */ diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h new file mode 100644 index 000000000000..597419b033f9 --- /dev/null +++ b/include/asm-cris/arch-v32/offset.h @@ -0,0 +1,35 @@ +#ifndef __ASM_OFFSETS_H__ +#define __ASM_OFFSETS_H__ +/* + * DO NOT MODIFY. + * + * This file was generated by arch/cris/Makefile + * + */ + +#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ +#define PT_r13 56 /* offsetof(struct pt_regs, r13) */ +#define PT_r12 52 /* offsetof(struct pt_regs, r12) */ +#define PT_r11 48 /* offsetof(struct pt_regs, r11) */ +#define PT_r10 44 /* offsetof(struct pt_regs, r10) */ +#define PT_r9 40 /* offsetof(struct pt_regs, r9) */ +#define PT_acr 60 /* offsetof(struct pt_regs, acr) */ +#define PT_srs 64 /* offsetof(struct pt_regs, srs) */ +#define PT_mof 68 /* offsetof(struct pt_regs, mof) */ +#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ +#define PT_srp 80 /* offsetof(struct pt_regs, srp) */ + +#define TI_task 0 /* offsetof(struct thread_info, task) */ +#define TI_flags 8 /* offsetof(struct thread_info, flags) */ +#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ + +#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ +#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ +#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ + +#define TASK_pid 149 /* offsetof(struct task_struct, pid) */ + +#define LCLONE_VM 256 /* CLONE_VM */ +#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ + +#endif diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h new file mode 100644 index 000000000000..77827bc17cca --- /dev/null +++ b/include/asm-cris/arch-v32/page.h @@ -0,0 +1,28 @@ +#ifndef _ASM_CRIS_ARCH_PAGE_H +#define _ASM_CRIS_ARCH_PAGE_H + +#include <linux/config.h> + +#ifdef __KERNEL__ + +#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ + +/* + * Macros to convert between physical and virtual addresses. By stripiing a + * selected bit it's possible to convert between KSEG_x and 0x40000000 where the + * DRAM really resides. DRAM is virtually at 0xc. + */ +#ifndef CONFIG_ETRAXFS_SIM +#define __pa(x) ((unsigned long)(x) & 0x7fffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) +#else +#define __pa(x) ((unsigned long)(x) & 0x3fffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000)) +#endif + +#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ + VM_MAYREAD | VM_MAYWRITE) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_CRIS_ARCH_PAGE_H */ diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h new file mode 100644 index 000000000000..08cb7ff7e4e7 --- /dev/null +++ b/include/asm-cris/arch-v32/pgtable.h @@ -0,0 +1,9 @@ +#ifndef _ASM_CRIS_ARCH_PGTABLE_H +#define _ASM_CRIS_ARCH_PGTABLE_H + +/* Define the kernels virtual memory area. */ +#define VMALLOC_START KSEG_D +#define VMALLOC_END KSEG_E +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) + +#endif /* _ASM_CRIS_ARCH_PGTABLE_H */ diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h new file mode 100644 index 000000000000..a66dc9970919 --- /dev/null +++ b/include/asm-cris/arch-v32/pinmux.h @@ -0,0 +1,39 @@ +#ifndef _ASM_CRIS_ARCH_PINMUX_H +#define _ASM_CRIS_ARCH_PINMUX_H + +#define PORT_B 0 +#define PORT_C 1 +#define PORT_D 2 +#define PORT_E 3 + +enum pin_mode +{ + pinmux_none = 0, + pinmux_fixed, + pinmux_gpio, + pinmux_iop +}; + +enum fixed_function +{ + pinmux_ser1, + pinmux_ser2, + pinmux_ser3, + pinmux_sser0, + pinmux_sser1, + pinmux_ata0, + pinmux_ata1, + pinmux_ata2, + pinmux_ata3, + pinmux_ata, + pinmux_eth1, + pinmux_timer +}; + +int crisv32_pinmux_init(void); +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); +int crisv32_pinmux_alloc_fixed(enum fixed_function function); +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +void crisv32_pinmux_dump(void); + +#endif diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h new file mode 100644 index 000000000000..8c939bf27987 --- /dev/null +++ b/include/asm-cris/arch-v32/processor.h @@ -0,0 +1,60 @@ +#ifndef _ASM_CRIS_ARCH_PROCESSOR_H +#define _ASM_CRIS_ARCH_PROCESSOR_H + +#include <linux/config.h> + +/* Return current instruction pointer. */ +#define current_text_addr() \ + ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) + +/* + * Since CRIS doesn't do hardware task-switching this hasn't really anything to + * do with the proccessor itself, it's just here for legacy reasons. This is + * used when task-switching using _resume defined in entry.S. The offsets here + * are hardcoded into _resume, so if this struct is changed, entry.S needs to be + * changed as well. + */ +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer. */ + unsigned long usp; /* User stack pointer. */ + unsigned long ccs; /* Saved flags register. */ +}; + +/* + * User-space process size. This is hardcoded into a few places, so don't + * changed it unless everything's clear! + */ +#ifndef CONFIG_ETRAXFS_SIM +#define TASK_SIZE (0xB0000000UL) +#else +#define TASK_SIZE (0xA0000000UL) +#endif + +/* CCS I=1, enable interrupts. */ +#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) } + +#define KSTK_EIP(tsk) \ +({ \ + unsigned long eip = 0; \ + unsigned long regs = (unsigned long)user_regs(tsk); \ + if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ + eip = ((struct pt_regs *)regs)->erp; \ + eip; \ +}) + +/* + * Give the thread a program location, set user-mode and switch user + * stackpointer. + */ +#define start_thread(regs, ip, usp) \ +do { \ + set_fs(USER_DS); \ + regs->erp = ip; \ + regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ + wrusp(usp); \ +} while(0) + +/* Nothing special to do for v32 when handling a kernel bus fault fixup. */ +#define arch_fixup(regs) {}; + +#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h new file mode 100644 index 000000000000..516cc7062d94 --- /dev/null +++ b/include/asm-cris/arch-v32/ptrace.h @@ -0,0 +1,114 @@ +#ifndef _CRIS_ARCH_PTRACE_H +#define _CRIS_ARCH_PTRACE_H + +/* Register numbers in the ptrace system call interface */ + +#define PT_ORIG_R10 0 +#define PT_R0 1 +#define PT_R1 2 +#define PT_R2 3 +#define PT_R3 4 +#define PT_R4 5 +#define PT_R5 6 +#define PT_R6 7 +#define PT_R7 8 +#define PT_R8 9 +#define PT_R9 10 +#define PT_R10 11 +#define PT_R11 12 +#define PT_R12 13 +#define PT_R13 14 +#define PT_ACR 15 +#define PT_SRS 16 +#define PT_MOF 17 +#define PT_SPC 18 +#define PT_CCS 19 +#define PT_SRP 20 +#define PT_ERP 21 /* This is actually the debugged process' PC */ +#define PT_EXS 22 +#define PT_EDA 23 +#define PT_USP 24 /* special case - USP is not in the pt_regs */ +#define PT_PPC 25 /* special case - pseudo PC */ +#define PT_BP 26 /* Base number for BP registers. */ +#define PT_BP_CTRL 26 /* BP control register. */ +#define PT_MAX 40 + +/* Condition code bit numbers. */ +#define C_CCS_BITNR 0 +#define V_CCS_BITNR 1 +#define Z_CCS_BITNR 2 +#define N_CCS_BITNR 3 +#define X_CCS_BITNR 4 +#define I_CCS_BITNR 5 +#define U_CCS_BITNR 6 +#define P_CCS_BITNR 7 +#define R_CCS_BITNR 8 +#define S_CCS_BITNR 9 +#define M_CCS_BITNR 30 +#define Q_CCS_BITNR 31 +#define CCS_SHIFT 10 /* Shift count for each level in CCS */ + +/* pt_regs not only specifices the format in the user-struct during + * ptrace but is also the frame format used in the kernel prologue/epilogues + * themselves + */ + +struct pt_regs { + unsigned long orig_r10; + /* pushed by movem r13, [sp] in SAVE_ALL. */ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long acr; + unsigned long srs; + unsigned long mof; + unsigned long spc; + unsigned long ccs; + unsigned long srp; + unsigned long erp; /* This is actually the debugged process' PC */ + /* For debugging purposes; saved only when needed. */ + unsigned long exs; + unsigned long eda; +}; + +/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) + * when doing a context-switch. it is used (apart from in resume) when a new + * thread is made and we need to make _resume (which is starting it for the + * first time) realise what is going on. + * + * Actually, the use is very close to the thread struct (TSS) in that both the + * switch_stack and the TSS are used to keep thread stuff when switching in + * _resume. + */ + +struct switch_stack { + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long return_ip; /* ip that _resume will return to */ +}; + +#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) +#define instruction_pointer(regs) ((regs)->erp) +extern void show_regs(struct pt_regs *); +#define profile_pc(regs) instruction_pointer(regs) + +#endif diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h new file mode 100644 index 000000000000..52df72a62232 --- /dev/null +++ b/include/asm-cris/arch-v32/spinlock.h @@ -0,0 +1,163 @@ +#ifndef __ASM_ARCH_SPINLOCK_H +#define __ASM_ARCH_SPINLOCK_H + +#include <asm/system.h> + +#define RW_LOCK_BIAS 0x01000000 +#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } +#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) + +#define spin_is_locked(x) (*(volatile signed char *)(&(x)->lock) <= 0) +#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) + +extern void cris_spin_unlock(void *l, int val); +extern void cris_spin_lock(void *l); +extern int cris_spin_trylock(void* l); + +static inline void _raw_spin_unlock(spinlock_t *lock) +{ + __asm__ volatile ("move.d %1,%0" \ + : "=m" (lock->lock) \ + : "r" (1) \ + : "memory"); +} + +static inline int _raw_spin_trylock(spinlock_t *lock) +{ + return cris_spin_trylock((void*)&lock->lock); +} + +static inline void _raw_spin_lock(spinlock_t *lock) +{ + cris_spin_lock((void*)&lock->lock); +} + +static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags) +{ + _raw_spin_lock(lock); +} + +/* + * Read-write spinlocks, allowing multiple readers + * but only one writer. + * + * NOTE! it is quite common to have readers in interrupts + * but no interrupt writers. For those circumstances we + * can "mix" irq-safe locks - any writer needs to get a + * irq-safe write-lock, but readers can get non-irqsafe + * read-locks. + */ +typedef struct { + spinlock_t lock; + volatile int counter; +#ifdef CONFIG_PREEMPT + unsigned int break_lock; +#endif +} rwlock_t; + +#define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 } + +#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while (0) + +/** + * read_can_lock - would read_trylock() succeed? + * @lock: the rwlock in question. + */ +#define read_can_lock(x) ((int)(x)->counter >= 0) + +/** + * write_can_lock - would write_trylock() succeed? + * @lock: the rwlock in question. + */ +#define write_can_lock(x) ((x)->counter == 0) + +#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) + +/* read_lock, read_unlock are pretty straightforward. Of course it somehow + * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */ + +static __inline__ void _raw_read_lock(rwlock_t *rw) +{ + unsigned long flags; + local_irq_save(flags); + _raw_spin_lock(&rw->lock); + + rw->counter++; + + _raw_spin_unlock(&rw->lock); + local_irq_restore(flags); +} + +static __inline__ void _raw_read_unlock(rwlock_t *rw) +{ + unsigned long flags; + local_irq_save(flags); + _raw_spin_lock(&rw->lock); + + rw->counter--; + + _raw_spin_unlock(&rw->lock); + local_irq_restore(flags); +} + +/* write_lock is less trivial. We optimistically grab the lock and check + * if we surprised any readers. If so we release the lock and wait till + * they're all gone before trying again + * + * Also note that we don't use the _irqsave / _irqrestore suffixes here. + * If we're called with interrupts enabled and we've got readers (or other + * writers) in interrupt handlers someone fucked up and we'd dead-lock + * sooner or later anyway. prumpf */ + +static __inline__ void _raw_write_lock(rwlock_t *rw) +{ +retry: + _raw_spin_lock(&rw->lock); + + if(rw->counter != 0) { + /* this basically never happens */ + _raw_spin_unlock(&rw->lock); + + while(rw->counter != 0); + + goto retry; + } + + /* got it. now leave without unlocking */ + rw->counter = -1; /* remember we are locked */ +} + +/* write_unlock is absolutely trivial - we don't have to wait for anything */ + +static __inline__ void _raw_write_unlock(rwlock_t *rw) +{ + rw->counter = 0; + _raw_spin_unlock(&rw->lock); +} + +static __inline__ int _raw_write_trylock(rwlock_t *rw) +{ + _raw_spin_lock(&rw->lock); + if (rw->counter != 0) { + /* this basically never happens */ + _raw_spin_unlock(&rw->lock); + + return 0; + } + + /* got it. now leave without unlocking */ + rw->counter = -1; /* remember we are locked */ + return 1; +} + +static __inline__ int is_read_locked(rwlock_t *rw) +{ + return rw->counter > 0; +} + +static __inline__ int is_write_locked(rwlock_t *rw) +{ + return rw->counter < 0; +} + +#endif /* __ASM_ARCH_SPINLOCK_H */ diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h new file mode 100644 index 000000000000..b9afbb95e0bb --- /dev/null +++ b/include/asm-cris/arch-v32/system.h @@ -0,0 +1,79 @@ +#ifndef _ASM_CRIS_ARCH_SYSTEM_H +#define _ASM_CRIS_ARCH_SYSTEM_H + +#include <linux/config.h> + +/* Read the CPU version register. */ +extern inline unsigned long rdvr(void) +{ + unsigned char vr; + + __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); + return vr; +} + +#define cris_machine_name "crisv32" + +/* Read the user-mode stack pointer. */ +extern inline unsigned long rdusp(void) +{ + unsigned long usp; + + __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); + return usp; +} + +/* Read the current stack pointer. */ +extern inline unsigned long rdsp(void) +{ + unsigned long sp; + + __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); + return sp; +} + +/* Write the user-mode stack pointer. */ +#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) + +#define nop() __asm__ __volatile__ ("nop"); + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr)))) + +#define tas(ptr) (xchg((ptr),1)) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* Used for interrupt control. */ +#define local_save_flags(x) \ + __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory"); + +#define local_irq_restore(x) \ + __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory"); + +#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory"); +#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory"); + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + \ + local_save_flags(flags);\ + !(flags & (1 << I_CCS_BITNR)); \ +}) + +/* Used for spinlocks, etc. */ +#define local_irq_save(x) \ + __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); + +#ifdef CONFIG_SMP +typedef struct { + volatile unsigned int lock __attribute__ ((aligned(4))); +#ifdef CONFIG_PREEMPT + unsigned int break_lock; +#endif +} spinlock_t; +#endif + +#endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h new file mode 100644 index 000000000000..a7a182307da0 --- /dev/null +++ b/include/asm-cris/arch-v32/thread_info.h @@ -0,0 +1,13 @@ +#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H +#define _ASM_CRIS_ARCH_THREAD_INFO_H + +/* Return a thread_info struct. */ +extern inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + + __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); + return ti; +} + +#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h new file mode 100644 index 000000000000..4d0fd23b21e9 --- /dev/null +++ b/include/asm-cris/arch-v32/timex.h @@ -0,0 +1,31 @@ +#ifndef _ASM_CRIS_ARCH_TIMEX_H +#define _ASM_CRIS_ARCH_TIMEX_H + +#include <asm/arch/hwregs/reg_map.h> +#include <asm/arch/hwregs/reg_rdwr.h> +#include <asm/arch/hwregs/timer_defs.h> + +/* + * The clock runs at 100MHz, we divide it by 1000000. If you change anything + * here you must check time.c as well. + */ + +#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ + +/* The timer0 values gives 10 ns resolution but interrupts at HZ. */ +#define TIMER0_FREQ (CLOCK_TICK_RATE) +#define TIMER0_DIV (TIMER0_FREQ/(HZ)) + +/* Convert the value in step of 10 ns to 1us without overflow: */ +#define GET_JIFFIES_USEC() \ + ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 ) + +extern unsigned long get_ns_in_jiffie(void); + +extern inline unsigned long get_us_in_jiffie_highres(void) +{ + return get_ns_in_jiffie() / 1000; +} + +#endif + diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h new file mode 100644 index 000000000000..4effb1253660 --- /dev/null +++ b/include/asm-cris/arch-v32/tlb.h @@ -0,0 +1,14 @@ +#ifndef _CRIS_ARCH_TLB_H +#define _CRIS_ARCH_TLB_H + +/* + * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used + * to store the "process" it belongs to (=> fast mm context switch). The + * last page_id is never used so we can make TLB entries that never matches. + */ +#define NUM_TLB_ENTRIES 64 +#define NUM_PAGEID 256 +#define INVALID_PAGEID 255 +#define NO_CONTEXT -1 + +#endif /* _CRIS_ARCH_TLB_H */ diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h new file mode 100644 index 000000000000..055a0bdbe835 --- /dev/null +++ b/include/asm-cris/arch-v32/uaccess.h @@ -0,0 +1,748 @@ +/* + * Authors: Hans-Peter Nilsson (hp@axis.com) + * + */ +#ifndef _CRIS_ARCH_UACCESS_H +#define _CRIS_ARCH_UACCESS_H + +/* + * We don't tell gcc that we are accessing memory, but this is OK + * because we do not write to any memory gcc knows about, so there + * are no aliasing issues. + * + * Note that PC at a fault is the address *at* the faulting + * instruction for CRISv32. + */ +#define __put_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + "2: "op" %1,[%2]\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " nop\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err) \ + : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __put_user_asm_64(x, addr, err) do { \ + int dummy_for_put_user_asm_64_; \ + __asm__ __volatile__( \ + "2: move.d %M2,[%1+]\n" \ + "4: move.d %H2,[%1]\n" \ + "5:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %4,%0\n" \ + " jump 5b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ + : "r" (x), "1" (addr), "g" (-EFAULT), \ + "0" (err)); \ + } while (0) + +/* See comment before __put_user_asm. */ + +#define __get_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + "2: "op" [%2],%1\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " moveq 0,%1\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x) \ + : "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __get_user_asm_64(x, addr, err) do { \ + int dummy_for_get_user_asm_64_; \ + __asm__ __volatile__( \ + "2: move.d [%2+],%M1\n" \ + "4: move.d [%2],%H1\n" \ + "5:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %4,%0\n" \ + " jump 5b\n" \ + " moveq 0,%1\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x), \ + "=b" (dummy_for_get_user_asm_64_) \ + : "2" (addr), "g" (-EFAULT), "0" (err));\ + } while (0) + +/* + * Copy a null terminated string from userspace. + * + * Must return: + * -EFAULT for an exception + * count if we hit the buffer limit + * bytes copied if we hit a null byte + * (without the null byte) + */ +extern inline long +__do_strncpy_from_user(char *dst, const char *src, long count) +{ + long res; + + if (count == 0) + return 0; + + /* + * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. + * So do we. + * + * This code is deduced from: + * + * char tmp2; + * long tmp1, tmp3; + * tmp1 = count; + * while ((*dst++ = (tmp2 = *src++)) != 0 + * && --tmp1) + * ; + * + * res = count - tmp1; + * + * with tweaks. + */ + + __asm__ __volatile__ ( + " move.d %3,%0\n" + "5: move.b [%2+],$acr\n" + "1: beq 2f\n" + " move.b $acr,[%1+]\n" + + " subq 1,%0\n" + "2: bne 1b\n" + " move.b [%2+],$acr\n" + + " sub.d %3,%0\n" + " neg.d %0,%0\n" + "3:\n" + " .section .fixup,\"ax\"\n" + "4: move.d %7,%0\n" + " jump 3b\n" + " nop\n" + + /* The address for a fault at the first move is trivial. + The address for a fault at the second move is that of + the preceding branch insn, since the move insn is in + its delay-slot. That address is also a branch + target. Just so you don't get confused... */ + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 5b,4b\n" + " .dword 2b,4b\n" + " .previous" + : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) + : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) + : "acr"); + + return res; +} + +/* A few copy asms to build up the more complex ones from. + + Note again, a post-increment is performed regardless of whether a bus + fault occurred in that instruction, and PC for a faulted insn is the + address for the insn, or for the preceding branch when in a delay-slot. */ + +#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + COPY \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous\n" \ + : "=b" (to), "=b" (from), "=r" (ret) \ + : "0" (to), "1" (from), "2" (ret) \ + : "acr", "memory") + +#define __asm_copy_from_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + "2: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "3: addq 1,%2\n" \ + " jump 1b\n" \ + " clear.b [%0+]\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + "2: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "3: addq 2,%2\n" \ + " jump 1b\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_3(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, \ + "4: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + "2: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "3: addq 4,%2\n" \ + " jump 1b\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_4(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_5(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + "4: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + COPY \ + "4: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "5: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_7(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, \ + "6: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + COPY \ + "4: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "5: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_8(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_9(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + "6: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + COPY \ + "6: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "7: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_11(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, \ + "8: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + COPY \ + "6: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "7: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_12(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_13(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + "8: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + COPY \ + "8: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "9: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_15(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, \ + "10: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "11: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + COPY \ + "8: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "9: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_16(to, from, ret) \ + __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_16x_cont(to, from, ret, \ + COPY \ + "10: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "11: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_20(to, from, ret) \ + __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_20x_cont(to, from, ret, \ + COPY \ + "12: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "13: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_copy_from_user_24(to, from, ret) \ + __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") + +/* And now, the to-user ones. */ + +#define __asm_copy_to_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "2: move.b $acr,[%0+]\n", \ + "3: jump 1b\n" \ + " addq 1,%2\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "2: move.w $acr,[%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 2,%2\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_3(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "4: move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "2: move.d $acr,[%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 4,%2\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_4(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_5(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "4: move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "4: move.w $acr,[%0+]\n", \ + FIXUP \ + "5: addq 2,%2\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_7(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "6: move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "4: move.d $acr,[%0+]\n", \ + FIXUP \ + "5: addq 4,%2\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_8(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_9(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "6: move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "6: move.w $acr,[%0+]\n", \ + FIXUP \ + "7: addq 2,%2\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_11(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "8: move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "6: move.d $acr,[%0+]\n", \ + FIXUP \ + "7: addq 4,%2\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_12(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_13(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "8: move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "8: move.w $acr,[%0+]\n", \ + FIXUP \ + "9: addq 2,%2\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_15(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "10: move.b $acr,[%0+]\n", \ + "11: addq 1,%2\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "8: move.d $acr,[%0+]\n", \ + FIXUP \ + "9: addq 4,%2\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_16(to, from, ret) \ + __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_16x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "10: move.d $acr,[%0+]\n", \ + FIXUP \ + "11: addq 4,%2\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_20(to, from, ret) \ + __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_20x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "12: move.d $acr,[%0+]\n", \ + FIXUP \ + "13: addq 4,%2\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_copy_to_user_24(to, from, ret) \ + __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") + +/* Define a few clearing asms with exception handlers. */ + +/* This frame-asm is like the __asm_copy_user_cont one, but has one less + input. */ + +#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + CLEAR \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous" \ + : "=b" (to), "=r" (ret) \ + : "0" (to), "1" (ret) \ + : "memory") + +#define __asm_clear_1(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.b [%0+]\n", \ + "3: jump 1b\n" \ + " addq 1,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_2(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.w [%0+]\n", \ + "3: jump 1b\n" \ + " addq 2,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_3(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.w [%0+]\n" \ + "3: clear.b [%0+]\n", \ + "4: addq 2,%1\n" \ + "5: jump 1b\n" \ + " addq 1,%1\n", \ + " .dword 2b,4b\n" \ + " .dword 3b,5b\n") + +#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear(to, ret, \ + CLEAR \ + "2: clear.d [%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 4,%1\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_clear_4(to, ret) \ + __asm_clear_4x_cont(to, ret, "", "", "") + +#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_4x_cont(to, ret, \ + CLEAR \ + "4: clear.d [%0+]\n", \ + FIXUP \ + "5: addq 4,%1\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_clear_8(to, ret) \ + __asm_clear_8x_cont(to, ret, "", "", "") + +#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_8x_cont(to, ret, \ + CLEAR \ + "6: clear.d [%0+]\n", \ + FIXUP \ + "7: addq 4,%1\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_clear_12(to, ret) \ + __asm_clear_12x_cont(to, ret, "", "", "") + +#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_12x_cont(to, ret, \ + CLEAR \ + "8: clear.d [%0+]\n", \ + FIXUP \ + "9: addq 4,%1\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_clear_16(to, ret) \ + __asm_clear_16x_cont(to, ret, "", "", "") + +#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_16x_cont(to, ret, \ + CLEAR \ + "10: clear.d [%0+]\n", \ + FIXUP \ + "11: addq 4,%1\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_clear_20(to, ret) \ + __asm_clear_20x_cont(to, ret, "", "", "") + +#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_20x_cont(to, ret, \ + CLEAR \ + "12: clear.d [%0+]\n", \ + FIXUP \ + "13: addq 4,%1\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_clear_24(to, ret) \ + __asm_clear_24x_cont(to, ret, "", "", "") + +/* + * Return the size of a string (including the ending 0) + * + * Return length of string in userspace including terminating 0 + * or 0 for error. Return a value greater than N if too long. + */ + +extern inline long +strnlen_user(const char *s, long n) +{ + long res, tmp1; + + if (!access_ok(VERIFY_READ, s, 0)) + return 0; + + /* + * This code is deduced from: + * + * tmp1 = n; + * while (tmp1-- > 0 && *s++) + * ; + * + * res = n - tmp1; + * + * (with tweaks). + */ + + __asm__ __volatile__ ( + " move.d %1,$acr\n" + " cmpq 0,$acr\n" + "0:\n" + " ble 1f\n" + " subq 1,$acr\n" + + "4: test.b [%0+]\n" + " bne 0b\n" + " cmpq 0,$acr\n" + "1:\n" + " move.d %1,%0\n" + " sub.d $acr,%0\n" + "2:\n" + " .section .fixup,\"ax\"\n" + + "3: jump 2b\n" + " clear.d %0\n" + + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 4b,3b\n" + " .previous\n" + : "=r" (res), "=r" (tmp1) + : "0" (s), "1" (n) + : "acr"); + + return res; +} + +#endif diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h new file mode 100644 index 000000000000..5d369d4439d9 --- /dev/null +++ b/include/asm-cris/arch-v32/unistd.h @@ -0,0 +1,148 @@ +#ifndef _ASM_CRIS_ARCH_UNISTD_H_ +#define _ASM_CRIS_ARCH_UNISTD_H_ + +/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ +/* + * Don't remove the .ifnc tests; they are an insurance against + * any hard-to-spot gcc register allocation bugs. + */ +#define _syscall0(type,name) \ +type name(void) \ +{ \ + register long __a __asm__ ("r10"); \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall1(type,name,type1,arg1) \ +type name(type1 arg1) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall2(type,name,type1,arg1,type2,arg2) \ +type name(type1 arg1,type2 arg2) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ +type name(type1 arg1,type2 arg2,type3 arg3) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __e __asm__ ("mof") = (long) arg5; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "h" (__e)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5,type6,arg6) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __e __asm__ ("mof") = (long) arg5; \ + register long __f __asm__ ("srp") = (long) arg6; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#endif diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h new file mode 100644 index 000000000000..03fa1f3c3c00 --- /dev/null +++ b/include/asm-cris/arch-v32/user.h @@ -0,0 +1,41 @@ +#ifndef _ASM_CRIS_ARCH_USER_H +#define _ASM_CRIS_ARCH_USER_H + +/* User-mode register used for core dumps. */ + +struct user_regs_struct { + unsigned long r0; /* General registers. */ + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long sp; /* R14, Stack pointer. */ + unsigned long acr; /* R15, Address calculation register. */ + unsigned long bz; /* P0, Constant zero (8-bits). */ + unsigned long vr; /* P1, Version register (8-bits). */ + unsigned long pid; /* P2, Process ID (8-bits). */ + unsigned long srs; /* P3, Support register select (8-bits). */ + unsigned long wz; /* P4, Constant zero (16-bits). */ + unsigned long exs; /* P5, Exception status. */ + unsigned long eda; /* P6, Exception data address. */ + unsigned long mof; /* P7, Multiply overflow regiter. */ + unsigned long dz; /* P8, Constant zero (32-bits). */ + unsigned long ebp; /* P9, Exception base pointer. */ + unsigned long erp; /* P10, Exception return pointer. */ + unsigned long srp; /* P11, Subroutine return pointer. */ + unsigned long nrp; /* P12, NMI return pointer. */ + unsigned long ccs; /* P13, Condition code stack. */ + unsigned long usp; /* P14, User mode stack pointer. */ + unsigned long spc; /* P15, Single step PC. */ +}; + +#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h index b3dfea5a71e4..70605b09e8b7 100644 --- a/include/asm-cris/atomic.h +++ b/include/asm-cris/atomic.h @@ -4,21 +4,14 @@ #define __ASM_CRIS_ATOMIC__ #include <asm/system.h> +#include <asm/arch/atomic.h> /* * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. */ -/* - * Make sure gcc doesn't try to be clever and move things around - * on us. We need to use _exactly_ the address the user gave us, - * not some alias that contains the same information. - */ - -#define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x) - -typedef struct { int counter; } atomic_t; +typedef struct { volatile int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } @@ -30,29 +23,26 @@ typedef struct { int counter; } atomic_t; extern __inline__ void atomic_add(int i, volatile atomic_t *v) { unsigned long flags; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); v->counter += i; - local_irq_restore(flags); + cris_atomic_restore(v, flags); } extern __inline__ void atomic_sub(int i, volatile atomic_t *v) { unsigned long flags; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); v->counter -= i; - local_irq_restore(flags); + cris_atomic_restore(v, flags); } extern __inline__ int atomic_add_return(int i, volatile atomic_t *v) { unsigned long flags; int retval; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); retval = (v->counter += i); - local_irq_restore(flags); + cris_atomic_restore(v, flags); return retval; } @@ -62,10 +52,9 @@ extern __inline__ int atomic_sub_return(int i, volatile atomic_t *v) { unsigned long flags; int retval; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); retval = (v->counter -= i); - local_irq_restore(flags); + cris_atomic_restore(v, flags); return retval; } @@ -73,39 +62,35 @@ extern __inline__ int atomic_sub_and_test(int i, volatile atomic_t *v) { int retval; unsigned long flags; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); retval = (v->counter -= i) == 0; - local_irq_restore(flags); + cris_atomic_restore(v, flags); return retval; } extern __inline__ void atomic_inc(volatile atomic_t *v) { unsigned long flags; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); (v->counter)++; - local_irq_restore(flags); + cris_atomic_restore(v, flags); } extern __inline__ void atomic_dec(volatile atomic_t *v) { unsigned long flags; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); (v->counter)--; - local_irq_restore(flags); + cris_atomic_restore(v, flags); } extern __inline__ int atomic_inc_return(volatile atomic_t *v) { unsigned long flags; int retval; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); retval = (v->counter)++; - local_irq_restore(flags); + cris_atomic_restore(v, flags); return retval; } @@ -113,20 +98,18 @@ extern __inline__ int atomic_dec_return(volatile atomic_t *v) { unsigned long flags; int retval; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); retval = (v->counter)--; - local_irq_restore(flags); + cris_atomic_restore(v, flags); return retval; } extern __inline__ int atomic_dec_and_test(volatile atomic_t *v) { int retval; unsigned long flags; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); retval = --(v->counter) == 0; - local_irq_restore(flags); + cris_atomic_restore(v, flags); return retval; } @@ -134,10 +117,9 @@ extern __inline__ int atomic_inc_and_test(volatile atomic_t *v) { int retval; unsigned long flags; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(v, flags); retval = ++(v->counter) == 0; - local_irq_restore(flags); + cris_atomic_restore(v, flags); return retval; } diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h index 600bb8715d89..7a8d3114e682 100644 --- a/include/asm-cris/axisflashmap.h +++ b/include/asm-cris/axisflashmap.h @@ -40,4 +40,7 @@ struct partitiontable_entry { #define PARTITION_TYPE_KERNEL 0x0002 #define PARTITION_TYPE_JFFS 0x0003 +/* The master mtd for the entire flash. */ +extern struct mtd_info* axisflash_mtd; + #endif diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h index d7861115d731..e3da57f97964 100644 --- a/include/asm-cris/bitops.h +++ b/include/asm-cris/bitops.h @@ -16,6 +16,7 @@ #include <asm/arch/bitops.h> #include <asm/system.h> +#include <asm/atomic.h> #include <linux/compiler.h> /* @@ -88,7 +89,7 @@ struct __dummy { unsigned long a[100]; }; * It also implies a memory barrier. */ -extern inline int test_and_set_bit(int nr, void *addr) +extern inline int test_and_set_bit(int nr, volatile unsigned long *addr) { unsigned int mask, retval; unsigned long flags; @@ -96,15 +97,15 @@ extern inline int test_and_set_bit(int nr, void *addr) adr += nr >> 5; mask = 1 << (nr & 0x1f); - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(addr, flags); retval = (mask & *adr) != 0; *adr |= mask; + cris_atomic_restore(addr, flags); local_irq_restore(flags); return retval; } -extern inline int __test_and_set_bit(int nr, void *addr) +extern inline int __test_and_set_bit(int nr, volatile unsigned long *addr) { unsigned int mask, retval; unsigned int *adr = (unsigned int *)addr; @@ -131,7 +132,7 @@ extern inline int __test_and_set_bit(int nr, void *addr) * It also implies a memory barrier. */ -extern inline int test_and_clear_bit(int nr, void *addr) +extern inline int test_and_clear_bit(int nr, volatile unsigned long *addr) { unsigned int mask, retval; unsigned long flags; @@ -139,11 +140,10 @@ extern inline int test_and_clear_bit(int nr, void *addr) adr += nr >> 5; mask = 1 << (nr & 0x1f); - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(addr, flags); retval = (mask & *adr) != 0; *adr &= ~mask; - local_irq_restore(flags); + cris_atomic_restore(addr, flags); return retval; } @@ -157,7 +157,7 @@ extern inline int test_and_clear_bit(int nr, void *addr) * but actually fail. You must protect multiple accesses with a lock. */ -extern inline int __test_and_clear_bit(int nr, void *addr) +extern inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) { unsigned int mask, retval; unsigned int *adr = (unsigned int *)addr; @@ -177,24 +177,23 @@ extern inline int __test_and_clear_bit(int nr, void *addr) * It also implies a memory barrier. */ -extern inline int test_and_change_bit(int nr, void *addr) +extern inline int test_and_change_bit(int nr, volatile unsigned long *addr) { unsigned int mask, retval; unsigned long flags; unsigned int *adr = (unsigned int *)addr; adr += nr >> 5; mask = 1 << (nr & 0x1f); - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(addr, flags); retval = (mask & *adr) != 0; *adr ^= mask; - local_irq_restore(flags); + cris_atomic_restore(addr, flags); return retval; } /* WARNING: non atomic and it can be reordered! */ -extern inline int __test_and_change_bit(int nr, void *addr) +extern inline int __test_and_change_bit(int nr, volatile unsigned long *addr) { unsigned int mask, retval; unsigned int *adr = (unsigned int *)addr; @@ -215,7 +214,7 @@ extern inline int __test_and_change_bit(int nr, void *addr) * This routine doesn't need to be atomic. */ -extern inline int test_bit(int nr, const void *addr) +extern inline int test_bit(int nr, const volatile unsigned long *addr) { unsigned int mask; unsigned int *adr = (unsigned int *)addr; @@ -259,7 +258,7 @@ extern inline int test_bit(int nr, const void *addr) * @offset: The bitnumber to start searching at * @size: The maximum size to search */ -extern inline int find_next_zero_bit (void * addr, int size, int offset) +extern inline int find_next_zero_bit (const unsigned long * addr, int size, int offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; @@ -301,7 +300,7 @@ extern inline int find_next_zero_bit (void * addr, int size, int offset) * @offset: The bitnumber to start searching at * @size: The maximum size to search */ -static __inline__ int find_next_bit(void *addr, int size, int offset) +static __inline__ int find_next_bit(const unsigned long *addr, int size, int offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; @@ -367,7 +366,7 @@ found_middle: #define minix_test_bit(nr,addr) test_bit(nr,addr) #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) -extern inline int sched_find_first_bit(unsigned long *b) +extern inline int sched_find_first_bit(const unsigned long *b) { if (unlikely(b[0])) return __ffs(b[0]); diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h index 0d770f60127a..0b5c3fdaefe1 100644 --- a/include/asm-cris/dma-mapping.h +++ b/include/asm-cris/dma-mapping.h @@ -1,125 +1,179 @@ +/* DMA mapping. Nothing tricky here, just virt_to_phys */ + #ifndef _ASM_CRIS_DMA_MAPPING_H #define _ASM_CRIS_DMA_MAPPING_H -#include "scatterlist.h" +#include <linux/mm.h> +#include <linux/kernel.h> -static inline int -dma_supported(struct device *dev, u64 mask) -{ - BUG(); - return 0; -} +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/scatterlist.h> -static inline int -dma_set_mask(struct device *dev, u64 dma_mask) -{ - BUG(); - return 1; -} +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) + +#ifdef CONFIG_PCI +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, int flag); +void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); +#else static inline void * dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - int flag) + int flag) { - BUG(); - return NULL; + BUG(); + return NULL; } static inline void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, - dma_addr_t dma_handle) + dma_addr_t dma_handle) { - BUG(); + BUG(); } - +#endif static inline dma_addr_t -dma_map_single(struct device *dev, void *cpu_addr, size_t size, +dma_map_single(struct device *dev, void *ptr, size_t size, enum dma_data_direction direction) { - BUG(); - return 0; + BUG_ON(direction == DMA_NONE); + return virt_to_phys(ptr); } static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction) { - BUG(); + BUG_ON(direction == DMA_NONE); +} + +static inline int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + printk("Map sg\n"); + return nents; } static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction direction) +dma_map_page(struct device *dev, struct page *page, unsigned long offset, + size_t size, enum dma_data_direction direction) { - BUG(); - return 0; + BUG_ON(direction == DMA_NONE); + return page_to_phys(page) + offset; } static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, enum dma_data_direction direction) { - BUG(); + BUG_ON(direction == DMA_NONE); } -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) -{ - BUG(); - return 1; -} static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction) { - BUG(); + BUG_ON(direction == DMA_NONE); } static inline void -dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) { - BUG(); } static inline void -dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) +dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) { - BUG(); } -/* Now for the API extensions over the pci_ one */ +static inline void +dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ +} -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) -#define dma_is_consistent(d) (1) +static inline void +dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ +} -static inline int -dma_get_cache_alignment(void) +static inline void +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) { - /* no easy way to get cache size on all processors, so return - * the maximum possible, to be safe */ - return (1 << L1_CACHE_SHIFT_MAX); } static inline void -dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) +dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) { - BUG(); } +static inline int +dma_mapping_error(dma_addr_t dma_addr) +{ + return 0; +} + +static inline int +dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if(mask < 0x00ffffff) + return 0; + + return 1; +} + +static inline int +dma_set_mask(struct device *dev, u64 mask) +{ + if(!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + + *dev->dma_mask = mask; + + return 0; +} + +static inline int +dma_get_cache_alignment(void) +{ + return (1 << L1_CACHE_SHIFT_MAX); +} + +#define dma_is_consistent(d) (1) + static inline void dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction direction) { - BUG(); } -#endif +#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY +extern int +dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, + dma_addr_t device_addr, size_t size, int flags); + +extern void +dma_release_declared_memory(struct device *dev); +extern void * +dma_mark_declared_memory_occupied(struct device *dev, + dma_addr_t device_addr, size_t size); + +#endif diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h index c229fac35cdc..6f188dc56138 100644 --- a/include/asm-cris/dma.h +++ b/include/asm-cris/dma.h @@ -10,4 +10,12 @@ #define MAX_DMA_ADDRESS PAGE_OFFSET +/* From PCI */ + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) +#endif + #endif /* _ASM_DMA_H */ diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h index d37fd5c4a567..87a60bd8e667 100644 --- a/include/asm-cris/elf.h +++ b/include/asm-cris/elf.h @@ -8,6 +8,27 @@ #include <asm/arch/elf.h> #include <asm/user.h> +#define R_CRIS_NONE 0 +#define R_CRIS_8 1 +#define R_CRIS_16 2 +#define R_CRIS_32 3 +#define R_CRIS_8_PCREL 4 +#define R_CRIS_16_PCREL 5 +#define R_CRIS_32_PCREL 6 +#define R_CRIS_GNU_VTINHERIT 7 +#define R_CRIS_GNU_VTENTRY 8 +#define R_CRIS_COPY 9 +#define R_CRIS_GLOB_DAT 10 +#define R_CRIS_JUMP_SLOT 11 +#define R_CRIS_RELATIVE 12 +#define R_CRIS_16_GOT 13 +#define R_CRIS_32_GOT 14 +#define R_CRIS_16_GOTPLT 15 +#define R_CRIS_32_GOTPLT 16 +#define R_CRIS_32_GOTREL 17 +#define R_CRIS_32_PLT_GOTREL 18 +#define R_CRIS_32_PLT_PCREL 19 + typedef unsigned long elf_greg_t; /* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is @@ -19,17 +40,29 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef unsigned long elf_fpregset_t; /* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ( (x)->e_machine == EM_CRIS ) - -/* * These are used to set parameters in the core dumps. */ #define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB; +#define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_CRIS +/* The master for these definitions is {binutils}/include/elf/cris.h: */ +/* User symbols in this file have a leading underscore. */ +#define EF_CRIS_UNDERSCORE 0x00000001 + +/* This is a mask for different incompatible machine variants. */ +#define EF_CRIS_VARIANT_MASK 0x0000000e + +/* Variant 0; may contain v0..10 object. */ +#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 + +/* Variant 1; contains v32 object. */ +#define EF_CRIS_VARIANT_V32 0x00000002 + +/* Variant 2; contains object compatible with v32 and v10. */ +#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 +/* End of excerpt from {binutils}/include/elf/cris.h. */ + #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 8192 diff --git a/include/asm-cris/emergency-restart.h b/include/asm-cris/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-cris/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h index cf04af9635cc..80ee10f70d43 100644 --- a/include/asm-cris/etraxgpio.h +++ b/include/asm-cris/etraxgpio.h @@ -13,7 +13,7 @@ are enabled. * * - * For ETRAX 200 (ARCH_V32): + * For ETRAX FS (ARCH_V32): * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction @@ -39,10 +39,10 @@ #define ETRAXGPIO_IOCTYPE 43 #define GPIO_MINOR_A 0 #define GPIO_MINOR_B 1 -#define GPIO_MINOR_C 2 -#define GPIO_MINOR_D 3 -#define GPIO_MINOR_E 4 -#define GPIO_MINOR_LEDS 5 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#define GPIO_MINOR_E 5 #define GPIO_MINOR_LAST 5 #endif diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h index f4d136228ee1..1c13dd3faac3 100644 --- a/include/asm-cris/hardirq.h +++ b/include/asm-cris/hardirq.h @@ -1,18 +1,17 @@ #ifndef __ASM_HARDIRQ_H #define __ASM_HARDIRQ_H -/* only non-SMP supported */ - #include <linux/threads.h> #include <linux/cache.h> -/* entry.S is sensitive to the offsets of these fields */ typedef struct { unsigned int __softirq_pending; } ____cacheline_aligned irq_cpustat_t; #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ +void ack_bad_irq(unsigned int irq); + #define HARDIRQ_BITS 8 /* diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h new file mode 100644 index 000000000000..341536a234e9 --- /dev/null +++ b/include/asm-cris/hw_irq.h @@ -0,0 +1,7 @@ +#ifndef _ASM_HW_IRQ_H +#define _ASM_HW_IRQ_H + +static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {} + +#endif + diff --git a/include/asm-cris/ide.h b/include/asm-cris/ide.h new file mode 100644 index 000000000000..a894f66665f8 --- /dev/null +++ b/include/asm-cris/ide.h @@ -0,0 +1 @@ +#include <asm/arch/ide.h> diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h index 1d2b51701e8d..16e791b3c721 100644 --- a/include/asm-cris/io.h +++ b/include/asm-cris/io.h @@ -3,6 +3,21 @@ #include <asm/page.h> /* for __va, __pa */ #include <asm/arch/io.h> +#include <linux/kernel.h> + +struct cris_io_operations +{ + u32 (*read_mem)(void *addr, int size); + void (*write_mem)(u32 val, int size, void *addr); + u32 (*read_io)(u32 port, void *addr, int size, int count); + void (*write_io)(u32 port, void *addr, int size, int count); +}; + +#ifdef CONFIG_PCI +extern struct cris_io_operations *cris_iops; +#else +#define cris_iops ((struct cris_io_operations*)NULL) +#endif /* * Change virtual addresses to physical addresses and vv. @@ -18,14 +33,17 @@ extern inline void * phys_to_virt(unsigned long address) return __va(address); } -extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); +extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); +extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); -extern inline void * ioremap (unsigned long offset, unsigned long size) +extern inline void __iomem * ioremap (unsigned long offset, unsigned long size) { return __ioremap(offset, size, 0); } -extern void iounmap(void *addr); +extern void iounmap(volatile void * __iomem addr); + +extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); /* * IO bus memory addresses are also 1:1 with the physical address @@ -39,9 +57,32 @@ extern void iounmap(void *addr); * differently. On the CRIS architecture, we just read/write the * memory location directly. */ -#define readb(addr) (*(volatile unsigned char *) (addr)) -#define readw(addr) (*(volatile unsigned short *) (addr)) -#define readl(addr) (*(volatile unsigned int *) (addr)) +#ifdef CONFIG_PCI +#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000) +#else +#define PCI_SPACE(x) 0 +#endif +static inline unsigned char readb(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 1); + else + return *(volatile unsigned char __force *) addr; +} +static inline unsigned short readw(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 2); + else + return *(volatile unsigned short __force *) addr; +} +static inline unsigned int readl(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 4); + else + return *(volatile unsigned int __force *) addr; +} #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) #define readl_relaxed(addr) readl(addr) @@ -49,9 +90,27 @@ extern void iounmap(void *addr); #define __raw_readw readw #define __raw_readl readl -#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) +static inline void writeb(unsigned char b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 1, (void*)addr); + else + *(volatile unsigned char __force *) addr = b; +} +static inline void writew(unsigned short b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 2, (void*)addr); + else + *(volatile unsigned short __force *) addr = b; +} +static inline void writel(unsigned int b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 4, (void*)addr); + else + *(volatile unsigned int __force *) addr = b; +} #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel @@ -66,25 +125,25 @@ extern void iounmap(void *addr); * Again, CRIS does not require mem IO specific function. */ -#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d)) +#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(b),(c),(d)) /* The following is junk needed for the arch-independent code but which * we never use in the CRIS port */ #define IO_SPACE_LIMIT 0xffff -#define inb(x) (0) -#define inw(x) (0) -#define inl(x) (0) -#define outb(x,y) -#define outw(x,y) -#define outl(x,y) -#define insb(x,y,z) -#define insw(x,y,z) -#define insl(x,y,z) -#define outsb(x,y,z) -#define outsw(x,y,z) -#define outsl(x,y,z) +#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0) +#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0) +#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0) +#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0) +#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0) +#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0) +#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1) +#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1) +#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1) +#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count) +#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count) +#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count) /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h index 87f342517bb1..8e787fdaedd4 100644 --- a/include/asm-cris/irq.h +++ b/include/asm-cris/irq.h @@ -8,16 +8,6 @@ extern __inline__ int irq_canonicalize(int irq) return irq; } -extern void disable_irq(unsigned int); -extern void enable_irq(unsigned int); - -#define disable_irq_nosync disable_irq -#define enable_irq_nosync enable_irq - -struct irqaction; -struct pt_regs; -int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); - #endif /* _ASM_IRQ_H */ diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h index eec0974c2417..492988cb9077 100644 --- a/include/asm-cris/kmap_types.h +++ b/include/asm-cris/kmap_types.h @@ -17,8 +17,8 @@ enum km_type { KM_PTE1, KM_IRQ0, KM_IRQ1, - KM_CRYPTO_USER, - KM_CRYPTO_SOFTIRQ, + KM_SOFTIRQ0, + KM_SOFTIRQ1, KM_TYPE_NR }; diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h index f9308c5bbd99..e6e659dc757b 100644 --- a/include/asm-cris/mmu_context.h +++ b/include/asm-cris/mmu_context.h @@ -15,7 +15,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, * registers like cr3 on the i386 */ -extern volatile pgd_t *current_pgd; /* defined in arch/cris/mm/fault.c */ +extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h index c767da1ef8f5..c99c478c482f 100644 --- a/include/asm-cris/page.h +++ b/include/asm-cris/page.h @@ -29,18 +29,15 @@ */ #ifndef __ASSEMBLY__ typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; #endif #define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) #define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) @@ -73,23 +70,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; #ifndef __ASSEMBLY__ -#define BUG() do { \ - printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ -} while (0) - -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} #endif /* __ASSEMBLY__ */ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ @@ -97,5 +77,7 @@ static inline int get_order(unsigned long size) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _CRIS_PAGE_H */ diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h index c61041531889..2064bc1de074 100644 --- a/include/asm-cris/pci.h +++ b/include/asm-cris/pci.h @@ -1,13 +1,105 @@ #ifndef __ASM_CRIS_PCI_H #define __ASM_CRIS_PCI_H +#include <linux/config.h> + +#ifdef __KERNEL__ +#include <linux/mm.h> /* for struct page */ + +/* Can be used to override the logic in pci_scan_bus for skipping + already-configured bus numbers - to be used for buggy BIOSes + or architectures with incomplete PCI setup by the loader */ + +#define pcibios_assign_all_busses(void) 1 + +extern unsigned long pci_mem_start; +#define PCIBIOS_MIN_IO 0x1000 +#define PCIBIOS_MIN_MEM 0x10000000 + +#define PCIBIOS_MIN_CARDBUS_IO 0x4000 + +void pcibios_config_init(void); +struct pci_bus * pcibios_scan_root(int bus); +int pcibios_assign_resources(void); + +void pcibios_set_master(struct pci_dev *dev); +void pcibios_penalize_isa_irq(int irq); +struct irq_routing_table *pcibios_get_irq_routing_table(void); +int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); + +/* Dynamic DMA mapping stuff. + * i386 has everything mapped statically. + */ + +#include <linux/types.h> +#include <linux/slab.h> #include <asm/scatterlist.h> -#include <asm-generic/pci-dma-compat.h> +#include <linux/string.h> +#include <asm/io.h> -/* ETRAX chips don't have a PCI bus. This file is just here because some stupid .c code - * includes it even if CONFIG_PCI is not set. +struct pci_dev; + +/* The PCI address space does equal the physical memory + * address space. The networking and block device layers use + * this boolean for bounce buffer decisions. */ -#define PCI_DMA_BUS_IS_PHYS (1) +#define PCI_DMA_BUS_IS_PHYS (1) -#endif /* __ASM_CRIS_PCI_H */ +/* pci_unmap_{page,single} is a nop so... */ +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) +#define pci_unmap_addr(PTR, ADDR_NAME) (0) +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) +#define pci_unmap_len(PTR, LEN_NAME) (0) +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) + +/* This is always fine. */ +#define pci_dac_dma_supported(pci_dev, mask) (1) +static inline dma64_addr_t +pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) +{ + return ((dma64_addr_t) page_to_phys(page) + + (dma64_addr_t) offset); +} + +static inline struct page * +pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) +{ + return pfn_to_page(dma_addr >> PAGE_SHIFT); +} + +static inline unsigned long +pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) +{ + return (dma_addr & ~PAGE_MASK); +} + +static inline void +pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) +{ +} + +static inline void +pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) +{ +} + +#define HAVE_PCI_MMAP +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine); + + +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + +#endif /* __KERNEL__ */ + +/* implement the pci_ DMA API in terms of the generic device dma_ one */ +#include <asm-generic/pci-dma-compat.h> + +/* generic pci stuff */ +#include <asm-generic/pci.h> + +#endif /* __ASM_CRIS_PCI_H */ diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h index b202e62ed6e0..a131776edf41 100644 --- a/include/asm-cris/pgalloc.h +++ b/include/asm-cris/pgalloc.h @@ -47,16 +47,6 @@ extern inline void pte_free(struct page *pte) #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) -/* - * We don't have any real pmd's, and this code never triggers because - * the pgd will always be present.. - */ - -#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); }) -#define pmd_free(x) do { } while (0) -#define __pmd_free_tlb(tlb,x) do { } while (0) -#define pgd_populate(mm, pmd, pte) BUG() - #define check_pgt_cache() do { } while (0) #endif diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h index f7042944b073..a9143bed99db 100644 --- a/include/asm-cris/pgtable.h +++ b/include/asm-cris/pgtable.h @@ -5,7 +5,8 @@ #ifndef _CRIS_PGTABLE_H #define _CRIS_PGTABLE_H -#include <asm-generic/4level-fixup.h> +#include <asm/page.h> +#include <asm-generic/pgtable-nopmd.h> #ifndef __ASSEMBLY__ #include <linux/config.h> @@ -41,22 +42,14 @@ extern void paging_init(void); * but the define is needed for a generic inline function.) */ #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) -#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) +#define set_pgu(pudptr, pudval) (*(pudptr) = pudval) -/* PMD_SHIFT determines the size of the area a second-level page table can +/* PGDIR_SHIFT determines the size of the area a second-level page table can * map. It is equal to the page size times the number of PTE's that fit in * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. */ -#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map. - * Since we fold into a two-level structure, this is the same as PMD_SHIFT. - */ - -#define PGDIR_SHIFT PMD_SHIFT +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -67,7 +60,6 @@ extern void paging_init(void); * divide it by 4 (shift by 2). */ #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) -#define PTRS_PER_PMD 1 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) /* calculate how many PGD entries a user-level program can use @@ -105,7 +97,7 @@ extern unsigned long empty_zero_page; #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) -#define pmd_none(x) (!pmd_val(x)) +#define pmd_none(x) (!pmd_val(x)) /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. */ @@ -116,16 +108,6 @@ extern unsigned long empty_zero_page; #ifndef __ASSEMBLY__ /* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) - */ -extern inline int pgd_none(pgd_t pgd) { return 0; } -extern inline int pgd_bad(pgd_t pgd) { return 0; } -extern inline int pgd_present(pgd_t pgd) { return 1; } -extern inline void pgd_clear(pgd_t * pgdp) { } - -/* * The following only work if pte_present() is true. * Undefined behaviour if not.. */ @@ -275,7 +257,7 @@ extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep) #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) /* to find an entry in a page-table-directory. */ -#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) /* to find an entry in a page-table-directory */ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) @@ -286,12 +268,6 @@ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(address) pgd_offset(&init_mm, address) -/* Find an entry in the second-level page table.. */ -extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) -{ - return (pmd_t *) dir; -} - /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) @@ -308,8 +284,6 @@ extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) #define pte_ERROR(e) \ printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) -#define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) @@ -348,5 +322,7 @@ extern inline void update_mmu_cache(struct vm_area_struct * vma, #define pte_to_pgoff(x) (pte_val(x) >> 6) #define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE) +typedef pte_t *pte_addr_t; + #endif /* __ASSEMBLY__ */ #endif /* _CRIS_PGTABLE_H */ diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h index 623bdf06d911..0dc218117bd8 100644 --- a/include/asm-cris/processor.h +++ b/include/asm-cris/processor.h @@ -55,15 +55,6 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) -/* - * Free current thread data structures etc.. - */ - -extern inline void exit_thread(void) -{ - /* Nothing needs to be done. */ -} - extern unsigned long thread_saved_pc(struct task_struct *tsk); /* Free all resources held by a thread. */ diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h index 7a8c2880e487..1ec69a7ea836 100644 --- a/include/asm-cris/ptrace.h +++ b/include/asm-cris/ptrace.h @@ -9,4 +9,6 @@ #define PTRACE_SETREGS 13 #endif +#define profile_pc(regs) instruction_pointer(regs) + #endif /* _CRIS_PTRACE_H */ diff --git a/include/asm-cris/semaphore.h b/include/asm-cris/semaphore.h index 605aa7eaaaf8..8ed7636ab311 100644 --- a/include/asm-cris/semaphore.h +++ b/include/asm-cris/semaphore.h @@ -72,10 +72,9 @@ extern inline void down(struct semaphore * sem) might_sleep(); /* atomically decrement the semaphores count, and if its negative, we wait */ - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(sem, flags); failed = --(sem->count.counter) < 0; - local_irq_restore(flags); + cris_atomic_restore(sem, flags); if(failed) { __down(sem); } @@ -95,10 +94,9 @@ extern inline int down_interruptible(struct semaphore * sem) might_sleep(); /* atomically decrement the semaphores count, and if its negative, we wait */ - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(sem, flags); failed = --(sem->count.counter) < 0; - local_irq_restore(flags); + cris_atomic_restore(sem, flags); if(failed) failed = __down_interruptible(sem); return(failed); @@ -109,13 +107,13 @@ extern inline int down_trylock(struct semaphore * sem) unsigned long flags; int failed; - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(sem, flags); failed = --(sem->count.counter) < 0; - local_irq_restore(flags); + cris_atomic_restore(sem, flags); if(failed) failed = __down_trylock(sem); return(failed); + } /* @@ -130,10 +128,9 @@ extern inline void up(struct semaphore * sem) int wakeup; /* atomically increment the semaphores count, and if it was negative, we wake people */ - local_save_flags(flags); - local_irq_disable(); + cris_atomic_save(sem, flags); wakeup = ++(sem->count.counter) <= 0; - local_irq_restore(flags); + cris_atomic_restore(sem, flags); if(wakeup) { __up(sem); } diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h index c2f4feaa041d..dca5ef1d8c97 100644 --- a/include/asm-cris/smp.h +++ b/include/asm-cris/smp.h @@ -1,4 +1,11 @@ #ifndef __ASM_SMP_H #define __ASM_SMP_H +#include <linux/cpumask.h> + +extern cpumask_t phys_cpu_present_map; +#define cpu_possible_map phys_cpu_present_map + +#define __smp_processor_id() (current_thread_info()->cpu) + #endif diff --git a/include/asm-cris/socket.h b/include/asm-cris/socket.h index f159b4f165f7..8b1da3e58c55 100644 --- a/include/asm-cris/socket.h +++ b/include/asm-cris/socket.h @@ -16,6 +16,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h new file mode 100644 index 000000000000..2e8ba8afc7af --- /dev/null +++ b/include/asm-cris/spinlock.h @@ -0,0 +1 @@ +#include <asm/arch/spinlock.h> diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h new file mode 100644 index 000000000000..f930b6e00663 --- /dev/null +++ b/include/asm-cris/sync_serial.h @@ -0,0 +1,106 @@ +/* + * ioctl defines for synchronous serial port driver + * + * Copyright (c) 2001-2003 Axis Communications AB + * + * Author: Mikael Starvik + * + */ + +#ifndef SYNC_SERIAL_H +#define SYNC_SERIAL_H + +#include <linux/ioctl.h> + +#define SSP_SPEED _IOR('S', 0, unsigned int) +#define SSP_MODE _IOR('S', 1, unsigned int) +#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) +#define SSP_IPOLARITY _IOR('S', 3, unsigned int) +#define SSP_OPOLARITY _IOR('S', 4, unsigned int) +#define SSP_SPI _IOR('S', 5, unsigned int) +#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) + +/* Values for SSP_SPEED */ +#define SSP150 0 +#define SSP300 1 +#define SSP600 2 +#define SSP1200 3 +#define SSP2400 4 +#define SSP4800 5 +#define SSP9600 6 +#define SSP19200 7 +#define SSP28800 8 +#define SSP57600 9 +#define SSP115200 10 +#define SSP230400 11 +#define SSP460800 12 +#define SSP921600 13 +#define SSP3125000 14 +#define CODEC 15 + +#define FREQ_4MHz 0 +#define FREQ_2MHz 1 +#define FREQ_1MHz 2 +#define FREQ_512kHz 3 +#define FREQ_256kHz 4 +#define FREQ_128kHz 5 +#define FREQ_64kHz 6 +#define FREQ_32kHz 7 + +/* Used by application to set CODEC divider, word rate and frame rate */ +#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28)) + +/* Used by driver to extract speed */ +#define GET_SPEED(x) (x & 0xff) +#define GET_FREQ(x) ((x & 0xff00) >> 8) +#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) +#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) + +/* Values for SSP_MODE */ +#define MASTER_OUTPUT 0 +#define SLAVE_OUTPUT 1 +#define MASTER_INPUT 2 +#define SLAVE_INPUT 3 +#define MASTER_BIDIR 4 +#define SLAVE_BIDIR 5 + +/* Values for SSP_FRAME_SYNC */ +#define NORMAL_SYNC 1 +#define EARLY_SYNC 2 + +#define BIT_SYNC 4 +#define WORD_SYNC 8 +#define EXTENDED_SYNC 0x10 + +#define SYNC_OFF 0x20 +#define SYNC_ON 0x40 +#define WORD_SIZE_8 0x80 +#define WORD_SIZE_12 0x100 +#define WORD_SIZE_16 0x200 +#define WORD_SIZE_24 0x400 +#define WORD_SIZE_32 0x800 +#define BIT_ORDER_LSB 0x1000 +#define BIT_ORDER_MSB 0x2000 +#define FLOW_CONTROL_ENABLE 0x4000 +#define FLOW_CONTROL_DISABLE 0x8000 +#define CLOCK_GATED 0x10000 +#define CLOCK_NOT_GATED 0x20000 + +/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ +#define CLOCK_NORMAL 1 +#define CLOCK_INVERT 2 +#define CLOCK_INEGEDGE CLOCK_NORMAL +#define CLOCK_IPOSEDGE CLOCK_INVERT +#define FRAME_NORMAL 4 +#define FRAME_INVERT 8 +#define STATUS_NORMAL 0x10 +#define STATUS_INVERT 0x20 + +/* Values for SSP_SPI */ +#define SPI_MASTER 0 +#define SPI_SLAVE 1 + +/* Values for SSP_INBUFCHUNK */ +/* plain integer with the size of DMA chunks */ + +#endif diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h index 16d9a491fdb3..be0836d2f282 100644 --- a/include/asm-cris/termbits.h +++ b/include/asm-cris/termbits.h @@ -152,7 +152,7 @@ struct termios { #define B921600 0010005 #define B1843200 0010006 #define B6250000 0010007 -/* etrax 200 supports this as well */ +/* ETRAX FS supports this as well */ #define B12500000 0010010 #define CIBAUD 002003600000 /* input baud rate (used in v32) */ /* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h index 5ba4b7865cc5..cef0140fc104 100644 --- a/include/asm-cris/thread_info.h +++ b/include/asm-cris/thread_info.h @@ -43,7 +43,7 @@ struct thread_info { #endif -#define PREEMPT_ACTIVE 0x4000000 +#define PREEMPT_ACTIVE 0x10000000 /* * macros/functions for gaining access to the thread information structure diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h index 375c41af47de..3fb069a37717 100644 --- a/include/asm-cris/timex.h +++ b/include/asm-cris/timex.h @@ -14,7 +14,7 @@ * used so it does not matter. */ -typedef unsigned int cycles_t; +typedef unsigned long long cycles_t; extern inline cycles_t get_cycles(void) { diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h index 1781fe1a32f6..6ed7d9ae90db 100644 --- a/include/asm-cris/tlbflush.h +++ b/include/asm-cris/tlbflush.h @@ -18,13 +18,26 @@ * */ +extern void __flush_tlb_all(void); +extern void __flush_tlb_mm(struct mm_struct *mm); +extern void __flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr); + +#ifdef CONFIG_SMP extern void flush_tlb_all(void); extern void flush_tlb_mm(struct mm_struct *mm); extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); -extern void flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, - unsigned long end); +#else +#define flush_tlb_all __flush_tlb_all +#define flush_tlb_mm __flush_tlb_mm +#define flush_tlb_page __flush_tlb_page +#endif + +static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) +{ + flush_tlb_mm(vma->vm_mm); +} extern inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h index 41a0d450ba1d..84557c9bac93 100644 --- a/include/asm-cris/types.h +++ b/include/asm-cris/types.h @@ -52,8 +52,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u32 dma64_addr_t; -typedef unsigned int kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h index e80bf276b101..28232ad2ff34 100644 --- a/include/asm-cris/unistd.h +++ b/include/asm-cris/unistd.h @@ -288,8 +288,15 @@ #define __NR_mq_timedreceive (__NR_mq_open+3) #define __NR_mq_notify (__NR_mq_open+4) #define __NR_mq_getsetattr (__NR_mq_open+5) - -#define NR_syscalls 283 +#define __NR_sys_kexec_load 283 +#define __NR_waitid 284 +/* #define __NR_sys_setaltroot 285 */ +#define __NR_add_key 286 +#define __NR_request_key 287 +#define __NR_keyctl 288 + +#define NR_syscalls 289 + #ifdef __KERNEL__ diff --git a/include/asm-frv/emergency-restart.h b/include/asm-frv/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-frv/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-frv/page.h b/include/asm-frv/page.h index f7914f1782b0..4feba567e7fd 100644 --- a/include/asm-frv/page.h +++ b/include/asm-frv/page.h @@ -45,21 +45,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) __attribute_const__; -static inline int get_order(unsigned long size) -{ - int order; - - size = (size - 1) >> (PAGE_SHIFT - 1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #define devmem_is_allowed(pfn) 1 #define __pa(vaddr) virt_to_phys((void *) vaddr) @@ -102,4 +87,6 @@ extern unsigned long max_pfn; #define WANT_PAGE_VIRTUAL 1 #endif +#include <asm-generic/page.h> + #endif /* _ASM_PAGE_H */ diff --git a/include/asm-frv/socket.h b/include/asm-frv/socket.h index c3be17c7de4b..7177f8b9817c 100644 --- a/include/asm-frv/socket.h +++ b/include/asm-frv/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-frv/types.h b/include/asm-frv/types.h index 1a5b6546bb41..50605df6d8ac 100644 --- a/include/asm-frv/types.h +++ b/include/asm-frv/types.h @@ -65,8 +65,6 @@ typedef u64 u_quad_t; typedef u32 dma_addr_t; -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-generic/emergency-restart.h b/include/asm-generic/emergency-restart.h new file mode 100644 index 000000000000..0d68a1eae985 --- /dev/null +++ b/include/asm-generic/emergency-restart.h @@ -0,0 +1,9 @@ +#ifndef _ASM_GENERIC_EMERGENCY_RESTART_H +#define _ASM_GENERIC_EMERGENCY_RESTART_H + +static inline void machine_emergency_restart(void) +{ + machine_restart(NULL); +} + +#endif /* _ASM_GENERIC_EMERGENCY_RESTART_H */ diff --git a/include/asm-generic/page.h b/include/asm-generic/page.h new file mode 100644 index 000000000000..a96b5d986b6e --- /dev/null +++ b/include/asm-generic/page.h @@ -0,0 +1,26 @@ +#ifndef _ASM_GENERIC_PAGE_H +#define _ASM_GENERIC_PAGE_H + +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +#include <linux/compiler.h> + +/* Pure 2^n version of get_order */ +static __inline__ __attribute_const__ int get_order(unsigned long size) +{ + int order; + + size = (size - 1) >> (PAGE_SHIFT - 1); + order = -1; + do { + size >>= 1; + order++; + } while (size); + return order; +} + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL__ */ + +#endif /* _ASM_GENERIC_PAGE_H */ diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h index 9d4cc47bde39..ee1d8b5d8168 100644 --- a/include/asm-generic/pci.h +++ b/include/asm-generic/pci.h @@ -22,6 +22,14 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, region->end = res->end; } +static inline void +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region) +{ + res->start = region->start; + res->end = region->end; +} + #define pcibios_scan_all_fns(a, b) 0 #ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index f40593565173..f86c1e549466 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -101,6 +101,22 @@ do { \ }) #endif +#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL +#define ptep_get_and_clear_full(__mm, __address, __ptep, __full) \ +({ \ + pte_t __pte; \ + __pte = ptep_get_and_clear((__mm), (__address), (__ptep)); \ + __pte; \ +}) +#endif + +#ifndef __HAVE_ARCH_PTE_CLEAR_FULL +#define pte_clear_full(__mm, __address, __ptep, __full) \ +do { \ + pte_clear((__mm), (__address), (__ptep)); \ +} while (0) +#endif + #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH #define ptep_clear_flush(__vma, __address, __ptep) \ ({ \ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 195ccdc069e6..450eae22c39a 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -11,5 +11,6 @@ extern char _sinittext[], _einittext[]; extern char _sextratext[] __attribute__((weak)); extern char _eextratext[] __attribute__((weak)); extern char _end[]; +extern char __per_cpu_start[], __per_cpu_end[]; #endif /* _ASM_GENERIC_SECTIONS_H_ */ diff --git a/include/asm-h8300/emergency-restart.h b/include/asm-h8300/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-h8300/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-h8300/page.h b/include/asm-h8300/page.h index e3b7960d445b..e8c02b8c2d99 100644 --- a/include/asm-h8300/page.h +++ b/include/asm-h8300/page.h @@ -54,20 +54,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - extern unsigned long memory_start; extern unsigned long memory_end; @@ -101,4 +87,6 @@ extern unsigned long memory_end; #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _H8300_PAGE_H */ diff --git a/include/asm-h8300/pci.h b/include/asm-h8300/pci.h index d032729b19df..5edad5b70fd5 100644 --- a/include/asm-h8300/pci.h +++ b/include/asm-h8300/pci.h @@ -15,7 +15,7 @@ extern inline void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -extern inline void pcibios_penalize_isa_irq(int irq) +extern inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-h8300/socket.h b/include/asm-h8300/socket.h index af33b8525dcf..d98cf85bafc1 100644 --- a/include/asm-h8300/socket.h +++ b/include/asm-h8300/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-h8300/types.h b/include/asm-h8300/types.h index 21f4fc07ac0e..bf91e0d4dde7 100644 --- a/include/asm-h8300/types.h +++ b/include/asm-h8300/types.h @@ -58,8 +58,6 @@ typedef u32 dma_addr_t; #define HAVE_SECTOR_T typedef u64 sector_t; -typedef unsigned int kmem_bufctl_t; - #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-i386/acpi.h b/include/asm-i386/acpi.h index c976c1dadece..cf828ace13f9 100644 --- a/include/asm-i386/acpi.h +++ b/include/asm-i386/acpi.h @@ -28,6 +28,8 @@ #ifdef __KERNEL__ +#include <acpi/pdc_intel.h> + #include <asm/system.h> /* defines cmpxchg */ #define COMPILER_DEPENDENT_INT64 long long @@ -101,12 +103,6 @@ __acpi_release_global_lock (unsigned int *lock) :"=r"(n_hi), "=r"(n_lo) \ :"0"(n_hi), "1"(n_lo)) -/* - * Refer Intel ACPI _PDC support document for bit definitions - */ -#define ACPI_PDC_EST_CAPABILITY_SMP 0xa -#define ACPI_PDC_EST_CAPABILITY_MSR 0x1 - #ifdef CONFIG_ACPI_BOOT extern int acpi_lapic; extern int acpi_ioapic; @@ -185,6 +181,8 @@ extern void acpi_reserve_bootmem(void); extern u8 x86_acpiid_to_apicid[]; +#define ARCH_HAS_POWER_PDC_INIT 1 + #endif /*__KERNEL__*/ #endif /*_ASM_ACPI_H*/ diff --git a/include/asm-i386/agp.h b/include/asm-i386/agp.h index b82f5f3ab887..9075083bab76 100644 --- a/include/asm-i386/agp.h +++ b/include/asm-i386/agp.h @@ -19,7 +19,7 @@ int unmap_page_from_agp(struct page *page); /* Could use CLFLUSH here if the cpu supports it. But then it would need to be called for each cacheline of the whole page so it may not be worth it. Would need a page for it. */ -#define flush_agp_cache() asm volatile("wbinvd":::"memory") +#define flush_agp_cache() wbinvd() /* Convert a physical address to an address suitable for the GART. */ #define phys_to_gart(x) (x) diff --git a/include/asm-i386/apicdef.h b/include/asm-i386/apicdef.h index 0fed5e3c699c..03185cef8e0a 100644 --- a/include/asm-i386/apicdef.h +++ b/include/asm-i386/apicdef.h @@ -16,6 +16,7 @@ #define GET_APIC_VERSION(x) ((x)&0xFF) #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF) #define APIC_INTEGRATED(x) ((x)&0xF0) +#define APIC_XAPIC(x) ((x) >= 0x14) #define APIC_TASKPRI 0x80 #define APIC_TPRI_MASK 0xFF #define APIC_ARBPRI 0x90 @@ -109,11 +110,7 @@ #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) -#ifdef CONFIG_NUMA - #define MAX_IO_APICS 32 -#else - #define MAX_IO_APICS 8 -#endif +#define MAX_IO_APICS 64 /* * the local APIC register structure, memory mapped. Not terribly well diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h index 9db0b712d57a..ddf1739dc7fd 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-i386/bitops.h @@ -311,6 +311,20 @@ static inline int find_first_zero_bit(const unsigned long *addr, unsigned size) int find_next_zero_bit(const unsigned long *addr, int size, int offset); /** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline unsigned long __ffs(unsigned long word) +{ + __asm__("bsfl %1,%0" + :"=r" (word) + :"rm" (word)); + return word; +} + +/** * find_first_bit - find the first set bit in a memory region * @addr: The address to start the search at * @size: The maximum size to search @@ -320,22 +334,15 @@ int find_next_zero_bit(const unsigned long *addr, int size, int offset); */ static inline int find_first_bit(const unsigned long *addr, unsigned size) { - int d0, d1; - int res; - - /* This looks at memory. Mark it volatile to tell gcc not to move it around */ - __asm__ __volatile__( - "xorl %%eax,%%eax\n\t" - "repe; scasl\n\t" - "jz 1f\n\t" - "leal -4(%%edi),%%edi\n\t" - "bsfl (%%edi),%%eax\n" - "1:\tsubl %%ebx,%%edi\n\t" - "shll $3,%%edi\n\t" - "addl %%edi,%%eax" - :"=a" (res), "=&c" (d0), "=&D" (d1) - :"1" ((size + 31) >> 5), "2" (addr), "b" (addr) : "memory"); - return res; + int x = 0; + + while (x < size) { + unsigned long val = *addr++; + if (val) + return __ffs(val) + x; + x += (sizeof(*addr)<<3); + } + return x; } /** @@ -360,20 +367,6 @@ static inline unsigned long ffz(unsigned long word) return word; } -/** - * __ffs - find first bit in word. - * @word: The word to search - * - * Undefined if no bit exists, so code should check against 0 first. - */ -static inline unsigned long __ffs(unsigned long word) -{ - __asm__("bsfl %1,%0" - :"=r" (word) - :"rm" (word)); - return word; -} - /* * fls: find last bit set. */ diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h index 6789fc275da3..ea54540638d2 100644 --- a/include/asm-i386/bugs.h +++ b/include/asm-i386/bugs.h @@ -118,7 +118,10 @@ static void __init check_hlt(void) printk("disabled\n"); return; } - __asm__ __volatile__("hlt ; hlt ; hlt ; hlt"); + halt(); + halt(); + halt(); + halt(); printk("OK.\n"); } diff --git a/include/asm-i386/checksum.h b/include/asm-i386/checksum.h index f949e44c2a35..67d3630c4e89 100644 --- a/include/asm-i386/checksum.h +++ b/include/asm-i386/checksum.h @@ -83,7 +83,7 @@ static inline unsigned short ip_fast_csum(unsigned char * iph, "adcl $0, %0 ;\n" "notl %0 ;\n" "2: ;\n" - /* Since the input registers which are loaded with iph and ipl + /* Since the input registers which are loaded with iph and ihl are modified, we must also specify them as outputs, or gcc will assume they contain their original values. */ : "=r" (sum), "=r" (iph), "=r" (ihl) diff --git a/include/asm-i386/desc.h b/include/asm-i386/desc.h index 11e67811a990..6df1a53c190e 100644 --- a/include/asm-i386/desc.h +++ b/include/asm-i386/desc.h @@ -27,8 +27,18 @@ struct Xgt_desc_struct { extern struct Xgt_desc_struct idt_descr, cpu_gdt_descr[NR_CPUS]; -#define load_TR_desc() __asm__ __volatile__("ltr %%ax"::"a" (GDT_ENTRY_TSS*8)) -#define load_LDT_desc() __asm__ __volatile__("lldt %%ax"::"a" (GDT_ENTRY_LDT*8)) +#define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) +#define load_LDT_desc() __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)) + +#define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) +#define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) +#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr)) +#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt)) + +#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr)) +#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr)) +#define store_tr(tr) __asm__ ("str %0":"=mr" (tr)) +#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt)) /* * This is the ldt that every process will get unless we need @@ -39,14 +49,14 @@ extern void set_intr_gate(unsigned int irq, void * addr); #define _set_tssldt_desc(n,addr,limit,type) \ __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \ - "movw %%ax,2(%2)\n\t" \ - "rorl $16,%%eax\n\t" \ - "movb %%al,4(%2)\n\t" \ + "movw %w1,2(%2)\n\t" \ + "rorl $16,%1\n\t" \ + "movb %b1,4(%2)\n\t" \ "movb %4,5(%2)\n\t" \ "movb $0,6(%2)\n\t" \ - "movb %%ah,7(%2)\n\t" \ - "rorl $16,%%eax" \ - : "=m"(*(n)) : "a" (addr), "r"(n), "ir"(limit), "i"(type)) + "movb %h1,7(%2)\n\t" \ + "rorl $16,%1" \ + : "=m"(*(n)) : "q" (addr), "r"(n), "ir"(limit), "i"(type)) static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr) { @@ -86,6 +96,13 @@ static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size) (info)->seg_not_present == 1 && \ (info)->useable == 0 ) +static inline void write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 entry_b) +{ + __u32 *lp = (__u32 *)((char *)ldt + entry*8); + *lp = entry_a; + *(lp+1) = entry_b; +} + #if TLS_SIZE != 24 # error update this code. #endif diff --git a/include/asm-i386/emergency-restart.h b/include/asm-i386/emergency-restart.h new file mode 100644 index 000000000000..680c39563345 --- /dev/null +++ b/include/asm-i386/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +extern void machine_emergency_restart(void); + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-i386/i387.h b/include/asm-i386/i387.h index f6feb98a9397..6747006743f9 100644 --- a/include/asm-i386/i387.h +++ b/include/asm-i386/i387.h @@ -19,10 +19,21 @@ extern void mxcsr_feature_mask_init(void); extern void init_fpu(struct task_struct *); + /* * FPU lazy state save handling... */ -extern void restore_fpu( struct task_struct *tsk ); + +/* + * The "nop" is needed to make the instructions the same + * length. + */ +#define restore_fpu(tsk) \ + alternative_input( \ + "nop ; frstor %1", \ + "fxrstor %1", \ + X86_FEATURE_FXSR, \ + "m" ((tsk)->thread.i387.fxsave)) extern void kernel_fpu_begin(void); #define kernel_fpu_end() do { stts(); preempt_enable(); } while(0) @@ -32,13 +43,12 @@ extern void kernel_fpu_begin(void); */ static inline void __save_init_fpu( struct task_struct *tsk ) { - if ( cpu_has_fxsr ) { - asm volatile( "fxsave %0 ; fnclex" - : "=m" (tsk->thread.i387.fxsave) ); - } else { - asm volatile( "fnsave %0 ; fwait" - : "=m" (tsk->thread.i387.fsave) ); - } + alternative_input( + "fnsave %1 ; fwait ;" GENERIC_NOP2, + "fxsave %1 ; fnclex", + X86_FEATURE_FXSR, + "m" (tsk->thread.i387.fxsave) + :"memory"); tsk->thread_info->status &= ~TS_USEDFPU; } diff --git a/include/asm-i386/kdebug.h b/include/asm-i386/kdebug.h index b3f8d5f59d5d..316138e89910 100644 --- a/include/asm-i386/kdebug.h +++ b/include/asm-i386/kdebug.h @@ -41,9 +41,16 @@ enum die_val { DIE_PAGE_FAULT, }; -static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig) +static inline int notify_die(enum die_val val, const char *str, + struct pt_regs *regs, long err, int trap, int sig) { - struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig }; + struct die_args args = { + .regs = regs, + .str = str, + .err = err, + .trapnr = trap, + .signr = sig + }; return notifier_call_chain(&i386die_chain, val, &args); } diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-i386/mach-es7000/mach_mpparse.h index 85809e0898d7..28a84f6185a7 100644 --- a/include/asm-i386/mach-es7000/mach_mpparse.h +++ b/include/asm-i386/mach-es7000/mach_mpparse.h @@ -1,6 +1,8 @@ #ifndef __ASM_MACH_MPPARSE_H #define __ASM_MACH_MPPARSE_H +#include <linux/acpi.h> + static inline void mpc_oem_bus_info(struct mpc_config_bus *m, char *name, struct mpc_config_translation *translation) { @@ -12,8 +14,9 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m, { } -extern int parse_unisys_oem (char *oemptr, int oem_entries); -extern int find_unisys_acpi_oem_table(unsigned long *oem_addr, int *length); +extern int parse_unisys_oem (char *oemptr); +extern int find_unisys_acpi_oem_table(unsigned long *oem_addr); +extern void setup_unisys(); static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, char *productid) @@ -22,18 +25,33 @@ static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, struct mp_config_oemtable *oem_table = (struct mp_config_oemtable *)mpc->mpc_oemptr; if (!strncmp(oem, "UNISYS", 6)) - return parse_unisys_oem((char *)oem_table, oem_table->oem_length); + return parse_unisys_oem((char *)oem_table); } return 0; } +static inline int es7000_check_dsdt() +{ + struct acpi_table_header *header = NULL; + if(!acpi_get_table_header_early(ACPI_DSDT, &header)) + acpi_table_print(header, 0); + if (!strncmp(header->oem_id, "UNISYS", 6)) + return 1; + return 0; +} + /* Hook from generic ACPI tables.c */ static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id) { unsigned long oem_addr; - int oem_entries; - if (!find_unisys_acpi_oem_table(&oem_addr, &oem_entries)) - return parse_unisys_oem((char *)oem_addr, oem_entries); + if (!find_unisys_acpi_oem_table(&oem_addr)) { + if (es7000_check_dsdt()) + return parse_unisys_oem((char *)oem_addr); + else { + setup_unisys(); + return 1; + } + } return 0; } diff --git a/include/asm-i386/mach-generic/mach_apic.h b/include/asm-i386/mach-generic/mach_apic.h index b13767a4e934..d9dc039da94a 100644 --- a/include/asm-i386/mach-generic/mach_apic.h +++ b/include/asm-i386/mach-generic/mach_apic.h @@ -28,4 +28,6 @@ #define enable_apic_mode (genapic->enable_apic_mode) #define phys_pkg_id (genapic->phys_pkg_id) +extern void generic_bigsmp_probe(void); + #endif /* __ASM_MACH_APIC_H */ diff --git a/include/asm-i386/mach-visws/do_timer.h b/include/asm-i386/mach-visws/do_timer.h index 33acd50fd9a8..92d638fc8b11 100644 --- a/include/asm-i386/mach-visws/do_timer.h +++ b/include/asm-i386/mach-visws/do_timer.h @@ -1,6 +1,7 @@ /* defines for inline arch setup functions */ #include <asm/fixmap.h> +#include <asm/i8259.h> #include "cobalt.h" static inline void do_timer_interrupt_hook(struct pt_regs *regs) diff --git a/include/asm-i386/mpspec.h b/include/asm-i386/mpspec.h index d9fafba075bc..d84a9c326c22 100644 --- a/include/asm-i386/mpspec.h +++ b/include/asm-i386/mpspec.h @@ -11,6 +11,7 @@ extern int mp_bus_id_to_local [MAX_MP_BUSSES]; extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; +extern unsigned int def_to_bigsmp; extern unsigned int boot_cpu_physical_apicid; extern int smp_found_config; extern void find_smp_config (void); diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index c76fce8badbb..62b76cd96957 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h @@ -47,6 +47,21 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val) : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\ ret__; }) +/* rdmsr with exception handling */ +#define rdmsr_safe(msr,a,b) ({ int ret__; \ + asm volatile("2: rdmsr ; xorl %0,%0\n" \ + "1:\n\t" \ + ".section .fixup,\"ax\"\n\t" \ + "3: movl %4,%0 ; jmp 1b\n\t" \ + ".previous\n\t" \ + ".section __ex_table,\"a\"\n" \ + " .align 4\n\t" \ + " .long 2b,3b\n\t" \ + ".previous" \ + : "=r" (ret__), "=a" (*(a)), "=d" (*(b)) \ + : "c" (msr), "i" (-EFAULT));\ + ret__; }) + #define rdtsc(low,high) \ __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) diff --git a/include/asm-i386/page.h b/include/asm-i386/page.h index 8d93f732d72d..73296d9924fb 100644 --- a/include/asm-i386/page.h +++ b/include/asm-i386/page.h @@ -68,7 +68,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define HPAGE_MASK (~(HPAGE_SIZE - 1)) #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA -#define ARCH_HAS_HUGETLB_CLEAN_STALE_PGTABLE #endif #define pgd_val(x) ((x).pgd) @@ -104,20 +103,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; */ extern unsigned int __VMALLOC_RESERVE; -/* Pure 2^n version of get_order */ -static __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - extern int sysctl_legacy_va_layout; extern int page_is_ram(unsigned long pagenr); @@ -156,4 +141,6 @@ extern int page_is_ram(unsigned long pagenr); #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _I386_PAGE_H */ diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h index 3561899eb826..78c85985aee3 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-i386/pci.h @@ -27,7 +27,7 @@ void pcibios_config_init(void); struct pci_bus * pcibios_scan_root(int bus); void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); +void pcibios_penalize_isa_irq(int irq, int active); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h index d609f9c2c1f0..2e3f4a344a2d 100644 --- a/include/asm-i386/pgtable-3level.h +++ b/include/asm-i386/pgtable-3level.h @@ -64,7 +64,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte) #define set_pmd(pmdptr,pmdval) \ set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval)) #define set_pud(pudptr,pudval) \ - set_64bit((unsigned long long *)(pudptr),pud_val(pudval)) + (*(pudptr) = (pudval)) /* * Pentium-II erratum A13: in PAE mode we explicitly have to flush diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h index 77c6497f416e..47bc1ffa3d4c 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-i386/pgtable.h @@ -86,9 +86,7 @@ void paging_init(void); #endif /* - * The 4MB page is guessing.. Detailed in the infamous "Chapter H" - * of the Pentium details, but assuming intel did the straightforward - * thing, this bit set in the page directory entry just means that + * _PAGE_PSE set in the page directory entry just means that * the page directory entry points directly to a 4MB-aligned block of * memory. */ @@ -119,8 +117,10 @@ void paging_init(void); #define _PAGE_UNUSED2 0x400 #define _PAGE_UNUSED3 0x800 -#define _PAGE_FILE 0x040 /* set:pagecache unset:swap */ -#define _PAGE_PROTNONE 0x080 /* If not present */ +/* If _PAGE_PRESENT is clear, we use these: */ +#define _PAGE_FILE 0x040 /* nonlinear file mapping, saved PTE; unset:swap */ +#define _PAGE_PROTNONE 0x080 /* if the user mapped it with PROT_NONE; + pte_present gives true */ #ifdef CONFIG_X86_PAE #define _PAGE_NX (1ULL<<_PAGE_BIT_NX) #else @@ -215,11 +215,13 @@ extern unsigned long pg0[]; * The following only work if pte_present() is true. * Undefined behaviour if not.. */ +#define __LARGE_PTE (_PAGE_PSE | _PAGE_PRESENT) static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; } static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; } static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; } static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; } +static inline int pte_huge(pte_t pte) { return ((pte).pte_low & __LARGE_PTE) == __LARGE_PTE; } /* * The following only works if pte_present() is not true. @@ -236,7 +238,7 @@ static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; } static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; } -static inline pte_t pte_mkhuge(pte_t pte) { (pte).pte_low |= _PAGE_PRESENT | _PAGE_PSE; return pte; } +static inline pte_t pte_mkhuge(pte_t pte) { (pte).pte_low |= __LARGE_PTE; return pte; } #ifdef CONFIG_X86_PAE # include <asm/pgtable-3level.h> @@ -258,12 +260,39 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low); } +static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full) +{ + pte_t pte; + if (full) { + pte = *ptep; + *ptep = __pte(0); + } else { + pte = ptep_get_and_clear(mm, addr, ptep); + } + return pte; +} + static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { clear_bit(_PAGE_BIT_RW, &ptep->pte_low); } /* + * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); + * + * dst - pointer to pgd range anwhere on a pgd page + * src - "" + * count - the number of pgds to copy. + * + * dst and src can be on the same page, but the range must not overlap, + * and must not cross a page boundary. + */ +static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) +{ + memcpy(dst, src, count * sizeof(pgd_t)); +} + +/* * Macro to mark a page protection value as "uncacheable". On processors which do not support * it, this is a no-op. */ @@ -415,6 +444,7 @@ extern void noexec_setup(const char *str); #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY #define __HAVE_ARCH_PTEP_GET_AND_CLEAR +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL #define __HAVE_ARCH_PTEP_SET_WRPROTECT #define __HAVE_ARCH_PTE_SAME #include <asm-generic/pgtable.h> diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 5d06e6bd6ba0..37bef8ed7bed 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -29,7 +29,7 @@ struct desc_struct { }; #define desc_empty(desc) \ - (!((desc)->a + (desc)->b)) + (!((desc)->a | (desc)->b)) #define desc_equal(desc1, desc2) \ (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b)) @@ -203,9 +203,7 @@ static inline unsigned int cpuid_edx(unsigned int op) return edx; } -#define load_cr3(pgdir) \ - asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir))) - +#define load_cr3(pgdir) write_cr3(__pa(pgdir)) /* * Intel CPU features in CR4 @@ -232,22 +230,20 @@ extern unsigned long mmu_cr4_features; static inline void set_in_cr4 (unsigned long mask) { + unsigned cr4; mmu_cr4_features |= mask; - __asm__("movl %%cr4,%%eax\n\t" - "orl %0,%%eax\n\t" - "movl %%eax,%%cr4\n" - : : "irg" (mask) - :"ax"); + cr4 = read_cr4(); + cr4 |= mask; + write_cr4(cr4); } static inline void clear_in_cr4 (unsigned long mask) { + unsigned cr4; mmu_cr4_features &= ~mask; - __asm__("movl %%cr4,%%eax\n\t" - "andl %0,%%eax\n\t" - "movl %%eax,%%cr4\n" - : : "irg" (~mask) - :"ax"); + cr4 = read_cr4(); + cr4 &= ~mask; + write_cr4(cr4); } /* @@ -281,6 +277,11 @@ static inline void clear_in_cr4 (unsigned long mask) outb((data), 0x23); \ } while (0) +static inline void serialize_cpu(void) +{ + __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); +} + static inline void __monitor(const void *eax, unsigned long ecx, unsigned long edx) { @@ -454,6 +455,7 @@ struct thread_struct { unsigned int saved_fs, saved_gs; /* IO permissions */ unsigned long *io_bitmap_ptr; + unsigned long iopl; /* max allowed port in the bitmap, in bytes: */ unsigned long io_bitmap_max; }; @@ -474,7 +476,6 @@ struct thread_struct { .esp0 = sizeof(init_stack) + (long)&init_stack, \ .ss0 = __KERNEL_DS, \ .ss1 = __KERNEL_CS, \ - .ldt = GDT_ENTRY_LDT, \ .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \ } @@ -511,6 +512,21 @@ static inline void load_esp0(struct tss_struct *tss, struct thread_struct *threa : /* no output */ \ :"r" (value)) +/* + * Set IOPL bits in EFLAGS from given mask + */ +static inline void set_iopl_mask(unsigned mask) +{ + unsigned int reg; + __asm__ __volatile__ ("pushfl;" + "popl %0;" + "andl %1, %0;" + "orl %2, %0;" + "pushl %0;" + "popfl" + : "=&r" (reg) + : "i" (~X86_EFLAGS_IOPL), "r" (mask)); +} /* Forward declaration, a strange C thing */ struct task_struct; diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h index eef9f93870d4..7e0f2945d17d 100644 --- a/include/asm-i386/ptrace.h +++ b/include/asm-i386/ptrace.h @@ -55,16 +55,33 @@ struct pt_regs { #define PTRACE_SET_THREAD_AREA 26 #ifdef __KERNEL__ + +#include <asm/vm86.h> + struct task_struct; extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code); -#define user_mode(regs) (3 & (regs)->xcs) -#define user_mode_vm(regs) ((VM_MASK & (regs)->eflags) || user_mode(regs)) + +/* + * user_mode_vm(regs) determines whether a register set came from user mode. + * This is true if V8086 mode was enabled OR if the register set was from + * protected mode with RPL-3 CS value. This tricky test checks that with + * one comparison. Many places in the kernel can bypass this full check + * if they have already ruled out V8086 mode, so user_mode(regs) can be used. + */ +static inline int user_mode(struct pt_regs *regs) +{ + return (regs->xcs & 3) != 0; +} +static inline int user_mode_vm(struct pt_regs *regs) +{ + return ((regs->xcs & 3) | (regs->eflags & VM_MASK)) != 0; +} #define instruction_pointer(regs) ((regs)->eip) #if defined(CONFIG_SMP) && defined(CONFIG_FRAME_POINTER) extern unsigned long profile_pc(struct pt_regs *regs); #else #define profile_pc(regs) instruction_pointer(regs) #endif -#endif +#endif /* __KERNEL__ */ #endif diff --git a/include/asm-i386/setup.h b/include/asm-i386/setup.h index 7a32184d54bf..826a8ca50ac8 100644 --- a/include/asm-i386/setup.h +++ b/include/asm-i386/setup.h @@ -44,7 +44,7 @@ extern unsigned char boot_params[PARAM_SIZE]; #define EFI_SYSTAB ((efi_system_table_t *) *((unsigned long *)(PARAM+0x1c4))) #define EFI_MEMDESC_SIZE (*((unsigned long *) (PARAM+0x1c8))) #define EFI_MEMDESC_VERSION (*((unsigned long *) (PARAM+0x1cc))) -#define EFI_MEMMAP ((efi_memory_desc_t *) *((unsigned long *)(PARAM+0x1d0))) +#define EFI_MEMMAP ((void *) *((unsigned long *)(PARAM+0x1d0))) #define EFI_MEMMAP_SIZE (*((unsigned long *) (PARAM+0x1d4))) #define MOUNT_ROOT_RDONLY (*(unsigned short *) (PARAM+0x1F2)) #define RAMDISK_FLAGS (*(unsigned short *) (PARAM+0x1F8)) diff --git a/include/asm-i386/smp.h b/include/asm-i386/smp.h index edad9b4712fa..13250199976d 100644 --- a/include/asm-i386/smp.h +++ b/include/asm-i386/smp.h @@ -37,9 +37,6 @@ extern int smp_num_siblings; extern cpumask_t cpu_sibling_map[]; extern cpumask_t cpu_core_map[]; -extern void smp_flush_tlb(void); -extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs); -extern void smp_invalidate_rcv(void); /* Process an NMI */ extern void (*mtrr_hook) (void); extern void zap_low_mappings (void); extern void lock_ipi_call_lock(void); @@ -62,7 +59,7 @@ extern void cpu_uninit(void); extern cpumask_t cpu_callout_map; extern cpumask_t cpu_callin_map; -#define cpu_possible_map cpu_callout_map +extern cpumask_t cpu_possible_map; /* We don't mark CPUs online until __cpu_up(), so we need another measure */ static inline int num_booting_cpus(void) diff --git a/include/asm-i386/socket.h b/include/asm-i386/socket.h index 07f6b38ad140..802ae76195b7 100644 --- a/include/asm-i386/socket.h +++ b/include/asm-i386/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h index 3db717a244f0..acd5c26b69ba 100644 --- a/include/asm-i386/system.h +++ b/include/asm-i386/system.h @@ -14,8 +14,7 @@ extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struc #define switch_to(prev,next,last) do { \ unsigned long esi,edi; \ - asm volatile("pushfl\n\t" \ - "pushl %%ebp\n\t" \ + asm volatile("pushl %%ebp\n\t" \ "movl %%esp,%0\n\t" /* save ESP */ \ "movl %5,%%esp\n\t" /* restore ESP */ \ "movl $1f,%1\n\t" /* save EIP */ \ @@ -23,7 +22,6 @@ extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struc "jmp __switch_to\n" \ "1:\t" \ "popl %%ebp\n\t" \ - "popfl" \ :"=m" (prev->thread.esp),"=m" (prev->thread.eip), \ "=a" (last),"=S" (esi),"=D" (edi) \ :"m" (next->thread.esp),"m" (next->thread.eip), \ @@ -93,13 +91,13 @@ static inline unsigned long _get_base(char * addr) ".align 4\n\t" \ ".long 1b,3b\n" \ ".previous" \ - : :"m" (value)) + : :"rm" (value)) /* * Save a segment register away */ #define savesegment(seg, value) \ - asm volatile("mov %%" #seg ",%0":"=m" (value)) + asm volatile("mov %%" #seg ",%0":"=rm" (value)) /* * Clear and set 'TS' bit respectively @@ -107,13 +105,33 @@ static inline unsigned long _get_base(char * addr) #define clts() __asm__ __volatile__ ("clts") #define read_cr0() ({ \ unsigned int __dummy; \ - __asm__( \ + __asm__ __volatile__( \ "movl %%cr0,%0\n\t" \ :"=r" (__dummy)); \ __dummy; \ }) #define write_cr0(x) \ - __asm__("movl %0,%%cr0": :"r" (x)); + __asm__ __volatile__("movl %0,%%cr0": :"r" (x)); + +#define read_cr2() ({ \ + unsigned int __dummy; \ + __asm__ __volatile__( \ + "movl %%cr2,%0\n\t" \ + :"=r" (__dummy)); \ + __dummy; \ +}) +#define write_cr2(x) \ + __asm__ __volatile__("movl %0,%%cr2": :"r" (x)); + +#define read_cr3() ({ \ + unsigned int __dummy; \ + __asm__ ( \ + "movl %%cr3,%0\n\t" \ + :"=r" (__dummy)); \ + __dummy; \ +}) +#define write_cr3(x) \ + __asm__ __volatile__("movl %0,%%cr3": :"r" (x)); #define read_cr4() ({ \ unsigned int __dummy; \ @@ -123,7 +141,7 @@ static inline unsigned long _get_base(char * addr) __dummy; \ }) #define write_cr4(x) \ - __asm__("movl %0,%%cr4": :"r" (x)); + __asm__ __volatile__("movl %0,%%cr4": :"r" (x)); #define stts() write_cr0(8 | read_cr0()) #endif /* __KERNEL__ */ @@ -447,6 +465,8 @@ struct alt_instr { #define local_irq_enable() __asm__ __volatile__("sti": : :"memory") /* used in the idle loop; sti takes one instruction cycle to complete */ #define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory") +/* used when interrupts are already enabled or to shutdown the processor */ +#define halt() __asm__ __volatile__("hlt": : :"memory") #define irqs_disabled() \ ({ \ diff --git a/include/asm-i386/thread_info.h b/include/asm-i386/thread_info.h index 95add81237ea..e2cb9fa6f563 100644 --- a/include/asm-i386/thread_info.h +++ b/include/asm-i386/thread_info.h @@ -139,6 +139,7 @@ register unsigned long current_stack_pointer asm("esp") __attribute_used__; #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ #define TIF_IRET 5 /* return with iret */ +#define TIF_SYSCALL_EMU 6 /* syscall emulation active */ #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ #define TIF_SECCOMP 8 /* secure computing */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ @@ -150,13 +151,15 @@ register unsigned long current_stack_pointer asm("esp") __attribute_used__; #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) #define _TIF_IRET (1<<TIF_IRET) +#define _TIF_SYSCALL_EMU (1<<TIF_SYSCALL_EMU) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) /* work to do on interrupt/exception return */ #define _TIF_WORK_MASK \ - (0x0000FFFF & ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP|_TIF_SECCOMP)) + (0x0000FFFF & ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP|\ + _TIF_SECCOMP|_TIF_SYSCALL_EMU)) /* work to do on any return to u-space */ #define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP) diff --git a/include/asm-i386/timer.h b/include/asm-i386/timer.h index dcf1e07db08a..aed16437479d 100644 --- a/include/asm-i386/timer.h +++ b/include/asm-i386/timer.h @@ -1,6 +1,7 @@ #ifndef _ASMi386_TIMER_H #define _ASMi386_TIMER_H #include <linux/init.h> +#include <linux/pm.h> /** * struct timer_ops - used to define a timer source @@ -23,6 +24,8 @@ struct timer_opts { unsigned long long (*monotonic_clock)(void); void (*delay)(unsigned long); unsigned long (*read_timer)(void); + int (*suspend)(pm_message_t state); + int (*resume)(void); }; struct init_timer_opts { diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h index 901b77c42b8a..ced00fe8fe61 100644 --- a/include/asm-i386/types.h +++ b/include/asm-i386/types.h @@ -63,8 +63,6 @@ typedef u64 sector_t; #define HAVE_SECTOR_T #endif -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h index e25e4c71a879..a7cb377745bf 100644 --- a/include/asm-i386/unistd.h +++ b/include/asm-i386/unistd.h @@ -296,8 +296,11 @@ #define __NR_keyctl 288 #define __NR_ioprio_set 289 #define __NR_ioprio_get 290 +#define __NR_inotify_init 291 +#define __NR_inotify_add_watch 292 +#define __NR_inotify_rm_watch 293 -#define NR_syscalls 291 +#define NR_syscalls 294 /* * user-visible error numbers are in the range -1 - -128: see diff --git a/include/asm-i386/xor.h b/include/asm-i386/xor.h index f80e2dbe1b56..23c86cef3b25 100644 --- a/include/asm-i386/xor.h +++ b/include/asm-i386/xor.h @@ -535,14 +535,14 @@ static struct xor_block_template xor_block_p5_mmx = { #define XMMS_SAVE do { \ preempt_disable(); \ + cr0 = read_cr0(); \ + clts(); \ __asm__ __volatile__ ( \ - "movl %%cr0,%0 ;\n\t" \ - "clts ;\n\t" \ - "movups %%xmm0,(%1) ;\n\t" \ - "movups %%xmm1,0x10(%1) ;\n\t" \ - "movups %%xmm2,0x20(%1) ;\n\t" \ - "movups %%xmm3,0x30(%1) ;\n\t" \ - : "=&r" (cr0) \ + "movups %%xmm0,(%0) ;\n\t" \ + "movups %%xmm1,0x10(%0) ;\n\t" \ + "movups %%xmm2,0x20(%0) ;\n\t" \ + "movups %%xmm3,0x30(%0) ;\n\t" \ + : \ : "r" (xmm_save) \ : "memory"); \ } while(0) @@ -550,14 +550,14 @@ static struct xor_block_template xor_block_p5_mmx = { #define XMMS_RESTORE do { \ __asm__ __volatile__ ( \ "sfence ;\n\t" \ - "movups (%1),%%xmm0 ;\n\t" \ - "movups 0x10(%1),%%xmm1 ;\n\t" \ - "movups 0x20(%1),%%xmm2 ;\n\t" \ - "movups 0x30(%1),%%xmm3 ;\n\t" \ - "movl %0,%%cr0 ;\n\t" \ + "movups (%0),%%xmm0 ;\n\t" \ + "movups 0x10(%0),%%xmm1 ;\n\t" \ + "movups 0x20(%0),%%xmm2 ;\n\t" \ + "movups 0x30(%0),%%xmm3 ;\n\t" \ : \ - : "r" (cr0), "r" (xmm_save) \ + : "r" (xmm_save) \ : "memory"); \ + write_cr0(cr0); \ preempt_enable(); \ } while(0) diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h index 6a26a977f253..3a544ffc5008 100644 --- a/include/asm-ia64/acpi.h +++ b/include/asm-ia64/acpi.h @@ -98,6 +98,15 @@ const char *acpi_get_sysname (void); int acpi_request_vector (u32 int_type); int acpi_gsi_to_irq (u32 gsi, unsigned int *irq); +/* + * Record the cpei override flag and current logical cpu. This is + * useful for CPU removal. + */ +extern unsigned int can_cpei_retarget(void); +extern unsigned int is_cpu_cpei_target(unsigned int cpu); +extern void set_cpei_target_cpu(unsigned int cpu); +extern unsigned int get_cpei_target_cpu(void); + #ifdef CONFIG_ACPI_NUMA /* Proximity bitmap length; _PXM is at most 255 (8 bit)*/ #define MAX_PXM_DOMAINS (256) @@ -107,6 +116,11 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES]; extern u16 ia64_acpiid_to_sapicid[]; +/* + * Refer Intel ACPI _PDC support document for bit definitions + */ +#define ACPI_PDC_EST_CAPABILITY_SMP 0x8 + #endif /*__KERNEL__*/ #endif /*_ASM_ACPI_H*/ diff --git a/include/asm-ia64/emergency-restart.h b/include/asm-ia64/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-ia64/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-ia64/fcntl.h b/include/asm-ia64/fcntl.h index c9f8d835d0cc..cee16ea1780a 100644 --- a/include/asm-ia64/fcntl.h +++ b/include/asm-ia64/fcntl.h @@ -81,6 +81,7 @@ struct flock { #define F_LINUX_SPECIFIC_BASE 1024 -#define force_o_largefile() ( ! (current->personality & PER_LINUX32) ) +#define force_o_largefile() \ + (personality(current->personality) != PER_LINUX32) #endif /* _ASM_IA64_FCNTL_H */ diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h index 491e9d1fc538..cf772a67f858 100644 --- a/include/asm-ia64/io.h +++ b/include/asm-ia64/io.h @@ -23,7 +23,7 @@ #define __SLOW_DOWN_IO do { } while (0) #define SLOW_DOWN_IO do { } while (0) -#define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */ +#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED) /* * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but @@ -41,7 +41,7 @@ #define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS) #define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1)) -#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | (p & 0xfff)) +#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff)) struct io_space { unsigned long mmio_base; /* base in MMIO space */ @@ -120,14 +120,6 @@ static inline void ___ia64_mmiowb(void) ia64_mfa(); } -static inline const unsigned long -__ia64_get_io_port_base (void) -{ - extern unsigned long ia64_iobase; - - return ia64_iobase; -} - static inline void* __ia64_mk_io_addr (unsigned long port) { diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h index 1093f35b3b90..a429fe225b07 100644 --- a/include/asm-ia64/iosapic.h +++ b/include/asm-ia64/iosapic.h @@ -75,6 +75,8 @@ extern int __devinit iosapic_init (unsigned long address, unsigned int gsi_base); #ifdef CONFIG_HOTPLUG extern int iosapic_remove (unsigned int gsi_base); +#else +#define iosapic_remove(gsi_base) (-EINVAL) #endif /* CONFIG_HOTPLUG */ extern int gsi_to_vector (unsigned int gsi); extern int gsi_to_irq (unsigned int gsi); @@ -102,9 +104,7 @@ extern void __devinit map_iosapic_to_node (unsigned int, int); #else #define iosapic_system_init(pcat_compat) do { } while (0) #define iosapic_init(address,gsi_base) (-EINVAL) -#ifdef CONFIG_HOTPLUG #define iosapic_remove(gsi_base) (-ENODEV) -#endif /* CONFIG_HOTPLUG */ #define iosapic_register_intr(gsi,polarity,trigger) (gsi) #define iosapic_unregister_intr(irq) do { } while (0) #define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0) diff --git a/include/asm-ia64/mmu.h b/include/asm-ia64/mmu.h index ae1525352a25..611432ba579c 100644 --- a/include/asm-ia64/mmu.h +++ b/include/asm-ia64/mmu.h @@ -2,10 +2,12 @@ #define __MMU_H /* - * Type for a context number. We declare it volatile to ensure proper ordering when it's - * accessed outside of spinlock'd critical sections (e.g., as done in activate_mm() and - * init_new_context()). + * Type for a context number. We declare it volatile to ensure proper + * ordering when it's accessed outside of spinlock'd critical sections + * (e.g., as done in activate_mm() and init_new_context()). */ typedef volatile unsigned long mm_context_t; +typedef unsigned long nv_mm_context_t; + #endif diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h index e3e5fededb04..8d6e72f7b08e 100644 --- a/include/asm-ia64/mmu_context.h +++ b/include/asm-ia64/mmu_context.h @@ -19,6 +19,7 @@ #define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61)) +# include <asm/page.h> # ifndef __ASSEMBLY__ #include <linux/compiler.h> @@ -55,34 +56,46 @@ static inline void delayed_tlb_flush (void) { extern void local_flush_tlb_all (void); + unsigned long flags; if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) { - local_flush_tlb_all(); - __ia64_per_cpu_var(ia64_need_tlb_flush) = 0; + spin_lock_irqsave(&ia64_ctx.lock, flags); + { + if (__ia64_per_cpu_var(ia64_need_tlb_flush)) { + local_flush_tlb_all(); + __ia64_per_cpu_var(ia64_need_tlb_flush) = 0; + } + } + spin_unlock_irqrestore(&ia64_ctx.lock, flags); } } -static inline mm_context_t +static inline nv_mm_context_t get_mmu_context (struct mm_struct *mm) { unsigned long flags; - mm_context_t context = mm->context; - - if (context) - return context; - - spin_lock_irqsave(&ia64_ctx.lock, flags); - { - /* re-check, now that we've got the lock: */ - context = mm->context; - if (context == 0) { - cpus_clear(mm->cpu_vm_mask); - if (ia64_ctx.next >= ia64_ctx.limit) - wrap_mmu_context(mm); - mm->context = context = ia64_ctx.next++; + nv_mm_context_t context = mm->context; + + if (unlikely(!context)) { + spin_lock_irqsave(&ia64_ctx.lock, flags); + { + /* re-check, now that we've got the lock: */ + context = mm->context; + if (context == 0) { + cpus_clear(mm->cpu_vm_mask); + if (ia64_ctx.next >= ia64_ctx.limit) + wrap_mmu_context(mm); + mm->context = context = ia64_ctx.next++; + } } + spin_unlock_irqrestore(&ia64_ctx.lock, flags); } - spin_unlock_irqrestore(&ia64_ctx.lock, flags); + /* + * Ensure we're not starting to use "context" before any old + * uses of it are gone from our TLB. + */ + delayed_tlb_flush(); + return context; } @@ -104,13 +117,13 @@ destroy_context (struct mm_struct *mm) } static inline void -reload_context (mm_context_t context) +reload_context (nv_mm_context_t context) { unsigned long rid; unsigned long rid_incr = 0; unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4; - old_rr4 = ia64_get_rr(0x8000000000000000UL); + old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE)); rid = context << 3; /* make space for encoding the region number */ rid_incr = 1 << 8; @@ -122,6 +135,10 @@ reload_context (mm_context_t context) rr4 = rr0 + 4*rid_incr; #ifdef CONFIG_HUGETLB_PAGE rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc); + +# if RGN_HPAGE != 4 +# error "reload_context assumes RGN_HPAGE is 4" +# endif #endif ia64_set_rr(0x0000000000000000UL, rr0); @@ -138,7 +155,7 @@ reload_context (mm_context_t context) static inline void activate_context (struct mm_struct *mm) { - mm_context_t context; + nv_mm_context_t context; do { context = get_mmu_context(mm); @@ -157,8 +174,6 @@ activate_context (struct mm_struct *mm) static inline void activate_mm (struct mm_struct *prev, struct mm_struct *next) { - delayed_tlb_flush(); - /* * We may get interrupts here, but that's OK because interrupt handlers cannot * touch user-space. diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h index 08894f73abf0..9edffad8c28b 100644 --- a/include/asm-ia64/page.h +++ b/include/asm-ia64/page.h @@ -13,6 +13,19 @@ #include <asm/types.h> /* + * The top three bits of an IA64 address are its Region Number. + * Different regions are assigned to different purposes. + */ +#define RGN_SHIFT (61) +#define RGN_BASE(r) (__IA64_UL_CONST(r)<<RGN_SHIFT) +#define RGN_BITS (RGN_BASE(-1)) + +#define RGN_KERNEL 7 /* Identity mapped region */ +#define RGN_UNCACHED 6 /* Identity mapped I/O region */ +#define RGN_GATE 5 /* Gate page, Kernel text, etc */ +#define RGN_HPAGE 4 /* For Huge TLB pages */ + +/* * PAGE_SHIFT determines the actual kernel page size. */ #if defined(CONFIG_IA64_PAGE_SIZE_4KB) @@ -36,10 +49,9 @@ #define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */ + #ifdef CONFIG_HUGETLB_PAGE -# define REGION_HPAGE (4UL) /* note: this is hardcoded in reload_context()!*/ -# define REGION_SHIFT 61 -# define HPAGE_REGION_BASE (REGION_HPAGE << REGION_SHIFT) +# define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE) # define HPAGE_SHIFT hpage_shift # define HPAGE_SHIFT_DEFAULT 28 /* check ia64 SDM for architecture supported size */ # define HPAGE_SIZE (__IA64_UL_CONST(1) << HPAGE_SHIFT) @@ -130,16 +142,13 @@ typedef union ia64_va { #define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;}) #define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;}) -#define REGION_SIZE REGION_NUMBER(1) -#define REGION_KERNEL 7 - #ifdef CONFIG_HUGETLB_PAGE # define htlbpage_to_page(x) (((unsigned long) REGION_NUMBER(x) << 61) \ | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT))) # define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) # define is_hugepage_only_range(mm, addr, len) \ - (REGION_NUMBER(addr) == REGION_HPAGE && \ - REGION_NUMBER((addr)+(len)-1) == REGION_HPAGE) + (REGION_NUMBER(addr) == RGN_HPAGE && \ + REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE) extern unsigned int hpage_shift; #endif @@ -197,7 +206,7 @@ get_order (unsigned long size) # define __pgprot(x) (x) #endif /* !STRICT_MM_TYPECHECKS */ -#define PAGE_OFFSET __IA64_UL_CONST(0xe000000000000000) +#define PAGE_OFFSET RGN_BASE(RGN_KERNEL) #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC | \ diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index 2303a10ee595..e828377ad295 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -75,6 +75,8 @@ #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ #define PAL_VM_TR_READ 261 /* read contents of translation register */ +#define PAL_GET_PSTATE 262 /* get the current P-state */ +#define PAL_SET_PSTATE 263 /* set the P-state */ #ifndef __ASSEMBLY__ @@ -1111,6 +1113,25 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) return iprv.status; } +/* Get the current P-state information */ +static inline s64 +ia64_pal_get_pstate (u64 *pstate_index) +{ + struct ia64_pal_retval iprv; + PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0); + *pstate_index = iprv.v0; + return iprv.status; +} + +/* Set the P-state */ +static inline s64 +ia64_pal_set_pstate (u64 pstate_index) +{ + struct ia64_pal_retval iprv; + PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0); + return iprv.status; +} + /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are * suspended, but cache and TLB coherency is maintained. */ diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 0c4c5d801d3f..dba9f220be71 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -47,7 +47,7 @@ pcibios_set_master (struct pci_dev *dev) } static inline void -pcibios_penalize_isa_irq (int irq) +pcibios_penalize_isa_irq (int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } @@ -128,6 +128,7 @@ struct pci_controller { void *acpi_handle; void *iommu; int segment; + int node; /* nearest node with memory or -1 for global allocation */ unsigned int windows; struct pci_window *window; diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index 48586e08f432..2e34c06e6777 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h @@ -204,21 +204,18 @@ ia64_phys_addr_valid (unsigned long addr) #define set_pte(ptep, pteval) (*(ptep) = (pteval)) #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) -#define RGN_SIZE (1UL << 61) -#define RGN_KERNEL 7 - -#define VMALLOC_START 0xa000000200000000UL +#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL) #ifdef CONFIG_VIRTUAL_MEM_MAP -# define VMALLOC_END_INIT (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9))) +# define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) # define VMALLOC_END vmalloc_end extern unsigned long vmalloc_end; #else -# define VMALLOC_END (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9))) +# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) #endif /* fs/proc/kcore.c */ -#define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL) -#define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL) +#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE)) +#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE)) /* * Conversion functions: convert page frame number (pfn) and a protection value to a page diff --git a/include/asm-ia64/rwsem.h b/include/asm-ia64/rwsem.h index 6ece5061dc19..e18b5ab0cb75 100644 --- a/include/asm-ia64/rwsem.h +++ b/include/asm-ia64/rwsem.h @@ -3,6 +3,7 @@ * * Copyright (C) 2003 Ken Chen <kenneth.w.chen@intel.com> * Copyright (C) 2003 Asit Mallick <asit.k.mallick@intel.com> + * Copyright (C) 2005 Christoph Lameter <clameter@sgi.com> * * Based on asm-i386/rwsem.h and other architecture implementation. * @@ -11,9 +12,9 @@ * * The lock count is initialized to 0 (no active and no waiting lockers). * - * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case - * of an uncontended lock. Readers increment by 1 and see a positive value - * when uncontended, negative if there are writers (and maybe) readers + * When a writer subtracts WRITE_BIAS, it'll get 0xffffffff00000001 for + * the case of an uncontended lock. Readers increment by 1 and see a positive + * value when uncontended, negative if there are writers (and maybe) readers * waiting (in which case it goes to sleep). */ @@ -29,7 +30,7 @@ * the semaphore definition */ struct rw_semaphore { - signed int count; + signed long count; spinlock_t wait_lock; struct list_head wait_list; #if RWSEM_DEBUG @@ -37,10 +38,10 @@ struct rw_semaphore { #endif }; -#define RWSEM_UNLOCKED_VALUE 0x00000000 -#define RWSEM_ACTIVE_BIAS 0x00000001 -#define RWSEM_ACTIVE_MASK 0x0000ffff -#define RWSEM_WAITING_BIAS (-0x00010000) +#define RWSEM_UNLOCKED_VALUE __IA64_UL_CONST(0x0000000000000000) +#define RWSEM_ACTIVE_BIAS __IA64_UL_CONST(0x0000000000000001) +#define RWSEM_ACTIVE_MASK __IA64_UL_CONST(0x00000000ffffffff) +#define RWSEM_WAITING_BIAS -__IA64_UL_CONST(0x0000000100000000) #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) @@ -83,7 +84,7 @@ init_rwsem (struct rw_semaphore *sem) static inline void __down_read (struct rw_semaphore *sem) { - int result = ia64_fetchadd4_acq((unsigned int *)&sem->count, 1); + long result = ia64_fetchadd8_acq((unsigned long *)&sem->count, 1); if (result < 0) rwsem_down_read_failed(sem); @@ -95,7 +96,7 @@ __down_read (struct rw_semaphore *sem) static inline void __down_write (struct rw_semaphore *sem) { - int old, new; + long old, new; do { old = sem->count; @@ -112,7 +113,7 @@ __down_write (struct rw_semaphore *sem) static inline void __up_read (struct rw_semaphore *sem) { - int result = ia64_fetchadd4_rel((unsigned int *)&sem->count, -1); + long result = ia64_fetchadd8_rel((unsigned long *)&sem->count, -1); if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0) rwsem_wake(sem); @@ -124,7 +125,7 @@ __up_read (struct rw_semaphore *sem) static inline void __up_write (struct rw_semaphore *sem) { - int old, new; + long old, new; do { old = sem->count; @@ -141,7 +142,7 @@ __up_write (struct rw_semaphore *sem) static inline int __down_read_trylock (struct rw_semaphore *sem) { - int tmp; + long tmp; while ((tmp = sem->count) >= 0) { if (tmp == cmpxchg_acq(&sem->count, tmp, tmp+1)) { return 1; @@ -156,7 +157,7 @@ __down_read_trylock (struct rw_semaphore *sem) static inline int __down_write_trylock (struct rw_semaphore *sem) { - int tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE, + long tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE, RWSEM_ACTIVE_WRITE_BIAS); return tmp == RWSEM_UNLOCKED_VALUE; } @@ -167,7 +168,7 @@ __down_write_trylock (struct rw_semaphore *sem) static inline void __downgrade_write (struct rw_semaphore *sem) { - int old, new; + long old, new; do { old = sem->count; @@ -182,7 +183,7 @@ __downgrade_write (struct rw_semaphore *sem) * Implement atomic add functionality. These used to be "inline" functions, but GCC v3.1 * doesn't quite optimize this stuff right and ends up with bad calls to fetchandadd. */ -#define rwsem_atomic_add(delta, sem) atomic_add(delta, (atomic_t *)(&(sem)->count)) -#define rwsem_atomic_update(delta, sem) atomic_add_return(delta, (atomic_t *)(&(sem)->count)) +#define rwsem_atomic_add(delta, sem) atomic64_add(delta, (atomic64_t *)(&(sem)->count)) +#define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count)) #endif /* _ASM_IA64_RWSEM_H */ diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index 103d745dc5f2..2c32e4b77b54 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_ADDRS_H @@ -65,7 +65,6 @@ #define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT) #define AS_MASK ((u64)AS_BITMASK << AS_SHIFT) -#define REGION_BITS 0xe000000000000000UL /* @@ -79,38 +78,30 @@ #define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT) -/* - * Base addresses for various address ranges. - */ -#define CACHED 0xe000000000000000UL -#define UNCACHED 0xc000000000000000UL -#define UNCACHED_PHYS 0x8000000000000000UL - - /* * Virtual Mode Local & Global MMR space. */ #define SH1_LOCAL_MMR_OFFSET 0x8000000000UL #define SH2_LOCAL_MMR_OFFSET 0x0200000000UL #define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET) -#define LOCAL_MMR_SPACE (UNCACHED | LOCAL_MMR_OFFSET) -#define LOCAL_PHYS_MMR_SPACE (UNCACHED_PHYS | LOCAL_MMR_OFFSET) +#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET) +#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET) #define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL #define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL #define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET) -#define GLOBAL_MMR_SPACE (UNCACHED | GLOBAL_MMR_OFFSET) +#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET) /* * Physical mode addresses */ -#define GLOBAL_PHYS_MMR_SPACE (UNCACHED_PHYS | GLOBAL_MMR_OFFSET) +#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET) /* * Clear region & AS bits. */ -#define TO_PHYS_MASK (~(REGION_BITS | AS_MASK)) +#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK)) /* @@ -126,6 +117,7 @@ #define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a)) #define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a)) #define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n))) +#define IS_TIO_NASID(n) ((n) & 1) /* non-II mmr's start at top of big window space (4G) */ @@ -134,10 +126,10 @@ /* * general address defines */ -#define CAC_BASE (CACHED | AS_CAC_SPACE) -#define AMO_BASE (UNCACHED | AS_AMO_SPACE) -#define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE) -#define GET_BASE (CACHED | AS_GET_SPACE) +#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE) +#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE) +#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE) +#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE) /* * Convert Memory addresses between various addressing modes. @@ -155,17 +147,35 @@ * the chiplet id is zero. If we implement TIO-TIO dma, we might need * to insert a chiplet id into this macro. However, it is our belief * right now that this chiplet id will be ICE, which is also zero. - * Nasid starts on bit 40. */ -#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x)) -#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) +#define SH1_TIO_PHYS_TO_DMA(x) \ + ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x)) + +#define SH2_NETWORK_BANK_OFFSET(x) \ + ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1)) + +#define SH2_NETWORK_BANK_SELECT(x) \ + ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \ + >> (sn_hub_info->nasid_shift - 4)) << 36) + +#define SH2_NETWORK_ADDRESS(x) \ + (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x)) + +#define SH2_TIO_PHYS_TO_DMA(x) \ + (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x)) + +#define PHYS_TO_TIODMA(x) \ + (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x)) + +#define PHYS_TO_DMA(x) \ + ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) /* * Macros to test for address type. */ -#define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE) -#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE) +#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE) +#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE) /* @@ -180,18 +190,20 @@ #define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \ ((u64) (w) << TIO_SWIN_SIZE_BITS)) #define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n)) -#define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n)) +#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n)) #define BWIN_SIZE (1UL << BWIN_SIZE_BITS) #define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE) #define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS)) #define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS)) #define BWIN_WIDGET_MASK 0x7 #define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) +#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP) #define TIO_BWIN_WINDOW_SELECT_MASK 0x7 #define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK) - +#define TIO_HWIN_SHIFT_BITS 33 +#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS) /* * The following definitions pertain to the IO special address @@ -216,10 +228,6 @@ #define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) -#define TIO_IOSPACE_ADDR(n,x) \ - /* Move in the Chiplet ID for TIO Local Block MMR */ \ - (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)) - /* * The following macros produce the correct base virtual address for * the hub registers. The REMOTE_HUB_* macro produce @@ -234,18 +242,40 @@ * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). * They're always safe. */ +/* Shub1 TIO & MMR addressing macros */ +#define SH1_TIO_IOSPACE_ADDR(n,x) \ + GLOBAL_MMR_ADDR(n,x) + +#define SH1_REMOTE_BWIN_MMR(n,x) \ + GLOBAL_MMR_ADDR(n,x) + +#define SH1_REMOTE_SWIN_MMR(n,x) \ + (NODE_SWIN_BASE(n,1) + 0x800000UL + (x)) + +#define SH1_REMOTE_MMR(n,x) \ + (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \ + SH1_REMOTE_SWIN_MMR(n,x)) + +/* Shub1 TIO & MMR addressing macros */ +#define SH2_TIO_IOSPACE_ADDR(n,x) \ + ((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))) + +#define SH2_REMOTE_MMR(n,x) \ + GLOBAL_MMR_ADDR(n,x) + + +/* TIO & MMR addressing macros that work on both shub1 & shub2 */ +#define TIO_IOSPACE_ADDR(n,x) \ + ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \ + SH2_TIO_IOSPACE_ADDR(n,x))) + +#define SH_REMOTE_MMR(n,x) \ + (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x)) + #define REMOTE_HUB_ADDR(n,x) \ - ((n & 1) ? \ - /* TIO: */ \ - (is_shub2() ? \ - /* TIO on Shub2 */ \ - (volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \ - : /* TIO on shub1 */ \ - (volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \ - \ - : /* SHUB1 and SHUB2 MMRs: */ \ - (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \ - : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x))))) + (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \ + ((volatile u64*)SH_REMOTE_MMR(n,x))) + #define HUB_L(x) (*((volatile typeof(*x) *)x)) #define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d)) diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h index 84b254603b8d..f083c9434066 100644 --- a/include/asm-ia64/sn/geo.h +++ b/include/asm-ia64/sn/geo.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_GEO_H @@ -108,7 +108,6 @@ typedef union geoid_u { #define INVALID_SLAB (slabid_t)-1 #define INVALID_SLOT (slotid_t)-1 #define INVALID_MODULE ((moduleid_t)-1) -#define INVALID_PARTID ((partid_t)-1) static inline slabid_t geo_slab(geoid_t g) { diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index e190dd4213d5..e35074f526d9 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h @@ -12,13 +12,12 @@ #include <linux/rcupdate.h> #define SGI_UART_VECTOR (0xe9) -#define SGI_PCIBR_ERROR (0x33) /* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */ #define SGI_XPC_ACTIVATE (0x30) #define SGI_II_ERROR (0x31) #define SGI_XBOW_ERROR (0x32) -#define SGI_PCIBR_ERROR (0x33) +#define SGI_PCIASIC_ERROR (0x33) #define SGI_ACPI_SCI_INT (0x34) #define SGI_TIOCA_ERROR (0x35) #define SGI_TIO_ERROR (0x36) diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index 7138b1eafd6b..47bb8100fd00 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h @@ -37,7 +37,6 @@ struct phys_cpuid { struct nodepda_s { void *pdinfo; /* Platform-dependent per-node info */ - spinlock_t bist_lock; /* * The BTEs on this node are shared by the local cpus @@ -55,6 +54,8 @@ struct nodepda_s { * Array of physical cpu identifiers. Indexed by cpuid. */ struct phys_cpuid phys_cpuid[NR_CPUS]; + spinlock_t ptc_lock ____cacheline_aligned_in_smp; + spinlock_t bist_lock; }; typedef struct nodepda_s nodepda_t; diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h index f9b8d2164007..2b42d9ece26b 100644 --- a/include/asm-ia64/sn/pcibr_provider.h +++ b/include/asm-ia64/sn/pcibr_provider.h @@ -128,7 +128,7 @@ pcibr_lock(struct pcibus_info *pcibus_info) #define pcibr_unlock(pcibus_info, flag) spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag) extern int pcibr_init_provider(void); -extern void *pcibr_bus_fixup(struct pcibus_bussoft *); +extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *); extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t); extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t); extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int); diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h index 04e27d5b3820..ad0e8e8ae53f 100644 --- a/include/asm-ia64/sn/pcibus_provider_defs.h +++ b/include/asm-ia64/sn/pcibus_provider_defs.h @@ -18,8 +18,9 @@ #define PCIIO_ASIC_TYPE_PIC 2 #define PCIIO_ASIC_TYPE_TIOCP 3 #define PCIIO_ASIC_TYPE_TIOCA 4 +#define PCIIO_ASIC_TYPE_TIOCE 5 -#define PCIIO_ASIC_MAX_TYPES 5 +#define PCIIO_ASIC_MAX_TYPES 6 /* * Common pciio bus provider data. There should be one of these as the @@ -30,13 +31,15 @@ struct pcibus_bussoft { uint32_t bs_asic_type; /* chipset type */ uint32_t bs_xid; /* xwidget id */ - uint64_t bs_persist_busnum; /* Persistent Bus Number */ + uint32_t bs_persist_busnum; /* Persistent Bus Number */ + uint32_t bs_persist_segment; /* Segment Number */ uint64_t bs_legacy_io; /* legacy io pio addr */ uint64_t bs_legacy_mem; /* legacy mem pio addr */ uint64_t bs_base; /* widget base */ struct xwidget_info *bs_xwidget_info; }; +struct pci_controller; /* * SN pci bus indirection */ @@ -45,7 +48,9 @@ struct sn_pcibus_provider { dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t); dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t); void (*dma_unmap)(struct pci_dev *, dma_addr_t, int); - void * (*bus_fixup)(struct pcibus_bussoft *); + void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *); + void (*force_interrupt)(struct sn_irq_info *); + void (*target_interrupt)(struct sn_irq_info *); }; extern struct sn_pcibus_provider *sn_pci_provider[]; diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h index ea5590c76ca4..1c5108d44d8b 100644 --- a/include/asm-ia64/sn/pda.h +++ b/include/asm-ia64/sn/pda.h @@ -39,7 +39,6 @@ typedef struct pda_s { unsigned long pio_write_status_val; volatile unsigned long *pio_shub_war_cam_addr; - unsigned long sn_soft_irr[4]; unsigned long sn_in_service_ivecs[4]; int sn_lb_int_war_ticks; int sn_last_irq; diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h index cf770e246af5..16a48b5a039c 100644 --- a/include/asm-ia64/sn/simulator.h +++ b/include/asm-ia64/sn/simulator.h @@ -13,16 +13,9 @@ #define SNMAGIC 0xaeeeeeee8badbeefL #define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;}) -#ifdef CONFIG_IA64_SGI_SN_SIM #define SIMULATOR_SLEEP() asm("nop.i 0x8beef") -#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type) +#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type) #define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2) extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */ -#else -#define IS_RUNNING_ON_SIMULATOR() (0) -#define IS_RUNNING_ON_FAKE_PROM() (0) -#define SIMULATOR_SLEEP() - -#endif #endif /* _ASM_IA64_SN_SIMULATOR_H */ diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h index df75f4c4aec3..291ef3d69da2 100644 --- a/include/asm-ia64/sn/sn2/sn_hwperf.h +++ b/include/asm-ia64/sn/sn2/sn_hwperf.h @@ -43,6 +43,7 @@ struct sn_hwperf_object_info { /* macros for object classification */ #define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub")) +#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2.")) #define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO")) #define SN_HWPERF_IS_ROUTER(x) ((x) && strstr((x)->name, "Router")) #define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router")) @@ -214,6 +215,15 @@ struct sn_hwperf_ioctl_args { */ #define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT) +/* + * Given a node id, determine the id of the nearest node with CPUs + * and the id of the nearest node that has memory. The argument + * node would normally be a "headless" node, e.g. an "IO node". + * Return 0 on success. + */ +extern int sn_hwperf_get_nearest_node(cnodeid_t node, + cnodeid_t *near_mem, cnodeid_t *near_cpu); + /* return codes */ #define SN_HWPERF_OP_OK 0 #define SN_HWPERF_OP_NOMEM 1 diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index 27976d223186..e67825ad1930 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -55,7 +55,6 @@ #define SN_SAL_BUS_CONFIG 0x02000037 #define SN_SAL_SYS_SERIAL_GET 0x02000038 #define SN_SAL_PARTITION_SERIAL_GET 0x02000039 -#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a #define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b #define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c #define SN_SAL_COHERENCE 0x0200003d @@ -78,7 +77,8 @@ #define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060 #define SN_SAL_BTE_RECOVER 0x02000061 -#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000062 +#define SN_SAL_RESERVED_DO_NOT_USE 0x02000062 +#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000064 /* * Service-specific constants @@ -586,35 +586,6 @@ sn_partition_serial_number_val(void) { } /* - * Returns the partition id of the nasid passed in as an argument, - * or INVALID_PARTID if the partition id cannot be retrieved. - */ -static inline partid_t -ia64_sn_sysctl_partition_get(nasid_t nasid) -{ - struct ia64_sal_retval ret_stuff; - ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid, - 0, 0, 0, 0, 0, 0); - if (ret_stuff.status != 0) - return INVALID_PARTID; - return ((partid_t)ret_stuff.v0); -} - -/* - * Returns the partition id of the current processor. - */ - -extern partid_t sn_partid; - -static inline partid_t -sn_local_partid(void) { - if (unlikely(sn_partid < 0)) { - sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id())); - } - return sn_partid; -} - -/* * Returns the physical address of the partition's reserved page through * an iterative number of calls. * @@ -749,7 +720,8 @@ ia64_sn_power_down(void) { struct ia64_sal_retval ret_stuff; SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0); - while(1); + while(1) + cpu_relax(); /* never returns */ } @@ -1018,24 +990,6 @@ ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift, ret_stuff.v2 = 0; SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0); -/***** BEGIN HACK - temp til old proms no longer supported ********/ - if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) { - int nasid = get_sapicid() & 0xfff;; -#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL -#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48 - if (shubtype) *shubtype = 0; - if (nasid_bitmask) *nasid_bitmask = 0x7ff; - if (nasid_shift) *nasid_shift = 38; - if (systemsize) *systemsize = 11; - if (sharing_domain_size) *sharing_domain_size = 9; - if (partid) *partid = ia64_sn_sysctl_partition_get(nasid); - if (coher) *coher = nasid >> 9; - if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >> - SH_SHUB_ID_NODES_PER_BIT_SHFT; - return 0; - } -/***** END HACK *******/ - if (ret_stuff.status < 0) return ret_stuff.status; @@ -1068,12 +1022,10 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2, } static inline int -ia64_sn_ioif_get_pci_topology(u64 rack, u64 bay, u64 slot, u64 slab, - u64 buf, u64 len) +ia64_sn_ioif_get_pci_topology(u64 buf, u64 len) { struct ia64_sal_retval rv; - SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, - rack, bay, slot, slab, buf, len, 0); + SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0); return (int) rv.status; } diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h new file mode 100644 index 000000000000..22879853e46c --- /dev/null +++ b/include/asm-ia64/sn/tioce.h @@ -0,0 +1,740 @@ +/************************************************************************** + * * + * Unpublished copyright (c) 2005, Silicon Graphics, Inc. * + * THIS IS UNPUBLISHED CONFIDENTIAL AND PROPRIETARY SOURCE CODE OF SGI. * + * * + * The copyright notice above does not evidence any actual or intended * + * publication or disclosure of this source code, which includes * + * information that is confidential and/or proprietary, and is a trade * + * secret, of Silicon Graphics, Inc. ANY REPRODUCTION, MODIFICATION, * + * DISTRIBUTION, PUBLIC PERFORMANCE, OR PUBLIC DISPLAY OF OR THROUGH * + * USE OF THIS SOURCE CODE WITHOUT THE EXPRESS WRITTEN CONSENT OF * + * SILICON GRAPHICS, INC. IS STRICTLY PROHIBITED, AND IN VIOLATION OF * + * APPLICABLE LAWS AND INTERNATIONAL TREATIES. THE RECEIPT OR * + * POSSESSION OF THIS SOURCE CODE AND/OR RELATED INFORMATION DOES NOT * + * CONVEY OR IMPLY ANY RIGHTS TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS * + * CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY * + * DESCRIBE, IN WHOLE OR IN PART. * + * * + **************************************************************************/ + +#ifndef __ASM_IA64_SN_TIOCE_H__ +#define __ASM_IA64_SN_TIOCE_H__ + +/* CE ASIC part & mfgr information */ +#define TIOCE_PART_NUM 0xCE00 +#define TIOCE_MFGR_NUM 0x36 +#define TIOCE_REV_A 0x1 + +/* CE Virtual PPB Vendor/Device IDs */ +#define CE_VIRT_PPB_VENDOR_ID 0x10a9 +#define CE_VIRT_PPB_DEVICE_ID 0x4002 + +/* CE Host Bridge Vendor/Device IDs */ +#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9 +#define CE_HOST_BRIDGE_DEVICE_ID 0x4003 + + +#define TIOCE_NUM_M40_ATES 4096 +#define TIOCE_NUM_M3240_ATES 2048 +#define TIOCE_NUM_PORTS 2 + +/* + * Register layout for TIOCE. MMR offsets are shown at the far right of the + * structure definition. + */ +typedef volatile struct tioce { + /* + * ADMIN : Administration Registers + */ + uint64_t ce_adm_id; /* 0x000000 */ + uint64_t ce_pad_000008; /* 0x000008 */ + uint64_t ce_adm_dyn_credit_status; /* 0x000010 */ + uint64_t ce_adm_last_credit_status; /* 0x000018 */ + uint64_t ce_adm_credit_limit; /* 0x000020 */ + uint64_t ce_adm_force_credit; /* 0x000028 */ + uint64_t ce_adm_control; /* 0x000030 */ + uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */ + uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */ + uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */ + uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */ + uint64_t ce_adm_int_status; /* 0x000058 */ + uint64_t ce_adm_int_status_alias; /* 0x000060 */ + uint64_t ce_adm_int_mask; /* 0x000068 */ + uint64_t ce_adm_int_pending; /* 0x000070 */ + uint64_t ce_adm_force_int; /* 0x000078 */ + uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */ + uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */ + uint64_t ce_adm_error_summary; /* 0x000100 */ + uint64_t ce_adm_error_summary_alias; /* 0x000108 */ + uint64_t ce_adm_error_mask; /* 0x000110 */ + uint64_t ce_adm_first_error; /* 0x000118 */ + uint64_t ce_adm_error_overflow; /* 0x000120 */ + uint64_t ce_adm_error_overflow_alias; /* 0x000128 */ + uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */ + uint64_t ce_adm_tnum_error; /* 0x000140 */ + uint64_t ce_adm_mmr_err_detail; /* 0x000148 */ + uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */ + uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */ + uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */ + uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */ + uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */ + uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */ + uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */ + + uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */ + uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */ + uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */ + uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */ + uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */ + uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */ + uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */ + uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */ + uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */ + uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */ + uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */ + uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */ + uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */ + uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */ + uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */ + uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */ + uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */ + + uint64_t ce_adm_bap_ctrl; /* 0x000400 */ + uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */ + + uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */ + uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */ + + uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */ + uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */ + + uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */ + uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */ + + uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */ + + /* + * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2) + * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000 + * NOTE: the comment offsets at far right: let 'z' = {2 or 3} + */ + #define ce_lsi(link_num) ce_lsi[link_num-1] + struct ce_lsi_reg { + uint64_t ce_lsi_lpu_id; /* 0x00z000 */ + uint64_t ce_lsi_rst; /* 0x00z008 */ + uint64_t ce_lsi_dbg_stat; /* 0x00z010 */ + uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */ + uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */ + uint64_t ce_lsi_lk_stat; /* 0x00z028 */ + uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */ + uint64_t ce_lsi_int_and_stat; /* 0x00z040 */ + uint64_t ce_lsi_int_mask; /* 0x00z048 */ + uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */ + uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */ + uint64_t ce_pad_00z108; /* 0x00z108 */ + uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */ + uint64_t ce_pad_00z118; /* 0x00z118 */ + uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */ + uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */ + uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */ + uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */ + uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */ + uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */ + uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */ + uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */ + uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */ + uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */ + uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */ + uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */ + uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */ + uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */ + uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */ + uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */ + uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */ + uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */ + uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */ + uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */ + uint64_t ce_lsi_rply_tmr; /* 0x00z418 */ + uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */ + uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */ + uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */ + uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */ + uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */ + uint64_t ce_lsi_seq_cnt; /* 0x00z448 */ + uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */ + uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */ + uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */ + uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */ + uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */ + uint64_t ce_pad_00z478; /* 0x00z478 */ + uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */ + uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */ + uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */ + uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */ + uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */ + uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */ + uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */ + uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */ + uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */ + uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */ + uint64_t ce_pad_00z4D8; /* 0x00z4D8 */ + uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */ + uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */ + uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */ + uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */ + uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */ + uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */ + uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */ + uint64_t ce_pad_00z608; /* 0x00z608 */ + uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */ + uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */ + uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */ + uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */ + uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */ + uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */ + uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */ + uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */ + uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */ + uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */ + uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */ + uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */ + uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */ + uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */ + uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */ + uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */ + uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */ + uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */ + uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */ + uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */ + uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */ + uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */ + uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */ + uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */ + uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */ + uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */ + uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */ + uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */ + uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */ + uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */ + uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */ + uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */ + uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */ + uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */ + uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */ + uint64_t ce_lsi_gb_stat; /* 0x00z820 */ + uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */ + uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */ + uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */ + uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */ + uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */ + uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */ + } ce_lsi[2]; + + uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */ + + /* + * CRM: Coretalk Receive Module Registers + */ + uint64_t ce_crm_debug_mux; /* 0x004050 */ + uint64_t ce_pad_004058; /* 0x004058 */ + uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */ + uint64_t ce_crm_ssp_err_addr; /* 0x004068 */ + uint64_t ce_crm_ssp_err_syn; /* 0x004070 */ + + uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */ + + /* + * CXM: Coretalk Xmit Module Registers + */ + uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */ + uint64_t ce_cxm_last_credit_status; /* 0x005018 */ + uint64_t ce_cxm_credit_limit; /* 0x005020 */ + uint64_t ce_cxm_force_credit; /* 0x005028 */ + uint64_t ce_cxm_disable_bypass; /* 0x005030 */ + uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */ + uint64_t ce_cxm_debug_mux; /* 0x005050 */ + + uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */ + + /* + * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2) + * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000 + * DTL: the comment offsets at far right: let 'y' = {6 or 8} + * + * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2) + * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000 + * UTL: the comment offsets at far right: let 'z' = {7 or 9} + */ + #define ce_dtl(link_num) ce_dtl_utl[link_num-1] + #define ce_utl(link_num) ce_dtl_utl[link_num-1] + struct ce_dtl_utl_reg { + /* DTL */ + uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */ + uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */ + uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */ + uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */ + uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */ + uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */ + uint64_t ce_dtl_debug_sel; /* 0x00y050 */ + uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */ + + /* UTL */ + uint64_t ce_utl_utl_ctrl; /* 0x00z000 */ + uint64_t ce_utl_debug_sel; /* 0x00z008 */ + uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */ + } ce_dtl_utl[2]; + + uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */ + + /* + * URE: Upstream Request Engine + */ + uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */ + uint64_t ce_ure_last_credit_status; /* 0x00B018 */ + uint64_t ce_ure_credit_limit; /* 0x00B020 */ + uint64_t ce_pad_00B028; /* 0x00B028 */ + uint64_t ce_ure_control; /* 0x00B030 */ + uint64_t ce_ure_status; /* 0x00B038 */ + uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */ + uint64_t ce_ure_debug_sel; /* 0x00B050 */ + uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */ + uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */ + uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */ + uint64_t ce_ure_page_map; /* 0x00B070 */ + uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */ + uint64_t ce_ure_pipe_sel1; /* 0x00B088 */ + uint64_t ce_ure_pipe_mask1; /* 0x00B090 */ + uint64_t ce_ure_pipe_sel2; /* 0x00B098 */ + uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */ + uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */ + uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */ + uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */ + uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */ + uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */ + uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */ + uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */ + uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */ + uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */ + uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */ + uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */ + uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */ + uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */ + uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */ + uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */ + uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */ + uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */ + uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */ + uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */ + uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */ + uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */ + uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */ + uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */ + uint64_t ce_ure_buf_flush10; /* 0x00B160 */ + uint64_t ce_ure_buf_flush11; /* 0x00B168 */ + uint64_t ce_ure_buf_flush12; /* 0x00B170 */ + uint64_t ce_ure_buf_flush13; /* 0x00B178 */ + uint64_t ce_ure_buf_flush20; /* 0x00B180 */ + uint64_t ce_ure_buf_flush21; /* 0x00B188 */ + uint64_t ce_ure_buf_flush22; /* 0x00B190 */ + uint64_t ce_ure_buf_flush23; /* 0x00B198 */ + uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */ + uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */ + + uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */ + + /* Upstream Data Buffer, Port1 */ + struct ce_ure_maint_ups_dat1_data { + uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */ + uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */ + uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */ + } ce_ure_maint_ups_dat1; + + /* Upstream Header Buffer, Port1 */ + struct ce_ure_maint_ups_hdr1_data { + uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */ + uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */ + uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */ + } ce_ure_maint_ups_hdr1; + + /* Upstream Data Buffer, Port2 */ + struct ce_ure_maint_ups_dat2_data { + uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */ + uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */ + uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */ + } ce_ure_maint_ups_dat2; + + /* Upstream Header Buffer, Port2 */ + struct ce_ure_maint_ups_hdr2_data { + uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */ + uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */ + uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */ + } ce_ure_maint_ups_hdr2; + + /* Downstream Data Buffer */ + struct ce_ure_maint_dns_dat_data { + uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */ + uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */ + uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */ + } ce_ure_maint_dns_dat; + + /* Downstream Header Buffer */ + struct ce_ure_maint_dns_hdr_data { + uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */ + uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */ + uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */ + } ce_ure_maint_dns_hdr; + + /* RCI Buffer Data */ + struct ce_ure_maint_rci_data { + uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */ + uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */ + } ce_ure_maint_rci; + + /* Response Queue */ + uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */ + + uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */ + + /* Admin Build-a-Packet Buffer */ + struct ce_adm_maint_bap_buf_data { + uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */ + uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */ + uint64_t parity[258]; /* 0x025020 -- 0x025828 */ + } ce_adm_maint_bap_buf; + + uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */ + + /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */ + uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES]; + + /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */ + uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES]; + + uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */ + + /* + * DRE: Down Stream Request Engine + */ + uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */ + uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */ + uint64_t ce_dre_last_credit_status1; /* 0x040020 */ + uint64_t ce_dre_last_credit_status2; /* 0x040028 */ + uint64_t ce_dre_credit_limit1; /* 0x040030 */ + uint64_t ce_dre_credit_limit2; /* 0x040038 */ + uint64_t ce_dre_force_credit1; /* 0x040040 */ + uint64_t ce_dre_force_credit2; /* 0x040048 */ + uint64_t ce_dre_debug_mux1; /* 0x040050 */ + uint64_t ce_dre_debug_mux2; /* 0x040058 */ + uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */ + uint64_t ce_dre_ssp_err_addr; /* 0x040068 */ + uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */ + uint64_t ce_dre_comp_err_addr; /* 0x040078 */ + uint64_t ce_dre_req_status; /* 0x040080 */ + uint64_t ce_dre_config1; /* 0x040088 */ + uint64_t ce_dre_config2; /* 0x040090 */ + uint64_t ce_dre_config_req_status; /* 0x040098 */ + uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */ + uint64_t ce_dre_dyn_fifo; /* 0x040100 */ + uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */ + uint64_t ce_dre_last_fifo; /* 0x040120 */ + + uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */ + + /* DRE Downstream Head Queue */ + struct ce_dre_maint_ds_head_queue { + uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */ + uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */ + uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */ + } ce_dre_maint_ds_head_q; + + uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */ + + /* DRE Downstream Data Queue */ + struct ce_dre_maint_ds_data_queue { + uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */ + uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */ + uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */ + uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */ + uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */ + uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */ + } ce_dre_maint_ds_data_q; + + /* DRE URE Upstream Response Queue */ + struct ce_dre_maint_ure_us_rsp_queue { + uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */ + uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */ + uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */ + uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */ + uint64_t parity[8]; /* 0x044200 -- 0x044238 */ + uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */ + } ce_dre_maint_ure_us_rsp_q; + + uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */ + + uint64_t ce_end_of_struct; /* 0x044400 */ +} tioce_t; + + +/* ce_adm_int_mask/ce_adm_int_status register bit defines */ +#define CE_ADM_INT_CE_ERROR_SHFT 0 +#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1 +#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2 +#define CE_ADM_INT_PCIE_ERROR_SHFT 3 +#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4 +#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5 +#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6 +#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7 +#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8 +#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9 +#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10 +#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11 +#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12 +#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13 +#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/ +#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14 +#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15 +#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16 +#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17 +#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22 +#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23 + +/* ce_adm_force_int register bit defines */ +#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0 +#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1 +#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2 +#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3 +#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4 +#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5 +#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6 +#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7 +#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8 + +/* ce_adm_int_dest register bit masks & shifts */ +#define INTR_VECTOR_SHFT 56 + +/* ce_adm_error_mask and ce_adm_error_summary register bit masks */ +#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0) +#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1) +#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2) +#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3) +#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4) +#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5) +#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6) +#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7) +#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8) +#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9) +#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10) +#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11) +#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12) +#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13) +#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14) +#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15) +#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16) +#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17) +#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18) +#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19) +#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20) +#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21) +#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22) +#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23) +#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24) +#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25) +#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26) +#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27) +#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28) +#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29) +#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30) +#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31) +#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32) +#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33) +#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34) +#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35) +#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36) +#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37) +#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38) +#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39) +#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40) +#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41) +#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42) +#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43) +#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44) +#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45) +#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46) +#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47) +#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48) +#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49) +#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50) +#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51) +#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52) +#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53) +#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54) +#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55) +#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56) +#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57) +#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58) +#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59) +#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60) +#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61) + +/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */ +#define FLUSH_SEL_PORT1_PIPE0_SHFT 0 +#define FLUSH_SEL_PORT1_PIPE1_SHFT 4 +#define FLUSH_SEL_PORT1_PIPE2_SHFT 8 +#define FLUSH_SEL_PORT1_PIPE3_SHFT 12 +#define FLUSH_SEL_PORT2_PIPE0_SHFT 16 +#define FLUSH_SEL_PORT2_PIPE1_SHFT 20 +#define FLUSH_SEL_PORT2_PIPE2_SHFT 24 +#define FLUSH_SEL_PORT2_PIPE3_SHFT 28 + +/* ce_dre_config1 register bit masks and shifts */ +#define CE_DRE_RO_ENABLE (0x1ULL << 0) +#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1) +#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2) +#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3) +#define CE_DRE_ADDR_MODE_SHFT 4 + +/* ce_dre_config_req_status register bit masks */ +#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0) +#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3) +#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4) +#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5) + +/* ce_ure_control register bit masks & shifts */ +#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0) +#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4) +#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5) +#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24) +#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32) +#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33) +#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34) +#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35) +#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36) +#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37) +#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38) +#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39) +#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40) +#define CE_URE_MALFORM_DISABLE (0x1ULL << 44) +#define CE_URE_UNSUP_DISABLE (0x1ULL << 45) + +/* ce_ure_page_map register bit masks & shifts */ +#define CE_URE_ATE3240_ENABLE (0x1ULL << 0) +#define CE_URE_ATE40_ENABLE (0x1ULL << 1) +#define CE_URE_PAGESIZE_SHFT 4 +#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT) +#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT) +#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT) +#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT) +#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT) +#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT) + +/* ce_ure_pipe_sel register bit masks & shifts */ +#define PKT_TRAFIC_SHRT 16 +#define BUS_SRC_ID_SHFT 8 +#define DEV_SRC_ID_SHFT 3 +#define FNC_SRC_ID_SHFT 0 +#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT) +#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT) +#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT) +#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT) +#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \ + CE_URE_BUS_MASK) +#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \ + CE_URE_DEV_MASK) +#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \ + CE_URE_FNC_MASK) + +#define CE_URE_SEL1_SHFT 0 +#define CE_URE_SEL2_SHFT 20 +#define CE_URE_SEL3_SHFT 40 +#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT) +#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT) +#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT) + + +/* ce_ure_pipe_mask register bit masks & shifts */ +#define CE_URE_MASK1_SHFT 0 +#define CE_URE_MASK2_SHFT 20 +#define CE_URE_MASK3_SHFT 40 +#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT) +#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT) +#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT) + + +/* ce_ure_pcie_control1 register bit masks & shifts */ +#define CE_URE_SI (0x1ULL << 0) +#define CE_URE_ELAL_SHFT 4 +#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT) +#define CE_URE_ELAL1_SHFT 8 +#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT) +#define CE_URE_SCC (0x1ULL << 12) +#define CE_URE_PN1_SHFT 16 +#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT) +#define CE_URE_PN2_SHFT 24 +#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT) +#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \ + CE_URE_PN1_MASK) +#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \ + CE_URE_PN2_MASK) + +/* ce_ure_pcie_control2 register bit masks & shifts */ +#define CE_URE_ABP (0x1ULL << 0) +#define CE_URE_PCP (0x1ULL << 1) +#define CE_URE_MSP (0x1ULL << 2) +#define CE_URE_AIP (0x1ULL << 3) +#define CE_URE_PIP (0x1ULL << 4) +#define CE_URE_HPS (0x1ULL << 5) +#define CE_URE_HPC (0x1ULL << 6) +#define CE_URE_SPLV_SHFT 7 +#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT) +#define CE_URE_SPLS_SHFT 15 +#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT) +#define CE_URE_PSN1_SHFT 19 +#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT) +#define CE_URE_PSN2_SHFT 32 +#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT) +#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \ + CE_URE_PSN1_MASK) +#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \ + CE_URE_PSN2_MASK) + +/* + * PIO address space ranges for CE + */ + +/* Local CE Registers Space */ +#define CE_PIO_MMR 0x00000000 +#define CE_PIO_MMR_LEN 0x04000000 + +/* PCI Compatible Config Space */ +#define CE_PIO_CONFIG_SPACE 0x04000000 +#define CE_PIO_CONFIG_SPACE_LEN 0x04000000 + +/* PCI I/O Space Alias */ +#define CE_PIO_IO_SPACE_ALIAS 0x08000000 +#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000 + +/* PCI Enhanced Config Space */ +#define CE_PIO_E_CONFIG_SPACE 0x10000000 +#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000 + +/* PCI I/O Space */ +#define CE_PIO_IO_SPACE 0x100000000 +#define CE_PIO_IO_SPACE_LEN 0x100000000 + +/* PCI MEM Space */ +#define CE_PIO_MEM_SPACE 0x200000000 +#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE + + +/* + * CE PCI Enhanced Config Space shifts & masks + */ +#define CE_E_CONFIG_BUS_SHFT 20 +#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT) +#define CE_E_CONFIG_DEVICE_SHFT 15 +#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT) +#define CE_E_CONFIG_FUNC_SHFT 12 +#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT) + +#endif /* __ASM_IA64_SN_TIOCE_H__ */ diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h new file mode 100644 index 000000000000..7f63dec0a79a --- /dev/null +++ b/include/asm-ia64/sn/tioce_provider.h @@ -0,0 +1,66 @@ +/************************************************************************** + * Copyright (C) 2005, Silicon Graphics, Inc. * + * * + * These coded instructions, statements, and computer programs contain * + * unpublished proprietary information of Silicon Graphics, Inc., and * + * are protected by Federal copyright law. They may not be disclosed * + * to third parties or copied or duplicated in any form, in whole or * + * in part, without the prior written consent of Silicon Graphics, Inc. * + * * + **************************************************************************/ + +#ifndef _ASM_IA64_SN_CE_PROVIDER_H +#define _ASM_IA64_SN_CE_PROVIDER_H + +#include <asm/sn/pcibus_provider_defs.h> +#include <asm/sn/tioce.h> + +/* + * Common TIOCE structure shared between the prom and kernel + * + * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE + * PROM VERSION. + */ +struct tioce_common { + struct pcibus_bussoft ce_pcibus; /* common pciio header */ + + uint32_t ce_rev; + uint64_t ce_kernel_private; + uint64_t ce_prom_private; +}; + +struct tioce_kernel { + struct tioce_common *ce_common; + spinlock_t ce_lock; + struct list_head ce_dmamap_list; + + uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES]; + uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES]; + uint32_t ce_ate3240_pagesize; + + uint8_t ce_port1_secondary; + + /* per-port resources */ + struct { + int dirmap_refcnt; + uint64_t dirmap_shadow; + } ce_port[TIOCE_NUM_PORTS]; +}; + +struct tioce_dmamap { + struct list_head ce_dmamap_list; /* headed by tioce_kernel */ + uint32_t refcnt; + + uint64_t nbytes; /* # bytes mapped */ + + uint64_t ct_start; /* coretalk start address */ + uint64_t pci_start; /* bus start address */ + + uint64_t *ate_hw; /* hw ptr of first ate in map */ + uint64_t *ate_shadow; /* shadow ptr of firat ate */ + uint16_t ate_count; /* # ate's in the map */ +}; + +extern int tioce_init_provider(void); + +#endif /* __ASM_IA64_SN_CE_PROVIDER_H */ diff --git a/include/asm-ia64/socket.h b/include/asm-ia64/socket.h index 21a9f10d6baa..a255006fb7b5 100644 --- a/include/asm-ia64/socket.h +++ b/include/asm-ia64/socket.h @@ -23,6 +23,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h index 909936f25512..d2430aa0d49d 100644 --- a/include/asm-ia64/spinlock.h +++ b/include/asm-ia64/spinlock.h @@ -93,7 +93,15 @@ _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags) # endif /* CONFIG_MCKINLEY */ #endif } + #define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0) + +/* Unlock by doing an ordered store and releasing the cacheline with nta */ +static inline void _raw_spin_unlock(spinlock_t *x) { + barrier(); + asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x)); +} + #else /* !ASM_SUPPORTED */ #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) # define _raw_spin_lock(x) \ @@ -109,16 +117,16 @@ do { \ } while (ia64_spinlock_val); \ } \ } while (0) +#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0) #endif /* !ASM_SUPPORTED */ #define spin_is_locked(x) ((x)->lock != 0) -#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0) #define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0) #define spin_unlock_wait(x) do { barrier(); } while ((x)->lock) typedef struct { - volatile unsigned int read_counter : 31; - volatile unsigned int write_lock : 1; + volatile unsigned int read_counter : 24; + volatile unsigned int write_lock : 8; #ifdef CONFIG_PREEMPT unsigned int break_lock; #endif @@ -174,6 +182,13 @@ do { \ (result == 0); \ }) +static inline void _raw_write_unlock(rwlock_t *x) +{ + u8 *y = (u8 *)x; + barrier(); + asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" ); +} + #else /* !ASM_SUPPORTED */ #define _raw_write_lock(l) \ @@ -195,14 +210,14 @@ do { \ (ia64_val == 0); \ }) +static inline void _raw_write_unlock(rwlock_t *x) +{ + barrier(); + x->write_lock = 0; +} + #endif /* !ASM_SUPPORTED */ #define _raw_read_trylock(lock) generic_raw_read_trylock(lock) -#define _raw_write_unlock(x) \ -({ \ - smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ \ - clear_bit(31, (x)); \ -}) - #endif /* _ASM_IA64_SPINLOCK_H */ diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index cd2cf76b2db1..33256db4a7cf 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h @@ -19,12 +19,13 @@ #include <asm/pal.h> #include <asm/percpu.h> -#define GATE_ADDR __IA64_UL_CONST(0xa000000000000000) +#define GATE_ADDR RGN_BASE(RGN_GATE) + /* * 0xa000000000000000+2*PERCPU_PAGE_SIZE * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page) */ -#define KERNEL_START __IA64_UL_CONST(0xa000000100000000) +#define KERNEL_START (GATE_ADDR+0x100000000) #define PERCPU_ADDR (-PERCPU_PAGE_SIZE) #ifndef __ASSEMBLY__ diff --git a/include/asm-ia64/topology.h b/include/asm-ia64/topology.h index 4e64c2a6b369..399bc29729fd 100644 --- a/include/asm-ia64/topology.h +++ b/include/asm-ia64/topology.h @@ -40,6 +40,11 @@ */ #define node_to_first_cpu(node) (__ffs(node_to_cpumask(node))) +/* + * Determines the node for a given pci bus + */ +#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node + void build_cpu_to_node_map(void); #define SD_CPU_INIT (struct sched_domain) { \ diff --git a/include/asm-ia64/types.h b/include/asm-ia64/types.h index a677565aa954..902850d12424 100644 --- a/include/asm-ia64/types.h +++ b/include/asm-ia64/types.h @@ -67,8 +67,6 @@ typedef __u64 u64; typedef u64 dma_addr_t; -typedef unsigned short kmem_bufctl_t; - # endif /* __KERNEL__ */ #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index 517f1649ee64..3a0c69524656 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h @@ -266,6 +266,9 @@ #define __NR_ioprio_set 1274 #define __NR_ioprio_get 1275 #define __NR_set_zone_reclaim 1276 +#define __NR_inotify_init 1277 +#define __NR_inotify_add_watch 1278 +#define __NR_inotify_rm_watch 1279 #ifdef __KERNEL__ diff --git a/include/asm-m32r/checksum.h b/include/asm-m32r/checksum.h index 99f37dbf2558..877ebf46e9ff 100644 --- a/include/asm-m32r/checksum.h +++ b/include/asm-m32r/checksum.h @@ -105,7 +105,7 @@ static inline unsigned short ip_fast_csum(unsigned char * iph, " addx %0, %3 \n" " .fillinsn\n" "2: \n" - /* Since the input registers which are loaded with iph and ipl + /* Since the input registers which are loaded with iph and ihl are modified, we must also specify them as outputs, or gcc will assume they contain their original values. */ : "=&r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmpreg0), "=&r" (tmpreg1) diff --git a/include/asm-m32r/emergency-restart.h b/include/asm-m32r/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-m32r/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-m32r/page.h b/include/asm-m32r/page.h index 1c6abb9f3f1f..4ab578876361 100644 --- a/include/asm-m32r/page.h +++ b/include/asm-m32r/page.h @@ -61,25 +61,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* This handles the memory map.. */ -#ifndef __ASSEMBLY__ - -/* Pure 2^n version of get_order */ -static __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size - 1) >> (PAGE_SHIFT - 1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - - return order; -} - -#endif /* __ASSEMBLY__ */ - #define __MEMORY_START CONFIG_MEMORY_START #define __MEMORY_SIZE CONFIG_MEMORY_SIZE @@ -111,5 +92,7 @@ static __inline__ int get_order(unsigned long size) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _ASM_M32R_PAGE_H */ diff --git a/include/asm-m32r/smp.h b/include/asm-m32r/smp.h index b9a20cdad65f..7885b7df84a2 100644 --- a/include/asm-m32r/smp.h +++ b/include/asm-m32r/smp.h @@ -61,9 +61,7 @@ extern physid_mask_t phys_cpu_present_map; * Some lowlevel functions might want to know about * the real CPU ID <-> CPU # mapping. */ -extern volatile int physid_2_cpu[NR_CPUS]; extern volatile int cpu_2_physid[NR_CPUS]; -#define physid_to_cpu(physid) physid_2_cpu[physid] #define cpu_to_physid(cpu_id) cpu_2_physid[cpu_id] #define raw_smp_processor_id() (current_thread_info()->cpu) diff --git a/include/asm-m32r/socket.h b/include/asm-m32r/socket.h index 159519d99042..8b6680f223c0 100644 --- a/include/asm-m32r/socket.h +++ b/include/asm-m32r/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-m32r/types.h b/include/asm-m32r/types.h index ca0a887d2237..fcf24c64c3ba 100644 --- a/include/asm-m32r/types.h +++ b/include/asm-m32r/types.h @@ -55,8 +55,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u64 dma64_addr_t; -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-m68k/cacheflush.h b/include/asm-m68k/cacheflush.h index e4773946f10d..8aba971b1368 100644 --- a/include/asm-m68k/cacheflush.h +++ b/include/asm-m68k/cacheflush.h @@ -130,20 +130,25 @@ static inline void __flush_page_to_ram(void *vaddr) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) #define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page)) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - do { \ - flush_cache_page(vma, vaddr, page_to_pfn(page));\ - memcpy(dst, src, len); \ - } while (0) - -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - do { \ - flush_cache_page(vma, vaddr, page_to_pfn(page));\ - memcpy(dst, src, len); \ - } while (0) +extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, + unsigned long addr, int len); extern void flush_icache_range(unsigned long address, unsigned long endaddr); +static inline void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, + void *dst, void *src, int len) +{ + flush_cache_page(vma, vaddr, page_to_pfn(page)); + memcpy(dst, src, len); + flush_icache_user_range(vma, page, vaddr, len); +} +static inline void copy_from_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, + void *dst, void *src, int len) +{ + flush_cache_page(vma, vaddr, page_to_pfn(page)); + memcpy(dst, src, len); +} + #endif /* _M68K_CACHEFLUSH_H */ diff --git a/include/asm-m68k/emergency-restart.h b/include/asm-m68k/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-m68k/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-m68k/page.h b/include/asm-m68k/page.h index 99a516709210..f206dfbc1d48 100644 --- a/include/asm-m68k/page.h +++ b/include/asm-m68k/page.h @@ -107,20 +107,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #endif /* !__ASSEMBLY__ */ #include <asm/page_offset.h> @@ -138,13 +124,13 @@ extern unsigned long m68k_memoffset; #define __pa(vaddr) ((unsigned long)(vaddr)+m68k_memoffset) #define __va(paddr) ((void *)((unsigned long)(paddr)-m68k_memoffset)) #else -#define __pa(vaddr) virt_to_phys((void *)vaddr) -#define __va(paddr) phys_to_virt((unsigned long)paddr) +#define __pa(vaddr) virt_to_phys((void *)(vaddr)) +#define __va(paddr) phys_to_virt((unsigned long)(paddr)) #endif #else /* !CONFIG_SUN3 */ /* This #define is a horrible hack to suppress lots of warnings. --m */ -#define __pa(x) ___pa((unsigned long)x) +#define __pa(x) ___pa((unsigned long)(x)) static inline unsigned long ___pa(unsigned long x) { if(x == 0) @@ -192,4 +178,6 @@ static inline void *__va(unsigned long x) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _M68K_PAGE_H */ diff --git a/include/asm-m68k/pci.h b/include/asm-m68k/pci.h index 9e7d79ab5d13..9d2c07abe44f 100644 --- a/include/asm-m68k/pci.h +++ b/include/asm-m68k/pci.h @@ -43,7 +43,7 @@ static inline void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -static inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-m68k/socket.h b/include/asm-m68k/socket.h index 8d0b9fc2d07e..f578ca4b776a 100644 --- a/include/asm-m68k/socket.h +++ b/include/asm-m68k/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-m68k/string.h b/include/asm-m68k/string.h index 44def078132a..6c59215b285e 100644 --- a/include/asm-m68k/string.h +++ b/include/asm-m68k/string.h @@ -80,43 +80,6 @@ static inline char * strchr(const char * s, int c) return( (char *) s); } -#if 0 -#define __HAVE_ARCH_STRPBRK -static inline char *strpbrk(const char *cs,const char *ct) -{ - const char *sc1,*sc2; - - for( sc1 = cs; *sc1 != '\0'; ++sc1) - for( sc2 = ct; *sc2 != '\0'; ++sc2) - if (*sc1 == *sc2) - return((char *) sc1); - return( NULL ); -} -#endif - -#if 0 -#define __HAVE_ARCH_STRSPN -static inline size_t strspn(const char *s, const char *accept) -{ - const char *p; - const char *a; - size_t count = 0; - - for (p = s; *p != '\0'; ++p) - { - for (a = accept; *a != '\0'; ++a) - if (*p == *a) - break; - if (*a == '\0') - return count; - else - ++count; - } - - return count; -} -#endif - /* strstr !! */ #define __HAVE_ARCH_STRLEN @@ -173,370 +136,18 @@ static inline int strncmp(const char * cs,const char * ct,size_t count) } #define __HAVE_ARCH_MEMSET -/* - * This is really ugly, but its highly optimizatiable by the - * compiler and is meant as compensation for gcc's missing - * __builtin_memset(). For the 680[23]0 it might be worth considering - * the optimal number of misaligned writes compared to the number of - * tests'n'branches needed to align the destination address. The - * 680[46]0 doesn't really care due to their copy-back caches. - * 10/09/96 - Jes Sorensen - */ -static inline void * __memset_g(void * s, int c, size_t count) -{ - void *xs = s; - size_t temp; - - if (!count) - return xs; - - c &= 0xff; - c |= c << 8; - c |= c << 16; - - if (count < 36){ - long *ls = s; - - switch(count){ - case 32: case 33: case 34: case 35: - *ls++ = c; - case 28: case 29: case 30: case 31: - *ls++ = c; - case 24: case 25: case 26: case 27: - *ls++ = c; - case 20: case 21: case 22: case 23: - *ls++ = c; - case 16: case 17: case 18: case 19: - *ls++ = c; - case 12: case 13: case 14: case 15: - *ls++ = c; - case 8: case 9: case 10: case 11: - *ls++ = c; - case 4: case 5: case 6: case 7: - *ls++ = c; - break; - default: - break; - } - s = ls; - if (count & 0x02){ - short *ss = s; - *ss++ = c; - s = ss; - } - if (count & 0x01){ - char *cs = s; - *cs++ = c; - s = cs; - } - return xs; - } - - if ((long) s & 1) - { - char *cs = s; - *cs++ = c; - s = cs; - count--; - } - if (count > 2 && (long) s & 2) - { - short *ss = s; - *ss++ = c; - s = ss; - count -= 2; - } - temp = count >> 2; - if (temp) - { - long *ls = s; - temp--; - do - *ls++ = c; - while (temp--); - s = ls; - } - if (count & 2) - { - short *ss = s; - *ss++ = c; - s = ss; - } - if (count & 1) - { - char *cs = s; - *cs = c; - } - return xs; -} - -/* - * __memset_page assumes that data is longword aligned. Most, if not - * all, of these page sized memsets are performed on page aligned - * areas, thus we do not need to check if the destination is longword - * aligned. Of course we suffer a serious performance loss if this is - * not the case but I think the risk of this ever happening is - * extremely small. We spend a lot of time clearing pages in - * get_empty_page() so I think it is worth it anyway. Besides, the - * 680[46]0 do not really care about misaligned writes due to their - * copy-back cache. - * - * The optimized case for the 680[46]0 is implemented using the move16 - * instruction. My tests showed that this implementation is 35-45% - * faster than the original implementation using movel, the only - * caveat is that the destination address must be 16-byte aligned. - * 01/09/96 - Jes Sorensen - */ -static inline void * __memset_page(void * s,int c,size_t count) -{ - unsigned long data, tmp; - void *xs = s; - - c = c & 255; - data = c | (c << 8); - data |= data << 16; - -#ifdef CPU_M68040_OR_M68060_ONLY - - if (((unsigned long) s) & 0x0f) - __memset_g(s, c, count); - else{ - unsigned long *sp = s; - *sp++ = data; - *sp++ = data; - *sp++ = data; - *sp++ = data; - - __asm__ __volatile__("1:\t" - ".chip 68040\n\t" - "move16 %2@+,%0@+\n\t" - ".chip 68k\n\t" - "subqw #8,%2\n\t" - "subqw #8,%2\n\t" - "dbra %1,1b\n\t" - : "=a" (sp), "=d" (tmp) - : "a" (s), "0" (sp), "1" ((count - 16) / 16 - 1) - ); - } - -#else - __asm__ __volatile__("1:\t" - "movel %2,%0@+\n\t" - "movel %2,%0@+\n\t" - "movel %2,%0@+\n\t" - "movel %2,%0@+\n\t" - "movel %2,%0@+\n\t" - "movel %2,%0@+\n\t" - "movel %2,%0@+\n\t" - "movel %2,%0@+\n\t" - "dbra %1,1b\n\t" - : "=a" (s), "=d" (tmp) - : "d" (data), "0" (s), "1" (count / 32 - 1) - ); -#endif - - return xs; -} - -extern void *memset(void *,int,__kernel_size_t); - -#define __memset_const(s,c,count) \ -((count==PAGE_SIZE) ? \ - __memset_page((s),(c),(count)) : \ - __memset_g((s),(c),(count))) - -#define memset(s, c, count) \ -(__builtin_constant_p(count) ? \ - __memset_const((s),(c),(count)) : \ - __memset_g((s),(c),(count))) +extern void *memset(void *, int, __kernel_size_t); +#define memset(d, c, n) __builtin_memset(d, c, n) #define __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, size_t ); -/* - * __builtin_memcpy() does not handle page-sized memcpys very well, - * thus following the same assumptions as for page-sized memsets, this - * function copies page-sized areas using an unrolled loop, without - * considering alignment. - * - * For the 680[46]0 only kernels we use the move16 instruction instead - * as it writes through the data-cache, invalidating the cache-lines - * touched. In this way we do not use up the entire data-cache (well, - * half of it on the 68060) by copying a page. An unrolled loop of two - * move16 instructions seem to the fastest. The only caveat is that - * both source and destination must be 16-byte aligned, if not we fall - * back to the generic memcpy function. - Jes - */ -static inline void * __memcpy_page(void * to, const void * from, size_t count) -{ - unsigned long tmp; - void *xto = to; - -#ifdef CPU_M68040_OR_M68060_ONLY - - if (((unsigned long) to | (unsigned long) from) & 0x0f) - return memcpy(to, from, count); - - __asm__ __volatile__("1:\t" - ".chip 68040\n\t" - "move16 %1@+,%0@+\n\t" - "move16 %1@+,%0@+\n\t" - ".chip 68k\n\t" - "dbra %2,1b\n\t" - : "=a" (to), "=a" (from), "=d" (tmp) - : "0" (to), "1" (from) , "2" (count / 32 - 1) - ); -#else - __asm__ __volatile__("1:\t" - "movel %1@+,%0@+\n\t" - "movel %1@+,%0@+\n\t" - "movel %1@+,%0@+\n\t" - "movel %1@+,%0@+\n\t" - "movel %1@+,%0@+\n\t" - "movel %1@+,%0@+\n\t" - "movel %1@+,%0@+\n\t" - "movel %1@+,%0@+\n\t" - "dbra %2,1b\n\t" - : "=a" (to), "=a" (from), "=d" (tmp) - : "0" (to), "1" (from) , "2" (count / 32 - 1) - ); -#endif - return xto; -} - -#define __memcpy_const(to, from, n) \ -((n==PAGE_SIZE) ? \ - __memcpy_page((to),(from),(n)) : \ - __builtin_memcpy((to),(from),(n))) - -#define memcpy(to, from, n) \ -(__builtin_constant_p(n) ? \ - __memcpy_const((to),(from),(n)) : \ - memcpy((to),(from),(n))) +extern void *memcpy(void *, const void *, __kernel_size_t); +#define memcpy(d, s, n) __builtin_memcpy(d, s, n) #define __HAVE_ARCH_MEMMOVE -static inline void * memmove(void * dest,const void * src, size_t n) -{ - void *xdest = dest; - size_t temp; - - if (!n) - return xdest; - - if (dest < src) - { - if ((long) dest & 1) - { - char *cdest = dest; - const char *csrc = src; - *cdest++ = *csrc++; - dest = cdest; - src = csrc; - n--; - } - if (n > 2 && (long) dest & 2) - { - short *sdest = dest; - const short *ssrc = src; - *sdest++ = *ssrc++; - dest = sdest; - src = ssrc; - n -= 2; - } - temp = n >> 2; - if (temp) - { - long *ldest = dest; - const long *lsrc = src; - temp--; - do - *ldest++ = *lsrc++; - while (temp--); - dest = ldest; - src = lsrc; - } - if (n & 2) - { - short *sdest = dest; - const short *ssrc = src; - *sdest++ = *ssrc++; - dest = sdest; - src = ssrc; - } - if (n & 1) - { - char *cdest = dest; - const char *csrc = src; - *cdest = *csrc; - } - } - else - { - dest = (char *) dest + n; - src = (const char *) src + n; - if ((long) dest & 1) - { - char *cdest = dest; - const char *csrc = src; - *--cdest = *--csrc; - dest = cdest; - src = csrc; - n--; - } - if (n > 2 && (long) dest & 2) - { - short *sdest = dest; - const short *ssrc = src; - *--sdest = *--ssrc; - dest = sdest; - src = ssrc; - n -= 2; - } - temp = n >> 2; - if (temp) - { - long *ldest = dest; - const long *lsrc = src; - temp--; - do - *--ldest = *--lsrc; - while (temp--); - dest = ldest; - src = lsrc; - } - if (n & 2) - { - short *sdest = dest; - const short *ssrc = src; - *--sdest = *--ssrc; - dest = sdest; - src = ssrc; - } - if (n & 1) - { - char *cdest = dest; - const char *csrc = src; - *--cdest = *--csrc; - } - } - return xdest; -} +extern void *memmove(void *, const void *, __kernel_size_t); #define __HAVE_ARCH_MEMCMP -extern int memcmp(const void * ,const void * ,size_t ); -#define memcmp(cs, ct, n) \ -(__builtin_constant_p(n) ? \ - __builtin_memcmp((cs),(ct),(n)) : \ - memcmp((cs),(ct),(n))) - -#define __HAVE_ARCH_MEMCHR -static inline void *memchr(const void *cs, int c, size_t count) -{ - /* Someone else can optimize this, I don't care - tonym@mac.linux-m68k.org */ - unsigned char *ret = (unsigned char *)cs; - for(;count>0;count--,ret++) - if(*ret == c) return ret; - - return NULL; -} +extern int memcmp(const void *, const void *, __kernel_size_t); +#define memcmp(d, s, n) __builtin_memcmp(d, s, n) #endif /* _M68K_STRING_H_ */ diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h index f391cbe39b96..b5a1febc97d4 100644 --- a/include/asm-m68k/types.h +++ b/include/asm-m68k/types.h @@ -60,8 +60,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u32 dma64_addr_t; -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-m68knommu/emergency-restart.h b/include/asm-m68knommu/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-m68knommu/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-m68knommu/page.h b/include/asm-m68knommu/page.h index 05e03df0ec29..942dfbead27f 100644 --- a/include/asm-m68knommu/page.h +++ b/include/asm-m68knommu/page.h @@ -48,20 +48,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - extern unsigned long memory_start; extern unsigned long memory_end; @@ -73,8 +59,8 @@ extern unsigned long memory_end; #ifndef __ASSEMBLY__ -#define __pa(vaddr) virt_to_phys((void *)vaddr) -#define __va(paddr) phys_to_virt((unsigned long)paddr) +#define __pa(vaddr) virt_to_phys((void *)(vaddr)) +#define __va(paddr) phys_to_virt((unsigned long)(paddr)) #define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) #define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) @@ -84,6 +70,7 @@ extern unsigned long memory_end; #define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) #define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) +#define pfn_valid(pfn) ((pfn) < max_mapnr) #define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ ((void *)(kaddr) < (void *)memory_end)) @@ -92,4 +79,6 @@ extern unsigned long memory_end; #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _M68KNOMMU_PAGE_H */ diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index e42b3093e903..2b3dc3bed4da 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h @@ -35,10 +35,10 @@ struct exec #ifdef __KERNEL__ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define STACK_TOP TASK_SIZE #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) #endif diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 2caa8c427204..7dc2619f5006 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -48,7 +48,7 @@ #define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff) #define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * Memory segments (64bit kernel mode addresses) diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index 37a460aa0378..30b18ea6cb11 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -7,14 +7,14 @@ */ #ifndef _ASM_ASMMACRO_H #define _ASM_ASMMACRO_H - + #include <linux/config.h> #include <asm/hazards.h> - -#ifdef CONFIG_MIPS32 + +#ifdef CONFIG_32BIT #include <asm/asmmacro-32.h> #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #include <asm/asmmacro-64.h> #endif diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 7d89e87bc8c6..c0bd8d014e14 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -334,7 +334,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) */ #define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT typedef struct { volatile __s64 counter; } atomic64_t; @@ -639,7 +639,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) */ #define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* * atomic*_return operations are serializing but not the non-*_return diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 779d2187a6a4..eb8d79dba11c 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -20,13 +20,13 @@ #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " -#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) +#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " #define __SC "scd " -#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) +#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif #ifdef __KERNEL__ @@ -533,14 +533,14 @@ static inline unsigned long ffz(unsigned long word) int b = 0, s; word = ~word; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 31 != 0) s = 0; b += s; #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s; s = 8; if (word << 56 != 0) s = 0; b += s; word >>= s; @@ -683,7 +683,7 @@ found_middle: */ static inline int sched_find_first_bit(const unsigned long *b) { -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT if (unlikely(b[0])) return __ffs(b[0]); if (unlikely(b[1])) @@ -694,7 +694,7 @@ static inline int sched_find_first_bit(const unsigned long *b) return __ffs(b[3]) + 96; return __ffs(b[4]) + 128; #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (unlikely(b[0])) return __ffs(b[0]); if (unlikely(b[1])) diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h index 18cced19cca4..b14b961c2100 100644 --- a/include/asm-mips/bugs.h +++ b/include/asm-mips/bugs.h @@ -15,7 +15,7 @@ extern void check_bugs64(void); static inline void check_bugs(void) { check_bugs32(); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT check_bugs64(); #endif } diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h index c25cc92b9950..c1ea5a8714f3 100644 --- a/include/asm-mips/checksum.h +++ b/include/asm-mips/checksum.h @@ -128,7 +128,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr, { __asm__( ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t" -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT "addu\t%0, %2\n\t" "sltu\t$1, %0, %2\n\t" "addu\t%0, $1\n\t" @@ -141,7 +141,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr, "sltu\t$1, %0, %4\n\t" "addu\t%0, $1\n\t" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT "daddu\t%0, %2\n\t" "daddu\t%0, %3\n\t" "daddu\t%0, %4\n\t" diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 1df2c299de82..9a2de642eee6 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -106,7 +106,7 @@ #define PLAT_TRAMPOLINE_STUFF_LINE 0UL #endif -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) # endif @@ -124,7 +124,7 @@ # endif #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex 0 # endif diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h index ae3e2a38fd5f..a438548e6ef3 100644 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ b/include/asm-mips/ddb5xxx/ddb5477.h @@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); * All PCI irq but INTC are active low. */ -/* +/* * irq number block assignment */ @@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); #define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ #define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ #define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ -#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) +#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) #define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ #define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ #define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ @@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); /* * i2859 irq assignment */ -#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) +#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) #define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */ #define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE) #define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h index b63e2f2317d1..a05d6d3395fe 100644 --- a/include/asm-mips/dec/prom.h +++ b/include/asm-mips/dec/prom.h @@ -48,15 +48,15 @@ */ #define REX_PROM_MAGIC 0x30464354 -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ -#else /* !CONFIG_MIPS64 */ +#else /* !CONFIG_64BIT */ #define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC) -#endif /* !CONFIG_MIPS64 */ +#endif /* !CONFIG_64BIT */ /* @@ -105,7 +105,7 @@ extern int (*__pmax_read)(int, void *, int); extern int (*__pmax_close)(int); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * On MIPS64 we have to call PROM functions via a helper @@ -138,7 +138,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; #define prom_getenv(x) _prom_getenv(__prom_getenv, x) #define prom_printf(x...) _prom_printf(__prom_printf, x) -#else /* !CONFIG_MIPS64 */ +#else /* !CONFIG_64BIT */ /* * On plain MIPS we just call PROM functions directly. @@ -160,7 +160,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; #define pmax_read __pmax_read #define pmax_close __pmax_close -#endif /* !CONFIG_MIPS64 */ +#endif /* !CONFIG_64BIT */ extern void prom_meminit(u32); diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index d0f68447e5a7..a606dbee0412 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -57,11 +57,11 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj) * The common rates of 1000 and 128 are rounded wrongly by the * catchall case for 64-bit. Excessive precission? Probably ... */ -#if defined(CONFIG_MIPS64) && (HZ == 128) +#if defined(CONFIG_64BIT) && (HZ == 128) usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */ -#elif defined(CONFIG_MIPS64) && (HZ == 1000) +#elif defined(CONFIG_64BIT) && (HZ == 1000) usecs *= 0x004189374BC6A7f0UL; /* 2**64 / (1000000 / HZ) */ -#elif defined(CONFIG_MIPS64) +#elif defined(CONFIG_64BIT) usecs *= (0x8000000000000000UL / (500000 / HZ)); #else /* 32-bit junk follows here */ usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) + diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index 7b92c8045cc2..e48811440015 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -125,7 +125,7 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * This is used to ensure we don't load something for the wrong architecture. @@ -153,9 +153,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; */ #define ELF_CLASS ELFCLASS32 -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * This is used to ensure we don't load something for the wrong architecture. */ @@ -177,7 +177,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; */ #define ELF_CLASS ELFCLASS64 -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* * These are used to set parameters in the core dumps. @@ -193,7 +193,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #ifdef __KERNEL__ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define SET_PERSONALITY(ex, ibcs2) \ do { \ @@ -202,9 +202,9 @@ do { \ set_personality(PER_LINUX); \ } while (0) -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define SET_PERSONALITY(ex, ibcs2) \ do { current->thread.mflags &= ~MF_ABI_MASK; \ @@ -222,7 +222,7 @@ do { current->thread.mflags &= ~MF_ABI_MASK; \ set_personality(PER_LINUX); \ } while (0) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ extern void dump_regs(elf_greg_t *, struct pt_regs *regs); extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); diff --git a/include/asm-mips/emergency-restart.h b/include/asm-mips/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-mips/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h index 1d9aa0979181..2b5fddc8f487 100644 --- a/include/asm-mips/fpregdef.h +++ b/include/asm-mips/fpregdef.h @@ -13,7 +13,7 @@ #define _ASM_FPREGDEF_H #include <asm/sgidefs.h> - + #if _MIPS_SIM == _MIPS_SIM_ABI32 /* @@ -56,7 +56,7 @@ #define fcr31 $31 /* FPU status register */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 #define fv0 $f0 /* return value */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 6cb38d5c0407..ea24e733b1bc 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -82,7 +82,7 @@ do { \ static inline int is_fpu_owner(void) { - return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); + return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); } static inline void own_fpu(void) @@ -90,7 +90,7 @@ static inline void own_fpu(void) if (cpu_has_fpu) { __enable_fpu(); KSTK_STATUS(current) |= ST0_CU1; - set_thread_flag(TIF_USEDFPU); + set_thread_flag(TIF_USEDFPU); } } @@ -98,7 +98,7 @@ static inline void lose_fpu(void) { if (cpu_has_fpu) { KSTK_STATUS(current) &= ~ST0_CU1; - clear_thread_flag(TIF_USEDFPU); + clear_thread_flag(TIF_USEDFPU); __disable_fpu(); } } @@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk) static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) { if (cpu_has_fpu) { - if ((tsk == current) && is_fpu_owner()) + if ((tsk == current) && is_fpu_owner()) _save_fp(current); return tsk->thread.fpu.hard.fpr; } diff --git a/include/asm-mips/hp-lj/asic.h b/include/asm-mips/hp-lj/asic.h deleted file mode 100644 index fc2ca656da00..000000000000 --- a/include/asm-mips/hp-lj/asic.h +++ /dev/null @@ -1,7 +0,0 @@ - -typedef enum { IllegalAsic, UnknownAsic, AndrosAsic, HarmonyAsic } AsicId; - -AsicId GetAsicId(void); - -const char* const GetAsicName(void); - diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h index 2b7b0fdeac19..432011b16c26 100644 --- a/include/asm-mips/ip32/mace.h +++ b/include/asm-mips/ip32/mace.h @@ -94,7 +94,7 @@ struct mace_video { unsigned long xxx; /* later... */ }; -/* +/* * Ethernet interface */ struct mace_ethernet { @@ -129,7 +129,7 @@ struct mace_ethernet { volatile unsigned long rx_fifo; }; -/* +/* * Peripherals */ @@ -251,7 +251,7 @@ struct mace_timers { timer_reg audio_out2; timer_reg video_in1; timer_reg video_in2; - timer_reg video_out; + timer_reg video_out; }; struct mace_perif { @@ -272,7 +272,7 @@ struct mace_perif { }; -/* +/* * ISA peripherals */ diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h index 21d0fb7cee64..9e88c7669c7a 100644 --- a/include/asm-mips/lasat/serial.h +++ b/include/asm-mips/lasat/serial.h @@ -1,13 +1,13 @@ #include <asm/lasat/lasat.h> /* Lasat 100 boards serial configuration */ -#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) +#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) #define LASAT_UART_REGS_BASE_100 0x1c8b0000 #define LASAT_UART_REGS_SHIFT_100 2 #define LASATINT_UART_100 8 /* * LASAT 200 boards serial configuration */ -#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) +#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) #define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) #define LASAT_UART_REGS_SHIFT_200 3 #define LASATINT_UART_200 13 diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h index 7eb6bf661b80..c38844f615fc 100644 --- a/include/asm-mips/local.h +++ b/include/asm-mips/local.h @@ -5,7 +5,7 @@ #include <linux/percpu.h> #include <asm/atomic.h> -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT typedef atomic_t local_t; @@ -20,7 +20,7 @@ typedef atomic_t local_t; #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT typedef atomic64_t local_t; diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 2b36ea346910..148bae2fa7d3 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define PCI_IO_START 0 #define PCI_IO_END 0 #define PCI_MEM_START 0 -#define PCI_MEM_END 0 +#define PCI_MEM_END 0 #define PCI_FIRST_DEVFN 0 #define PCI_LAST_DEVFN 0 #endif diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 4691398a414f..efafe65258b6 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -23,7 +23,7 @@ * * ######################################################################## * - * + * */ #ifndef __ASM_DB1X00_H #define __ASM_DB1X00_H diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h index 63c0a81c7832..5a2c1efb4eb7 100644 --- a/include/asm-mips/mach-generic/spaces.h +++ b/include/asm-mips/mach-generic/spaces.h @@ -12,7 +12,7 @@ #include <linux/config.h> -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define CAC_BASE 0x80000000 #define IO_BASE 0xa0000000 @@ -32,9 +32,9 @@ #define HIGHMEM_START 0x20000000UL #endif -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * This handles the memory map. @@ -67,6 +67,6 @@ #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h index 30d42fcafe3d..e96166f27c49 100644 --- a/include/asm-mips/mach-ip22/spaces.h +++ b/include/asm-mips/mach-ip22/spaces.h @@ -12,7 +12,7 @@ #include <linux/config.h> -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define CAC_BASE 0x80000000 #define IO_BASE 0xa0000000 @@ -32,9 +32,9 @@ #define HIGHMEM_START 0x20000000UL #endif -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define PAGE_OFFSET 0xffffffff80000000UL #ifndef HIGHMEM_START @@ -50,6 +50,6 @@ #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* __ASM_MACH_IP22_SPACES_H */ diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index b932237f2193..04713973c6c3 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -18,7 +18,7 @@ * so, for 64bit IP32 kernel we just don't use ll/sc. * This does not affect luserland. */ -#if defined(CONFIG_CPU_R5000) && defined(CONFIG_MIPS64) +#if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT) #define cpu_has_llsc 0 #else #define cpu_has_llsc 1 diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h index 8cf0d042c864..c9dad99b1232 100644 --- a/include/asm-mips/mach-jazz/floppy.h +++ b/include/asm-mips/mach-jazz/floppy.h @@ -92,7 +92,7 @@ static inline int fd_request_irq(void) return request_irq(FLOPPY_IRQ, floppy_interrupt, SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL); } - + static inline void fd_free_irq(void) { free_irq(FLOPPY_IRQ, NULL); diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h index d6c779747b3c..ff6d40c87a25 100644 --- a/include/asm-mips/mach-pb1x00/pb1500.h +++ b/include/asm-mips/mach-pb1x00/pb1500.h @@ -33,11 +33,11 @@ #define PCI_BOARD_REG 0xAE000010 #define PCMCIA_BOARD_REG 0xAE000010 #define PC_DEASSERT_RST 0x80 - #define PC_DRV_EN 0x10 + #define PC_DRV_EN 0x10 #define PB1500_G_CONTROL 0xAE000014 #define PB1500_RST_VDDI 0xAE00001C #define PB1500_LEDS 0xAE000018 - + #define PB1500_HEX_LED 0xAF000004 #define PB1500_HEX_LED_BLANK 0xAF000008 diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h new file mode 100644 index 000000000000..f4e370e27168 --- /dev/null +++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h @@ -0,0 +1,31 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H + +/* + * QEMU only comes with a hazard-free MIPS32 processor, so things are easy. + */ +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_dsp 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 + +#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-qemu/param.h b/include/asm-mips/mach-qemu/param.h new file mode 100644 index 000000000000..cb30ee490ae6 --- /dev/null +++ b/include/asm-mips/mach-qemu/param.h @@ -0,0 +1,13 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 by Ralf Baechle + */ +#ifndef __ASM_MACH_QEMU_PARAM_H +#define __ASM_MACH_QEMU_PARAM_H + +#define HZ 100 /* Internal kernel timer frequency */ + +#endif /* __ASM_MACH_QEMU_PARAM_H */ diff --git a/include/asm-mips/mach-vr41xx/timex.h b/include/asm-mips/mach-vr41xx/timex.h deleted file mode 100644 index 8d71485d003a..000000000000 --- a/include/asm-mips/mach-vr41xx/timex.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 by Ralf Baechle - */ -/* - * Changes: - * Yoichi Yuasa <yuasa@hh.iij4u.or.jp> - * - CLOCK_TICK_RATE is changed into 32768 from 6144000. - */ -#ifndef __ASM_MACH_VR41XX_TIMEX_H -#define __ASM_MACH_VR41XX_TIMEX_H - -#define CLOCK_TICK_RATE 32768 - -#endif /* __ASM_MACH_VR41XX_TIMEX_H */ diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 48b77c9fb4f2..45cd72d172e8 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -28,17 +28,17 @@ extern unsigned long pgd_current[]; #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ pgd_current[smp_processor_id()] = (unsigned long)(pgd) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) &pgd_current[smp_processor_id()] << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif -#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 90ee24aad955..0be58b2aeb9f 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -25,7 +25,7 @@ typedef struct Elf64_Sxword r_addend; /* Addend. */ } Elf64_Mips_Rela; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define Elf_Shdr Elf32_Shdr #define Elf_Sym Elf32_Sym @@ -33,7 +33,7 @@ typedef struct #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define Elf_Shdr Elf64_Shdr #define Elf_Sym Elf64_Sym diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h index 513b2824838b..a1533959742e 100644 --- a/include/asm-mips/msgbuf.h +++ b/include/asm-mips/msgbuf.h @@ -15,25 +15,25 @@ struct msqid64_ds { struct ipc64_perm msg_perm; -#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused1; #endif __kernel_time_t msg_stime; /* last msgsnd time */ -#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused1; #endif -#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused2; #endif __kernel_time_t msg_rtime; /* last msgrcv time */ -#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused2; #endif -#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused3; #endif __kernel_time_t msg_ctime; /* last change time */ -#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused3; #endif unsigned long msg_cbytes; /* current number of bytes on queue */ diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h index 36cec9e31696..309bc3099f68 100644 --- a/include/asm-mips/paccess.h +++ b/include/asm-mips/paccess.h @@ -16,10 +16,10 @@ #include <linux/config.h> #include <linux/errno.h> -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __PA_ADDR ".word" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define __PA_ADDR ".dword" #endif diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 5cae35cd9ba9..652b6d67a571 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -103,20 +103,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) -/* Pure 2^n version of get_order */ -static __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #endif /* !__ASSEMBLY__ */ /* to align the pointer to the (next) page boundary */ @@ -148,4 +134,6 @@ static __inline__ int get_order(unsigned long size) #define WANT_PAGE_VIRTUAL #endif +#include <asm-generic/page.h> + #endif /* _ASM_PAGE_H */ diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 2d323b6e147d..c9a00ca1c012 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -69,7 +69,7 @@ extern unsigned long PCIBIOS_MIN_MEM; extern void pcibios_set_master(struct pci_dev *dev); -static inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } @@ -94,7 +94,7 @@ struct pci_dev; */ extern unsigned int PCI_DMA_BUS_IS_PHYS; -#ifdef CONFIG_MAPPED_DMA_IO +#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE /* pci_unmap_{single,page} is not a nop, thus... */ #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME; @@ -104,7 +104,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; #define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) -#else /* CONFIG_MAPPED_DMA_IO */ +#else /* CONFIG_DMA_NEED_PCI_MAP_STATE */ /* pci_unmap_{page,single} is a nop so... */ #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) @@ -114,7 +114,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; #define pci_unmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -#endif /* CONFIG_MAPPED_DMA_IO */ +#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ /* This is always fine. */ #define pci_dac_dma_supported(pci_dev, mask) (1) @@ -142,6 +142,8 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void pcibios_bus_to_resource(struct pci_dev *dev, + struct resource *res, struct pci_bus_region *region); #ifdef CONFIG_PCI_DOMAINS @@ -167,4 +169,17 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev) /* Do platform specific device initialization at pci_enable_device() time */ extern int pcibios_plat_dev_init(struct pci_dev *dev); +static inline struct resource * +pcibios_select_root(struct pci_dev *pdev, struct resource *res) +{ + struct resource *root = NULL; + + if (res->flags & IORESOURCE_IO) + root = &ioport_resource; + if (res->flags & IORESOURCE_MEM) + root = &iomem_resource; + + return root; +} + #endif /* _ASM_PCI_H */ diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index 2d63f5ba403f..ce57288d43bd 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -85,7 +85,7 @@ static inline void pte_free(struct page *pte) #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define pgd_populate(mm, pmd, pte) BUG() /* @@ -97,7 +97,7 @@ static inline void pte_free(struct page *pte) #define __pmd_free_tlb(tlb,x) do { } while (0) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define pgd_populate(mm, pgd, pmd) set_pgd(pgd, __pgd(pmd)) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index e76ccd6e3a5d..dbe13da0bdad 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -11,10 +11,10 @@ #include <asm-generic/4level-fixup.h> #include <linux/config.h> -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #include <asm/pgtable-32.h> #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #include <asm/pgtable-64.h> #endif diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 13c54d5b3b48..d6466aa09fb7 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -33,7 +33,7 @@ extern void (*cpu_wait)(void); extern unsigned int vced_count, vcei_count; -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. @@ -47,7 +47,7 @@ extern unsigned int vced_count, vcei_count; #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * User space process size: 1TB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. TASK_SIZE diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index d3c46d633826..2b5c624c3d4f 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -28,7 +28,7 @@ * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* Pad bytes for argument save space on the stack. */ unsigned long pad0[6]; #endif diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h new file mode 100644 index 000000000000..905c39585903 --- /dev/null +++ b/include/asm-mips/qemu.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_QEMU_H +#define __ASM_QEMU_H + +/* + * Interrupt numbers + */ +#define Q_PIC_IRQ_BASE 0 +#define Q_COUNT_COMPARE_IRQ 16 + +/* + * Qemu clock rate. Unlike on real MIPS this has no relation to the + * instruction issue rate, so the choosen value is pure fiction, just needs + * to match the value in Qemu itself. + */ +#define QEMU_C0_COUNTER_CLOCK 100000000 + +#endif /* __ASM_QEMU_H */ diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index da03a32c1ca7..5bea49feec66 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -171,11 +171,11 @@ static inline void blast_dcache16(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.dcache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << + unsigned long ws_end = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -214,8 +214,8 @@ static inline void blast_icache16(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } @@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Invalidate_I); } @@ -249,11 +249,11 @@ static inline void blast_scache16(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x200) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -318,8 +318,8 @@ static inline void blast_dcache32(void) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page) current_cpu_data.dcache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_D); } @@ -357,8 +357,8 @@ static inline void blast_icache32(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -392,11 +392,11 @@ static inline void blast_scache32(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -461,8 +461,8 @@ static inline void blast_icache64(void) current_cpu_data.icache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } @@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page) unsigned long ws, addr; for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Invalidate_I); } @@ -496,11 +496,11 @@ static inline void blast_scache64(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x800) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -561,11 +561,11 @@ static inline void blast_scache128(void) unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << + unsigned long ws_end = current_cpu_data.scache.ways << current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) + for (ws = 0; ws < ws_end; ws += ws_inc) for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } @@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page) current_cpu_data.scache.waybit; unsigned long ws, addr; - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x1000) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h index 7b33bbca9585..6173004cc88e 100644 --- a/include/asm-mips/reg.h +++ b/include/asm-mips/reg.h @@ -14,7 +14,7 @@ #include <linux/config.h> -#if defined(CONFIG_MIPS32) || defined(WANT_COMPAT_REG_H) +#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H) #define EF_R0 6 #define EF_R1 7 @@ -70,7 +70,7 @@ #endif -#if CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define EF_R0 0 #define EF_R1 1 @@ -124,6 +124,6 @@ #define EF_SIZE 304 /* size in bytes */ -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h index fd3c6d17a5f6..1fba00c22077 100644 --- a/include/asm-mips/resource.h +++ b/include/asm-mips/resource.h @@ -27,7 +27,7 @@ * but we keep the old value on MIPS32, * for compatibility: */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT # define RLIM_INFINITY 0x7fffffffUL #endif diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h index 31c0c2347f4f..3c4b637fd925 100644 --- a/include/asm-mips/rtc.h +++ b/include/asm-mips/rtc.h @@ -1,5 +1,5 @@ /* - * include/asm-mips/rtc.h + * include/asm-mips/rtc.h * * (Really an interface for drivers/char/genrtc.c) * diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h index a38d66f99872..889cf028c95d 100644 --- a/include/asm-mips/sgi/gio.h +++ b/include/asm-mips/sgi/gio.h @@ -16,7 +16,7 @@ * * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have * three physical connectors, but only two slots, GFX and EXP0. - * + * * There is 10MB of GIO address space for GIO64 slot devices * slot# slot type address range size * ----- --------- ----------------------- ----- diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h index a5b988d7327a..ac3dfc7af5b0 100644 --- a/include/asm-mips/sgi/hpc3.h +++ b/include/asm-mips/sgi/hpc3.h @@ -221,7 +221,7 @@ struct hpc3_regs { #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ u32 _unused1[0x14000/4 - 5]; /* padding */ - + /* Now direct PIO per-HPC3 peripheral access to external regs. */ volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ u32 _unused2[0x7c00/4]; @@ -304,7 +304,7 @@ struct hpc3_regs { volatile u32 bbram[8192-50-14]; /* Battery backed ram */ }; -/* +/* * It is possible to have two HPC3's within the address space on * one machine, though only having one is more likely on an Indy. */ diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h index 169187f53fbc..f3e3dc9bb732 100644 --- a/include/asm-mips/sgi/ioc.h +++ b/include/asm-mips/sgi/ioc.h @@ -16,7 +16,7 @@ #include <linux/types.h> #include <asm/sgi/pi1.h> -/* +/* * All registers are 8-bit wide alligned on 32-bit boundary. Bad things * happen if you try word access them. You have been warned. */ @@ -138,7 +138,7 @@ struct sgioc_regs { u8 _sysid[3]; volatile u8 sysid; #define SGIOC_SYSID_FULLHOUSE 0x01 -#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) +#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) #define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1) u32 _unused2; u8 _read[3]; diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h index 97d73adb4e40..bbfc05c3cab9 100644 --- a/include/asm-mips/sgi/ip22.h +++ b/include/asm-mips/sgi/ip22.h @@ -12,7 +12,7 @@ #ifndef _SGI_IP22_H #define _SGI_IP22_H -/* +/* * These are the virtual IRQ numbers, we divide all IRQ's into * 'spaces', the 'space' determines where and how to enable/disable * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h index fd98f930607c..c52f7834c7c8 100644 --- a/include/asm-mips/sgi/mc.h +++ b/include/asm-mips/sgi/mc.h @@ -182,14 +182,14 @@ struct sgimc_regs { volatile u32 dtlb_hi3; u32 _unused33; volatile u32 dtlb_lo3; - + u32 _unused34[0x0392]; - + u32 _unused35; volatile u32 rpsscounter; /* Chirps at 100ns */ u32 _unused36[0x1000/4-2*4]; - + u32 _unused37; volatile u32 maddronly; /* Address DMA goes at */ u32 _unused38; diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h index 59450335f049..722b77a8c5e5 100644 --- a/include/asm-mips/sgiarcs.h +++ b/include/asm-mips/sgiarcs.h @@ -367,7 +367,7 @@ struct linux_smonblock { * Macros for calling a 32-bit ARC implementation from 64-bit code */ -#if defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) +#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) #define __arc_clobbers \ "$2","$3" /* ... */, "$8","$9","$10","$11", \ @@ -476,10 +476,10 @@ struct linux_smonblock { __res; \ }) -#endif /* defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) */ +#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */ -#if (defined(CONFIG_MIPS32) && defined(CONFIG_ARC32)) || \ - (defined(CONFIG_MIPS64) && defined(CONFIG_ARC64)) +#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) || \ + (defined(CONFIG_64BIT) && defined(CONFIG_ARC64)) #define ARC_CALL0(dest) \ ({ long __res; \ diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h index 7ac5da13ce8a..b5e7dae19f0f 100644 --- a/include/asm-mips/sibyte/carmel.h +++ b/include/asm-mips/sibyte/carmel.h @@ -25,12 +25,12 @@ #define SIBYTE_BOARD_NAME "Carmel" -#define GPIO_PHY_INTERRUPT 2 -#define GPIO_NONMASKABLE_INT 3 -#define GPIO_CF_INSERTED 6 -#define GPIO_MONTEREY_RESET 7 -#define GPIO_QUADUART_INT 8 -#define GPIO_CF_INT 9 +#define GPIO_PHY_INTERRUPT 2 +#define GPIO_NONMASKABLE_INT 3 +#define GPIO_CF_INSERTED 6 +#define GPIO_MONTEREY_RESET 7 +#define GPIO_QUADUART_INT 8 +#define GPIO_CF_INT 9 #define GPIO_FPGA_CCLK 10 #define GPIO_FPGA_DOUT 11 #define GPIO_FPGA_DIN 12 diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h index 96088fb074a4..40ef97c76c8b 100644 --- a/include/asm-mips/sibyte/sb1250_defs.h +++ b/include/asm-mips/sibyte/sb1250_defs.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * - * Global constants and macros File: sb1250_defs.h - * + * + * Global constants and macros File: sb1250_defs.h + * * This file contains macros and definitions used by the other * include files. * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -105,7 +105,7 @@ #define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 #define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 -/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ +/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ #define SIBYTE_HDR_FMASK(chip, pass) \ (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) #define SIBYTE_HDR_FMASK_ALLREVS(chip) \ @@ -150,31 +150,31 @@ /* ********************************************************************* * Naming schemes for constants in these files: - * - * M_xxx MASK constant (identifies bits in a register). + * + * M_xxx MASK constant (identifies bits in a register). * For multi-bit fields, all bits in the field will * be set. * * K_xxx "Code" constant (value for data in a multi-bit * field). The value is right justified. * - * V_xxx "Value" constant. This is the same as the + * V_xxx "Value" constant. This is the same as the * corresponding "K_xxx" constant, except it is * shifted to the correct position in the register. * * S_xxx SHIFT constant. This is the number of bits that - * a field value (code) needs to be shifted + * a field value (code) needs to be shifted * (towards the left) to put the value in the right * position for the register. * - * A_xxx ADDRESS constant. This will be a physical + * A_xxx ADDRESS constant. This will be a physical * address. Use the PHYS_TO_K1 macro to generate * a K1SEG address. * * R_xxx RELATIVE offset constant. This is an offset from * an A_xxx constant (usually the first register in * a group). - * + * * G_xxx(X) GET value. This macro obtains a multi-bit field * from a register, masks it, and shifts it to * the bottom of the register (retrieving a K_xxx @@ -189,7 +189,7 @@ /* - * Cast to 64-bit number. Presumably the syntax is different in + * Cast to 64-bit number. Presumably the syntax is different in * assembly language. * * Note: you'll need to define uint32_t and uint64_t in your headers. diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h index f1b08d32338d..3cdb48f50ed0 100644 --- a/include/asm-mips/sibyte/sb1250_dma.h +++ b/include/asm-mips/sibyte/sb1250_dma.h @@ -1,24 +1,24 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * DMA definitions File: sb1250_dma.h - * + * * This module contains constants and macros useful for * programming the SB1250's DMA controllers, both the data mover * and the Ethernet DMA. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -28,7 +28,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -43,9 +43,9 @@ * DMA Registers ********************************************************************* */ -/* +/* * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) - * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 + * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 * Registers: DMA_CONFIG0_SER_x_RX * Registers: DMA_CONFIG0_SER_x_TX @@ -98,7 +98,7 @@ /* * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) - * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 + * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 * Registers: DMA_CONFIG1_SER_x_RX * Registers: DMA_CONFIG1_SER_x_TX @@ -152,11 +152,11 @@ /* * DMA Descriptor Count Registers (Table 7-8) */ - + /* No bitfields */ -/* +/* * Current Descriptor Address Register (Table 7-11) */ @@ -275,14 +275,14 @@ #define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) #define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) -/* +/* * Ethernet Descriptor Status Bits (Table 7-15) */ #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) +#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) /* Note: BADTCPCS is actually in DSCR_B options field */ #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) #endif /* 1250 PASS2 || 112x PASS1 */ @@ -324,7 +324,7 @@ #define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) -/* +/* * Ethernet Transmit Options (Table 7-17) */ @@ -377,7 +377,7 @@ * Data Mover Registers ********************************************************************* */ -/* +/* * Data Mover Descriptor Base Address Register (Table 7-22) * Register: DM_DSCR_BASE_0 * Register: DM_DSCR_BASE_1 @@ -414,7 +414,7 @@ #define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) #define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) -/* +/* * Data Mover Descriptor Count Register (Table 7-25) */ diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h index 0d9dfac3d7db..f1f509f295c4 100644 --- a/include/asm-mips/sibyte/sb1250_genbus.h +++ b/include/asm-mips/sibyte/sb1250_genbus.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Generic Bus Constants File: sb1250_genbus.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's Generic Bus interface - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h index c3f74df211f4..e173e2ea4c98 100644 --- a/include/asm-mips/sibyte/sb1250_int.h +++ b/include/asm-mips/sibyte/sb1250_int.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Interrupt Mapper definitions File: sb1250_int.h - * + * * This module contains constants for manipulating the SB1250's * interrupt mapper and definitions for the interrupt sources. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -43,7 +43,7 @@ /* * Interrupt sources (Table 4-8, UM 0.2) - * + * * First, the interrupt numbers. */ diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h index 799db828d963..8afe8e01581b 100644 --- a/include/asm-mips/sibyte/sb1250_l2c.h +++ b/include/asm-mips/sibyte/sb1250_l2c.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * L2 Cache constants and macros File: sb1250_l2c.h - * + * * This module contains constants useful for manipulating the * level 2 cache. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h index d8753885df17..f2617ded0a8f 100644 --- a/include/asm-mips/sibyte/sb1250_ldt.h +++ b/include/asm-mips/sibyte/sb1250_ldt.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * LDT constants File: sb1250_ldt.h - * - * This module contains constants and macros to describe - * the LDT interface on the SB1250. - * + * + * This module contains constants and macros to describe + * the LDT interface on the SB1250. + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -155,7 +155,7 @@ /* * LDT Status Register (Table 8-14). Note that these constants - * assume you've read the command and status register + * assume you've read the command and status register * together (32-bit read at offset 0x04) * * These bits also apply to the secondary status @@ -183,8 +183,8 @@ #define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) /* - * Bridge Control Register (Table 8-16). Note that these - * constants assume you've read the register as a 32-bit + * Bridge Control Register (Table 8-16). Note that these + * constants assume you've read the register as a 32-bit * read (offset 0x3C) */ diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h index 81f603f03a98..18e74e43f4a2 100644 --- a/include/asm-mips/sibyte/sb1250_mac.h +++ b/include/asm-mips/sibyte/sb1250_mac.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * MAC constants and macros File: sb1250_mac.h - * + * * This module contains constants and macros for the SB1250's * ethernet controllers. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -311,7 +311,7 @@ /* * These constants are used to configure the fields within the Frame - * Configuration Register. + * Configuration Register. */ #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ @@ -393,7 +393,7 @@ * Register: MAC_INT_MASK_2 */ -/* +/* * Use these constants to shift the appropriate channel * into the CH0 position so the same tests can be used * on each channel. diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h index 93a48334b874..1dd41c927996 100644 --- a/include/asm-mips/sibyte/sb1250_mc.h +++ b/include/asm-mips/sibyte/sb1250_mc.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * - * Memory Controller constants File: sb1250_mc.h - * + * + * Memory Controller constants File: sb1250_mc.h + * * This module contains constants and macros useful for * programming the memory controller. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -166,7 +166,7 @@ #define K_MC_REF_RATE_100MHz 0x62 #define K_MC_REF_RATE_133MHz 0x81 -#define K_MC_REF_RATE_200MHz 0xC4 +#define K_MC_REF_RATE_200MHz 0xC4 #define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) #define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) @@ -228,7 +228,7 @@ V_MC_ADDR_DRIVE_DEFAULT | \ V_MC_DATA_DRIVE_DEFAULT | \ V_MC_CLOCK_DRIVE_DEFAULT | \ - V_MC_REF_RATE_DEFAULT + V_MC_REF_RATE_DEFAULT diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h index 5d496c6faba6..9db80cd13a79 100644 --- a/include/asm-mips/sibyte/sb1250_regs.h +++ b/include/asm-mips/sibyte/sb1250_regs.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * Register Definitions File: sb1250_regs.h - * + * * This module contains the addresses of the on-chip peripherals * on the SB1250. - * + * * SB1250 specification level: 01/02/2002 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -40,20 +40,20 @@ /* ********************************************************************* * Some general notes: - * + * * For the most part, when there is more than one peripheral * of the same type on the SOC, the constants below will be * offsets from the base of each peripheral. For example, * the MAC registers are described as offsets from the first * MAC register, and there will be a MAC_REGISTER() macro - * to calculate the base address of a given MAC. - * + * to calculate the base address of a given MAC. + * * The information in this file is based on the SB1250 SOC * manual version 0.2, July 2000. ********************************************************************* */ -/* ********************************************************************* +/* ********************************************************************* * Memory Controller Registers ********************************************************************* */ @@ -101,7 +101,7 @@ #define R_MC_TEST_ECC 0x0000000420 #define R_MC_MCLK_CFG 0x0000000500 -/* ********************************************************************* +/* ********************************************************************* * L2 Cache Control Registers ********************************************************************* */ @@ -126,7 +126,7 @@ #define A_L2_EEC_ADDRESS A_L2_ECC_TAG -/* ********************************************************************* +/* ********************************************************************* * PCI Interface Registers ********************************************************************* */ @@ -134,7 +134,7 @@ #define A_PCI_TYPE01_HEADER 0x00DE000800 -/* ********************************************************************* +/* ********************************************************************* * Ethernet DMA and MACs ********************************************************************* */ @@ -184,7 +184,7 @@ (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ (reg)) -/* +/* * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE */ @@ -259,7 +259,7 @@ #define MAC_CHMAP_COUNT 4 -/* ********************************************************************* +/* ********************************************************************* * DUART Registers ********************************************************************* */ @@ -363,7 +363,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * Synchronous Serial Registers ********************************************************************* */ @@ -397,7 +397,7 @@ (reg)) -/* +/* * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE */ @@ -457,7 +457,7 @@ #define R_SER_RMON_RX_ERRORS 0x000001F0 #define R_SER_RMON_RX_BADADDR 0x000001F8 -/* ********************************************************************* +/* ********************************************************************* * Generic Bus Registers ********************************************************************* */ @@ -513,7 +513,7 @@ #define R_IO_PCMCIA_CFG 0x0A60 #define R_IO_PCMCIA_STATUS 0x0A70 -/* ********************************************************************* +/* ********************************************************************* * GPIO Registers ********************************************************************* */ @@ -537,7 +537,7 @@ #define R_GPIO_PIN_CLR 0x30 #define R_GPIO_PIN_SET 0x38 -/* ********************************************************************* +/* ********************************************************************* * SMBus Registers ********************************************************************* */ @@ -573,7 +573,7 @@ #define R_SMB_CONTROL 0x0000000060 #define R_SMB_PEC 0x0000000070 -/* ********************************************************************* +/* ********************************************************************* * Timer Registers ********************************************************************* */ @@ -641,7 +641,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * System Control Registers ********************************************************************* */ @@ -649,7 +649,7 @@ #define A_SCD_SYSTEM_CFG 0x0010020008 #define A_SCD_SYSTEM_MANUF 0x0010038000 -/* ********************************************************************* +/* ********************************************************************* * System Address Trap Registers ********************************************************************* */ @@ -672,7 +672,7 @@ #endif /* 1250 PASS2 || 112x PASS1 */ -/* ********************************************************************* +/* ********************************************************************* * System Interrupt Mapper Registers ********************************************************************* */ @@ -701,7 +701,7 @@ #define R_IMR_INTERRUPT_MAP_BASE 0x0200 #define R_IMR_INTERRUPT_MAP_COUNT 64 -/* ********************************************************************* +/* ********************************************************************* * System Performance Counter Registers ********************************************************************* */ @@ -711,7 +711,7 @@ #define A_SCD_PERF_CNT_2 0x00100204E0 #define A_SCD_PERF_CNT_3 0x00100204E8 -/* ********************************************************************* +/* ********************************************************************* * System Bus Watcher Registers ********************************************************************* */ @@ -726,13 +726,13 @@ #define A_BUS_L2_ERRORS 0x00100208C0 #define A_BUS_MEM_IO_ERRORS 0x00100208C8 -/* ********************************************************************* +/* ********************************************************************* * System Debug Controller Registers ********************************************************************* */ #define A_SCD_JTAG_BASE 0x0010000000 -/* ********************************************************************* +/* ********************************************************************* * System Trace Buffer Registers ********************************************************************* */ @@ -755,7 +755,7 @@ #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 -/* ********************************************************************* +/* ********************************************************************* * System Generic DMA Registers ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h index 22e8041959e2..dbbd682fb47e 100644 --- a/include/asm-mips/sibyte/sb1250_scd.h +++ b/include/asm-mips/sibyte/sb1250_scd.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * SCD Constants and Macros File: sb1250_scd.h - * + * * This module contains constants and macros useful for * manipulating the System Control and Debug module on the 1250. - * + * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -130,40 +130,40 @@ /* System Manufacturing Register * Register: SCD_SYSTEM_MANUF */ - + /* Wafer ID: bits 31:0 */ #define S_SYS_WAFERID1_200 _SB_MAKE64(0) #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) - + #define S_SYS_BIN _SB_MAKE64(32) #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) - + /* Wafer ID: bits 39:36 */ #define S_SYS_WAFERID2_200 _SB_MAKE64(36) #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) - + /* Wafer ID: bits 39:0 */ #define S_SYS_WAFERID_300 _SB_MAKE64(0) #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) - + #define S_SYS_XPOS _SB_MAKE64(40) #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) - + #define S_SYS_YPOS _SB_MAKE64(46) #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) - + /* * System Config Register (Table 4-2) * Register: SCD_SYSTEM_CFG diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h index 287cbfe9efa2..335c53e92936 100644 --- a/include/asm-mips/sibyte/sb1250_smbus.h +++ b/include/asm-mips/sibyte/sb1250_smbus.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * SMBUS Constants File: sb1250_smbus.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's SMbus devices. - * + * * SB1250 specification level: 01/02/2002 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h index 8d5e8edd3c4b..fa2760d38b8b 100644 --- a/include/asm-mips/sibyte/sb1250_syncser.h +++ b/include/asm-mips/sibyte/sb1250_syncser.h @@ -7,17 +7,17 @@ * manipulating the SB1250's Synchronous Serial * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg * ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h index 7655d6945cca..923ea4f44e0f 100644 --- a/include/asm-mips/sibyte/sb1250_uart.h +++ b/include/asm-mips/sibyte/sb1250_uart.h @@ -1,23 +1,23 @@ /* ********************************************************************* * SB1250 Board Support Package - * + * * UART Constants File: sb1250_uart.h - * - * This module contains constants and macros useful for + * + * This module contains constants and macros useful for * manipulating the SB1250's UARTs * * SB1250 specification level: User's manual 1/02/02 - * + * * Author: Mitch Lichtenberg - * - ********************************************************************* + * + ********************************************************************* * * Copyright 2000,2001,2002,2003 * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -27,7 +27,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ********************************************************************* */ @@ -37,7 +37,7 @@ #include "sb1250_defs.h" -/* ********************************************************************** +/* ********************************************************************** * DUART Registers ********************************************************************** */ @@ -145,7 +145,7 @@ #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) -#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) +#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) /* * DUART Status Register (Table 10-6) @@ -165,7 +165,7 @@ /* * DUART Baud Rate Register (Table 10-7) - * Register: DUART_CLK_SEL_A + * Register: DUART_CLK_SEL_A * Register: DUART_CLK_SEL_B */ @@ -332,7 +332,7 @@ (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* +/* * Full Interrupt Control Register */ diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index 18939e84b6f2..f7fbebaa0744 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h @@ -10,7 +10,7 @@ #define _ASM_SIGCONTEXT_H #include <asm/sgidefs.h> - + #if _MIPS_SIM == _MIPS_SIM_ABI32 /* @@ -38,7 +38,7 @@ struct sigcontext { }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 /* diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index a0e26e6c994d..698becab5a9e 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -25,10 +25,10 @@ struct siginfo; /* * Careful to keep union _sifields from shifting ... */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) #endif diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h index 6333169be329..3ccfe09fa744 100644 --- a/include/asm-mips/sim.h +++ b/include/asm-mips/sim.h @@ -16,7 +16,7 @@ #define __str2(x) #x #define __str(x) __str2(x) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define save_static_function(symbol) \ __asm__ ( \ @@ -42,9 +42,9 @@ __asm__ ( \ #define nabi_no_regargs -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define save_static_function(symbol) \ __asm__ ( \ @@ -78,6 +78,6 @@ __asm__ ( \ unsigned long __dummy6, \ unsigned long __dummy7, -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* _ASM_SIM_H */ diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h index 020b4db70ee5..753b6620e6fa 100644 --- a/include/asm-mips/socket.h +++ b/include/asm-mips/socket.h @@ -37,6 +37,8 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SO_ERROR 0x1007 /* get error status and clear */ #define SO_SNDBUF 0x1001 /* Send buffer size. */ #define SO_RCVBUF 0x1002 /* Receive buffer. */ +#define SO_SNDBUFFORCE 0x100a +#define SO_RCVBUFFORCE 0x100b #define SO_SNDLOWAT 0x1003 /* send low-water mark */ #define SO_RCVLOWAT 0x1004 /* receive low-water mark */ #define SO_SNDTIMEO 0x1005 /* send timeout */ @@ -80,7 +82,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ * @SOCK_STREAM - stream (connection) socket * @SOCK_RAW - raw socket * @SOCK_RDM - reliably-delivered message - * @SOCK_SEQPACKET - sequential packet socket + * @SOCK_SEQPACKET - sequential packet socket * @SOCK_PACKET - linux specific way of getting packets at the dev level. * For writing rarp and other similar things on the user level. */ diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 86283c25fd5b..fb42f99f8527 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -26,7 +26,7 @@ .macro SAVE_TEMP mfhi v1 -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif @@ -56,7 +56,7 @@ #ifdef CONFIG_SMP .macro get_saved_sp /* SMP variation */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT mfc0 k0, CP0_CONTEXT lui k1, %hi(kernelsp) srl k0, k0, 23 @@ -64,7 +64,7 @@ addu k1, k0 LONG_L k1, %lo(kernelsp)(k1) #endif -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) MFC0 k1, CP0_CONTEXT dsra k1, 23 lui k0, %hi(pgd_current) @@ -74,7 +74,7 @@ daddu k1, k0 LONG_L k1, %lo(kernelsp)(k1) #endif -#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) MFC0 k1, CP0_CONTEXT dsrl k1, 23 dsll k1, k1, 3 @@ -83,20 +83,20 @@ .endm .macro set_saved_sp stackp temp temp2 -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT mfc0 \temp, CP0_CONTEXT srl \temp, 23 sll \temp, 2 LONG_S \stackp, kernelsp(\temp) #endif -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) lw \temp, TI_CPU(gp) dsll \temp, 3 lui \temp2, %hi(kernelsp) daddu \temp, \temp2 LONG_S \stackp, %lo(kernelsp)(\temp) #endif -#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64) lw \temp, TI_CPU(gp) dsll \temp, 3 LONG_S \stackp, kernelsp(\temp) @@ -140,7 +140,7 @@ LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC LONG_S $7, PT_R7(sp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif @@ -169,7 +169,7 @@ .macro RESTORE_TEMP LONG_L $24, PT_LO(sp) -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) #endif @@ -217,7 +217,7 @@ LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) LONG_L $25, PT_R25(sp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) #endif @@ -262,7 +262,7 @@ LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) LONG_L $25, PT_R25(sp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) #endif diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h index 5076fec65780..c3ddf973c1c0 100644 --- a/include/asm-mips/statfs.h +++ b/include/asm-mips/statfs.h @@ -57,7 +57,7 @@ struct statfs64 { }; #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - + #if _MIPS_SIM == _MIPS_SIM_ABI64 struct statfs64 { /* Same as struct statfs */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index b18345504f8a..5a06f6d13899 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -16,7 +16,7 @@ * Most of the inline functions are rather naive implementations so I just * didn't bother updating them for 64-bit ... */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #ifndef IN_STRING_C @@ -130,7 +130,7 @@ strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) return __res; } -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ #define __HAVE_ARCH_MEMSET extern void *memset(void *__s, int __c, size_t __count); @@ -141,7 +141,7 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #define __HAVE_ARCH_MEMMOVE extern void *memmove(void *__dest, __const__ void *__src, size_t __n); -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __HAVE_ARCH_MEMSCAN static __inline__ void *memscan(void *__addr, int __c, size_t __size) { @@ -161,6 +161,6 @@ static __inline__ void *memscan(void *__addr, int __c, size_t __size) return __addr; } -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ #endif /* _ASM_STRING_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 169f3d4265b1..6663efd49b27 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -208,7 +208,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) return retval; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) { __u64 retval; @@ -330,7 +330,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, return retval; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, unsigned long new) { diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 42fcd6f2c206..a70cb0854c8a 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -62,10 +62,10 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define current_thread_info() __current_thread_info /* thread information allocation */ -#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS32) +#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) #define THREAD_SIZE_ORDER (1) #endif -#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS64) +#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT) #define THREAD_SIZE_ORDER (2) #endif #ifdef CONFIG_PAGE_SIZE_8KB diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h index fd9599e40a0a..fee1908c65d2 100644 --- a/include/asm-mips/titan_dep.h +++ b/include/asm-mips/titan_dep.h @@ -228,4 +228,4 @@ extern unsigned long ocd_base; #define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) #define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) -#endif +#endif diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 5d939db6e220..3bb7f0087d68 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -45,14 +45,14 @@ /* TX4927 SDRAM controller (64-bit registers) */ -#define TX4927_SDRAMC_BASE 0x8000 -#define TX4927_SDRAMC_SDCCR0 0x8000 +#define TX4927_SDRAMC_BASE 0x8000 +#define TX4927_SDRAMC_SDCCR0 0x8000 #define TX4927_SDRAMC_SDCCR1 0x8008 #define TX4927_SDRAMC_SDCCR2 0x8010 #define TX4927_SDRAMC_SDCCR3 0x8018 #define TX4927_SDRAMC_SDCTR 0x8040 #define TX4927_SDRAMC_SDCMD 0x8058 -#define TX4927_SDRAMC_LIMIT 0x8fff +#define TX4927_SDRAMC_LIMIT 0x8fff /* TX4927 external bus controller (64-bit registers) */ @@ -289,8 +289,8 @@ /* TX4927 serial port 0 (32-bit registers) */ -#define TX4927_SIO0_BASE 0xf300 -#define TX4927_SIO0_SILCR0 0xf300 +#define TX4927_SIO0_BASE 0xf300 +#define TX4927_SIO0_SILCR0 0xf300 #define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SILCR0_RWUB BM_15_15 #define TX4927_SIO0_SILCR0_TWUB BM_14_14 @@ -309,7 +309,7 @@ #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 -#define TX4927_SIO0_SIDICR0 0xf304 +#define TX4927_SIO0_SIDICR0 0xf304 #define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIDICR0_TDE BM_15_15 #define TX4927_SIO0_SIDICR0_RDE BM_14_14 @@ -330,7 +330,7 @@ #define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 #define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 #define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 -#define TX4927_SIO0_SIDISR0 0xf308 +#define TX4927_SIO0_SIDISR0 0xf308 #define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIDISR0_UBRK BM_15_15 #define TX4927_SIO0_SIDISR0_UVALID BM_14_14 @@ -344,7 +344,7 @@ #define TX4927_SIO0_SIDISR0_STIS BM_06_06 #define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 #define TX4927_SIO0_SIDISR0_RFDN BM_00_04 -#define TX4927_SIO0_SISCISR0 0xf30c +#define TX4927_SIO0_SISCISR0 0xf30c #define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 #define TX4927_SIO0_SISCISR0_OERS BM_05_05 #define TX4927_SIO0_SISCISR0_CTSS BM_04_04 @@ -352,7 +352,7 @@ #define TX4927_SIO0_SISCISR0_TRDY BM_02_02 #define TX4927_SIO0_SISCISR0_TXALS BM_01_01 #define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 -#define TX4927_SIO0_SIFCR0 0xf310 +#define TX4927_SIO0_SIFCR0 0xf310 #define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 #define TX4927_SIO0_SIFCR0_SWRST BM_16_31 #define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 @@ -370,7 +370,7 @@ #define TX4927_SIO0_SIFCR0_TFRST BM_02_02 #define TX4927_SIO0_SIFCR0_RFRST BM_01_01 #define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 -#define TX4927_SIO0_SIFLCR0 0xf314 +#define TX4927_SIO0_SIFLCR0 0xf314 #define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 #define TX4927_SIO0_SIFLCR0_RCS BM_12_12 #define TX4927_SIO0_SIFLCR0_TES BM_11_11 @@ -381,7 +381,7 @@ #define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 #define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 #define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 -#define TX4927_SIO0_SIBGR0 0xf318 +#define TX4927_SIO0_SIBGR0 0xf318 #define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 #define TX4927_SIO0_SIBGR0_BCLK BM_08_09 #define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) @@ -389,28 +389,28 @@ #define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 #define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 #define TX4927_SIO0_SIBGR0_BRD BM_00_07 -#define TX4927_SIO0_SITFIF00 0xf31c +#define TX4927_SIO0_SITFIF00 0xf31c #define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 #define TX4927_SIO0_SITFIF00_TXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 +#define TX4927_SIO0_SIRFIFO0 0xf320 #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 #define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 -#define TX4927_SIO0_SIRFIFO0 0xf320 -#define TX4927_SIO0_LIMIT 0xf3ff +#define TX4927_SIO0_SIRFIFO0 0xf320 +#define TX4927_SIO0_LIMIT 0xf3ff /* TX4927 serial port 1 (32-bit registers) */ -#define TX4927_SIO1_BASE 0xf400 -#define TX4927_SIO1_SILCR1 0xf400 -#define TX4927_SIO1_SIDICR1 0xf404 -#define TX4927_SIO1_SIDISR1 0xf408 -#define TX4927_SIO1_SISCISR1 0xf40c -#define TX4927_SIO1_SIFCR1 0xf410 -#define TX4927_SIO1_SIFLCR1 0xf414 -#define TX4927_SIO1_SIBGR1 0xf418 -#define TX4927_SIO1_SITFIF01 0xf41c -#define TX4927_SIO1_SIRFIFO1 0xf420 -#define TX4927_SIO1_LIMIT 0xf4ff +#define TX4927_SIO1_BASE 0xf400 +#define TX4927_SIO1_SILCR1 0xf400 +#define TX4927_SIO1_SIDICR1 0xf404 +#define TX4927_SIO1_SIDISR1 0xf408 +#define TX4927_SIO1_SISCISR1 0xf40c +#define TX4927_SIO1_SIFCR1 0xf410 +#define TX4927_SIO1_SIFLCR1 0xf414 +#define TX4927_SIO1_SIBGR1 0xf418 +#define TX4927_SIO1_SITFIF01 0xf41c +#define TX4927_SIO1_SIRFIFO1 0xf420 +#define TX4927_SIO1_LIMIT 0xf4ff /* TX4927 parallel port (32-bit registers) */ diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 170433492246..165f6b8b217f 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -5,8 +5,8 @@ * * Copyright (C) 2000-2001 Toshiba Corporation */ -#ifndef __ASM_TX4927_TX4927_PCI_H -#define __ASM_TX4927_TX4927_PCI_H +#ifndef __ASM_TX4927_TX4927_PCI_H +#define __ASM_TX4927_TX4927_PCI_H #define TX4927_CCFG_TOE 0x00004000 diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index d2f0c76b00a9..421b3aea14cc 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -78,7 +78,7 @@ typedef unsigned long long u64; #endif #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_MIPS64) + || defined(CONFIG_64BIT) typedef u64 dma_addr_t; #else typedef u32 dma_addr_t; @@ -99,8 +99,6 @@ typedef u64 sector_t; #define HAVE_SECTOR_T #endif -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 07114898e065..a543ead72ecf 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -22,7 +22,7 @@ * * For historical reasons, these macros are grossly misnamed. */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define __UA_LIMIT 0x80000000UL @@ -32,9 +32,9 @@ #define __UA_t0 "$8" #define __UA_t1 "$9" -#endif /* CONFIG_MIPS32 */ +#endif /* CONFIG_32BIT */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define __UA_LIMIT (- TASK_SIZE) @@ -44,7 +44,7 @@ #define __UA_t0 "$12" #define __UA_t1 "$13" -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* * USER_DS is a bitmask that has the bits set that may not be set in a valid diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 6d21cc964f76..ad4d48056307 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -1124,7 +1124,7 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ # ifndef __mips64 # define __ARCH_WANT_STAT64 # endif -# ifdef CONFIG_MIPS32 +# ifdef CONFIG_32BIT # define __ARCH_WANT_SYS_TIME # endif # ifdef CONFIG_MIPS32_O32 diff --git a/include/asm-mips/vr4181/irq.h b/include/asm-mips/vr4181/irq.h deleted file mode 100644 index 4bf0ea970ed0..000000000000 --- a/include/asm-mips/vr4181/irq.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Macros for vr4181 IRQ numbers. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * Strategy: - * - * Vr4181 has conceptually three levels of interrupt controllers: - * 1. the CPU itself with 8 intr level. - * 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs - * 3. GPIO interrupts : forwarding external interrupts to sys intr controller - */ - -/* decide the irq block assignment */ -#define VR4181_NUM_CPU_IRQ 8 -#define VR4181_NUM_SYS_IRQ 32 -#define VR4181_NUM_GPIO_IRQ 16 - -#define VR4181_IRQ_BASE 0 - -#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE -#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ) -#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ) - -/* CPU interrupts */ - -/* - IP0 - Software interrupt - IP1 - Software interrupt - IP2 - All but battery, high speed modem, and real time clock - IP3 - RTC Long1 (system timer) - IP4 - RTC Long2 - IP5 - High Speed Modem (unused on VR4181) - IP6 - Unused - IP7 - Timer interrupt from CPO_COMPARE -*/ - -#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0) -#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1) -#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2) -#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3) -#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4) -#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5) -#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6) -#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7) - - -/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */ - -/* - IP2 - same as VR4181_IRQ_INT1 - IP8 - This is a cascade to GPIO IRQ's. Do not use. - IP16 - same as VR4181_IRQ_INT2 - IP18 - CompactFlash -*/ - -#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0) -#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1) -#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2) -#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3) -#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4) -#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5) -#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6) -#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7) -#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8) -#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9) -#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10) -#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11) -#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12) -#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13) -#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14) -#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15) -#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16) -#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17) -#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18) -#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19) -#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20) -#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21) -#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22) -#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23) -#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24) -#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25) -#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26) -#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27) -#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28) -#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29) -#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30) -#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31) - -/* Cascaded from VR4181_IRQ_GIU */ -#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0) -#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1) -#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2) -#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3) -#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4) -#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5) -#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6) -#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7) -#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8) -#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9) -#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10) -#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11) -#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12) -#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13) -#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14) -#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15) - - -// Alternative to above GPIO IRQ defines -#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin)) - -#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \ - VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ) diff --git a/include/asm-mips/vr4181/vr4181.h b/include/asm-mips/vr4181/vr4181.h deleted file mode 100644 index 5c5d60741515..000000000000 --- a/include/asm-mips/vr4181/vr4181.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - */ -#ifndef __ASM_VR4181_VR4181_H -#define __ASM_VR4181_VR4181_H - -#include <asm/addrspace.h> - -#include <asm/vr4181/irq.h> - -#ifndef __ASSEMBLY__ -#define __preg8 (volatile unsigned char*) -#define __preg16 (volatile unsigned short*) -#define __preg32 (volatile unsigned int*) -#else -#define __preg8 -#define __preg16 -#define __preg32 -#endif - -// Embedded CPU peripheral registers -// Note that many of the registers have different physical address for VR4181 - -// Bus Control Unit (BCU) -#define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */ -#define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */ -#define VR4181_CMUCLKMSK_MSKCSUPCLK 0x0040 -#define VR4181_CMUCLKMSK_MSKAIUPCLK 0x0020 -#define VR4181_CMUCLKMSK_MSKPIUPCLK 0x0010 -#define VR4181_CMUCLKMSK_MSKADUPCLK 0x0008 -#define VR4181_CMUCLKMSK_MSKSIU18M 0x0004 -#define VR4181_CMUCLKMSK_MSKADU18M 0x0002 -#define VR4181_CMUCLKMSK_MSKUSB 0x0001 -#define VR4181_CMUCLKMSK_MSKSIU VR4181_CMUCLKMSK_MSKSIU18M -#define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */ -#define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */ -#define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */ -#define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */ -#define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */ -#define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */ -#define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */ -#define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */ - -// DMA Control Unit (DCU) -#define VR4181_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */ -#define VR4181_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */ -#define VR4181_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */ -#define VR4181_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */ -#define VR4181_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */ -#define VR4181_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */ -#define VR4181_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */ -#define VR4181_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */ -#define VR4181_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */ -#define VR4181_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */ -#define VR4181_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */ -#define VR4181_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */ -#define VR4181_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */ -#define VR4181_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */ -#define VR4181_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */ -#define VR4181_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */ -#define VR4181_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */ -#define VR4181_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */ -#define VR4181_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */ -#define VR4181_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */ -#define VR4181_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */ -#define VR4181_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */ -#define VR4181_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */ -#define VR4181_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */ -#define VR4181_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */ -#define VR4181_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */ -#define VR4181_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */ -#define VR4181_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */ -#define VR4181_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */ -#define VR4181_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */ -#define VR4181_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */ -#define VR4181_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */ -#define VR4181_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */ -#define VR4181_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */ -#define VR4181_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */ -#define VR4181_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */ -#define VR4181_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */ - -// ISA Bridge -#define VR4181_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */ -#define VR4181_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */ -#define VR4181_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */ - -// Clocked Serial Interface (CSI) -#define VR4181_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */ -#define VR4181_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */ -#define VR4181_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */ -#define VR4181_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */ -#define VR4181_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */ -#define VR4181_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */ -#define VR4181_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */ -#define VR4181_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */ - -// Interrupt Control Unit (ICU) -#define VR4181_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */ -#define VR4181_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */ -#define VR4181_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */ -#define VR4181_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */ -#define VR4181_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */ -#define VR4181_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */ -#define VR4181_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ -#define VR4181_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ -#define VR4181_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ -#define VR4181_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ -#define VR4181_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ -#define VR4181_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */ - -// Power Management Unit (PMU) -#define VR4181_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ -#define VR4181_PMUINT_POWERSW 0x1 /* Power switch */ -#define VR4181_PMUINT_BATT 0x2 /* Low batt during normal operation */ -#define VR4181_PMUINT_DEADMAN 0x4 /* Deadman's switch */ -#define VR4181_PMUINT_RESET 0x8 /* Reset switch */ -#define VR4181_PMUINT_RTCRESET 0x10 /* RTC Reset */ -#define VR4181_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ -#define VR4181_PMUINT_BATTLOW 0x100 /* Battery low */ -#define VR4181_PMUINT_RTC 0x200 /* RTC Alarm */ -#define VR4181_PMUINT_DCD 0x400 /* DCD# */ -#define VR4181_PMUINT_GPIO0 0x1000 /* GPIO0 */ -#define VR4181_PMUINT_GPIO1 0x2000 /* GPIO1 */ -#define VR4181_PMUINT_GPIO2 0x4000 /* GPIO2 */ -#define VR4181_PMUINT_GPIO3 0x8000 /* GPIO3 */ - -#define VR4181_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ -#define VR4181_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ -#define VR4181_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */ -#define VR4181_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */ - -// Real Time Clock Unit (RTC) -#define VR4181_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ -#define VR4181_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ -#define VR4181_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ -#define VR4181_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ -#define VR4181_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ -#define VR4181_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ -#define VR4181_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ -#define VR4181_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ -#define VR4181_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ -#define VR4181_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ -#define VR4181_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ -#define VR4181_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ -#define VR4181_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ -#define VR4181_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ -#define VR4181_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ - -// Deadman's Switch Unit (DSU) -#define VR4181_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ -#define VR4181_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ -#define VR4181_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ -#define VR4181_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ - -// General Purpose I/O Unit (GIU) -#define VR4181_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */ -#define VR4181_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */ -#define VR4181_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */ -#define VR4181_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */ -#define VR4181_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */ -#define VR4181_GPDATHREG_GPIO16 0x0001 -#define VR4181_GPDATHREG_GPIO17 0x0002 -#define VR4181_GPDATHREG_GPIO18 0x0004 -#define VR4181_GPDATHREG_GPIO19 0x0008 -#define VR4181_GPDATHREG_GPIO20 0x0010 -#define VR4181_GPDATHREG_GPIO21 0x0020 -#define VR4181_GPDATHREG_GPIO22 0x0040 -#define VR4181_GPDATHREG_GPIO23 0x0080 -#define VR4181_GPDATHREG_GPIO24 0x0100 -#define VR4181_GPDATHREG_GPIO25 0x0200 -#define VR4181_GPDATHREG_GPIO26 0x0400 -#define VR4181_GPDATHREG_GPIO27 0x0800 -#define VR4181_GPDATHREG_GPIO28 0x1000 -#define VR4181_GPDATHREG_GPIO29 0x2000 -#define VR4181_GPDATHREG_GPIO30 0x4000 -#define VR4181_GPDATHREG_GPIO31 0x8000 -#define VR4181_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */ -#define VR4181_GPDATLREG_GPIO0 0x0001 -#define VR4181_GPDATLREG_GPIO1 0x0002 -#define VR4181_GPDATLREG_GPIO2 0x0004 -#define VR4181_GPDATLREG_GPIO3 0x0008 -#define VR4181_GPDATLREG_GPIO4 0x0010 -#define VR4181_GPDATLREG_GPIO5 0x0020 -#define VR4181_GPDATLREG_GPIO6 0x0040 -#define VR4181_GPDATLREG_GPIO7 0x0080 -#define VR4181_GPDATLREG_GPIO8 0x0100 -#define VR4181_GPDATLREG_GPIO9 0x0200 -#define VR4181_GPDATLREG_GPIO10 0x0400 -#define VR4181_GPDATLREG_GPIO11 0x0800 -#define VR4181_GPDATLREG_GPIO12 0x1000 -#define VR4181_GPDATLREG_GPIO13 0x2000 -#define VR4181_GPDATLREG_GPIO14 0x4000 -#define VR4181_GPDATLREG_GPIO15 0x8000 -#define VR4181_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */ -#define VR4181_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */ -#define VR4181_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */ -#define VR4181_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */ -#define VR4181_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */ -#define VR4181_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */ -#define VR4181_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */ -#define VR4181_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */ -#define VR4181_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */ -#define VR4181_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */ -#define VR4181_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */ -#define VR4181_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */ -#define VR4181_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */ -#define VR4181_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */ -#define VR4181_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */ -#define VR4181_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */ -#define VR4181_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */ -#define VR4181_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ -#define VR4181_SECIRQMASKL VR4181_GPINTEN -// No SECIRQMASKH for VR4181 - -// Touch Panel Interface Unit (PIU) -#define VR4181_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ -#define VR4181_PIUCNTREG_PIUSEQEN 0x0004 -#define VR4181_PIUCNTREG_PIUPWR 0x0002 -#define VR4181_PIUCNTREG_PADRST 0x0001 - -#define VR4181_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ -#define VR4181_PIUINTREG_OVP 0x8000 -#define VR4181_PIUINTREG_PADCMD 0x0040 -#define VR4181_PIUINTREG_PADADP 0x0020 -#define VR4181_PIUINTREG_PADPAGE1 0x0010 -#define VR4181_PIUINTREG_PADPAGE0 0x0008 -#define VR4181_PIUINTREG_PADDLOST 0x0004 -#define VR4181_PIUINTREG_PENCHG 0x0001 - -#define VR4181_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ -#define VR4181_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ -#define VR4181_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ -#define VR4181_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ -#define VR4181_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ -#define VR4181_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ -#define VR4181_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ -#define VR4181_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ -#define VR4181_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ -#define VR4181_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ -#define VR4181_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ -#define VR4181_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ -#define VR4181_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ -#define VR4181_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ -#define VR4181_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ -#define VR4181_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ -#define VR4181_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ -#define VR4181_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ -#define VR4181_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ -#define VR4181_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ - -// Audio Interface Unit (AIU) -#define VR4181_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ -#define VR4181_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ -#define VR4181_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ -#define VR4181_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ -#define VR4181_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ -#define VR4181_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */ -#define VR4181_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */ -#define VR4181_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */ -#define VR4181_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */ -#define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */ -#define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */ -#define VR4181_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */ - -// Keyboard Interface Unit (KIU) -#define VR4181_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ -#define VR4181_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ -#define VR4181_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ -#define VR4181_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ -#define VR4181_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ -#define VR4181_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ -#define VR4181_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ -#define VR4181_KIUSCANREP_KEYEN 0x8000 -#define VR4181_KIUSCANREP_SCANSTP 0x0008 -#define VR4181_KIUSCANREP_SCANSTART 0x0004 -#define VR4181_KIUSCANREP_ATSTP 0x0002 -#define VR4181_KIUSCANREP_ATSCAN 0x0001 -#define VR4181_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ -#define VR4181_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ -#define VR4181_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ -#define VR4181_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ -#define VR4181_KIUINT_KDATLOST 0x0004 -#define VR4181_KIUINT_KDATRDY 0x0002 -#define VR4181_KIUINT_SCANINT 0x0001 -#define VR4181_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */ -#define VR4181_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */ - -// CompactFlash Controller -#define VR4181_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */ -#define VR4181_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */ -#define VR4181_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */ -#define VR4181_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */ -#define VR4181_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */ - -// LED Control Unit (LED) -#define VR4181_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ -#define VR4181_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ -#define VR4181_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ -#define VR4181_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ -#define VR4181_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ - -// Serial Interface Unit (SIU / SIU1 and SIU2) -#define VR4181_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ -#define VR4181_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ -#define VR4181_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */ -#define VR4181_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ -#define VR4181_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */ -#define VR4181_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */ -#define VR4181_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */ -#define VR4181_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */ -#define VR4181_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */ -#define VR4181_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */ -#define VR4181_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */ -#define VR4181_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */ -#define VR4181_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */ -#define VR4181_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */ -#define VR4181_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */ -#define VR4181_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */ -#define VR4181_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */ -#define VR4181_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ -#define VR4181_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ -#define VR4181_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ -#define VR4181_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */ -#define VR4181_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ -#define VR4181_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */ -#define VR4181_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ -#define VR4181_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */ -#define VR4181_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ -#define VR4181_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */ -#define VR4181_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */ -#define VR4181_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */ - - -// USB Module -#define VR4181_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */ -#define VR4181_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */ -#define VR4181_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */ -#define VR4181_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */ -#define VR4181_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */ -#define VR4181_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */ -#define VR4181_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */ - -// LCD Controller -#define VR4181_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */ -#define VR4181_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */ -#define VR4181_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */ -#define VR4181_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */ -#define VR4181_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */ -#define VR4181_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */ -#define VR4181_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */ -#define VR4181_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */ -#define VR4181_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */ -#define VR4181_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */ -#define VR4181_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */ -#define VR4181_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */ -#define VR4181_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */ -#define VR4181_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */ -#define VR4181_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */ -#define VR4181_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */ -#define VR4181_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */ -#define VR4181_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */ -#define VR4181_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */ -#define VR4181_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */ -#define VR4181_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */ -#define VR4181_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */ -#define VR4181_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */ - -// physical address spaces -#define VR4181_LCD 0x0a000000 -#define VR4181_INTERNAL_IO_2 0x0b000000 -#define VR4181_INTERNAL_IO_1 0x0c000000 -#define VR4181_ISA_MEM 0x10000000 -#define VR4181_ISA_IO 0x14000000 -#define VR4181_ROM 0x18000000 - -// This is the base address for IO port decoding to which the 16 bit IO port address -// is added. Defining it to 0 will usually cause a kernel oops any time port IO is -// attempted, which can be handy for turning up parts of the kernel that make -// incorrect architecture assumptions (by assuming that everything acts like a PC), -// but we need it correctly defined to use the PCMCIA/CF controller: -#define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO) -#define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM) - -#endif /* __ASM_VR4181_VR4181_H */ diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h index 7d41e44463f9..bd2723c30901 100644 --- a/include/asm-mips/vr41xx/vr41xx.h +++ b/include/asm-mips/vr41xx/vr41xx.h @@ -7,7 +7,7 @@ * Copyright (C) 2001, 2002 Paul Mundt * Copyright (C) 2002 MontaVista Software, Inc. * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> + * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -79,11 +79,11 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2) -#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3) -#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4) -#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5) -#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6) +#define INT0_IRQ MIPS_CPU_IRQ(2) +#define INT1_IRQ MIPS_CPU_IRQ(3) +#define INT2_IRQ MIPS_CPU_IRQ(4) +#define INT3_IRQ MIPS_CPU_IRQ(5) +#define INT4_IRQ MIPS_CPU_IRQ(6) #define TIMER_IRQ MIPS_CPU_IRQ(7) /* SYINT1 Interrupt Numbers */ @@ -97,7 +97,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define PIU_IRQ SYSINT1_IRQ(5) #define AIU_IRQ SYSINT1_IRQ(6) #define KIU_IRQ SYSINT1_IRQ(7) -#define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8) +#define GIUINT_IRQ SYSINT1_IRQ(8) #define SIU_IRQ SYSINT1_IRQ(9) #define BUSERR_IRQ SYSINT1_IRQ(10) #define SOFTINT_IRQ SYSINT1_IRQ(11) @@ -128,7 +128,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define GIU_IRQ_LAST GIU_IRQ(31) extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); -extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); +extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)); #define PIUINT_COMMAND 0x0040 #define PIUINT_DATA 0x0020 diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h index 58e193c51b45..bb7a85c186e4 100644 --- a/include/asm-mips/vr41xx/vrc4173.h +++ b/include/asm-mips/vr41xx/vrc4173.h @@ -21,8 +21,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __NEC_VRC4173_H -#define __NEC_VRC4173_H +#ifndef __NEC_VRC4173_H +#define __NEC_VRC4173_H #include <linux/config.h> #include <asm/io.h> diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a704121343..04ee53b34c2e 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -113,7 +113,7 @@ */ #define BCM1250_M3_WAR 1 -/* +/* * This is a DUART workaround related to glitches around register accesses */ #define SIBYTE_1956_WAR 1 @@ -122,7 +122,7 @@ /* * Fill buffers not flushed on CACHE instructions - * + * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h index 75c0ddfeca13..4d84a90b0f20 100644 --- a/include/asm-mips/xxs1500.h +++ b/include/asm-mips/xxs1500.h @@ -22,7 +22,7 @@ * * ######################################################################## * - * + * */ #ifndef __ASM_XXS1500_H #define __ASM_XXS1500_H diff --git a/include/asm-parisc/emergency-restart.h b/include/asm-parisc/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-parisc/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-parisc/page.h b/include/asm-parisc/page.h index 4a12692f94b4..44eae9f8274d 100644 --- a/include/asm-parisc/page.h +++ b/include/asm-parisc/page.h @@ -74,20 +74,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define __pgd(x) ((pgd_t) { (x) } ) #define __pgprot(x) ((pgprot_t) { (x) } ) -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - typedef struct __physmem_range { unsigned long start_pfn; unsigned long pages; /* PAGE_SIZE pages */ @@ -159,4 +145,6 @@ extern int npmem_ranges; #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _PARISC_PAGE_H */ diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h index ee741c150176..98d79a3d54fa 100644 --- a/include/asm-parisc/pci.h +++ b/include/asm-parisc/pci.h @@ -253,6 +253,10 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region); + static inline void pcibios_add_platform_entries(struct pci_dev *dev) { } diff --git a/include/asm-parisc/socket.h b/include/asm-parisc/socket.h index 4a77996c1862..1bf54dc53c10 100644 --- a/include/asm-parisc/socket.h +++ b/include/asm-parisc/socket.h @@ -16,6 +16,8 @@ /* To add :#define SO_REUSEPORT 0x0200 */ #define SO_SNDBUF 0x1001 #define SO_RCVBUF 0x1002 +#define SO_SNDBUFFORCE 0x100a +#define SO_RCVBUFFORCE 0x100b #define SO_SNDLOWAT 0x1003 #define SO_RCVLOWAT 0x1004 #define SO_SNDTIMEO 0x1005 diff --git a/include/asm-parisc/types.h b/include/asm-parisc/types.h index 8fe7a44ea205..d21b9d0d63ea 100644 --- a/include/asm-parisc/types.h +++ b/include/asm-parisc/types.h @@ -56,8 +56,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u64 dma64_addr_t; -typedef unsigned int kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/8253pit.h b/include/asm-powerpc/8253pit.h index 285f78488ccb..862708a749b0 100644 --- a/include/asm-ppc/8253pit.h +++ b/include/asm-powerpc/8253pit.h @@ -5,6 +5,6 @@ #ifndef _8253PIT_H #define _8253PIT_H -#define PIT_TICK_RATE 1193182UL +#define PIT_TICK_RATE 1193182UL #endif diff --git a/include/asm-ppc/agp.h b/include/asm-powerpc/agp.h index ca9e423307f4..ca9e423307f4 100644 --- a/include/asm-ppc/agp.h +++ b/include/asm-powerpc/agp.h diff --git a/include/asm-powerpc/cputime.h b/include/asm-powerpc/cputime.h new file mode 100644 index 000000000000..6d68ad7e0ea3 --- /dev/null +++ b/include/asm-powerpc/cputime.h @@ -0,0 +1 @@ +#include <asm-generic/cputime.h> diff --git a/include/asm-ppc/div64.h b/include/asm-powerpc/div64.h index 6cd978cefb28..6cd978cefb28 100644 --- a/include/asm-ppc/div64.h +++ b/include/asm-powerpc/div64.h diff --git a/include/asm-powerpc/emergency-restart.h b/include/asm-powerpc/emergency-restart.h new file mode 100644 index 000000000000..3711bd9d50bd --- /dev/null +++ b/include/asm-powerpc/emergency-restart.h @@ -0,0 +1 @@ +#include <asm-generic/emergency-restart.h> diff --git a/include/asm-ppc/errno.h b/include/asm-powerpc/errno.h index 19f20bd41ae6..19f20bd41ae6 100644 --- a/include/asm-ppc/errno.h +++ b/include/asm-powerpc/errno.h diff --git a/include/asm-ppc/ioctl.h b/include/asm-powerpc/ioctl.h index 93c6acfdd0fd..93c6acfdd0fd 100644 --- a/include/asm-ppc/ioctl.h +++ b/include/asm-powerpc/ioctl.h diff --git a/include/asm-ppc/ioctls.h b/include/asm-powerpc/ioctls.h index f5b7f2b055e7..f5b7f2b055e7 100644 --- a/include/asm-ppc/ioctls.h +++ b/include/asm-powerpc/ioctls.h diff --git a/include/asm-ppc/ipc.h b/include/asm-powerpc/ipc.h index a46e3d9c2a3f..a46e3d9c2a3f 100644 --- a/include/asm-ppc/ipc.h +++ b/include/asm-powerpc/ipc.h diff --git a/include/asm-ppc/linkage.h b/include/asm-powerpc/linkage.h index 291c2d01c44f..291c2d01c44f 100644 --- a/include/asm-ppc/linkage.h +++ b/include/asm-powerpc/linkage.h diff --git a/include/asm-ppc64/local.h b/include/asm-powerpc/local.h index c11c530f74d0..c11c530f74d0 100644 --- a/include/asm-ppc64/local.h +++ b/include/asm-powerpc/local.h diff --git a/include/asm-ppc/namei.h b/include/asm-powerpc/namei.h index 29c9ec832133..29c9ec832133 100644 --- a/include/asm-ppc/namei.h +++ b/include/asm-powerpc/namei.h diff --git a/include/asm-powerpc/percpu.h b/include/asm-powerpc/percpu.h new file mode 100644 index 000000000000..06a959d67234 --- /dev/null +++ b/include/asm-powerpc/percpu.h @@ -0,0 +1 @@ +#include <asm-generic/percpu.h> diff --git a/include/asm-ppc/poll.h b/include/asm-powerpc/poll.h index be5024913c62..be5024913c62 100644 --- a/include/asm-ppc/poll.h +++ b/include/asm-powerpc/poll.h diff --git a/include/asm-powerpc/resource.h b/include/asm-powerpc/resource.h new file mode 100644 index 000000000000..04bc4db8921b --- /dev/null +++ b/include/asm-powerpc/resource.h @@ -0,0 +1 @@ +#include <asm-generic/resource.h> diff --git a/include/asm-ppc/shmparam.h b/include/asm-powerpc/shmparam.h index d6250602ae64..d6250602ae64 100644 --- a/include/asm-ppc/shmparam.h +++ b/include/asm-powerpc/shmparam.h diff --git a/include/asm-ppc/string.h b/include/asm-powerpc/string.h index 225575997392..225575997392 100644 --- a/include/asm-ppc/string.h +++ b/include/asm-powerpc/string.h diff --git a/include/asm-ppc/unaligned.h b/include/asm-powerpc/unaligned.h index 45520d9b85d1..45520d9b85d1 100644 --- a/include/asm-ppc/unaligned.h +++ b/include/asm-powerpc/unaligned.h diff --git a/include/asm-ppc/xor.h b/include/asm-powerpc/xor.h index c82eb12a5b18..c82eb12a5b18 100644 --- a/include/asm-ppc/xor.h +++ b/include/asm-powerpc/xor.h diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h index c5883dbed63f..9483d4bfacf7 100644 --- a/include/asm-ppc/cpm2.h +++ b/include/asm-ppc/cpm2.h @@ -109,6 +109,7 @@ static inline long IS_DPERR(const uint offset) * and dual port ram. */ extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ + extern uint cpm_dpalloc(uint size, uint align); extern int cpm_dpfree(uint offset); extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); @@ -116,6 +117,8 @@ extern void cpm_dpdump(void); extern void *cpm_dpram_addr(uint offset); extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); +extern void cpm2_reset(void); + /* Buffer descriptors used by many of the CPM protocols. */ @@ -1087,5 +1090,3 @@ typedef struct im_idma { #endif /* __CPM2__ */ #endif /* __KERNEL__ */ - - diff --git a/include/asm-ppc/cputime.h b/include/asm-ppc/cputime.h deleted file mode 100644 index 8e9faf5ce720..000000000000 --- a/include/asm-ppc/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __PPC_CPUTIME_H -#define __PPC_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __PPC_CPUTIME_H */ diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h index 7f0487afebbe..92b8ee78dcc2 100644 --- a/include/asm-ppc/dma-mapping.h +++ b/include/asm-ppc/dma-mapping.h @@ -60,7 +60,8 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask) } static inline void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t * dma_handle, int gfp) + dma_addr_t * dma_handle, + unsigned int __nocast gfp) { #ifdef CONFIG_NOT_COHERENT_CACHE return __dma_alloc_coherent(size, dma_handle, gfp); @@ -117,7 +118,7 @@ dma_map_page(struct device *dev, struct page *page, __dma_sync_page(page, offset, size, direction); - return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset; + return page_to_bus(page) + offset; } /* We do nothing. */ diff --git a/include/asm-ppc/hdreg.h b/include/asm-ppc/hdreg.h deleted file mode 100644 index 7f7fd1af0af3..000000000000 --- a/include/asm-ppc/hdreg.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/hdreg.h> diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index 87f051138b9d..e5374be86aef 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -35,8 +35,10 @@ #define PPC44x_LOW_SLOT 63 /* LS 32-bits of UART0 physical address location for early serial text debug */ -#ifdef CONFIG_440SP +#if defined(CONFIG_440SP) #define UART0_PHYS_IO_BASE 0xf0000200 +#elif defined(CONFIG_440EP) +#define UART0_PHYS_IO_BASE 0xe0000000 #else #define UART0_PHYS_IO_BASE 0x40000200 #endif @@ -49,11 +51,16 @@ /* * Standard 4GB "page" definitions */ -#ifdef CONFIG_440SP +#if defined(CONFIG_440SP) #define PPC44x_IO_PAGE 0x0000000100000000ULL #define PPC44x_PCICFG_PAGE 0x0000000900000000ULL #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE #define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL +#elif defined(CONFIG_440EP) +#define PPC44x_IO_PAGE 0x0000000000000000ULL +#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL +#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE +#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL #else #define PPC44x_IO_PAGE 0x0000000100000000ULL #define PPC44x_PCICFG_PAGE 0x0000000200000000ULL @@ -64,7 +71,7 @@ /* * 36-bit trap ranges */ -#ifdef CONFIG_440SP +#if defined(CONFIG_440SP) #define PPC44x_IO_LO 0xf0000000UL #define PPC44x_IO_HI 0xf0000fffUL #define PPC44x_PCI0CFG_LO 0x0ec00000UL @@ -75,6 +82,13 @@ #define PPC44x_PCI2CFG_HI 0x2ec00007UL #define PPC44x_PCIMEM_LO 0x80000000UL #define PPC44x_PCIMEM_HI 0xdfffffffUL +#elif defined(CONFIG_440EP) +#define PPC44x_IO_LO 0xef500000UL +#define PPC44x_IO_HI 0xefffffffUL +#define PPC44x_PCI0CFG_LO 0xeec00000UL +#define PPC44x_PCI0CFG_HI 0xeecfffffUL +#define PPC44x_PCIMEM_LO 0xa0000000UL +#define PPC44x_PCIMEM_HI 0xdfffffffUL #else #define PPC44x_IO_LO 0x40000000UL #define PPC44x_IO_HI 0x40000fffUL @@ -152,6 +166,12 @@ #define DCRN_SDR_UART0 0x0120 #define DCRN_SDR_UART1 0x0121 +#ifdef CONFIG_440EP +#define DCRN_SDR_UART2 0x0122 +#define DCRN_SDR_UART3 0x0123 +#define DCRN_SDR_CUST0 0x4000 +#endif + /* SDR read/write helper macros */ #define SDR_READ(offset) ({\ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ @@ -169,6 +189,14 @@ #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ #define DCRN_MAL_BASE 0x180 +#ifdef CONFIG_440EP +#define DCRN_DMA2P40_BASE 0x300 +#define DCRN_DMA2P41_BASE 0x308 +#define DCRN_DMA2P42_BASE 0x310 +#define DCRN_DMA2P43_BASE 0x318 +#define DCRN_DMA2P4SR_BASE 0x320 +#endif + /* UIC */ #define DCRN_UIC0_BASE 0xc0 #define DCRN_UIC1_BASE 0xd0 @@ -395,11 +423,7 @@ #define MQ0_CONFIG_SIZE_2G 0x0000c000 /* Internal SRAM Controller 440GX/440SP */ -#ifdef CONFIG_440SP -#define DCRN_SRAM0_BASE 0x100 -#else /* 440GX */ #define DCRN_SRAM0_BASE 0x000 -#endif #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) #define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021) diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h index 35260afa33a9..e992369cb8e9 100644 --- a/include/asm-ppc/ibm4xx.h +++ b/include/asm-ppc/ibm4xx.h @@ -19,10 +19,6 @@ #ifdef CONFIG_40x -#if defined(CONFIG_ASH) -#include <platforms/4xx/ash.h> -#endif - #if defined(CONFIG_BUBINGA) #include <platforms/4xx/bubinga.h> #endif @@ -35,14 +31,6 @@ #include <platforms/4xx/ep405.h> #endif -#if defined(CONFIG_OAK) -#include <platforms/4xx/oak.h> -#endif - -#if defined(CONFIG_REDWOOD_4) -#include <platforms/4xx/redwood.h> -#endif - #if defined(CONFIG_REDWOOD_5) #include <platforms/4xx/redwood5.h> #endif @@ -97,6 +85,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, #elif CONFIG_44x +#if defined(CONFIG_BAMBOO) +#include <platforms/4xx/bamboo.h> +#endif + #if defined(CONFIG_EBONY) #include <platforms/4xx/ebony.h> #endif diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h index 8c61d93043af..bd7656fa2026 100644 --- a/include/asm-ppc/ibm_ocp.h +++ b/include/asm-ppc/ibm_ocp.h @@ -67,10 +67,13 @@ struct ocp_func_emac_data { int phy_mode; /* PHY type or configurable mode */ u8 mac_addr[6]; /* EMAC mac address */ u32 phy_map; /* EMAC phy map */ + u32 phy_feat_exc; /* Excluded PHY features */ }; /* Sysfs support */ #define OCP_SYSFS_EMAC_DATA() \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ @@ -78,9 +81,14 @@ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \ \ void ocp_show_emac_data(struct device *dev) \ { \ + device_create_file(dev, &dev_attr_emac_rgmii_idx); \ + device_create_file(dev, &dev_attr_emac_rgmii_mux); \ device_create_file(dev, &dev_attr_emac_zmii_idx); \ device_create_file(dev, &dev_attr_emac_zmii_mux); \ device_create_file(dev, &dev_attr_emac_mal_idx); \ @@ -88,8 +96,24 @@ void ocp_show_emac_data(struct device *dev) \ device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ device_create_file(dev, &dev_attr_emac_wol_irq); \ device_create_file(dev, &dev_attr_emac_mdio_idx); \ + device_create_file(dev, &dev_attr_emac_tah_idx); \ + device_create_file(dev, &dev_attr_emac_phy_mode); \ + device_create_file(dev, &dev_attr_emac_phy_map); \ } +/* + * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY) + */ +#define PHY_MODE_NA 0 +#define PHY_MODE_MII 1 +#define PHY_MODE_RMII 2 +#define PHY_MODE_SMII 3 +#define PHY_MODE_RGMII 4 +#define PHY_MODE_TBI 5 +#define PHY_MODE_GMII 6 +#define PHY_MODE_RTBI 7 +#define PHY_MODE_SGMII 8 + #ifdef CONFIG_40x /* * Helper function to copy MAC addresses from the bd_t to OCP EMAC @@ -123,6 +147,7 @@ struct ocp_func_mal_data { int txde_irq; /* TX Descriptor Error IRQ */ int rxde_irq; /* RX Descriptor Error IRQ */ int serr_irq; /* MAL System Error IRQ */ + int dcr_base; /* MALx_CFG DCR number */ }; #define OCP_SYSFS_MAL_DATA() \ @@ -133,6 +158,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \ +OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \ \ void ocp_show_mal_data(struct device *dev) \ { \ @@ -143,6 +169,7 @@ void ocp_show_mal_data(struct device *dev) \ device_create_file(dev, &dev_attr_mal_txde_irq); \ device_create_file(dev, &dev_attr_mal_rxde_irq); \ device_create_file(dev, &dev_attr_mal_serr_irq); \ + device_create_file(dev, &dev_attr_mal_dcr_base); \ } /* @@ -157,7 +184,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \ \ void ocp_show_iic_data(struct device *dev) \ { \ - device_create_file(dev, &dev_attr_iic_fast_mode); \ + device_create_file(dev, &dev_attr_iic_fast_mode); \ } #endif /* __IBM_OCP_H__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h index a9b33324f562..a244d93ca953 100644 --- a/include/asm-ppc/irq.h +++ b/include/asm-ppc/irq.h @@ -337,6 +337,7 @@ static __inline__ int irq_canonicalize(int irq) #define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET) #define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET) #define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET) +#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET) #define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET) #define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET) #define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET) diff --git a/include/asm-ppc/kexec.h b/include/asm-ppc/kexec.h index 73191310d8db..6d2aa0aa4642 100644 --- a/include/asm-ppc/kexec.h +++ b/include/asm-ppc/kexec.h @@ -27,6 +27,8 @@ #ifndef __ASSEMBLY__ +extern void *crash_notes; + struct kimage; extern void machine_kexec_simple(struct kimage *image); diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h index 2589f182a6ad..6d6fc78731e5 100644 --- a/include/asm-ppc/kmap_types.h +++ b/include/asm-ppc/kmap_types.h @@ -17,6 +17,7 @@ enum km_type { KM_SOFTIRQ0, KM_SOFTIRQ1, KM_PPC_SYNC_PAGE, + KM_PPC_SYNC_ICACHE, KM_TYPE_NR }; diff --git a/include/asm-ppc/local.h b/include/asm-ppc/local.h deleted file mode 100644 index b08e3eced10e..000000000000 --- a/include/asm-ppc/local.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __PPC_LOCAL_H -#define __PPC_LOCAL_H - -#include <asm-generic/local.h> - -#endif /* __PPC_LOCAL_H */ diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h index ccabbce39d85..afe26ffc2e2d 100644 --- a/include/asm-ppc/mmu_context.h +++ b/include/asm-ppc/mmu_context.h @@ -149,6 +149,7 @@ static inline void get_mmu_context(struct mm_struct *mm) */ static inline void destroy_context(struct mm_struct *mm) { + preempt_disable(); if (mm->context != NO_CONTEXT) { clear_bit(mm->context, context_map); mm->context = NO_CONTEXT; @@ -156,6 +157,7 @@ static inline void destroy_context(struct mm_struct *mm) atomic_inc(&nr_free_contexts); #endif } + preempt_enable(); } static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h index f5196a4efbe0..77b1e092c206 100644 --- a/include/asm-ppc/mpc10x.h +++ b/include/asm-ppc/mpc10x.h @@ -163,7 +163,8 @@ enum ppc_sys_devices { MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, - MPC10X_DUART, + MPC10X_UART0, + MPC10X_UART1, }; int mpc10x_bridge_init(struct pci_controller *hose, diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h index 89eb8a2ac693..9694eca16e92 100644 --- a/include/asm-ppc/mpc8260.h +++ b/include/asm-ppc/mpc8260.h @@ -67,6 +67,24 @@ #define IO_VIRT_ADDR IO_PHYS_ADDR #endif +enum ppc_sys_devices { + MPC82xx_CPM_FCC1, + MPC82xx_CPM_FCC2, + MPC82xx_CPM_FCC3, + MPC82xx_CPM_I2C, + MPC82xx_CPM_SCC1, + MPC82xx_CPM_SCC2, + MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, + MPC82xx_CPM_SPI, + MPC82xx_CPM_MCC1, + MPC82xx_CPM_MCC2, + MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, + MPC82xx_CPM_USB, + MPC82xx_SEC1, +}; + #ifndef __ASSEMBLY__ /* The "residual" data board information structure the boot loader * hands to us. diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h index 7c31f2d564a1..dc8e59896050 100644 --- a/include/asm-ppc/mpc8xx.h +++ b/include/asm-ppc/mpc8xx.h @@ -36,10 +36,6 @@ #include <platforms/tqm8xx.h> #endif -#if defined(CONFIG_SPD823TS) -#include <platforms/spd8xx.h> -#endif - #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) #include <platforms/ivms8.h> #endif diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h index cc25b921ad4f..835930d6faa1 100644 --- a/include/asm-ppc/mv64x60.h +++ b/include/asm-ppc/mv64x60.h @@ -278,6 +278,13 @@ mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask) #define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) #define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits) +#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) +#define MV64XXX_DEV_NAME "mv64xxx" + +struct mv64xxx_pdata { + u32 hs_reg_valid; +}; +#endif /* Externally visible function prototypes */ int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si); diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h index 2f428746c02b..f8f7f16b9b53 100644 --- a/include/asm-ppc/mv64x60_defs.h +++ b/include/asm-ppc/mv64x60_defs.h @@ -333,7 +333,7 @@ /* ***************************************************************************** * - * SRAM Cotnroller Registers + * SRAM Controller Registers * ***************************************************************************** */ @@ -352,7 +352,7 @@ /* ***************************************************************************** * - * SDRAM/MEM Cotnroller Registers + * SDRAM/MEM Controller Registers * ***************************************************************************** */ @@ -375,6 +375,7 @@ /* SDRAM Control Registers */ #define MV64360_D_UNIT_CONTROL_LOW 0x1404 #define MV64360_D_UNIT_CONTROL_HIGH 0x1424 +#define MV64460_D_UNIT_MMASK 0x14b0 /* SDRAM Error Report Registers (64360) */ #define MV64360_SDRAM_ERR_DATA_LO 0x1444 @@ -388,7 +389,7 @@ /* ***************************************************************************** * - * Device/BOOT Cotnroller Registers + * Device/BOOT Controller Registers * ***************************************************************************** */ @@ -680,6 +681,8 @@ #define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec #define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0 +#define MV64360_PCICFG_CPCI_HOTSWAP 0x68 + /* ***************************************************************************** * diff --git a/include/asm-ppc/param.h b/include/asm-ppc/param.h index b24a4e37196a..6198b1657a45 100644 --- a/include/asm-ppc/param.h +++ b/include/asm-ppc/param.h @@ -1,8 +1,10 @@ #ifndef _ASM_PPC_PARAM_H #define _ASM_PPC_PARAM_H +#include <linux/config.h> + #ifdef __KERNEL__ -#define HZ 1000 /* internal timer frequency */ +#define HZ CONFIG_HZ /* internal timer frequency */ #define USER_HZ 100 /* for user interfaces in "ticks" */ #define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h index db0a2a0ec74d..a811e440c978 100644 --- a/include/asm-ppc/pci.h +++ b/include/asm-ppc/pci.h @@ -37,7 +37,7 @@ extern inline void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -extern inline void pcibios_penalize_isa_irq(int irq) +extern inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } @@ -105,6 +105,10 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region); + extern void pcibios_add_platform_entries(struct pci_dev *dev); struct file; diff --git a/include/asm-ppc/percpu.h b/include/asm-ppc/percpu.h deleted file mode 100644 index d66667cd5878..000000000000 --- a/include/asm-ppc/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARCH_PPC_PERCPU__ -#define __ARCH_PPC_PERCPU__ - -#include <asm-generic/percpu.h> - -#endif /* __ARCH_PPC_PERCPU__ */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 4d4b20c9de78..92f30b28b252 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -202,18 +202,64 @@ extern unsigned long ioremap_bot, ioremap_base; * * Note that these bits preclude future use of a page size * less than 4KB. + * + * + * PPC 440 core has following TLB attribute fields; + * + * TLB1: + * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + * RPN................................. - - - - - - ERPN....... + * + * TLB2: + * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR + * + * There are some constrains and options, to decide mapping software bits + * into TLB entry. + * + * - PRESENT *must* be in the bottom three bits because swap cache + * entries use the top 29 bits for TLB2. + * + * - FILE *must* be in the bottom three bits because swap cache + * entries use the top 29 bits for TLB2. + * + * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it + * doesn't support SMP. So we can use this as software bit, like + * DIRTY. + * + * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used + * for memory protection related functions (see PTE structure in + * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the + * above bits. Note that the bit values are CPU specific, not architecture + * specific. + * + * The kernel PTE entry holds an arch-dependent swp_entry structure under + * certain situations. In other words, in such situations some portion of + * the PTE bits are used as a swp_entry. In the PPC implementation, the + * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still + * hold protection values. That means the three protection bits are + * reserved for both PTE and SWAP entry at the most significant three + * LSBs. + * + * There are three protection bits available for SWAP entry: + * _PAGE_PRESENT + * _PAGE_FILE + * _PAGE_HASHPTE (if HW has) + * + * So those three bits have to be inside of 0-2nd LSB of PTE. + * */ + #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ #define _PAGE_RW 0x00000002 /* S: Write permission */ -#define _PAGE_DIRTY 0x00000004 /* S: Page dirty */ +#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ #define _PAGE_USER 0x00000040 /* S: User page */ #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ #define _PAGE_GUARDED 0x00000100 /* H: G bit */ -#define _PAGE_COHERENT 0x00000200 /* H: M bit */ -#define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */ +#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h index 8636cdbf6f8f..a415001165fa 100644 --- a/include/asm-ppc/ppc4xx_dma.h +++ b/include/asm-ppc/ppc4xx_dma.h @@ -285,7 +285,7 @@ typedef uint32_t sgl_handle_t; #define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan)) -#elif defined(CONFIG_STBXXX_DMA) /* stb03xxx */ +#elif defined(CONFIG_STB03xxx) /* stb03xxx */ #define DMA_PPC4xx_SIZE 4096 diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h index f76221def484..bb53e2def363 100644 --- a/include/asm-ppc/ppc_asm.h +++ b/include/asm-ppc/ppc_asm.h @@ -186,6 +186,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #define PPC405_ERR77_SYNC #endif +#ifdef CONFIG_IBM440EP_ERR42 +#define PPC440EP_ERR42 isync +#else +#define PPC440EP_ERR42 +#endif + /* The boring bits... */ /* Condition Register Bit Fields */ diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h index 8ea624566231..048f7c8596ee 100644 --- a/include/asm-ppc/ppc_sys.h +++ b/include/asm-ppc/ppc_sys.h @@ -21,7 +21,9 @@ #include <linux/device.h> #include <linux/types.h> -#if defined(CONFIG_83xx) +#if defined(CONFIG_8260) +#include <asm/mpc8260.h> +#elif defined(CONFIG_83xx) #include <asm/mpc83xx.h> #elif defined(CONFIG_85xx) #include <asm/mpc85xx.h> @@ -50,6 +52,7 @@ extern struct ppc_sys_spec *cur_ppc_sys_spec; /* determine which specific SOC we are */ extern void identify_ppc_sys_by_id(u32 id) __init; extern void identify_ppc_sys_by_name(char *name) __init; +extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init; /* describes all devices that may exist in a given family of processors */ extern struct platform_device ppc_sys_platform_devices[]; diff --git a/include/asm-ppc/resource.h b/include/asm-ppc/resource.h deleted file mode 100644 index 86a1ea23a6ed..000000000000 --- a/include/asm-ppc/resource.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _PPC_RESOURCE_H -#define _PPC_RESOURCE_H - -#include <asm-generic/resource.h> - -#endif diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h index 6d47438be58c..485a924e4d06 100644 --- a/include/asm-ppc/serial.h +++ b/include/asm-ppc/serial.h @@ -18,8 +18,6 @@ #include <platforms/powerpmc250.h> #elif defined(CONFIG_LOPEC) #include <platforms/lopec.h> -#elif defined(CONFIG_MCPN765) -#include <platforms/mcpn765.h> #elif defined(CONFIG_MVME5100) #include <platforms/mvme5100.h> #elif defined(CONFIG_PAL4) diff --git a/include/asm-ppc/socket.h b/include/asm-ppc/socket.h index 4134376b0f66..296e1a3469d0 100644 --- a/include/asm-ppc/socket.h +++ b/include/asm-ppc/socket.h @@ -20,6 +20,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index 82395f30004b..513a334c5810 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -84,9 +84,14 @@ extern void cvt_fd(float *from, double *to, unsigned long *fpscr); extern void cvt_df(double *from, float *to, unsigned long *fpscr); extern int call_rtas(const char *, int, int, unsigned long *, ...); extern void cacheable_memzero(void *p, unsigned int nb); +extern void *cacheable_memcpy(void *, const void *, unsigned int); extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); extern void bad_page_fault(struct pt_regs *, unsigned long, int); extern void die(const char *, struct pt_regs *, long); +#ifdef CONFIG_BOOKE_WDT +extern u32 booke_wdt_enabled; +extern u32 booke_wdt_period; +#endif /* CONFIG_BOOKE_WDT */ struct device_node; extern void note_scsi_host(struct device_node *, void *); diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h index ce09b47fa819..321fb75b5f22 100644 --- a/include/asm-ppc/time.h +++ b/include/asm-ppc/time.h @@ -58,7 +58,7 @@ static __inline__ void set_dec(unsigned int val) /* Accessor functions for the timebase (RTC on 601) registers. */ /* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ #ifdef CONFIG_6xx -extern __inline__ int const __USE_RTC(void) { +extern __inline__ int __attribute_pure__ __USE_RTC(void) { return (mfspr(SPRN_PVR)>>16) == 1; } #else diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h index a787bc032587..77dc24d7d2ad 100644 --- a/include/asm-ppc/types.h +++ b/include/asm-ppc/types.h @@ -62,8 +62,6 @@ typedef u64 sector_t; #define HAVE_SECTOR_T #endif -typedef unsigned int kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h index a7894e0fbbb1..3173ab3d2eb9 100644 --- a/include/asm-ppc/unistd.h +++ b/include/asm-ppc/unistd.h @@ -279,8 +279,11 @@ #define __NR_waitid 272 #define __NR_ioprio_set 273 #define __NR_ioprio_get 274 +#define __NR_inotify_init 275 +#define __NR_inotify_add_watch 276 +#define __NR_inotify_rm_watch 277 -#define __NR_syscalls 275 +#define __NR_syscalls 278 #define __NR(n) #n diff --git a/include/asm-ppc64/8253pit.h b/include/asm-ppc64/8253pit.h deleted file mode 100644 index 285f78488ccb..000000000000 --- a/include/asm-ppc64/8253pit.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * 8253/8254 Programmable Interval Timer - */ - -#ifndef _8253PIT_H -#define _8253PIT_H - -#define PIT_TICK_RATE 1193182UL - -#endif diff --git a/include/asm-ppc64/abs_addr.h b/include/asm-ppc64/abs_addr.h index 6d4e8e787058..84c24d4cdb71 100644 --- a/include/asm-ppc64/abs_addr.h +++ b/include/asm-ppc64/abs_addr.h @@ -16,93 +16,51 @@ #include <asm/page.h> #include <asm/prom.h> #include <asm/lmb.h> +#include <asm/firmware.h> -typedef u32 msChunks_entry; -struct msChunks { +struct mschunks_map { unsigned long num_chunks; unsigned long chunk_size; unsigned long chunk_shift; unsigned long chunk_mask; - msChunks_entry *abs; + u32 *mapping; }; -extern struct msChunks msChunks; +extern struct mschunks_map mschunks_map; -extern unsigned long msChunks_alloc(unsigned long, unsigned long, unsigned long); -extern unsigned long reloc_offset(void); +/* Chunks are 256 KB */ +#define MSCHUNKS_CHUNK_SHIFT (18) +#define MSCHUNKS_CHUNK_SIZE (1UL << MSCHUNKS_CHUNK_SHIFT) +#define MSCHUNKS_OFFSET_MASK (MSCHUNKS_CHUNK_SIZE - 1) -#ifdef CONFIG_MSCHUNKS - -static inline unsigned long -chunk_to_addr(unsigned long chunk) +static inline unsigned long chunk_to_addr(unsigned long chunk) { - unsigned long offset = reloc_offset(); - struct msChunks *_msChunks = PTRRELOC(&msChunks); - - return chunk << _msChunks->chunk_shift; + return chunk << MSCHUNKS_CHUNK_SHIFT; } -static inline unsigned long -addr_to_chunk(unsigned long addr) +static inline unsigned long addr_to_chunk(unsigned long addr) { - unsigned long offset = reloc_offset(); - struct msChunks *_msChunks = PTRRELOC(&msChunks); - - return addr >> _msChunks->chunk_shift; + return addr >> MSCHUNKS_CHUNK_SHIFT; } -static inline unsigned long -chunk_offset(unsigned long addr) +static inline unsigned long phys_to_abs(unsigned long pa) { - unsigned long offset = reloc_offset(); - struct msChunks *_msChunks = PTRRELOC(&msChunks); + unsigned long chunk; - return addr & _msChunks->chunk_mask; -} + /* This is a no-op on non-iSeries */ + if (!firmware_has_feature(FW_FEATURE_ISERIES)) + return pa; -static inline unsigned long -abs_chunk(unsigned long pchunk) -{ - unsigned long offset = reloc_offset(); - struct msChunks *_msChunks = PTRRELOC(&msChunks); - if ( pchunk >= _msChunks->num_chunks ) { - return pchunk; - } - return PTRRELOC(_msChunks->abs)[pchunk]; -} + chunk = addr_to_chunk(pa); -/* A macro so it can take pointers or unsigned long. */ -#define phys_to_abs(pa) \ - ({ unsigned long _pa = (unsigned long)(pa); \ - chunk_to_addr(abs_chunk(addr_to_chunk(_pa))) + chunk_offset(_pa); \ - }) + if (chunk < mschunks_map.num_chunks) + chunk = mschunks_map.mapping[chunk]; -static inline unsigned long -physRpn_to_absRpn(unsigned long rpn) -{ - unsigned long pa = rpn << PAGE_SHIFT; - unsigned long aa = phys_to_abs(pa); - return (aa >> PAGE_SHIFT); + return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK); } -/* A macro so it can take pointers or unsigned long. */ -#define abs_to_phys(aa) lmb_abs_to_phys((unsigned long)(aa)) - -#else /* !CONFIG_MSCHUNKS */ - -#define chunk_to_addr(chunk) ((unsigned long)(chunk)) -#define addr_to_chunk(addr) (addr) -#define chunk_offset(addr) (0) -#define abs_chunk(pchunk) (pchunk) - -#define phys_to_abs(pa) (pa) -#define physRpn_to_absRpn(rpn) (rpn) -#define abs_to_phys(aa) (aa) - -#endif /* !CONFIG_MSCHUNKS */ - /* Convenience macros */ #define virt_to_abs(va) phys_to_abs(__pa(va)) -#define abs_to_virt(aa) __va(abs_to_phys(aa)) +#define abs_to_virt(aa) __va(aa) #endif /* _ABS_ADDR_H */ diff --git a/include/asm-ppc64/agp.h b/include/asm-ppc64/agp.h deleted file mode 100644 index ca9e423307f4..000000000000 --- a/include/asm-ppc64/agp.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef AGP_H -#define AGP_H 1 - -#include <asm/io.h> - -/* nothing much needed here */ - -#define map_page_into_agp(page) -#define unmap_page_from_agp(page) -#define flush_agp_mappings() -#define flush_agp_cache() mb() - -/* Convert a physical address to an address suitable for the GART. */ -#define phys_to_gart(x) (x) -#define gart_to_phys(x) (x) - -/* GATT allocation. Returns/accepts GATT kernel virtual address. */ -#define alloc_gatt_pages(order) \ - ((char *)__get_free_pages(GFP_KERNEL, (order))) -#define free_gatt_pages(table, order) \ - free_pages((unsigned long)(table), (order)) - -#endif diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h index 169868fa307d..160178278861 100644 --- a/include/asm-ppc64/bug.h +++ b/include/asm-ppc64/bug.h @@ -43,8 +43,8 @@ struct bug_entry *find_bug(unsigned long bugaddr); ".section __bug_table,\"a\"\n\t" \ " .llong 1b,%1,%2,%3\n" \ ".previous" \ - : : "r" (x), "i" (__LINE__), "i" (__FILE__), \ - "i" (__FUNCTION__)); \ + : : "r" ((long long)(x)), "i" (__LINE__), \ + "i" (__FILE__), "i" (__FUNCTION__)); \ } while (0) #define WARN_ON(x) do { \ @@ -53,7 +53,8 @@ struct bug_entry *find_bug(unsigned long bugaddr); ".section __bug_table,\"a\"\n\t" \ " .llong 1b,%1,%2,%3\n" \ ".previous" \ - : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \ + : : "r" ((long long)(x)), \ + "i" (__LINE__ + BUG_WARNING_TRAP), \ "i" (__FILE__), "i" (__FUNCTION__)); \ } while (0) diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h index d67fa9e26079..ae6cf3830108 100644 --- a/include/asm-ppc64/cputable.h +++ b/include/asm-ppc64/cputable.h @@ -56,11 +56,6 @@ struct cpu_spec { * BHT, SPD, etc... from head.S before branching to identify_machine */ cpu_setup_t cpu_setup; - - /* This is used to identify firmware features which are available - * to the kernel. - */ - unsigned long firmware_features; }; extern struct cpu_spec cpu_specs[]; @@ -71,39 +66,6 @@ static inline unsigned long cpu_has_feature(unsigned long feature) return cur_cpu_spec->cpu_features & feature; } - -/* firmware feature bitmask values */ -#define FIRMWARE_MAX_FEATURES 63 - -#define FW_FEATURE_PFT (1UL<<0) -#define FW_FEATURE_TCE (1UL<<1) -#define FW_FEATURE_SPRG0 (1UL<<2) -#define FW_FEATURE_DABR (1UL<<3) -#define FW_FEATURE_COPY (1UL<<4) -#define FW_FEATURE_ASR (1UL<<5) -#define FW_FEATURE_DEBUG (1UL<<6) -#define FW_FEATURE_TERM (1UL<<7) -#define FW_FEATURE_PERF (1UL<<8) -#define FW_FEATURE_DUMP (1UL<<9) -#define FW_FEATURE_INTERRUPT (1UL<<10) -#define FW_FEATURE_MIGRATE (1UL<<11) -#define FW_FEATURE_PERFMON (1UL<<12) -#define FW_FEATURE_CRQ (1UL<<13) -#define FW_FEATURE_VIO (1UL<<14) -#define FW_FEATURE_RDMA (1UL<<15) -#define FW_FEATURE_LLAN (1UL<<16) -#define FW_FEATURE_BULK (1UL<<17) -#define FW_FEATURE_XDABR (1UL<<18) -#define FW_FEATURE_MULTITCE (1UL<<19) -#define FW_FEATURE_SPLPAR (1UL<<20) - -typedef struct { - unsigned long val; - char * name; -} firmware_feature_t; - -extern firmware_feature_t firmware_features_table[]; - #endif /* __ASSEMBLY__ */ /* CPU kernel features */ @@ -140,10 +102,8 @@ extern firmware_feature_t firmware_features_table[]; #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) #define CPU_FTR_CTRL ASM_CONST(0x0000100000000000) -/* Platform firmware features */ -#define FW_FTR_ ASM_CONST(0x0000000000000001) - #ifndef __ASSEMBLY__ + #define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \ PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU) @@ -156,10 +116,9 @@ extern firmware_feature_t firmware_features_table[]; #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE) #else #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE) -#endif +#endif /* CONFIG_PPC_ISERIES */ -#define COMMON_PPC64_FW (0) -#endif +#endif /* __ASSEMBLY */ #ifdef __ASSEMBLY__ diff --git a/include/asm-ppc64/cputime.h b/include/asm-ppc64/cputime.h deleted file mode 100644 index 8e9faf5ce720..000000000000 --- a/include/asm-ppc64/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __PPC_CPUTIME_H -#define __PPC_CPUTIME_H - -#include <asm-generic/cputime.h> - -#endif /* __PPC_CPUTIME_H */ diff --git a/include/asm-ppc64/div64.h b/include/asm-ppc64/div64.h deleted file mode 100644 index 6cd978cefb28..000000000000 --- a/include/asm-ppc64/div64.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/div64.h> diff --git a/include/asm-ppc64/errno.h b/include/asm-ppc64/errno.h deleted file mode 100644 index 69bc3b0c6cbe..000000000000 --- a/include/asm-ppc64/errno.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _PPC64_ERRNO_H -#define _PPC64_ERRNO_H - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include <asm-generic/errno.h> - -#undef EDEADLOCK -#define EDEADLOCK 58 /* File locking deadlock error */ - -#define _LAST_ERRNO 516 - -#endif diff --git a/include/asm-ppc64/firmware.h b/include/asm-ppc64/firmware.h new file mode 100644 index 000000000000..22bb85cf60af --- /dev/null +++ b/include/asm-ppc64/firmware.h @@ -0,0 +1,101 @@ +/* + * include/asm-ppc64/firmware.h + * + * Extracted from include/asm-ppc64/cputable.h + * + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) + * + * Modifications for ppc64: + * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_PPC_FIRMWARE_H +#define __ASM_PPC_FIRMWARE_H + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ + +/* firmware feature bitmask values */ +#define FIRMWARE_MAX_FEATURES 63 + +#define FW_FEATURE_PFT (1UL<<0) +#define FW_FEATURE_TCE (1UL<<1) +#define FW_FEATURE_SPRG0 (1UL<<2) +#define FW_FEATURE_DABR (1UL<<3) +#define FW_FEATURE_COPY (1UL<<4) +#define FW_FEATURE_ASR (1UL<<5) +#define FW_FEATURE_DEBUG (1UL<<6) +#define FW_FEATURE_TERM (1UL<<7) +#define FW_FEATURE_PERF (1UL<<8) +#define FW_FEATURE_DUMP (1UL<<9) +#define FW_FEATURE_INTERRUPT (1UL<<10) +#define FW_FEATURE_MIGRATE (1UL<<11) +#define FW_FEATURE_PERFMON (1UL<<12) +#define FW_FEATURE_CRQ (1UL<<13) +#define FW_FEATURE_VIO (1UL<<14) +#define FW_FEATURE_RDMA (1UL<<15) +#define FW_FEATURE_LLAN (1UL<<16) +#define FW_FEATURE_BULK (1UL<<17) +#define FW_FEATURE_XDABR (1UL<<18) +#define FW_FEATURE_MULTITCE (1UL<<19) +#define FW_FEATURE_SPLPAR (1UL<<20) +#define FW_FEATURE_ISERIES (1UL<<21) + +enum { + FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE | + FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY | + FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM | + FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT | + FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ | + FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN | + FW_FEATURE_BULK | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE | + FW_FEATURE_SPLPAR, + FW_FEATURE_PSERIES_ALWAYS = 0, + FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES, + FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES, + FW_FEATURE_POSSIBLE = +#ifdef CONFIG_PPC_PSERIES + FW_FEATURE_PSERIES_POSSIBLE | +#endif +#ifdef CONFIG_PPC_ISERIES + FW_FEATURE_ISERIES_POSSIBLE | +#endif + 0, + FW_FEATURE_ALWAYS = +#ifdef CONFIG_PPC_PSERIES + FW_FEATURE_PSERIES_ALWAYS & +#endif +#ifdef CONFIG_PPC_ISERIES + FW_FEATURE_ISERIES_ALWAYS & +#endif + FW_FEATURE_POSSIBLE, +}; + +/* This is used to identify firmware features which are available + * to the kernel. + */ +extern unsigned long ppc64_firmware_features; + +static inline unsigned long firmware_has_feature(unsigned long feature) +{ + return (FW_FEATURE_ALWAYS & feature) || + (FW_FEATURE_POSSIBLE & ppc64_firmware_features & feature); +} + +#ifdef CONFIG_PPC_PSERIES +typedef struct { + unsigned long val; + char * name; +} firmware_feature_t; + +extern firmware_feature_t firmware_features_table[]; +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL__ */ +#endif /* __ASM_PPC_FIRMWARE_H */ diff --git a/include/asm-ppc64/hdreg.h b/include/asm-ppc64/hdreg.h deleted file mode 100644 index 7f7fd1af0af3..000000000000 --- a/include/asm-ppc64/hdreg.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/hdreg.h> diff --git a/include/asm-ppc64/iSeries/HvCallHpt.h b/include/asm-ppc64/iSeries/HvCallHpt.h index 66f38222ff75..43a1969230b8 100644 --- a/include/asm-ppc64/iSeries/HvCallHpt.h +++ b/include/asm-ppc64/iSeries/HvCallHpt.h @@ -77,27 +77,26 @@ static inline u64 HvCallHpt_invalidateSetSwBitsGet(u32 hpteIndex, u8 bitson, return compressedStatus; } -static inline u64 HvCallHpt_findValid(HPTE *hpte, u64 vpn) +static inline u64 HvCallHpt_findValid(hpte_t *hpte, u64 vpn) { return HvCall3Ret16(HvCallHptFindValid, hpte, vpn, 0, 0); } -static inline u64 HvCallHpt_findNextValid(HPTE *hpte, u32 hpteIndex, +static inline u64 HvCallHpt_findNextValid(hpte_t *hpte, u32 hpteIndex, u8 bitson, u8 bitsoff) { return HvCall3Ret16(HvCallHptFindNextValid, hpte, hpteIndex, bitson, bitsoff); } -static inline void HvCallHpt_get(HPTE *hpte, u32 hpteIndex) +static inline void HvCallHpt_get(hpte_t *hpte, u32 hpteIndex) { HvCall2Ret16(HvCallHptGet, hpte, hpteIndex, 0); } -static inline void HvCallHpt_addValidate(u32 hpteIndex, u32 hBit, HPTE *hpte) +static inline void HvCallHpt_addValidate(u32 hpteIndex, u32 hBit, hpte_t *hpte) { - HvCall4(HvCallHptAddValidate, hpteIndex, hBit, (*((u64 *)hpte)), - (*(((u64 *)hpte)+1))); + HvCall4(HvCallHptAddValidate, hpteIndex, hBit, hpte->v, hpte->r); } #endif /* _HVCALLHPT_H */ diff --git a/include/asm-ppc64/iSeries/HvReleaseData.h b/include/asm-ppc64/iSeries/HvReleaseData.h index 01a1f13ea4a0..c8162e5ccb21 100644 --- a/include/asm-ppc64/iSeries/HvReleaseData.h +++ b/include/asm-ppc64/iSeries/HvReleaseData.h @@ -39,6 +39,11 @@ * know that this PLIC does not support running an OS "that old". */ +#define HVREL_TAGSINACTIVE 0x8000 +#define HVREL_32BIT 0x4000 +#define HVREL_NOSHAREDPROCS 0x2000 +#define HVREL_NOHMT 0x1000 + struct HvReleaseData { u32 xDesc; /* Descriptor "HvRD" ebcdic x00-x03 */ u16 xSize; /* Size of this control block x04-x05 */ @@ -46,11 +51,7 @@ struct HvReleaseData { struct naca_struct *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */ u32 xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */ u32 xRsvd1; /* Reserved x14-x17 */ - u16 xTagsMode:1; /* 0 == tags active, 1 == tags inactive */ - u16 xAddressSize:1; /* 0 == 64-bit, 1 == 32-bit */ - u16 xNoSharedProcs:1; /* 0 == shared procs, 1 == no shared */ - u16 xNoHMT:1; /* 0 == allow HMT, 1 == no HMT */ - u16 xRsvd2:12; /* Reserved x18-x19 */ + u16 xFlags; u16 xVrmIndex; /* VRM Index of OS image x1A-x1B */ u16 xMinSupportedPlicVrmIndex; /* Min PLIC level (soft) x1C-x1D */ u16 xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */ diff --git a/include/asm-ppc64/iSeries/LparMap.h b/include/asm-ppc64/iSeries/LparMap.h index 038e5df7e9f8..a6840b186d03 100644 --- a/include/asm-ppc64/iSeries/LparMap.h +++ b/include/asm-ppc64/iSeries/LparMap.h @@ -19,6 +19,8 @@ #ifndef _LPARMAP_H #define _LPARMAP_H +#ifndef __ASSEMBLY__ + #include <asm/types.h> /* @@ -49,21 +51,33 @@ * entry to map the Esid to the Vsid. */ +#define HvEsidsToMap 2 +#define HvRangesToMap 1 + /* Hypervisor initially maps 32MB of the load area */ #define HvPagesToMap 8192 struct LparMap { - u64 xNumberEsids; // Number of ESID/VSID pairs (1) - u64 xNumberRanges; // Number of VA ranges to map (1) - u64 xSegmentTableOffs; // Page number within load area of seg table (0) + u64 xNumberEsids; // Number of ESID/VSID pairs + u64 xNumberRanges; // Number of VA ranges to map + u64 xSegmentTableOffs; // Page number within load area of seg table u64 xRsvd[5]; - u64 xKernelEsid; // Esid used to map kernel load (0x0C00000000) - u64 xKernelVsid; // Vsid used to map kernel load (0x0C00000000) - u64 xPages; // Number of pages to be mapped (8192) - u64 xOffset; // Offset from start of load area (0) - u64 xVPN; // Virtual Page Number (0x000C000000000000) + struct { + u64 xKernelEsid; // Esid used to map kernel load + u64 xKernelVsid; // Vsid used to map kernel load + } xEsids[HvEsidsToMap]; + struct { + u64 xPages; // Number of pages to be mapped + u64 xOffset; // Offset from start of load area + u64 xVPN; // Virtual Page Number + } xRanges[HvRangesToMap]; }; -extern struct LparMap xLparMap; +extern const struct LparMap xLparMap; + +#endif /* __ASSEMBLY__ */ + +/* the fixed address where the LparMap exists */ +#define LPARMAP_PHYS 0x7000 #endif /* _LPARMAP_H */ diff --git a/include/asm-ppc64/imalloc.h b/include/asm-ppc64/imalloc.h index e46ff68a6e41..42adf7033a81 100644 --- a/include/asm-ppc64/imalloc.h +++ b/include/asm-ppc64/imalloc.h @@ -6,7 +6,7 @@ */ #define PHBS_IO_BASE VMALLOC_END #define IMALLOC_BASE (PHBS_IO_BASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */ -#define IMALLOC_END (VMALLOC_START + EADDR_MASK) +#define IMALLOC_END (VMALLOC_START + PGTABLE_RANGE) /* imalloc region types */ diff --git a/include/asm-ppc64/ioctl.h b/include/asm-ppc64/ioctl.h deleted file mode 100644 index 42b8c5da7fbc..000000000000 --- a/include/asm-ppc64/ioctl.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef _PPC64_IOCTL_H -#define _PPC64_IOCTL_H - - -/* - * This was copied from the alpha as it's a bit cleaner there. - * -- Cort - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define _IOC_NRBITS 8 -#define _IOC_TYPEBITS 8 -#define _IOC_SIZEBITS 13 -#define _IOC_DIRBITS 3 - -#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) -#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) -#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) -#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) - -#define _IOC_NRSHIFT 0 -#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) -#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) -#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) - -/* - * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. - * And this turns out useful to catch old ioctl numbers in header - * files for us. - */ -#define _IOC_NONE 1U -#define _IOC_READ 2U -#define _IOC_WRITE 4U - -#define _IOC(dir,type,nr,size) \ - (((dir) << _IOC_DIRSHIFT) | \ - ((type) << _IOC_TYPESHIFT) | \ - ((nr) << _IOC_NRSHIFT) | \ - ((size) << _IOC_SIZESHIFT)) - -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __invalid_size_argument_for_IOC; -#define _IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ - sizeof(t) : __invalid_size_argument_for_IOC) - -/* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) - -/* used to decode them.. */ -#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) -#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) -#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) -#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) - -/* various drivers, such as the pcmcia stuff, need these... */ -#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) -#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) -#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) -#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) -#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) - -#endif /* _PPC64_IOCTL_H */ diff --git a/include/asm-ppc64/ioctls.h b/include/asm-ppc64/ioctls.h deleted file mode 100644 index 48796bf3e4fc..000000000000 --- a/include/asm-ppc64/ioctls.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef _ASM_PPC64_IOCTLS_H -#define _ASM_PPC64_IOCTLS_H - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include <asm/ioctl.h> - -#define FIOCLEX _IO('f', 1) -#define FIONCLEX _IO('f', 2) -#define FIOASYNC _IOW('f', 125, int) -#define FIONBIO _IOW('f', 126, int) -#define FIONREAD _IOR('f', 127, int) -#define TIOCINQ FIONREAD -#define FIOQSIZE _IOR('f', 128, loff_t) - -#define TIOCGETP _IOR('t', 8, struct sgttyb) -#define TIOCSETP _IOW('t', 9, struct sgttyb) -#define TIOCSETN _IOW('t', 10, struct sgttyb) /* TIOCSETP wo flush */ - -#define TIOCSETC _IOW('t', 17, struct tchars) -#define TIOCGETC _IOR('t', 18, struct tchars) -#define TCGETS _IOR('t', 19, struct termios) -#define TCSETS _IOW('t', 20, struct termios) -#define TCSETSW _IOW('t', 21, struct termios) -#define TCSETSF _IOW('t', 22, struct termios) - -#define TCGETA _IOR('t', 23, struct termio) -#define TCSETA _IOW('t', 24, struct termio) -#define TCSETAW _IOW('t', 25, struct termio) -#define TCSETAF _IOW('t', 28, struct termio) - -#define TCSBRK _IO('t', 29) -#define TCXONC _IO('t', 30) -#define TCFLSH _IO('t', 31) - -#define TIOCSWINSZ _IOW('t', 103, struct winsize) -#define TIOCGWINSZ _IOR('t', 104, struct winsize) -#define TIOCSTART _IO('t', 110) /* start output, like ^Q */ -#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */ -#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */ - -#define TIOCGLTC _IOR('t', 116, struct ltchars) -#define TIOCSLTC _IOW('t', 117, struct ltchars) -#define TIOCSPGRP _IOW('t', 118, int) -#define TIOCGPGRP _IOR('t', 119, int) - -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E - -#define TIOCSTI 0x5412 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -# define TIOCM_LE 0x001 -# define TIOCM_DTR 0x002 -# define TIOCM_RTS 0x004 -# define TIOCM_ST 0x008 -# define TIOCM_SR 0x010 -# define TIOCM_CTS 0x020 -# define TIOCM_CAR 0x040 -# define TIOCM_RNG 0x080 -# define TIOCM_DSR 0x100 -# define TIOCM_CD TIOCM_CAR -# define TIOCM_RI TIOCM_RNG - -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -# define TIOCPKT_DATA 0 -# define TIOCPKT_FLUSHREAD 1 -# define TIOCPKT_FLUSHWRITE 2 -# define TIOCPKT_STOP 4 -# define TIOCPKT_START 8 -# define TIOCPKT_NOSTOP 16 -# define TIOCPKT_DOSTOP 32 - - -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ - -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ - /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ -# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ - -#endif /* _ASM_PPC64_IOCTLS_H */ diff --git a/include/asm-ppc64/iommu.h b/include/asm-ppc64/iommu.h index 729de5cc21d9..72dcf8116b04 100644 --- a/include/asm-ppc64/iommu.h +++ b/include/asm-ppc64/iommu.h @@ -104,9 +104,6 @@ extern void iommu_devnode_init_pSeries(struct device_node *dn); #ifdef CONFIG_PPC_ISERIES -/* Initializes tables for bio buses */ -extern void __init iommu_vio_init(void); - struct iSeries_Device_Node; /* Creates table for an individual device node */ extern void iommu_devnode_init_iSeries(struct iSeries_Device_Node *dn); diff --git a/include/asm-ppc64/ipc.h b/include/asm-ppc64/ipc.h deleted file mode 100644 index a46e3d9c2a3f..000000000000 --- a/include/asm-ppc64/ipc.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/ipc.h> diff --git a/include/asm-ppc64/linkage.h b/include/asm-ppc64/linkage.h deleted file mode 100644 index 291c2d01c44f..000000000000 --- a/include/asm-ppc64/linkage.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -/* Nothing to see here... */ - -#endif diff --git a/include/asm-ppc64/lmb.h b/include/asm-ppc64/lmb.h index a6cbca21ac1d..de91e034bd98 100644 --- a/include/asm-ppc64/lmb.h +++ b/include/asm-ppc64/lmb.h @@ -22,7 +22,6 @@ struct lmb_property { unsigned long base; - unsigned long physbase; unsigned long size; }; @@ -57,4 +56,26 @@ extern void lmb_dump_all(void); extern unsigned long io_hole_start; +static inline unsigned long +lmb_size_bytes(struct lmb_region *type, unsigned long region_nr) +{ + return type->region[region_nr].size; +} +static inline unsigned long +lmb_size_pages(struct lmb_region *type, unsigned long region_nr) +{ + return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT; +} +static inline unsigned long +lmb_start_pfn(struct lmb_region *type, unsigned long region_nr) +{ + return type->region[region_nr].base >> PAGE_SHIFT; +} +static inline unsigned long +lmb_end_pfn(struct lmb_region *type, unsigned long region_nr) +{ + return lmb_start_pfn(type, region_nr) + + lmb_size_pages(type, region_nr); +} + #endif /* _PPC64_LMB_H */ diff --git a/include/asm-ppc64/lppaca.h b/include/asm-ppc64/lppaca.h index 70766b5f26c1..9e2a6c0649a0 100644 --- a/include/asm-ppc64/lppaca.h +++ b/include/asm-ppc64/lppaca.h @@ -108,7 +108,7 @@ struct lppaca volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B u16 slb_count; // # of SLBs to maintain x7C-x7D u8 idle; // Indicate OS is idle x7E - u8 reserved5; // Reserved x7F + u8 vmxregs_in_use; // VMX registers in use x7F //============================================================================= diff --git a/include/asm-ppc64/machdep.h b/include/asm-ppc64/machdep.h index 1e6ad4824132..ff2c9287d3b6 100644 --- a/include/asm-ppc64/machdep.h +++ b/include/asm-ppc64/machdep.h @@ -53,10 +53,8 @@ struct machdep_calls { long (*hpte_insert)(unsigned long hpte_group, unsigned long va, unsigned long prpn, - int secondary, - unsigned long hpteflags, - int bolted, - int large); + unsigned long vflags, + unsigned long rflags); long (*hpte_remove)(unsigned long hpte_group); void (*flush_hash_range)(unsigned long context, unsigned long number, @@ -86,7 +84,7 @@ struct machdep_calls { void (*init_IRQ)(void); int (*get_irq)(struct pt_regs *); - void (*cpu_irq_down)(void); + void (*cpu_irq_down)(int secondary); /* PCI stuff */ void (*pcibios_fixup)(void); @@ -142,6 +140,9 @@ struct machdep_calls { /* Idle loop for this platform, leave empty for default idle loop */ int (*idle_loop)(void); + + /* Function to enable pmcs for this platform, called once per cpu. */ + void (*enable_pmcs)(void); }; extern int default_idle(void); diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h index f373de5e3dd9..ad36bb28de29 100644 --- a/include/asm-ppc64/mmu.h +++ b/include/asm-ppc64/mmu.h @@ -28,9 +28,12 @@ #define STE_VSID_SHIFT 12 /* Location of cpu0's segment table */ -#define STAB0_PAGE 0x9 +#define STAB0_PAGE 0x6 #define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT) -#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR) + +#ifndef __ASSEMBLY__ +extern char initial_stab[]; +#endif /* ! __ASSEMBLY */ /* * SLB @@ -60,6 +63,22 @@ #define HPTES_PER_GROUP 8 +#define HPTE_V_AVPN_SHIFT 7 +#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80) +#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) +#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) +#define HPTE_V_LOCK ASM_CONST(0x0000000000000008) +#define HPTE_V_LARGE ASM_CONST(0x0000000000000004) +#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) +#define HPTE_V_VALID ASM_CONST(0x0000000000000001) + +#define HPTE_R_PP0 ASM_CONST(0x8000000000000000) +#define HPTE_R_TS ASM_CONST(0x4000000000000000) +#define HPTE_R_RPN_SHIFT 12 +#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000) +#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff) +#define HPTE_R_PP ASM_CONST(0x0000000000000003) + /* Values for PP (assumes Ks=0, Kp=1) */ /* pp0 will always be 0 for linux */ #define PP_RWXX 0 /* Supervisor read/write, User none */ @@ -69,54 +88,13 @@ #ifndef __ASSEMBLY__ -/* Hardware Page Table Entry */ typedef struct { - unsigned long avpn:57; /* vsid | api == avpn */ - unsigned long : 2; /* Software use */ - unsigned long bolted: 1; /* HPTE is "bolted" */ - unsigned long lock: 1; /* lock on pSeries SMP */ - unsigned long l: 1; /* Virtual page is large (L=1) or 4 KB (L=0) */ - unsigned long h: 1; /* Hash function identifier */ - unsigned long v: 1; /* Valid (v=1) or invalid (v=0) */ -} Hpte_dword0; + unsigned long v; + unsigned long r; +} hpte_t; -typedef struct { - unsigned long pp0: 1; /* Page protection bit 0 */ - unsigned long ts: 1; /* Tag set bit */ - unsigned long rpn: 50; /* Real page number */ - unsigned long : 2; /* Reserved */ - unsigned long ac: 1; /* Address compare */ - unsigned long r: 1; /* Referenced */ - unsigned long c: 1; /* Changed */ - unsigned long w: 1; /* Write-thru cache mode */ - unsigned long i: 1; /* Cache inhibited */ - unsigned long m: 1; /* Memory coherence required */ - unsigned long g: 1; /* Guarded */ - unsigned long n: 1; /* No-execute */ - unsigned long pp: 2; /* Page protection bits 1:2 */ -} Hpte_dword1; - -typedef struct { - char padding[6]; /* padding */ - unsigned long : 6; /* padding */ - unsigned long flags: 10; /* HPTE flags */ -} Hpte_dword1_flags; - -typedef struct { - union { - unsigned long dword0; - Hpte_dword0 dw0; - } dw0; - - union { - unsigned long dword1; - Hpte_dword1 dw1; - Hpte_dword1_flags flags; - } dw1; -} HPTE; - -extern HPTE * htab_address; -extern unsigned long htab_hash_mask; +extern hpte_t *htab_address; +extern unsigned long htab_hash_mask; static inline unsigned long hpt_hash(unsigned long vpn, int large) { @@ -181,18 +159,18 @@ static inline void tlbiel(unsigned long va) asm volatile("ptesync": : :"memory"); } -static inline unsigned long slot2va(unsigned long avpn, unsigned long large, - unsigned long secondary, unsigned long slot) +static inline unsigned long slot2va(unsigned long hpte_v, unsigned long slot) { + unsigned long avpn = HPTE_V_AVPN_VAL(hpte_v); unsigned long va; va = avpn << 23; - if (!large) { + if (! (hpte_v & HPTE_V_LARGE)) { unsigned long vpi, pteg; pteg = slot / HPTES_PER_GROUP; - if (secondary) + if (hpte_v & HPTE_V_SECONDARY) pteg = ~pteg; vpi = ((va >> 28) ^ pteg) & htab_hash_mask; @@ -219,11 +197,13 @@ extern void hpte_init_iSeries(void); extern long pSeries_lpar_hpte_insert(unsigned long hpte_group, unsigned long va, unsigned long prpn, - int secondary, unsigned long hpteflags, - int bolted, int large); + unsigned long vflags, + unsigned long rflags); extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, - unsigned long prpn, int secondary, - unsigned long hpteflags, int bolted, int large); + unsigned long prpn, + unsigned long vflags, unsigned long rflags); + +extern void stabs_alloc(void); #endif /* __ASSEMBLY__ */ @@ -282,8 +262,10 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, #define VSID_BITS 36 #define VSID_MODULUS ((1UL<<VSID_BITS)-1) -#define CONTEXT_BITS 20 -#define USER_ESID_BITS 15 +#define CONTEXT_BITS 19 +#define USER_ESID_BITS 16 + +#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT)) /* * This macro generates asm code to compute the VSID scramble @@ -325,8 +307,7 @@ typedef unsigned long mm_context_id_t; typedef struct { mm_context_id_t id; #ifdef CONFIG_HUGETLB_PAGE - pgd_t *huge_pgdir; - u16 htlb_segs; /* bitmask */ + u16 low_htlb_areas, high_htlb_areas; #endif } mm_context_t; @@ -361,6 +342,9 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea) | (ea >> SID_SHIFT)); } +#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS) +#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea)) + #endif /* __ASSEMBLY */ #endif /* _PPC64_MMU_H_ */ diff --git a/include/asm-ppc64/naca.h b/include/asm-ppc64/naca.h index bfb7caa32eaf..d2afe6447597 100644 --- a/include/asm-ppc64/naca.h +++ b/include/asm-ppc64/naca.h @@ -12,8 +12,6 @@ #include <asm/types.h> -#ifndef __ASSEMBLY__ - struct naca_struct { /* Kernel only data - undefined for user space */ void *xItVpdAreas; /* VPD Data 0x00 */ @@ -23,9 +21,4 @@ struct naca_struct { extern struct naca_struct naca; -#endif /* __ASSEMBLY__ */ - -#define NACA_PAGE 0x4 -#define NACA_PHYS_ADDR (NACA_PAGE<<PAGE_SHIFT) - #endif /* _NACA_H */ diff --git a/include/asm-ppc64/namei.h b/include/asm-ppc64/namei.h deleted file mode 100644 index a1412a2d102a..000000000000 --- a/include/asm-ppc64/namei.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/include/asm-ppc/namei.h - * Adapted from linux/include/asm-alpha/namei.h - * - * Included from linux/fs/namei.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef __PPC64_NAMEI_H -#define __PPC64_NAMEI_H - -/* This dummy routine maybe changed to something useful - * for /usr/gnemul/ emulation stuff. - * Look at asm-sparc/namei.h for details. - */ - -#define __emul_prefix() NULL - -#endif /* __PPC64_NAMEI_H */ diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h index a5893a305a09..a15422bcf30d 100644 --- a/include/asm-ppc64/page.h +++ b/include/asm-ppc64/page.h @@ -37,39 +37,45 @@ #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) -/* For 64-bit processes the hugepage range is 1T-1.5T */ -#define TASK_HPAGE_BASE ASM_CONST(0x0000010000000000) -#define TASK_HPAGE_END ASM_CONST(0x0000018000000000) +#define HTLB_AREA_SHIFT 40 +#define HTLB_AREA_SIZE (1UL << HTLB_AREA_SHIFT) +#define GET_HTLB_AREA(x) ((x) >> HTLB_AREA_SHIFT) #define LOW_ESID_MASK(addr, len) (((1U << (GET_ESID(addr+len-1)+1)) \ - (1U << GET_ESID(addr))) & 0xffff) +#define HTLB_AREA_MASK(addr, len) (((1U << (GET_HTLB_AREA(addr+len-1)+1)) \ + - (1U << GET_HTLB_AREA(addr))) & 0xffff) #define ARCH_HAS_HUGEPAGE_ONLY_RANGE #define ARCH_HAS_PREPARE_HUGEPAGE_RANGE +#define ARCH_HAS_SETCLEAR_HUGE_PTE #define touches_hugepage_low_range(mm, addr, len) \ - (LOW_ESID_MASK((addr), (len)) & mm->context.htlb_segs) -#define touches_hugepage_high_range(addr, len) \ - (((addr) > (TASK_HPAGE_BASE-(len))) && ((addr) < TASK_HPAGE_END)) + (LOW_ESID_MASK((addr), (len)) & (mm)->context.low_htlb_areas) +#define touches_hugepage_high_range(mm, addr, len) \ + (HTLB_AREA_MASK((addr), (len)) & (mm)->context.high_htlb_areas) #define __within_hugepage_low_range(addr, len, segmask) \ ((LOW_ESID_MASK((addr), (len)) | (segmask)) == (segmask)) #define within_hugepage_low_range(addr, len) \ __within_hugepage_low_range((addr), (len), \ - current->mm->context.htlb_segs) -#define within_hugepage_high_range(addr, len) (((addr) >= TASK_HPAGE_BASE) \ - && ((addr)+(len) <= TASK_HPAGE_END) && ((addr)+(len) >= (addr))) + current->mm->context.low_htlb_areas) +#define __within_hugepage_high_range(addr, len, zonemask) \ + ((HTLB_AREA_MASK((addr), (len)) | (zonemask)) == (zonemask)) +#define within_hugepage_high_range(addr, len) \ + __within_hugepage_high_range((addr), (len), \ + current->mm->context.high_htlb_areas) #define is_hugepage_only_range(mm, addr, len) \ - (touches_hugepage_high_range((addr), (len)) || \ + (touches_hugepage_high_range((mm), (addr), (len)) || \ touches_hugepage_low_range((mm), (addr), (len))) #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA #define in_hugepage_area(context, addr) \ (cpu_has_feature(CPU_FTR_16M_PAGE) && \ - ( (((addr) >= TASK_HPAGE_BASE) && ((addr) < TASK_HPAGE_END)) || \ + ( ((1 << GET_HTLB_AREA(addr)) & (context).high_htlb_areas) || \ ( ((addr) < 0x100000000L) && \ - ((1 << GET_ESID(addr)) & (context).htlb_segs) ) ) ) + ((1 << GET_ESID(addr)) & (context).low_htlb_areas) ) ) ) #else /* !CONFIG_HUGETLB_PAGE */ @@ -125,55 +131,47 @@ extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct pag * Entries in the pte table are 64b, while entries in the pgd & pmd are 32b. */ typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned int pmd; } pmd_t; -typedef struct { unsigned int pgd; } pgd_t; +typedef struct { unsigned long pmd; } pmd_t; +typedef struct { unsigned long pud; } pud_t; +typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; #define pte_val(x) ((x).pte) #define pmd_val(x) ((x).pmd) +#define pud_val(x) ((x).pud) #define pgd_val(x) ((x).pgd) #define pgprot_val(x) ((x).pgprot) -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) +#define __pte(x) ((pte_t) { (x) }) +#define __pmd(x) ((pmd_t) { (x) }) +#define __pud(x) ((pud_t) { (x) }) +#define __pgd(x) ((pgd_t) { (x) }) +#define __pgprot(x) ((pgprot_t) { (x) }) #else /* * .. while these make it easier on the compiler */ typedef unsigned long pte_t; -typedef unsigned int pmd_t; -typedef unsigned int pgd_t; +typedef unsigned long pmd_t; +typedef unsigned long pud_t; +typedef unsigned long pgd_t; typedef unsigned long pgprot_t; #define pte_val(x) (x) #define pmd_val(x) (x) +#define pud_val(x) (x) #define pgd_val(x) (x) #define pgprot_val(x) (x) #define __pte(x) (x) #define __pmd(x) (x) +#define __pud(x) (x) #define __pgd(x) (x) #define __pgprot(x) (x) #endif -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #define __pa(x) ((unsigned long)(x)-PAGE_OFFSET) extern int page_is_ram(unsigned long pfn); @@ -208,9 +206,6 @@ extern u64 ppc64_pft_size; /* Log 2 of page table size */ #define USER_REGION_ID (0UL) #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) -#define __bpn_to_ba(x) ((((unsigned long)(x)) << PAGE_SHIFT) + KERNELBASE) -#define __ba_to_bpn(x) ((((unsigned long)(x)) & ~REGION_MASK) >> PAGE_SHIFT) - #define __va(x) ((void *)((unsigned long)(x) + KERNELBASE)) #ifdef CONFIG_DISCONTIGMEM @@ -261,4 +256,7 @@ extern u64 ppc64_pft_size; /* Log 2 of page table size */ VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64) #endif /* __KERNEL__ */ + +#include <asm-generic/page.h> + #endif /* _PPC64_PAGE_H */ diff --git a/include/asm-ppc64/param.h b/include/asm-ppc64/param.h index 1fad38dcf707..76c212d475b3 100644 --- a/include/asm-ppc64/param.h +++ b/include/asm-ppc64/param.h @@ -1,6 +1,8 @@ #ifndef _ASM_PPC64_PARAM_H #define _ASM_PPC64_PARAM_H +#include <linux/config.h> + /* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -9,7 +11,7 @@ */ #ifdef __KERNEL__ -# define HZ 1000 /* Internal kernel timer frequency */ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h index d12dfce21e20..4d057452f59b 100644 --- a/include/asm-ppc64/pci.h +++ b/include/asm-ppc64/pci.h @@ -37,7 +37,7 @@ static inline void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -static inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } @@ -134,6 +134,10 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region); + extern int unmap_bus_range(struct pci_bus *bus); diff --git a/include/asm-ppc64/percpu.h b/include/asm-ppc64/percpu.h deleted file mode 100644 index 60a659a4ce1f..000000000000 --- a/include/asm-ppc64/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARCH_PPC64_PERCPU__ -#define __ARCH_PPC64_PERCPU__ - -#include <asm-generic/percpu.h> - -#endif /* __ARCH_PPC64_PERCPU__ */ diff --git a/include/asm-ppc64/pgalloc.h b/include/asm-ppc64/pgalloc.h index 4fc4b739b380..26bc49c1108d 100644 --- a/include/asm-ppc64/pgalloc.h +++ b/include/asm-ppc64/pgalloc.h @@ -6,7 +6,12 @@ #include <linux/cpumask.h> #include <linux/percpu.h> -extern kmem_cache_t *zero_cache; +extern kmem_cache_t *pgtable_cache[]; + +#define PTE_CACHE_NUM 0 +#define PMD_CACHE_NUM 1 +#define PUD_CACHE_NUM 1 +#define PGD_CACHE_NUM 0 /* * This program is free software; you can redistribute it and/or @@ -15,30 +20,40 @@ extern kmem_cache_t *zero_cache; * 2 of the License, or (at your option) any later version. */ -static inline pgd_t * -pgd_alloc(struct mm_struct *mm) +static inline pgd_t *pgd_alloc(struct mm_struct *mm) { - return kmem_cache_alloc(zero_cache, GFP_KERNEL); + return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL); } -static inline void -pgd_free(pgd_t *pgd) +static inline void pgd_free(pgd_t *pgd) { - kmem_cache_free(zero_cache, pgd); + kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd); +} + +#define pgd_populate(MM, PGD, PUD) pgd_set(PGD, PUD) + +static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr) +{ + return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM], + GFP_KERNEL|__GFP_REPEAT); +} + +static inline void pud_free(pud_t *pud) +{ + kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud); } #define pud_populate(MM, PUD, PMD) pud_set(PUD, PMD) -static inline pmd_t * -pmd_alloc_one(struct mm_struct *mm, unsigned long addr) +static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) { - return kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT); + return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM], + GFP_KERNEL|__GFP_REPEAT); } -static inline void -pmd_free(pmd_t *pmd) +static inline void pmd_free(pmd_t *pmd) { - kmem_cache_free(zero_cache, pmd); + kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd); } #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) @@ -47,44 +62,58 @@ pmd_free(pmd_t *pmd) static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) { - return kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT); + return kmem_cache_alloc(pgtable_cache[PTE_CACHE_NUM], + GFP_KERNEL|__GFP_REPEAT); } static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) { - pte_t *pte = kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT); - if (pte) - return virt_to_page(pte); - return NULL; + return virt_to_page(pte_alloc_one_kernel(mm, address)); } static inline void pte_free_kernel(pte_t *pte) { - kmem_cache_free(zero_cache, pte); + kmem_cache_free(pgtable_cache[PTE_CACHE_NUM], pte); } static inline void pte_free(struct page *ptepage) { - kmem_cache_free(zero_cache, page_address(ptepage)); + pte_free_kernel(page_address(ptepage)); } -struct pte_freelist_batch +#define PGF_CACHENUM_MASK 0xf + +typedef struct pgtable_free { + unsigned long val; +} pgtable_free_t; + +static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum, + unsigned long mask) { - struct rcu_head rcu; - unsigned int index; - struct page * pages[0]; -}; + BUG_ON(cachenum > PGF_CACHENUM_MASK); -#define PTE_FREELIST_SIZE ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) / \ - sizeof(struct page *)) + return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum}; +} -extern void pte_free_now(struct page *ptepage); -extern void pte_free_submit(struct pte_freelist_batch *batch); +static inline void pgtable_free(pgtable_free_t pgf) +{ + void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK); + int cachenum = pgf.val & PGF_CACHENUM_MASK; -DECLARE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur); + kmem_cache_free(pgtable_cache[cachenum], p); +} -void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage); -#define __pmd_free_tlb(tlb, pmd) __pte_free_tlb(tlb, virt_to_page(pmd)) +void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf); + +#define __pte_free_tlb(tlb, ptepage) \ + pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \ + PTE_CACHE_NUM, PTE_TABLE_SIZE-1)) +#define __pmd_free_tlb(tlb, pmd) \ + pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \ + PMD_CACHE_NUM, PMD_TABLE_SIZE-1)) +#define __pud_free_tlb(tlb, pmd) \ + pgtable_free_tlb(tlb, pgtable_free_cache(pud, \ + PUD_CACHE_NUM, PUD_TABLE_SIZE-1)) #define check_pgt_cache() do { } while (0) diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h index 46cf61c2ff69..c83679c9d2b0 100644 --- a/include/asm-ppc64/pgtable.h +++ b/include/asm-ppc64/pgtable.h @@ -15,19 +15,24 @@ #include <asm/tlbflush.h> #endif /* __ASSEMBLY__ */ -#include <asm-generic/pgtable-nopud.h> - /* * Entries per page directory level. The PTE level must use a 64b record * for each page table entry. The PMD and PGD level use a 32b record for * each entry by assuming that each entry is page aligned. */ #define PTE_INDEX_SIZE 9 -#define PMD_INDEX_SIZE 10 -#define PGD_INDEX_SIZE 10 +#define PMD_INDEX_SIZE 7 +#define PUD_INDEX_SIZE 7 +#define PGD_INDEX_SIZE 9 + +#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) +#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) +#define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) +#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) +#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE) #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) /* PMD_SHIFT determines what a second-level page table entry can map */ @@ -35,8 +40,13 @@ #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) +/* PUD_SHIFT determines what a third-level page table entry can map */ +#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) +#define PUD_SIZE (1UL << PUD_SHIFT) +#define PUD_MASK (~(PUD_SIZE-1)) + +/* PGDIR_SHIFT determines what a fourth-level page table entry can map */ +#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -45,15 +55,23 @@ /* * Size of EA range mapped by our pagetables. */ -#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ - PGD_INDEX_SIZE + PAGE_SHIFT) -#define EADDR_MASK ((1UL << EADDR_SIZE) - 1) +#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ + PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) +#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE) + +#if TASK_SIZE_USER64 > PGTABLE_RANGE +#error TASK_SIZE_USER64 exceeds pagetable range +#endif + +#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT)) +#error TASK_SIZE_USER64 exceeds user VSID range +#endif /* * Define the address range of the vmalloc VM area. */ #define VMALLOC_START (0xD000000000000000ul) -#define VMALLOC_SIZE (0x10000000000UL) +#define VMALLOC_SIZE (0x80000000000UL) #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE) /* @@ -154,8 +172,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; #ifndef __ASSEMBLY__ int hash_huge_page(struct mm_struct *mm, unsigned long access, unsigned long ea, unsigned long vsid, int local); - -void hugetlb_mm_free_pgd(struct mm_struct *mm); #endif /* __ASSEMBLY__ */ #define HAVE_ARCH_UNMAPPED_AREA @@ -163,7 +179,6 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); #else #define hash_huge_page(mm,a,ea,vsid,local) -1 -#define hugetlb_mm_free_pgd(mm) do {} while (0) #endif @@ -197,39 +212,45 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) #define pte_pfn(x) ((unsigned long)((pte_val(x) >> PTE_SHIFT))) #define pte_page(x) pfn_to_page(pte_pfn(x)) -#define pmd_set(pmdp, ptep) \ - (pmd_val(*(pmdp)) = __ba_to_bpn(ptep)) +#define pmd_set(pmdp, ptep) ({BUG_ON((u64)ptep < KERNELBASE); pmd_val(*(pmdp)) = (unsigned long)(ptep);}) #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_bad(pmd) (pmd_val(pmd) == 0) #define pmd_present(pmd) (pmd_val(pmd) != 0) #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0) -#define pmd_page_kernel(pmd) (__bpn_to_ba(pmd_val(pmd))) +#define pmd_page_kernel(pmd) (pmd_val(pmd)) #define pmd_page(pmd) virt_to_page(pmd_page_kernel(pmd)) -#define pud_set(pudp, pmdp) (pud_val(*(pudp)) = (__ba_to_bpn(pmdp))) +#define pud_set(pudp, pmdp) (pud_val(*(pudp)) = (unsigned long)(pmdp)) #define pud_none(pud) (!pud_val(pud)) -#define pud_bad(pud) ((pud_val(pud)) == 0UL) -#define pud_present(pud) (pud_val(pud) != 0UL) -#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) -#define pud_page(pud) (__bpn_to_ba(pud_val(pud))) +#define pud_bad(pud) ((pud_val(pud)) == 0) +#define pud_present(pud) (pud_val(pud) != 0) +#define pud_clear(pudp) (pud_val(*(pudp)) = 0) +#define pud_page(pud) (pud_val(pud)) + +#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);}) +#define pgd_none(pgd) (!pgd_val(pgd)) +#define pgd_bad(pgd) (pgd_val(pgd) == 0) +#define pgd_present(pgd) (pgd_val(pgd) != 0) +#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0) +#define pgd_page(pgd) (pgd_val(pgd)) /* * Find an entry in a page-table-directory. We combine the address region * (the high order N bits) and the pgd portion of the address. */ /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */ -#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x7ff) +#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff) #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) -/* Find an entry in the second-level page table.. */ +#define pud_offset(pgdp, addr) \ + (((pud_t *) pgd_page(*(pgdp))) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))) + #define pmd_offset(pudp,addr) \ - ((pmd_t *) pud_page(*(pudp)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) + (((pmd_t *) pud_page(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) -/* Find an entry in the third-level page table.. */ #define pte_offset_kernel(dir,addr) \ - ((pte_t *) pmd_page_kernel(*(dir)) \ - + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) + (((pte_t *) pmd_page_kernel(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) @@ -458,23 +479,20 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0) #define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %08x.\n", __FILE__, __LINE__, pmd_val(e)) + printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) +#define pud_ERROR(e) \ + printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pud_val(e)) #define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %08x.\n", __FILE__, __LINE__, pgd_val(e)) + printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) extern pgd_t swapper_pg_dir[]; extern void paging_init(void); -/* - * Because the huge pgtables are only 2 level, they can take - * at most around 4M, much less than one hugepage which the - * process is presumably entitled to use. So we don't bother - * freeing up the pagetables on unmap, and wait until - * destroy_context() to clean up the lot. - */ +#ifdef CONFIG_HUGETLB_PAGE #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \ - do { } while (0) + free_pgd_range(tlb, addr, end, floor, ceiling) +#endif /* * This gets called at the end of handling a page fault, when diff --git a/include/asm-ppc64/pmc.h b/include/asm-ppc64/pmc.h index c924748c0bea..d1d297dbccfe 100644 --- a/include/asm-ppc64/pmc.h +++ b/include/asm-ppc64/pmc.h @@ -26,4 +26,6 @@ typedef void (*perf_irq_t)(struct pt_regs *); int reserve_pmc_hardware(perf_irq_t new_perf_irq); void release_pmc_hardware(void); +void power4_enable_pmcs(void); + #endif /* _PPC64_PMC_H */ diff --git a/include/asm-ppc64/poll.h b/include/asm-ppc64/poll.h deleted file mode 100644 index 370fa3ba0db4..000000000000 --- a/include/asm-ppc64/poll.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef __PPC64_POLL_H -#define __PPC64_POLL_H - -/* - * Copyright (C) 2001 PPC64 Team, IBM Corp - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define POLLIN 0x0001 -#define POLLPRI 0x0002 -#define POLLOUT 0x0004 -#define POLLERR 0x0008 -#define POLLHUP 0x0010 -#define POLLNVAL 0x0020 -#define POLLRDNORM 0x0040 -#define POLLRDBAND 0x0080 -#define POLLWRNORM 0x0100 -#define POLLWRBAND 0x0200 -#define POLLMSG 0x0400 -#define POLLREMOVE 0x1000 - -struct pollfd { - int fd; - short events; - short revents; -}; - -#endif /* __PPC64_POLL_H */ diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index 352306cfb579..7bd4796f1236 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h @@ -268,6 +268,7 @@ #define PV_970FX 0x003C #define PV_630 0x0040 #define PV_630p 0x0041 +#define PV_970MP 0x0044 #define PV_BE 0x0070 /* Platforms supported by PPC64 */ @@ -382,8 +383,8 @@ extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); extern struct task_struct *last_task_used_math; extern struct task_struct *last_task_used_altivec; -/* 64-bit user address space is 41-bits (2TBs user VM) */ -#define TASK_SIZE_USER64 (0x0000020000000000UL) +/* 64-bit user address space is 44-bits (16TB user VM) */ +#define TASK_SIZE_USER64 (0x0000100000000000UL) /* * 32-bit user address space is 4GB - 1 page diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h index 04b1a84f7ca3..dc5330b39509 100644 --- a/include/asm-ppc64/prom.h +++ b/include/asm-ppc64/prom.h @@ -22,13 +22,15 @@ #define RELOC(x) (*PTRRELOC(&(x))) /* Definitions used by the flattened device tree */ -#define OF_DT_HEADER 0xd00dfeed /* 4: version, 4: total size */ -#define OF_DT_BEGIN_NODE 0x1 /* Start node: full name */ +#define OF_DT_HEADER 0xd00dfeed /* marker */ +#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */ #define OF_DT_END_NODE 0x2 /* End node */ -#define OF_DT_PROP 0x3 /* Property: name off, size, content */ +#define OF_DT_PROP 0x3 /* Property: name off, size, + * content */ +#define OF_DT_NOP 0x4 /* nop */ #define OF_DT_END 0x9 -#define OF_DT_VERSION 1 +#define OF_DT_VERSION 0x10 /* * This is what gets passed to the kernel by prom_init or kexec @@ -54,7 +56,9 @@ struct boot_param_header u32 version; /* format version */ u32 last_comp_version; /* last compatible version */ /* version 2 fields below */ - u32 boot_cpuid_phys; /* Which physical CPU id we're booting on */ + u32 boot_cpuid_phys; /* Physical CPU id we're booting on */ + /* version 3 fields below */ + u32 dt_strings_size; /* size of the DT strings block */ }; diff --git a/include/asm-ppc64/resource.h b/include/asm-ppc64/resource.h deleted file mode 100644 index add031b9dfd4..000000000000 --- a/include/asm-ppc64/resource.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _PPC64_RESOURCE_H -#define _PPC64_RESOURCE_H - -#include <asm-generic/resource.h> - -#endif /* _PPC64_RESOURCE_H */ diff --git a/include/asm-ppc64/shmparam.h b/include/asm-ppc64/shmparam.h deleted file mode 100644 index b2825ceff05e..000000000000 --- a/include/asm-ppc64/shmparam.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _PPC64_SHMPARAM_H -#define _PPC64_SHMPARAM_H - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ - -#endif /* _PPC64_SHMPARAM_H */ diff --git a/include/asm-ppc64/socket.h b/include/asm-ppc64/socket.h index 59e00dfc8b8e..9e1af8eb2d96 100644 --- a/include/asm-ppc64/socket.h +++ b/include/asm-ppc64/socket.h @@ -21,6 +21,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-ppc64/string.h b/include/asm-ppc64/string.h deleted file mode 100644 index eeca68ef1e91..000000000000 --- a/include/asm-ppc64/string.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef _PPC64_STRING_H_ -#define _PPC64_STRING_H_ - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRNCPY -#define __HAVE_ARCH_STRLEN -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRCAT -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMCHR - -extern int strcasecmp(const char *, const char *); -extern int strncasecmp(const char *, const char *, int); -extern char * strcpy(char *,const char *); -extern char * strncpy(char *,const char *, __kernel_size_t); -extern __kernel_size_t strlen(const char *); -extern int strcmp(const char *,const char *); -extern char * strcat(char *, const char *); -extern void * memset(void *,int,__kernel_size_t); -extern void * memcpy(void *,const void *,__kernel_size_t); -extern void * memmove(void *,const void *,__kernel_size_t); -extern int memcmp(const void *,const void *,__kernel_size_t); -extern void * memchr(const void *,int,__kernel_size_t); - -#endif /* _PPC64_STRING_H_ */ diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h index 98d120ca8a91..b9e1835351e9 100644 --- a/include/asm-ppc64/system.h +++ b/include/asm-ppc64/system.h @@ -88,7 +88,7 @@ DEBUGGER_BOILERPLATE(debugger_dabr_match) DEBUGGER_BOILERPLATE(debugger_fault_handler) #ifdef CONFIG_XMON -extern void xmon_init(void); +extern void xmon_init(int enable); #endif #else @@ -302,5 +302,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) #define arch_align_stack(x) (x) +extern unsigned long reloc_offset(void); + #endif /* __KERNEL__ */ #endif diff --git a/include/asm-ppc64/topology.h b/include/asm-ppc64/topology.h index fcdcfd26a26b..1e9b19073230 100644 --- a/include/asm-ppc64/topology.h +++ b/include/asm-ppc64/topology.h @@ -33,6 +33,7 @@ static inline int node_to_first_cpu(int node) return first_cpu(tmp); } +#define pcibus_to_node(node) (-1) #define pcibus_to_cpumask(bus) (cpu_online_map) #define nr_cpus_node(node) (nr_cpus_in_node[node]) @@ -59,8 +60,10 @@ static inline int node_to_first_cpu(int node) .nr_balance_failed = 0, \ } -#endif /* CONFIG_NUMA */ +#else #include <asm-generic/topology.h> +#endif /* CONFIG_NUMA */ + #endif /* _ASM_PPC64_TOPOLOGY_H */ diff --git a/include/asm-ppc64/types.h b/include/asm-ppc64/types.h index 5b8c2cfa1138..bf294c1761b2 100644 --- a/include/asm-ppc64/types.h +++ b/include/asm-ppc64/types.h @@ -72,7 +72,6 @@ typedef struct { unsigned long env; } func_descr_t; -typedef unsigned int kmem_bufctl_t; #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc64/unaligned.h b/include/asm-ppc64/unaligned.h deleted file mode 100644 index 636e93c4f379..000000000000 --- a/include/asm-ppc64/unaligned.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __PPC64_UNALIGNED_H -#define __PPC64_UNALIGNED_H - -/* - * The PowerPC can do unaligned accesses itself in big endian mode. - * - * The strange macros are there to make sure these can't - * be misused in a way that makes them not work on other - * architectures where unaligned accesses aren't as simple. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define get_unaligned(ptr) (*(ptr)) - -#define put_unaligned(val, ptr) ((void)( *(ptr) = (val) )) - -#endif /* __PPC64_UNALIGNED_H */ diff --git a/include/asm-ppc64/unistd.h b/include/asm-ppc64/unistd.h index 4a94acf6bfed..977bc980c1af 100644 --- a/include/asm-ppc64/unistd.h +++ b/include/asm-ppc64/unistd.h @@ -285,8 +285,11 @@ #define __NR_waitid 272 #define __NR_ioprio_set 273 #define __NR_ioprio_get 274 +#define __NR_inotify_init 275 +#define __NR_inotify_add_watch 276 +#define __NR_inotify_rm_watch 277 -#define __NR_syscalls 275 +#define __NR_syscalls 278 #ifdef __KERNEL__ #define NR_syscalls __NR_syscalls #endif diff --git a/include/asm-ppc64/vio.h b/include/asm-ppc64/vio.h index 20cd98ee6337..03f1b95f433b 100644 --- a/include/asm-ppc64/vio.h +++ b/include/asm-ppc64/vio.h @@ -19,13 +19,15 @@ #include <linux/errno.h> #include <linux/device.h> #include <linux/dma-mapping.h> +#include <linux/mod_devicetable.h> + #include <asm/hvcall.h> -#include <asm/prom.h> #include <asm/scatterlist.h> -/* + +/* * Architecture-specific constants for drivers to * extract attributes of the device using vio_get_attribute() -*/ + */ #define VETH_MAC_ADDR "local-mac-address" #define VETH_MCAST_FILTER_SIZE "ibm,mac-address-filters" @@ -37,64 +39,65 @@ #define VIO_IRQ_DISABLE 0UL #define VIO_IRQ_ENABLE 1UL -struct vio_dev; -struct vio_driver; -struct vio_device_id; struct iommu_table; -int vio_register_driver(struct vio_driver *drv); -void vio_unregister_driver(struct vio_driver *drv); - -#ifdef CONFIG_PPC_PSERIES -struct vio_dev * __devinit vio_register_device_node( - struct device_node *node_vdev); -#endif -void __devinit vio_unregister_device(struct vio_dev *dev); -struct vio_dev *vio_find_node(struct device_node *vnode); - -const void * vio_get_attribute(struct vio_dev *vdev, void* which, int* length); -int vio_get_irq(struct vio_dev *dev); -int vio_enable_interrupts(struct vio_dev *dev); -int vio_disable_interrupts(struct vio_dev *dev); - -extern struct dma_mapping_ops vio_dma_ops; - -extern struct bus_type vio_bus_type; - -struct vio_device_id { +/* + * The vio_dev structure is used to describe virtual I/O devices. + */ +struct vio_dev { + struct iommu_table *iommu_table; /* vio_map_* uses this */ + char *name; char *type; - char *compat; + uint32_t unit_address; + unsigned int irq; + struct device dev; }; struct vio_driver { struct list_head node; char *name; - const struct vio_device_id *id_table; /* NULL if wants all devices */ - int (*probe) (struct vio_dev *dev, const struct vio_device_id *id); /* New device inserted */ - int (*remove) (struct vio_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ + const struct vio_device_id *id_table; + int (*probe)(struct vio_dev *dev, const struct vio_device_id *id); + int (*remove)(struct vio_dev *dev); unsigned long driver_data; - struct device_driver driver; }; +struct vio_bus_ops { + int (*match)(const struct vio_device_id *id, const struct vio_dev *dev); + void (*unregister_device)(struct vio_dev *); + void (*release_device)(struct device *); +}; + +extern struct dma_mapping_ops vio_dma_ops; +extern struct bus_type vio_bus_type; +extern struct vio_dev vio_bus_device; + +extern int vio_register_driver(struct vio_driver *drv); +extern void vio_unregister_driver(struct vio_driver *drv); + +extern struct vio_dev * __devinit vio_register_device(struct vio_dev *viodev); +extern void __devinit vio_unregister_device(struct vio_dev *dev); + +extern int vio_bus_init(struct vio_bus_ops *); + +#ifdef CONFIG_PPC_PSERIES +struct device_node; + +extern struct vio_dev * __devinit vio_register_device_node( + struct device_node *node_vdev); +extern struct vio_dev *vio_find_node(struct device_node *vnode); +extern const void *vio_get_attribute(struct vio_dev *vdev, void *which, + int *length); +extern int vio_enable_interrupts(struct vio_dev *dev); +extern int vio_disable_interrupts(struct vio_dev *dev); +#endif + static inline struct vio_driver *to_vio_driver(struct device_driver *drv) { return container_of(drv, struct vio_driver, driver); } -/* - * The vio_dev structure is used to describe virtual I/O devices. - */ -struct vio_dev { - struct iommu_table *iommu_table; /* vio_map_* uses this */ - char *name; - char *type; - uint32_t unit_address; - unsigned int irq; - - struct device dev; -}; - static inline struct vio_dev *to_vio_dev(struct device *dev) { return container_of(dev, struct vio_dev, dev); diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h index 0c45e14e26ca..1092af55d707 100644 --- a/include/asm-ppc64/xics.h +++ b/include/asm-ppc64/xics.h @@ -17,7 +17,7 @@ void xics_init_IRQ(void); int xics_get_irq(struct pt_regs *); void xics_setup_cpu(void); -void xics_teardown_cpu(void); +void xics_teardown_cpu(int secondary); void xics_cause_IPI(int cpu); void xics_request_IPIs(void); void xics_migrate_irqs_away(void); diff --git a/include/asm-ppc64/xor.h b/include/asm-ppc64/xor.h deleted file mode 100644 index c82eb12a5b18..000000000000 --- a/include/asm-ppc64/xor.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/xor.h> diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h index d5a05cf47168..9d86ba6f12d0 100644 --- a/include/asm-s390/atomic.h +++ b/include/asm-s390/atomic.h @@ -123,19 +123,19 @@ typedef struct { #define atomic64_read(v) ((v)->counter) #define atomic64_set(v,i) (((v)->counter) = (i)) -static __inline__ void atomic64_add(int i, atomic64_t * v) +static __inline__ void atomic64_add(long long i, atomic64_t * v) { __CSG_LOOP(v, i, "agr"); } -static __inline__ long long atomic64_add_return(int i, atomic64_t * v) +static __inline__ long long atomic64_add_return(long long i, atomic64_t * v) { return __CSG_LOOP(v, i, "agr"); } -static __inline__ long long atomic64_add_negative(int i, atomic64_t * v) +static __inline__ long long atomic64_add_negative(long long i, atomic64_t * v) { return __CSG_LOOP(v, i, "agr") < 0; } -static __inline__ void atomic64_sub(int i, atomic64_t * v) +static __inline__ void atomic64_sub(long long i, atomic64_t * v) { __CSG_LOOP(v, i, "sgr"); } diff --git a/include/asm-s390/bitops.h b/include/asm-s390/bitops.h index 16bb08499c7f..8651524217fd 100644 --- a/include/asm-s390/bitops.h +++ b/include/asm-s390/bitops.h @@ -527,13 +527,64 @@ __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) { __constant_test_bit((nr),(addr)) : \ __test_bit((nr),(addr)) ) -#ifndef __s390x__ +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + unsigned long bit = 0; + +#ifdef __s390x__ + if (likely((word & 0xffffffff) == 0xffffffff)) { + word >>= 32; + bit += 32; + } +#endif + if (likely((word & 0xffff) == 0xffff)) { + word >>= 16; + bit += 16; + } + if (likely((word & 0xff) == 0xff)) { + word >>= 8; + bit += 8; + } + return bit + _zb_findmap[word & 0xff]; +} + +/* + * __ffs = find first bit in word. Undefined if no bit exists, + * so code should check against 0UL first.. + */ +static inline unsigned long __ffs (unsigned long word) +{ + unsigned long bit = 0; + +#ifdef __s390x__ + if (likely((word & 0xffffffff) == 0)) { + word >>= 32; + bit += 32; + } +#endif + if (likely((word & 0xffff) == 0)) { + word >>= 16; + bit += 16; + } + if (likely((word & 0xff) == 0)) { + word >>= 8; + bit += 8; + } + return bit + _sb_findmap[word & 0xff]; +} /* * Find-bit routines.. */ + +#ifndef __s390x__ + static inline int -find_first_zero_bit(const unsigned long * addr, unsigned int size) +find_first_zero_bit(const unsigned long * addr, unsigned long size) { typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; unsigned long cmp, count; @@ -548,7 +599,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size) " srl %2,5\n" "0: c %1,0(%0,%4)\n" " jne 1f\n" - " ahi %0,4\n" + " la %0,4(%0)\n" " brct %2,0b\n" " lr %0,%3\n" " j 4f\n" @@ -574,7 +625,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size) } static inline int -find_first_bit(const unsigned long * addr, unsigned int size) +find_first_bit(const unsigned long * addr, unsigned long size) { typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; unsigned long cmp, count; @@ -589,7 +640,7 @@ find_first_bit(const unsigned long * addr, unsigned int size) " srl %2,5\n" "0: c %1,0(%0,%4)\n" " jne 1f\n" - " ahi %0,4\n" + " la %0,4(%0)\n" " brct %2,0b\n" " lr %0,%3\n" " j 4f\n" @@ -614,89 +665,8 @@ find_first_bit(const unsigned long * addr, unsigned int size) return (res < size) ? res : size; } -static inline int -find_next_zero_bit (const unsigned long * addr, int size, int offset) -{ - unsigned long * p = ((unsigned long *) addr) + (offset >> 5); - unsigned long bitvec, reg; - int set, bit = offset & 31, res; - - if (bit) { - /* - * Look for zero in first word - */ - bitvec = (*p) >> bit; - __asm__(" slr %0,%0\n" - " lhi %2,0xff\n" - " tml %1,0xffff\n" - " jno 0f\n" - " ahi %0,16\n" - " srl %1,16\n" - "0: tml %1,0x00ff\n" - " jno 1f\n" - " ahi %0,8\n" - " srl %1,8\n" - "1: nr %1,%2\n" - " ic %1,0(%1,%3)\n" - " alr %0,%1" - : "=&d" (set), "+a" (bitvec), "=&d" (reg) - : "a" (&_zb_findmap) : "cc" ); - if (set < (32 - bit)) - return set + offset; - offset += 32 - bit; - p++; - } - /* - * No zero yet, search remaining full words for a zero - */ - res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr)); - return (offset + res); -} - -static inline int -find_next_bit (const unsigned long * addr, int size, int offset) -{ - unsigned long * p = ((unsigned long *) addr) + (offset >> 5); - unsigned long bitvec, reg; - int set, bit = offset & 31, res; - - if (bit) { - /* - * Look for set bit in first word - */ - bitvec = (*p) >> bit; - __asm__(" slr %0,%0\n" - " lhi %2,0xff\n" - " tml %1,0xffff\n" - " jnz 0f\n" - " ahi %0,16\n" - " srl %1,16\n" - "0: tml %1,0x00ff\n" - " jnz 1f\n" - " ahi %0,8\n" - " srl %1,8\n" - "1: nr %1,%2\n" - " ic %1,0(%1,%3)\n" - " alr %0,%1" - : "=&d" (set), "+a" (bitvec), "=&d" (reg) - : "a" (&_sb_findmap) : "cc" ); - if (set < (32 - bit)) - return set + offset; - offset += 32 - bit; - p++; - } - /* - * No set bit yet, search remaining full words for a bit - */ - res = find_first_bit (p, size - 32 * (p - (unsigned long *) addr)); - return (offset + res); -} - #else /* __s390x__ */ -/* - * Find-bit routines.. - */ static inline unsigned long find_first_zero_bit(const unsigned long * addr, unsigned long size) { @@ -712,7 +682,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size) " srlg %2,%2,6\n" "0: cg %1,0(%0,%4)\n" " jne 1f\n" - " aghi %0,8\n" + " la %0,8(%0)\n" " brct %2,0b\n" " lgr %0,%3\n" " j 5f\n" @@ -785,143 +755,66 @@ find_first_bit(const unsigned long * addr, unsigned long size) return (res < size) ? res : size; } -static inline unsigned long -find_next_zero_bit (const unsigned long * addr, unsigned long size, unsigned long offset) -{ - unsigned long * p = ((unsigned long *) addr) + (offset >> 6); - unsigned long bitvec, reg; - unsigned long set, bit = offset & 63, res; - - if (bit) { - /* - * Look for zero in first word - */ - bitvec = (*p) >> bit; - __asm__(" lhi %2,-1\n" - " slgr %0,%0\n" - " clr %1,%2\n" - " jne 0f\n" - " aghi %0,32\n" - " srlg %1,%1,32\n" - "0: lghi %2,0xff\n" - " tmll %1,0xffff\n" - " jno 1f\n" - " aghi %0,16\n" - " srlg %1,%1,16\n" - "1: tmll %1,0x00ff\n" - " jno 2f\n" - " aghi %0,8\n" - " srlg %1,%1,8\n" - "2: ngr %1,%2\n" - " ic %1,0(%1,%3)\n" - " algr %0,%1" - : "=&d" (set), "+a" (bitvec), "=&d" (reg) - : "a" (&_zb_findmap) : "cc" ); - if (set < (64 - bit)) - return set + offset; - offset += 64 - bit; - p++; - } - /* - * No zero yet, search remaining full words for a zero - */ - res = find_first_zero_bit (p, size - 64 * (p - (unsigned long *) addr)); - return (offset + res); -} - -static inline unsigned long -find_next_bit (const unsigned long * addr, unsigned long size, unsigned long offset) -{ - unsigned long * p = ((unsigned long *) addr) + (offset >> 6); - unsigned long bitvec, reg; - unsigned long set, bit = offset & 63, res; - - if (bit) { - /* - * Look for zero in first word - */ - bitvec = (*p) >> bit; - __asm__(" slgr %0,%0\n" - " ltr %1,%1\n" - " jnz 0f\n" - " aghi %0,32\n" - " srlg %1,%1,32\n" - "0: lghi %2,0xff\n" - " tmll %1,0xffff\n" - " jnz 1f\n" - " aghi %0,16\n" - " srlg %1,%1,16\n" - "1: tmll %1,0x00ff\n" - " jnz 2f\n" - " aghi %0,8\n" - " srlg %1,%1,8\n" - "2: ngr %1,%2\n" - " ic %1,0(%1,%3)\n" - " algr %0,%1" - : "=&d" (set), "+a" (bitvec), "=&d" (reg) - : "a" (&_sb_findmap) : "cc" ); - if (set < (64 - bit)) - return set + offset; - offset += 64 - bit; - p++; - } - /* - * No set bit yet, search remaining full words for a bit - */ - res = find_first_bit (p, size - 64 * (p - (unsigned long *) addr)); - return (offset + res); -} - #endif /* __s390x__ */ -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) +static inline int +find_next_zero_bit (const unsigned long * addr, unsigned long size, + unsigned long offset) { - unsigned long bit = 0; - -#ifdef __s390x__ - if (likely((word & 0xffffffff) == 0xffffffff)) { - word >>= 32; - bit += 32; - } -#endif - if (likely((word & 0xffff) == 0xffff)) { - word >>= 16; - bit += 16; + const unsigned long *p; + unsigned long bit, set; + + if (offset >= size) + return size; + bit = offset & (__BITOPS_WORDSIZE - 1); + offset -= bit; + size -= offset; + p = addr + offset / __BITOPS_WORDSIZE; + if (bit) { + /* + * s390 version of ffz returns __BITOPS_WORDSIZE + * if no zero bit is present in the word. + */ + set = ffz(*p >> bit) + bit; + if (set >= size) + return size + offset; + if (set < __BITOPS_WORDSIZE) + return set + offset; + offset += __BITOPS_WORDSIZE; + size -= __BITOPS_WORDSIZE; + p++; } - if (likely((word & 0xff) == 0xff)) { - word >>= 8; - bit += 8; - } - return bit + _zb_findmap[word & 0xff]; + return offset + find_first_zero_bit(p, size); } -/* - * __ffs = find first bit in word. Undefined if no bit exists, - * so code should check against 0UL first.. - */ -static inline unsigned long __ffs (unsigned long word) +static inline int +find_next_bit (const unsigned long * addr, unsigned long size, + unsigned long offset) { - unsigned long bit = 0; - -#ifdef __s390x__ - if (likely((word & 0xffffffff) == 0)) { - word >>= 32; - bit += 32; + const unsigned long *p; + unsigned long bit, set; + + if (offset >= size) + return size; + bit = offset & (__BITOPS_WORDSIZE - 1); + offset -= bit; + size -= offset; + p = addr + offset / __BITOPS_WORDSIZE; + if (bit) { + /* + * s390 version of __ffs returns __BITOPS_WORDSIZE + * if no one bit is present in the word. + */ + set = __ffs(*p & (~0UL << bit)); + if (set >= size) + return size + offset; + if (set < __BITOPS_WORDSIZE) + return set + offset; + offset += __BITOPS_WORDSIZE; + size -= __BITOPS_WORDSIZE; + p++; } -#endif - if (likely((word & 0xffff) == 0)) { - word >>= 16; - bit += 16; - } - if (likely((word & 0xff) == 0)) { - word >>= 8; - bit += 8; - } - return bit + _sb_findmap[word & 0xff]; + return offset + find_first_bit(p, size); } /* @@ -1031,49 +924,6 @@ ext2_find_first_zero_bit(void *vaddr, unsigned int size) return (res < size) ? res : size; } -static inline int -ext2_find_next_zero_bit(void *vaddr, unsigned int size, unsigned offset) -{ - unsigned long *addr = vaddr; - unsigned long *p = addr + (offset >> 5); - unsigned long word, reg; - unsigned int bit = offset & 31UL, res; - - if (offset >= size) - return size; - - if (bit) { - __asm__(" ic %0,0(%1)\n" - " icm %0,2,1(%1)\n" - " icm %0,4,2(%1)\n" - " icm %0,8,3(%1)" - : "=&a" (word) : "a" (p) : "cc" ); - word >>= bit; - res = bit; - /* Look for zero in first longword */ - __asm__(" lhi %2,0xff\n" - " tml %1,0xffff\n" - " jno 0f\n" - " ahi %0,16\n" - " srl %1,16\n" - "0: tml %1,0x00ff\n" - " jno 1f\n" - " ahi %0,8\n" - " srl %1,8\n" - "1: nr %1,%2\n" - " ic %1,0(%1,%3)\n" - " alr %0,%1" - : "+&d" (res), "+&a" (word), "=&d" (reg) - : "a" (&_zb_findmap) : "cc" ); - if (res < 32) - return (p - addr)*32 + res; - p++; - } - /* No zero yet, search remaining full bytes for a zero */ - res = ext2_find_first_zero_bit (p, size - 32 * (p - addr)); - return (p - addr) * 32 + res; -} - #else /* __s390x__ */ static inline unsigned long @@ -1120,56 +970,46 @@ ext2_find_first_zero_bit(void *vaddr, unsigned long size) return (res < size) ? res : size; } -static inline unsigned long +#endif /* __s390x__ */ + +static inline int ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset) { - unsigned long *addr = vaddr; - unsigned long *p = addr + (offset >> 6); - unsigned long word, reg; - unsigned long bit = offset & 63UL, res; + unsigned long *addr = vaddr, *p; + unsigned long word, bit, set; if (offset >= size) return size; - + bit = offset & (__BITOPS_WORDSIZE - 1); + offset -= bit; + size -= offset; + p = addr + offset / __BITOPS_WORDSIZE; if (bit) { - __asm__(" lrvg %0,%1" /* load reversed, neat instruction */ - : "=a" (word) : "m" (*p) ); - word >>= bit; - res = bit; - /* Look for zero in first 8 byte word */ - __asm__(" lghi %2,0xff\n" - " tmll %1,0xffff\n" - " jno 2f\n" - " ahi %0,16\n" - " srlg %1,%1,16\n" - "0: tmll %1,0xffff\n" - " jno 2f\n" - " ahi %0,16\n" - " srlg %1,%1,16\n" - "1: tmll %1,0xffff\n" - " jno 2f\n" - " ahi %0,16\n" - " srl %1,16\n" - "2: tmll %1,0x00ff\n" - " jno 3f\n" - " ahi %0,8\n" - " srl %1,8\n" - "3: ngr %1,%2\n" - " ic %1,0(%1,%3)\n" - " alr %0,%1" - : "+&d" (res), "+a" (word), "=&d" (reg) - : "a" (&_zb_findmap) : "cc" ); - if (res < 64) - return (p - addr)*64 + res; - p++; +#ifndef __s390x__ + asm(" ic %0,0(%1)\n" + " icm %0,2,1(%1)\n" + " icm %0,4,2(%1)\n" + " icm %0,8,3(%1)" + : "=&a" (word) : "a" (p), "m" (*p) : "cc" ); +#else + asm(" lrvg %0,%1" : "=a" (word) : "m" (*p) ); +#endif + /* + * s390 version of ffz returns __BITOPS_WORDSIZE + * if no zero bit is present in the word. + */ + set = ffz(word >> bit) + bit; + if (set >= size) + return size + offset; + if (set < __BITOPS_WORDSIZE) + return set + offset; + offset += __BITOPS_WORDSIZE; + size -= __BITOPS_WORDSIZE; + p++; } - /* No zero yet, search remaining full bytes for a zero */ - res = ext2_find_first_zero_bit (p, size - 64 * (p - addr)); - return (p - addr) * 64 + res; + return offset + ext2_find_first_zero_bit(p, size); } -#endif /* __s390x__ */ - /* Bitmap functions for the minix filesystem. */ /* FIXME !!! */ #define minix_test_and_set_bit(nr,addr) \ diff --git a/include/asm-s390/debug.h b/include/asm-s390/debug.h index 92360d90144b..7127030ae162 100644 --- a/include/asm-s390/debug.h +++ b/include/asm-s390/debug.h @@ -52,8 +52,6 @@ struct __debug_entry{ #define DEBUG_DATA(entry) (char*)(entry + 1) /* data is stored behind */ /* the entry information */ -#define STCK(x) asm volatile ("STCK 0(%1)" : "=m" (x) : "a" (&(x)) : "cc") - typedef struct __debug_entry debug_entry_t; struct debug_view; diff --git a/include/asm-s390/emergency-restart.h b/include/asm-s390/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-s390/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h index 76b5b19c0ae2..c6f51c9ce3ff 100644 --- a/include/asm-s390/lowcore.h +++ b/include/asm-s390/lowcore.h @@ -68,6 +68,7 @@ #define __LC_SYSTEM_TIMER 0x270 #define __LC_LAST_UPDATE_CLOCK 0x278 #define __LC_STEAL_CLOCK 0x280 +#define __LC_RETURN_MCCK_PSW 0x288 #define __LC_KERNEL_STACK 0xC40 #define __LC_THREAD_INFO 0xC44 #define __LC_ASYNC_STACK 0xC48 @@ -90,7 +91,7 @@ #define __LC_SYSTEM_TIMER 0x278 #define __LC_LAST_UPDATE_CLOCK 0x280 #define __LC_STEAL_CLOCK 0x288 -#define __LC_DIAG44_OPCODE 0x290 +#define __LC_RETURN_MCCK_PSW 0x290 #define __LC_KERNEL_STACK 0xD40 #define __LC_THREAD_INFO 0xD48 #define __LC_ASYNC_STACK 0xD50 @@ -197,7 +198,8 @@ struct _lowcore __u64 system_timer; /* 0x270 */ __u64 last_update_clock; /* 0x278 */ __u64 steal_clock; /* 0x280 */ - __u8 pad8[0xc00-0x288]; /* 0x288 */ + psw_t return_mcck_psw; /* 0x288 */ + __u8 pad8[0xc00-0x290]; /* 0x290 */ /* System info area */ __u32 save_area[16]; /* 0xc00 */ @@ -286,8 +288,8 @@ struct _lowcore __u64 system_timer; /* 0x278 */ __u64 last_update_clock; /* 0x280 */ __u64 steal_clock; /* 0x288 */ - __u32 diag44_opcode; /* 0x290 */ - __u8 pad8[0xc00-0x294]; /* 0x294 */ + psw_t return_mcck_psw; /* 0x290 */ + __u8 pad8[0xc00-0x2a0]; /* 0x2a0 */ /* System info area */ __u64 save_area[16]; /* 0xc00 */ __u8 pad9[0xd40-0xc80]; /* 0xc80 */ diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h index 2be287b9df88..2430c561e021 100644 --- a/include/asm-s390/page.h +++ b/include/asm-s390/page.h @@ -111,20 +111,6 @@ static inline void copy_page(void *to, void *from) #define alloc_zeroed_user_highpage(vma, vaddr) alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO, vma, vaddr) #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - /* * These are used to make use of C type-checking.. */ @@ -207,4 +193,6 @@ page_get_storage_key(unsigned long addr) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _S390_PAGE_H */ diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h index 8bd14de69e35..4ec652ebb3b1 100644 --- a/include/asm-s390/processor.h +++ b/include/asm-s390/processor.h @@ -203,7 +203,10 @@ unsigned long get_wchan(struct task_struct *p); # define cpu_relax() asm volatile ("diag 0,0,68" : : : "memory") #else /* __s390x__ */ # define cpu_relax() \ - asm volatile ("ex 0,%0" : : "i" (__LC_DIAG44_OPCODE) : "memory") + do { \ + if (MACHINE_HAS_DIAG44) \ + asm volatile ("diag 0,0,68" : : : "memory"); \ + } while (0) #endif /* __s390x__ */ /* diff --git a/include/asm-s390/socket.h b/include/asm-s390/socket.h index 0e96eeca4e6b..15a5298c8744 100644 --- a/include/asm-s390/socket.h +++ b/include/asm-s390/socket.h @@ -22,6 +22,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h index 53cc736b9820..321b23bba1ec 100644 --- a/include/asm-s390/spinlock.h +++ b/include/asm-s390/spinlock.h @@ -11,21 +11,16 @@ #ifndef __ASM_SPINLOCK_H #define __ASM_SPINLOCK_H -#ifdef __s390x__ -/* - * Grmph, take care of %&#! user space programs that include - * asm/spinlock.h. The diagnose is only available in kernel - * context. - */ -#ifdef __KERNEL__ -#include <asm/lowcore.h> -#define __DIAG44_INSN "ex" -#define __DIAG44_OPERAND __LC_DIAG44_OPCODE -#else -#define __DIAG44_INSN "#" -#define __DIAG44_OPERAND 0 -#endif -#endif /* __s390x__ */ +static inline int +_raw_compare_and_swap(volatile unsigned int *lock, + unsigned int old, unsigned int new) +{ + asm volatile ("cs %0,%3,0(%4)" + : "=d" (old), "=m" (*lock) + : "0" (old), "d" (new), "a" (lock), "m" (*lock) + : "cc", "memory" ); + return old; +} /* * Simple spin lock operations. There are two variants, one clears IRQ's @@ -41,58 +36,35 @@ typedef struct { #endif } __attribute__ ((aligned (4))) spinlock_t; -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } -#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0) +#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } +#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0) #define spin_unlock_wait(lp) do { barrier(); } while(((volatile spinlock_t *)(lp))->lock) -#define spin_is_locked(x) ((x)->lock != 0) +#define spin_is_locked(x) ((x)->lock != 0) #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) -extern inline void _raw_spin_lock(spinlock_t *lp) +extern void _raw_spin_lock_wait(spinlock_t *lp, unsigned int pc); +extern int _raw_spin_trylock_retry(spinlock_t *lp, unsigned int pc); + +static inline void _raw_spin_lock(spinlock_t *lp) { -#ifndef __s390x__ - unsigned int reg1, reg2; - __asm__ __volatile__(" bras %0,1f\n" - "0: diag 0,0,68\n" - "1: slr %1,%1\n" - " cs %1,%0,0(%3)\n" - " jl 0b\n" - : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock) - : "a" (&lp->lock), "m" (lp->lock) - : "cc", "memory" ); -#else /* __s390x__ */ - unsigned long reg1, reg2; - __asm__ __volatile__(" bras %1,1f\n" - "0: " __DIAG44_INSN " 0,%4\n" - "1: slr %0,%0\n" - " cs %0,%1,0(%3)\n" - " jl 0b\n" - : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock) - : "a" (&lp->lock), "i" (__DIAG44_OPERAND), - "m" (lp->lock) : "cc", "memory" ); -#endif /* __s390x__ */ + unsigned long pc = 1 | (unsigned long) __builtin_return_address(0); + + if (unlikely(_raw_compare_and_swap(&lp->lock, 0, pc) != 0)) + _raw_spin_lock_wait(lp, pc); } -extern inline int _raw_spin_trylock(spinlock_t *lp) +static inline int _raw_spin_trylock(spinlock_t *lp) { - unsigned long reg; - unsigned int result; - - __asm__ __volatile__(" basr %1,0\n" - "0: cs %0,%1,0(%3)" - : "=d" (result), "=&d" (reg), "=m" (lp->lock) - : "a" (&lp->lock), "m" (lp->lock), "0" (0) - : "cc", "memory" ); - return !result; + unsigned long pc = 1 | (unsigned long) __builtin_return_address(0); + + if (likely(_raw_compare_and_swap(&lp->lock, 0, pc) == 0)) + return 1; + return _raw_spin_trylock_retry(lp, pc); } -extern inline void _raw_spin_unlock(spinlock_t *lp) +static inline void _raw_spin_unlock(spinlock_t *lp) { - unsigned int old; - - __asm__ __volatile__("cs %0,%3,0(%4)" - : "=d" (old), "=m" (lp->lock) - : "0" (lp->lock), "d" (0), "a" (lp) - : "cc", "memory" ); + _raw_compare_and_swap(&lp->lock, lp->lock, 0); } /* @@ -106,7 +78,7 @@ extern inline void _raw_spin_unlock(spinlock_t *lp) * read-locks. */ typedef struct { - volatile unsigned long lock; + volatile unsigned int lock; volatile unsigned long owner_pc; #ifdef CONFIG_PREEMPT unsigned int break_lock; @@ -129,123 +101,55 @@ typedef struct { */ #define write_can_lock(x) ((x)->lock == 0) -#ifndef __s390x__ -#define _raw_read_lock(rw) \ - asm volatile(" l 2,0(%1)\n" \ - " j 1f\n" \ - "0: diag 0,0,68\n" \ - "1: la 2,0(2)\n" /* clear high (=write) bit */ \ - " la 3,1(2)\n" /* one more reader */ \ - " cs 2,3,0(%1)\n" /* try to write new value */ \ - " jl 0b" \ - : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#else /* __s390x__ */ -#define _raw_read_lock(rw) \ - asm volatile(" lg 2,0(%1)\n" \ - " j 1f\n" \ - "0: " __DIAG44_INSN " 0,%2\n" \ - "1: nihh 2,0x7fff\n" /* clear high (=write) bit */ \ - " la 3,1(2)\n" /* one more reader */ \ - " csg 2,3,0(%1)\n" /* try to write new value */ \ - " jl 0b" \ - : "=m" ((rw)->lock) \ - : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#endif /* __s390x__ */ - -#ifndef __s390x__ -#define _raw_read_unlock(rw) \ - asm volatile(" l 2,0(%1)\n" \ - " j 1f\n" \ - "0: diag 0,0,68\n" \ - "1: lr 3,2\n" \ - " ahi 3,-1\n" /* one less reader */ \ - " cs 2,3,0(%1)\n" \ - " jl 0b" \ - : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#else /* __s390x__ */ -#define _raw_read_unlock(rw) \ - asm volatile(" lg 2,0(%1)\n" \ - " j 1f\n" \ - "0: " __DIAG44_INSN " 0,%2\n" \ - "1: lgr 3,2\n" \ - " bctgr 3,0\n" /* one less reader */ \ - " csg 2,3,0(%1)\n" \ - " jl 0b" \ - : "=m" ((rw)->lock) \ - : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#endif /* __s390x__ */ - -#ifndef __s390x__ -#define _raw_write_lock(rw) \ - asm volatile(" lhi 3,1\n" \ - " sll 3,31\n" /* new lock value = 0x80000000 */ \ - " j 1f\n" \ - "0: diag 0,0,68\n" \ - "1: slr 2,2\n" /* old lock value must be 0 */ \ - " cs 2,3,0(%1)\n" \ - " jl 0b" \ - : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#else /* __s390x__ */ -#define _raw_write_lock(rw) \ - asm volatile(" llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \ - " j 1f\n" \ - "0: " __DIAG44_INSN " 0,%2\n" \ - "1: slgr 2,2\n" /* old lock value must be 0 */ \ - " csg 2,3,0(%1)\n" \ - " jl 0b" \ - : "=m" ((rw)->lock) \ - : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#endif /* __s390x__ */ - -#ifndef __s390x__ -#define _raw_write_unlock(rw) \ - asm volatile(" slr 3,3\n" /* new lock value = 0 */ \ - " j 1f\n" \ - "0: diag 0,0,68\n" \ - "1: lhi 2,1\n" \ - " sll 2,31\n" /* old lock value must be 0x80000000 */ \ - " cs 2,3,0(%1)\n" \ - " jl 0b" \ - : "=m" ((rw)->lock) : "a" (&(rw)->lock), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#else /* __s390x__ */ -#define _raw_write_unlock(rw) \ - asm volatile(" slgr 3,3\n" /* new lock value = 0 */ \ - " j 1f\n" \ - "0: " __DIAG44_INSN " 0,%2\n" \ - "1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\ - " csg 2,3,0(%1)\n" \ - " jl 0b" \ - : "=m" ((rw)->lock) \ - : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \ - "m" ((rw)->lock) : "2", "3", "cc", "memory" ) -#endif /* __s390x__ */ - -#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) - -extern inline int _raw_write_trylock(rwlock_t *rw) +extern void _raw_read_lock_wait(rwlock_t *lp); +extern int _raw_read_trylock_retry(rwlock_t *lp); +extern void _raw_write_lock_wait(rwlock_t *lp); +extern int _raw_write_trylock_retry(rwlock_t *lp); + +static inline void _raw_read_lock(rwlock_t *rw) +{ + unsigned int old; + old = rw->lock & 0x7fffffffU; + if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old) + _raw_read_lock_wait(rw); +} + +static inline void _raw_read_unlock(rwlock_t *rw) +{ + unsigned int old, cmp; + + old = rw->lock; + do { + cmp = old; + old = _raw_compare_and_swap(&rw->lock, old, old - 1); + } while (cmp != old); +} + +static inline void _raw_write_lock(rwlock_t *rw) +{ + if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0)) + _raw_write_lock_wait(rw); +} + +static inline void _raw_write_unlock(rwlock_t *rw) +{ + _raw_compare_and_swap(&rw->lock, 0x80000000, 0); +} + +static inline int _raw_read_trylock(rwlock_t *rw) +{ + unsigned int old; + old = rw->lock & 0x7fffffffU; + if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old)) + return 1; + return _raw_read_trylock_retry(rw); +} + +static inline int _raw_write_trylock(rwlock_t *rw) { - unsigned long result, reg; - - __asm__ __volatile__( -#ifndef __s390x__ - " lhi %1,1\n" - " sll %1,31\n" - " cs %0,%1,0(%3)" -#else /* __s390x__ */ - " llihh %1,0x8000\n" - "0: csg %0,%1,0(%3)\n" -#endif /* __s390x__ */ - : "=d" (result), "=&d" (reg), "=m" (rw->lock) - : "a" (&rw->lock), "m" (rw->lock), "0" (0UL) - : "cc", "memory" ); - return result == 0; + if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)) + return 1; + return _raw_write_trylock_retry(rw); } #endif /* __ASM_SPINLOCK_H */ diff --git a/include/asm-s390/types.h b/include/asm-s390/types.h index 3fefd61416a5..d0be3e477013 100644 --- a/include/asm-s390/types.h +++ b/include/asm-s390/types.h @@ -79,8 +79,6 @@ typedef unsigned long u64; typedef u32 dma_addr_t; -typedef unsigned int kmem_bufctl_t; - #ifndef __s390x__ typedef union { unsigned long long pair; diff --git a/include/asm-s390/uaccess.h b/include/asm-s390/uaccess.h index a7f43a251f81..3e3bfe6a8fa8 100644 --- a/include/asm-s390/uaccess.h +++ b/include/asm-s390/uaccess.h @@ -149,11 +149,11 @@ struct exception_table_entry }) #endif -#ifndef __CHECKER__ #define __put_user(x, ptr) \ ({ \ __typeof__(*(ptr)) __x = (x); \ int __pu_err; \ + __chk_user_ptr(ptr); \ switch (sizeof (*(ptr))) { \ case 1: \ case 2: \ @@ -167,14 +167,6 @@ struct exception_table_entry } \ __pu_err; \ }) -#else -#define __put_user(x, ptr) \ -({ \ - void __user *p; \ - p = (ptr); \ - 0; \ -}) -#endif #define put_user(x, ptr) \ ({ \ @@ -213,11 +205,11 @@ extern int __put_user_bad(void) __attribute__((noreturn)); }) #endif -#ifndef __CHECKER__ #define __get_user(x, ptr) \ ({ \ __typeof__(*(ptr)) __x; \ int __gu_err; \ + __chk_user_ptr(ptr); \ switch (sizeof(*(ptr))) { \ case 1: \ case 2: \ @@ -232,15 +224,6 @@ extern int __put_user_bad(void) __attribute__((noreturn)); (x) = __x; \ __gu_err; \ }) -#else -#define __get_user(x, ptr) \ -({ \ - void __user *p; \ - p = (ptr); \ - 0; \ -}) -#endif - #define get_user(x, ptr) \ ({ \ diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h index 363db45f8d07..221e965da924 100644 --- a/include/asm-s390/unistd.h +++ b/include/asm-s390/unistd.h @@ -274,8 +274,13 @@ #define __NR_request_key 279 #define __NR_keyctl 280 #define __NR_waitid 281 +#define __NR_ioprio_set 282 +#define __NR_ioprio_get 283 +#define __NR_inotify_init 284 +#define __NR_inotify_add_watch 285 +#define __NR_inotify_rm_watch 286 -#define NR_syscalls 282 +#define NR_syscalls 287 /* * There are some system calls that are not present on 64 bit, some diff --git a/include/asm-sh/emergency-restart.h b/include/asm-sh/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-sh/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index 180467be8e7b..324e6cc5ecf7 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h @@ -122,24 +122,8 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -#ifndef __ASSEMBLY__ - -/* Pure 2^n version of get_order */ -static __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif - #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* __ASM_SH_PAGE_H */ diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h index 26044889c770..0a523c85b11c 100644 --- a/include/asm-sh/pci.h +++ b/include/asm-sh/pci.h @@ -36,7 +36,7 @@ struct pci_dev; extern void pcibios_set_master(struct pci_dev *dev); -static inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-sh/socket.h b/include/asm-sh/socket.h index dde696c3b4c7..553904ff9336 100644 --- a/include/asm-sh/socket.h +++ b/include/asm-sh/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_RCVBUFFORCE 32 +#define SO_SNDBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h index c4dc126c5621..cb7e183a0a6b 100644 --- a/include/asm-sh/types.h +++ b/include/asm-sh/types.h @@ -58,8 +58,6 @@ typedef u64 sector_t; #define HAVE_SECTOR_T #endif -typedef unsigned int kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h index 245447081f0d..ea89e8f223ea 100644 --- a/include/asm-sh/unistd.h +++ b/include/asm-sh/unistd.h @@ -295,8 +295,14 @@ #define __NR_add_key 285 #define __NR_request_key 286 #define __NR_keyctl 287 +#define __NR_ioprio_set 288 +#define __NR_ioprio_get 289 +#define __NR_inotify_init 290 +#define __NR_inotify_add_watch 291 +#define __NR_inotify_rm_watch 292 -#define NR_syscalls 288 + +#define NR_syscalls 293 /* user-visible error numbers are in the range -1 - -124: see <asm-sh/errno.h> */ @@ -406,7 +412,7 @@ register long __sc6 __asm__ ("r6") = (long) arg3; \ register long __sc7 __asm__ ("r7") = (long) arg4; \ register long __sc0 __asm__ ("r0") = (long) arg5; \ register long __sc1 __asm__ ("r1") = (long) arg6; \ -__asm__ __volatile__ ("trapa #0x15" \ +__asm__ __volatile__ ("trapa #0x16" \ : "=z" (__sc0) \ : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \ "r" (__sc3), "r" (__sc1) \ diff --git a/include/asm-sh64/emergency-restart.h b/include/asm-sh64/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-sh64/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-sh64/page.h b/include/asm-sh64/page.h index d6167f1c0e99..c86df90f7cbd 100644 --- a/include/asm-sh64/page.h +++ b/include/asm-sh64/page.h @@ -115,24 +115,8 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -#ifndef __ASSEMBLY__ - -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif - #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* __ASM_SH64_PAGE_H */ diff --git a/include/asm-sh64/pci.h b/include/asm-sh64/pci.h index c68870e02d91..aa8043089bb6 100644 --- a/include/asm-sh64/pci.h +++ b/include/asm-sh64/pci.h @@ -26,7 +26,7 @@ extern void pcibios_set_master(struct pci_dev *dev); /* * Set penalize isa irq function */ -static inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-sh64/types.h b/include/asm-sh64/types.h index 41d4d2f82aa9..8d41db2153b5 100644 --- a/include/asm-sh64/types.h +++ b/include/asm-sh64/types.h @@ -65,8 +65,6 @@ typedef u32 dma_addr_t; #endif typedef u64 dma64_addr_t; -typedef unsigned int kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #define BITS_PER_LONG 32 diff --git a/include/asm-sh64/unistd.h b/include/asm-sh64/unistd.h index 95f0b130405c..2a1cfa404ea4 100644 --- a/include/asm-sh64/unistd.h +++ b/include/asm-sh64/unistd.h @@ -338,8 +338,13 @@ #define __NR_add_key 313 #define __NR_request_key 314 #define __NR_keyctl 315 +#define __NR_ioprio_set 316 +#define __NR_ioprio_get 317 +#define __NR_inotify_init 318 +#define __NR_inotify_add_watch 319 +#define __NR_inotify_rm_watch 320 -#define NR_syscalls 316 +#define NR_syscalls 321 /* user-visible error numbers are in the range -1 - -125: see <asm-sh64/errno.h> */ diff --git a/include/asm-sparc/emergency-restart.h b/include/asm-sparc/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-sparc/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h index 383060e90d94..9122684f6c1e 100644 --- a/include/asm-sparc/page.h +++ b/include/asm-sparc/page.h @@ -132,20 +132,6 @@ BTFIXUPDEF_SETHI(sparc_unmapped_base) #define TASK_UNMAPPED_BASE BTFIXUP_SETHI(sparc_unmapped_base) -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #else /* !(__ASSEMBLY__) */ #define __pgprot(x) (x) @@ -178,4 +164,6 @@ extern unsigned long pfn_base; #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _SPARC_PAGE_H */ diff --git a/include/asm-sparc/pci.h b/include/asm-sparc/pci.h index 44bb38758c96..97052baf90c1 100644 --- a/include/asm-sparc/pci.h +++ b/include/asm-sparc/pci.h @@ -20,7 +20,7 @@ extern inline void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -extern inline void pcibios_penalize_isa_irq(int irq) +extern inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h index 40ed30a2b7c6..8f4f6a959651 100644 --- a/include/asm-sparc/pgtable.h +++ b/include/asm-sparc/pgtable.h @@ -435,9 +435,6 @@ extern unsigned long *sparc_valid_addr_bitmap; #define kern_addr_valid(addr) \ (test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap)) -extern int io_remap_page_range(struct vm_area_struct *vma, - unsigned long from, unsigned long to, - unsigned long size, pgprot_t prot, int space); extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h index 32c9699367cf..5a7a1a8d29ac 100644 --- a/include/asm-sparc/processor.h +++ b/include/asm-sparc/processor.h @@ -19,7 +19,6 @@ #include <asm/ptrace.h> #include <asm/head.h> #include <asm/signal.h> -#include <asm/segment.h> #include <asm/btfixup.h> #include <asm/page.h> diff --git a/include/asm-sparc/segment.h b/include/asm-sparc/segment.h deleted file mode 100644 index a1b7ffc9eec9..000000000000 --- a/include/asm-sparc/segment.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __SPARC_SEGMENT_H -#define __SPARC_SEGMENT_H - -/* Only here because we have some old header files that expect it.. */ - -#endif diff --git a/include/asm-sparc/socket.h b/include/asm-sparc/socket.h index c1154e3ecfdf..09575b608adb 100644 --- a/include/asm-sparc/socket.h +++ b/include/asm-sparc/socket.h @@ -29,6 +29,8 @@ #define SO_SNDBUF 0x1001 #define SO_RCVBUF 0x1002 +#define SO_SNDBUFFORCE 0x100a +#define SO_RCVBUFFORCE 0x100b #define SO_ERROR 0x1007 #define SO_TYPE 0x1008 diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h index 898562ebe94c..3557781a4bfd 100644 --- a/include/asm-sparc/system.h +++ b/include/asm-sparc/system.h @@ -9,7 +9,6 @@ #include <linux/threads.h> /* NR_CPUS */ #include <linux/thread_info.h> -#include <asm/segment.h> #include <asm/page.h> #include <asm/psr.h> #include <asm/ptrace.h> diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h index 9eabf6e61ccc..42fc6ed98156 100644 --- a/include/asm-sparc/types.h +++ b/include/asm-sparc/types.h @@ -54,8 +54,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; typedef u32 dma64_addr_t; -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h index aee17d7e2e44..58dba518239e 100644 --- a/include/asm-sparc/unistd.h +++ b/include/asm-sparc/unistd.h @@ -167,12 +167,12 @@ #define __NR_pciconfig_read 148 /* ENOSYS under SunOS */ #define __NR_pciconfig_write 149 /* ENOSYS under SunOS */ #define __NR_getsockname 150 /* Common */ -/* #define __NR_getmsg 151 SunOS Specific */ -/* #define __NR_putmsg 152 SunOS Specific */ +#define __NR_inotify_init 151 /* Linux specific */ +#define __NR_inotify_add_watch 152 /* Linux specific */ #define __NR_poll 153 /* Common */ #define __NR_getdents64 154 /* Linux specific */ #define __NR_fcntl64 155 /* Linux sparc32 Specific */ -/* #define __NR_getdirentires 156 SunOS Specific */ +#define __NR_inotify_rm_watch 156 /* Linux specific */ #define __NR_statfs 157 /* Common */ #define __NR_fstatfs 158 /* Common */ #define __NR_umount 159 /* Common */ diff --git a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h index d80f3379669b..e175afcf2cde 100644 --- a/include/asm-sparc64/atomic.h +++ b/include/asm-sparc64/atomic.h @@ -72,10 +72,10 @@ extern int atomic64_sub_ret(int, atomic64_t *); /* Atomic operations are already serializing */ #ifdef CONFIG_SMP -#define smp_mb__before_atomic_dec() membar("#StoreLoad | #LoadLoad") -#define smp_mb__after_atomic_dec() membar("#StoreLoad | #StoreStore") -#define smp_mb__before_atomic_inc() membar("#StoreLoad | #LoadLoad") -#define smp_mb__after_atomic_inc() membar("#StoreLoad | #StoreStore") +#define smp_mb__before_atomic_dec() membar_storeload_loadload(); +#define smp_mb__after_atomic_dec() membar_storeload_storestore(); +#define smp_mb__before_atomic_inc() membar_storeload_loadload(); +#define smp_mb__after_atomic_inc() membar_storeload_storestore(); #else #define smp_mb__before_atomic_dec() barrier() #define smp_mb__after_atomic_dec() barrier() diff --git a/include/asm-sparc64/bitops.h b/include/asm-sparc64/bitops.h index 9d722dc8cca3..6388b8376c50 100644 --- a/include/asm-sparc64/bitops.h +++ b/include/asm-sparc64/bitops.h @@ -20,72 +20,72 @@ extern void change_bit(unsigned long nr, volatile unsigned long *addr); /* "non-atomic" versions... */ -static __inline__ void __set_bit(int nr, volatile unsigned long *addr) +static inline void __set_bit(int nr, volatile unsigned long *addr) { - volatile unsigned long *m = addr + (nr >> 6); + unsigned long *m = ((unsigned long *)addr) + (nr >> 6); *m |= (1UL << (nr & 63)); } -static __inline__ void __clear_bit(int nr, volatile unsigned long *addr) +static inline void __clear_bit(int nr, volatile unsigned long *addr) { - volatile unsigned long *m = addr + (nr >> 6); + unsigned long *m = ((unsigned long *)addr) + (nr >> 6); *m &= ~(1UL << (nr & 63)); } -static __inline__ void __change_bit(int nr, volatile unsigned long *addr) +static inline void __change_bit(int nr, volatile unsigned long *addr) { - volatile unsigned long *m = addr + (nr >> 6); + unsigned long *m = ((unsigned long *)addr) + (nr >> 6); *m ^= (1UL << (nr & 63)); } -static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr) +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) { - volatile unsigned long *m = addr + (nr >> 6); - long old = *m; - long mask = (1UL << (nr & 63)); + unsigned long *m = ((unsigned long *)addr) + (nr >> 6); + unsigned long old = *m; + unsigned long mask = (1UL << (nr & 63)); *m = (old | mask); return ((old & mask) != 0); } -static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr) +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) { - volatile unsigned long *m = addr + (nr >> 6); - long old = *m; - long mask = (1UL << (nr & 63)); + unsigned long *m = ((unsigned long *)addr) + (nr >> 6); + unsigned long old = *m; + unsigned long mask = (1UL << (nr & 63)); *m = (old & ~mask); return ((old & mask) != 0); } -static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr) +static inline int __test_and_change_bit(int nr, volatile unsigned long *addr) { - volatile unsigned long *m = addr + (nr >> 6); - long old = *m; - long mask = (1UL << (nr & 63)); + unsigned long *m = ((unsigned long *)addr) + (nr >> 6); + unsigned long old = *m; + unsigned long mask = (1UL << (nr & 63)); *m = (old ^ mask); return ((old & mask) != 0); } #ifdef CONFIG_SMP -#define smp_mb__before_clear_bit() membar("#StoreLoad | #LoadLoad") -#define smp_mb__after_clear_bit() membar("#StoreLoad | #StoreStore") +#define smp_mb__before_clear_bit() membar_storeload_loadload() +#define smp_mb__after_clear_bit() membar_storeload_storestore() #else #define smp_mb__before_clear_bit() barrier() #define smp_mb__after_clear_bit() barrier() #endif -static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr) +static inline int test_bit(int nr, __const__ volatile unsigned long *addr) { - return (1UL & ((addr)[nr >> 6] >> (nr & 63))) != 0UL; + return (1UL & (addr[nr >> 6] >> (nr & 63))) != 0UL; } /* The easy/cheese version for now. */ -static __inline__ unsigned long ffz(unsigned long word) +static inline unsigned long ffz(unsigned long word) { unsigned long result; @@ -103,7 +103,7 @@ static __inline__ unsigned long ffz(unsigned long word) * * Undefined if no bit exists, so code should check against 0 first. */ -static __inline__ unsigned long __ffs(unsigned long word) +static inline unsigned long __ffs(unsigned long word) { unsigned long result = 0; @@ -144,7 +144,7 @@ static inline int sched_find_first_bit(unsigned long *b) * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ -static __inline__ int ffs(int x) +static inline int ffs(int x) { if (!x) return 0; @@ -158,7 +158,7 @@ static __inline__ int ffs(int x) #ifdef ULTRA_HAS_POPULATION_COUNT -static __inline__ unsigned int hweight64(unsigned long w) +static inline unsigned int hweight64(unsigned long w) { unsigned int res; @@ -166,7 +166,7 @@ static __inline__ unsigned int hweight64(unsigned long w) return res; } -static __inline__ unsigned int hweight32(unsigned int w) +static inline unsigned int hweight32(unsigned int w) { unsigned int res; @@ -174,7 +174,7 @@ static __inline__ unsigned int hweight32(unsigned int w) return res; } -static __inline__ unsigned int hweight16(unsigned int w) +static inline unsigned int hweight16(unsigned int w) { unsigned int res; @@ -182,7 +182,7 @@ static __inline__ unsigned int hweight16(unsigned int w) return res; } -static __inline__ unsigned int hweight8(unsigned int w) +static inline unsigned int hweight8(unsigned int w) { unsigned int res; @@ -236,7 +236,7 @@ extern unsigned long find_next_zero_bit(const unsigned long *, #define test_and_clear_le_bit(nr,addr) \ test_and_clear_bit((nr) ^ 0x38, (addr)) -static __inline__ int test_le_bit(int nr, __const__ unsigned long * addr) +static inline int test_le_bit(int nr, __const__ unsigned long * addr) { int mask; __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h index cc7198aaac50..9a3a81f1cc58 100644 --- a/include/asm-sparc64/cpudata.h +++ b/include/asm-sparc64/cpudata.h @@ -1,6 +1,6 @@ /* cpudata.h: Per-cpu parameters. * - * Copyright (C) 2003 David S. Miller (davem@redhat.com) + * Copyright (C) 2003, 2005 David S. Miller (davem@redhat.com) */ #ifndef _SPARC64_CPUDATA_H @@ -10,7 +10,7 @@ typedef struct { /* Dcache line 1 */ - unsigned int __pad0; /* bh_count moved to irq_stat for consistency. KAO */ + unsigned int __softirq_pending; /* must be 1st, see rtrap.S */ unsigned int multiplier; unsigned int counter; unsigned int idle_volume; diff --git a/include/asm-sparc64/emergency-restart.h b/include/asm-sparc64/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-sparc64/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-sparc64/hardirq.h b/include/asm-sparc64/hardirq.h index d6db1aed7645..f0cf71376ec5 100644 --- a/include/asm-sparc64/hardirq.h +++ b/include/asm-sparc64/hardirq.h @@ -1,22 +1,16 @@ /* hardirq.h: 64-bit Sparc hard IRQ support. * - * Copyright (C) 1997, 1998 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1997, 1998, 2005 David S. Miller (davem@davemloft.net) */ #ifndef __SPARC64_HARDIRQ_H #define __SPARC64_HARDIRQ_H -#include <linux/config.h> -#include <linux/threads.h> -#include <linux/spinlock.h> -#include <linux/cache.h> +#include <asm/cpudata.h> -/* rtrap.S is sensitive to the offsets of these fields */ -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ +#define __ARCH_IRQ_STAT +#define local_softirq_pending() \ + (local_cpu_data().__softirq_pending) #define HARDIRQ_BITS 8 diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h index afdcea90707a..0056770e83ad 100644 --- a/include/asm-sparc64/io.h +++ b/include/asm-sparc64/io.h @@ -100,18 +100,41 @@ static __inline__ void _outl(u32 l, unsigned long addr) #define inl_p(__addr) inl(__addr) #define outl_p(__l, __addr) outl(__l, __addr) -extern void outsb(void __iomem *addr, const void *src, unsigned long count); -extern void outsw(void __iomem *addr, const void *src, unsigned long count); -extern void outsl(void __iomem *addr, const void *src, unsigned long count); -extern void insb(void __iomem *addr, void *dst, unsigned long count); -extern void insw(void __iomem *addr, void *dst, unsigned long count); -extern void insl(void __iomem *addr, void *dst, unsigned long count); -#define ioread8_rep(a,d,c) insb(a,d,c) -#define ioread16_rep(a,d,c) insw(a,d,c) -#define ioread32_rep(a,d,c) insl(a,d,c) -#define iowrite8_rep(a,s,c) outsb(a,s,c) -#define iowrite16_rep(a,s,c) outsw(a,s,c) -#define iowrite32_rep(a,s,c) outsl(a,s,c) +extern void outsb(unsigned long, const void *, unsigned long); +extern void outsw(unsigned long, const void *, unsigned long); +extern void outsl(unsigned long, const void *, unsigned long); +extern void insb(unsigned long, void *, unsigned long); +extern void insw(unsigned long, void *, unsigned long); +extern void insl(unsigned long, void *, unsigned long); + +static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count) +{ + insb((unsigned long __force)port, buf, count); +} +static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count) +{ + insw((unsigned long __force)port, buf, count); +} + +static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count) +{ + insl((unsigned long __force)port, buf, count); +} + +static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count) +{ + outsb((unsigned long __force)port, buf, count); +} + +static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count) +{ + outsw((unsigned long __force)port, buf, count); +} + +static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count) +{ + outsl((unsigned long __force)port, buf, count); +} /* Memory functions, same as I/O accesses on Ultra. */ static inline u8 _readb(const volatile void __iomem *addr) diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h index b87dbbd64bc9..c9f8ef208ea5 100644 --- a/include/asm-sparc64/page.h +++ b/include/asm-sparc64/page.h @@ -150,20 +150,6 @@ struct sparc_phys_banks { extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS]; -/* Pure 2^n version of get_order */ -static __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #endif /* !(__ASSEMBLY__) */ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ @@ -171,4 +157,6 @@ static __inline__ int get_order(unsigned long size) #endif /* !(__KERNEL__) */ +#include <asm-generic/page.h> + #endif /* !(_SPARC64_PAGE_H) */ diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h index 84e41c1ef3f8..a4ab0ec7143a 100644 --- a/include/asm-sparc64/pci.h +++ b/include/asm-sparc64/pci.h @@ -23,7 +23,7 @@ static inline void pcibios_set_master(struct pci_dev *dev) /* No special bus mastering setup handling */ } -static inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index 1ae00c5087f1..a2b4f5ed4625 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -410,9 +410,6 @@ extern unsigned long *sparc64_valid_addr_bitmap; #define kern_addr_valid(addr) \ (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap)) -extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from, - unsigned long offset, - unsigned long size, pgprot_t prot, int space); extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index d0bee2413560..3169f3e2237e 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -18,7 +18,6 @@ #include <asm/a.out.h> #include <asm/pstate.h> #include <asm/ptrace.h> -#include <asm/segment.h> #include <asm/page.h> /* The sparc has no problems with write protection */ diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h index 2d2b5a113d24..6194f771e9fc 100644 --- a/include/asm-sparc64/ptrace.h +++ b/include/asm-sparc64/ptrace.h @@ -94,8 +94,9 @@ struct sparc_trapf { #define STACKFRAME32_SZ sizeof(struct sparc_stackf32) #ifdef __KERNEL__ -#define force_successful_syscall_return() \ - set_thread_flag(TIF_SYSCALL_SUCCESS) +#define force_successful_syscall_return() \ +do { current_thread_info()->syscall_noerror = 1; \ +} while (0) #define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV)) #define instruction_pointer(regs) ((regs)->tpc) #ifdef CONFIG_SMP diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h index a1cc94f95984..4568ee4022df 100644 --- a/include/asm-sparc64/rwsem.h +++ b/include/asm-sparc64/rwsem.h @@ -46,54 +46,14 @@ extern void __up_read(struct rw_semaphore *sem); extern void __up_write(struct rw_semaphore *sem); extern void __downgrade_write(struct rw_semaphore *sem); -static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem) +static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem) { - int tmp = delta; - - __asm__ __volatile__( - "1:\tlduw [%2], %%g1\n\t" - "add %%g1, %1, %%g7\n\t" - "cas [%2], %%g1, %%g7\n\t" - "cmp %%g1, %%g7\n\t" - "membar #StoreLoad | #StoreStore\n\t" - "bne,pn %%icc, 1b\n\t" - " nop\n\t" - "mov %%g7, %0\n\t" - : "=&r" (tmp) - : "0" (tmp), "r" (sem) - : "g1", "g7", "memory", "cc"); - - return tmp + delta; -} - -#define rwsem_atomic_add rwsem_atomic_update - -static __inline__ __u16 rwsem_cmpxchgw(struct rw_semaphore *sem, __u16 __old, __u16 __new) -{ - u32 old = (sem->count & 0xffff0000) | (u32) __old; - u32 new = (old & 0xffff0000) | (u32) __new; - u32 prev; - -again: - __asm__ __volatile__("cas [%2], %3, %0\n\t" - "membar #StoreLoad | #StoreStore" - : "=&r" (prev) - : "0" (new), "r" (sem), "r" (old) - : "memory"); - - /* To give the same semantics as x86 cmpxchgw, keep trying - * if only the upper 16-bits changed. - */ - if (prev != old && - ((prev & 0xffff) == (old & 0xffff))) - goto again; - - return prev & 0xffff; + return atomic_add_return(delta, (atomic_t *)(&sem->count)); } -static __inline__ signed long rwsem_cmpxchg(struct rw_semaphore *sem, signed long old, signed long new) +static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem) { - return cmpxchg(&sem->count,old,new); + atomic_add(delta, (atomic_t *)(&sem->count)); } #endif /* __KERNEL__ */ diff --git a/include/asm-sparc64/segment.h b/include/asm-sparc64/segment.h deleted file mode 100644 index b03e709fc945..000000000000 --- a/include/asm-sparc64/segment.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __SPARC64_SEGMENT_H -#define __SPARC64_SEGMENT_H - -/* Only here because we have some old header files that expect it.. */ - -#endif diff --git a/include/asm-sparc64/sfafsr.h b/include/asm-sparc64/sfafsr.h new file mode 100644 index 000000000000..2f792c20b53c --- /dev/null +++ b/include/asm-sparc64/sfafsr.h @@ -0,0 +1,82 @@ +#ifndef _SPARC64_SFAFSR_H +#define _SPARC64_SFAFSR_H + +#include <asm/const.h> + +/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ + +#define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT) +#define SFAFSR_ME_SHIFT 32 +#define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT) +#define SFAFSR_PRIV_SHIFT 31 +#define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT) +#define SFAFSR_ISAP_SHIFT 30 +#define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT) +#define SFAFSR_ETP_SHIFT 29 +#define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT) +#define SFAFSR_IVUE_SHIFT 28 +#define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT) +#define SFAFSR_TO_SHIFT 27 +#define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT) +#define SFAFSR_BERR_SHIFT 26 +#define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT) +#define SFAFSR_LDP_SHIFT 25 +#define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT) +#define SFAFSR_CP_SHIFT 24 +#define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT) +#define SFAFSR_WP_SHIFT 23 +#define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT) +#define SFAFSR_EDP_SHIFT 22 +#define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT) +#define SFAFSR_UE_SHIFT 21 +#define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT) +#define SFAFSR_CE_SHIFT 20 +#define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT) +#define SFAFSR_ETS_SHIFT 16 +#define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT) +#define SFAFSR_PSYND_SHIFT 0 + +/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read + * ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write + */ + +#define UDBE_UE (_AC(1,UL) << 9) +#define UDBE_CE (_AC(1,UL) << 8) +#define UDBE_E_SYNDR (_AC(0xff,UL) << 0) + +/* The trap handlers for asynchronous errors encode the AFSR and + * other pieces of information into a 64-bit argument for C code + * encoded as follows: + * + * ----------------------------------------------- + * | UDB_H | UDB_L | TL>1 | TT | AFSR | + * ----------------------------------------------- + * 63 54 53 44 42 41 33 32 0 + * + * The AFAR is passed in unchanged. + */ +#define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT) +#define SFSTAT_UDBH_SHIFT 54 +#define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT) +#define SFSTAT_UDBL_SHIFT 44 +#define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT) +#define SFSTAT_TL_GT_ONE_SHIFT 42 +#define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT) +#define SFSTAT_TRAP_TYPE_SHIFT 33 +#define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT) +#define SFSTAT_AFSR_SHIFT 0 + +/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */ +#define ESTATE_ERR_CE 0x1 /* Correctable errors */ +#define ESTATE_ERR_NCE 0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */ +#define ESTATE_ERR_ISAP 0x4 /* System address parity error */ +#define ESTATE_ERR_ALL (ESTATE_ERR_CE | \ + ESTATE_ERR_NCE | \ + ESTATE_ERR_ISAP) + +/* The various trap types that report using the above state. */ +#define TRAP_TYPE_IAE 0x09 /* Instruction Access Error */ +#define TRAP_TYPE_DAE 0x32 /* Data Access Error */ +#define TRAP_TYPE_CEE 0x63 /* Correctable ECC Error */ + +#endif /* _SPARC64_SFAFSR_H */ diff --git a/include/asm-sparc64/socket.h b/include/asm-sparc64/socket.h index 865547a23908..59987dad3359 100644 --- a/include/asm-sparc64/socket.h +++ b/include/asm-sparc64/socket.h @@ -29,6 +29,8 @@ #define SO_SNDBUF 0x1001 #define SO_RCVBUF 0x1002 +#define SO_SNDBUFFORCE 0x100a +#define SO_RCVBUFFORCE 0x100b #define SO_ERROR 0x1007 #define SO_TYPE 0x1008 diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h index 9cb93a5c2b4f..a02c4370eb42 100644 --- a/include/asm-sparc64/spinlock.h +++ b/include/asm-sparc64/spinlock.h @@ -43,7 +43,7 @@ typedef struct { #define spin_is_locked(lp) ((lp)->lock != 0) #define spin_unlock_wait(lp) \ -do { membar("#LoadLoad"); \ +do { rmb(); \ } while((lp)->lock) static inline void _raw_spin_lock(spinlock_t *lock) @@ -129,15 +129,18 @@ typedef struct { #define spin_is_locked(__lock) ((__lock)->lock != 0) #define spin_unlock_wait(__lock) \ do { \ - membar("#LoadLoad"); \ + rmb(); \ } while((__lock)->lock) -extern void _do_spin_lock (spinlock_t *lock, char *str); -extern void _do_spin_unlock (spinlock_t *lock); -extern int _do_spin_trylock (spinlock_t *lock); +extern void _do_spin_lock(spinlock_t *lock, char *str, unsigned long caller); +extern void _do_spin_unlock(spinlock_t *lock); +extern int _do_spin_trylock(spinlock_t *lock, unsigned long caller); -#define _raw_spin_trylock(lp) _do_spin_trylock(lp) -#define _raw_spin_lock(lock) _do_spin_lock(lock, "spin_lock") +#define _raw_spin_trylock(lp) \ + _do_spin_trylock(lp, (unsigned long) __builtin_return_address(0)) +#define _raw_spin_lock(lock) \ + _do_spin_lock(lock, "spin_lock", \ + (unsigned long) __builtin_return_address(0)) #define _raw_spin_unlock(lock) _do_spin_unlock(lock) #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) @@ -279,37 +282,41 @@ typedef struct { #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0, 0xff, { } } #define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0) -extern void _do_read_lock(rwlock_t *rw, char *str); -extern void _do_read_unlock(rwlock_t *rw, char *str); -extern void _do_write_lock(rwlock_t *rw, char *str); -extern void _do_write_unlock(rwlock_t *rw); -extern int _do_write_trylock(rwlock_t *rw, char *str); +extern void _do_read_lock(rwlock_t *rw, char *str, unsigned long caller); +extern void _do_read_unlock(rwlock_t *rw, char *str, unsigned long caller); +extern void _do_write_lock(rwlock_t *rw, char *str, unsigned long caller); +extern void _do_write_unlock(rwlock_t *rw, unsigned long caller); +extern int _do_write_trylock(rwlock_t *rw, char *str, unsigned long caller); #define _raw_read_lock(lock) \ do { unsigned long flags; \ local_irq_save(flags); \ - _do_read_lock(lock, "read_lock"); \ + _do_read_lock(lock, "read_lock", \ + (unsigned long) __builtin_return_address(0)); \ local_irq_restore(flags); \ } while(0) #define _raw_read_unlock(lock) \ do { unsigned long flags; \ local_irq_save(flags); \ - _do_read_unlock(lock, "read_unlock"); \ + _do_read_unlock(lock, "read_unlock", \ + (unsigned long) __builtin_return_address(0)); \ local_irq_restore(flags); \ } while(0) #define _raw_write_lock(lock) \ do { unsigned long flags; \ local_irq_save(flags); \ - _do_write_lock(lock, "write_lock"); \ + _do_write_lock(lock, "write_lock", \ + (unsigned long) __builtin_return_address(0)); \ local_irq_restore(flags); \ } while(0) #define _raw_write_unlock(lock) \ do { unsigned long flags; \ local_irq_save(flags); \ - _do_write_unlock(lock); \ + _do_write_unlock(lock, \ + (unsigned long) __builtin_return_address(0)); \ local_irq_restore(flags); \ } while(0) @@ -317,7 +324,8 @@ do { unsigned long flags; \ ({ unsigned long flags; \ int val; \ local_irq_save(flags); \ - val = _do_write_trylock(lock, "write_trylock"); \ + val = _do_write_trylock(lock, "write_trylock", \ + (unsigned long) __builtin_return_address(0)); \ local_irq_restore(flags); \ val; \ }) diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h index 1aa932773af8..962638c9d122 100644 --- a/include/asm-sparc64/spitfire.h +++ b/include/asm-sparc64/spitfire.h @@ -56,52 +56,6 @@ extern void cheetah_enable_pcache(void); SPITFIRE_HIGHEST_LOCKED_TLBENT : \ CHEETAH_HIGHEST_LOCKED_TLBENT) -static __inline__ unsigned long spitfire_get_isfsr(void) -{ - unsigned long ret; - - __asm__ __volatile__("ldxa [%1] %2, %0" - : "=r" (ret) - : "r" (TLB_SFSR), "i" (ASI_IMMU)); - return ret; -} - -static __inline__ unsigned long spitfire_get_dsfsr(void) -{ - unsigned long ret; - - __asm__ __volatile__("ldxa [%1] %2, %0" - : "=r" (ret) - : "r" (TLB_SFSR), "i" (ASI_DMMU)); - return ret; -} - -static __inline__ unsigned long spitfire_get_sfar(void) -{ - unsigned long ret; - - __asm__ __volatile__("ldxa [%1] %2, %0" - : "=r" (ret) - : "r" (DMMU_SFAR), "i" (ASI_DMMU)); - return ret; -} - -static __inline__ void spitfire_put_isfsr(unsigned long sfsr) -{ - __asm__ __volatile__("stxa %0, [%1] %2\n\t" - "membar #Sync" - : /* no outputs */ - : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU)); -} - -static __inline__ void spitfire_put_dsfsr(unsigned long sfsr) -{ - __asm__ __volatile__("stxa %0, [%1] %2\n\t" - "membar #Sync" - : /* no outputs */ - : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU)); -} - /* The data cache is write through, so this just invalidates the * specified line. */ @@ -193,90 +147,6 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) "i" (ASI_ITLB_DATA_ACCESS)); } -/* Spitfire hardware assisted TLB flushes. */ - -/* Context level flushes. */ -static __inline__ void spitfire_flush_dtlb_primary_context(void) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (0x40), "i" (ASI_DMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_itlb_primary_context(void) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (0x40), "i" (ASI_IMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_dtlb_secondary_context(void) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (0x50), "i" (ASI_DMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_itlb_secondary_context(void) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (0x50), "i" (ASI_IMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_dtlb_nucleus_context(void) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (0x60), "i" (ASI_DMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_itlb_nucleus_context(void) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (0x60), "i" (ASI_IMMU_DEMAP)); -} - -/* Page level flushes. */ -static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (page), "i" (ASI_DMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (page), "i" (ASI_IMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP)); -} - -static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) -{ - __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP)); -} - static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h index f9be2c5b4dc9..5e94c05dc2fc 100644 --- a/include/asm-sparc64/system.h +++ b/include/asm-sparc64/system.h @@ -28,6 +28,14 @@ enum sparc_cpu { #define ARCH_SUN4C_SUN4 0 #define ARCH_SUN4 0 +extern void mb(void); +extern void rmb(void); +extern void wmb(void); +extern void membar_storeload(void); +extern void membar_storeload_storestore(void); +extern void membar_storeload_loadload(void); +extern void membar_storestore_loadstore(void); + #endif #define setipl(__new_ipl) \ @@ -78,16 +86,11 @@ enum sparc_cpu { #define nop() __asm__ __volatile__ ("nop") -#define membar(type) __asm__ __volatile__ ("membar " type : : : "memory") -#define mb() \ - membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad") -#define rmb() membar("#LoadLoad") -#define wmb() membar("#StoreStore") #define read_barrier_depends() do { } while(0) #define set_mb(__var, __value) \ - do { __var = __value; membar("#StoreLoad | #StoreStore"); } while(0) + do { __var = __value; membar_storeload_storestore(); } while(0) #define set_wmb(__var, __value) \ - do { __var = __value; membar("#StoreStore"); } while(0) + do { __var = __value; wmb(); } while(0) #ifdef CONFIG_SMP #define smp_mb() mb() @@ -190,24 +193,23 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ "wrpr %%g1, %%cwp\n\t" \ "ldx [%%g6 + %3], %%o6\n\t" \ "ldub [%%g6 + %2], %%o5\n\t" \ - "ldx [%%g6 + %4], %%o7\n\t" \ + "ldub [%%g6 + %4], %%o7\n\t" \ "mov %%g6, %%l2\n\t" \ "wrpr %%o5, 0x0, %%wstate\n\t" \ "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \ "wrpr %%g0, 0x94, %%pstate\n\t" \ "mov %%l2, %%g6\n\t" \ - "ldx [%%g6 + %7], %%g4\n\t" \ + "ldx [%%g6 + %6], %%g4\n\t" \ "wrpr %%g0, 0x96, %%pstate\n\t" \ - "andcc %%o7, %6, %%g0\n\t" \ - "beq,pt %%icc, 1f\n\t" \ + "brz,pt %%o7, 1f\n\t" \ " mov %%g7, %0\n\t" \ "b,a ret_from_syscall\n\t" \ "1:\n\t" \ : "=&r" (last) \ : "0" (next->thread_info), \ - "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_FLAGS), "i" (TI_CWP), \ - "i" (_TIF_NEWCHILD), "i" (TI_TASK) \ + "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \ + "i" (TI_CWP), "i" (TI_TASK) \ : "cc", \ "g1", "g2", "g3", "g7", \ "l2", "l3", "l4", "l5", "l6", "l7", \ diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h index a1d25c06f92a..c94d8b3991bd 100644 --- a/include/asm-sparc64/thread_info.h +++ b/include/asm-sparc64/thread_info.h @@ -47,7 +47,9 @@ struct thread_info { struct pt_regs *kregs; struct exec_domain *exec_domain; int preempt_count; /* 0 => preemptable, <0 => BUG */ - int __pad; + __u8 new_child; + __u8 syscall_noerror; + __u16 __pad; unsigned long *utraps; @@ -66,6 +68,9 @@ struct thread_info { struct restart_block restart_block; + struct pt_regs *kern_una_regs; + unsigned int kern_una_insn; + unsigned long fpregs[0] __attribute__ ((aligned(64))); }; @@ -87,6 +92,8 @@ struct thread_info { #define TI_KREGS 0x00000028 #define TI_EXEC_DOMAIN 0x00000030 #define TI_PRE_COUNT 0x00000038 +#define TI_NEW_CHILD 0x0000003c +#define TI_SYS_NOERROR 0x0000003d #define TI_UTRAPS 0x00000040 #define TI_REG_WINDOW 0x00000048 #define TI_RWIN_SPTRS 0x000003c8 @@ -99,6 +106,8 @@ struct thread_info { #define TI_PCR 0x00000490 #define TI_CEE_STUFF 0x00000498 #define TI_RESTART_BLOCK 0x000004a0 +#define TI_KUNA_REGS 0x000004c8 +#define TI_KUNA_INSN 0x000004d0 #define TI_FPREGS 0x00000500 /* We embed this in the uppermost byte of thread_info->flags */ @@ -219,10 +228,10 @@ register struct thread_info *current_thread_info_reg asm("g6"); #define TIF_UNALIGNED 5 /* allowed to do unaligned accesses */ #define TIF_NEWSIGNALS 6 /* wants new-style signals */ #define TIF_32BIT 7 /* 32-bit binary */ -#define TIF_NEWCHILD 8 /* just-spawned child process */ +/* flag bit 8 is available */ #define TIF_SECCOMP 9 /* secure computing */ #define TIF_SYSCALL_AUDIT 10 /* syscall auditing active */ -#define TIF_SYSCALL_SUCCESS 11 +/* flag bit 11 is available */ /* NOTE: Thread flags >= 12 should be ones we have no interest * in using in assembly, else we can't use the mask as * an immediate value in instructions such as andcc. @@ -239,10 +248,8 @@ register struct thread_info *current_thread_info_reg asm("g6"); #define _TIF_UNALIGNED (1<<TIF_UNALIGNED) #define _TIF_NEWSIGNALS (1<<TIF_NEWSIGNALS) #define _TIF_32BIT (1<<TIF_32BIT) -#define _TIF_NEWCHILD (1<<TIF_NEWCHILD) #define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) -#define _TIF_SYSCALL_SUCCESS (1<<TIF_SYSCALL_SUCCESS) #define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) diff --git a/include/asm-sparc64/timer.h b/include/asm-sparc64/timer.h index ba33a2b6b7bd..edc8e08c3a39 100644 --- a/include/asm-sparc64/timer.h +++ b/include/asm-sparc64/timer.h @@ -9,49 +9,8 @@ #include <linux/types.h> -/* How timers work: - * - * On uniprocessors we just use counter zero for the system wide - * ticker, this performs thread scheduling, clock book keeping, - * and runs timer based events. Previously we used the Ultra - * %tick interrupt for this purpose. - * - * On multiprocessors we pick one cpu as the master level 10 tick - * processor. Here this counter zero tick handles clock book - * keeping and timer events only. Each Ultra has it's level - * 14 %tick interrupt set to fire off as well, even the master - * tick cpu runs this locally. This ticker performs thread - * scheduling, system/user tick counting for the current thread, - * and also profiling if enabled. - */ - #include <linux/config.h> -/* Two timers, traditionally steered to PIL's 10 and 14 respectively. - * But since INO packets are used on sun5, we could use any PIL level - * we like, however for now we use the normal ones. - * - * The 'reg' and 'interrupts' properties for these live in nodes named - * 'counter-timer'. The first of three 'reg' properties describe where - * the sun5_timer registers are. The other two I have no idea. (XXX) - */ -struct sun5_timer { - u64 count0; - u64 limit0; - u64 count1; - u64 limit1; -}; - -#define SUN5_LIMIT_ENABLE 0x80000000 -#define SUN5_LIMIT_TOZERO 0x40000000 -#define SUN5_LIMIT_ZRESTART 0x20000000 -#define SUN5_LIMIT_CMASK 0x1fffffff - -/* Given a HZ value, set the limit register to so that the timer IRQ - * gets delivered that often. - */ -#define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz)) - struct sparc64_tick_ops { void (*init_tick)(unsigned long); unsigned long (*get_tick)(void); diff --git a/include/asm-sparc64/types.h b/include/asm-sparc64/types.h index 6248ed1a9a7a..d0ee7f105838 100644 --- a/include/asm-sparc64/types.h +++ b/include/asm-sparc64/types.h @@ -56,8 +56,6 @@ typedef unsigned long u64; typedef u32 dma_addr_t; typedef u64 dma64_addr_t; -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h index f59144c6b76a..51ec2879b881 100644 --- a/include/asm-sparc64/unistd.h +++ b/include/asm-sparc64/unistd.h @@ -167,12 +167,12 @@ #define __NR_pciconfig_read 148 /* ENOSYS under SunOS */ #define __NR_pciconfig_write 149 /* ENOSYS under SunOS */ #define __NR_getsockname 150 /* Common */ -/* #define __NR_getmsg 151 SunOS Specific */ -/* #define __NR_putmsg 152 SunOS Specific */ +#define __NR_inotify_init 151 /* Linux specific */ +#define __NR_inotify_add_watch 152 /* Linux specific */ #define __NR_poll 153 /* Common */ #define __NR_getdents64 154 /* Linux specific */ /* #define __NR_fcntl64 155 Linux sparc32 Specific */ -/* #define __NR_getdirentries 156 SunOS Specific */ +#define __NR_inotify_rm_watch 156 /* Linux specific */ #define __NR_statfs 157 /* Common */ #define __NR_fstatfs 158 /* Common */ #define __NR_umount 159 /* Common */ diff --git a/include/asm-um/emergency-restart.h b/include/asm-um/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-um/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-um/ldt.h b/include/asm-um/ldt.h new file mode 100644 index 000000000000..e908439d338a --- /dev/null +++ b/include/asm-um/ldt.h @@ -0,0 +1,5 @@ +#ifndef __UM_LDT_H +#define __UM_LDT_H + +#include "asm/arch/ldt.h" +#endif diff --git a/include/asm-um/mmu_context.h b/include/asm-um/mmu_context.h index 7529c9c853dd..2edb4f1f789c 100644 --- a/include/asm-um/mmu_context.h +++ b/include/asm-um/mmu_context.h @@ -16,8 +16,20 @@ #define deactivate_mm(tsk,mm) do { } while (0) +extern void force_flush_all(void); + static inline void activate_mm(struct mm_struct *old, struct mm_struct *new) { + /* + * This is called by fs/exec.c and fs/aio.c. In the first case, for an + * exec, we don't need to do anything as we're called from userspace + * and thus going to use a new host PID. In the second, we're called + * from a kernel thread, and thus need to go doing the mmap's on the + * host. Since they're very expensive, we want to avoid that as far as + * possible. + */ + if (old != new && (current->flags & PF_BORROWED_MM)) + force_flush_all(); } static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, diff --git a/include/asm-um/page.h b/include/asm-um/page.h index 5afee8a8cdf3..bd850a249183 100644 --- a/include/asm-um/page.h +++ b/include/asm-um/page.h @@ -104,8 +104,8 @@ extern void *to_virt(unsigned long phys); * casting is the right thing, but 32-bit UML can't have 64-bit virtual * addresses */ -#define __pa(virt) to_phys((void *) (unsigned long) virt) -#define __va(phys) to_virt((unsigned long) phys) +#define __pa(virt) to_phys((void *) (unsigned long) (virt)) +#define __va(phys) to_virt((unsigned long) (phys)) #define page_to_pfn(page) ((page) - mem_map) #define pfn_to_page(pfn) (mem_map + (pfn)) @@ -116,24 +116,12 @@ extern void *to_virt(unsigned long phys); #define pfn_valid(pfn) ((pfn) < max_mapnr) #define virt_addr_valid(v) pfn_valid(phys_to_pfn(__pa(v))) -/* Pure 2^n version of get_order */ -static __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - extern struct page *arch_validate(struct page *page, int mask, int order); #define HAVE_ARCH_VALIDATE extern void arch_free_page(struct page *page, int order); #define HAVE_ARCH_FREE_PAGE +#include <asm-generic/page.h> + #endif diff --git a/include/asm-um/pgalloc.h b/include/asm-um/pgalloc.h index 8fcb2fc0a892..ea49411236dc 100644 --- a/include/asm-um/pgalloc.h +++ b/include/asm-um/pgalloc.h @@ -42,11 +42,13 @@ static inline void pte_free(struct page *pte) #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) #ifdef CONFIG_3_LEVEL_PGTABLES -/* - * In the 3-level case we free the pmds as part of the pgd. - */ -#define pmd_free(x) do { } while (0) -#define __pmd_free_tlb(tlb,x) do { } while (0) + +extern __inline__ void pmd_free(pmd_t *pmd) +{ + free_page((unsigned long)pmd); +} + +#define __pmd_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x)) #endif #define check_pgt_cache() do { } while (0) diff --git a/include/asm-um/pgtable-2level.h b/include/asm-um/pgtable-2level.h index 9b3abc01d60e..ffe017f6b64b 100644 --- a/include/asm-um/pgtable-2level.h +++ b/include/asm-um/pgtable-2level.h @@ -35,35 +35,8 @@ static inline int pgd_newpage(pgd_t pgd) { return 0; } static inline void pgd_mkuptodate(pgd_t pgd) { } -#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE)) - -static inline pte_t pte_mknewprot(pte_t pte) -{ - pte_val(pte) |= _PAGE_NEWPROT; - return(pte); -} - -static inline pte_t pte_mknewpage(pte_t pte) -{ - pte_val(pte) |= _PAGE_NEWPAGE; - return(pte); -} - -static inline void set_pte(pte_t *pteptr, pte_t pteval) -{ - /* If it's a swap entry, it needs to be marked _PAGE_NEWPAGE so - * fix_range knows to unmap it. _PAGE_NEWPROT is specific to - * mapped pages. - */ - *pteptr = pte_mknewpage(pteval); - if(pte_present(*pteptr)) *pteptr = pte_mknewprot(*pteptr); -} -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) - #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval)) -#define pte_page(x) pfn_to_page(pte_pfn(x)) -#define pte_none(x) !(pte_val(x) & ~_PAGE_NEWPAGE) #define pte_pfn(x) phys_to_pfn(pte_val(x)) #define pfn_pte(pfn, prot) __pte(pfn_to_phys(pfn) | pgprot_val(prot)) #define pfn_pmd(pfn, prot) __pmd(pfn_to_phys(pfn) | pgprot_val(prot)) diff --git a/include/asm-um/pgtable-3level.h b/include/asm-um/pgtable-3level.h index 65e8bfc55fc4..786c25727289 100644 --- a/include/asm-um/pgtable-3level.h +++ b/include/asm-um/pgtable-3level.h @@ -57,35 +57,6 @@ static inline int pgd_newpage(pgd_t pgd) static inline void pgd_mkuptodate(pgd_t pgd) { pgd_val(pgd) &= ~_PAGE_NEWPAGE; } - -#define pte_present(x) pte_get_bits(x, (_PAGE_PRESENT | _PAGE_PROTNONE)) - -static inline pte_t pte_mknewprot(pte_t pte) -{ - pte_set_bits(pte, _PAGE_NEWPROT); - return(pte); -} - -static inline pte_t pte_mknewpage(pte_t pte) -{ - pte_set_bits(pte, _PAGE_NEWPAGE); - return(pte); -} - -static inline void set_pte(pte_t *pteptr, pte_t pteval) -{ - pte_copy(*pteptr, pteval); - - /* If it's a swap entry, it needs to be marked _PAGE_NEWPAGE so - * fix_range knows to unmap it. _PAGE_NEWPROT is specific to - * mapped pages. - */ - - *pteptr = pte_mknewpage(*pteptr); - if(pte_present(*pteptr)) *pteptr = pte_mknewprot(*pteptr); -} -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) - #define set_pmd(pmdptr, pmdval) set_64bit((phys_t *) (pmdptr), pmd_val(pmdval)) static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) @@ -98,14 +69,11 @@ static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) return pmd; } -static inline void pmd_free(pmd_t *pmd){ - free_page((unsigned long) pmd); +extern inline void pud_clear (pud_t *pud) +{ + set_pud(pud, __pud(0)); } -#define __pmd_free_tlb(tlb,x) do { } while (0) - -static inline void pud_clear (pud_t * pud) { } - #define pud_page(pud) \ ((struct page *) __va(pud_val(pud) & PAGE_MASK)) @@ -113,13 +81,6 @@ static inline void pud_clear (pud_t * pud) { } #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \ pmd_index(address)) -#define pte_page(x) pfn_to_page(pte_pfn(x)) - -static inline int pte_none(pte_t pte) -{ - return pte_is_zero(pte); -} - static inline unsigned long pte_pfn(pte_t pte) { return phys_to_pfn(pte_val(pte)); diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h index a88040920311..b48e0966ecd7 100644 --- a/include/asm-um/pgtable.h +++ b/include/asm-um/pgtable.h @@ -16,13 +16,15 @@ #define _PAGE_PRESENT 0x001 #define _PAGE_NEWPAGE 0x002 -#define _PAGE_NEWPROT 0x004 -#define _PAGE_FILE 0x008 /* set:pagecache unset:swap */ -#define _PAGE_PROTNONE 0x010 /* If not present */ +#define _PAGE_NEWPROT 0x004 #define _PAGE_RW 0x020 #define _PAGE_USER 0x040 #define _PAGE_ACCESSED 0x080 #define _PAGE_DIRTY 0x100 +/* If _PAGE_PRESENT is clear, we use these: */ +#define _PAGE_FILE 0x008 /* nonlinear file mapping, saved PTE; unset:swap */ +#define _PAGE_PROTNONE 0x010 /* if the user mapped it with PROT_NONE; + pte_present gives true */ #ifdef CONFIG_3_LEVEL_PGTABLES #include "asm/pgtable-3level.h" @@ -151,10 +153,24 @@ extern unsigned long pg0[1024]; #define pmd_page(pmd) phys_to_page(pmd_val(pmd) & PAGE_MASK) +#define pte_page(x) pfn_to_page(pte_pfn(x)) #define pte_address(x) (__va(pte_val(x) & PAGE_MASK)) #define mk_phys(a, r) ((a) + (((unsigned long) r) << REGION_SHIFT)) #define phys_addr(p) ((p) & ~REGION_MASK) +#define pte_present(x) pte_get_bits(x, (_PAGE_PRESENT | _PAGE_PROTNONE)) + +/* + * ================================= + * Flags checking section. + * ================================= + */ + +static inline int pte_none(pte_t pte) +{ + return pte_is_zero(pte); +} + /* * The following only work if pte_present() is true. * Undefined behaviour if not.. @@ -210,6 +226,18 @@ static inline int pte_newprot(pte_t pte) return(pte_present(pte) && (pte_get_bits(pte, _PAGE_NEWPROT))); } +/* + * ================================= + * Flags setting section. + * ================================= + */ + +static inline pte_t pte_mknewprot(pte_t pte) +{ + pte_set_bits(pte, _PAGE_NEWPROT); + return(pte); +} + static inline pte_t pte_rdprotect(pte_t pte) { pte_clear_bits(pte, _PAGE_USER); @@ -278,6 +306,26 @@ static inline pte_t pte_mkuptodate(pte_t pte) return(pte); } +static inline pte_t pte_mknewpage(pte_t pte) +{ + pte_set_bits(pte, _PAGE_NEWPAGE); + return(pte); +} + +static inline void set_pte(pte_t *pteptr, pte_t pteval) +{ + pte_copy(*pteptr, pteval); + + /* If it's a swap entry, it needs to be marked _PAGE_NEWPAGE so + * fix_range knows to unmap it. _PAGE_NEWPROT is specific to + * mapped pages. + */ + + *pteptr = pte_mknewpage(*pteptr); + if(pte_present(*pteptr)) *pteptr = pte_mknewprot(*pteptr); +} +#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) + extern phys_t page_to_phys(struct page *page); /* diff --git a/include/asm-um/vm86.h b/include/asm-um/vm86.h new file mode 100644 index 000000000000..7801f82de1f4 --- /dev/null +++ b/include/asm-um/vm86.h @@ -0,0 +1,6 @@ +#ifndef __UM_VM86_H +#define __UM_VM86_H + +#include "asm/arch/vm86.h" + +#endif diff --git a/include/asm-v850/bitops.h b/include/asm-v850/bitops.h index 7c4ecaf5151c..0e5c2f210872 100644 --- a/include/asm-v850/bitops.h +++ b/include/asm-v850/bitops.h @@ -1,8 +1,8 @@ /* * include/asm-v850/bitops.h -- Bit operations * - * Copyright (C) 2001,02,03,04 NEC Electronics Corporation - * Copyright (C) 2001,02,03,04 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,02,03,04,05 NEC Electronics Corporation + * Copyright (C) 2001,02,03,04,05 Miles Bader <miles@gnu.org> * Copyright (C) 1992 Linus Torvalds. * * This file is subject to the terms and conditions of the GNU General @@ -157,7 +157,7 @@ extern __inline__ int __test_bit (int nr, const void *addr) #define find_first_zero_bit(addr, size) \ find_next_zero_bit ((addr), (size), 0) -extern __inline__ int find_next_zero_bit (void *addr, int size, int offset) +extern __inline__ int find_next_zero_bit(const void *addr, int size, int offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; diff --git a/include/asm-v850/cache.h b/include/asm-v850/cache.h index 027f8c9090cd..cbf9096e8517 100644 --- a/include/asm-v850/cache.h +++ b/include/asm-v850/cache.h @@ -1,8 +1,8 @@ /* * include/asm-v850/cache.h -- Cache operations * - * Copyright (C) 2001 NEC Corporation - * Copyright (C) 2001 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,05 NEC Corporation + * Copyright (C) 2001,05 Miles Bader <miles@gnu.org> * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -20,6 +20,9 @@ #ifndef L1_CACHE_BYTES /* This processor has no cache, so just choose an arbitrary value. */ #define L1_CACHE_BYTES 16 +#define L1_CACHE_SHIFT 4 #endif +#define L1_CACHE_SHIFT_MAX L1_CACHE_SHIFT + #endif /* __V850_CACHE_H__ */ diff --git a/include/asm-v850/emergency-restart.h b/include/asm-v850/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-v850/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-v850/io.h b/include/asm-v850/io.h index bb5efd1b4b7d..cc364fcbec10 100644 --- a/include/asm-v850/io.h +++ b/include/asm-v850/io.h @@ -1,8 +1,8 @@ /* * include/asm-v850/io.h -- Misc I/O operations * - * Copyright (C) 2001,02,03,04 NEC Electronics Corporation - * Copyright (C) 2001,02,03,04 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,02,03,04,05 NEC Electronics Corporation + * Copyright (C) 2001,02,03,04,05 Miles Bader <miles@gnu.org> * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -27,12 +27,12 @@ #define readw_relaxed(a) readw(a) #define readl_relaxed(a) readl(a) -#define writeb(b, addr) \ - (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) \ - (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) \ - (void)((*(volatile unsigned int *) (addr)) = (b)) +#define writeb(val, addr) \ + (void)((*(volatile unsigned char *) (addr)) = (val)) +#define writew(val, addr) \ + (void)((*(volatile unsigned short *) (addr)) = (val)) +#define writel(val, addr) \ + (void)((*(volatile unsigned int *) (addr)) = (val)) #define __raw_readb readb #define __raw_readw readw @@ -96,11 +96,22 @@ outsl (unsigned long port, const void *src, unsigned long count) outl (*p++, port); } -#define iounmap(addr) ((void)0) -#define ioremap(physaddr, size) (physaddr) -#define ioremap_nocache(physaddr, size) (physaddr) -#define ioremap_writethrough(physaddr, size) (physaddr) -#define ioremap_fullcache(physaddr, size) (physaddr) + +/* Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to + long before casting it to a pointer to avoid compiler warnings. */ +#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr)) +#define iounmap(addr) ((void)0) + +#define ioremap_nocache(physaddr, size) ioremap (physaddr, size) +#define ioremap_writethrough(physaddr, size) ioremap (physaddr, size) +#define ioremap_fullcache(physaddr, size) ioremap (physaddr, size) + +#define ioread8(addr) readb (addr) +#define ioread16(addr) readw (addr) +#define ioread32(addr) readl (addr) +#define iowrite8(val, addr) writeb (val, addr) +#define iowrite16(val, addr) writew (val, addr) +#define iowrite32(val, addr) writel (val, addr) #define mmiowb() diff --git a/include/asm-v850/page.h b/include/asm-v850/page.h index 06085b0c043e..b4bc85e7b91a 100644 --- a/include/asm-v850/page.h +++ b/include/asm-v850/page.h @@ -1,8 +1,8 @@ /* * include/asm-v850/page.h -- VM ops * - * Copyright (C) 2001,02,03 NEC Electronics Corporation - * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,02,03,05 NEC Electronics Corporation + * Copyright (C) 2001,02,03,05 Miles Bader <miles@gnu.org> * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -98,25 +98,6 @@ typedef unsigned long pgprot_t; #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) -#ifndef __ASSEMBLY__ - -/* Pure 2^n version of get_order */ -extern __inline__ int get_order (unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif /* !__ASSEMBLY__ */ - - /* No current v850 processor has virtual memory. */ #define __virt_to_phys(addr) (addr) #define __phys_to_virt(addr) (addr) @@ -132,6 +113,7 @@ extern __inline__ int get_order (unsigned long size) #define pfn_to_page(pfn) virt_to_page (pfn_to_virt (pfn)) #define page_to_pfn(page) virt_to_pfn (page_to_virt (page)) +#define pfn_valid(pfn) ((pfn) < max_mapnr) #define virt_addr_valid(kaddr) \ (((void *)(kaddr) >= (void *)PAGE_OFFSET) && MAP_NR (kaddr) < max_mapnr) @@ -143,4 +125,6 @@ extern __inline__ int get_order (unsigned long size) #endif /* KERNEL */ +#include <asm-generic/page.h> + #endif /* __V850_PAGE_H__ */ diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h index 8e79be0fe99d..4581826e1cac 100644 --- a/include/asm-v850/pci.h +++ b/include/asm-v850/pci.h @@ -1,8 +1,8 @@ /* * include/asm-v850/pci.h -- PCI support * - * Copyright (C) 2001,02 NEC Corporation - * Copyright (C) 2001,02 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,02,05 NEC Corporation + * Copyright (C) 2001,02,05 Miles Bader <miles@gnu.org> * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -48,12 +48,12 @@ pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size, perform a pci_dma_sync_for_device, and then the device again owns the buffer. */ extern void -pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr, size_t size, - int dir); +pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr, + size_t size, int dir); extern void -pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr, size_t size, - int dir); +pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr, + size_t size, int dir); /* Do multiple DMA mappings at once. */ @@ -65,6 +65,28 @@ extern void pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len, int dir); +/* SG-list versions of pci_dma_sync functions. */ +extern void +pci_dma_sync_sg_for_cpu (struct pci_dev *dev, + struct scatterlist *sg, int sg_len, + int dir); +extern void +pci_dma_sync_sg_for_device (struct pci_dev *dev, + struct scatterlist *sg, int sg_len, + int dir); + +#define pci_map_page(dev, page, offs, size, dir) \ + pci_map_single(dev, (page_address(page) + (offs)), size, dir) +#define pci_unmap_page(dev,addr,sz,dir) \ + pci_unmap_single(dev, addr, sz, dir) + +/* Test for pci_map_single or pci_map_page having generated an error. */ +static inline int +pci_dma_mapping_error (dma_addr_t dma_addr) +{ + return dma_addr == 0; +} + /* Allocate and map kernel buffer using consistent mode DMA for PCI device. Returns non-NULL cpu-view pointer to the buffer if successful and sets *DMA_ADDR to the pci side dma address as well, @@ -91,6 +113,9 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif +extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); +extern void pci_iounmap (struct pci_dev *dev, void __iomem *addr); + static inline void pcibios_add_platform_entries(struct pci_dev *dev) { } diff --git a/include/asm-v850/pgtable.h b/include/asm-v850/pgtable.h index 76e380e481e9..3cf8775ce85f 100644 --- a/include/asm-v850/pgtable.h +++ b/include/asm-v850/pgtable.h @@ -23,6 +23,8 @@ #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) +static inline int pte_file (pte_t pte) { return 0; } + /* These mean nothing to !CONFIG_MMU. */ #define PAGE_NONE __pgprot(0) diff --git a/include/asm-v850/socket.h b/include/asm-v850/socket.h index 213b852af53e..0240d366a0a4 100644 --- a/include/asm-v850/socket.h +++ b/include/asm-v850/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-v850/types.h b/include/asm-v850/types.h index e7cfe5b33a10..dcef57196875 100644 --- a/include/asm-v850/types.h +++ b/include/asm-v850/types.h @@ -59,8 +59,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; -typedef unsigned int kmem_bufctl_t; - #endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-v850/v850e2_cache.h b/include/asm-v850/v850e2_cache.h index 61acda1023e8..87edf0d311d5 100644 --- a/include/asm-v850/v850e2_cache.h +++ b/include/asm-v850/v850e2_cache.h @@ -2,8 +2,8 @@ * include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2 * cache memories * - * Copyright (C) 2003 NEC Electronics Corporation - * Copyright (C) 2003 Miles Bader <miles@gnu.org> + * Copyright (C) 2003,05 NEC Electronics Corporation + * Copyright (C) 2003,05 Miles Bader <miles@gnu.org> * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -69,6 +69,7 @@ /* For <asm/cache.h> */ #define L1_CACHE_BYTES V850E2_CACHE_LINE_SIZE +#define L1_CACHE_SHIFT V850E2_CACHE_LINE_SIZE_BITS #endif /* __V850_V850E2_CACHE_H__ */ diff --git a/include/asm-x86_64/acpi.h b/include/asm-x86_64/acpi.h index a6b41b892062..dc8c981af27f 100644 --- a/include/asm-x86_64/acpi.h +++ b/include/asm-x86_64/acpi.h @@ -28,6 +28,8 @@ #ifdef __KERNEL__ +#include <acpi/pdc_intel.h> + #define COMPILER_DEPENDENT_INT64 long long #define COMPILER_DEPENDENT_UINT64 unsigned long long @@ -99,12 +101,6 @@ __acpi_release_global_lock (unsigned int *lock) :"=r"(n_hi), "=r"(n_lo) \ :"0"(n_hi), "1"(n_lo)) -/* - * Refer Intel ACPI _PDC support document for bit definitions - */ -#define ACPI_PDC_EST_CAPABILITY_SMP 0xa -#define ACPI_PDC_EST_CAPABILITY_MSR 0x1 - #ifdef CONFIG_ACPI_BOOT extern int acpi_lapic; extern int acpi_ioapic; diff --git a/include/asm-x86_64/bitops.h b/include/asm-x86_64/bitops.h index a31bb99be53f..05a0d374404b 100644 --- a/include/asm-x86_64/bitops.h +++ b/include/asm-x86_64/bitops.h @@ -348,8 +348,7 @@ static inline int sched_find_first_bit(const unsigned long *b) return __ffs(b[0]); if (b[1]) return __ffs(b[1]) + 64; - if (b[2]) - return __ffs(b[2]) + 128; + return __ffs(b[2]) + 128; } /** diff --git a/include/asm-x86_64/bug.h b/include/asm-x86_64/bug.h index 3d2a666a5dd5..eed785667289 100644 --- a/include/asm-x86_64/bug.h +++ b/include/asm-x86_64/bug.h @@ -8,17 +8,24 @@ * this frame. */ struct bug_frame { - unsigned char ud2[2]; + unsigned char ud2[2]; + unsigned char mov; /* should use 32bit offset instead, but the assembler doesn't like it */ char *filename; + unsigned char ret; unsigned short line; } __attribute__((packed)); #ifdef CONFIG_BUG #define HAVE_ARCH_BUG -#define BUG() \ - asm volatile("ud2 ; .quad %c1 ; .short %c0" :: \ +/* We turn the bug frame into valid instructions to not confuse + the disassembler. Thanks to Jan Beulich & Suresh Siddha + for nice instruction selection. + The magic numbers generate mov $64bitimm,%eax ; ret $offset. */ +#define BUG() \ + asm volatile( \ + "ud2 ; .byte 0xa3 ; .quad %c1 ; .byte 0xc2 ; .short %c0" :: \ "i"(__LINE__), "i" (__stringify(__FILE__))) void out_of_line_bug(void); #else diff --git a/include/asm-x86_64/checksum.h b/include/asm-x86_64/checksum.h index d01356f01448..989469e8e0b7 100644 --- a/include/asm-x86_64/checksum.h +++ b/include/asm-x86_64/checksum.h @@ -64,7 +64,7 @@ static inline unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl) " adcl $0, %0\n" " notl %0\n" "2:" - /* Since the input registers which are loaded with iph and ipl + /* Since the input registers which are loaded with iph and ihl are modified, we must also specify them as outputs, or gcc will assume they contain their original values. */ : "=r" (sum), "=r" (iph), "=r" (ihl) diff --git a/include/asm-x86_64/desc.h b/include/asm-x86_64/desc.h index 6aefb9c0280d..c89b58bebee2 100644 --- a/include/asm-x86_64/desc.h +++ b/include/asm-x86_64/desc.h @@ -75,6 +75,7 @@ struct desc_ptr { */ extern struct desc_struct default_ldt[]; extern struct gate_struct idt_table[]; +extern struct desc_ptr cpu_gdt_descr[]; static inline void _set_gate(void *adr, unsigned type, unsigned long func, unsigned dpl, unsigned ist) { diff --git a/include/asm-x86_64/e820.h b/include/asm-x86_64/e820.h index 8e94edf0b984..e682edc24a68 100644 --- a/include/asm-x86_64/e820.h +++ b/include/asm-x86_64/e820.h @@ -51,6 +51,8 @@ extern int e820_mapped(unsigned long start, unsigned long end, unsigned type); extern void e820_bootmem_free(pg_data_t *pgdat, unsigned long start,unsigned long end); extern void e820_setup_gap(void); +extern unsigned long e820_hole_size(unsigned long start_pfn, + unsigned long end_pfn); extern void __init parse_memopt(char *p, char **end); diff --git a/include/asm-x86_64/emergency-restart.h b/include/asm-x86_64/emergency-restart.h new file mode 100644 index 000000000000..680c39563345 --- /dev/null +++ b/include/asm-x86_64/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +extern void machine_emergency_restart(void); + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-x86_64/ia32_unistd.h b/include/asm-x86_64/ia32_unistd.h index f3b7111cf33d..d5166ec3868d 100644 --- a/include/asm-x86_64/ia32_unistd.h +++ b/include/asm-x86_64/ia32_unistd.h @@ -294,7 +294,12 @@ #define __NR_ia32_add_key 286 #define __NR_ia32_request_key 287 #define __NR_ia32_keyctl 288 +#define __NR_ia32_ioprio_set 289 +#define __NR_ia32_ioprio_get 290 +#define __NR_ia32_inotify_init 291 +#define __NR_ia32_inotify_add_watch 292 +#define __NR_ia32_inotify_rm_watch 293 -#define IA32_NR_syscalls 290 /* must be > than biggest syscall! */ +#define IA32_NR_syscalls 294 /* must be > than biggest syscall! */ #endif /* _ASM_X86_64_IA32_UNISTD_H_ */ diff --git a/include/asm-x86_64/ipi.h b/include/asm-x86_64/ipi.h index d1841847ed89..5e166b9d3bde 100644 --- a/include/asm-x86_64/ipi.h +++ b/include/asm-x86_64/ipi.h @@ -82,30 +82,27 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector) */ local_irq_save(flags); - for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) { - if (cpu_isset(query_cpu, mask)) { - - /* - * Wait for idle. - */ - apic_wait_icr_idle(); - - /* - * prepare target chip field - */ - cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]); - apic_write_around(APIC_ICR2, cfg); - - /* - * program the ICR - */ - cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL); - - /* - * Send the IPI. The write to APIC_ICR fires this off. - */ - apic_write_around(APIC_ICR, cfg); - } + for_each_cpu_mask(query_cpu, mask) { + /* + * Wait for idle. + */ + apic_wait_icr_idle(); + + /* + * prepare target chip field + */ + cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]); + apic_write_around(APIC_ICR2, cfg); + + /* + * program the ICR + */ + cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL); + + /* + * Send the IPI. The write to APIC_ICR fires this off. + */ + apic_write_around(APIC_ICR, cfg); } local_irq_restore(flags); } diff --git a/include/asm-x86_64/irq.h b/include/asm-x86_64/irq.h index eb3b7aa9eb9f..4482657777bb 100644 --- a/include/asm-x86_64/irq.h +++ b/include/asm-x86_64/irq.h @@ -57,4 +57,6 @@ int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); extern void fixup_irqs(cpumask_t map); #endif +#define __ARCH_HAS_DO_SOFTIRQ 1 + #endif /* _ASM_IRQ_H */ diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h index bc700232728d..ba15279a79d0 100644 --- a/include/asm-x86_64/msr.h +++ b/include/asm-x86_64/msr.h @@ -218,7 +218,7 @@ extern inline unsigned int cpuid_edx(unsigned int op) #define MSR_K7_PERFCTR3 0xC0010007 #define MSR_K8_TOP_MEM1 0xC001001A #define MSR_K8_TOP_MEM2 0xC001001D -#define MSR_K8_SYSCFG 0xC0000010 +#define MSR_K8_SYSCFG 0xC0010010 /* K6 MSRs */ #define MSR_K6_EFER 0xC0000080 diff --git a/include/asm-x86_64/page.h b/include/asm-x86_64/page.h index 431318764af6..135ffaa0393b 100644 --- a/include/asm-x86_64/page.h +++ b/include/asm-x86_64/page.h @@ -28,7 +28,6 @@ #define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) #define HPAGE_MASK (~(HPAGE_SIZE - 1)) #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) -#define ARCH_HAS_HUGETLB_CLEAN_STALE_PGTABLE #ifdef __KERNEL__ #ifndef __ASSEMBLY__ @@ -92,20 +91,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; #include <asm/bug.h> -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - #endif /* __ASSEMBLY__ */ #define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET) @@ -141,4 +126,6 @@ extern __inline__ int get_order(unsigned long size) #endif /* __KERNEL__ */ +#include <asm-generic/page.h> + #endif /* _X86_64_PAGE_H */ diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h index c1961db88fac..eeb3088a1c9e 100644 --- a/include/asm-x86_64/pci.h +++ b/include/asm-x86_64/pci.h @@ -33,7 +33,7 @@ extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int le extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value); void pcibios_set_master(struct pci_dev *dev); -void pcibios_penalize_isa_irq(int irq); +void pcibios_penalize_isa_irq(int irq, int active); struct irq_routing_table *pcibios_get_irq_routing_table(void); int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h index 4eec176c3c39..5e0f2fdab0d3 100644 --- a/include/asm-x86_64/pgtable.h +++ b/include/asm-x86_64/pgtable.h @@ -104,6 +104,19 @@ extern inline void pgd_clear (pgd_t * pgd) ((unsigned long) __va(pud_val(pud) & PHYSICAL_PAGE_MASK)) #define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte, 0)) + +static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full) +{ + pte_t pte; + if (full) { + pte = *ptep; + *ptep = __pte(0); + } else { + pte = ptep_get_and_clear(mm, addr, ptep); + } + return pte; +} + #define pte_same(a, b) ((a).pte == (b).pte) #define PMD_SIZE (1UL << PMD_SHIFT) @@ -143,7 +156,7 @@ extern inline void pgd_clear (pgd_t * pgd) #define _PAGE_ACCESSED 0x020 #define _PAGE_DIRTY 0x040 #define _PAGE_PSE 0x080 /* 2MB page */ -#define _PAGE_FILE 0x040 /* set:pagecache, unset:swap */ +#define _PAGE_FILE 0x040 /* nonlinear file mapping, saved PTE; unset:swap */ #define _PAGE_GLOBAL 0x100 /* Global TLB entry */ #define _PAGE_PROTNONE 0x080 /* If not present */ @@ -176,6 +189,8 @@ extern inline void pgd_clear (pgd_t * pgd) (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PCD) #define __PAGE_KERNEL_LARGE \ (__PAGE_KERNEL | _PAGE_PSE) +#define __PAGE_KERNEL_LARGE_EXEC \ + (__PAGE_KERNEL_EXEC | _PAGE_PSE) #define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL) @@ -245,6 +260,7 @@ static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) * The following only work if pte_present() is true. * Undefined behaviour if not.. */ +#define __LARGE_PTE (_PAGE_PSE|_PAGE_PRESENT) static inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_USER; } extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } extern inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; } @@ -252,8 +268,8 @@ extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } +static inline int pte_huge(pte_t pte) { return (pte_val(pte) & __LARGE_PTE) == __LARGE_PTE; } -#define __LARGE_PTE (_PAGE_PSE|_PAGE_PRESENT) extern inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } extern inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } extern inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; } @@ -431,6 +447,7 @@ extern int kern_addr_valid(unsigned long addr); #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY #define __HAVE_ARCH_PTEP_GET_AND_CLEAR +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL #define __HAVE_ARCH_PTEP_SET_WRPROTECT #define __HAVE_ARCH_PTE_SAME #include <asm-generic/pgtable.h> diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index 106f666517bb..194160f6a43f 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h @@ -32,7 +32,7 @@ #define ID_MASK 0x00200000 #define desc_empty(desc) \ - (!((desc)->a + (desc)->b)) + (!((desc)->a | (desc)->b)) #define desc_equal(desc1, desc2) \ (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b)) @@ -437,6 +437,11 @@ static inline void prefetchw(void *x) outb((data), 0x23); \ } while (0) +static inline void serialize_cpu(void) +{ + __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); +} + static inline void __monitor(const void *eax, unsigned long ecx, unsigned long edx) { diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h index aeb1b73e21e1..de8b57b2b62b 100644 --- a/include/asm-x86_64/smp.h +++ b/include/asm-x86_64/smp.h @@ -46,12 +46,12 @@ extern int pic_mode; extern void lock_ipi_call_lock(void); extern void unlock_ipi_call_lock(void); extern int smp_num_siblings; -extern void smp_flush_tlb(void); -extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs); extern void smp_send_reschedule(int cpu); -extern void smp_invalidate_rcv(void); /* Process an NMI */ extern void zap_low_mappings(void); void smp_stop_cpu(void); +extern int smp_call_function_single(int cpuid, void (*func) (void *info), + void *info, int retry, int wait); + extern cpumask_t cpu_sibling_map[NR_CPUS]; extern cpumask_t cpu_core_map[NR_CPUS]; extern u8 phys_proc_id[NR_CPUS]; diff --git a/include/asm-x86_64/socket.h b/include/asm-x86_64/socket.h index d9a252ea8210..f2cdbeae5d5b 100644 --- a/include/asm-x86_64/socket.h +++ b/include/asm-x86_64/socket.h @@ -14,6 +14,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h index 76165736e43a..8606e170a7dc 100644 --- a/include/asm-x86_64/system.h +++ b/include/asm-x86_64/system.h @@ -116,12 +116,12 @@ struct alt_instr { /* * Alternative inline assembly with input. * - * Pecularities: + * Peculiarities: * No memory clobber here. * Argument numbers start with 1. * Best is to use constraints that are fixed size (like (%1) ... "r") * If you use variable sized constraints like "m" or "g" in the - * replacement maake sure to pad to the worst case length. + * replacement make sure to pad to the worst case length. */ #define alternative_input(oldinstr, newinstr, feature, input...) \ asm volatile ("661:\n\t" oldinstr "\n662:\n" \ @@ -335,9 +335,6 @@ void cpu_idle_wait(void); void disable_hlt(void); void enable_hlt(void); -#define HAVE_EAT_KEY -void eat_key(void); - extern unsigned long arch_align_stack(unsigned long sp); #endif diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h index 061742382520..505b0cf906de 100644 --- a/include/asm-x86_64/tlbflush.h +++ b/include/asm-x86_64/tlbflush.h @@ -56,8 +56,9 @@ extern unsigned long pgkern_mask; * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables * - * ..but the x86_64 has somewhat limited tlb flushing capabilities, - * and page-granular flushes are available only on i486 and up. + * x86-64 can only flush individual pages or full VMs. For a range flush + * we always do the full VM. Might be worth trying if for a small + * range a few INVLPGs in a row are a win. */ #ifndef CONFIG_SMP @@ -115,7 +116,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st static inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) { - /* x86_64 does not keep any page table caches in TLB */ + /* x86_64 does not keep any page table caches in a software TLB. + The CPUs do in their hardware TLBs, but they are handled + by the normal TLB flushing algorithms. */ } #endif /* _X8664_TLBFLUSH_H */ diff --git a/include/asm-x86_64/types.h b/include/asm-x86_64/types.h index 32bd1426b523..c86c2e6793e2 100644 --- a/include/asm-x86_64/types.h +++ b/include/asm-x86_64/types.h @@ -51,8 +51,6 @@ typedef u64 dma_addr_t; typedef u64 sector_t; #define HAVE_SECTOR_T -typedef unsigned short kmem_bufctl_t; - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h index 6560439a83e4..11ba931cf82f 100644 --- a/include/asm-x86_64/unistd.h +++ b/include/asm-x86_64/unistd.h @@ -565,8 +565,14 @@ __SYSCALL(__NR_keyctl, sys_keyctl) __SYSCALL(__NR_ioprio_set, sys_ioprio_set) #define __NR_ioprio_get 252 __SYSCALL(__NR_ioprio_get, sys_ioprio_get) - -#define __NR_syscall_max __NR_ioprio_get +#define __NR_inotify_init 253 +__SYSCALL(__NR_inotify_init, sys_inotify_init) +#define __NR_inotify_add_watch 254 +__SYSCALL(__NR_inotify_add_watch, sys_inotify_add_watch) +#define __NR_inotify_rm_watch 255 +__SYSCALL(__NR_inotify_rm_watch, sys_inotify_rm_watch) + +#define __NR_syscall_max __NR_inotify_rm_watch #ifndef __NO_STUBS /* user-visible error numbers are in the range -1 - -4095 */ diff --git a/include/asm-xtensa/atomic.h b/include/asm-xtensa/atomic.h index d72bcb32ba4f..24f86f0e43cf 100644 --- a/include/asm-xtensa/atomic.h +++ b/include/asm-xtensa/atomic.h @@ -66,7 +66,7 @@ typedef struct { volatile int counter; } atomic_t; * * Atomically adds @i to @v. */ -extern __inline__ void atomic_add(int i, atomic_t * v) +static inline void atomic_add(int i, atomic_t * v) { unsigned int vval; @@ -90,7 +90,7 @@ extern __inline__ void atomic_add(int i, atomic_t * v) * * Atomically subtracts @i from @v. */ -extern __inline__ void atomic_sub(int i, atomic_t *v) +static inline void atomic_sub(int i, atomic_t *v) { unsigned int vval; @@ -111,7 +111,7 @@ extern __inline__ void atomic_sub(int i, atomic_t *v) * We use atomic_{add|sub}_return to define other functions. */ -extern __inline__ int atomic_add_return(int i, atomic_t * v) +static inline int atomic_add_return(int i, atomic_t * v) { unsigned int vval; @@ -130,7 +130,7 @@ extern __inline__ int atomic_add_return(int i, atomic_t * v) return vval; } -extern __inline__ int atomic_sub_return(int i, atomic_t * v) +static inline int atomic_sub_return(int i, atomic_t * v) { unsigned int vval; @@ -224,7 +224,7 @@ extern __inline__ int atomic_sub_return(int i, atomic_t * v) #define atomic_add_negative(i,v) (atomic_add_return((i),(v)) < 0) -extern __inline__ void atomic_clear_mask(unsigned int mask, atomic_t *v) +static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) { unsigned int all_f = -1; unsigned int vval; @@ -243,7 +243,7 @@ extern __inline__ void atomic_clear_mask(unsigned int mask, atomic_t *v) ); } -extern __inline__ void atomic_set_mask(unsigned int mask, atomic_t *v) +static inline void atomic_set_mask(unsigned int mask, atomic_t *v) { unsigned int vval; diff --git a/include/asm-xtensa/checksum.h b/include/asm-xtensa/checksum.h index 1a00fad19929..81a797ae3abe 100644 --- a/include/asm-xtensa/checksum.h +++ b/include/asm-xtensa/checksum.h @@ -47,14 +47,14 @@ asmlinkage unsigned int csum_partial_copy_generic( const char *src, char *dst, i * If you use these functions directly please don't forget the * verify_area(). */ -extern __inline__ +static inline unsigned int csum_partial_copy_nocheck ( const char *src, char *dst, int len, int sum) { return csum_partial_copy_generic ( src, dst, len, sum, NULL, NULL); } -extern __inline__ +static inline unsigned int csum_partial_copy_from_user ( const char *src, char *dst, int len, int sum, int *err_ptr) { diff --git a/include/asm-xtensa/delay.h b/include/asm-xtensa/delay.h index 0a123d53a636..1bc601ec3621 100644 --- a/include/asm-xtensa/delay.h +++ b/include/asm-xtensa/delay.h @@ -18,7 +18,7 @@ extern unsigned long loops_per_jiffy; -extern __inline__ void __delay(unsigned long loops) +static inline void __delay(unsigned long loops) { /* 2 cycles per loop. */ __asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 2, 1b" diff --git a/include/asm-xtensa/emergency-restart.h b/include/asm-xtensa/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/include/asm-xtensa/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include <asm-generic/emergency-restart.h> + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h index 2c471c42ecfc..c5c13985bbe1 100644 --- a/include/asm-xtensa/io.h +++ b/include/asm-xtensa/io.h @@ -41,12 +41,12 @@ static inline unsigned int _swapl (unsigned int v) * These are trivial on the 1:1 Linux/Xtensa mapping */ -extern inline unsigned long virt_to_phys(volatile void * address) +static inline unsigned long virt_to_phys(volatile void * address) { return PHYSADDR((unsigned long)address); } -extern inline void * phys_to_virt(unsigned long address) +static inline void * phys_to_virt(unsigned long address) { return (void*) CACHED_ADDR(address); } @@ -55,12 +55,12 @@ extern inline void * phys_to_virt(unsigned long address) * IO bus memory addresses are also 1:1 with the physical address */ -extern inline unsigned long virt_to_bus(volatile void * address) +static inline unsigned long virt_to_bus(volatile void * address) { return PHYSADDR((unsigned long)address); } -extern inline void * bus_to_virt (unsigned long address) +static inline void * bus_to_virt (unsigned long address) { return (void *) CACHED_ADDR(address); } @@ -69,17 +69,17 @@ extern inline void * bus_to_virt (unsigned long address) * Change "struct page" to physical address. */ -extern inline void *ioremap(unsigned long offset, unsigned long size) +static inline void *ioremap(unsigned long offset, unsigned long size) { return (void *) CACHED_ADDR_IO(offset); } -extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) +static inline void *ioremap_nocache(unsigned long offset, unsigned long size) { return (void *) BYPASS_ADDR_IO(offset); } -extern inline void iounmap(void *addr) +static inline void iounmap(void *addr) { } diff --git a/include/asm-xtensa/mmu_context.h b/include/asm-xtensa/mmu_context.h index 1b0801548cd9..364a7b057bfa 100644 --- a/include/asm-xtensa/mmu_context.h +++ b/include/asm-xtensa/mmu_context.h @@ -199,13 +199,13 @@ extern pgd_t *current_pgd; #define ASID_FIRST_VERSION \ ((unsigned long)(~ASID_VERSION_MASK) + 1 + ASID_FIRST_NONRESERVED) -extern inline void set_rasid_register (unsigned long val) +static inline void set_rasid_register (unsigned long val) { __asm__ __volatile__ (" wsr %0, "__stringify(RASID)"\n\t" " isync\n" : : "a" (val)); } -extern inline unsigned long get_rasid_register (void) +static inline unsigned long get_rasid_register (void) { unsigned long tmp; __asm__ __volatile__ (" rsr %0, "__stringify(RASID)"\n\t" : "=a" (tmp)); @@ -215,7 +215,7 @@ extern inline unsigned long get_rasid_register (void) #if ((XCHAL_MMU_ASID_INVALID == 0) && (XCHAL_MMU_ASID_KERNEL == 1)) -extern inline void +static inline void get_new_mmu_context(struct mm_struct *mm, unsigned long asid) { extern void flush_tlb_all(void); @@ -234,7 +234,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long asid) /* XCHAL_MMU_ASID_INVALID == 0 and XCHAL_MMU_ASID_KERNEL ==1 are really the best, but if you insist... */ -extern inline int validate_asid (unsigned long asid) +static inline int validate_asid (unsigned long asid) { switch (asid) { case XCHAL_MMU_ASID_INVALID: @@ -247,7 +247,7 @@ extern inline int validate_asid (unsigned long asid) return 1; /* valid */ } -extern inline void +static inline void get_new_mmu_context(struct mm_struct *mm, unsigned long asid) { extern void flush_tlb_all(void); @@ -274,14 +274,14 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long asid) * instance. */ -extern inline int +static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { mm->context = NO_CONTEXT; return 0; } -extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) { unsigned long asid = asid_cache; @@ -301,7 +301,7 @@ extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * Destroy context related info for an mm_struct that is about * to be put to rest. */ -extern inline void destroy_context(struct mm_struct *mm) +static inline void destroy_context(struct mm_struct *mm) { /* Nothing to do. */ } @@ -310,7 +310,7 @@ extern inline void destroy_context(struct mm_struct *mm) * After we have set current->mm to a new value, this activates * the context for the new mm so we see the new mappings. */ -extern inline void +static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) { /* Unconditionally get a new ASID. */ diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h index b495e5b5a942..8ded36f255a2 100644 --- a/include/asm-xtensa/page.h +++ b/include/asm-xtensa/page.h @@ -55,7 +55,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; * Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) +static inline int get_order(unsigned long size) { int order; #ifndef XCHAL_HAVE_NSU diff --git a/include/asm-xtensa/page.h.n b/include/asm-xtensa/page.h.n deleted file mode 100644 index 546cc6624f24..000000000000 --- a/include/asm-xtensa/page.h.n +++ /dev/null @@ -1,135 +0,0 @@ -/* - * linux/include/asm-xtensa/page.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version2 as - * published by the Free Software Foundation. - * - * Copyright (C) 2001 - 2005 Tensilica Inc. - */ - -#ifndef _XTENSA_PAGE_H -#define _XTENSA_PAGE_H - -#ifdef __KERNEL__ - -#include <asm/processor.h> -#include <linux/config.h> - -/* - * PAGE_SHIFT determines the page size - * PAGE_ALIGN(x) aligns the pointer to the (next) page boundary - */ -#define PAGE_SHIFT XCHAL_MMU_MIN_PTE_PAGE_SIZE -#define PAGE_SIZE (1 << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE - 1) & PAGE_MASK) - -#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS) -#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR - -#ifdef __ASSEMBLY__ - -#define __pgprot(x) (x) - -#else - - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pte; } pte_t; /* page table entry */ -typedef struct { unsigned long pmd; } pmd_t; /* PMD table entry */ -typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */ -typedef struct { unsigned long pgprot; } pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* - * Pure 2^n version of get_order - */ -extern __inline__ int get_order(unsigned long size) -{ - int order; -#ifndef XCHAL_HAVE_NSU - unsigned long x1, x2, x4, x8, x16; - - size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; - x1 = size & 0xAAAAAAAA; - x2 = size & 0xCCCCCCCC; - x4 = size & 0xF0F0F0F0; - x8 = size & 0xFF00FF00; - x16 = size & 0xFFFF0000; - order = x2 ? 2 : 0; - order += (x16 != 0) * 16; - order += (x8 != 0) * 8; - order += (x4 != 0) * 4; - order += (x1 != 0); - - return order; -#else - size = (size - 1) >> PAGE_SHIFT; - asm ("nsau %0, %1" : "=r" (order) : "r" (size)); - return 32 - order; -#endif -} - - -struct page; -extern void clear_page(void *page); -extern void copy_page(void *to, void *from); - -/* - * If we have cache aliasing and writeback caches, we might have to do - * some extra work - */ - -#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK -void clear_user_page(void *addr, unsigned long vaddr, struct page* page); -void copy_user_page(void *to, void* from, unsigned long vaddr, struct page* page); -#else -# define clear_user_page(page,vaddr,pg) clear_page(page) -# define copy_user_page(to, from, vaddr, pg) copy_page(to, from) -#endif - - -/* - * This handles the memory map. We handle pages at - * XCHAL_KSEG_CACHED_VADDR for kernels with 32 bit address space. - * These macros are for conversion of kernel address, not user - * addresses. - */ - -#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) -#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) -#define pfn_valid(pfn) ((unsigned long)pfn < max_mapnr) -#ifndef CONFIG_DISCONTIGMEM -# define pfn_to_page(pfn) (mem_map + (pfn)) -# define page_to_pfn(page) ((unsigned long)((page) - mem_map)) -#else -# error CONFIG_DISCONTIGMEM not supported -#endif - -#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) -#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) -#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) - -#define WANT_PAGE_VIRTUAL - - -#endif /* __ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#endif /* __KERNEL__ */ -#endif /* _XTENSA_PAGE_H */ diff --git a/include/asm-xtensa/pci.h b/include/asm-xtensa/pci.h index 6817742301c2..24eb7fc25da8 100644 --- a/include/asm-xtensa/pci.h +++ b/include/asm-xtensa/pci.h @@ -22,12 +22,12 @@ extern struct pci_controller* pcibios_alloc_controller(void); -extern inline void pcibios_set_master(struct pci_dev *dev) +static inline void pcibios_set_master(struct pci_dev *dev) { /* No special bus mastering setup handling */ } -extern inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h index 0bb6416ae266..883ebc2d75d6 100644 --- a/include/asm-xtensa/pgtable.h +++ b/include/asm-xtensa/pgtable.h @@ -260,7 +260,7 @@ static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_RW; return pt #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) -extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); } @@ -278,14 +278,14 @@ static inline void update_pte(pte_t *ptep, pte_t pteval) #endif } -extern inline void +static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) { update_pte(ptep, pteval); } -extern inline void +static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval) { *pmdp = pmdval; diff --git a/include/asm-xtensa/semaphore.h b/include/asm-xtensa/semaphore.h index c8a7574a9a57..db740b8bc6f0 100644 --- a/include/asm-xtensa/semaphore.h +++ b/include/asm-xtensa/semaphore.h @@ -47,7 +47,7 @@ struct semaphore { #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) -extern inline void sema_init (struct semaphore *sem, int val) +static inline void sema_init (struct semaphore *sem, int val) { /* * *sem = (struct semaphore)__SEMAPHORE_INITIALIZER((*sem),val); @@ -79,7 +79,7 @@ asmlinkage void __up(struct semaphore * sem); extern spinlock_t semaphore_wake_lock; -extern __inline__ void down(struct semaphore * sem) +static inline void down(struct semaphore * sem) { #if WAITQUEUE_DEBUG CHECK_MAGIC(sem->__magic); @@ -89,7 +89,7 @@ extern __inline__ void down(struct semaphore * sem) __down(sem); } -extern __inline__ int down_interruptible(struct semaphore * sem) +static inline int down_interruptible(struct semaphore * sem) { int ret = 0; #if WAITQUEUE_DEBUG @@ -101,7 +101,7 @@ extern __inline__ int down_interruptible(struct semaphore * sem) return ret; } -extern __inline__ int down_trylock(struct semaphore * sem) +static inline int down_trylock(struct semaphore * sem) { int ret = 0; #if WAITQUEUE_DEBUG @@ -117,7 +117,7 @@ extern __inline__ int down_trylock(struct semaphore * sem) * Note! This is subtle. We jump to wake people up only if * the semaphore was negative (== somebody was waiting on it). */ -extern __inline__ void up(struct semaphore * sem) +static inline void up(struct semaphore * sem) { #if WAITQUEUE_DEBUG CHECK_MAGIC(sem->__magic); diff --git a/include/asm-xtensa/socket.h b/include/asm-xtensa/socket.h index daccd05a14cd..00f83f3a6d72 100644 --- a/include/asm-xtensa/socket.h +++ b/include/asm-xtensa/socket.h @@ -24,6 +24,8 @@ #define SO_BROADCAST 6 #define SO_SNDBUF 7 #define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 #define SO_KEEPALIVE 9 #define SO_OOBINLINE 10 #define SO_NO_CHECK 11 diff --git a/include/asm-xtensa/string.h b/include/asm-xtensa/string.h index 3f81b27d9809..5fb8c27cbef5 100644 --- a/include/asm-xtensa/string.h +++ b/include/asm-xtensa/string.h @@ -16,7 +16,7 @@ #define _XTENSA_STRING_H #define __HAVE_ARCH_STRCPY -extern __inline__ char *strcpy(char *__dest, const char *__src) +static inline char *strcpy(char *__dest, const char *__src) { register char *__xdest = __dest; unsigned long __dummy; @@ -35,7 +35,7 @@ extern __inline__ char *strcpy(char *__dest, const char *__src) } #define __HAVE_ARCH_STRNCPY -extern __inline__ char *strncpy(char *__dest, const char *__src, size_t __n) +static inline char *strncpy(char *__dest, const char *__src, size_t __n) { register char *__xdest = __dest; unsigned long __dummy; @@ -60,7 +60,7 @@ extern __inline__ char *strncpy(char *__dest, const char *__src, size_t __n) } #define __HAVE_ARCH_STRCMP -extern __inline__ int strcmp(const char *__cs, const char *__ct) +static inline int strcmp(const char *__cs, const char *__ct) { register int __res; unsigned long __dummy; @@ -82,7 +82,7 @@ extern __inline__ int strcmp(const char *__cs, const char *__ct) } #define __HAVE_ARCH_STRNCMP -extern __inline__ int strncmp(const char *__cs, const char *__ct, size_t __n) +static inline int strncmp(const char *__cs, const char *__ct, size_t __n) { register int __res; unsigned long __dummy; diff --git a/include/asm-xtensa/system.h b/include/asm-xtensa/system.h index 690fe325e671..f09393232e5e 100644 --- a/include/asm-xtensa/system.h +++ b/include/asm-xtensa/system.h @@ -56,7 +56,7 @@ static inline int irqs_disabled(void) #define clear_cpenable() __clear_cpenable() -extern __inline__ void __clear_cpenable(void) +static inline void __clear_cpenable(void) { #if XCHAL_HAVE_CP unsigned long i = 0; @@ -64,7 +64,7 @@ extern __inline__ void __clear_cpenable(void) #endif } -extern __inline__ void enable_coprocessor(int i) +static inline void enable_coprocessor(int i) { #if XCHAL_HAVE_CP int cp; @@ -74,7 +74,7 @@ extern __inline__ void enable_coprocessor(int i) #endif } -extern __inline__ void disable_coprocessor(int i) +static inline void disable_coprocessor(int i) { #if XCHAL_HAVE_CP int cp; @@ -123,7 +123,7 @@ do { \ * cmpxchg */ -extern __inline__ unsigned long +static inline unsigned long __cmpxchg_u32(volatile int *p, int old, int new) { __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t" @@ -173,7 +173,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) * where no register reference will cause an overflow. */ -extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) +static inline unsigned long xchg_u32(volatile int * m, unsigned long val) { unsigned long tmp; __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t" diff --git a/include/asm-xtensa/tlbflush.h b/include/asm-xtensa/tlbflush.h index 23bfe9db45f5..43f6ec859af9 100644 --- a/include/asm-xtensa/tlbflush.h +++ b/include/asm-xtensa/tlbflush.h @@ -39,7 +39,7 @@ extern void flush_tlb_range(struct vm_area_struct*,unsigned long,unsigned long); * page-table pages. */ -extern inline void flush_tlb_pgtables(struct mm_struct *mm, +static inline void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long end) { } @@ -51,26 +51,26 @@ extern inline void flush_tlb_pgtables(struct mm_struct *mm, #define ITLB_PROBE_SUCCESS (1 << ITLB_WAYS_LOG2) #define DTLB_PROBE_SUCCESS (1 << DTLB_WAYS_LOG2) -extern inline unsigned long itlb_probe(unsigned long addr) +static inline unsigned long itlb_probe(unsigned long addr) { unsigned long tmp; __asm__ __volatile__("pitlb %0, %1\n\t" : "=a" (tmp) : "a" (addr)); return tmp; } -extern inline unsigned long dtlb_probe(unsigned long addr) +static inline unsigned long dtlb_probe(unsigned long addr) { unsigned long tmp; __asm__ __volatile__("pdtlb %0, %1\n\t" : "=a" (tmp) : "a" (addr)); return tmp; } -extern inline void invalidate_itlb_entry (unsigned long probe) +static inline void invalidate_itlb_entry (unsigned long probe) { __asm__ __volatile__("iitlb %0; isync\n\t" : : "a" (probe)); } -extern inline void invalidate_dtlb_entry (unsigned long probe) +static inline void invalidate_dtlb_entry (unsigned long probe) { __asm__ __volatile__("idtlb %0; dsync\n\t" : : "a" (probe)); } @@ -80,68 +80,68 @@ extern inline void invalidate_dtlb_entry (unsigned long probe) * caller must follow up with an 'isync', which can be relatively * expensive on some Xtensa implementations. */ -extern inline void invalidate_itlb_entry_no_isync (unsigned entry) +static inline void invalidate_itlb_entry_no_isync (unsigned entry) { /* Caller must follow up with 'isync'. */ __asm__ __volatile__ ("iitlb %0\n" : : "a" (entry) ); } -extern inline void invalidate_dtlb_entry_no_isync (unsigned entry) +static inline void invalidate_dtlb_entry_no_isync (unsigned entry) { /* Caller must follow up with 'isync'. */ __asm__ __volatile__ ("idtlb %0\n" : : "a" (entry) ); } -extern inline void set_itlbcfg_register (unsigned long val) +static inline void set_itlbcfg_register (unsigned long val) { __asm__ __volatile__("wsr %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t" : : "a" (val)); } -extern inline void set_dtlbcfg_register (unsigned long val) +static inline void set_dtlbcfg_register (unsigned long val) { __asm__ __volatile__("wsr %0, "__stringify(DTLBCFG)"; dsync\n\t" : : "a" (val)); } -extern inline void set_ptevaddr_register (unsigned long val) +static inline void set_ptevaddr_register (unsigned long val) { __asm__ __volatile__(" wsr %0, "__stringify(PTEVADDR)"; isync\n" : : "a" (val)); } -extern inline unsigned long read_ptevaddr_register (void) +static inline unsigned long read_ptevaddr_register (void) { unsigned long tmp; __asm__ __volatile__("rsr %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp)); return tmp; } -extern inline void write_dtlb_entry (pte_t entry, int way) +static inline void write_dtlb_entry (pte_t entry, int way) { __asm__ __volatile__("wdtlb %1, %0; dsync\n\t" : : "r" (way), "r" (entry) ); } -extern inline void write_itlb_entry (pte_t entry, int way) +static inline void write_itlb_entry (pte_t entry, int way) { __asm__ __volatile__("witlb %1, %0; isync\n\t" : : "r" (way), "r" (entry) ); } -extern inline void invalidate_page_directory (void) +static inline void invalidate_page_directory (void) { invalidate_dtlb_entry (DTLB_WAY_PGTABLE); } -extern inline void invalidate_itlb_mapping (unsigned address) +static inline void invalidate_itlb_mapping (unsigned address) { unsigned long tlb_entry; while ((tlb_entry = itlb_probe (address)) & ITLB_PROBE_SUCCESS) invalidate_itlb_entry (tlb_entry); } -extern inline void invalidate_dtlb_mapping (unsigned address) +static inline void invalidate_dtlb_mapping (unsigned address) { unsigned long tlb_entry; while ((tlb_entry = dtlb_probe (address)) & DTLB_PROBE_SUCCESS) @@ -165,28 +165,28 @@ extern inline void invalidate_dtlb_mapping (unsigned address) * as[07..00] contain the asid */ -extern inline unsigned long read_dtlb_virtual (int way) +static inline unsigned long read_dtlb_virtual (int way) { unsigned long tmp; __asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); return tmp; } -extern inline unsigned long read_dtlb_translation (int way) +static inline unsigned long read_dtlb_translation (int way) { unsigned long tmp; __asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); return tmp; } -extern inline unsigned long read_itlb_virtual (int way) +static inline unsigned long read_itlb_virtual (int way) { unsigned long tmp; __asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); return tmp; } -extern inline unsigned long read_itlb_translation (int way) +static inline unsigned long read_itlb_translation (int way) { unsigned long tmp; __asm__ __volatile__("ritlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); diff --git a/include/asm-xtensa/types.h b/include/asm-xtensa/types.h index ebac00469852..9d99a8e9e337 100644 --- a/include/asm-xtensa/types.h +++ b/include/asm-xtensa/types.h @@ -58,8 +58,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; -typedef unsigned int kmem_bufctl_t; - #endif /* __KERNEL__ */ #endif diff --git a/include/asm-xtensa/uaccess.h b/include/asm-xtensa/uaccess.h index 35576b25c7b2..fc268ac923c0 100644 --- a/include/asm-xtensa/uaccess.h +++ b/include/asm-xtensa/uaccess.h @@ -211,7 +211,7 @@ #define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size))) #define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size)) -extern inline int verify_area(int type, const void * addr, unsigned long size) +static inline int verify_area(int type, const void * addr, unsigned long size) { return access_ok(type,addr,size) ? 0 : -EFAULT; } @@ -464,7 +464,7 @@ __generic_copy_from_user(void *to, const void *from, unsigned long n) * success. */ -extern inline unsigned long +static inline unsigned long __xtensa_clear_user(void *addr, unsigned long size) { if ( ! memset(addr, 0, size) ) @@ -472,7 +472,7 @@ __xtensa_clear_user(void *addr, unsigned long size) return 0; } -extern inline unsigned long +static inline unsigned long clear_user(void *addr, unsigned long size) { if (access_ok(VERIFY_WRITE, addr, size)) @@ -486,7 +486,7 @@ clear_user(void *addr, unsigned long size) extern long __strncpy_user(char *, const char *, long); #define __strncpy_from_user __strncpy_user -extern inline long +static inline long strncpy_from_user(char *dst, const char *src, long count) { if (access_ok(VERIFY_READ, src, 1)) @@ -502,7 +502,7 @@ strncpy_from_user(char *dst, const char *src, long count) */ extern long __strnlen_user(const char *, long); -extern inline long strnlen_user(const char *str, long len) +static inline long strnlen_user(const char *str, long len) { unsigned long top = __kernel_ok ? ~0UL : TASK_SIZE - 1; diff --git a/include/linux/8250_pci.h b/include/linux/8250_pci.h index 5f3ab21b339b..3209dd46ea7d 100644 --- a/include/linux/8250_pci.h +++ b/include/linux/8250_pci.h @@ -1,2 +1,37 @@ -int pci_siig10x_fn(struct pci_dev *dev, int enable); -int pci_siig20x_fn(struct pci_dev *dev, int enable); +/* + * Definitions for PCI support. + */ +#define FL_BASE_MASK 0x0007 +#define FL_BASE0 0x0000 +#define FL_BASE1 0x0001 +#define FL_BASE2 0x0002 +#define FL_BASE3 0x0003 +#define FL_BASE4 0x0004 +#define FL_GET_BASE(x) (x & FL_BASE_MASK) + +/* Use successive BARs (PCI base address registers), + else use offset into some specified BAR */ +#define FL_BASE_BARS 0x0008 + +/* do not assign an irq */ +#define FL_NOIRQ 0x0080 + +/* Use the Base address register size to cap number of ports */ +#define FL_REGION_SZ_CAP 0x0100 + +struct pciserial_board { + unsigned int flags; + unsigned int num_ports; + unsigned int base_baud; + unsigned int uart_offset; + unsigned int reg_shift; + unsigned int first_offset; +}; + +struct serial_private; + +struct serial_private * +pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board); +void pciserial_remove_ports(struct serial_private *priv); +void pciserial_suspend_ports(struct serial_private *priv); +void pciserial_resume_ports(struct serial_private *priv); diff --git a/include/linux/acpi.h b/include/linux/acpi.h index ef8483673aa3..b46a5205ee7b 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -206,7 +206,10 @@ struct acpi_table_plat_int_src { u8 eid; u8 iosapic_vector; u32 global_irq; - u32 reserved; + struct { + u32 cpei_override_flag:1; + u32 reserved:31; + } plint_flags; } __attribute__ ((packed)); enum acpi_interrupt_id { @@ -450,9 +453,7 @@ int acpi_gsi_to_irq (u32 gsi, unsigned int *irq); * If this matches the last registration, any IRQ resources for gsi * are freed. */ -#ifdef CONFIG_ACPI_DEALLOCATE_IRQ void acpi_unregister_gsi (u32 gsi); -#endif #ifdef CONFIG_ACPI_PCI @@ -475,11 +476,9 @@ struct acpi_prt_list { struct pci_dev; int acpi_pci_irq_enable (struct pci_dev *dev); -void acpi_penalize_isa_irq(int irq); +void acpi_penalize_isa_irq(int irq, int active); -#ifdef CONFIG_ACPI_DEALLOCATE_IRQ void acpi_pci_irq_disable (struct pci_dev *dev); -#endif struct acpi_pci_driver { struct acpi_pci_driver *next; diff --git a/include/linux/ata.h b/include/linux/ata.h index ca5fcadf9981..a5b74efab067 100644 --- a/include/linux/ata.h +++ b/include/linux/ata.h @@ -1,24 +1,29 @@ /* - Copyright 2003-2004 Red Hat, Inc. All rights reserved. - Copyright 2003-2004 Jeff Garzik - - The contents of this file are subject to the Open - Software License version 1.1 that can be found at - http://www.opensource.org/licenses/osl-1.1.txt and is included herein - by reference. - - Alternatively, the contents of this file may be used under the terms - of the GNU General Public License version 2 (the "GPL") as distributed - in the kernel source COPYING file, in which case the provisions of - the GPL are applicable instead of the above. If you wish to allow - the use of your version of this file only under the terms of the - GPL and not to allow others to use your version of this file under - the OSL, indicate your decision by deleting the provisions above and - replace them with the notice and other provisions required by the GPL. - If you do not delete the provisions above, a recipient may use your - version of this file under either the OSL or the GPL. - + * Copyright 2003-2004 Red Hat, Inc. All rights reserved. + * Copyright 2003-2004 Jeff Garzik + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * libata documentation is available via 'make {ps|pdf}docs', + * as Documentation/DocBook/libata.* + * + * Hardware documentation available from http://www.t13.org/ + * */ #ifndef __LINUX_ATA_H__ @@ -108,6 +113,8 @@ enum { /* ATA device commands */ ATA_CMD_CHK_POWER = 0xE5, /* check power mode */ + ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */ + ATA_CMD_IDLE = 0xE3, /* place in idle power mode */ ATA_CMD_EDD = 0x90, /* execute device diagnostic */ ATA_CMD_FLUSH = 0xE7, ATA_CMD_FLUSH_EXT = 0xEA, diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 0881b5cdee3d..19bd8e7e11bf 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -301,6 +301,7 @@ struct blk_queue_tag { struct list_head busy_list; /* fifo list of busy tags */ int busy; /* current depth */ int max_depth; /* what we will send to device */ + int real_max_depth; /* what the array can hold */ atomic_t refcnt; /* map can be shared */ }; diff --git a/include/linux/capability.h b/include/linux/capability.h index 8d139f4acf23..6b4618902d3d 100644 --- a/include/linux/capability.h +++ b/include/linux/capability.h @@ -233,6 +233,7 @@ typedef __u32 kernel_cap_t; /* Allow enabling/disabling tagged queuing on SCSI controllers and sending arbitrary SCSI commands */ /* Allow setting encryption key on loopback filesystem */ +/* Allow setting zone reclaim policy */ #define CAP_SYS_ADMIN 21 diff --git a/include/linux/cpu.h b/include/linux/cpu.h index e8904c0da686..86980c68234a 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -8,7 +8,7 @@ * Basic handling of the devices is done in drivers/base/cpu.c * and system devices are handled in drivers/base/sys.c. * - * CPUs are exported via driverfs in the class/cpu/devices/ + * CPUs are exported via sysfs in the class/cpu/devices/ * directory. * * Per-cpu interfaces can be implemented using a struct device_interface. diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 5e2bcc636a02..3c89df6e7768 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -45,6 +45,7 @@ #define CRYPTO_TFM_MODE_CTR 0x00000008 #define CRYPTO_TFM_REQ_WEAK_KEY 0x00000100 +#define CRYPTO_TFM_REQ_MAY_SLEEP 0x00000200 #define CRYPTO_TFM_RES_WEAK_KEY 0x00100000 #define CRYPTO_TFM_RES_BAD_KEY_LEN 0x00200000 #define CRYPTO_TFM_RES_BAD_KEY_SCHED 0x00400000 diff --git a/include/linux/dccp.h b/include/linux/dccp.h new file mode 100644 index 000000000000..007c290f74d4 --- /dev/null +++ b/include/linux/dccp.h @@ -0,0 +1,456 @@ +#ifndef _LINUX_DCCP_H +#define _LINUX_DCCP_H + +#include <linux/types.h> +#include <asm/byteorder.h> + +/* Structure describing an Internet (DCCP) socket address. */ +struct sockaddr_dccp { + __u16 sdccp_family; /* Address family */ + __u16 sdccp_port; /* Port number */ + __u32 sdccp_addr; /* Internet address */ + __u32 sdccp_service; /* Service */ + /* Pad to size of `struct sockaddr': 16 bytes . */ + __u32 sdccp_pad; +}; + +/** + * struct dccp_hdr - generic part of DCCP packet header + * + * @dccph_sport - Relevant port on the endpoint that sent this packet + * @dccph_dport - Relevant port on the other endpoint + * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words + * @dccph_ccval - Used by the HC-Sender CCID + * @dccph_cscov - Parts of the packet that are covered by the Checksum field + * @dccph_checksum - Internet checksum, depends on dccph_cscov + * @dccph_x - 0 = 24 bit sequence number, 1 = 48 + * @dccph_type - packet type, see DCCP_PKT_ prefixed macros + * @dccph_seq - sequence number high or low order 24 bits, depends on dccph_x + */ +struct dccp_hdr { + __u16 dccph_sport, + dccph_dport; + __u8 dccph_doff; +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 dccph_cscov:4, + dccph_ccval:4; +#elif defined(__BIG_ENDIAN_BITFIELD) + __u8 dccph_ccval:4, + dccph_cscov:4; +#else +#error "Adjust your <asm/byteorder.h> defines" +#endif + __u16 dccph_checksum; +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u32 dccph_x:1, + dccph_type:4, + dccph_reserved:3, + dccph_seq:24; +#elif defined(__BIG_ENDIAN_BITFIELD) + __u32 dccph_reserved:3, + dccph_type:4, + dccph_x:1, + dccph_seq:24; +#else +#error "Adjust your <asm/byteorder.h> defines" +#endif +}; + +/** + * struct dccp_hdr_ext - the low bits of a 48 bit seq packet + * + * @dccph_seq_low - low 24 bits of a 48 bit seq packet + */ +struct dccp_hdr_ext { + __u32 dccph_seq_low; +}; + +/** + * struct dccp_hdr_request - Conection initiation request header + * + * @dccph_req_service - Service to which the client app wants to connect + * @dccph_req_options - list of options (must be a multiple of 32 bits + */ +struct dccp_hdr_request { + __u32 dccph_req_service; +}; +/** + * struct dccp_hdr_ack_bits - acknowledgment bits common to most packets + * + * @dccph_resp_ack_nr_high - 48 bit ack number high order bits, contains GSR + * @dccph_resp_ack_nr_low - 48 bit ack number low order bits, contains GSR + */ +struct dccp_hdr_ack_bits { + __u32 dccph_reserved1:8, + dccph_ack_nr_high:24; + __u32 dccph_ack_nr_low; +}; +/** + * struct dccp_hdr_response - Conection initiation response header + * + * @dccph_resp_ack_nr_high - 48 bit ack number high order bits, contains GSR + * @dccph_resp_ack_nr_low - 48 bit ack number low order bits, contains GSR + * @dccph_resp_service - Echoes the Service Code on a received DCCP-Request + * @dccph_resp_options - list of options (must be a multiple of 32 bits + */ +struct dccp_hdr_response { + struct dccp_hdr_ack_bits dccph_resp_ack; + __u32 dccph_resp_service; +}; + +/** + * struct dccp_hdr_reset - Unconditionally shut down a connection + * + * @dccph_reset_service - Echoes the Service Code on a received DCCP-Request + * @dccph_reset_options - list of options (must be a multiple of 32 bits + */ +struct dccp_hdr_reset { + struct dccp_hdr_ack_bits dccph_reset_ack; + __u8 dccph_reset_code, + dccph_reset_data[3]; +}; + +enum dccp_pkt_type { + DCCP_PKT_REQUEST = 0, + DCCP_PKT_RESPONSE, + DCCP_PKT_DATA, + DCCP_PKT_ACK, + DCCP_PKT_DATAACK, + DCCP_PKT_CLOSEREQ, + DCCP_PKT_CLOSE, + DCCP_PKT_RESET, + DCCP_PKT_SYNC, + DCCP_PKT_SYNCACK, + DCCP_PKT_INVALID, +}; + +#define DCCP_NR_PKT_TYPES DCCP_PKT_INVALID + +static inline unsigned int dccp_packet_hdr_len(const __u8 type) +{ + if (type == DCCP_PKT_DATA) + return 0; + if (type == DCCP_PKT_DATAACK || + type == DCCP_PKT_ACK || + type == DCCP_PKT_SYNC || + type == DCCP_PKT_SYNCACK || + type == DCCP_PKT_CLOSE || + type == DCCP_PKT_CLOSEREQ) + return sizeof(struct dccp_hdr_ack_bits); + if (type == DCCP_PKT_REQUEST) + return sizeof(struct dccp_hdr_request); + if (type == DCCP_PKT_RESPONSE) + return sizeof(struct dccp_hdr_response); + return sizeof(struct dccp_hdr_reset); +} +enum dccp_reset_codes { + DCCP_RESET_CODE_UNSPECIFIED = 0, + DCCP_RESET_CODE_CLOSED, + DCCP_RESET_CODE_ABORTED, + DCCP_RESET_CODE_NO_CONNECTION, + DCCP_RESET_CODE_PACKET_ERROR, + DCCP_RESET_CODE_OPTION_ERROR, + DCCP_RESET_CODE_MANDATORY_ERROR, + DCCP_RESET_CODE_CONNECTION_REFUSED, + DCCP_RESET_CODE_BAD_SERVICE_CODE, + DCCP_RESET_CODE_TOO_BUSY, + DCCP_RESET_CODE_BAD_INIT_COOKIE, + DCCP_RESET_CODE_AGGRESSION_PENALTY, +}; + +/* DCCP options */ +enum { + DCCPO_PADDING = 0, + DCCPO_MANDATORY = 1, + DCCPO_MIN_RESERVED = 3, + DCCPO_MAX_RESERVED = 31, + DCCPO_NDP_COUNT = 37, + DCCPO_ACK_VECTOR_0 = 38, + DCCPO_ACK_VECTOR_1 = 39, + DCCPO_TIMESTAMP = 41, + DCCPO_TIMESTAMP_ECHO = 42, + DCCPO_ELAPSED_TIME = 43, + DCCPO_MAX = 45, + DCCPO_MIN_CCID_SPECIFIC = 128, + DCCPO_MAX_CCID_SPECIFIC = 255, +}; + +/* DCCP features */ +enum { + DCCPF_RESERVED = 0, + DCCPF_SEQUENCE_WINDOW = 3, + DCCPF_SEND_ACK_VECTOR = 6, + DCCPF_SEND_NDP_COUNT = 7, + /* 10-127 reserved */ + DCCPF_MIN_CCID_SPECIFIC = 128, + DCCPF_MAX_CCID_SPECIFIC = 255, +}; + +/* DCCP socket options */ +#define DCCP_SOCKOPT_PACKET_SIZE 1 + +#ifdef __KERNEL__ + +#include <linux/in.h> +#include <linux/list.h> +#include <linux/uio.h> +#include <linux/workqueue.h> + +#include <net/inet_connection_sock.h> +#include <net/inet_timewait_sock.h> +#include <net/sock.h> +#include <net/tcp_states.h> +#include <net/tcp.h> + +enum dccp_state { + DCCP_OPEN = TCP_ESTABLISHED, + DCCP_REQUESTING = TCP_SYN_SENT, + DCCP_PARTOPEN = TCP_FIN_WAIT1, /* FIXME: + This mapping is horrible, but TCP has + no matching state for DCCP_PARTOPEN, + as TCP_SYN_RECV is already used by + DCCP_RESPOND, why don't stop using TCP + mapping of states? OK, now we don't use + sk_stream_sendmsg anymore, so doesn't + seem to exist any reason for us to + do the TCP mapping here */ + DCCP_LISTEN = TCP_LISTEN, + DCCP_RESPOND = TCP_SYN_RECV, + DCCP_CLOSING = TCP_CLOSING, + DCCP_TIME_WAIT = TCP_TIME_WAIT, + DCCP_CLOSED = TCP_CLOSE, + DCCP_MAX_STATES = TCP_MAX_STATES, +}; + +#define DCCP_STATE_MASK 0xf +#define DCCP_ACTION_FIN (1<<7) + +enum { + DCCPF_OPEN = TCPF_ESTABLISHED, + DCCPF_REQUESTING = TCPF_SYN_SENT, + DCCPF_PARTOPEN = TCPF_FIN_WAIT1, + DCCPF_LISTEN = TCPF_LISTEN, + DCCPF_RESPOND = TCPF_SYN_RECV, + DCCPF_CLOSING = TCPF_CLOSING, + DCCPF_TIME_WAIT = TCPF_TIME_WAIT, + DCCPF_CLOSED = TCPF_CLOSE, +}; + +static inline struct dccp_hdr *dccp_hdr(const struct sk_buff *skb) +{ + return (struct dccp_hdr *)skb->h.raw; +} + +static inline struct dccp_hdr_ext *dccp_hdrx(const struct sk_buff *skb) +{ + return (struct dccp_hdr_ext *)(skb->h.raw + sizeof(struct dccp_hdr)); +} + +static inline unsigned int __dccp_basic_hdr_len(const struct dccp_hdr *dh) +{ + return sizeof(*dh) + (dh->dccph_x ? sizeof(struct dccp_hdr_ext) : 0); +} + +static inline unsigned int dccp_basic_hdr_len(const struct sk_buff *skb) +{ + const struct dccp_hdr *dh = dccp_hdr(skb); + return __dccp_basic_hdr_len(dh); +} + +static inline __u64 dccp_hdr_seq(const struct sk_buff *skb) +{ + const struct dccp_hdr *dh = dccp_hdr(skb); +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u64 seq_nr = ntohl(dh->dccph_seq << 8); +#elif defined(__BIG_ENDIAN_BITFIELD) + __u64 seq_nr = ntohl(dh->dccph_seq); +#else +#error "Adjust your <asm/byteorder.h> defines" +#endif + + if (dh->dccph_x != 0) + seq_nr = (seq_nr << 32) + ntohl(dccp_hdrx(skb)->dccph_seq_low); + + return seq_nr; +} + +static inline struct dccp_hdr_request *dccp_hdr_request(struct sk_buff *skb) +{ + return (struct dccp_hdr_request *)(skb->h.raw + dccp_basic_hdr_len(skb)); +} + +static inline struct dccp_hdr_ack_bits *dccp_hdr_ack_bits(const struct sk_buff *skb) +{ + return (struct dccp_hdr_ack_bits *)(skb->h.raw + dccp_basic_hdr_len(skb)); +} + +static inline u64 dccp_hdr_ack_seq(const struct sk_buff *skb) +{ + const struct dccp_hdr_ack_bits *dhack = dccp_hdr_ack_bits(skb); +#if defined(__LITTLE_ENDIAN_BITFIELD) + return (((u64)ntohl(dhack->dccph_ack_nr_high << 8)) << 32) + ntohl(dhack->dccph_ack_nr_low); +#elif defined(__BIG_ENDIAN_BITFIELD) + return (((u64)ntohl(dhack->dccph_ack_nr_high)) << 32) + ntohl(dhack->dccph_ack_nr_low); +#else +#error "Adjust your <asm/byteorder.h> defines" +#endif +} + +static inline struct dccp_hdr_response *dccp_hdr_response(struct sk_buff *skb) +{ + return (struct dccp_hdr_response *)(skb->h.raw + dccp_basic_hdr_len(skb)); +} + +static inline struct dccp_hdr_reset *dccp_hdr_reset(struct sk_buff *skb) +{ + return (struct dccp_hdr_reset *)(skb->h.raw + dccp_basic_hdr_len(skb)); +} + +static inline unsigned int __dccp_hdr_len(const struct dccp_hdr *dh) +{ + return __dccp_basic_hdr_len(dh) + + dccp_packet_hdr_len(dh->dccph_type); +} + +static inline unsigned int dccp_hdr_len(const struct sk_buff *skb) +{ + return __dccp_hdr_len(dccp_hdr(skb)); +} + + +/* initial values for each feature */ +#define DCCPF_INITIAL_SEQUENCE_WINDOW 100 +/* FIXME: for now we're using CCID 3 (TFRC) */ +#define DCCPF_INITIAL_CCID 3 +#define DCCPF_INITIAL_SEND_ACK_VECTOR 0 +/* FIXME: for now we're default to 1 but it should really be 0 */ +#define DCCPF_INITIAL_SEND_NDP_COUNT 1 + +#define DCCP_NDP_LIMIT 0xFFFFFF + +/** + * struct dccp_options - option values for a DCCP connection + * @dccpo_sequence_window - Sequence Window Feature (section 7.5.2) + * @dccpo_ccid - Congestion Control Id (CCID) (section 10) + * @dccpo_send_ack_vector - Send Ack Vector Feature (section 11.5) + * @dccpo_send_ndp_count - Send NDP Count Feature (7.7.2) + */ +struct dccp_options { + __u64 dccpo_sequence_window; + __u8 dccpo_ccid; + __u8 dccpo_send_ack_vector; + __u8 dccpo_send_ndp_count; +}; + +extern void __dccp_options_init(struct dccp_options *dccpo); +extern void dccp_options_init(struct dccp_options *dccpo); +extern int dccp_parse_options(struct sock *sk, struct sk_buff *skb); + +struct dccp_request_sock { + struct inet_request_sock dreq_inet_rsk; + __u64 dreq_iss; + __u64 dreq_isr; + __u32 dreq_service; +}; + +static inline struct dccp_request_sock *dccp_rsk(const struct request_sock *req) +{ + return (struct dccp_request_sock *)req; +} + +extern struct inet_timewait_death_row dccp_death_row; + +/* Read about the ECN nonce to see why it is 253 */ +#define DCCP_MAX_ACK_VECTOR_LEN 253 + +struct dccp_options_received { + u32 dccpor_ndp:24, + dccpor_ack_vector_len:8; + u32 dccpor_ack_vector_idx:10; + /* 22 bits hole, try to pack */ + u32 dccpor_timestamp; + u32 dccpor_timestamp_echo; + u32 dccpor_elapsed_time; +}; + +struct ccid; + +enum dccp_role { + DCCP_ROLE_UNDEFINED, + DCCP_ROLE_LISTEN, + DCCP_ROLE_CLIENT, + DCCP_ROLE_SERVER, +}; + +/** + * struct dccp_sock - DCCP socket state + * + * @dccps_swl - sequence number window low + * @dccps_swh - sequence number window high + * @dccps_awl - acknowledgement number window low + * @dccps_awh - acknowledgement number window high + * @dccps_iss - initial sequence number sent + * @dccps_isr - initial sequence number received + * @dccps_osr - first OPEN sequence number received + * @dccps_gss - greatest sequence number sent + * @dccps_gsr - greatest valid sequence number received + * @dccps_gar - greatest valid ack number received on a non-Sync; initialized to %dccps_iss + * @dccps_timestamp_time - time of latest TIMESTAMP option + * @dccps_timestamp_echo - latest timestamp received on a TIMESTAMP option + * @dccps_ext_header_len - network protocol overhead (IP/IPv6 options) + * @dccps_pmtu_cookie - Last pmtu seen by socket + * @dccps_packet_size - Set thru setsockopt + * @dccps_role - Role of this sock, one of %dccp_role + * @dccps_ndp_count - number of Non Data Packets since last data packet + * @dccps_hc_rx_ackpkts - receiver half connection acked packets + */ +struct dccp_sock { + /* inet_connection_sock has to be the first member of dccp_sock */ + struct inet_connection_sock dccps_inet_connection; + __u64 dccps_swl; + __u64 dccps_swh; + __u64 dccps_awl; + __u64 dccps_awh; + __u64 dccps_iss; + __u64 dccps_isr; + __u64 dccps_osr; + __u64 dccps_gss; + __u64 dccps_gsr; + __u64 dccps_gar; + unsigned long dccps_service; + struct timeval dccps_timestamp_time; + __u32 dccps_timestamp_echo; + __u32 dccps_packet_size; + unsigned long dccps_ndp_count; + __u16 dccps_ext_header_len; + __u32 dccps_pmtu_cookie; + __u32 dccps_mss_cache; + struct dccp_options dccps_options; + struct dccp_ackpkts *dccps_hc_rx_ackpkts; + void *dccps_hc_rx_ccid_private; + void *dccps_hc_tx_ccid_private; + struct ccid *dccps_hc_rx_ccid; + struct ccid *dccps_hc_tx_ccid; + struct dccp_options_received dccps_options_received; + enum dccp_role dccps_role:2; +}; + +static inline struct dccp_sock *dccp_sk(const struct sock *sk) +{ + return (struct dccp_sock *)sk; +} + +static inline const char *dccp_role(const struct sock *sk) +{ + switch (dccp_sk(sk)->dccps_role) { + case DCCP_ROLE_UNDEFINED: return "undefined"; + case DCCP_ROLE_LISTEN: return "listen"; + case DCCP_ROLE_SERVER: return "server"; + case DCCP_ROLE_CLIENT: return "client"; + } + return NULL; +} + +#endif /* __KERNEL__ */ + +#endif /* _LINUX_DCCP_H */ diff --git a/include/linux/dcookies.h b/include/linux/dcookies.h index c28050136164..1d68428c925d 100644 --- a/include/linux/dcookies.h +++ b/include/linux/dcookies.h @@ -48,12 +48,12 @@ int get_dcookie(struct dentry * dentry, struct vfsmount * vfsmnt, #else -struct dcookie_user * dcookie_register(void) +static inline struct dcookie_user * dcookie_register(void) { return NULL; } -void dcookie_unregister(struct dcookie_user * user) +static inline void dcookie_unregister(struct dcookie_user * user) { return; } diff --git a/include/linux/device.h b/include/linux/device.h index f378c846e6d5..06e5d42f2c7b 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -284,8 +284,10 @@ struct device { struct device_driver *driver; /* which driver has allocated this device */ void *driver_data; /* data private to the driver */ - void *platform_data; /* Platform specific data (e.g. ACPI, - BIOS data relevant to device) */ + void *platform_data; /* Platform specific data, device + core doesn't touch it */ + void *firmware_data; /* Firmware specific data (e.g. ACPI, + BIOS data),reserved for device core*/ struct dev_pm_info power; u64 *dma_mask; /* dma mask (if dma'able device) */ diff --git a/include/linux/efi.h b/include/linux/efi.h index 73781ec165b4..c7c5dd316182 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -91,11 +91,6 @@ typedef struct { #define EFI_PAGE_SHIFT 12 -/* - * For current x86 implementations of EFI, there is - * additional padding in the mem descriptors. This is not - * the case in ia64. Need to have this fixed in the f/w. - */ typedef struct { u32 type; u32 pad; @@ -103,9 +98,6 @@ typedef struct { u64 virt_addr; u64 num_pages; u64 attribute; -#if defined (__i386__) - u64 pad1; -#endif } efi_memory_desc_t; typedef int (*efi_freemem_callback_t) (unsigned long start, unsigned long end, void *arg); @@ -240,10 +232,12 @@ typedef struct { } efi_system_table_t; struct efi_memory_map { - efi_memory_desc_t *phys_map; - efi_memory_desc_t *map; + void *phys_map; + void *map; + void *map_end; int nr_map; unsigned long desc_version; + unsigned long desc_size; }; /* diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index cf3847edc50f..4522c7186bf3 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -33,7 +33,7 @@ extern int eth_header(struct sk_buff *skb, struct net_device *dev, unsigned short type, void *daddr, void *saddr, unsigned len); extern int eth_rebuild_header(struct sk_buff *skb); -extern unsigned short eth_type_trans(struct sk_buff *skb, struct net_device *dev); +extern __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); extern void eth_header_cache_update(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr); extern int eth_header_cache(struct neighbour *neigh, @@ -69,6 +69,12 @@ static inline int is_multicast_ether_addr(const u8 *addr) return ((addr[0] != 0xff) && (0x01 & addr[0])); } +static inline int is_broadcast_ether_addr(const u8 *addr) +{ + return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && + (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); +} + /** * is_valid_ether_addr - Determine if the given Ethernet address is valid * @addr: Pointer to a six-byte array containing the Ethernet address diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index a0ab26aab450..ed1440ea4c91 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -250,6 +250,12 @@ struct ethtool_stats { u64 data[0]; }; +struct ethtool_perm_addr { + u32 cmd; /* ETHTOOL_GPERMADDR */ + u32 size; + u8 data[0]; +}; + struct net_device; /* Some generic methods drivers may use in their ethtool_ops */ @@ -261,6 +267,8 @@ u32 ethtool_op_get_sg(struct net_device *dev); int ethtool_op_set_sg(struct net_device *dev, u32 data); u32 ethtool_op_get_tso(struct net_device *dev); int ethtool_op_set_tso(struct net_device *dev, u32 data); +int ethtool_op_get_perm_addr(struct net_device *dev, + struct ethtool_perm_addr *addr, u8 *data); /** * ðtool_ops - Alter and report network device settings @@ -294,7 +302,8 @@ int ethtool_op_set_tso(struct net_device *dev, u32 data); * get_strings: Return a set of strings that describe the requested objects * phys_id: Identify the device * get_stats: Return statistics about the device - * + * get_perm_addr: Gets the permanent hardware address + * * Description: * * get_settings: @@ -352,6 +361,7 @@ struct ethtool_ops { int (*phys_id)(struct net_device *, u32); int (*get_stats_count)(struct net_device *); void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *); + int (*get_perm_addr)(struct net_device *, struct ethtool_perm_addr *, u8 *); int (*begin)(struct net_device *); void (*complete)(struct net_device *); }; @@ -389,6 +399,7 @@ struct ethtool_ops { #define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ #define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ #define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ +#define ETHTOOL_GPERMADDR 0x00000020 /* Get permanent hardware address */ /* compatibility with older code */ #define SPARC_ETH_GSET ETHTOOL_GSET @@ -408,6 +419,8 @@ struct ethtool_ops { #define SUPPORTED_FIBRE (1 << 10) #define SUPPORTED_BNC (1 << 11) #define SUPPORTED_10000baseT_Full (1 << 12) +#define SUPPORTED_Pause (1 << 13) +#define SUPPORTED_Asym_Pause (1 << 14) /* Indicates what features are advertised by the interface. */ #define ADVERTISED_10baseT_Half (1 << 0) @@ -423,6 +436,8 @@ struct ethtool_ops { #define ADVERTISED_FIBRE (1 << 10) #define ADVERTISED_BNC (1 << 11) #define ADVERTISED_10000baseT_Full (1 << 12) +#define ADVERTISED_Pause (1 << 13) +#define ADVERTISED_Asym_Pause (1 << 14) /* The following are all involved in forcing a particular link * mode for the device for setting things. When getting the diff --git a/include/linux/ext3_fs.h b/include/linux/ext3_fs.h index 4b6e1ab216a5..c16662836c58 100644 --- a/include/linux/ext3_fs.h +++ b/include/linux/ext3_fs.h @@ -239,6 +239,20 @@ struct ext3_new_group_data { #define EXT3_IOC_SETRSVSZ _IOW('f', 6, long) /* + * Mount options + */ +struct ext3_mount_options { + unsigned long s_mount_opt; + uid_t s_resuid; + gid_t s_resgid; + unsigned long s_commit_interval; +#ifdef CONFIG_QUOTA + int s_jquota_fmt; + char *s_qf_names[MAXQUOTAS]; +#endif +}; + +/* * Structure of an inode on the disk */ struct ext3_inode { diff --git a/include/linux/fadvise.h b/include/linux/fadvise.h index 6fc656dfb93d..e8e747139b9a 100644 --- a/include/linux/fadvise.h +++ b/include/linux/fadvise.h @@ -5,7 +5,17 @@ #define POSIX_FADV_RANDOM 1 /* Expect random page references. */ #define POSIX_FADV_SEQUENTIAL 2 /* Expect sequential page references. */ #define POSIX_FADV_WILLNEED 3 /* Will need these pages. */ + +/* + * The advise values for POSIX_FADV_DONTNEED and POSIX_ADV_NOREUSE + * for s390-64 differ from the values for the rest of the world. + */ +#if defined(__s390x__) +#define POSIX_FADV_DONTNEED 6 /* Don't need these pages. */ +#define POSIX_FADV_NOREUSE 7 /* Data will be accessed once. */ +#else #define POSIX_FADV_DONTNEED 4 /* Don't need these pages. */ #define POSIX_FADV_NOREUSE 5 /* Data will be accessed once. */ +#endif #endif /* FADVISE_H_INCLUDED */ diff --git a/include/linux/fddidevice.h b/include/linux/fddidevice.h index 002f6367697d..e61e42dfd317 100644 --- a/include/linux/fddidevice.h +++ b/include/linux/fddidevice.h @@ -25,7 +25,7 @@ #include <linux/if_fddi.h> #ifdef __KERNEL__ -extern unsigned short fddi_type_trans(struct sk_buff *skb, +extern __be16 fddi_type_trans(struct sk_buff *skb, struct net_device *dev); extern struct net_device *alloc_fddidev(int sizeof_priv); #endif diff --git a/include/linux/fs.h b/include/linux/fs.h index 302ec20838ca..67e6732d4fdc 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -474,6 +474,11 @@ struct inode { struct dnotify_struct *i_dnotify; /* for directory notifications */ #endif +#ifdef CONFIG_INOTIFY + struct list_head inotify_watches; /* watches on this inode */ + struct semaphore inotify_sem; /* protects the watches list */ +#endif + unsigned long i_state; unsigned long dirtied_when; /* jiffies of first dirtying */ @@ -692,11 +697,13 @@ extern struct list_head file_lock_list; #include <linux/fcntl.h> extern int fcntl_getlk(struct file *, struct flock __user *); -extern int fcntl_setlk(struct file *, unsigned int, struct flock __user *); +extern int fcntl_setlk(unsigned int, struct file *, unsigned int, + struct flock __user *); #if BITS_PER_LONG == 32 extern int fcntl_getlk64(struct file *, struct flock64 __user *); -extern int fcntl_setlk64(struct file *, unsigned int, struct flock64 __user *); +extern int fcntl_setlk64(unsigned int, struct file *, unsigned int, + struct flock64 __user *); #endif extern void send_sigio(struct fown_struct *fown, int fd, int band); @@ -986,8 +993,8 @@ struct inode_operations { int (*rename) (struct inode *, struct dentry *, struct inode *, struct dentry *); int (*readlink) (struct dentry *, char __user *,int); - int (*follow_link) (struct dentry *, struct nameidata *); - void (*put_link) (struct dentry *, struct nameidata *); + void * (*follow_link) (struct dentry *, struct nameidata *); + void (*put_link) (struct dentry *, struct nameidata *, void *); void (*truncate) (struct inode *); int (*permission) (struct inode *, int, struct nameidata *); int (*setattr) (struct dentry *, struct iattr *); @@ -1393,7 +1400,6 @@ extern void emergency_remount(void); extern int do_remount_sb(struct super_block *sb, int flags, void *data, int force); extern sector_t bmap(struct inode *, sector_t); -extern int setattr_mask(unsigned int); extern int notify_change(struct dentry *, struct iattr *); extern int permission(struct inode *, int, struct nameidata *); extern int generic_permission(struct inode *, int, @@ -1437,6 +1443,9 @@ extern int inode_needs_sync(struct inode *inode); extern void generic_delete_inode(struct inode *inode); extern void generic_drop_inode(struct inode *inode); +extern struct inode *ilookup5_nowait(struct super_block *sb, + unsigned long hashval, int (*test)(struct inode *, void *), + void *data); extern struct inode *ilookup5(struct super_block *sb, unsigned long hashval, int (*test)(struct inode *, void *), void *data); extern struct inode *ilookup(struct super_block *sb, unsigned long ino); @@ -1593,8 +1602,8 @@ extern struct file_operations generic_ro_fops; extern int vfs_readlink(struct dentry *, char __user *, int, const char *); extern int vfs_follow_link(struct nameidata *, const char *); extern int page_readlink(struct dentry *, char __user *, int); -extern int page_follow_link_light(struct dentry *, struct nameidata *); -extern void page_put_link(struct dentry *, struct nameidata *); +extern void *page_follow_link_light(struct dentry *, struct nameidata *); +extern void page_put_link(struct dentry *, struct nameidata *, void *); extern int page_symlink(struct inode *inode, const char *symname, int len); extern struct inode_operations page_symlink_inode_operations; extern int generic_readlink(struct dentry *, char __user *, int); diff --git a/include/linux/fsnotify.h b/include/linux/fsnotify.h new file mode 100644 index 000000000000..03b8e7932b83 --- /dev/null +++ b/include/linux/fsnotify.h @@ -0,0 +1,251 @@ +#ifndef _LINUX_FS_NOTIFY_H +#define _LINUX_FS_NOTIFY_H + +/* + * include/linux/fsnotify.h - generic hooks for filesystem notification, to + * reduce in-source duplication from both dnotify and inotify. + * + * We don't compile any of this away in some complicated menagerie of ifdefs. + * Instead, we rely on the code inside to optimize away as needed. + * + * (C) Copyright 2005 Robert Love + */ + +#ifdef __KERNEL__ + +#include <linux/dnotify.h> +#include <linux/inotify.h> + +/* + * fsnotify_move - file old_name at old_dir was moved to new_name at new_dir + */ +static inline void fsnotify_move(struct inode *old_dir, struct inode *new_dir, + const char *old_name, const char *new_name, + int isdir, struct inode *target, struct inode *source) +{ + u32 cookie = inotify_get_cookie(); + + if (old_dir == new_dir) + inode_dir_notify(old_dir, DN_RENAME); + else { + inode_dir_notify(old_dir, DN_DELETE); + inode_dir_notify(new_dir, DN_CREATE); + } + + if (isdir) + isdir = IN_ISDIR; + inotify_inode_queue_event(old_dir, IN_MOVED_FROM|isdir,cookie,old_name); + inotify_inode_queue_event(new_dir, IN_MOVED_TO|isdir, cookie, new_name); + + if (target) { + inotify_inode_queue_event(target, IN_DELETE_SELF, 0, NULL); + inotify_inode_is_dead(target); + } + + if (source) { + inotify_inode_queue_event(source, IN_MOVE_SELF, 0, NULL); + } +} + +/* + * fsnotify_nameremove - a filename was removed from a directory + */ +static inline void fsnotify_nameremove(struct dentry *dentry, int isdir) +{ + if (isdir) + isdir = IN_ISDIR; + dnotify_parent(dentry, DN_DELETE); + inotify_dentry_parent_queue_event(dentry, IN_DELETE|isdir, 0, dentry->d_name.name); +} + +/* + * fsnotify_inoderemove - an inode is going away + */ +static inline void fsnotify_inoderemove(struct inode *inode) +{ + inotify_inode_queue_event(inode, IN_DELETE_SELF, 0, NULL); + inotify_inode_is_dead(inode); +} + +/* + * fsnotify_create - 'name' was linked in + */ +static inline void fsnotify_create(struct inode *inode, const char *name) +{ + inode_dir_notify(inode, DN_CREATE); + inotify_inode_queue_event(inode, IN_CREATE, 0, name); +} + +/* + * fsnotify_mkdir - directory 'name' was created + */ +static inline void fsnotify_mkdir(struct inode *inode, const char *name) +{ + inode_dir_notify(inode, DN_CREATE); + inotify_inode_queue_event(inode, IN_CREATE | IN_ISDIR, 0, name); +} + +/* + * fsnotify_access - file was read + */ +static inline void fsnotify_access(struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + u32 mask = IN_ACCESS; + + if (S_ISDIR(inode->i_mode)) + mask |= IN_ISDIR; + + dnotify_parent(dentry, DN_ACCESS); + inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name); + inotify_inode_queue_event(inode, mask, 0, NULL); +} + +/* + * fsnotify_modify - file was modified + */ +static inline void fsnotify_modify(struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + u32 mask = IN_MODIFY; + + if (S_ISDIR(inode->i_mode)) + mask |= IN_ISDIR; + + dnotify_parent(dentry, DN_MODIFY); + inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name); + inotify_inode_queue_event(inode, mask, 0, NULL); +} + +/* + * fsnotify_open - file was opened + */ +static inline void fsnotify_open(struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + u32 mask = IN_OPEN; + + if (S_ISDIR(inode->i_mode)) + mask |= IN_ISDIR; + + inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name); + inotify_inode_queue_event(inode, mask, 0, NULL); +} + +/* + * fsnotify_close - file was closed + */ +static inline void fsnotify_close(struct file *file) +{ + struct dentry *dentry = file->f_dentry; + struct inode *inode = dentry->d_inode; + const char *name = dentry->d_name.name; + mode_t mode = file->f_mode; + u32 mask = (mode & FMODE_WRITE) ? IN_CLOSE_WRITE : IN_CLOSE_NOWRITE; + + if (S_ISDIR(inode->i_mode)) + mask |= IN_ISDIR; + + inotify_dentry_parent_queue_event(dentry, mask, 0, name); + inotify_inode_queue_event(inode, mask, 0, NULL); +} + +/* + * fsnotify_xattr - extended attributes were changed + */ +static inline void fsnotify_xattr(struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + u32 mask = IN_ATTRIB; + + if (S_ISDIR(inode->i_mode)) + mask |= IN_ISDIR; + + inotify_dentry_parent_queue_event(dentry, mask, 0, dentry->d_name.name); + inotify_inode_queue_event(inode, mask, 0, NULL); +} + +/* + * fsnotify_change - notify_change event. file was modified and/or metadata + * was changed. + */ +static inline void fsnotify_change(struct dentry *dentry, unsigned int ia_valid) +{ + struct inode *inode = dentry->d_inode; + int dn_mask = 0; + u32 in_mask = 0; + + if (ia_valid & ATTR_UID) { + in_mask |= IN_ATTRIB; + dn_mask |= DN_ATTRIB; + } + if (ia_valid & ATTR_GID) { + in_mask |= IN_ATTRIB; + dn_mask |= DN_ATTRIB; + } + if (ia_valid & ATTR_SIZE) { + in_mask |= IN_MODIFY; + dn_mask |= DN_MODIFY; + } + /* both times implies a utime(s) call */ + if ((ia_valid & (ATTR_ATIME | ATTR_MTIME)) == (ATTR_ATIME | ATTR_MTIME)) + { + in_mask |= IN_ATTRIB; + dn_mask |= DN_ATTRIB; + } else if (ia_valid & ATTR_ATIME) { + in_mask |= IN_ACCESS; + dn_mask |= DN_ACCESS; + } else if (ia_valid & ATTR_MTIME) { + in_mask |= IN_MODIFY; + dn_mask |= DN_MODIFY; + } + if (ia_valid & ATTR_MODE) { + in_mask |= IN_ATTRIB; + dn_mask |= DN_ATTRIB; + } + + if (dn_mask) + dnotify_parent(dentry, dn_mask); + if (in_mask) { + if (S_ISDIR(inode->i_mode)) + in_mask |= IN_ISDIR; + inotify_inode_queue_event(inode, in_mask, 0, NULL); + inotify_dentry_parent_queue_event(dentry, in_mask, 0, + dentry->d_name.name); + } +} + +#ifdef CONFIG_INOTIFY /* inotify helpers */ + +/* + * fsnotify_oldname_init - save off the old filename before we change it + */ +static inline const char *fsnotify_oldname_init(const char *name) +{ + return kstrdup(name, GFP_KERNEL); +} + +/* + * fsnotify_oldname_free - free the name we got from fsnotify_oldname_init + */ +static inline void fsnotify_oldname_free(const char *old_name) +{ + kfree(old_name); +} + +#else /* CONFIG_INOTIFY */ + +static inline const char *fsnotify_oldname_init(const char *name) +{ + return NULL; +} + +static inline void fsnotify_oldname_free(const char *old_name) +{ +} + +#endif /* ! CONFIG_INOTIFY */ + +#endif /* __KERNEL__ */ + +#endif /* _LINUX_FS_NOTIFY_H */ diff --git a/include/linux/ftape.h b/include/linux/ftape.h index c6b38d5b9186..72faeec9f6e1 100644 --- a/include/linux/ftape.h +++ b/include/linux/ftape.h @@ -165,7 +165,7 @@ typedef union { # undef CONFIG_FT_FDC_DMA # define CONFIG_FT_FDC_DMA 2 # endif -#elif CONFIG_FT_ALT_FDC == 1 /* CONFIG_FT_MACH2 */ +#elif defined(CONFIG_FT_ALT_FDC) /* CONFIG_FT_MACH2 */ # if CONFIG_FT_FDC_BASE == 0 # undef CONFIG_FT_FDC_BASE # define CONFIG_FT_FDC_BASE 0x370 diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h index 8336dba18971..5912874ca83c 100644 --- a/include/linux/hardirq.h +++ b/include/linux/hardirq.h @@ -2,6 +2,7 @@ #define LINUX_HARDIRQ_H #include <linux/config.h> +#include <linux/preempt.h> #include <linux/smp_lock.h> #include <asm/hardirq.h> #include <asm/system.h> diff --git a/include/linux/hdlc.h b/include/linux/hdlc.h index ed2927ef1ff7..df695e9ae327 100644 --- a/include/linux/hdlc.h +++ b/include/linux/hdlc.h @@ -242,8 +242,8 @@ static __inline__ struct net_device_stats *hdlc_stats(struct net_device *dev) } -static __inline__ unsigned short hdlc_type_trans(struct sk_buff *skb, - struct net_device *dev) +static __inline__ __be16 hdlc_type_trans(struct sk_buff *skb, + struct net_device *dev) { hdlc_device *hdlc = dev_to_hdlc(dev); diff --git a/include/linux/hippidevice.h b/include/linux/hippidevice.h index 9debe6bbe5f0..bab303dafd6e 100644 --- a/include/linux/hippidevice.h +++ b/include/linux/hippidevice.h @@ -26,8 +26,12 @@ #include <linux/if_hippi.h> #ifdef __KERNEL__ -extern unsigned short hippi_type_trans(struct sk_buff *skb, - struct net_device *dev); + +struct hippi_cb { + __u32 ifield; +}; + +extern __be16 hippi_type_trans(struct sk_buff *skb, struct net_device *dev); extern struct net_device *alloc_hippi_dev(int sizeof_priv); #endif diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index f529d1442815..e670b0d13fe0 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -70,12 +70,6 @@ pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, void hugetlb_prefault_arch_hook(struct mm_struct *mm); #endif -#ifndef ARCH_HAS_HUGETLB_CLEAN_STALE_PGTABLE -#define hugetlb_clean_stale_pgtable(pte) BUG() -#else -void hugetlb_clean_stale_pgtable(pte_t *pte); -#endif - #else /* !CONFIG_HUGETLB_PAGE */ static inline int is_vm_hugetlb_page(struct vm_area_struct *vma) diff --git a/include/linux/hwmon-sysfs.h b/include/linux/hwmon-sysfs.h index 1b5018a965f5..7eb4004b3601 100644 --- a/include/linux/hwmon-sysfs.h +++ b/include/linux/hwmon-sysfs.h @@ -33,4 +33,19 @@ struct sensor_device_attribute sensor_dev_attr_##_name = { \ .index = _index, \ } +struct sensor_device_attribute_2 { + struct device_attribute dev_attr; + u8 index; + u8 nr; +}; +#define to_sensor_dev_attr_2(_dev_attr) \ + container_of(_dev_attr, struct sensor_device_attribute_2, dev_attr) + +#define SENSOR_DEVICE_ATTR_2(_name,_mode,_show,_store,_nr,_index) \ +struct sensor_device_attribute_2 sensor_dev_attr_##_name = { \ + .dev_attr = __ATTR(_name,_mode,_show,_store), \ + .index = _index, \ + .nr = _nr, \ +} + #endif /* _LINUX_HWMON_SYSFS_H */ diff --git a/include/linux/hwmon-vid.h b/include/linux/hwmon-vid.h new file mode 100644 index 000000000000..cd4b7a042b86 --- /dev/null +++ b/include/linux/hwmon-vid.h @@ -0,0 +1,45 @@ +/* + hwmon-vid.h - VID/VRM/VRD voltage conversions + + Originally part of lm_sensors + Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com> + With assistance from Trent Piepho <xyzzy@speakeasy.org> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef _LINUX_HWMON_VID_H +#define _LINUX_HWMON_VID_H + +int vid_from_reg(int val, int vrm); +int vid_which_vrm(void); + +/* vrm is the VRM/VRD document version multiplied by 10. + val is in mV to avoid floating point in the kernel. + Returned value is the 4-, 5- or 6-bit VID code. + Note that only VRM 9.x is supported for now. */ +static inline int vid_to_reg(int val, int vrm) +{ + switch (vrm) { + case 91: /* VRM 9.1 */ + case 90: /* VRM 9.0 */ + return ((val >= 1100) && (val <= 1850) ? + ((18499 - val * 10) / 25 + 5) / 10 : -1); + default: + return -1; + } +} + +#endif /* _LINUX_HWMON_VID_H */ diff --git a/include/linux/hwmon.h b/include/linux/hwmon.h new file mode 100644 index 000000000000..0efd994c37f1 --- /dev/null +++ b/include/linux/hwmon.h @@ -0,0 +1,35 @@ +/* + hwmon.h - part of lm_sensors, Linux kernel modules for hardware monitoring + + This file declares helper functions for the sysfs class "hwmon", + for use by sensors drivers. + + Copyright (C) 2005 Mark M. Hoffman <mhoffman@lightlink.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License. +*/ + +#ifndef _HWMON_H_ +#define _HWMON_H_ + +#include <linux/device.h> + +struct class_device *hwmon_device_register(struct device *dev); + +void hwmon_device_unregister(struct class_device *cdev); + +/* Scale user input to sensible values */ +static inline int SENSORS_LIMIT(long value, long low, long high) +{ + if (value < low) + return low; + else if (value > high) + return high; + else + return value; +} + +#endif + diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index 33f08258f22b..44f30876a1c9 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@ -1,6 +1,6 @@ /* ------------------------------------------------------------------------- */ /* */ -/* i2c.h - definitions for the i2c-bus interface */ +/* i2c-id.h - identifier values for i2c drivers and adapters */ /* */ /* ------------------------------------------------------------------------- */ /* Copyright (C) 1995-1999 Simon G. Vogl @@ -24,16 +24,6 @@ #define LINUX_I2C_ID_H /* - * This file is part of the i2c-bus package and contains the identifier - * values for drivers, adapters and other folk populating these serial - * worlds. - * - * These will change often (i.e. additions) , therefore this has been - * separated from the functional interface definitions of the i2c api. - * - */ - -/* * ---- Driver types ----------------------------------------------------- * device id name + number function description, i2c address(es) * @@ -170,151 +160,113 @@ /* * ---- Adapter types ---------------------------------------------------- - * - * First, we distinguish between several algorithms to access the hardware - * interface types, as a PCF 8584 needs other care than a bit adapter. - */ - -#define I2C_ALGO_NONE 0x000000 -#define I2C_ALGO_BIT 0x010000 /* bit style adapters */ -#define I2C_ALGO_PCF 0x020000 /* PCF 8584 style adapters */ -#define I2C_ALGO_ATI 0x030000 /* ATI video card */ -#define I2C_ALGO_SMBUS 0x040000 -#define I2C_ALGO_ISA 0x050000 /* lm_sensors ISA pseudo-adapter */ -#define I2C_ALGO_SAA7146 0x060000 /* SAA 7146 video decoder bus */ -#define I2C_ALGO_ACB 0x070000 /* ACCESS.bus algorithm */ -#define I2C_ALGO_IIC 0x080000 /* ITE IIC bus */ -#define I2C_ALGO_SAA7134 0x090000 -#define I2C_ALGO_MPC824X 0x0a0000 /* Motorola 8240 / 8245 */ -#define I2C_ALGO_IPMI 0x0b0000 /* IPMI dummy adapter */ -#define I2C_ALGO_IPMB 0x0c0000 /* IPMB adapter */ -#define I2C_ALGO_MPC107 0x0d0000 -#define I2C_ALGO_EC 0x100000 /* ACPI embedded controller */ - -#define I2C_ALGO_MPC8XX 0x110000 /* MPC8xx PowerPC I2C algorithm */ -#define I2C_ALGO_OCP 0x120000 /* IBM or otherwise On-chip I2C algorithm */ -#define I2C_ALGO_BITHS 0x130000 /* enhanced bit style adapters */ -#define I2C_ALGO_IOP3XX 0x140000 /* XSCALE IOP3XX On-chip I2C alg */ -#define I2C_ALGO_SIBYTE 0x150000 /* Broadcom SiByte SOCs */ -#define I2C_ALGO_SGI 0x160000 /* SGI algorithm */ - -#define I2C_ALGO_USB 0x170000 /* USB algorithm */ -#define I2C_ALGO_VIRT 0x180000 /* Virtual bus adapter */ - -#define I2C_ALGO_MV64XXX 0x190000 /* Marvell mv64xxx i2c ctlr */ -#define I2C_ALGO_PCA 0x1a0000 /* PCA 9564 style adapters */ -#define I2C_ALGO_AU1550 0x1b0000 /* Au1550 PSC algorithm */ - -#define I2C_ALGO_EXP 0x800000 /* experimental */ - -#define I2C_ALGO_MASK 0xff0000 /* Mask for algorithms */ -#define I2C_ALGO_SHIFT 0x10 /* right shift to get index values */ - -#define I2C_HW_ADAPS 0x10000 /* # adapter types */ -#define I2C_HW_MASK 0xffff - - -/* hw specific modules that are defined per algorithm layer */ /* --- Bit algorithm adapters */ -#define I2C_HW_B_LP 0x00 /* Parallel port Philips style adapter */ -#define I2C_HW_B_LPC 0x01 /* Parallel port, over control reg. */ -#define I2C_HW_B_SER 0x02 /* Serial line interface */ -#define I2C_HW_B_ELV 0x03 /* ELV Card */ -#define I2C_HW_B_VELLE 0x04 /* Vellemann K8000 */ -#define I2C_HW_B_BT848 0x05 /* BT848 video boards */ -#define I2C_HW_B_WNV 0x06 /* Winnov Videums */ -#define I2C_HW_B_VIA 0x07 /* Via vt82c586b */ -#define I2C_HW_B_HYDRA 0x08 /* Apple Hydra Mac I/O */ -#define I2C_HW_B_G400 0x09 /* Matrox G400 */ -#define I2C_HW_B_I810 0x0a /* Intel I810 */ -#define I2C_HW_B_VOO 0x0b /* 3dfx Voodoo 3 / Banshee */ -#define I2C_HW_B_PPORT 0x0c /* Primitive parallel port adapter */ -#define I2C_HW_B_SAVG 0x0d /* Savage 4 */ -#define I2C_HW_B_SCX200 0x0e /* Nat'l Semi SCx200 I2C */ -#define I2C_HW_B_RIVA 0x10 /* Riva based graphics cards */ -#define I2C_HW_B_IOC 0x11 /* IOC bit-wiggling */ -#define I2C_HW_B_TSUNA 0x12 /* DEC Tsunami chipset */ -#define I2C_HW_B_FRODO 0x13 /* 2d3D, Inc. SA-1110 Development Board */ -#define I2C_HW_B_OMAHA 0x14 /* Omaha I2C interface (ARM) */ -#define I2C_HW_B_GUIDE 0x15 /* Guide bit-basher */ -#define I2C_HW_B_IXP2000 0x16 /* GPIO on IXP2000 systems */ -#define I2C_HW_B_IXP4XX 0x17 /* GPIO on IXP4XX systems */ -#define I2C_HW_B_S3VIA 0x18 /* S3Via ProSavage adapter */ -#define I2C_HW_B_ZR36067 0x19 /* Zoran-36057/36067 based boards */ -#define I2C_HW_B_PCILYNX 0x1a /* TI PCILynx I2C adapter */ -#define I2C_HW_B_CX2388x 0x1b /* connexant 2388x based tv cards */ +#define I2C_HW_B_LP 0x010000 /* Parallel port Philips style */ +#define I2C_HW_B_LPC 0x010001 /* Parallel port control reg. */ +#define I2C_HW_B_SER 0x010002 /* Serial line interface */ +#define I2C_HW_B_ELV 0x010003 /* ELV Card */ +#define I2C_HW_B_VELLE 0x010004 /* Vellemann K8000 */ +#define I2C_HW_B_BT848 0x010005 /* BT848 video boards */ +#define I2C_HW_B_WNV 0x010006 /* Winnov Videums */ +#define I2C_HW_B_VIA 0x010007 /* Via vt82c586b */ +#define I2C_HW_B_HYDRA 0x010008 /* Apple Hydra Mac I/O */ +#define I2C_HW_B_G400 0x010009 /* Matrox G400 */ +#define I2C_HW_B_I810 0x01000a /* Intel I810 */ +#define I2C_HW_B_VOO 0x01000b /* 3dfx Voodoo 3 / Banshee */ +#define I2C_HW_B_PPORT 0x01000c /* Primitive parallel port adapter */ +#define I2C_HW_B_SAVG 0x01000d /* Savage 4 */ +#define I2C_HW_B_SCX200 0x01000e /* Nat'l Semi SCx200 I2C */ +#define I2C_HW_B_RIVA 0x010010 /* Riva based graphics cards */ +#define I2C_HW_B_IOC 0x010011 /* IOC bit-wiggling */ +#define I2C_HW_B_TSUNA 0x010012 /* DEC Tsunami chipset */ +#define I2C_HW_B_FRODO 0x010013 /* 2d3D SA-1110 Development Board */ +#define I2C_HW_B_OMAHA 0x010014 /* Omaha I2C interface (ARM) */ +#define I2C_HW_B_GUIDE 0x010015 /* Guide bit-basher */ +#define I2C_HW_B_IXP2000 0x010016 /* GPIO on IXP2000 systems */ +#define I2C_HW_B_IXP4XX 0x010017 /* GPIO on IXP4XX systems */ +#define I2C_HW_B_S3VIA 0x010018 /* S3Via ProSavage adapter */ +#define I2C_HW_B_ZR36067 0x010019 /* Zoran-36057/36067 based boards */ +#define I2C_HW_B_PCILYNX 0x01001a /* TI PCILynx I2C adapter */ +#define I2C_HW_B_CX2388x 0x01001b /* connexant 2388x based tv cards */ +#define I2C_HW_B_NVIDIA 0x01001c /* nvidia framebuffer driver */ +#define I2C_HW_B_SAVAGE 0x01001d /* savage framebuffer driver */ +#define I2C_HW_B_RADEON 0x01001e /* radeon framebuffer driver */ /* --- PCF 8584 based algorithms */ -#define I2C_HW_P_LP 0x00 /* Parallel port interface */ -#define I2C_HW_P_ISA 0x01 /* generic ISA Bus inteface card */ -#define I2C_HW_P_ELEK 0x02 /* Elektor ISA Bus inteface card */ +#define I2C_HW_P_LP 0x020000 /* Parallel port interface */ +#define I2C_HW_P_ISA 0x020001 /* generic ISA Bus inteface card */ +#define I2C_HW_P_ELEK 0x020002 /* Elektor ISA Bus inteface card */ /* --- PCA 9564 based algorithms */ -#define I2C_HW_A_ISA 0x00 /* generic ISA Bus interface card */ +#define I2C_HW_A_ISA 0x1a0000 /* generic ISA Bus interface card */ /* --- ACPI Embedded controller algorithms */ -#define I2C_HW_ACPI_EC 0x00 +#define I2C_HW_ACPI_EC 0x1f0000 /* --- MPC824x PowerPC adapters */ -#define I2C_HW_MPC824X 0x00 /* Motorola 8240 / 8245 */ +#define I2C_HW_MPC824X 0x100001 /* Motorola 8240 / 8245 */ /* --- MPC8xx PowerPC adapters */ -#define I2C_HW_MPC8XX_EPON 0x00 /* Eponymous MPC8xx I2C adapter */ +#define I2C_HW_MPC8XX_EPON 0x110000 /* Eponymous MPC8xx I2C adapter */ /* --- ITE based algorithms */ -#define I2C_HW_I_IIC 0x00 /* controller on the ITE */ +#define I2C_HW_I_IIC 0x080000 /* controller on the ITE */ /* --- PowerPC on-chip adapters */ -#define I2C_HW_OCP 0x00 /* IBM on-chip I2C adapter */ +#define I2C_HW_OCP 0x120000 /* IBM on-chip I2C adapter */ /* --- Broadcom SiByte adapters */ -#define I2C_HW_SIBYTE 0x00 +#define I2C_HW_SIBYTE 0x150000 /* --- SGI adapters */ -#define I2C_HW_SGI_VINO 0x00 -#define I2C_HW_SGI_MACE 0x01 +#define I2C_HW_SGI_VINO 0x160000 +#define I2C_HW_SGI_MACE 0x160001 /* --- XSCALE on-chip adapters */ -#define I2C_HW_IOP3XX 0x00 +#define I2C_HW_IOP3XX 0x140000 /* --- Au1550 PSC adapters adapters */ -#define I2C_HW_AU1550_PSC 0x00 +#define I2C_HW_AU1550_PSC 0x1b0000 /* --- SMBus only adapters */ -#define I2C_HW_SMBUS_PIIX4 0x00 -#define I2C_HW_SMBUS_ALI15X3 0x01 -#define I2C_HW_SMBUS_VIA2 0x02 -#define I2C_HW_SMBUS_VOODOO3 0x03 -#define I2C_HW_SMBUS_I801 0x04 -#define I2C_HW_SMBUS_AMD756 0x05 -#define I2C_HW_SMBUS_SIS5595 0x06 -#define I2C_HW_SMBUS_ALI1535 0x07 -#define I2C_HW_SMBUS_SIS630 0x08 -#define I2C_HW_SMBUS_SIS96X 0x09 -#define I2C_HW_SMBUS_AMD8111 0x0a -#define I2C_HW_SMBUS_SCX200 0x0b -#define I2C_HW_SMBUS_NFORCE2 0x0c -#define I2C_HW_SMBUS_W9968CF 0x0d -#define I2C_HW_SMBUS_OV511 0x0e /* OV511(+) USB 1.1 webcam ICs */ -#define I2C_HW_SMBUS_OV518 0x0f /* OV518(+) USB 1.1 webcam ICs */ -#define I2C_HW_SMBUS_OV519 0x10 /* OV519 USB 1.1 webcam IC */ -#define I2C_HW_SMBUS_OVFX2 0x11 /* Cypress/OmniVision FX2 webcam */ +#define I2C_HW_SMBUS_PIIX4 0x040000 +#define I2C_HW_SMBUS_ALI15X3 0x040001 +#define I2C_HW_SMBUS_VIA2 0x040002 +#define I2C_HW_SMBUS_VOODOO3 0x040003 +#define I2C_HW_SMBUS_I801 0x040004 +#define I2C_HW_SMBUS_AMD756 0x040005 +#define I2C_HW_SMBUS_SIS5595 0x040006 +#define I2C_HW_SMBUS_ALI1535 0x040007 +#define I2C_HW_SMBUS_SIS630 0x040008 +#define I2C_HW_SMBUS_SIS96X 0x040009 +#define I2C_HW_SMBUS_AMD8111 0x04000a +#define I2C_HW_SMBUS_SCX200 0x04000b +#define I2C_HW_SMBUS_NFORCE2 0x04000c +#define I2C_HW_SMBUS_W9968CF 0x04000d +#define I2C_HW_SMBUS_OV511 0x04000e /* OV511(+) USB 1.1 webcam ICs */ +#define I2C_HW_SMBUS_OV518 0x04000f /* OV518(+) USB 1.1 webcam ICs */ +#define I2C_HW_SMBUS_OV519 0x040010 /* OV519 USB 1.1 webcam IC */ +#define I2C_HW_SMBUS_OVFX2 0x040011 /* Cypress/OmniVision FX2 webcam */ /* --- ISA pseudo-adapter */ -#define I2C_HW_ISA 0x00 +#define I2C_HW_ISA 0x050000 /* --- IPMI pseudo-adapter */ -#define I2C_HW_IPMI 0x00 +#define I2C_HW_IPMI 0x0b0000 /* --- IPMB adapter */ -#define I2C_HW_IPMB 0x00 +#define I2C_HW_IPMB 0x0c0000 /* --- MCP107 adapter */ -#define I2C_HW_MPC107 0x00 +#define I2C_HW_MPC107 0x0d0000 /* --- Marvell mv64xxx i2c adapter */ -#define I2C_HW_MV64XXX 0x00 +#define I2C_HW_MV64XXX 0x190000 + +/* --- Miscellaneous adapters */ +#define I2C_HW_SAA7146 0x060000 /* SAA7146 video decoder bus */ +#define I2C_HW_SAA7134 0x090000 /* SAA7134 video decoder bus */ #endif /* LINUX_I2C_ID_H */ diff --git a/include/linux/i2c-isa.h b/include/linux/i2c-isa.h new file mode 100644 index 000000000000..67e3598c4cec --- /dev/null +++ b/include/linux/i2c-isa.h @@ -0,0 +1,36 @@ +/* + * i2c-isa.h - definitions for the i2c-isa pseudo-i2c-adapter interface + * + * Copyright (C) 2005 Jean Delvare <khali@linux-fr.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _LINUX_I2C_ISA_H +#define _LINUX_I2C_ISA_H + +#include <linux/i2c.h> + +extern int i2c_isa_add_driver(struct i2c_driver *driver); +extern int i2c_isa_del_driver(struct i2c_driver *driver); + +/* Detect whether we are on the isa bus. This is only useful to hybrid + (i2c+isa) drivers. */ +#define i2c_is_isa_adapter(adapptr) \ + ((adapptr)->id == I2C_HW_ISA) +#define i2c_is_isa_client(clientptr) \ + i2c_is_isa_adapter((clientptr)->adapter) + +#endif /* _LINUX_I2C_ISA_H */ diff --git a/include/linux/i2c-sensor.h b/include/linux/i2c-sensor.h deleted file mode 100644 index 21b625204956..000000000000 --- a/include/linux/i2c-sensor.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - i2c-sensor.h - Part of the i2c package - was originally sensors.h - Part of lm_sensors, Linux kernel modules - for hardware monitoring - Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef _LINUX_I2C_SENSOR_H -#define _LINUX_I2C_SENSOR_H - -/* A structure containing detect information. - Force variables overrule all other variables; they force a detection on - that place. If a specific chip is given, the module blindly assumes this - chip type is present; if a general force (kind == 0) is given, the module - will still try to figure out what type of chip is present. This is useful - if for some reasons the detect for SMBus or ISA address space filled - fails. - probe: insmod parameter. Initialize this list with I2C_CLIENT_ISA_END values. - A list of pairs. The first value is a bus number (ANY_I2C_ISA_BUS for - the ISA bus, -1 for any I2C bus), the second is the address. - kind: The kind of chip. 0 equals any chip. -*/ -struct i2c_force_data { - unsigned short *force; - unsigned short kind; -}; - -/* A structure containing the detect information. - normal_i2c: filled in by the module writer. Terminated by I2C_CLIENT_ISA_END. - A list of I2C addresses which should normally be examined. - normal_isa: filled in by the module writer. Terminated by SENSORS_ISA_END. - A list of ISA addresses which should normally be examined. - probe: insmod parameter. Initialize this list with I2C_CLIENT_ISA_END values. - A list of pairs. The first value is a bus number (ANY_I2C_ISA_BUS for - the ISA bus, -1 for any I2C bus), the second is the address. These - addresses are also probed, as if they were in the 'normal' list. - ignore: insmod parameter. Initialize this list with I2C_CLIENT_ISA_END values. - A list of pairs. The first value is a bus number (ANY_I2C_ISA_BUS for - the ISA bus, -1 for any I2C bus), the second is the I2C address. These - addresses are never probed. This parameter overrules 'normal' and - 'probe', but not the 'force' lists. - force_data: insmod parameters. A list, ending with an element of which - the force field is NULL. -*/ -struct i2c_address_data { - unsigned short *normal_i2c; - unsigned int *normal_isa; - unsigned short *probe; - unsigned short *ignore; - struct i2c_force_data *forces; -}; - -#define SENSORS_MODULE_PARM_FORCE(name) \ - I2C_CLIENT_MODULE_PARM(force_ ## name, \ - "List of adapter,address pairs which are unquestionably" \ - " assumed to contain a `" # name "' chip") - - -/* This defines several insmod variables, and the addr_data structure */ -#define SENSORS_INSMOD \ - I2C_CLIENT_MODULE_PARM(probe, \ - "List of adapter,address pairs to scan additionally"); \ - I2C_CLIENT_MODULE_PARM(ignore, \ - "List of adapter,address pairs not to scan"); \ - static struct i2c_address_data addr_data = { \ - .normal_i2c = normal_i2c, \ - .normal_isa = normal_isa, \ - .probe = probe, \ - .ignore = ignore, \ - .forces = forces, \ - } - -/* The following functions create an enum with the chip names as elements. - The first element of the enum is any_chip. These are the only macros - a module will want to use. */ - -#define SENSORS_INSMOD_0 \ - enum chips { any_chip }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - static struct i2c_force_data forces[] = {{force,any_chip},{NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_1(chip1) \ - enum chips { any_chip, chip1 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - static struct i2c_force_data forces[] = {{force,any_chip},\ - {force_ ## chip1,chip1}, \ - {NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_2(chip1,chip2) \ - enum chips { any_chip, chip1, chip2 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - SENSORS_MODULE_PARM_FORCE(chip2); \ - static struct i2c_force_data forces[] = {{force,any_chip}, \ - {force_ ## chip1,chip1}, \ - {force_ ## chip2,chip2}, \ - {NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_3(chip1,chip2,chip3) \ - enum chips { any_chip, chip1, chip2, chip3 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - SENSORS_MODULE_PARM_FORCE(chip2); \ - SENSORS_MODULE_PARM_FORCE(chip3); \ - static struct i2c_force_data forces[] = {{force,any_chip}, \ - {force_ ## chip1,chip1}, \ - {force_ ## chip2,chip2}, \ - {force_ ## chip3,chip3}, \ - {NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_4(chip1,chip2,chip3,chip4) \ - enum chips { any_chip, chip1, chip2, chip3, chip4 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - SENSORS_MODULE_PARM_FORCE(chip2); \ - SENSORS_MODULE_PARM_FORCE(chip3); \ - SENSORS_MODULE_PARM_FORCE(chip4); \ - static struct i2c_force_data forces[] = {{force,any_chip}, \ - {force_ ## chip1,chip1}, \ - {force_ ## chip2,chip2}, \ - {force_ ## chip3,chip3}, \ - {force_ ## chip4,chip4}, \ - {NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_5(chip1,chip2,chip3,chip4,chip5) \ - enum chips { any_chip, chip1, chip2, chip3, chip4, chip5 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - SENSORS_MODULE_PARM_FORCE(chip2); \ - SENSORS_MODULE_PARM_FORCE(chip3); \ - SENSORS_MODULE_PARM_FORCE(chip4); \ - SENSORS_MODULE_PARM_FORCE(chip5); \ - static struct i2c_force_data forces[] = {{force,any_chip}, \ - {force_ ## chip1,chip1}, \ - {force_ ## chip2,chip2}, \ - {force_ ## chip3,chip3}, \ - {force_ ## chip4,chip4}, \ - {force_ ## chip5,chip5}, \ - {NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_6(chip1,chip2,chip3,chip4,chip5,chip6) \ - enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - SENSORS_MODULE_PARM_FORCE(chip2); \ - SENSORS_MODULE_PARM_FORCE(chip3); \ - SENSORS_MODULE_PARM_FORCE(chip4); \ - SENSORS_MODULE_PARM_FORCE(chip5); \ - SENSORS_MODULE_PARM_FORCE(chip6); \ - static struct i2c_force_data forces[] = {{force,any_chip}, \ - {force_ ## chip1,chip1}, \ - {force_ ## chip2,chip2}, \ - {force_ ## chip3,chip3}, \ - {force_ ## chip4,chip4}, \ - {force_ ## chip5,chip5}, \ - {force_ ## chip6,chip6}, \ - {NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_7(chip1,chip2,chip3,chip4,chip5,chip6,chip7) \ - enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6, chip7 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - SENSORS_MODULE_PARM_FORCE(chip2); \ - SENSORS_MODULE_PARM_FORCE(chip3); \ - SENSORS_MODULE_PARM_FORCE(chip4); \ - SENSORS_MODULE_PARM_FORCE(chip5); \ - SENSORS_MODULE_PARM_FORCE(chip6); \ - SENSORS_MODULE_PARM_FORCE(chip7); \ - static struct i2c_force_data forces[] = {{force,any_chip}, \ - {force_ ## chip1,chip1}, \ - {force_ ## chip2,chip2}, \ - {force_ ## chip3,chip3}, \ - {force_ ## chip4,chip4}, \ - {force_ ## chip5,chip5}, \ - {force_ ## chip6,chip6}, \ - {force_ ## chip7,chip7}, \ - {NULL}}; \ - SENSORS_INSMOD - -#define SENSORS_INSMOD_8(chip1,chip2,chip3,chip4,chip5,chip6,chip7,chip8) \ - enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6, chip7, chip8 }; \ - I2C_CLIENT_MODULE_PARM(force, \ - "List of adapter,address pairs to boldly assume " \ - "to be present"); \ - SENSORS_MODULE_PARM_FORCE(chip1); \ - SENSORS_MODULE_PARM_FORCE(chip2); \ - SENSORS_MODULE_PARM_FORCE(chip3); \ - SENSORS_MODULE_PARM_FORCE(chip4); \ - SENSORS_MODULE_PARM_FORCE(chip5); \ - SENSORS_MODULE_PARM_FORCE(chip6); \ - SENSORS_MODULE_PARM_FORCE(chip7); \ - SENSORS_MODULE_PARM_FORCE(chip8); \ - static struct i2c_force_data forces[] = {{force,any_chip}, \ - {force_ ## chip1,chip1}, \ - {force_ ## chip2,chip2}, \ - {force_ ## chip3,chip3}, \ - {force_ ## chip4,chip4}, \ - {force_ ## chip5,chip5}, \ - {force_ ## chip6,chip6}, \ - {force_ ## chip7,chip7}, \ - {force_ ## chip8,chip8}, \ - {NULL}}; \ - SENSORS_INSMOD - -/* Detect function. It iterates over all possible addresses itself. For - SMBus addresses, it will only call found_proc if some client is connected - to the SMBus (unless a 'force' matched); for ISA detections, this is not - done. */ -extern int i2c_detect(struct i2c_adapter *adapter, - struct i2c_address_data *address_data, - int (*found_proc) (struct i2c_adapter *, int, int)); - - -/* This macro is used to scale user-input to sensible values in almost all - chip drivers. */ -static inline int SENSORS_LIMIT(long value, long low, long high) -{ - if (value < low) - return low; - else if (value > high) - return high; - else - return value; -} -#endif /* def _LINUX_I2C_SENSOR_H */ diff --git a/include/linux/i2c-vid.h b/include/linux/i2c-vid.h deleted file mode 100644 index 41d0635e0ba9..000000000000 --- a/include/linux/i2c-vid.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - i2c-vid.h - Part of lm_sensors, Linux kernel modules for hardware - monitoring - Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com> - With assistance from Trent Piepho <xyzzy@speakeasy.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -/* - This file contains common code for decoding VID pins. - This file is #included in various chip drivers in this directory. - As the user is unlikely to load more than one driver which - includes this code we don't worry about the wasted space. - Reference: VRM x.y DC-DC Converter Design Guidelines, - available at http://developer.intel.com -*/ - -/* - AMD Opteron processors don't follow the Intel VRM spec. - I'm going to "make up" 2.4 as the VRM spec for the Opterons. - No good reason just a mnemonic for the 24x Opteron processor - series - - Opteron VID encoding is: - - 00000 = 1.550 V - 00001 = 1.525 V - . . . . - 11110 = 0.800 V - 11111 = 0.000 V (off) - */ - -/* - Legal val values 0x00 - 0x1f; except for VRD 10.0, 0x00 - 0x3f. - vrm is the Intel VRM document version. - Note: vrm version is scaled by 10 and the return value is scaled by 1000 - to avoid floating point in the kernel. -*/ - -int i2c_which_vrm(void); - -#define DEFAULT_VRM 82 - -static inline int vid_from_reg(int val, int vrm) -{ - int vid; - - switch(vrm) { - - case 0: - return 0; - - case 100: /* VRD 10.0 */ - if((val & 0x1f) == 0x1f) - return 0; - if((val & 0x1f) <= 0x09 || val == 0x0a) - vid = 10875 - (val & 0x1f) * 250; - else - vid = 18625 - (val & 0x1f) * 250; - if(val & 0x20) - vid -= 125; - vid /= 10; /* only return 3 dec. places for now */ - return vid; - - case 24: /* Opteron processor */ - return(val == 0x1f ? 0 : 1550 - val * 25); - - case 91: /* VRM 9.1 */ - case 90: /* VRM 9.0 */ - return(val == 0x1f ? 0 : - 1850 - val * 25); - - case 85: /* VRM 8.5 */ - return((val & 0x10 ? 25 : 0) + - ((val & 0x0f) > 0x04 ? 2050 : 1250) - - ((val & 0x0f) * 50)); - - case 84: /* VRM 8.4 */ - val &= 0x0f; - /* fall through */ - default: /* VRM 8.2 */ - return(val == 0x1f ? 0 : - val & 0x10 ? 5100 - (val) * 100 : - 2050 - (val) * 50); - } -} - -static inline int vid_to_reg(int val, int vrm) -{ - switch (vrm) { - case 91: /* VRM 9.1 */ - case 90: /* VRM 9.0 */ - return ((val >= 1100) && (val <= 1850) ? - ((18499 - val * 10) / 25 + 5) / 10 : -1); - default: - return -1; - } -} diff --git a/include/linux/i2c.h b/include/linux/i2c.h index be837b13f297..be35332b67e6 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -34,6 +34,13 @@ #include <linux/device.h> /* for struct device */ #include <asm/semaphore.h> +/* --- For i2c-isa ---------------------------------------------------- */ + +extern void i2c_adapter_dev_release(struct device *dev); +extern struct device_driver i2c_adapter_driver; +extern struct class i2c_adapter_class; +extern struct bus_type i2c_bus_type; + /* --- General options ------------------------------------------------ */ struct i2c_msg; @@ -41,7 +48,6 @@ struct i2c_algorithm; struct i2c_adapter; struct i2c_client; struct i2c_driver; -struct i2c_client_address_data; union i2c_smbus_data; /* @@ -143,12 +149,9 @@ struct i2c_driver { */ struct i2c_client { unsigned int flags; /* div., see below */ - unsigned int addr; /* chip address - NOTE: 7bit */ + unsigned short addr; /* chip address - NOTE: 7bit */ /* addresses are stored in the */ - /* _LOWER_ 7 bits of this char */ - /* addr: unsigned int to make lm_sensors i2c-isa adapter work - more cleanly. It does not take any more memory space, due to - alignment considerations */ + /* _LOWER_ 7 bits */ struct i2c_adapter *adapter; /* the adapter we sit on */ struct i2c_driver *driver; /* and our access routines */ int usage_count; /* How many accesses currently */ @@ -160,6 +163,11 @@ struct i2c_client { }; #define to_i2c_client(d) container_of(d, struct i2c_client, dev) +static inline struct i2c_client *kobj_to_i2c_client(struct kobject *kobj) +{ + return to_i2c_client(container_of(kobj, struct device, kobj)); +} + static inline void *i2c_get_clientdata (struct i2c_client *dev) { return dev_get_drvdata (&dev->dev); @@ -170,13 +178,6 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data) dev_set_drvdata (&dev->dev, data); } -#define I2C_DEVNAME(str) .name = str - -static inline char *i2c_clientname(struct i2c_client *c) -{ - return &c->name[0]; -} - /* * The following structs are for those who like to implement new bus drivers: * i2c_algorithm is the interface to a class of hardware solutions which can @@ -184,9 +185,6 @@ static inline char *i2c_clientname(struct i2c_client *c) * to name two of the most common. */ struct i2c_algorithm { - char name[32]; /* textual description */ - unsigned int id; - /* If an adapter algorithm can't do I2C-level access, set master_xfer to NULL. If an adapter algorithm can do SMBus access, set smbus_xfer. If set to NULL, the SMBus protocol is simulated @@ -214,8 +212,7 @@ struct i2c_algorithm { */ struct i2c_adapter { struct module *owner; - unsigned int id;/* == is algo->id | hwdep.struct->id, */ - /* for registered values see below */ + unsigned int id; unsigned int class; struct i2c_algorithm *algo;/* the algorithm to access the bus */ void *algo_data; @@ -292,12 +289,11 @@ struct i2c_client_address_data { unsigned short *normal_i2c; unsigned short *probe; unsigned short *ignore; - unsigned short *force; + unsigned short **forces; }; /* Internal numbers to terminate lists */ #define I2C_CLIENT_END 0xfffeU -#define I2C_CLIENT_ISA_END 0xfffefffeU /* The numbers to use to set I2C bus address */ #define ANY_I2C_BUS 0xffff @@ -356,10 +352,6 @@ extern int i2c_probe(struct i2c_adapter *adapter, */ extern int i2c_control(struct i2c_client *,unsigned int, unsigned long); -/* This call returns a unique low identifier for each registered adapter, - * or -1 if the adapter was not registered. - */ -extern int i2c_adapter_id(struct i2c_adapter *adap); extern struct i2c_adapter* i2c_get_adapter(int id); extern void i2c_put_adapter(struct i2c_adapter *adap); @@ -376,6 +368,12 @@ static inline int i2c_check_functionality(struct i2c_adapter *adap, u32 func) return (func & i2c_get_functionality(adap)) == func; } +/* Return id number for a specific adapter */ +static inline int i2c_adapter_id(struct i2c_adapter *adap) +{ + return adap->nr; +} + /* * I2C Message - used for pure i2c transaction, also from /dev interface */ @@ -510,9 +508,6 @@ union i2c_smbus_data { #define I2C_FUNCS 0x0705 /* Get the adapter functionality */ #define I2C_RDWR 0x0707 /* Combined R/W transfer (one stop only)*/ #define I2C_PEC 0x0708 /* != 0 for SMBus PEC */ -#if 0 -#define I2C_ACK_TEST 0x0710 /* See if a slave is at a specific address */ -#endif #define I2C_SMBUS 0x0720 /* SMBus-level access */ @@ -556,27 +551,148 @@ union i2c_smbus_data { module_param_array(var, short, &var##_num, 0); \ MODULE_PARM_DESC(var,desc) -/* This is the one you want to use in your own modules */ +#define I2C_CLIENT_MODULE_PARM_FORCE(name) \ +I2C_CLIENT_MODULE_PARM(force_##name, \ + "List of adapter,address pairs which are " \ + "unquestionably assumed to contain a `" \ + # name "' chip") + + +#define I2C_CLIENT_INSMOD_COMMON \ +I2C_CLIENT_MODULE_PARM(probe, "List of adapter,address pairs to scan " \ + "additionally"); \ +I2C_CLIENT_MODULE_PARM(ignore, "List of adapter,address pairs not to " \ + "scan"); \ +static struct i2c_client_address_data addr_data = { \ + .normal_i2c = normal_i2c, \ + .probe = probe, \ + .ignore = ignore, \ + .forces = forces, \ +} + +/* These are the ones you want to use in your own drivers. Pick the one + which matches the number of devices the driver differenciates between. */ #define I2C_CLIENT_INSMOD \ - I2C_CLIENT_MODULE_PARM(probe, \ - "List of adapter,address pairs to scan additionally"); \ - I2C_CLIENT_MODULE_PARM(ignore, \ - "List of adapter,address pairs not to scan"); \ I2C_CLIENT_MODULE_PARM(force, \ "List of adapter,address pairs to boldly assume " \ "to be present"); \ - static struct i2c_client_address_data addr_data = { \ - .normal_i2c = normal_i2c, \ - .probe = probe, \ - .ignore = ignore, \ - .force = force, \ - } - -/* Detect whether we are on the isa bus. If this returns true, all i2c - access will fail! */ -#define i2c_is_isa_client(clientptr) \ - ((clientptr)->adapter->algo->id == I2C_ALGO_ISA) -#define i2c_is_isa_adapter(adapptr) \ - ((adapptr)->algo->id == I2C_ALGO_ISA) + static unsigned short *forces[] = { \ + force, \ + NULL \ + }; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_1(chip1) \ +enum chips { any_chip, chip1 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +static unsigned short *forces[] = { force, force_##chip1, NULL }; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_2(chip1, chip2) \ +enum chips { any_chip, chip1, chip2 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip2); \ +static unsigned short *forces[] = { force, force_##chip1, \ + force_##chip2, NULL }; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_3(chip1, chip2, chip3) \ +enum chips { any_chip, chip1, chip2, chip3 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip2); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip3); \ +static unsigned short *forces[] = { force, force_##chip1, \ + force_##chip2, force_##chip3, \ + NULL }; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_4(chip1, chip2, chip3, chip4) \ +enum chips { any_chip, chip1, chip2, chip3, chip4 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip2); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip3); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip4); \ +static unsigned short *forces[] = { force, force_##chip1, \ + force_##chip2, force_##chip3, \ + force_##chip4, NULL}; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_5(chip1, chip2, chip3, chip4, chip5) \ +enum chips { any_chip, chip1, chip2, chip3, chip4, chip5 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip2); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip3); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip4); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip5); \ +static unsigned short *forces[] = { force, force_##chip1, \ + force_##chip2, force_##chip3, \ + force_##chip4, force_##chip5, \ + NULL }; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_6(chip1, chip2, chip3, chip4, chip5, chip6) \ +enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip2); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip3); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip4); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip5); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip6); \ +static unsigned short *forces[] = { force, force_##chip1, \ + force_##chip2, force_##chip3, \ + force_##chip4, force_##chip5, \ + force_##chip6, NULL }; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_7(chip1, chip2, chip3, chip4, chip5, chip6, chip7) \ +enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6, \ + chip7 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip2); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip3); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip4); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip5); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip6); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip7); \ +static unsigned short *forces[] = { force, force_##chip1, \ + force_##chip2, force_##chip3, \ + force_##chip4, force_##chip5, \ + force_##chip6, force_##chip7, \ + NULL }; \ +I2C_CLIENT_INSMOD_COMMON + +#define I2C_CLIENT_INSMOD_8(chip1, chip2, chip3, chip4, chip5, chip6, chip7, chip8) \ +enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6, \ + chip7, chip8 }; \ +I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to " \ + "boldly assume to be present"); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip1); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip2); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip3); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip4); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip5); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip6); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip7); \ +I2C_CLIENT_MODULE_PARM_FORCE(chip8); \ +static unsigned short *forces[] = { force, force_##chip1, \ + force_##chip2, force_##chip3, \ + force_##chip4, force_##chip5, \ + force_##chip6, force_##chip7, \ + force_##chip8, NULL }; \ +I2C_CLIENT_INSMOD_COMMON #endif /* _LINUX_I2C_H */ diff --git a/include/linux/ide.h b/include/linux/ide.h index 92129078d4f3..a6dbb51ecd7b 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1501,4 +1501,10 @@ extern struct bus_type ide_bus_type; #define ide_id_has_flush_cache_ext(id) \ (((id)->cfs_enable_2 & 0x2400) == 0x2400) +static inline int hwif_to_node(ide_hwif_t *hwif) +{ + struct pci_dev *dev = hwif->pci_dev; + return dev ? pcibus_to_node(dev->bus) : -1; +} + #endif /* _IDE_H */ diff --git a/include/linux/if_ether.h b/include/linux/if_ether.h index b5b58e9c054c..fc2d4c8225aa 100644 --- a/include/linux/if_ether.h +++ b/include/linux/if_ether.h @@ -110,6 +110,8 @@ static inline struct ethhdr *eth_hdr(const struct sk_buff *skb) { return (struct ethhdr *)skb->mac.raw; } + +extern struct ctl_table ether_table[]; #endif #endif /* _LINUX_IF_ETHER_H */ diff --git a/include/linux/if_fc.h b/include/linux/if_fc.h index 33330b458b95..376a34ea4723 100644 --- a/include/linux/if_fc.h +++ b/include/linux/if_fc.h @@ -44,7 +44,7 @@ struct fcllc { __u8 ssap; /* source SAP */ __u8 llc; /* LLC control field */ __u8 protid[3]; /* protocol id */ - __u16 ethertype; /* ether type field */ + __be16 ethertype; /* ether type field */ }; #endif /* _LINUX_IF_FC_H */ diff --git a/include/linux/if_fddi.h b/include/linux/if_fddi.h index a912818e6361..1288a161bc0b 100644 --- a/include/linux/if_fddi.h +++ b/include/linux/if_fddi.h @@ -85,7 +85,7 @@ struct fddi_snap_hdr __u8 ssap; /* always 0xAA */ __u8 ctrl; /* always 0x03 */ __u8 oui[FDDI_K_OUI_LEN]; /* organizational universal id */ - __u16 ethertype; /* packet type ID field */ + __be16 ethertype; /* packet type ID field */ } __attribute__ ((packed)); /* Define FDDI LLC frame header */ diff --git a/include/linux/if_frad.h b/include/linux/if_frad.h index 3c94b1736570..511999c7eeda 100644 --- a/include/linux/if_frad.h +++ b/include/linux/if_frad.h @@ -191,10 +191,12 @@ struct frad_local int buffer; /* current buffer for S508 firmware */ }; -extern void dlci_ioctl_set(int (*hook)(unsigned int, void __user *)); - #endif /* __KERNEL__ */ #endif /* CONFIG_DLCI || CONFIG_DLCI_MODULE */ +#ifdef __KERNEL__ +extern void dlci_ioctl_set(int (*hook)(unsigned int, void __user *)); +#endif + #endif diff --git a/include/linux/if_hippi.h b/include/linux/if_hippi.h index c8ca72c46f76..94d31ca7d71a 100644 --- a/include/linux/if_hippi.h +++ b/include/linux/if_hippi.h @@ -102,9 +102,9 @@ struct hippi_fp_hdr #error "Please fix <asm/byteorder.h>" #endif #else - __u32 fixed; + __be32 fixed; #endif - __u32 d2_size; + __be32 d2_size; } __attribute__ ((packed)); struct hippi_le_hdr @@ -144,7 +144,7 @@ struct hippi_snap_hdr __u8 ssap; /* always 0xAA */ __u8 ctrl; /* always 0x03 */ __u8 oui[HIPPI_OUI_LEN]; /* organizational universal id (zero)*/ - __u16 ethertype; /* packet type ID field */ + __be16 ethertype; /* packet type ID field */ } __attribute__ ((packed)); struct hippi_hdr diff --git a/include/linux/if_tr.h b/include/linux/if_tr.h index 3fba9e2f5427..5502f597cf0e 100644 --- a/include/linux/if_tr.h +++ b/include/linux/if_tr.h @@ -43,12 +43,16 @@ struct trh_hdr { }; #ifdef __KERNEL__ +#include <linux/config.h> #include <linux/skbuff.h> static inline struct trh_hdr *tr_hdr(const struct sk_buff *skb) { return (struct trh_hdr *)skb->mac.raw; } +#ifdef CONFIG_SYSCTL +extern struct ctl_table tr_table[]; +#endif #endif /* This is an Token-Ring LLC structure */ diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h index 096a85a58ae5..88aef7b86ef4 100644 --- a/include/linux/if_tun.h +++ b/include/linux/if_tun.h @@ -77,6 +77,7 @@ struct tun_struct { #define TUNSETIFF _IOW('T', 202, int) #define TUNSETPERSIST _IOW('T', 203, int) #define TUNSETOWNER _IOW('T', 204, int) +#define TUNSETLINK _IOW('T', 205, int) /* TUNSETIFF ifr flags */ #define IFF_TUN 0x0001 diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index 62a9d89dfbe2..17d0c0d40b0e 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -155,7 +155,6 @@ static inline int __vlan_hwaccel_rx(struct sk_buff *skb, { struct net_device_stats *stats; - skb->real_dev = skb->dev; skb->dev = grp->vlan_devices[vlan_tag & VLAN_VID_MASK]; if (skb->dev == NULL) { dev_kfree_skb_any(skb); diff --git a/include/linux/igmp.h b/include/linux/igmp.h index 0c31ef0b5bad..28f4f3b36950 100644 --- a/include/linux/igmp.h +++ b/include/linux/igmp.h @@ -129,6 +129,9 @@ struct igmpv3_query { #include <linux/skbuff.h> #include <linux/in.h> +extern int sysctl_igmp_max_memberships; +extern int sysctl_igmp_max_msf; + struct ip_sf_socklist { unsigned int sl_max; diff --git a/include/linux/in.h b/include/linux/in.h index fb88c66d748d..ba355384016a 100644 --- a/include/linux/in.h +++ b/include/linux/in.h @@ -32,6 +32,7 @@ enum { IPPROTO_PUP = 12, /* PUP protocol */ IPPROTO_UDP = 17, /* User Datagram Protocol */ IPPROTO_IDP = 22, /* XNS IDP protocol */ + IPPROTO_DCCP = 33, /* Datagram Congestion Control Protocol */ IPPROTO_RSVP = 46, /* RSVP protocol */ IPPROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */ diff --git a/include/linux/inet_diag.h b/include/linux/inet_diag.h new file mode 100644 index 000000000000..a4606e5810e5 --- /dev/null +++ b/include/linux/inet_diag.h @@ -0,0 +1,138 @@ +#ifndef _INET_DIAG_H_ +#define _INET_DIAG_H_ 1 + +/* Just some random number */ +#define TCPDIAG_GETSOCK 18 +#define DCCPDIAG_GETSOCK 19 + +#define INET_DIAG_GETSOCK_MAX 24 + +/* Socket identity */ +struct inet_diag_sockid { + __u16 idiag_sport; + __u16 idiag_dport; + __u32 idiag_src[4]; + __u32 idiag_dst[4]; + __u32 idiag_if; + __u32 idiag_cookie[2]; +#define INET_DIAG_NOCOOKIE (~0U) +}; + +/* Request structure */ + +struct inet_diag_req { + __u8 idiag_family; /* Family of addresses. */ + __u8 idiag_src_len; + __u8 idiag_dst_len; + __u8 idiag_ext; /* Query extended information */ + + struct inet_diag_sockid id; + + __u32 idiag_states; /* States to dump */ + __u32 idiag_dbs; /* Tables to dump (NI) */ +}; + +enum { + INET_DIAG_REQ_NONE, + INET_DIAG_REQ_BYTECODE, +}; + +#define INET_DIAG_REQ_MAX INET_DIAG_REQ_BYTECODE + +/* Bytecode is sequence of 4 byte commands followed by variable arguments. + * All the commands identified by "code" are conditional jumps forward: + * to offset cc+"yes" or to offset cc+"no". "yes" is supposed to be + * length of the command and its arguments. + */ + +struct inet_diag_bc_op { + unsigned char code; + unsigned char yes; + unsigned short no; +}; + +enum { + INET_DIAG_BC_NOP, + INET_DIAG_BC_JMP, + INET_DIAG_BC_S_GE, + INET_DIAG_BC_S_LE, + INET_DIAG_BC_D_GE, + INET_DIAG_BC_D_LE, + INET_DIAG_BC_AUTO, + INET_DIAG_BC_S_COND, + INET_DIAG_BC_D_COND, +}; + +struct inet_diag_hostcond { + __u8 family; + __u8 prefix_len; + int port; + __u32 addr[0]; +}; + +/* Base info structure. It contains socket identity (addrs/ports/cookie) + * and, alas, the information shown by netstat. */ +struct inet_diag_msg { + __u8 idiag_family; + __u8 idiag_state; + __u8 idiag_timer; + __u8 idiag_retrans; + + struct inet_diag_sockid id; + + __u32 idiag_expires; + __u32 idiag_rqueue; + __u32 idiag_wqueue; + __u32 idiag_uid; + __u32 idiag_inode; +}; + +/* Extensions */ + +enum { + INET_DIAG_NONE, + INET_DIAG_MEMINFO, + INET_DIAG_INFO, + INET_DIAG_VEGASINFO, + INET_DIAG_CONG, +}; + +#define INET_DIAG_MAX INET_DIAG_CONG + + +/* INET_DIAG_MEM */ + +struct inet_diag_meminfo { + __u32 idiag_rmem; + __u32 idiag_wmem; + __u32 idiag_fmem; + __u32 idiag_tmem; +}; + +/* INET_DIAG_VEGASINFO */ + +struct tcpvegas_info { + __u32 tcpv_enabled; + __u32 tcpv_rttcnt; + __u32 tcpv_rtt; + __u32 tcpv_minrtt; +}; + +#ifdef __KERNEL__ +struct sock; +struct inet_hashinfo; + +struct inet_diag_handler { + struct inet_hashinfo *idiag_hashinfo; + void (*idiag_get_info)(struct sock *sk, + struct inet_diag_msg *r, + void *info); + __u16 idiag_info_size; + __u16 idiag_type; +}; + +extern int inet_diag_register(const struct inet_diag_handler *handler); +extern void inet_diag_unregister(const struct inet_diag_handler *handler); +#endif /* __KERNEL__ */ + +#endif /* _INET_DIAG_H_ */ diff --git a/include/linux/inotify.h b/include/linux/inotify.h new file mode 100644 index 000000000000..93bb3afe646b --- /dev/null +++ b/include/linux/inotify.h @@ -0,0 +1,110 @@ +/* + * Inode based directory notification for Linux + * + * Copyright (C) 2005 John McCutchan + */ + +#ifndef _LINUX_INOTIFY_H +#define _LINUX_INOTIFY_H + +#include <linux/types.h> + +/* + * struct inotify_event - structure read from the inotify device for each event + * + * When you are watching a directory, you will receive the filename for events + * such as IN_CREATE, IN_DELETE, IN_OPEN, IN_CLOSE, ..., relative to the wd. + */ +struct inotify_event { + __s32 wd; /* watch descriptor */ + __u32 mask; /* watch mask */ + __u32 cookie; /* cookie to synchronize two events */ + __u32 len; /* length (including nulls) of name */ + char name[0]; /* stub for possible name */ +}; + +/* the following are legal, implemented events that user-space can watch for */ +#define IN_ACCESS 0x00000001 /* File was accessed */ +#define IN_MODIFY 0x00000002 /* File was modified */ +#define IN_ATTRIB 0x00000004 /* Metadata changed */ +#define IN_CLOSE_WRITE 0x00000008 /* Writtable file was closed */ +#define IN_CLOSE_NOWRITE 0x00000010 /* Unwrittable file closed */ +#define IN_OPEN 0x00000020 /* File was opened */ +#define IN_MOVED_FROM 0x00000040 /* File was moved from X */ +#define IN_MOVED_TO 0x00000080 /* File was moved to Y */ +#define IN_CREATE 0x00000100 /* Subfile was created */ +#define IN_DELETE 0x00000200 /* Subfile was deleted */ +#define IN_DELETE_SELF 0x00000400 /* Self was deleted */ +#define IN_MOVE_SELF 0x00000800 /* Self was moved */ + +/* the following are legal events. they are sent as needed to any watch */ +#define IN_UNMOUNT 0x00002000 /* Backing fs was unmounted */ +#define IN_Q_OVERFLOW 0x00004000 /* Event queued overflowed */ +#define IN_IGNORED 0x00008000 /* File was ignored */ + +/* helper events */ +#define IN_CLOSE (IN_CLOSE_WRITE | IN_CLOSE_NOWRITE) /* close */ +#define IN_MOVE (IN_MOVED_FROM | IN_MOVED_TO) /* moves */ + +/* special flags */ +#define IN_ISDIR 0x40000000 /* event occurred against dir */ +#define IN_ONESHOT 0x80000000 /* only send event once */ + +/* + * All of the events - we build the list by hand so that we can add flags in + * the future and not break backward compatibility. Apps will get only the + * events that they originally wanted. Be sure to add new events here! + */ +#define IN_ALL_EVENTS (IN_ACCESS | IN_MODIFY | IN_ATTRIB | IN_CLOSE_WRITE | \ + IN_CLOSE_NOWRITE | IN_OPEN | IN_MOVED_FROM | \ + IN_MOVED_TO | IN_DELETE | IN_CREATE | IN_DELETE_SELF | \ + IN_MOVE_SELF) + +#ifdef __KERNEL__ + +#include <linux/dcache.h> +#include <linux/fs.h> +#include <linux/config.h> + +#ifdef CONFIG_INOTIFY + +extern void inotify_inode_queue_event(struct inode *, __u32, __u32, + const char *); +extern void inotify_dentry_parent_queue_event(struct dentry *, __u32, __u32, + const char *); +extern void inotify_unmount_inodes(struct list_head *); +extern void inotify_inode_is_dead(struct inode *); +extern u32 inotify_get_cookie(void); + +#else + +static inline void inotify_inode_queue_event(struct inode *inode, + __u32 mask, __u32 cookie, + const char *filename) +{ +} + +static inline void inotify_dentry_parent_queue_event(struct dentry *dentry, + __u32 mask, __u32 cookie, + const char *filename) +{ +} + +static inline void inotify_unmount_inodes(struct list_head *list) +{ +} + +static inline void inotify_inode_is_dead(struct inode *inode) +{ +} + +static inline u32 inotify_get_cookie(void) +{ + return 0; +} + +#endif /* CONFIG_INOTIFY */ + +#endif /* __KERNEL __ */ + +#endif /* _LINUX_INOTIFY_H */ diff --git a/include/linux/input.h b/include/linux/input.h index b9cc0ac71f44..bdc53c6cc962 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -811,9 +811,9 @@ struct input_dev { void *private; - char *name; - char *phys; - char *uniq; + const char *name; + const char *phys; + const char *uniq; struct input_id id; unsigned long evbit[NBITS(EV_MAX)]; diff --git a/include/linux/ip.h b/include/linux/ip.h index 31e7cedd9f84..33e8a19a1a0f 100644 --- a/include/linux/ip.h +++ b/include/linux/ip.h @@ -196,6 +196,8 @@ static inline void inet_sk_copy_descendant(struct sock *sk_to, #endif #endif +extern int inet_sk_rebuild_header(struct sock *sk); + struct iphdr { #if defined(__LITTLE_ENDIAN_BITFIELD) __u8 ihl:4, diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 6fcd6a0ade24..3c7dbc6a0a70 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -193,6 +193,11 @@ struct inet6_skb_parm { #define IP6CB(skb) ((struct inet6_skb_parm*)((skb)->cb)) +static inline int inet6_iif(const struct sk_buff *skb) +{ + return IP6CB(skb)->iif; +} + struct tcp6_request_sock { struct tcp_request_sock req; struct in6_addr loc_addr; @@ -308,6 +313,36 @@ static inline void inet_sk_copy_descendant(struct sock *sk_to, #define __ipv6_only_sock(sk) (inet6_sk(sk)->ipv6only) #define ipv6_only_sock(sk) ((sk)->sk_family == PF_INET6 && __ipv6_only_sock(sk)) + +#include <linux/tcp.h> + +struct tcp6_timewait_sock { + struct tcp_timewait_sock tw_v6_sk; + struct in6_addr tw_v6_daddr; + struct in6_addr tw_v6_rcv_saddr; +}; + +static inline struct tcp6_timewait_sock *tcp6_twsk(const struct sock *sk) +{ + return (struct tcp6_timewait_sock *)sk; +} + +static inline struct in6_addr *__tcp_v6_rcv_saddr(const struct sock *sk) +{ + return likely(sk->sk_state != TCP_TIME_WAIT) ? + &inet6_sk(sk)->rcv_saddr : &tcp6_twsk(sk)->tw_v6_rcv_saddr; +} + +static inline struct in6_addr *tcp_v6_rcv_saddr(const struct sock *sk) +{ + return sk->sk_family == AF_INET6 ? __tcp_v6_rcv_saddr(sk) : NULL; +} + +static inline int inet_v6_ipv6only(const struct sock *sk) +{ + return likely(sk->sk_state != TCP_TIME_WAIT) ? + ipv6_only_sock(sk) : inet_twsk(sk)->tw_ipv6only; +} #else #define __ipv6_only_sock(sk) 0 #define ipv6_only_sock(sk) 0 @@ -322,8 +357,19 @@ static inline struct raw6_sock *raw6_sk(const struct sock *sk) return NULL; } -#endif +#define __tcp_v6_rcv_saddr(__sk) NULL +#define tcp_v6_rcv_saddr(__sk) NULL +#define tcp_twsk_ipv6only(__sk) 0 +#define inet_v6_ipv6only(__sk) 0 +#endif /* defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) */ -#endif +#define INET6_MATCH(__sk, __saddr, __daddr, __ports, __dif) \ + (((*((__u32 *)&(inet_sk(__sk)->dport))) == (__ports)) && \ + ((__sk)->sk_family == AF_INET6) && \ + ipv6_addr_equal(&inet6_sk(__sk)->daddr, (__saddr)) && \ + ipv6_addr_equal(&inet6_sk(__sk)->rcv_saddr, (__daddr)) && \ + (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) -#endif +#endif /* __KERNEL__ */ + +#endif /* _IPV6_H */ diff --git a/include/linux/klist.h b/include/linux/klist.h index eebf5e5696ec..c4d1fae4dd89 100644 --- a/include/linux/klist.h +++ b/include/linux/klist.h @@ -9,6 +9,9 @@ * This file is rleased under the GPL v2. */ +#ifndef _LINUX_KLIST_H +#define _LINUX_KLIST_H + #include <linux/spinlock.h> #include <linux/completion.h> #include <linux/kref.h> @@ -31,8 +34,8 @@ struct klist_node { struct completion n_removed; }; -extern void klist_add_tail(struct klist * k, struct klist_node * n); -extern void klist_add_head(struct klist * k, struct klist_node * n); +extern void klist_add_tail(struct klist_node * n, struct klist * k); +extern void klist_add_head(struct klist_node * n, struct klist * k); extern void klist_del(struct klist_node * n); extern void klist_remove(struct klist_node * n); @@ -53,3 +56,4 @@ extern void klist_iter_init_node(struct klist * k, struct klist_iter * i, extern void klist_iter_exit(struct klist_iter * i); extern struct klist_node * klist_next(struct klist_iter * i); +#endif diff --git a/include/linux/libata.h b/include/linux/libata.h index 6cd9ba63563b..022105c745fc 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -1,23 +1,26 @@ /* - Copyright 2003-2004 Red Hat, Inc. All rights reserved. - Copyright 2003-2004 Jeff Garzik - - The contents of this file are subject to the Open - Software License version 1.1 that can be found at - http://www.opensource.org/licenses/osl-1.1.txt and is included herein - by reference. - - Alternatively, the contents of this file may be used under the terms - of the GNU General Public License version 2 (the "GPL") as distributed - in the kernel source COPYING file, in which case the provisions of - the GPL are applicable instead of the above. If you wish to allow - the use of your version of this file only under the terms of the - GPL and not to allow others to use your version of this file under - the OSL, indicate your decision by deleting the provisions above and - replace them with the notice and other provisions required by the GPL. - If you do not delete the provisions above, a recipient may use your - version of this file under either the OSL or the GPL. - + * Copyright 2003-2005 Red Hat, Inc. All rights reserved. + * Copyright 2003-2005 Jeff Garzik + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * libata documentation is available via 'make {ps|pdf}docs', + * as Documentation/DocBook/libata.* + * */ #ifndef __LINUX_LIBATA_H__ @@ -37,7 +40,6 @@ #undef ATA_VERBOSE_DEBUG /* yet more debugging output */ #undef ATA_IRQ_TRAP /* define to ack screaming irqs */ #undef ATA_NDEBUG /* define to disable quick runtime checks */ -#undef ATA_ENABLE_ATAPI /* define to enable ATAPI support */ #undef ATA_ENABLE_PATA /* define to enable PATA support in some * low-level drivers */ #undef ATAPI_ENABLE_DMADIR /* enables ATAPI DMADIR bridge support */ @@ -113,6 +115,8 @@ enum { ATA_FLAG_MMIO = (1 << 6), /* use MMIO, not PIO */ ATA_FLAG_SATA_RESET = (1 << 7), /* use COMRESET */ ATA_FLAG_PIO_DMA = (1 << 8), /* PIO cmds via DMA */ + ATA_FLAG_NOINTR = (1 << 9), /* FIXME: Remove this once + * proper HSM is in place. */ ATA_QCFLAG_ACTIVE = (1 << 1), /* cmd not yet ack'd to scsi lyer */ ATA_QCFLAG_SG = (1 << 3), /* have s/g table? */ @@ -363,7 +367,7 @@ struct ata_port_operations { void (*host_stop) (struct ata_host_set *host_set); - void (*bmdma_stop) (struct ata_port *ap); + void (*bmdma_stop) (struct ata_queued_cmd *qc); u8 (*bmdma_status) (struct ata_port *ap); }; @@ -424,7 +428,7 @@ extern void ata_dev_id_string(u16 *id, unsigned char *s, extern void ata_dev_config(struct ata_port *ap, unsigned int i); extern void ata_bmdma_setup (struct ata_queued_cmd *qc); extern void ata_bmdma_start (struct ata_queued_cmd *qc); -extern void ata_bmdma_stop(struct ata_port *ap); +extern void ata_bmdma_stop(struct ata_queued_cmd *qc); extern u8 ata_bmdma_status(struct ata_port *ap); extern void ata_bmdma_irq_clear(struct ata_port *ap); extern void ata_qc_complete(struct ata_queued_cmd *qc, u8 drv_stat); @@ -445,6 +449,7 @@ struct pci_bits { unsigned long val; }; +extern void ata_pci_host_stop (struct ata_host_set *host_set); extern struct ata_probe_ent * ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port); extern int pci_test_config_bits(struct pci_dev *pdev, struct pci_bits *bits); @@ -644,7 +649,7 @@ static inline void scr_write(struct ata_port *ap, unsigned int reg, u32 val) ap->ops->scr_write(ap, reg, val); } -static inline void scr_write_flush(struct ata_port *ap, unsigned int reg, +static inline void scr_write_flush(struct ata_port *ap, unsigned int reg, u32 val) { ap->ops->scr_write(ap, reg, val); diff --git a/include/linux/list.h b/include/linux/list.h index aab2db21b013..e6ec59682274 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -419,6 +419,20 @@ static inline void list_splice_init(struct list_head *list, pos = n, n = list_entry(n->member.next, typeof(*n), member)) /** + * list_for_each_entry_safe_continue - iterate over list of given type + * continuing after existing point safe against removal of list entry + * @pos: the type * to use as a loop counter. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** * list_for_each_rcu - iterate over an rcu-protected list * @pos: the &struct list_head to use as a loop counter. * @head: the head for your list. @@ -620,6 +634,57 @@ static inline void hlist_add_after(struct hlist_node *n, next->next->pprev = &next->next; } +/** + * hlist_add_before_rcu - adds the specified element to the specified hlist + * before the specified node while permitting racing traversals. + * @n: the new element to add to the hash list. + * @next: the existing element to add the new element before. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as hlist_add_head_rcu() + * or hlist_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * hlist_for_each_rcu(), used to prevent memory-consistency + * problems on Alpha CPUs. + */ +static inline void hlist_add_before_rcu(struct hlist_node *n, + struct hlist_node *next) +{ + n->pprev = next->pprev; + n->next = next; + smp_wmb(); + next->pprev = &n->next; + *(n->pprev) = n; +} + +/** + * hlist_add_after_rcu - adds the specified element to the specified hlist + * after the specified node while permitting racing traversals. + * @prev: the existing element to add the new element after. + * @n: the new element to add to the hash list. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as hlist_add_head_rcu() + * or hlist_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * hlist_for_each_rcu(), used to prevent memory-consistency + * problems on Alpha CPUs. + */ +static inline void hlist_add_after_rcu(struct hlist_node *prev, + struct hlist_node *n) +{ + n->next = prev->next; + n->pprev = &prev->next; + smp_wmb(); + prev->next = n; + if (n->next) + n->next->pprev = &n->next; +} + #define hlist_entry(ptr, type, member) container_of(ptr,type,member) #define hlist_for_each(pos, head) \ diff --git a/include/linux/mbcache.h b/include/linux/mbcache.h index 8e5a10410a30..9263d2db2d67 100644 --- a/include/linux/mbcache.h +++ b/include/linux/mbcache.h @@ -29,7 +29,7 @@ struct mb_cache_op { struct mb_cache * mb_cache_create(const char *, struct mb_cache_op *, size_t, int, int); -void mb_cache_shrink(struct mb_cache *, struct block_device *); +void mb_cache_shrink(struct block_device *); void mb_cache_destroy(struct mb_cache *); /* Functions on cache entries */ diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h index 8480aef10e62..94a46f38c532 100644 --- a/include/linux/mempolicy.h +++ b/include/linux/mempolicy.h @@ -150,6 +150,9 @@ void mpol_free_shared_policy(struct shared_policy *p); struct mempolicy *mpol_shared_policy_lookup(struct shared_policy *sp, unsigned long idx); +struct mempolicy *get_vma_policy(struct task_struct *task, + struct vm_area_struct *vma, unsigned long addr); + extern void numa_default_policy(void); extern void numa_policy_init(void); diff --git a/include/linux/mii.h b/include/linux/mii.h index 374b615ea9ea..9b8d0476988a 100644 --- a/include/linux/mii.h +++ b/include/linux/mii.h @@ -22,6 +22,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -54,7 +55,10 @@ #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ -#define BMSR_RESV 0x07c0 /* Unused... */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ @@ -114,6 +118,9 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ + /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ diff --git a/include/linux/mm.h b/include/linux/mm.h index 6eb7f48317f8..82d7024f0765 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -625,10 +625,16 @@ static inline int page_mapped(struct page *page) * Used to decide whether a process gets delivered SIGBUS or * just gets major/minor fault counters bumped up. */ -#define VM_FAULT_OOM (-1) -#define VM_FAULT_SIGBUS 0 -#define VM_FAULT_MINOR 1 -#define VM_FAULT_MAJOR 2 +#define VM_FAULT_OOM 0x00 +#define VM_FAULT_SIGBUS 0x01 +#define VM_FAULT_MINOR 0x02 +#define VM_FAULT_MAJOR 0x03 + +/* + * Special case for get_user_pages. + * Must be in a distinct bit from the above VM_FAULT_ flags. + */ +#define VM_FAULT_WRITE 0x10 #define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) @@ -704,7 +710,13 @@ extern pte_t *FASTCALL(pte_alloc_kernel(struct mm_struct *mm, pmd_t *pmd, unsign extern pte_t *FASTCALL(pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address)); extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot); extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot); -extern int handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access); +extern int __handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access); + +static inline int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, int write_access) +{ + return __handle_mm_fault(mm, vma, address, write_access) & (~VM_FAULT_WRITE); +} + extern int make_pages_present(unsigned long addr, unsigned long end); extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write); void install_arg_page(struct vm_area_struct *, struct page *, unsigned long); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index f90f674eb3b0..30f68c0c8c6e 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -46,6 +46,12 @@ struct mmc_ios { #define MMC_BUSMODE_OPENDRAIN 1 #define MMC_BUSMODE_PUSHPULL 2 + unsigned char chip_select; /* SPI chip select */ + +#define MMC_CS_DONTCARE 0 +#define MMC_CS_HIGH 1 +#define MMC_CS_LOW 2 + unsigned char power_mode; /* power supply mode */ #define MMC_POWER_OFF 0 @@ -63,11 +69,12 @@ struct device; struct mmc_host { struct device *dev; + struct class_device class_dev; + int index; struct mmc_host_ops *ops; unsigned int f_min; unsigned int f_max; u32 ocr_avail; - char host_name[8]; /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ @@ -97,6 +104,7 @@ extern void mmc_free_host(struct mmc_host *); #define mmc_priv(x) ((void *)((x) + 1)) #define mmc_dev(x) ((x)->dev) +#define mmc_hostname(x) ((x)->class_dev.class_id) extern int mmc_suspend_host(struct mmc_host *, pm_message_t); extern int mmc_resume_host(struct mmc_host *); diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index 6c90461ed99f..5ed471b58f4f 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -487,11 +487,27 @@ struct mem_section { unsigned long section_mem_map; }; -extern struct mem_section mem_section[NR_MEM_SECTIONS]; +#ifdef CONFIG_SPARSEMEM_EXTREME +#define SECTIONS_PER_ROOT (PAGE_SIZE / sizeof (struct mem_section)) +#else +#define SECTIONS_PER_ROOT 1 +#endif + +#define SECTION_NR_TO_ROOT(sec) ((sec) / SECTIONS_PER_ROOT) +#define NR_SECTION_ROOTS (NR_MEM_SECTIONS / SECTIONS_PER_ROOT) +#define SECTION_ROOT_MASK (SECTIONS_PER_ROOT - 1) + +#ifdef CONFIG_SPARSEMEM_EXTREME +extern struct mem_section *mem_section[NR_SECTION_ROOTS]; +#else +extern struct mem_section mem_section[NR_SECTION_ROOTS][SECTIONS_PER_ROOT]; +#endif static inline struct mem_section *__nr_to_section(unsigned long nr) { - return &mem_section[nr]; + if (!mem_section[SECTION_NR_TO_ROOT(nr)]) + return NULL; + return &mem_section[SECTION_NR_TO_ROOT(nr)][nr & SECTION_ROOT_MASK]; } /* @@ -513,12 +529,12 @@ static inline struct page *__section_mem_map_addr(struct mem_section *section) static inline int valid_section(struct mem_section *section) { - return (section->section_mem_map & SECTION_MARKED_PRESENT); + return (section && (section->section_mem_map & SECTION_MARKED_PRESENT)); } static inline int section_has_mem_map(struct mem_section *section) { - return (section->section_mem_map & SECTION_HAS_MEM_MAP); + return (section && (section->section_mem_map & SECTION_HAS_MEM_MAP)); } static inline int valid_section_nr(unsigned long nr) @@ -572,6 +588,7 @@ static inline int pfn_valid(unsigned long pfn) void sparse_init(void); #else #define sparse_init() do {} while (0) +#define sparse_index_init(_sec, _nid) do {} while (0) #endif /* CONFIG_SPARSEMEM */ #ifdef CONFIG_NODES_SPAN_OTHER_NODES diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index dce53ac1625d..47da39ba3f03 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -1,6 +1,6 @@ /* * Device tables which are exported to userspace via - * scripts/table2alias.c. You must keep that file in sync with this + * scripts/mod/file2alias.c. You must keep that file in sync with this * header. */ @@ -33,7 +33,8 @@ struct ieee1394_device_id { __u32 model_id; __u32 specifier_id; __u32 version; - kernel_ulong_t driver_data; + kernel_ulong_t driver_data + __attribute__((aligned(sizeof(kernel_ulong_t)))); }; @@ -182,9 +183,18 @@ struct of_device_id char name[32]; char type[32]; char compatible[128]; +#if __KERNEL__ void *data; +#else + kernel_ulong_t data; +#endif }; +/* VIO */ +struct vio_device_id { + char type[32]; + char compat[32]; +}; /* PCMCIA */ @@ -208,7 +218,8 @@ struct pcmcia_device_id { #ifdef __KERNEL__ const char * prod_id[4]; #else - kernel_ulong_t prod_id[4]; + kernel_ulong_t prod_id[4] + __attribute__((aligned(sizeof(kernel_ulong_t)))); #endif /* not matched against */ diff --git a/include/linux/mount.h b/include/linux/mount.h index 74b4727a4e30..f8f39937e301 100644 --- a/include/linux/mount.h +++ b/include/linux/mount.h @@ -12,6 +12,7 @@ #define _LINUX_MOUNT_H #ifdef __KERNEL__ +#include <linux/types.h> #include <linux/list.h> #include <linux/spinlock.h> #include <asm/atomic.h> @@ -76,6 +77,7 @@ extern int do_add_mount(struct vfsmount *newmnt, struct nameidata *nd, extern void mark_mounts_for_expiry(struct list_head *mounts); extern spinlock_t vfsmount_lock; +extern dev_t name_to_dev_t(char *name); #endif #endif /* _LINUX_MOUNT_H */ diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h index 5773ea42f6e4..0b08cd692201 100644 --- a/include/linux/mv643xx.h +++ b/include/linux/mv643xx.h @@ -980,7 +980,7 @@ /* I2C Registers */ /****************************************/ -#define MV64XXX_I2C_CTLR_NAME "mv64xxx i2c" +#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c" #define MV64XXX_I2C_OFFSET 0xc000 #define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020 diff --git a/include/linux/net.h b/include/linux/net.h index 20cb226b2268..4e981585a89a 100644 --- a/include/linux/net.h +++ b/include/linux/net.h @@ -84,6 +84,7 @@ enum sock_type { SOCK_RAW = 3, SOCK_RDM = 4, SOCK_SEQPACKET = 5, + SOCK_DCCP = 6, SOCK_PACKET = 10, }; @@ -282,5 +283,15 @@ static struct proto_ops name##_ops = { \ #define MODULE_ALIAS_NETPROTO(proto) \ MODULE_ALIAS("net-pf-" __stringify(proto)) +#define MODULE_ALIAS_NET_PF_PROTO(pf, proto) \ + MODULE_ALIAS("net-pf-" __stringify(pf) "-proto-" __stringify(proto)) + +#ifdef CONFIG_SYSCTL +#include <linux/sysctl.h> +extern ctl_table net_table[]; +extern int net_msg_cost; +extern int net_msg_burst; +#endif + #endif /* __KERNEL__ */ #endif /* _LINUX_NET_H */ diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 3a0ed7f9e801..7c717907896d 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -244,6 +244,7 @@ struct netdev_boot_setup { }; #define NETDEV_BOOT_SETUP_MAX 8 +extern int __init netdev_boot_setup(char *str); /* * The DEVICE structure. @@ -336,6 +337,7 @@ struct net_device /* Interface address info. */ unsigned char broadcast[MAX_ADDR_LEN]; /* hw bcast add */ unsigned char dev_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned char perm_addr[MAX_ADDR_LEN]; /* permanent hw address */ unsigned char addr_len; /* hardware address length */ unsigned short dev_id; /* for shared network cards */ @@ -497,10 +499,12 @@ static inline void *netdev_priv(struct net_device *dev) #define SET_NETDEV_DEV(net, pdev) ((net)->class_dev.dev = (pdev)) struct packet_type { - __be16 type; /* This is really htons(ether_type). */ - struct net_device *dev; /* NULL is wildcarded here */ - int (*func) (struct sk_buff *, struct net_device *, - struct packet_type *); + __be16 type; /* This is really htons(ether_type). */ + struct net_device *dev; /* NULL is wildcarded here */ + int (*func) (struct sk_buff *, + struct net_device *, + struct packet_type *, + struct net_device *); void *af_packet_priv; struct list_head list; }; @@ -671,6 +675,7 @@ extern void dev_queue_xmit_nit(struct sk_buff *skb, struct net_device *dev); extern void dev_init(void); extern int netdev_nit; +extern int netdev_budget; /* Called by rtnetlink.c:rtnl_unlock() */ extern void netdev_run_todo(void); @@ -697,19 +702,9 @@ static inline int netif_carrier_ok(const struct net_device *dev) extern void __netdev_watchdog_up(struct net_device *dev); -static inline void netif_carrier_on(struct net_device *dev) -{ - if (test_and_clear_bit(__LINK_STATE_NOCARRIER, &dev->state)) - linkwatch_fire_event(dev); - if (netif_running(dev)) - __netdev_watchdog_up(dev); -} +extern void netif_carrier_on(struct net_device *dev); -static inline void netif_carrier_off(struct net_device *dev) -{ - if (!test_and_set_bit(__LINK_STATE_NOCARRIER, &dev->state)) - linkwatch_fire_event(dev); -} +extern void netif_carrier_off(struct net_device *dev); /* Hot-plugging. */ static inline int netif_device_present(struct net_device *dev) @@ -916,6 +911,14 @@ extern int skb_checksum_help(struct sk_buff *skb, int inward); extern void net_enable_timestamp(void); extern void net_disable_timestamp(void); +#ifdef CONFIG_PROC_FS +extern void *dev_seq_start(struct seq_file *seq, loff_t *pos); +extern void *dev_seq_next(struct seq_file *seq, void *v, loff_t *pos); +extern void dev_seq_stop(struct seq_file *seq, void *v); +#endif + +extern void linkwatch_run_queue(void); + #endif /* __KERNEL__ */ #endif /* _LINUX_DEV_H */ diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 2e2045482cb1..be365e70ee99 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -21,10 +21,23 @@ #define NF_STOP 5 #define NF_MAX_VERDICT NF_STOP +/* we overload the higher bits for encoding auxiliary data such as the queue + * number. Not nice, but better than additional function arguments. */ +#define NF_VERDICT_MASK 0x0000ffff +#define NF_VERDICT_BITS 16 + +#define NF_VERDICT_QMASK 0xffff0000 +#define NF_VERDICT_QBITS 16 + +#define NF_QUEUE_NR(x) (((x << NF_VERDICT_QBITS) & NF_VERDICT_QMASK) | NF_QUEUE) + +/* only for userspace compatibility */ +#ifndef __KERNEL__ /* Generic cache responses from hook functions. <= 0x2000 is used for protocol-flags. */ #define NFC_UNKNOWN 0x4000 #define NFC_ALTERED 0x8000 +#endif #ifdef __KERNEL__ #include <linux/config.h> @@ -101,15 +114,51 @@ void nf_unregister_sockopt(struct nf_sockopt_ops *reg); extern struct list_head nf_hooks[NPROTO][NF_MAX_HOOKS]; -typedef void nf_logfn(unsigned int hooknum, +/* those NF_LOG_* defines and struct nf_loginfo are legacy definitios that will + * disappear once iptables is replaced with pkttables. Please DO NOT use them + * for any new code! */ +#define NF_LOG_TCPSEQ 0x01 /* Log TCP sequence numbers */ +#define NF_LOG_TCPOPT 0x02 /* Log TCP options */ +#define NF_LOG_IPOPT 0x04 /* Log IP options */ +#define NF_LOG_UID 0x08 /* Log UID owning local socket */ +#define NF_LOG_MASK 0x0f + +#define NF_LOG_TYPE_LOG 0x01 +#define NF_LOG_TYPE_ULOG 0x02 + +struct nf_loginfo { + u_int8_t type; + union { + struct { + u_int32_t copy_len; + u_int16_t group; + u_int16_t qthreshold; + } ulog; + struct { + u_int8_t level; + u_int8_t logflags; + } log; + } u; +}; + +typedef void nf_logfn(unsigned int pf, + unsigned int hooknum, const struct sk_buff *skb, const struct net_device *in, const struct net_device *out, + const struct nf_loginfo *li, const char *prefix); +struct nf_logger { + struct module *me; + nf_logfn *logfn; + char *name; +}; + /* Function to register/unregister log function. */ -int nf_log_register(int pf, nf_logfn *logfn); -void nf_log_unregister(int pf, nf_logfn *logfn); +int nf_log_register(int pf, struct nf_logger *logger); +int nf_log_unregister_pf(int pf); +void nf_log_unregister_logger(struct nf_logger *logger); /* Calls the registered backend logging function */ void nf_log_packet(int pf, @@ -117,6 +166,7 @@ void nf_log_packet(int pf, const struct sk_buff *skb, const struct net_device *in, const struct net_device *out, + struct nf_loginfo *li, const char *fmt, ...); /* Activate hook; either okfn or kfree_skb called, unless a hook @@ -175,11 +225,16 @@ int nf_getsockopt(struct sock *sk, int pf, int optval, char __user *opt, int *len); /* Packet queuing */ -typedef int (*nf_queue_outfn_t)(struct sk_buff *skb, - struct nf_info *info, void *data); +struct nf_queue_handler { + int (*outfn)(struct sk_buff *skb, struct nf_info *info, + unsigned int queuenum, void *data); + void *data; + char *name; +}; extern int nf_register_queue_handler(int pf, - nf_queue_outfn_t outfn, void *data); + struct nf_queue_handler *qh); extern int nf_unregister_queue_handler(int pf); +extern void nf_unregister_queue_handlers(struct nf_queue_handler *qh); extern void nf_reinject(struct sk_buff *skb, struct nf_info *info, unsigned int verdict); @@ -190,6 +245,27 @@ extern void nf_ct_attach(struct sk_buff *, struct sk_buff *); /* FIXME: Before cache is ever used, this must be implemented for real. */ extern void nf_invalidate_cache(int pf); +/* Call this before modifying an existing packet: ensures it is + modifiable and linear to the point you care about (writable_len). + Returns true or false. */ +extern int skb_make_writable(struct sk_buff **pskb, unsigned int writable_len); + +struct nf_queue_rerouter { + void (*save)(const struct sk_buff *skb, struct nf_info *info); + int (*reroute)(struct sk_buff **skb, const struct nf_info *info); + int rer_size; +}; + +#define nf_info_reroute(x) ((void *)x + sizeof(struct nf_info)) + +extern int nf_register_queue_rerouter(int pf, struct nf_queue_rerouter *rer); +extern int nf_unregister_queue_rerouter(int pf); + +#ifdef CONFIG_PROC_FS +#include <linux/proc_fs.h> +extern struct proc_dir_entry *proc_net_netfilter; +#endif + #else /* !CONFIG_NETFILTER */ #define NF_HOOK(pf, hook, skb, indev, outdev, okfn) (okfn)(skb) static inline void nf_ct_attach(struct sk_buff *new, struct sk_buff *skb) {} diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h new file mode 100644 index 000000000000..1d5b10ae2399 --- /dev/null +++ b/include/linux/netfilter/nfnetlink.h @@ -0,0 +1,169 @@ +#ifndef _NFNETLINK_H +#define _NFNETLINK_H +#include <linux/types.h> + +#ifndef __KERNEL__ +/* nfnetlink groups: Up to 32 maximum - backwards compatibility for userspace */ +#define NF_NETLINK_CONNTRACK_NEW 0x00000001 +#define NF_NETLINK_CONNTRACK_UPDATE 0x00000002 +#define NF_NETLINK_CONNTRACK_DESTROY 0x00000004 +#define NF_NETLINK_CONNTRACK_EXP_NEW 0x00000008 +#define NF_NETLINK_CONNTRACK_EXP_UPDATE 0x00000010 +#define NF_NETLINK_CONNTRACK_EXP_DESTROY 0x00000020 +#endif + +enum nfnetlink_groups { + NFNLGRP_NONE, +#define NFNLGRP_NONE NFNLGRP_NONE + NFNLGRP_CONNTRACK_NEW, +#define NFNLGRP_CONNTRACK_NEW NFNLGRP_CONNTRACK_NEW + NFNLGRP_CONNTRACK_UPDATE, +#define NFNLGRP_CONNTRACK_UPDATE NFNLGRP_CONNTRACK_UPDATE + NFNLGRP_CONNTRACK_DESTROY, +#define NFNLGRP_CONNTRACK_DESTROY NFNLGRP_CONNTRACK_DESTROY + NFNLGRP_CONNTRACK_EXP_NEW, +#define NFNLGRP_CONNTRACK_EXP_NEW NFNLGRP_CONNTRACK_EXP_NEW + NFNLGRP_CONNTRACK_EXP_UPDATE, +#define NFNLGRP_CONNTRACK_EXP_UPDATE NFNLGRP_CONNTRACK_EXP_UPDATE + NFNLGRP_CONNTRACK_EXP_DESTROY, +#define NFNLGRP_CONNTRACK_EXP_DESTROY NFNLGRP_CONNTRACK_EXP_DESTROY + __NFNLGRP_MAX, +}; +#define NFNLGRP_MAX (__NFNLGRP_MAX - 1) + +/* Generic structure for encapsulation optional netfilter information. + * It is reminiscent of sockaddr, but with sa_family replaced + * with attribute type. + * ! This should someday be put somewhere generic as now rtnetlink and + * ! nfnetlink use the same attributes methods. - J. Schulist. + */ + +struct nfattr +{ + u_int16_t nfa_len; + u_int16_t nfa_type; +} __attribute__ ((packed)); + +/* FIXME: Shamelessly copy and pasted from rtnetlink.h, it's time + * to put this in a generic file */ + +#define NFA_ALIGNTO 4 +#define NFA_ALIGN(len) (((len) + NFA_ALIGNTO - 1) & ~(NFA_ALIGNTO - 1)) +#define NFA_OK(nfa,len) ((len) > 0 && (nfa)->nfa_len >= sizeof(struct nfattr) \ + && (nfa)->nfa_len <= (len)) +#define NFA_NEXT(nfa,attrlen) ((attrlen) -= NFA_ALIGN((nfa)->nfa_len), \ + (struct nfattr *)(((char *)(nfa)) + NFA_ALIGN((nfa)->nfa_len))) +#define NFA_LENGTH(len) (NFA_ALIGN(sizeof(struct nfattr)) + (len)) +#define NFA_SPACE(len) NFA_ALIGN(NFA_LENGTH(len)) +#define NFA_DATA(nfa) ((void *)(((char *)(nfa)) + NFA_LENGTH(0))) +#define NFA_PAYLOAD(nfa) ((int)((nfa)->nfa_len) - NFA_LENGTH(0)) +#define NFA_NEST(skb, type) \ +({ struct nfattr *__start = (struct nfattr *) (skb)->tail; \ + NFA_PUT(skb, type, 0, NULL); \ + __start; }) +#define NFA_NEST_END(skb, start) \ +({ (start)->nfa_len = ((skb)->tail - (unsigned char *) (start)); \ + (skb)->len; }) +#define NFA_NEST_CANCEL(skb, start) \ +({ if (start) \ + skb_trim(skb, (unsigned char *) (start) - (skb)->data); \ + -1; }) + +/* General form of address family dependent message. + */ +struct nfgenmsg { + u_int8_t nfgen_family; /* AF_xxx */ + u_int8_t version; /* nfnetlink version */ + u_int16_t res_id; /* resource id */ +} __attribute__ ((packed)); + +#define NFNETLINK_V0 0 + +#define NFM_NFA(n) ((struct nfattr *)(((char *)(n)) \ + + NLMSG_ALIGN(sizeof(struct nfgenmsg)))) +#define NFM_PAYLOAD(n) NLMSG_PAYLOAD(n, sizeof(struct nfgenmsg)) + +/* netfilter netlink message types are split in two pieces: + * 8 bit subsystem, 8bit operation. + */ + +#define NFNL_SUBSYS_ID(x) ((x & 0xff00) >> 8) +#define NFNL_MSG_TYPE(x) (x & 0x00ff) + +/* No enum here, otherwise __stringify() trick of MODULE_ALIAS_NFNL_SUBSYS() + * won't work anymore */ +#define NFNL_SUBSYS_NONE 0 +#define NFNL_SUBSYS_CTNETLINK 1 +#define NFNL_SUBSYS_CTNETLINK_EXP 2 +#define NFNL_SUBSYS_QUEUE 3 +#define NFNL_SUBSYS_ULOG 4 +#define NFNL_SUBSYS_COUNT 5 + +#ifdef __KERNEL__ + +#include <linux/netlink.h> +#include <linux/capability.h> + +struct nfnl_callback +{ + int (*call)(struct sock *nl, struct sk_buff *skb, + struct nlmsghdr *nlh, struct nfattr *cda[], int *errp); + kernel_cap_t cap_required; /* capabilities required for this msg */ + u_int16_t attr_count; /* number of nfattr's */ +}; + +struct nfnetlink_subsystem +{ + const char *name; + __u8 subsys_id; /* nfnetlink subsystem ID */ + __u8 cb_count; /* number of callbacks */ + struct nfnl_callback *cb; /* callback for individual types */ +}; + +extern void __nfa_fill(struct sk_buff *skb, int attrtype, + int attrlen, const void *data); +#define NFA_PUT(skb, attrtype, attrlen, data) \ +({ if (skb_tailroom(skb) < (int)NFA_SPACE(attrlen)) goto nfattr_failure; \ + __nfa_fill(skb, attrtype, attrlen, data); }) + +extern struct semaphore nfnl_sem; + +#define nfnl_shlock() down(&nfnl_sem) +#define nfnl_shlock_nowait() down_trylock(&nfnl_sem) + +#define nfnl_shunlock() do { up(&nfnl_sem); \ + if(nfnl && nfnl->sk_receive_queue.qlen) \ + nfnl->sk_data_ready(nfnl, 0); \ + } while(0) + +extern void nfnl_lock(void); +extern void nfnl_unlock(void); + +extern int nfnetlink_subsys_register(struct nfnetlink_subsystem *n); +extern int nfnetlink_subsys_unregister(struct nfnetlink_subsystem *n); + +extern int nfattr_parse(struct nfattr *tb[], int maxattr, + struct nfattr *nfa, int len); + +#define nfattr_parse_nested(tb, max, nfa) \ + nfattr_parse((tb), (max), NFA_DATA((nfa)), NFA_PAYLOAD((nfa))) + +#define nfattr_bad_size(tb, max, cta_min) \ +({ int __i, __res = 0; \ + for (__i=0; __i<max; __i++) \ + if (tb[__i] && NFA_PAYLOAD(tb[__i]) < cta_min[__i]){ \ + __res = 1; \ + break; \ + } \ + __res; \ +}) + +extern int nfnetlink_send(struct sk_buff *skb, u32 pid, unsigned group, + int echo); +extern int nfnetlink_unicast(struct sk_buff *skb, u_int32_t pid, int flags); + +#define MODULE_ALIAS_NFNL_SUBSYS(subsys) \ + MODULE_ALIAS("nfnetlink-subsys-" __stringify(subsys)) + +#endif /* __KERNEL__ */ +#endif /* _NFNETLINK_H */ diff --git a/include/linux/netfilter/nfnetlink_conntrack.h b/include/linux/netfilter/nfnetlink_conntrack.h new file mode 100644 index 000000000000..5c55751c78e4 --- /dev/null +++ b/include/linux/netfilter/nfnetlink_conntrack.h @@ -0,0 +1,124 @@ +#ifndef _IPCONNTRACK_NETLINK_H +#define _IPCONNTRACK_NETLINK_H +#include <linux/netfilter/nfnetlink.h> + +enum cntl_msg_types { + IPCTNL_MSG_CT_NEW, + IPCTNL_MSG_CT_GET, + IPCTNL_MSG_CT_DELETE, + IPCTNL_MSG_CT_GET_CTRZERO, + + IPCTNL_MSG_MAX +}; + +enum ctnl_exp_msg_types { + IPCTNL_MSG_EXP_NEW, + IPCTNL_MSG_EXP_GET, + IPCTNL_MSG_EXP_DELETE, + + IPCTNL_MSG_EXP_MAX +}; + + +enum ctattr_type { + CTA_UNSPEC, + CTA_TUPLE_ORIG, + CTA_TUPLE_REPLY, + CTA_STATUS, + CTA_PROTOINFO, + CTA_HELP, + CTA_NAT, + CTA_TIMEOUT, + CTA_MARK, + CTA_COUNTERS_ORIG, + CTA_COUNTERS_REPLY, + CTA_USE, + CTA_ID, + __CTA_MAX +}; +#define CTA_MAX (__CTA_MAX - 1) + +enum ctattr_tuple { + CTA_TUPLE_UNSPEC, + CTA_TUPLE_IP, + CTA_TUPLE_PROTO, + __CTA_TUPLE_MAX +}; +#define CTA_TUPLE_MAX (__CTA_TUPLE_MAX - 1) + +enum ctattr_ip { + CTA_IP_UNSPEC, + CTA_IP_V4_SRC, + CTA_IP_V4_DST, + CTA_IP_V6_SRC, + CTA_IP_V6_DST, + __CTA_IP_MAX +}; +#define CTA_IP_MAX (__CTA_IP_MAX - 1) + +enum ctattr_l4proto { + CTA_PROTO_UNSPEC, + CTA_PROTO_NUM, + CTA_PROTO_SRC_PORT, + CTA_PROTO_DST_PORT, + CTA_PROTO_ICMP_ID, + CTA_PROTO_ICMP_TYPE, + CTA_PROTO_ICMP_CODE, + __CTA_PROTO_MAX +}; +#define CTA_PROTO_MAX (__CTA_PROTO_MAX - 1) + +enum ctattr_protoinfo { + CTA_PROTOINFO_UNSPEC, + CTA_PROTOINFO_TCP_STATE, + __CTA_PROTOINFO_MAX +}; +#define CTA_PROTOINFO_MAX (__CTA_PROTOINFO_MAX - 1) + +enum ctattr_counters { + CTA_COUNTERS_UNSPEC, + CTA_COUNTERS_PACKETS, + CTA_COUNTERS_BYTES, + __CTA_COUNTERS_MAX +}; +#define CTA_COUNTERS_MAX (__CTA_COUNTERS_MAX - 1) + +enum ctattr_nat { + CTA_NAT_UNSPEC, + CTA_NAT_MINIP, + CTA_NAT_MAXIP, + CTA_NAT_PROTO, + __CTA_NAT_MAX +}; +#define CTA_NAT_MAX (__CTA_NAT_MAX - 1) + +enum ctattr_protonat { + CTA_PROTONAT_UNSPEC, + CTA_PROTONAT_PORT_MIN, + CTA_PROTONAT_PORT_MAX, + __CTA_PROTONAT_MAX +}; +#define CTA_PROTONAT_MAX (__CTA_PROTONAT_MAX - 1) + +enum ctattr_expect { + CTA_EXPECT_UNSPEC, + CTA_EXPECT_MASTER, + CTA_EXPECT_TUPLE, + CTA_EXPECT_MASK, + CTA_EXPECT_TIMEOUT, + CTA_EXPECT_ID, + CTA_EXPECT_HELP_NAME, + __CTA_EXPECT_MAX +}; +#define CTA_EXPECT_MAX (__CTA_EXPECT_MAX - 1) + +enum ctattr_help { + CTA_HELP_UNSPEC, + CTA_HELP_NAME, + __CTA_HELP_MAX +}; +#define CTA_HELP_MAX (__CTA_HELP_MAX - 1) + +#define CTA_HELP_MAXNAMESIZE 32 + +#endif /* _IPCONNTRACK_NETLINK_H */ diff --git a/include/linux/netfilter/nfnetlink_log.h b/include/linux/netfilter/nfnetlink_log.h new file mode 100644 index 000000000000..b04b03880595 --- /dev/null +++ b/include/linux/netfilter/nfnetlink_log.h @@ -0,0 +1,88 @@ +#ifndef _NFNETLINK_LOG_H +#define _NFNETLINK_LOG_H + +/* This file describes the netlink messages (i.e. 'protocol packets'), + * and not any kind of function definitions. It is shared between kernel and + * userspace. Don't put kernel specific stuff in here */ + +#include <linux/types.h> +#include <linux/netfilter/nfnetlink.h> + +enum nfulnl_msg_types { + NFULNL_MSG_PACKET, /* packet from kernel to userspace */ + NFULNL_MSG_CONFIG, /* connect to a particular queue */ + + NFULNL_MSG_MAX +}; + +struct nfulnl_msg_packet_hdr { + u_int16_t hw_protocol; /* hw protocol (network order) */ + u_int8_t hook; /* netfilter hook */ + u_int8_t _pad; +} __attribute__ ((packed)); + +struct nfulnl_msg_packet_hw { + u_int16_t hw_addrlen; + u_int16_t _pad; + u_int8_t hw_addr[8]; +} __attribute__ ((packed)); + +struct nfulnl_msg_packet_timestamp { + aligned_u64 sec; + aligned_u64 usec; +} __attribute__ ((packed)); + +#define NFULNL_PREFIXLEN 30 /* just like old log target */ + +enum nfulnl_attr_type { + NFULA_UNSPEC, + NFULA_PACKET_HDR, + NFULA_MARK, /* u_int32_t nfmark */ + NFULA_TIMESTAMP, /* nfulnl_msg_packet_timestamp */ + NFULA_IFINDEX_INDEV, /* u_int32_t ifindex */ + NFULA_IFINDEX_OUTDEV, /* u_int32_t ifindex */ + NFULA_IFINDEX_PHYSINDEV, /* u_int32_t ifindex */ + NFULA_IFINDEX_PHYSOUTDEV, /* u_int32_t ifindex */ + NFULA_HWADDR, /* nfulnl_msg_packet_hw */ + NFULA_PAYLOAD, /* opaque data payload */ + NFULA_PREFIX, /* string prefix */ + NFULA_UID, /* user id of socket */ + + __NFULA_MAX +}; +#define NFULA_MAX (__NFULA_MAX - 1) + +enum nfulnl_msg_config_cmds { + NFULNL_CFG_CMD_NONE, + NFULNL_CFG_CMD_BIND, + NFULNL_CFG_CMD_UNBIND, + NFULNL_CFG_CMD_PF_BIND, + NFULNL_CFG_CMD_PF_UNBIND, +}; + +struct nfulnl_msg_config_cmd { + u_int8_t command; /* nfulnl_msg_config_cmds */ +} __attribute__ ((packed)); + +struct nfulnl_msg_config_mode { + u_int32_t copy_range; + u_int8_t copy_mode; + u_int8_t _pad; +} __attribute__ ((packed)); + +enum nfulnl_attr_config { + NFULA_CFG_UNSPEC, + NFULA_CFG_CMD, /* nfulnl_msg_config_cmd */ + NFULA_CFG_MODE, /* nfulnl_msg_config_mode */ + NFULA_CFG_NLBUFSIZ, /* u_int32_t buffer size */ + NFULA_CFG_TIMEOUT, /* u_int32_t in 1/100 s */ + NFULA_CFG_QTHRESH, /* u_int32_t */ + __NFULA_CFG_MAX +}; +#define NFULA_CFG_MAX (__NFULA_CFG_MAX -1) + +#define NFULNL_COPY_NONE 0x00 +#define NFULNL_COPY_META 0x01 +#define NFULNL_COPY_PACKET 0x02 + +#endif /* _NFNETLINK_LOG_H */ diff --git a/include/linux/netfilter/nfnetlink_queue.h b/include/linux/netfilter/nfnetlink_queue.h new file mode 100644 index 000000000000..9e774373244c --- /dev/null +++ b/include/linux/netfilter/nfnetlink_queue.h @@ -0,0 +1,89 @@ +#ifndef _NFNETLINK_QUEUE_H +#define _NFNETLINK_QUEUE_H + +#include <linux/types.h> +#include <linux/netfilter/nfnetlink.h> + +enum nfqnl_msg_types { + NFQNL_MSG_PACKET, /* packet from kernel to userspace */ + NFQNL_MSG_VERDICT, /* verdict from userspace to kernel */ + NFQNL_MSG_CONFIG, /* connect to a particular queue */ + + NFQNL_MSG_MAX +}; + +struct nfqnl_msg_packet_hdr { + u_int32_t packet_id; /* unique ID of packet in queue */ + u_int16_t hw_protocol; /* hw protocol (network order) */ + u_int8_t hook; /* netfilter hook */ +} __attribute__ ((packed)); + +struct nfqnl_msg_packet_hw { + u_int16_t hw_addrlen; + u_int16_t _pad; + u_int8_t hw_addr[8]; +} __attribute__ ((packed)); + +struct nfqnl_msg_packet_timestamp { + aligned_u64 sec; + aligned_u64 usec; +} __attribute__ ((packed)); + +enum nfqnl_attr_type { + NFQA_UNSPEC, + NFQA_PACKET_HDR, + NFQA_VERDICT_HDR, /* nfqnl_msg_verdict_hrd */ + NFQA_MARK, /* u_int32_t nfmark */ + NFQA_TIMESTAMP, /* nfqnl_msg_packet_timestamp */ + NFQA_IFINDEX_INDEV, /* u_int32_t ifindex */ + NFQA_IFINDEX_OUTDEV, /* u_int32_t ifindex */ + NFQA_IFINDEX_PHYSINDEV, /* u_int32_t ifindex */ + NFQA_IFINDEX_PHYSOUTDEV, /* u_int32_t ifindex */ + NFQA_HWADDR, /* nfqnl_msg_packet_hw */ + NFQA_PAYLOAD, /* opaque data payload */ + + __NFQA_MAX +}; +#define NFQA_MAX (__NFQA_MAX - 1) + +struct nfqnl_msg_verdict_hdr { + u_int32_t verdict; + u_int32_t id; +} __attribute__ ((packed)); + + +enum nfqnl_msg_config_cmds { + NFQNL_CFG_CMD_NONE, + NFQNL_CFG_CMD_BIND, + NFQNL_CFG_CMD_UNBIND, + NFQNL_CFG_CMD_PF_BIND, + NFQNL_CFG_CMD_PF_UNBIND, +}; + +struct nfqnl_msg_config_cmd { + u_int8_t command; /* nfqnl_msg_config_cmds */ + u_int8_t _pad; + u_int16_t pf; /* AF_xxx for PF_[UN]BIND */ +} __attribute__ ((packed)); + +enum nfqnl_config_mode { + NFQNL_COPY_NONE, + NFQNL_COPY_META, + NFQNL_COPY_PACKET, +}; + +struct nfqnl_msg_config_params { + u_int32_t copy_range; + u_int8_t copy_mode; /* enum nfqnl_config_mode */ +} __attribute__ ((packed)); + + +enum nfqnl_attr_config { + NFQA_CFG_UNSPEC, + NFQA_CFG_CMD, /* nfqnl_msg_config_cmd */ + NFQA_CFG_PARAMS, /* nfqnl_msg_config_params */ + __NFQA_CFG_MAX +}; +#define NFQA_CFG_MAX (__NFQA_CFG_MAX-1) + +#endif /* _NFNETLINK_QUEUE_H */ diff --git a/include/linux/netfilter_decnet.h b/include/linux/netfilter_decnet.h index 3064eec9cb8e..6f425369ee29 100644 --- a/include/linux/netfilter_decnet.h +++ b/include/linux/netfilter_decnet.h @@ -9,6 +9,8 @@ #include <linux/netfilter.h> +/* only for userspace compatibility */ +#ifndef __KERNEL__ /* IP Cache bits. */ /* Src IP address. */ #define NFC_DN_SRC 0x0001 @@ -18,6 +20,7 @@ #define NFC_DN_IF_IN 0x0004 /* Output device. */ #define NFC_DN_IF_OUT 0x0008 +#endif /* ! __KERNEL__ */ /* DECnet Hooks */ /* After promisc drops, checksum checks. */ @@ -53,7 +56,21 @@ struct nf_dn_rtmsg { #define NFDN_RTMSG(r) ((unsigned char *)(r) + NLMSG_ALIGN(sizeof(struct nf_dn_rtmsg))) +#ifndef __KERNEL__ +/* backwards compatibility for userspace */ #define DNRMG_L1_GROUP 0x01 #define DNRMG_L2_GROUP 0x02 +#endif + +enum { + DNRNG_NLGRP_NONE, +#define DNRNG_NLGRP_NONE DNRNG_NLGRP_NONE + DNRNG_NLGRP_L1, +#define DNRNG_NLGRP_L1 DNRNG_NLGRP_L1 + DNRNG_NLGRP_L2, +#define DNRNG_NLGRP_L2 DNRNG_NLGRP_L2 + __DNRNG_NLGRP_MAX +}; +#define DNRNG_NLGRP_MAX (__DNRNG_NLGRP_MAX - 1) #endif /*__LINUX_DECNET_NETFILTER_H*/ diff --git a/include/linux/netfilter_ipv4.h b/include/linux/netfilter_ipv4.h index 3ebc36afae1a..fdc4a9527343 100644 --- a/include/linux/netfilter_ipv4.h +++ b/include/linux/netfilter_ipv4.h @@ -8,6 +8,8 @@ #include <linux/config.h> #include <linux/netfilter.h> +/* only for userspace compatibility */ +#ifndef __KERNEL__ /* IP Cache bits. */ /* Src IP address. */ #define NFC_IP_SRC 0x0001 @@ -35,6 +37,7 @@ #define NFC_IP_DST_PT 0x0400 /* Something else about the proto */ #define NFC_IP_PROTO_UNKNOWN 0x2000 +#endif /* ! __KERNEL__ */ /* IP Hooks */ /* After promisc drops, checksum checks. */ @@ -77,11 +80,6 @@ enum nf_ip_hook_priorities { #ifdef __KERNEL__ extern int ip_route_me_harder(struct sk_buff **pskb); -/* Call this before modifying an existing IP packet: ensures it is - modifiable and linear to the point you care about (writable_len). - Returns true or false. */ -extern int skb_ip_make_writable(struct sk_buff **pskb, - unsigned int writable_len); #endif /*__KERNEL__*/ #endif /*__LINUX_IP_NETFILTER_H*/ diff --git a/include/linux/netfilter_ipv4/ip_conntrack.h b/include/linux/netfilter_ipv4/ip_conntrack.h index 3781192ce159..088742befe49 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack.h +++ b/include/linux/netfilter_ipv4/ip_conntrack.h @@ -65,6 +65,63 @@ enum ip_conntrack_status { /* Both together */ IPS_NAT_DONE_MASK = (IPS_DST_NAT_DONE | IPS_SRC_NAT_DONE), + + /* Connection is dying (removed from lists), can not be unset. */ + IPS_DYING_BIT = 9, + IPS_DYING = (1 << IPS_DYING_BIT), +}; + +/* Connection tracking event bits */ +enum ip_conntrack_events +{ + /* New conntrack */ + IPCT_NEW_BIT = 0, + IPCT_NEW = (1 << IPCT_NEW_BIT), + + /* Expected connection */ + IPCT_RELATED_BIT = 1, + IPCT_RELATED = (1 << IPCT_RELATED_BIT), + + /* Destroyed conntrack */ + IPCT_DESTROY_BIT = 2, + IPCT_DESTROY = (1 << IPCT_DESTROY_BIT), + + /* Timer has been refreshed */ + IPCT_REFRESH_BIT = 3, + IPCT_REFRESH = (1 << IPCT_REFRESH_BIT), + + /* Status has changed */ + IPCT_STATUS_BIT = 4, + IPCT_STATUS = (1 << IPCT_STATUS_BIT), + + /* Update of protocol info */ + IPCT_PROTOINFO_BIT = 5, + IPCT_PROTOINFO = (1 << IPCT_PROTOINFO_BIT), + + /* Volatile protocol info */ + IPCT_PROTOINFO_VOLATILE_BIT = 6, + IPCT_PROTOINFO_VOLATILE = (1 << IPCT_PROTOINFO_VOLATILE_BIT), + + /* New helper for conntrack */ + IPCT_HELPER_BIT = 7, + IPCT_HELPER = (1 << IPCT_HELPER_BIT), + + /* Update of helper info */ + IPCT_HELPINFO_BIT = 8, + IPCT_HELPINFO = (1 << IPCT_HELPINFO_BIT), + + /* Volatile helper info */ + IPCT_HELPINFO_VOLATILE_BIT = 9, + IPCT_HELPINFO_VOLATILE = (1 << IPCT_HELPINFO_VOLATILE_BIT), + + /* NAT info */ + IPCT_NATINFO_BIT = 10, + IPCT_NATINFO = (1 << IPCT_NATINFO_BIT), +}; + +enum ip_conntrack_expect_events { + IPEXP_NEW_BIT = 0, + IPEXP_NEW = (1 << IPEXP_NEW_BIT), }; #ifdef __KERNEL__ @@ -152,6 +209,9 @@ struct ip_conntrack /* Current number of expected connections */ unsigned int expecting; + /* Unique ID that identifies this conntrack*/ + unsigned int id; + /* Helper, if any. */ struct ip_conntrack_helper *helper; @@ -171,7 +231,7 @@ struct ip_conntrack #endif /* CONFIG_IP_NF_NAT_NEEDED */ #if defined(CONFIG_IP_NF_CONNTRACK_MARK) - unsigned long mark; + u_int32_t mark; #endif /* Traversed often, so hopefully in different cacheline to top */ @@ -197,6 +257,12 @@ struct ip_conntrack_expect /* Timer function; deletes the expectation. */ struct timer_list timeout; + /* Usage count. */ + atomic_t use; + + /* Unique ID */ + unsigned int id; + #ifdef CONFIG_IP_NF_NAT_NEEDED /* This is the original per-proto part, used to map the * expected connection the way the recipient expects. */ @@ -236,7 +302,12 @@ ip_conntrack_get(const struct sk_buff *skb, enum ip_conntrack_info *ctinfo) } /* decrement reference count on a conntrack */ -extern inline void ip_conntrack_put(struct ip_conntrack *ct); +static inline void +ip_conntrack_put(struct ip_conntrack *ct) +{ + IP_NF_ASSERT(ct); + nf_conntrack_put(&ct->ct_general); +} /* call to create an explicit dependency on ip_conntrack. */ extern void need_ip_conntrack(void); @@ -271,12 +342,50 @@ extern void ip_ct_iterate_cleanup(int (*iter)(struct ip_conntrack *i, void *data), void *data); +extern struct ip_conntrack_helper * +__ip_conntrack_helper_find_byname(const char *); +extern struct ip_conntrack_helper * +ip_conntrack_helper_find_get(const struct ip_conntrack_tuple *tuple); +extern void ip_conntrack_helper_put(struct ip_conntrack_helper *helper); + +extern struct ip_conntrack_protocol * +__ip_conntrack_proto_find(u_int8_t protocol); +extern struct ip_conntrack_protocol * +ip_conntrack_proto_find_get(u_int8_t protocol); +extern void ip_conntrack_proto_put(struct ip_conntrack_protocol *proto); + +extern void ip_ct_remove_expectations(struct ip_conntrack *ct); + +extern struct ip_conntrack *ip_conntrack_alloc(struct ip_conntrack_tuple *, + struct ip_conntrack_tuple *); + +extern void ip_conntrack_free(struct ip_conntrack *ct); + +extern void ip_conntrack_hash_insert(struct ip_conntrack *ct); + +extern struct ip_conntrack_expect * +__ip_conntrack_expect_find(const struct ip_conntrack_tuple *tuple); + +extern struct ip_conntrack_expect * +ip_conntrack_expect_find_get(const struct ip_conntrack_tuple *tuple); + +extern struct ip_conntrack_tuple_hash * +__ip_conntrack_find(const struct ip_conntrack_tuple *tuple, + const struct ip_conntrack *ignored_conntrack); + +extern void ip_conntrack_flush(void); + /* It's confirmed if it is, or has been in the hash table. */ static inline int is_confirmed(struct ip_conntrack *ct) { return test_bit(IPS_CONFIRMED_BIT, &ct->status); } +static inline int is_dying(struct ip_conntrack *ct) +{ + return test_bit(IPS_DYING_BIT, &ct->status); +} + extern unsigned int ip_conntrack_htable_size; struct ip_conntrack_stat @@ -300,6 +409,85 @@ struct ip_conntrack_stat #define CONNTRACK_STAT_INC(count) (__get_cpu_var(ip_conntrack_stat).count++) +#ifdef CONFIG_IP_NF_CONNTRACK_EVENTS +#include <linux/notifier.h> +#include <linux/interrupt.h> + +struct ip_conntrack_ecache { + struct ip_conntrack *ct; + unsigned int events; +}; +DECLARE_PER_CPU(struct ip_conntrack_ecache, ip_conntrack_ecache); + +#define CONNTRACK_ECACHE(x) (__get_cpu_var(ip_conntrack_ecache).x) + +extern struct notifier_block *ip_conntrack_chain; +extern struct notifier_block *ip_conntrack_expect_chain; + +static inline int ip_conntrack_register_notifier(struct notifier_block *nb) +{ + return notifier_chain_register(&ip_conntrack_chain, nb); +} + +static inline int ip_conntrack_unregister_notifier(struct notifier_block *nb) +{ + return notifier_chain_unregister(&ip_conntrack_chain, nb); +} + +static inline int +ip_conntrack_expect_register_notifier(struct notifier_block *nb) +{ + return notifier_chain_register(&ip_conntrack_expect_chain, nb); +} + +static inline int +ip_conntrack_expect_unregister_notifier(struct notifier_block *nb) +{ + return notifier_chain_unregister(&ip_conntrack_expect_chain, nb); +} + +extern void ip_ct_deliver_cached_events(const struct ip_conntrack *ct); +extern void __ip_ct_event_cache_init(struct ip_conntrack *ct); + +static inline void +ip_conntrack_event_cache(enum ip_conntrack_events event, + const struct sk_buff *skb) +{ + struct ip_conntrack *ct = (struct ip_conntrack *)skb->nfct; + struct ip_conntrack_ecache *ecache; + + local_bh_disable(); + ecache = &__get_cpu_var(ip_conntrack_ecache); + if (ct != ecache->ct) + __ip_ct_event_cache_init(ct); + ecache->events |= event; + local_bh_enable(); +} + +static inline void ip_conntrack_event(enum ip_conntrack_events event, + struct ip_conntrack *ct) +{ + if (is_confirmed(ct) && !is_dying(ct)) + notifier_call_chain(&ip_conntrack_chain, event, ct); +} + +static inline void +ip_conntrack_expect_event(enum ip_conntrack_expect_events event, + struct ip_conntrack_expect *exp) +{ + notifier_call_chain(&ip_conntrack_expect_chain, event, exp); +} +#else /* CONFIG_IP_NF_CONNTRACK_EVENTS */ +static inline void ip_conntrack_event_cache(enum ip_conntrack_events event, + const struct sk_buff *skb) {} +static inline void ip_conntrack_event(enum ip_conntrack_events event, + struct ip_conntrack *ct) {} +static inline void ip_ct_deliver_cached_events(const struct ip_conntrack *ct) {} +static inline void +ip_conntrack_expect_event(enum ip_conntrack_expect_events event, + struct ip_conntrack_expect *exp) {} +#endif /* CONFIG_IP_NF_CONNTRACK_EVENTS */ + #ifdef CONFIG_IP_NF_NAT_NEEDED static inline int ip_nat_initialized(struct ip_conntrack *conntrack, enum ip_nat_manip_type manip) diff --git a/include/linux/netfilter_ipv4/ip_conntrack_core.h b/include/linux/netfilter_ipv4/ip_conntrack_core.h index 694aec9b4784..dc4d2a0575de 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_core.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_core.h @@ -2,6 +2,9 @@ #define _IP_CONNTRACK_CORE_H #include <linux/netfilter.h> +#define MAX_IP_CT_PROTO 256 +extern struct ip_conntrack_protocol *ip_ct_protos[MAX_IP_CT_PROTO]; + /* This header is used to share core functionality between the standalone connection tracking module, and the compatibility layer's use of connection tracking. */ @@ -38,12 +41,19 @@ extern int __ip_conntrack_confirm(struct sk_buff **pskb); /* Confirm a connection: returns NF_DROP if packet must be dropped. */ static inline int ip_conntrack_confirm(struct sk_buff **pskb) { - if ((*pskb)->nfct - && !is_confirmed((struct ip_conntrack *)(*pskb)->nfct)) - return __ip_conntrack_confirm(pskb); - return NF_ACCEPT; + struct ip_conntrack *ct = (struct ip_conntrack *)(*pskb)->nfct; + int ret = NF_ACCEPT; + + if (ct) { + if (!is_confirmed(ct)) + ret = __ip_conntrack_confirm(pskb); + ip_ct_deliver_cached_events(ct); + } + return ret; } +extern void __ip_ct_expect_unlink_destroy(struct ip_conntrack_expect *exp); + extern struct list_head *ip_conntrack_hash; extern struct list_head ip_conntrack_expect_list; extern rwlock_t ip_conntrack_lock; diff --git a/include/linux/netfilter_ipv4/ip_conntrack_helper.h b/include/linux/netfilter_ipv4/ip_conntrack_helper.h index b1bbba0a12cb..8d69279ccfe4 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_helper.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_helper.h @@ -24,15 +24,18 @@ struct ip_conntrack_helper int (*help)(struct sk_buff **pskb, struct ip_conntrack *ct, enum ip_conntrack_info conntrackinfo); + + int (*to_nfattr)(struct sk_buff *skb, const struct ip_conntrack *ct); }; extern int ip_conntrack_helper_register(struct ip_conntrack_helper *); extern void ip_conntrack_helper_unregister(struct ip_conntrack_helper *); /* Allocate space for an expectation: this is mandatory before calling - ip_conntrack_expect_related. */ -extern struct ip_conntrack_expect *ip_conntrack_expect_alloc(void); -extern void ip_conntrack_expect_free(struct ip_conntrack_expect *exp); + ip_conntrack_expect_related. You will have to call put afterwards. */ +extern struct ip_conntrack_expect * +ip_conntrack_expect_alloc(struct ip_conntrack *master); +extern void ip_conntrack_expect_put(struct ip_conntrack_expect *exp); /* Add an expected connection: can have more than one per connection */ extern int ip_conntrack_expect_related(struct ip_conntrack_expect *exp); diff --git a/include/linux/netfilter_ipv4/ip_conntrack_protocol.h b/include/linux/netfilter_ipv4/ip_conntrack_protocol.h index e20b57c5e1b7..b6b99be8632a 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_protocol.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_protocol.h @@ -2,6 +2,7 @@ #ifndef _IP_CONNTRACK_PROTOCOL_H #define _IP_CONNTRACK_PROTOCOL_H #include <linux/netfilter_ipv4/ip_conntrack.h> +#include <linux/netfilter/nfnetlink_conntrack.h> struct seq_file; @@ -47,22 +48,22 @@ struct ip_conntrack_protocol int (*error)(struct sk_buff *skb, enum ip_conntrack_info *ctinfo, unsigned int hooknum); + /* convert protoinfo to nfnetink attributes */ + int (*to_nfattr)(struct sk_buff *skb, struct nfattr *nfa, + const struct ip_conntrack *ct); + + int (*tuple_to_nfattr)(struct sk_buff *skb, + const struct ip_conntrack_tuple *t); + int (*nfattr_to_tuple)(struct nfattr *tb[], + struct ip_conntrack_tuple *t); + /* Module (if any) which this is connected to. */ struct module *me; }; -#define MAX_IP_CT_PROTO 256 -extern struct ip_conntrack_protocol *ip_ct_protos[MAX_IP_CT_PROTO]; - /* Protocol registration. */ extern int ip_conntrack_protocol_register(struct ip_conntrack_protocol *proto); extern void ip_conntrack_protocol_unregister(struct ip_conntrack_protocol *proto); - -static inline struct ip_conntrack_protocol *ip_ct_find_proto(u_int8_t protocol) -{ - return ip_ct_protos[protocol]; -} - /* Existing built-in protocols */ extern struct ip_conntrack_protocol ip_conntrack_protocol_tcp; extern struct ip_conntrack_protocol ip_conntrack_protocol_udp; @@ -73,6 +74,11 @@ extern int ip_conntrack_protocol_tcp_init(void); /* Log invalid packets */ extern unsigned int ip_ct_log_invalid; +extern int ip_ct_port_tuple_to_nfattr(struct sk_buff *, + const struct ip_conntrack_tuple *); +extern int ip_ct_port_nfattr_to_tuple(struct nfattr *tb[], + struct ip_conntrack_tuple *); + #ifdef CONFIG_SYSCTL #ifdef DEBUG_INVALID_PACKETS #define LOG_INVALID(proto) \ diff --git a/include/linux/netfilter_ipv4/ip_logging.h b/include/linux/netfilter_ipv4/ip_logging.h deleted file mode 100644 index 0c5c52cb6589..000000000000 --- a/include/linux/netfilter_ipv4/ip_logging.h +++ /dev/null @@ -1,20 +0,0 @@ -/* IPv4 macros for the internal logging interface. */ -#ifndef __IP_LOGGING_H -#define __IP_LOGGING_H - -#ifdef __KERNEL__ -#include <linux/socket.h> -#include <linux/netfilter_logging.h> - -#define nf_log_ip_packet(pskb,hooknum,in,out,fmt,args...) \ - nf_log_packet(AF_INET,pskb,hooknum,in,out,fmt,##args) - -#define nf_log_ip(pfh,len,fmt,args...) \ - nf_log(AF_INET,pfh,len,fmt,##args) - -#define nf_ip_log_register(logging) nf_log_register(AF_INET,logging) -#define nf_ip_log_unregister(logging) nf_log_unregister(AF_INET,logging) - -#endif /*__KERNEL__*/ - -#endif /*__IP_LOGGING_H*/ diff --git a/include/linux/netfilter_ipv4/ip_nat_protocol.h b/include/linux/netfilter_ipv4/ip_nat_protocol.h index 129708c22386..ef63aa991a06 100644 --- a/include/linux/netfilter_ipv4/ip_nat_protocol.h +++ b/include/linux/netfilter_ipv4/ip_nat_protocol.h @@ -4,6 +4,9 @@ #include <linux/init.h> #include <linux/list.h> +#include <linux/netfilter_ipv4/ip_nat.h> +#include <linux/netfilter/nfnetlink_conntrack.h> + struct iphdr; struct ip_nat_range; @@ -15,6 +18,8 @@ struct ip_nat_protocol /* Protocol number. */ unsigned int protonum; + struct module *me; + /* Translate a packet to the target according to manip type. Return true if succeeded. */ int (*manip_pkt)(struct sk_buff **pskb, @@ -43,19 +48,20 @@ struct ip_nat_protocol unsigned int (*print_range)(char *buffer, const struct ip_nat_range *range); -}; -#define MAX_IP_NAT_PROTO 256 -extern struct ip_nat_protocol *ip_nat_protos[MAX_IP_NAT_PROTO]; + int (*range_to_nfattr)(struct sk_buff *skb, + const struct ip_nat_range *range); + + int (*nfattr_to_range)(struct nfattr *tb[], + struct ip_nat_range *range); +}; /* Protocol registration. */ extern int ip_nat_protocol_register(struct ip_nat_protocol *proto); extern void ip_nat_protocol_unregister(struct ip_nat_protocol *proto); -static inline struct ip_nat_protocol *ip_nat_find_proto(u_int8_t protocol) -{ - return ip_nat_protos[protocol]; -} +extern struct ip_nat_protocol *ip_nat_proto_find_get(u_int8_t protocol); +extern void ip_nat_proto_put(struct ip_nat_protocol *proto); /* Built-in protocols. */ extern struct ip_nat_protocol ip_nat_protocol_tcp; @@ -67,4 +73,9 @@ extern int init_protocols(void) __init; extern void cleanup_protocols(void); extern struct ip_nat_protocol *find_nat_proto(u_int16_t protonum); +extern int ip_nat_port_range_to_nfattr(struct sk_buff *skb, + const struct ip_nat_range *range); +extern int ip_nat_port_nfattr_to_range(struct nfattr *tb[], + struct ip_nat_range *range); + #endif /*_IP_NAT_PROTO_H*/ diff --git a/include/linux/netfilter_ipv4/ip_tables.h b/include/linux/netfilter_ipv4/ip_tables.h index 12ce47808e7d..d19d65cf4530 100644 --- a/include/linux/netfilter_ipv4/ip_tables.h +++ b/include/linux/netfilter_ipv4/ip_tables.h @@ -109,7 +109,8 @@ struct ipt_counters /* Values for "flag" field in struct ipt_ip (general ip structure). */ #define IPT_F_FRAG 0x01 /* Set if rule is a fragment rule */ -#define IPT_F_MASK 0x01 /* All possible flag bits mask. */ +#define IPT_F_GOTO 0x02 /* Set if jump is a goto */ +#define IPT_F_MASK 0x03 /* All possible flag bits mask. */ /* Values for "inv" field in struct ipt_ip. */ #define IPT_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ diff --git a/include/linux/netfilter_ipv4/ipt_LOG.h b/include/linux/netfilter_ipv4/ipt_LOG.h index d25f782e57d1..22d16177319b 100644 --- a/include/linux/netfilter_ipv4/ipt_LOG.h +++ b/include/linux/netfilter_ipv4/ipt_LOG.h @@ -1,6 +1,7 @@ #ifndef _IPT_LOG_H #define _IPT_LOG_H +/* make sure not to change this without changing netfilter.h:NF_LOG_* (!) */ #define IPT_LOG_TCPSEQ 0x01 /* Log TCP sequence numbers */ #define IPT_LOG_TCPOPT 0x02 /* Log TCP options */ #define IPT_LOG_IPOPT 0x04 /* Log IP options */ diff --git a/include/linux/netfilter_ipv4/ipt_NFQUEUE.h b/include/linux/netfilter_ipv4/ipt_NFQUEUE.h new file mode 100644 index 000000000000..b5b2943b0c66 --- /dev/null +++ b/include/linux/netfilter_ipv4/ipt_NFQUEUE.h @@ -0,0 +1,16 @@ +/* iptables module for using NFQUEUE mechanism + * + * (C) 2005 Harald Welte <laforge@netfilter.org> + * + * This software is distributed under GNU GPL v2, 1991 + * +*/ +#ifndef _IPT_NFQ_TARGET_H +#define _IPT_NFQ_TARGET_H + +/* target info */ +struct ipt_NFQ_info { + u_int16_t queuenum; +}; + +#endif /* _IPT_DSCP_TARGET_H */ diff --git a/include/linux/netfilter_ipv4/ipt_TTL.h b/include/linux/netfilter_ipv4/ipt_TTL.h new file mode 100644 index 000000000000..ee6611edc112 --- /dev/null +++ b/include/linux/netfilter_ipv4/ipt_TTL.h @@ -0,0 +1,21 @@ +/* TTL modification module for IP tables + * (C) 2000 by Harald Welte <laforge@netfilter.org> */ + +#ifndef _IPT_TTL_H +#define _IPT_TTL_H + +enum { + IPT_TTL_SET = 0, + IPT_TTL_INC, + IPT_TTL_DEC +}; + +#define IPT_TTL_MAXMODE IPT_TTL_DEC + +struct ipt_TTL_info { + u_int8_t mode; + u_int8_t ttl; +}; + + +#endif diff --git a/include/linux/netfilter_ipv4/ipt_connbytes.h b/include/linux/netfilter_ipv4/ipt_connbytes.h new file mode 100644 index 000000000000..9e5532f8d8ac --- /dev/null +++ b/include/linux/netfilter_ipv4/ipt_connbytes.h @@ -0,0 +1,25 @@ +#ifndef _IPT_CONNBYTES_H +#define _IPT_CONNBYTES_H + +enum ipt_connbytes_what { + IPT_CONNBYTES_PKTS, + IPT_CONNBYTES_BYTES, + IPT_CONNBYTES_AVGPKT, +}; + +enum ipt_connbytes_direction { + IPT_CONNBYTES_DIR_ORIGINAL, + IPT_CONNBYTES_DIR_REPLY, + IPT_CONNBYTES_DIR_BOTH, +}; + +struct ipt_connbytes_info +{ + struct { + aligned_u64 from; /* count to be matched */ + aligned_u64 to; /* count to be matched */ + } count; + u_int8_t what; /* ipt_connbytes_what */ + u_int8_t direction; /* ipt_connbytes_direction */ +}; +#endif diff --git a/include/linux/netfilter_ipv4/ipt_dccp.h b/include/linux/netfilter_ipv4/ipt_dccp.h new file mode 100644 index 000000000000..3cb3a522e62b --- /dev/null +++ b/include/linux/netfilter_ipv4/ipt_dccp.h @@ -0,0 +1,23 @@ +#ifndef _IPT_DCCP_H_ +#define _IPT_DCCP_H_ + +#define IPT_DCCP_SRC_PORTS 0x01 +#define IPT_DCCP_DEST_PORTS 0x02 +#define IPT_DCCP_TYPE 0x04 +#define IPT_DCCP_OPTION 0x08 + +#define IPT_DCCP_VALID_FLAGS 0x0f + +struct ipt_dccp_info { + u_int16_t dpts[2]; /* Min, Max */ + u_int16_t spts[2]; /* Min, Max */ + + u_int16_t flags; + u_int16_t invflags; + + u_int16_t typemask; + u_int8_t option; +}; + +#endif /* _IPT_DCCP_H_ */ + diff --git a/include/linux/netfilter_ipv4/ipt_string.h b/include/linux/netfilter_ipv4/ipt_string.h new file mode 100644 index 000000000000..a265f6e44eab --- /dev/null +++ b/include/linux/netfilter_ipv4/ipt_string.h @@ -0,0 +1,18 @@ +#ifndef _IPT_STRING_H +#define _IPT_STRING_H + +#define IPT_STRING_MAX_PATTERN_SIZE 128 +#define IPT_STRING_MAX_ALGO_NAME_SIZE 16 + +struct ipt_string_info +{ + u_int16_t from_offset; + u_int16_t to_offset; + char algo[IPT_STRING_MAX_ALGO_NAME_SIZE]; + char pattern[IPT_STRING_MAX_PATTERN_SIZE]; + u_int8_t patlen; + u_int8_t invert; + struct ts_config __attribute__((aligned(8))) *config; +}; + +#endif /*_IPT_STRING_H*/ diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h index bee7a5ec7c66..edcc2c6eb5c7 100644 --- a/include/linux/netfilter_ipv6.h +++ b/include/linux/netfilter_ipv6.h @@ -10,6 +10,8 @@ #include <linux/netfilter.h> +/* only for userspace compatibility */ +#ifndef __KERNEL__ /* IP Cache bits. */ /* Src IP address. */ #define NFC_IP6_SRC 0x0001 @@ -38,6 +40,7 @@ #define NFC_IP6_DST_PT 0x0400 /* Something else about the proto */ #define NFC_IP6_PROTO_UNKNOWN 0x2000 +#endif /* ! __KERNEL__ */ /* IP6 Hooks */ @@ -68,4 +71,7 @@ enum nf_ip6_hook_priorities { NF_IP6_PRI_LAST = INT_MAX, }; +extern int ipv6_netfilter_init(void); +extern void ipv6_netfilter_fini(void); + #endif /*__LINUX_IP6_NETFILTER_H*/ diff --git a/include/linux/netfilter_ipv6/ip6_logging.h b/include/linux/netfilter_ipv6/ip6_logging.h deleted file mode 100644 index a0b2ee3043aa..000000000000 --- a/include/linux/netfilter_ipv6/ip6_logging.h +++ /dev/null @@ -1,20 +0,0 @@ -/* IPv6 macros for the nternal logging interface. */ -#ifndef __IP6_LOGGING_H -#define __IP6_LOGGING_H - -#ifdef __KERNEL__ -#include <linux/socket.h> -#include <linux/netfilter_logging.h> - -#define nf_log_ip6_packet(pskb,hooknum,in,out,fmt,args...) \ - nf_log_packet(AF_INET6,pskb,hooknum,in,out,fmt,##args) - -#define nf_log_ip6(pfh,len,fmt,args...) \ - nf_log(AF_INET6,pfh,len,fmt,##args) - -#define nf_ip6_log_register(logging) nf_log_register(AF_INET6,logging) -#define nf_ip6_log_unregister(logging) nf_log_unregister(AF_INET6,logging) - -#endif /*__KERNEL__*/ - -#endif /*__IP6_LOGGING_H*/ diff --git a/include/linux/netfilter_ipv6/ip6_tables.h b/include/linux/netfilter_ipv6/ip6_tables.h index f1ce3b009853..58c72a52dc65 100644 --- a/include/linux/netfilter_ipv6/ip6_tables.h +++ b/include/linux/netfilter_ipv6/ip6_tables.h @@ -111,7 +111,8 @@ struct ip6t_counters #define IP6T_F_PROTO 0x01 /* Set if rule cares about upper protocols */ #define IP6T_F_TOS 0x02 /* Match the TOS. */ -#define IP6T_F_MASK 0x03 /* All possible flag bits mask. */ +#define IP6T_F_GOTO 0x04 /* Set if jump is a goto */ +#define IP6T_F_MASK 0x07 /* All possible flag bits mask. */ /* Values for "inv" field in struct ip6t_ip6. */ #define IP6T_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ diff --git a/include/linux/netfilter_ipv6/ip6t_HL.h b/include/linux/netfilter_ipv6/ip6t_HL.h new file mode 100644 index 000000000000..afb7813d45ab --- /dev/null +++ b/include/linux/netfilter_ipv6/ip6t_HL.h @@ -0,0 +1,22 @@ +/* Hop Limit modification module for ip6tables + * Maciej Soltysiak <solt@dns.toxicfilms.tv> + * Based on HW's TTL module */ + +#ifndef _IP6T_HL_H +#define _IP6T_HL_H + +enum { + IP6T_HL_SET = 0, + IP6T_HL_INC, + IP6T_HL_DEC +}; + +#define IP6T_HL_MAXMODE IP6T_HL_DEC + +struct ip6t_HL_info { + u_int8_t mode; + u_int8_t hop_limit; +}; + + +#endif diff --git a/include/linux/netfilter_ipv6/ip6t_LOG.h b/include/linux/netfilter_ipv6/ip6t_LOG.h index 42996a43bb39..9008ff5c40ae 100644 --- a/include/linux/netfilter_ipv6/ip6t_LOG.h +++ b/include/linux/netfilter_ipv6/ip6t_LOG.h @@ -1,6 +1,7 @@ #ifndef _IP6T_LOG_H #define _IP6T_LOG_H +/* make sure not to change this without changing netfilter.h:NF_LOG_* (!) */ #define IP6T_LOG_TCPSEQ 0x01 /* Log TCP sequence numbers */ #define IP6T_LOG_TCPOPT 0x02 /* Log TCP options */ #define IP6T_LOG_IPOPT 0x04 /* Log IP options */ diff --git a/include/linux/netfilter_ipv6/ip6t_REJECT.h b/include/linux/netfilter_ipv6/ip6t_REJECT.h new file mode 100644 index 000000000000..6be6504162bb --- /dev/null +++ b/include/linux/netfilter_ipv6/ip6t_REJECT.h @@ -0,0 +1,18 @@ +#ifndef _IP6T_REJECT_H +#define _IP6T_REJECT_H + +enum ip6t_reject_with { + IP6T_ICMP6_NO_ROUTE, + IP6T_ICMP6_ADM_PROHIBITED, + IP6T_ICMP6_NOT_NEIGHBOUR, + IP6T_ICMP6_ADDR_UNREACH, + IP6T_ICMP6_PORT_UNREACH, + IP6T_ICMP6_ECHOREPLY, + IP6T_TCP_RESET +}; + +struct ip6t_reject_info { + u_int32_t with; /* reject type */ +}; + +#endif /*_IP6T_REJECT_H*/ diff --git a/include/linux/netlink.h b/include/linux/netlink.h index 27e4d164a108..167518668936 100644 --- a/include/linux/netlink.h +++ b/include/linux/netlink.h @@ -5,21 +5,20 @@ #include <linux/types.h> #define NETLINK_ROUTE 0 /* Routing/device hook */ -#define NETLINK_SKIP 1 /* Reserved for ENskip */ +#define NETLINK_W1 1 /* 1-wire subsystem */ #define NETLINK_USERSOCK 2 /* Reserved for user mode socket protocols */ #define NETLINK_FIREWALL 3 /* Firewalling hook */ -#define NETLINK_TCPDIAG 4 /* TCP socket monitoring */ +#define NETLINK_INET_DIAG 4 /* INET socket monitoring */ #define NETLINK_NFLOG 5 /* netfilter/iptables ULOG */ #define NETLINK_XFRM 6 /* ipsec */ #define NETLINK_SELINUX 7 /* SELinux event notifications */ -#define NETLINK_ARPD 8 +#define NETLINK_ISCSI 8 /* Open-iSCSI */ #define NETLINK_AUDIT 9 /* auditing */ #define NETLINK_FIB_LOOKUP 10 -#define NETLINK_ROUTE6 11 /* af_inet6 route comm channel */ +#define NETLINK_NETFILTER 12 /* netfilter subsystem */ #define NETLINK_IP6_FW 13 #define NETLINK_DNRTMSG 14 /* DECnet routing messages */ #define NETLINK_KOBJECT_UEVENT 15 /* Kernel messages to userspace */ -#define NETLINK_TAPBASE 16 /* 16 to 31 are ethertap */ #define MAX_LINKS 32 @@ -91,6 +90,15 @@ struct nlmsgerr struct nlmsghdr msg; }; +#define NETLINK_ADD_MEMBERSHIP 1 +#define NETLINK_DROP_MEMBERSHIP 2 +#define NETLINK_PKTINFO 3 + +struct nl_pktinfo +{ + __u32 group; +}; + #define NET_MAJOR 36 /* Major 36 is reserved for networking */ enum { @@ -107,9 +115,8 @@ struct netlink_skb_parms { struct ucred creds; /* Skb credentials */ __u32 pid; - __u32 groups; __u32 dst_pid; - __u32 dst_groups; + __u32 dst_group; kernel_cap_t eff_cap; __u32 loginuid; /* Login (audit) uid */ }; @@ -118,11 +125,11 @@ struct netlink_skb_parms #define NETLINK_CREDS(skb) (&NETLINK_CB((skb)).creds) -extern struct sock *netlink_kernel_create(int unit, void (*input)(struct sock *sk, int len)); +extern struct sock *netlink_kernel_create(int unit, unsigned int groups, void (*input)(struct sock *sk, int len), struct module *module); extern void netlink_ack(struct sk_buff *in_skb, struct nlmsghdr *nlh, int err); extern int netlink_unicast(struct sock *ssk, struct sk_buff *skb, __u32 pid, int nonblock); extern int netlink_broadcast(struct sock *ssk, struct sk_buff *skb, __u32 pid, - __u32 group, int allocation); + __u32 group, unsigned int __nocast allocation); extern void netlink_set_err(struct sock *ssk, __u32 pid, __u32 group, int code); extern int netlink_register_notifier(struct notifier_block *nb); extern int netlink_unregister_notifier(struct notifier_block *nb); diff --git a/include/linux/netpoll.h b/include/linux/netpoll.h index bcd0ac33f592..5ade54a78dbb 100644 --- a/include/linux/netpoll.h +++ b/include/linux/netpoll.h @@ -9,6 +9,7 @@ #include <linux/netdevice.h> #include <linux/interrupt.h> +#include <linux/rcupdate.h> #include <linux/list.h> struct netpoll; @@ -26,6 +27,7 @@ struct netpoll { struct netpoll_info { spinlock_t poll_lock; int poll_owner; + int tries; int rx_flags; spinlock_t rx_lock; struct netpoll *rx_np; /* netpoll that registered an rx_hook */ @@ -60,25 +62,31 @@ static inline int netpoll_rx(struct sk_buff *skb) return ret; } -static inline void netpoll_poll_lock(struct net_device *dev) +static inline void *netpoll_poll_lock(struct net_device *dev) { + rcu_read_lock(); /* deal with race on ->npinfo */ if (dev->npinfo) { spin_lock(&dev->npinfo->poll_lock); dev->npinfo->poll_owner = smp_processor_id(); + return dev->npinfo; } + return NULL; } -static inline void netpoll_poll_unlock(struct net_device *dev) +static inline void netpoll_poll_unlock(void *have) { - if (dev->npinfo) { - dev->npinfo->poll_owner = -1; - spin_unlock(&dev->npinfo->poll_lock); + struct netpoll_info *npi = have; + + if (npi) { + npi->poll_owner = -1; + spin_unlock(&npi->poll_lock); } + rcu_read_unlock(); } #else #define netpoll_rx(a) 0 -#define netpoll_poll_lock(a) +#define netpoll_poll_lock(a) 0 #define netpoll_poll_unlock(a) #endif diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 8ea249110fb0..9a6047ff1b25 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -112,7 +112,8 @@ struct nfs_inode { /* * Various flags */ - unsigned int flags; + unsigned long flags; /* atomic bit ops */ + unsigned long cache_validity; /* bit mask */ /* * read_cache_jiffies is when we started read-caching this inode, @@ -174,8 +175,6 @@ struct nfs_inode { /* Open contexts for shared mmap writes */ struct list_head open_files; - wait_queue_head_t nfs_i_wait; - #ifdef CONFIG_NFS_V4 struct nfs4_cached_acl *nfs4_acl; /* NFSv4 state */ @@ -188,17 +187,21 @@ struct nfs_inode { }; /* - * Legal inode flag values + * Cache validity bit flags */ -#define NFS_INO_STALE 0x0001 /* possible stale inode */ -#define NFS_INO_ADVISE_RDPLUS 0x0002 /* advise readdirplus */ -#define NFS_INO_REVALIDATING 0x0004 /* revalidating attrs */ -#define NFS_INO_INVALID_ATTR 0x0008 /* cached attrs are invalid */ -#define NFS_INO_INVALID_DATA 0x0010 /* cached data is invalid */ -#define NFS_INO_INVALID_ATIME 0x0020 /* cached atime is invalid */ -#define NFS_INO_INVALID_ACCESS 0x0040 /* cached access cred invalid */ -#define NFS_INO_INVALID_ACL 0x0080 /* cached acls are invalid */ -#define NFS_INO_REVAL_PAGECACHE 0x1000 /* must revalidate pagecache */ +#define NFS_INO_INVALID_ATTR 0x0001 /* cached attrs are invalid */ +#define NFS_INO_INVALID_DATA 0x0002 /* cached data is invalid */ +#define NFS_INO_INVALID_ATIME 0x0004 /* cached atime is invalid */ +#define NFS_INO_INVALID_ACCESS 0x0008 /* cached access cred invalid */ +#define NFS_INO_INVALID_ACL 0x0010 /* cached acls are invalid */ +#define NFS_INO_REVAL_PAGECACHE 0x0020 /* must revalidate pagecache */ + +/* + * Bit offsets in flags field + */ +#define NFS_INO_REVALIDATING (0) /* revalidating attrs */ +#define NFS_INO_ADVISE_RDPLUS (1) /* advise readdirplus */ +#define NFS_INO_STALE (2) /* possible stale inode */ static inline struct nfs_inode *NFS_I(struct inode *inode) { @@ -224,8 +227,7 @@ static inline struct nfs_inode *NFS_I(struct inode *inode) #define NFS_ATTRTIMEO_UPDATE(inode) (NFS_I(inode)->attrtimeo_timestamp) #define NFS_FLAGS(inode) (NFS_I(inode)->flags) -#define NFS_REVALIDATING(inode) (NFS_FLAGS(inode) & NFS_INO_REVALIDATING) -#define NFS_STALE(inode) (NFS_FLAGS(inode) & NFS_INO_STALE) +#define NFS_STALE(inode) (test_bit(NFS_INO_STALE, &NFS_FLAGS(inode))) #define NFS_FILEID(inode) (NFS_I(inode)->fileid) @@ -236,8 +238,11 @@ static inline int nfs_caches_unstable(struct inode *inode) static inline void NFS_CACHEINV(struct inode *inode) { - if (!nfs_caches_unstable(inode)) - NFS_FLAGS(inode) |= NFS_INO_INVALID_ATTR | NFS_INO_INVALID_ACCESS; + if (!nfs_caches_unstable(inode)) { + spin_lock(&inode->i_lock); + NFS_I(inode)->cache_validity |= NFS_INO_INVALID_ATTR | NFS_INO_INVALID_ACCESS; + spin_unlock(&inode->i_lock); + } } static inline int nfs_server_capable(struct inode *inode, int cap) @@ -247,7 +252,7 @@ static inline int nfs_server_capable(struct inode *inode, int cap) static inline int NFS_USE_READDIRPLUS(struct inode *inode) { - return NFS_FLAGS(inode) & NFS_INO_ADVISE_RDPLUS; + return test_bit(NFS_INO_ADVISE_RDPLUS, &NFS_FLAGS(inode)); } /** @@ -292,6 +297,7 @@ extern int nfs_revalidate_inode(struct nfs_server *server, struct inode *inode); extern int __nfs_revalidate_inode(struct nfs_server *, struct inode *); extern void nfs_revalidate_mapping(struct inode *inode, struct address_space *mapping); extern int nfs_setattr(struct dentry *, struct iattr *); +extern void nfs_setattr_update_inode(struct inode *inode, struct iattr *attr); extern void nfs_begin_attr_update(struct inode *); extern void nfs_end_attr_update(struct inode *); extern void nfs_begin_data_update(struct inode *); diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h index f5a6695d4d21..f34767c5fc79 100644 --- a/include/linux/page-flags.h +++ b/include/linux/page-flags.h @@ -134,6 +134,7 @@ struct page_state { }; extern void get_page_state(struct page_state *ret); +extern void get_page_state_node(struct page_state *ret, int node); extern void get_full_page_state(struct page_state *ret); extern unsigned long __read_page_state(unsigned long offset); extern void __mod_page_state(unsigned long offset, unsigned long delta); @@ -194,6 +195,7 @@ extern void __mod_page_state(unsigned long offset, unsigned long delta); #define SetPageDirty(page) set_bit(PG_dirty, &(page)->flags) #define TestSetPageDirty(page) test_and_set_bit(PG_dirty, &(page)->flags) #define ClearPageDirty(page) clear_bit(PG_dirty, &(page)->flags) +#define __ClearPageDirty(page) __clear_bit(PG_dirty, &(page)->flags) #define TestClearPageDirty(page) test_and_clear_bit(PG_dirty, &(page)->flags) #define SetPageLRU(page) set_bit(PG_lru, &(page)->flags) diff --git a/include/linux/pci.h b/include/linux/pci.h index 7ac14961ba22..bc4c40000c0d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -556,7 +556,8 @@ struct pci_dev { /* keep track of device state */ unsigned int is_enabled:1; /* pci_enable_device has been called */ unsigned int is_busmaster:1; /* device is busmaster */ - + unsigned int no_msi:1; /* device may not use msi */ + u32 saved_config_space[16]; /* config space saved at suspend time */ struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ int rom_attr_enabled; /* has display of the rom attribute been enabled? */ @@ -971,6 +972,8 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en #define isa_bridge ((struct pci_dev *)NULL) +#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) + #else /* @@ -985,9 +988,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return 0; } #endif - -#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) - #endif /* !CONFIG_PCI */ /* these helpers provide future and backwards compatibility diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 27348c22dacb..95c941f8c747 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -881,7 +881,7 @@ #define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e #define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032 -#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA 0x0033 +#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034 #define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b #define PCI_DEVICE_ID_APPLE_KEYLARGO_I 0x003e @@ -911,6 +911,15 @@ #define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 #define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 #define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 +#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300 +#define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312 +#define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322 +#define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312 +#define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322 +#define PCI_DEVICE_ID_QLOGIC_ISP2422 0x2422 +#define PCI_DEVICE_ID_QLOGIC_ISP2432 0x2432 +#define PCI_DEVICE_ID_QLOGIC_ISP2512 0x2512 +#define PCI_DEVICE_ID_QLOGIC_ISP2522 0x2522 #define PCI_VENDOR_ID_CYRIX 0x1078 #define PCI_DEVICE_ID_CYRIX_5510 0x0000 @@ -1011,6 +1020,7 @@ #define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 #define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 #define PCI_DEVICE_ID_PLX_R753 0x1152 +#define PCI_DEVICE_ID_PLX_OLITEC 0x1187 #define PCI_DEVICE_ID_PLX_9030 0x9030 #define PCI_DEVICE_ID_PLX_9050 0x9050 #define PCI_DEVICE_ID_PLX_9060 0x9060 @@ -1239,6 +1249,7 @@ #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267 #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE 0x036E +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA 0x036F #define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268 #define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269 #define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO 0x026B @@ -1570,6 +1581,7 @@ #define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 #define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 #define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 #define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB @@ -1872,6 +1884,7 @@ #define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 #define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_SUBVENDOR_ID_SIIG 0x131f #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 #define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 #define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 @@ -1909,6 +1922,7 @@ #define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 #define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 #define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 +#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL 0x2050 #define PCI_VENDOR_ID_RADISYS 0x1331 #define PCI_DEVICE_ID_RADISYS_ENP2611 0x0030 @@ -2096,6 +2110,8 @@ #define PCI_DEVICE_ID_TIGON3_5721 0x1659 #define PCI_DEVICE_ID_TIGON3_5705M 0x165d #define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_TIGON3_5780 0x166a +#define PCI_DEVICE_ID_TIGON3_5780S 0x166b #define PCI_DEVICE_ID_TIGON3_5705F 0x166e #define PCI_DEVICE_ID_TIGON3_5750 0x1676 #define PCI_DEVICE_ID_TIGON3_5751 0x1677 @@ -2129,6 +2145,10 @@ #define PCI_DEVICE_ID_ENE_1225 0x1225 #define PCI_DEVICE_ID_ENE_1410 0x1410 #define PCI_DEVICE_ID_ENE_1420 0x1420 +#define PCI_VENDOR_ID_CHELSIO 0x1425 + +#define PCI_VENDOR_ID_MIPS 0x153f +#define PCI_DEVICE_ID_SOC_IT 0x0001 #define PCI_VENDOR_ID_SYBA 0x1592 #define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 @@ -2170,6 +2190,9 @@ #define PCI_VENDOR_ID_SIBYTE 0x166d #define PCI_DEVICE_ID_BCM1250_HT 0x0002 +#define PCI_VENDOR_ID_NETCELL 0x169c +#define PCI_DEVICE_ID_REVOLUTION 0x0044 + #define PCI_VENDOR_ID_LINKSYS 0x1737 #define PCI_DEVICE_ID_LINKSYS_EG1032 0x1032 #define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064 @@ -2267,6 +2290,11 @@ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 #define PCI_DEVICE_ID_INTEL_21145 0x0039 +#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 +#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321 +#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329 +#define PCI_DEVICE_ID_INTEL_PXH_1 0x032A +#define PCI_DEVICE_ID_INTEL_PXHV 0x032C #define PCI_DEVICE_ID_INTEL_82375 0x0482 #define PCI_DEVICE_ID_INTEL_82424 0x0483 #define PCI_DEVICE_ID_INTEL_82378 0x0484 diff --git a/include/linux/phy.h b/include/linux/phy.h new file mode 100644 index 000000000000..72cb67b66e0c --- /dev/null +++ b/include/linux/phy.h @@ -0,0 +1,377 @@ +/* + * include/linux/phy.h + * + * Framework and drivers for configuring and reading different PHYs + * Based on code in sungem_phy.c and gianfar_phy.c + * + * Author: Andy Fleming + * + * Copyright (c) 2004 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __PHY_H +#define __PHY_H + +#include <linux/spinlock.h> +#include <linux/device.h> + +#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ + SUPPORTED_10baseT_Full | \ + SUPPORTED_100baseT_Half | \ + SUPPORTED_100baseT_Full | \ + SUPPORTED_Autoneg | \ + SUPPORTED_TP | \ + SUPPORTED_MII) + +#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ + SUPPORTED_1000baseT_Half | \ + SUPPORTED_1000baseT_Full) + +/* Set phydev->irq to PHY_POLL if interrupts are not supported, + * or not desired for this PHY. Set to PHY_IGNORE_INTERRUPT if + * the attached driver handles the interrupt + */ +#define PHY_POLL -1 +#define PHY_IGNORE_INTERRUPT -2 + +#define PHY_HAS_INTERRUPT 0x00000001 +#define PHY_HAS_MAGICANEG 0x00000002 + +#define MII_BUS_MAX 4 + + +#define PHY_INIT_TIMEOUT 100000 +#define PHY_STATE_TIME 1 +#define PHY_FORCE_TIMEOUT 10 +#define PHY_AN_TIMEOUT 10 + +#define PHY_MAX_ADDR 32 + +/* The Bus class for PHYs. Devices which provide access to + * PHYs should register using this structure */ +struct mii_bus { + const char *name; + int id; + void *priv; + int (*read)(struct mii_bus *bus, int phy_id, int regnum); + int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val); + int (*reset)(struct mii_bus *bus); + + /* A lock to ensure that only one thing can read/write + * the MDIO bus at a time */ + spinlock_t mdio_lock; + + struct device *dev; + + /* list of all PHYs on bus */ + struct phy_device *phy_map[PHY_MAX_ADDR]; + + /* Pointer to an array of interrupts, each PHY's + * interrupt at the index matching its address */ + int *irq; +}; + +#define PHY_INTERRUPT_DISABLED 0x0 +#define PHY_INTERRUPT_ENABLED 0x80000000 + +/* PHY state machine states: + * + * DOWN: PHY device and driver are not ready for anything. probe + * should be called if and only if the PHY is in this state, + * given that the PHY device exists. + * - PHY driver probe function will, depending on the PHY, set + * the state to STARTING or READY + * + * STARTING: PHY device is coming up, and the ethernet driver is + * not ready. PHY drivers may set this in the probe function. + * If they do, they are responsible for making sure the state is + * eventually set to indicate whether the PHY is UP or READY, + * depending on the state when the PHY is done starting up. + * - PHY driver will set the state to READY + * - start will set the state to PENDING + * + * READY: PHY is ready to send and receive packets, but the + * controller is not. By default, PHYs which do not implement + * probe will be set to this state by phy_probe(). If the PHY + * driver knows the PHY is ready, and the PHY state is STARTING, + * then it sets this STATE. + * - start will set the state to UP + * + * PENDING: PHY device is coming up, but the ethernet driver is + * ready. phy_start will set this state if the PHY state is + * STARTING. + * - PHY driver will set the state to UP when the PHY is ready + * + * UP: The PHY and attached device are ready to do work. + * Interrupts should be started here. + * - timer moves to AN + * + * AN: The PHY is currently negotiating the link state. Link is + * therefore down for now. phy_timer will set this state when it + * detects the state is UP. config_aneg will set this state + * whenever called with phydev->autoneg set to AUTONEG_ENABLE. + * - If autonegotiation finishes, but there's no link, it sets + * the state to NOLINK. + * - If aneg finishes with link, it sets the state to RUNNING, + * and calls adjust_link + * - If autonegotiation did not finish after an arbitrary amount + * of time, autonegotiation should be tried again if the PHY + * supports "magic" autonegotiation (back to AN) + * - If it didn't finish, and no magic_aneg, move to FORCING. + * + * NOLINK: PHY is up, but not currently plugged in. + * - If the timer notes that the link comes back, we move to RUNNING + * - config_aneg moves to AN + * - phy_stop moves to HALTED + * + * FORCING: PHY is being configured with forced settings + * - if link is up, move to RUNNING + * - If link is down, we drop to the next highest setting, and + * retry (FORCING) after a timeout + * - phy_stop moves to HALTED + * + * RUNNING: PHY is currently up, running, and possibly sending + * and/or receiving packets + * - timer will set CHANGELINK if we're polling (this ensures the + * link state is polled every other cycle of this state machine, + * which makes it every other second) + * - irq will set CHANGELINK + * - config_aneg will set AN + * - phy_stop moves to HALTED + * + * CHANGELINK: PHY experienced a change in link state + * - timer moves to RUNNING if link + * - timer moves to NOLINK if the link is down + * - phy_stop moves to HALTED + * + * HALTED: PHY is up, but no polling or interrupts are done. Or + * PHY is in an error state. + * + * - phy_start moves to RESUMING + * + * RESUMING: PHY was halted, but now wants to run again. + * - If we are forcing, or aneg is done, timer moves to RUNNING + * - If aneg is not done, timer moves to AN + * - phy_stop moves to HALTED + */ +enum phy_state { + PHY_DOWN=0, + PHY_STARTING, + PHY_READY, + PHY_PENDING, + PHY_UP, + PHY_AN, + PHY_RUNNING, + PHY_NOLINK, + PHY_FORCING, + PHY_CHANGELINK, + PHY_HALTED, + PHY_RESUMING +}; + +/* phy_device: An instance of a PHY + * + * drv: Pointer to the driver for this PHY instance + * bus: Pointer to the bus this PHY is on + * dev: driver model device structure for this PHY + * phy_id: UID for this device found during discovery + * state: state of the PHY for management purposes + * dev_flags: Device-specific flags used by the PHY driver. + * addr: Bus address of PHY + * link_timeout: The number of timer firings to wait before the + * giving up on the current attempt at acquiring a link + * irq: IRQ number of the PHY's interrupt (-1 if none) + * phy_timer: The timer for handling the state machine + * phy_queue: A work_queue for the interrupt + * attached_dev: The attached enet driver's device instance ptr + * adjust_link: Callback for the enet controller to respond to + * changes in the link state. + * adjust_state: Callback for the enet driver to respond to + * changes in the state machine. + * + * speed, duplex, pause, supported, advertising, and + * autoneg are used like in mii_if_info + * + * interrupts currently only supports enabled or disabled, + * but could be changed in the future to support enabling + * and disabling specific interrupts + * + * Contains some infrastructure for polling and interrupt + * handling, as well as handling shifts in PHY hardware state + */ +struct phy_device { + /* Information about the PHY type */ + /* And management functions */ + struct phy_driver *drv; + + struct mii_bus *bus; + + struct device dev; + + u32 phy_id; + + enum phy_state state; + + u32 dev_flags; + + /* Bus address of the PHY (0-32) */ + int addr; + + /* forced speed & duplex (no autoneg) + * partner speed & duplex & pause (autoneg) + */ + int speed; + int duplex; + int pause; + int asym_pause; + + /* The most recently read link state */ + int link; + + /* Enabled Interrupts */ + u32 interrupts; + + /* Union of PHY and Attached devices' supported modes */ + /* See mii.h for more info */ + u32 supported; + u32 advertising; + + int autoneg; + + int link_timeout; + + /* Interrupt number for this PHY + * -1 means no interrupt */ + int irq; + + /* private data pointer */ + /* For use by PHYs to maintain extra state */ + void *priv; + + /* Interrupt and Polling infrastructure */ + struct work_struct phy_queue; + struct timer_list phy_timer; + + spinlock_t lock; + + struct net_device *attached_dev; + + void (*adjust_link)(struct net_device *dev); + + void (*adjust_state)(struct net_device *dev); +}; +#define to_phy_device(d) container_of(d, struct phy_device, dev) + +/* struct phy_driver: Driver structure for a particular PHY type + * + * phy_id: The result of reading the UID registers of this PHY + * type, and ANDing them with the phy_id_mask. This driver + * only works for PHYs with IDs which match this field + * name: The friendly name of this PHY type + * phy_id_mask: Defines the important bits of the phy_id + * features: A list of features (speed, duplex, etc) supported + * by this PHY + * flags: A bitfield defining certain other features this PHY + * supports (like interrupts) + * + * The drivers must implement config_aneg and read_status. All + * other functions are optional. Note that none of these + * functions should be called from interrupt time. The goal is + * for the bus read/write functions to be able to block when the + * bus transaction is happening, and be freed up by an interrupt + * (The MPC85xx has this ability, though it is not currently + * supported in the driver). + */ +struct phy_driver { + u32 phy_id; + char *name; + unsigned int phy_id_mask; + u32 features; + u32 flags; + + /* Called to initialize the PHY, + * including after a reset */ + int (*config_init)(struct phy_device *phydev); + + /* Called during discovery. Used to set + * up device-specific structures, if any */ + int (*probe)(struct phy_device *phydev); + + /* PHY Power Management */ + int (*suspend)(struct phy_device *phydev); + int (*resume)(struct phy_device *phydev); + + /* Configures the advertisement and resets + * autonegotiation if phydev->autoneg is on, + * forces the speed to the current settings in phydev + * if phydev->autoneg is off */ + int (*config_aneg)(struct phy_device *phydev); + + /* Determines the negotiated speed and duplex */ + int (*read_status)(struct phy_device *phydev); + + /* Clears any pending interrupts */ + int (*ack_interrupt)(struct phy_device *phydev); + + /* Enables or disables interrupts */ + int (*config_intr)(struct phy_device *phydev); + + /* Clears up any memory if needed */ + void (*remove)(struct phy_device *phydev); + + struct device_driver driver; +}; +#define to_phy_driver(d) container_of(d, struct phy_driver, driver) + +int phy_read(struct phy_device *phydev, u16 regnum); +int phy_write(struct phy_device *phydev, u16 regnum, u16 val); +struct phy_device* get_phy_device(struct mii_bus *bus, int addr); +int phy_clear_interrupt(struct phy_device *phydev); +int phy_config_interrupt(struct phy_device *phydev, u32 interrupts); +struct phy_device * phy_attach(struct net_device *dev, + const char *phy_id, u32 flags); +struct phy_device * phy_connect(struct net_device *dev, const char *phy_id, + void (*handler)(struct net_device *), u32 flags); +void phy_disconnect(struct phy_device *phydev); +void phy_detach(struct phy_device *phydev); +void phy_start(struct phy_device *phydev); +void phy_stop(struct phy_device *phydev); +int phy_start_aneg(struct phy_device *phydev); + +int mdiobus_register(struct mii_bus *bus); +void mdiobus_unregister(struct mii_bus *bus); +void phy_sanitize_settings(struct phy_device *phydev); +int phy_stop_interrupts(struct phy_device *phydev); + +static inline int phy_read_status(struct phy_device *phydev) { + return phydev->drv->read_status(phydev); +} + +int genphy_config_advert(struct phy_device *phydev); +int genphy_setup_forced(struct phy_device *phydev); +int genphy_restart_aneg(struct phy_device *phydev); +int genphy_config_aneg(struct phy_device *phydev); +int genphy_update_link(struct phy_device *phydev); +int genphy_read_status(struct phy_device *phydev); +void phy_driver_unregister(struct phy_driver *drv); +int phy_driver_register(struct phy_driver *new_driver); +void phy_prepare_link(struct phy_device *phydev, + void (*adjust_link)(struct net_device *)); +void phy_start_machine(struct phy_device *phydev, + void (*handler)(struct net_device *)); +void phy_stop_machine(struct phy_device *phydev); +int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); +int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); +int phy_mii_ioctl(struct phy_device *phydev, + struct mii_ioctl_data *mii_data, int cmd); +int phy_start_interrupts(struct phy_device *phydev); +void phy_print_status(struct phy_device *phydev); + +extern struct bus_type mdio_bus_type; +#endif /* __PHY_H */ diff --git a/include/linux/pm.h b/include/linux/pm.h index 14479325e3f3..5cfb07648eca 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -176,7 +176,7 @@ struct pm_ops { }; extern void pm_set_ops(struct pm_ops *); - +extern struct pm_ops *pm_ops; extern int pm_suspend(suspend_state_t state); @@ -186,7 +186,9 @@ extern int pm_suspend(suspend_state_t state); struct device; -typedef u32 __bitwise pm_message_t; +typedef struct pm_message { + int event; +} pm_message_t; /* * There are 4 important states driver can be in: @@ -207,9 +209,13 @@ typedef u32 __bitwise pm_message_t; * or something similar soon. */ -#define PMSG_FREEZE ((__force pm_message_t) 3) -#define PMSG_SUSPEND ((__force pm_message_t) 3) -#define PMSG_ON ((__force pm_message_t) 0) +#define PM_EVENT_ON 0 +#define PM_EVENT_FREEZE 1 +#define PM_EVENT_SUSPEND 2 + +#define PMSG_FREEZE ((struct pm_message){ .event = PM_EVENT_FREEZE, }) +#define PMSG_SUSPEND ((struct pm_message){ .event = PM_EVENT_SUSPEND, }) +#define PMSG_ON ((struct pm_message){ .event = PM_EVENT_ON, }) struct dev_pm_info { pm_message_t power_state; diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index a373fc254df2..2afdafb62123 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h @@ -20,6 +20,8 @@ #define PTRACE_DETACH 0x11 #define PTRACE_SYSCALL 24 +#define PTRACE_SYSEMU 31 +#define PTRACE_SYSEMU_SINGLESTEP 32 /* 0x4200-0x4300 are reserved for architecture-independent additions. */ #define PTRACE_SETOPTIONS 0x4200 diff --git a/include/linux/raid/bitmap.h b/include/linux/raid/bitmap.h index e24b74b11150..4bf1659f8aa8 100644 --- a/include/linux/raid/bitmap.h +++ b/include/linux/raid/bitmap.h @@ -248,6 +248,7 @@ struct bitmap { /* these are used only by md/bitmap */ int bitmap_create(mddev_t *mddev); +void bitmap_flush(mddev_t *mddev); void bitmap_destroy(mddev_t *mddev); int bitmap_active(struct bitmap *bitmap); @@ -262,7 +263,7 @@ void bitmap_write_all(struct bitmap *bitmap); int bitmap_startwrite(struct bitmap *bitmap, sector_t offset, unsigned long sectors); void bitmap_endwrite(struct bitmap *bitmap, sector_t offset, unsigned long sectors, int success); -int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks); +int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int degraded); void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int aborted); void bitmap_close_sync(struct bitmap *bitmap); diff --git a/include/linux/random.h b/include/linux/random.h index cc6703449916..7b2adb3322d5 100644 --- a/include/linux/random.h +++ b/include/linux/random.h @@ -59,6 +59,8 @@ extern __u32 secure_tcp_sequence_number(__u32 saddr, __u32 daddr, __u16 sport, __u16 dport); extern __u32 secure_tcpv6_sequence_number(__u32 *saddr, __u32 *daddr, __u16 sport, __u16 dport); +extern u64 secure_dccp_sequence_number(__u32 saddr, __u32 daddr, + __u16 sport, __u16 dport); #ifndef MODULE extern struct file_operations random_fops, urandom_fops; diff --git a/include/linux/reboot.h b/include/linux/reboot.h index 2d4dd23168dd..3b3266ff1a95 100644 --- a/include/linux/reboot.h +++ b/include/linux/reboot.h @@ -55,6 +55,22 @@ extern void machine_shutdown(void); struct pt_regs; extern void machine_crash_shutdown(struct pt_regs *); +/* + * Architecture independent implemenations of sys_reboot commands. + */ + +extern void kernel_restart(char *cmd); +extern void kernel_halt(void); +extern void kernel_power_off(void); +extern void kernel_kexec(void); + +/* + * Emergency restart, callable from an interrupt handler. + */ + +extern void emergency_restart(void); +#include <asm/emergency-restart.h> + #endif #endif /* _LINUX_REBOOT_H */ diff --git a/include/linux/reiserfs_acl.h b/include/linux/reiserfs_acl.h index 0760507a545b..0a3605099c44 100644 --- a/include/linux/reiserfs_acl.h +++ b/include/linux/reiserfs_acl.h @@ -4,29 +4,29 @@ #define REISERFS_ACL_VERSION 0x0001 typedef struct { - __le16 e_tag; - __le16 e_perm; - __le32 e_id; + __le16 e_tag; + __le16 e_perm; + __le32 e_id; } reiserfs_acl_entry; typedef struct { - __le16 e_tag; - __le16 e_perm; + __le16 e_tag; + __le16 e_perm; } reiserfs_acl_entry_short; typedef struct { - __le32 a_version; + __le32 a_version; } reiserfs_acl_header; static inline size_t reiserfs_acl_size(int count) { if (count <= 4) { return sizeof(reiserfs_acl_header) + - count * sizeof(reiserfs_acl_entry_short); + count * sizeof(reiserfs_acl_entry_short); } else { return sizeof(reiserfs_acl_header) + - 4 * sizeof(reiserfs_acl_entry_short) + - (count - 4) * sizeof(reiserfs_acl_entry); + 4 * sizeof(reiserfs_acl_entry_short) + + (count - 4) * sizeof(reiserfs_acl_entry); } } @@ -46,14 +46,14 @@ static inline int reiserfs_acl_count(size_t size) } } - #ifdef CONFIG_REISERFS_FS_POSIX_ACL -struct posix_acl * reiserfs_get_acl(struct inode *inode, int type); -int reiserfs_acl_chmod (struct inode *inode); -int reiserfs_inherit_default_acl (struct inode *dir, struct dentry *dentry, struct inode *inode); -int reiserfs_cache_default_acl (struct inode *dir); -extern int reiserfs_xattr_posix_acl_init (void) __init; -extern int reiserfs_xattr_posix_acl_exit (void); +struct posix_acl *reiserfs_get_acl(struct inode *inode, int type); +int reiserfs_acl_chmod(struct inode *inode); +int reiserfs_inherit_default_acl(struct inode *dir, struct dentry *dentry, + struct inode *inode); +int reiserfs_cache_default_acl(struct inode *dir); +extern int reiserfs_xattr_posix_acl_init(void) __init; +extern int reiserfs_xattr_posix_acl_exit(void); extern struct reiserfs_xattr_handler posix_acl_default_handler; extern struct reiserfs_xattr_handler posix_acl_access_handler; #else @@ -61,28 +61,26 @@ extern struct reiserfs_xattr_handler posix_acl_access_handler; #define reiserfs_get_acl NULL #define reiserfs_cache_default_acl(inode) 0 -static inline int -reiserfs_xattr_posix_acl_init (void) +static inline int reiserfs_xattr_posix_acl_init(void) { - return 0; + return 0; } -static inline int -reiserfs_xattr_posix_acl_exit (void) +static inline int reiserfs_xattr_posix_acl_exit(void) { - return 0; + return 0; } -static inline int -reiserfs_acl_chmod (struct inode *inode) +static inline int reiserfs_acl_chmod(struct inode *inode) { - return 0; + return 0; } static inline int -reiserfs_inherit_default_acl (const struct inode *dir, struct dentry *dentry, struct inode *inode) +reiserfs_inherit_default_acl(const struct inode *dir, struct dentry *dentry, + struct inode *inode) { - return 0; + return 0; } #endif diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h index 4c7c5689ad93..17e458e17e2b 100644 --- a/include/linux/reiserfs_fs.h +++ b/include/linux/reiserfs_fs.h @@ -3,11 +3,10 @@ */ /* this file has an amazingly stupid - name, yura please fix it to be - reiserfs.h, and merge all the rest - of our .h files that are in this - directory into it. */ - + name, yura please fix it to be + reiserfs.h, and merge all the rest + of our .h files that are in this + directory into it. */ #ifndef _LINUX_REISER_FS_H #define _LINUX_REISER_FS_H @@ -74,9 +73,9 @@ /* debug levels. Right now, CONFIG_REISERFS_CHECK means print all debug ** messages. */ -#define REISERFS_DEBUG_CODE 5 /* extra messages to help find/debug errors */ +#define REISERFS_DEBUG_CODE 5 /* extra messages to help find/debug errors */ -void reiserfs_warning (struct super_block *s, const char * fmt, ...); +void reiserfs_warning(struct super_block *s, const char *fmt, ...); /* assertions handling */ /** always check a condition and panic if it's false. */ @@ -105,82 +104,78 @@ if( !( cond ) ) \ * Structure of super block on disk, a version of which in RAM is often accessed as REISERFS_SB(s)->s_rs * the version in RAM is part of a larger structure containing fields never written to disk. */ -#define UNSET_HASH 0 // read_super will guess about, what hash names - // in directories were sorted with +#define UNSET_HASH 0 // read_super will guess about, what hash names + // in directories were sorted with #define TEA_HASH 1 #define YURA_HASH 2 #define R5_HASH 3 #define DEFAULT_HASH R5_HASH - struct journal_params { - __le32 jp_journal_1st_block; /* where does journal start from on its - * device */ - __le32 jp_journal_dev; /* journal device st_rdev */ - __le32 jp_journal_size; /* size of the journal */ - __le32 jp_journal_trans_max; /* max number of blocks in a transaction. */ - __le32 jp_journal_magic; /* random value made on fs creation (this - * was sb_journal_block_count) */ - __le32 jp_journal_max_batch; /* max number of blocks to batch into a - * trans */ - __le32 jp_journal_max_commit_age; /* in seconds, how old can an async - * commit be */ - __le32 jp_journal_max_trans_age; /* in seconds, how old can a transaction - * be */ + __le32 jp_journal_1st_block; /* where does journal start from on its + * device */ + __le32 jp_journal_dev; /* journal device st_rdev */ + __le32 jp_journal_size; /* size of the journal */ + __le32 jp_journal_trans_max; /* max number of blocks in a transaction. */ + __le32 jp_journal_magic; /* random value made on fs creation (this + * was sb_journal_block_count) */ + __le32 jp_journal_max_batch; /* max number of blocks to batch into a + * trans */ + __le32 jp_journal_max_commit_age; /* in seconds, how old can an async + * commit be */ + __le32 jp_journal_max_trans_age; /* in seconds, how old can a transaction + * be */ }; /* this is the super from 3.5.X, where X >= 10 */ -struct reiserfs_super_block_v1 -{ - __le32 s_block_count; /* blocks count */ - __le32 s_free_blocks; /* free blocks count */ - __le32 s_root_block; /* root block number */ - struct journal_params s_journal; - __le16 s_blocksize; /* block size */ - __le16 s_oid_maxsize; /* max size of object id array, see - * get_objectid() commentary */ - __le16 s_oid_cursize; /* current size of object id array */ - __le16 s_umount_state; /* this is set to 1 when filesystem was - * umounted, to 2 - when not */ - char s_magic[10]; /* reiserfs magic string indicates that - * file system is reiserfs: - * "ReIsErFs" or "ReIsEr2Fs" or "ReIsEr3Fs" */ - __le16 s_fs_state; /* it is set to used by fsck to mark which - * phase of rebuilding is done */ - __le32 s_hash_function_code; /* indicate, what hash function is being use - * to sort names in a directory*/ - __le16 s_tree_height; /* height of disk tree */ - __le16 s_bmap_nr; /* amount of bitmap blocks needed to address - * each block of file system */ - __le16 s_version; /* this field is only reliable on filesystem - * with non-standard journal */ - __le16 s_reserved_for_journal; /* size in blocks of journal area on main - * device, we need to keep after - * making fs with non-standard journal */ +struct reiserfs_super_block_v1 { + __le32 s_block_count; /* blocks count */ + __le32 s_free_blocks; /* free blocks count */ + __le32 s_root_block; /* root block number */ + struct journal_params s_journal; + __le16 s_blocksize; /* block size */ + __le16 s_oid_maxsize; /* max size of object id array, see + * get_objectid() commentary */ + __le16 s_oid_cursize; /* current size of object id array */ + __le16 s_umount_state; /* this is set to 1 when filesystem was + * umounted, to 2 - when not */ + char s_magic[10]; /* reiserfs magic string indicates that + * file system is reiserfs: + * "ReIsErFs" or "ReIsEr2Fs" or "ReIsEr3Fs" */ + __le16 s_fs_state; /* it is set to used by fsck to mark which + * phase of rebuilding is done */ + __le32 s_hash_function_code; /* indicate, what hash function is being use + * to sort names in a directory*/ + __le16 s_tree_height; /* height of disk tree */ + __le16 s_bmap_nr; /* amount of bitmap blocks needed to address + * each block of file system */ + __le16 s_version; /* this field is only reliable on filesystem + * with non-standard journal */ + __le16 s_reserved_for_journal; /* size in blocks of journal area on main + * device, we need to keep after + * making fs with non-standard journal */ } __attribute__ ((__packed__)); #define SB_SIZE_V1 (sizeof(struct reiserfs_super_block_v1)) /* this is the on disk super block */ -struct reiserfs_super_block -{ - struct reiserfs_super_block_v1 s_v1; - __le32 s_inode_generation; - __le32 s_flags; /* Right now used only by inode-attributes, if enabled */ - unsigned char s_uuid[16]; /* filesystem unique identifier */ - unsigned char s_label[16]; /* filesystem volume label */ - char s_unused[88] ; /* zero filled by mkreiserfs and - * reiserfs_convert_objectid_map_v1() - * so any additions must be updated - * there as well. */ -} __attribute__ ((__packed__)); +struct reiserfs_super_block { + struct reiserfs_super_block_v1 s_v1; + __le32 s_inode_generation; + __le32 s_flags; /* Right now used only by inode-attributes, if enabled */ + unsigned char s_uuid[16]; /* filesystem unique identifier */ + unsigned char s_label[16]; /* filesystem volume label */ + char s_unused[88]; /* zero filled by mkreiserfs and + * reiserfs_convert_objectid_map_v1() + * so any additions must be updated + * there as well. */ +} __attribute__ ((__packed__)); #define SB_SIZE (sizeof(struct reiserfs_super_block)) #define REISERFS_VERSION_1 0 #define REISERFS_VERSION_2 2 - // on-disk super block fields converted to cpu form #define SB_DISK_SUPER_BLOCK(s) (REISERFS_SB(s)->s_rs) #define SB_V1_DISK_SUPER_BLOCK(s) (&(SB_DISK_SUPER_BLOCK(s)->s_v1)) @@ -210,13 +205,12 @@ struct reiserfs_super_block #define PUT_SB_TREE_HEIGHT(s, val) \ do { SB_V1_DISK_SUPER_BLOCK(s)->s_tree_height = cpu_to_le16(val); } while (0) #define PUT_SB_REISERFS_STATE(s, val) \ - do { SB_V1_DISK_SUPER_BLOCK(s)->s_umount_state = cpu_to_le16(val); } while (0) + do { SB_V1_DISK_SUPER_BLOCK(s)->s_umount_state = cpu_to_le16(val); } while (0) #define PUT_SB_VERSION(s, val) \ do { SB_V1_DISK_SUPER_BLOCK(s)->s_version = cpu_to_le16(val); } while (0) #define PUT_SB_BMAP_NR(s, val) \ do { SB_V1_DISK_SUPER_BLOCK(s)->s_bmap_nr = cpu_to_le16 (val); } while (0) - #define SB_ONDISK_JP(s) (&SB_V1_DISK_SUPER_BLOCK(s)->s_journal) #define SB_ONDISK_JOURNAL_SIZE(s) \ le32_to_cpu ((SB_ONDISK_JP(s)->jp_journal_size)) @@ -231,21 +225,19 @@ struct reiserfs_super_block block >= SB_JOURNAL_1st_RESERVED_BLOCK(s) \ && block < SB_JOURNAL_1st_RESERVED_BLOCK(s) + \ ((!is_reiserfs_jr(SB_DISK_SUPER_BLOCK(s)) ? \ - SB_ONDISK_JOURNAL_SIZE(s) + 1 : SB_ONDISK_RESERVED_FOR_JOURNAL(s))) - - + SB_ONDISK_JOURNAL_SIZE(s) + 1 : SB_ONDISK_RESERVED_FOR_JOURNAL(s))) /* used by gcc */ #define REISERFS_SUPER_MAGIC 0x52654973 /* used by file system utilities that - look at the superblock, etc. */ + look at the superblock, etc. */ #define REISERFS_SUPER_MAGIC_STRING "ReIsErFs" #define REISER2FS_SUPER_MAGIC_STRING "ReIsEr2Fs" #define REISER2FS_JR_SUPER_MAGIC_STRING "ReIsEr3Fs" -int is_reiserfs_3_5 (struct reiserfs_super_block * rs); -int is_reiserfs_3_6 (struct reiserfs_super_block * rs); -int is_reiserfs_jr (struct reiserfs_super_block * rs); +int is_reiserfs_3_5(struct reiserfs_super_block *rs); +int is_reiserfs_3_6(struct reiserfs_super_block *rs); +int is_reiserfs_jr(struct reiserfs_super_block *rs); /* ReiserFS leaves the first 64k unused, so that partition labels have enough space. If someone wants to write a fancy bootloader that @@ -272,8 +264,8 @@ typedef __u32 b_blocknr_t; typedef __le32 unp_t; struct unfm_nodeinfo { - unp_t unfm_nodenum; - unsigned short unfm_freespace; + unp_t unfm_nodenum; + unsigned short unfm_freespace; }; /* there are two formats of keys: 3.5 and 3.6 @@ -285,7 +277,6 @@ struct unfm_nodeinfo { #define STAT_DATA_V1 0 #define STAT_DATA_V2 1 - static inline struct reiserfs_inode_info *REISERFS_I(const struct inode *inode) { return container_of(inode, struct reiserfs_inode_info, vfs_inode); @@ -343,15 +334,13 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb) file would fit into one DIRECT item. Primary intention for this one is to increase performance by decreasing seeking. -*/ +*/ #define STORE_TAIL_IN_UNFM_S2(n_file_size,n_tail_size,n_block_size) \ (\ (!(n_tail_size)) || \ (((n_file_size) > MAX_DIRECT_ITEM_LEN(n_block_size)) ) \ ) - - /* * values for s_umount_state field */ @@ -364,9 +353,9 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb) #define TYPE_STAT_DATA 0 #define TYPE_INDIRECT 1 #define TYPE_DIRECT 2 -#define TYPE_DIRENTRY 3 -#define TYPE_MAXTYPE 3 -#define TYPE_ANY 15 // FIXME: comment is required +#define TYPE_DIRENTRY 3 +#define TYPE_MAXTYPE 3 +#define TYPE_ANY 15 // FIXME: comment is required /***************************************************************************/ /* KEY & ITEM HEAD */ @@ -376,60 +365,62 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb) // directories use this key as well as old files // struct offset_v1 { - __le32 k_offset; - __le32 k_uniqueness; + __le32 k_offset; + __le32 k_uniqueness; } __attribute__ ((__packed__)); struct offset_v2 { __le64 v; } __attribute__ ((__packed__)); -static inline __u16 offset_v2_k_type( const struct offset_v2 *v2 ) +static inline __u16 offset_v2_k_type(const struct offset_v2 *v2) { __u8 type = le64_to_cpu(v2->v) >> 60; - return (type <= TYPE_MAXTYPE)?type:TYPE_ANY; + return (type <= TYPE_MAXTYPE) ? type : TYPE_ANY; } - -static inline void set_offset_v2_k_type( struct offset_v2 *v2, int type ) + +static inline void set_offset_v2_k_type(struct offset_v2 *v2, int type) { - v2->v = (v2->v & cpu_to_le64(~0ULL>>4)) | cpu_to_le64((__u64)type<<60); + v2->v = + (v2->v & cpu_to_le64(~0ULL >> 4)) | cpu_to_le64((__u64) type << 60); } - -static inline loff_t offset_v2_k_offset( const struct offset_v2 *v2 ) + +static inline loff_t offset_v2_k_offset(const struct offset_v2 *v2) { - return le64_to_cpu(v2->v) & (~0ULL>>4); + return le64_to_cpu(v2->v) & (~0ULL >> 4); } -static inline void set_offset_v2_k_offset( struct offset_v2 *v2, loff_t offset ){ - offset &= (~0ULL>>4); - v2->v = (v2->v & cpu_to_le64(15ULL<<60)) | cpu_to_le64(offset); +static inline void set_offset_v2_k_offset(struct offset_v2 *v2, loff_t offset) +{ + offset &= (~0ULL >> 4); + v2->v = (v2->v & cpu_to_le64(15ULL << 60)) | cpu_to_le64(offset); } /* Key of an item determines its location in the S+tree, and is composed of 4 components */ struct reiserfs_key { - __le32 k_dir_id; /* packing locality: by default parent - directory object id */ - __le32 k_objectid; /* object identifier */ - union { - struct offset_v1 k_offset_v1; - struct offset_v2 k_offset_v2; - } __attribute__ ((__packed__)) u; + __le32 k_dir_id; /* packing locality: by default parent + directory object id */ + __le32 k_objectid; /* object identifier */ + union { + struct offset_v1 k_offset_v1; + struct offset_v2 k_offset_v2; + } __attribute__ ((__packed__)) u; } __attribute__ ((__packed__)); struct in_core_key { - __u32 k_dir_id; /* packing locality: by default parent - directory object id */ - __u32 k_objectid; /* object identifier */ - __u64 k_offset; - __u8 k_type; + __u32 k_dir_id; /* packing locality: by default parent + directory object id */ + __u32 k_objectid; /* object identifier */ + __u64 k_offset; + __u8 k_type; }; struct cpu_key { - struct in_core_key on_disk_key; - int version; - int key_length; /* 3 in all cases but direct2indirect and - indirect2direct conversion */ + struct in_core_key on_disk_key; + int version; + int key_length; /* 3 in all cases but direct2indirect and + indirect2direct conversion */ }; /* Our function for comparing keys can compare keys of different @@ -475,8 +466,7 @@ struct cpu_key { indirect items) and specifies the location of the item itself within the block. */ -struct item_head -{ +struct item_head { /* Everything in the tree is found by searching for it based on * its key.*/ struct reiserfs_key ih_key; @@ -492,13 +482,13 @@ struct item_head number of directory entries in the directory item. */ __le16 ih_entry_count; } __attribute__ ((__packed__)) u; - __le16 ih_item_len; /* total size of the item body */ - __le16 ih_item_location; /* an offset to the item body - * within the block */ - __le16 ih_version; /* 0 for all old items, 2 for new - ones. Highest bit is set by fsck - temporary, cleaned after all - done */ + __le16 ih_item_len; /* total size of the item body */ + __le16 ih_item_location; /* an offset to the item body + * within the block */ + __le16 ih_version; /* 0 for all old items, 2 for new + ones. Highest bit is set by fsck + temporary, cleaned after all + done */ } __attribute__ ((__packed__)); /* size of item header */ #define IH_SIZE (sizeof(struct item_head)) @@ -515,7 +505,6 @@ struct item_head #define put_ih_location(ih, val) do { (ih)->ih_item_location = cpu_to_le16(val); } while (0) #define put_ih_item_len(ih, val) do { (ih)->ih_item_len = cpu_to_le16(val); } while (0) - #define unreachable_item(ih) (ih_version(ih) & (1 << 15)) #define get_ih_free_space(ih) (ih_version (ih) == KEY_FORMAT_3_6 ? 0 : ih_free_space (ih)) @@ -537,40 +526,48 @@ struct item_head #define V1_INDIRECT_UNIQUENESS 0xfffffffe #define V1_DIRECT_UNIQUENESS 0xffffffff #define V1_DIRENTRY_UNIQUENESS 500 -#define V1_ANY_UNIQUENESS 555 // FIXME: comment is required +#define V1_ANY_UNIQUENESS 555 // FIXME: comment is required // // here are conversion routines // -static inline int uniqueness2type (__u32 uniqueness) CONSTF; -static inline int uniqueness2type (__u32 uniqueness) +static inline int uniqueness2type(__u32 uniqueness) CONSTF; +static inline int uniqueness2type(__u32 uniqueness) { - switch ((int)uniqueness) { - case V1_SD_UNIQUENESS: return TYPE_STAT_DATA; - case V1_INDIRECT_UNIQUENESS: return TYPE_INDIRECT; - case V1_DIRECT_UNIQUENESS: return TYPE_DIRECT; - case V1_DIRENTRY_UNIQUENESS: return TYPE_DIRENTRY; - default: - reiserfs_warning (NULL, "vs-500: unknown uniqueness %d", - uniqueness); + switch ((int)uniqueness) { + case V1_SD_UNIQUENESS: + return TYPE_STAT_DATA; + case V1_INDIRECT_UNIQUENESS: + return TYPE_INDIRECT; + case V1_DIRECT_UNIQUENESS: + return TYPE_DIRECT; + case V1_DIRENTRY_UNIQUENESS: + return TYPE_DIRENTRY; + default: + reiserfs_warning(NULL, "vs-500: unknown uniqueness %d", + uniqueness); case V1_ANY_UNIQUENESS: - return TYPE_ANY; - } + return TYPE_ANY; + } } -static inline __u32 type2uniqueness (int type) CONSTF; -static inline __u32 type2uniqueness (int type) +static inline __u32 type2uniqueness(int type) CONSTF; +static inline __u32 type2uniqueness(int type) { - switch (type) { - case TYPE_STAT_DATA: return V1_SD_UNIQUENESS; - case TYPE_INDIRECT: return V1_INDIRECT_UNIQUENESS; - case TYPE_DIRECT: return V1_DIRECT_UNIQUENESS; - case TYPE_DIRENTRY: return V1_DIRENTRY_UNIQUENESS; - default: - reiserfs_warning (NULL, "vs-501: unknown type %d", type); + switch (type) { + case TYPE_STAT_DATA: + return V1_SD_UNIQUENESS; + case TYPE_INDIRECT: + return V1_INDIRECT_UNIQUENESS; + case TYPE_DIRECT: + return V1_DIRECT_UNIQUENESS; + case TYPE_DIRENTRY: + return V1_DIRENTRY_UNIQUENESS; + default: + reiserfs_warning(NULL, "vs-501: unknown type %d", type); case TYPE_ANY: - return V1_ANY_UNIQUENESS; - } + return V1_ANY_UNIQUENESS; + } } // @@ -578,57 +575,56 @@ static inline __u32 type2uniqueness (int type) // there is no way to get version of object from key, so, provide // version to these defines // -static inline loff_t le_key_k_offset (int version, const struct reiserfs_key * key) +static inline loff_t le_key_k_offset(int version, + const struct reiserfs_key *key) { - return (version == KEY_FORMAT_3_5) ? - le32_to_cpu( key->u.k_offset_v1.k_offset ) : - offset_v2_k_offset( &(key->u.k_offset_v2) ); + return (version == KEY_FORMAT_3_5) ? + le32_to_cpu(key->u.k_offset_v1.k_offset) : + offset_v2_k_offset(&(key->u.k_offset_v2)); } -static inline loff_t le_ih_k_offset (const struct item_head * ih) +static inline loff_t le_ih_k_offset(const struct item_head *ih) { - return le_key_k_offset (ih_version (ih), &(ih->ih_key)); + return le_key_k_offset(ih_version(ih), &(ih->ih_key)); } -static inline loff_t le_key_k_type (int version, const struct reiserfs_key * key) +static inline loff_t le_key_k_type(int version, const struct reiserfs_key *key) { - return (version == KEY_FORMAT_3_5) ? - uniqueness2type( le32_to_cpu( key->u.k_offset_v1.k_uniqueness)) : - offset_v2_k_type( &(key->u.k_offset_v2) ); + return (version == KEY_FORMAT_3_5) ? + uniqueness2type(le32_to_cpu(key->u.k_offset_v1.k_uniqueness)) : + offset_v2_k_type(&(key->u.k_offset_v2)); } -static inline loff_t le_ih_k_type (const struct item_head * ih) +static inline loff_t le_ih_k_type(const struct item_head *ih) { - return le_key_k_type (ih_version (ih), &(ih->ih_key)); + return le_key_k_type(ih_version(ih), &(ih->ih_key)); } - -static inline void set_le_key_k_offset (int version, struct reiserfs_key * key, loff_t offset) +static inline void set_le_key_k_offset(int version, struct reiserfs_key *key, + loff_t offset) { - (version == KEY_FORMAT_3_5) ? - (void)(key->u.k_offset_v1.k_offset = cpu_to_le32 (offset)) : /* jdm check */ - (void)(set_offset_v2_k_offset( &(key->u.k_offset_v2), offset )); + (version == KEY_FORMAT_3_5) ? (void)(key->u.k_offset_v1.k_offset = cpu_to_le32(offset)) : /* jdm check */ + (void)(set_offset_v2_k_offset(&(key->u.k_offset_v2), offset)); } - -static inline void set_le_ih_k_offset (struct item_head * ih, loff_t offset) +static inline void set_le_ih_k_offset(struct item_head *ih, loff_t offset) { - set_le_key_k_offset (ih_version (ih), &(ih->ih_key), offset); + set_le_key_k_offset(ih_version(ih), &(ih->ih_key), offset); } - -static inline void set_le_key_k_type (int version, struct reiserfs_key * key, int type) +static inline void set_le_key_k_type(int version, struct reiserfs_key *key, + int type) { - (version == KEY_FORMAT_3_5) ? - (void)(key->u.k_offset_v1.k_uniqueness = cpu_to_le32(type2uniqueness(type))): - (void)(set_offset_v2_k_type( &(key->u.k_offset_v2), type )); + (version == KEY_FORMAT_3_5) ? + (void)(key->u.k_offset_v1.k_uniqueness = + cpu_to_le32(type2uniqueness(type))) + : (void)(set_offset_v2_k_type(&(key->u.k_offset_v2), type)); } -static inline void set_le_ih_k_type (struct item_head * ih, int type) +static inline void set_le_ih_k_type(struct item_head *ih, int type) { - set_le_key_k_type (ih_version (ih), &(ih->ih_key), type); + set_le_key_k_type(ih_version(ih), &(ih->ih_key), type); } - #define is_direntry_le_key(version,key) (le_key_k_type (version, key) == TYPE_DIRENTRY) #define is_direct_le_key(version,key) (le_key_k_type (version, key) == TYPE_DIRECT) #define is_indirect_le_key(version,key) (le_key_k_type (version, key) == TYPE_INDIRECT) @@ -642,34 +638,32 @@ static inline void set_le_ih_k_type (struct item_head * ih, int type) #define is_indirect_le_ih(ih) is_indirect_le_key (ih_version(ih), &((ih)->ih_key)) #define is_statdata_le_ih(ih) is_statdata_le_key (ih_version (ih), &((ih)->ih_key)) - - // // key is pointer to cpu key, result is cpu // -static inline loff_t cpu_key_k_offset (const struct cpu_key * key) +static inline loff_t cpu_key_k_offset(const struct cpu_key *key) { - return key->on_disk_key.k_offset; + return key->on_disk_key.k_offset; } -static inline loff_t cpu_key_k_type (const struct cpu_key * key) +static inline loff_t cpu_key_k_type(const struct cpu_key *key) { - return key->on_disk_key.k_type; + return key->on_disk_key.k_type; } -static inline void set_cpu_key_k_offset (struct cpu_key * key, loff_t offset) +static inline void set_cpu_key_k_offset(struct cpu_key *key, loff_t offset) { key->on_disk_key.k_offset = offset; } -static inline void set_cpu_key_k_type (struct cpu_key * key, int type) +static inline void set_cpu_key_k_type(struct cpu_key *key, int type) { key->on_disk_key.k_type = type; } -static inline void cpu_key_k_offset_dec (struct cpu_key * key) +static inline void cpu_key_k_offset_dec(struct cpu_key *key) { - key->on_disk_key.k_offset --; + key->on_disk_key.k_offset--; } #define is_direntry_cpu_key(key) (cpu_key_k_type (key) == TYPE_DIRENTRY) @@ -677,34 +671,25 @@ static inline void cpu_key_k_offset_dec (struct cpu_key * key) #define is_indirect_cpu_key(key) (cpu_key_k_type (key) == TYPE_INDIRECT) #define is_statdata_cpu_key(key) (cpu_key_k_type (key) == TYPE_STAT_DATA) - /* are these used ? */ #define is_direntry_cpu_ih(ih) (is_direntry_cpu_key (&((ih)->ih_key))) #define is_direct_cpu_ih(ih) (is_direct_cpu_key (&((ih)->ih_key))) #define is_indirect_cpu_ih(ih) (is_indirect_cpu_key (&((ih)->ih_key))) #define is_statdata_cpu_ih(ih) (is_statdata_cpu_key (&((ih)->ih_key))) - - - - #define I_K_KEY_IN_ITEM(p_s_ih, p_s_key, n_blocksize) \ ( ! COMP_SHORT_KEYS(p_s_ih, p_s_key) && \ I_OFF_BYTE_IN_ITEM(p_s_ih, k_offset (p_s_key), n_blocksize) ) -/* maximal length of item */ +/* maximal length of item */ #define MAX_ITEM_LEN(block_size) (block_size - BLKH_SIZE - IH_SIZE) #define MIN_ITEM_LEN 1 - /* object identifier for root dir */ #define REISERFS_ROOT_OBJECTID 2 #define REISERFS_ROOT_PARENT_OBJECTID 1 extern struct reiserfs_key root_key; - - - /* * Picture represents a leaf of the S+tree * ______________________________________________________ @@ -716,13 +701,13 @@ extern struct reiserfs_key root_key; /* Header of a disk block. More precisely, header of a formatted leaf or internal node, and not the header of an unformatted node. */ -struct block_head { - __le16 blk_level; /* Level of a block in the tree. */ - __le16 blk_nr_item; /* Number of keys/items in a block. */ - __le16 blk_free_space; /* Block free space in bytes. */ - __le16 blk_reserved; - /* dump this in v4/planA */ - struct reiserfs_key blk_right_delim_key; /* kept only for compatibility */ +struct block_head { + __le16 blk_level; /* Level of a block in the tree. */ + __le16 blk_nr_item; /* Number of keys/items in a block. */ + __le16 blk_free_space; /* Block free space in bytes. */ + __le16 blk_reserved; + /* dump this in v4/planA */ + struct reiserfs_key blk_right_delim_key; /* kept only for compatibility */ }; #define BLKH_SIZE (sizeof(struct block_head)) @@ -741,12 +726,12 @@ struct block_head { * values for blk_level field of the struct block_head */ -#define FREE_LEVEL 0 /* when node gets removed from the tree its - blk_level is set to FREE_LEVEL. It is then - used to see whether the node is still in the - tree */ +#define FREE_LEVEL 0 /* when node gets removed from the tree its + blk_level is set to FREE_LEVEL. It is then + used to see whether the node is still in the + tree */ -#define DISK_LEAF_NODE_LEVEL 1 /* Leaf node level.*/ +#define DISK_LEAF_NODE_LEVEL 1 /* Leaf node level. */ /* Given the buffer head of a formatted node, resolve to the block head of that node. */ #define B_BLK_HEAD(p_s_bh) ((struct block_head *)((p_s_bh)->b_data)) @@ -759,7 +744,6 @@ struct block_head { #define PUT_B_LEVEL(p_s_bh,val) do { set_blkh_level(B_BLK_HEAD(p_s_bh),val); } while (0) #define PUT_B_FREE_SPACE(p_s_bh,val) do { set_blkh_free_space(B_BLK_HEAD(p_s_bh),val); } while (0) - /* Get right delimiting key. -- little endian */ #define B_PRIGHT_DELIM_KEY(p_s_bh) (&(blk_right_delim_key(B_BLK_HEAD(p_s_bh)) @@ -770,41 +754,36 @@ struct block_head { #define B_IS_KEYS_LEVEL(p_s_bh) (B_LEVEL(p_s_bh) > DISK_LEAF_NODE_LEVEL \ && B_LEVEL(p_s_bh) <= MAX_HEIGHT) - - - /***************************************************************************/ /* STAT DATA */ /***************************************************************************/ - // // old stat data is 32 bytes long. We are going to distinguish new one by // different size // -struct stat_data_v1 -{ - __le16 sd_mode; /* file type, permissions */ - __le16 sd_nlink; /* number of hard links */ - __le16 sd_uid; /* owner */ - __le16 sd_gid; /* group */ - __le32 sd_size; /* file size */ - __le32 sd_atime; /* time of last access */ - __le32 sd_mtime; /* time file was last modified */ - __le32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ - union { - __le32 sd_rdev; - __le32 sd_blocks; /* number of blocks file uses */ - } __attribute__ ((__packed__)) u; - __le32 sd_first_direct_byte; /* first byte of file which is stored - in a direct item: except that if it - equals 1 it is a symlink and if it - equals ~(__u32)0 there is no - direct item. The existence of this - field really grates on me. Let's - replace it with a macro based on - sd_size and our tail suppression - policy. Someday. -Hans */ +struct stat_data_v1 { + __le16 sd_mode; /* file type, permissions */ + __le16 sd_nlink; /* number of hard links */ + __le16 sd_uid; /* owner */ + __le16 sd_gid; /* group */ + __le32 sd_size; /* file size */ + __le32 sd_atime; /* time of last access */ + __le32 sd_mtime; /* time file was last modified */ + __le32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ + union { + __le32 sd_rdev; + __le32 sd_blocks; /* number of blocks file uses */ + } __attribute__ ((__packed__)) u; + __le32 sd_first_direct_byte; /* first byte of file which is stored + in a direct item: except that if it + equals 1 it is a symlink and if it + equals ~(__u32)0 there is no + direct item. The existence of this + field really grates on me. Let's + replace it with a macro based on + sd_size and our tail suppression + policy. Someday. -Hans */ } __attribute__ ((__packed__)); #define SD_V1_SIZE (sizeof(struct stat_data_v1)) @@ -862,29 +841,29 @@ struct stat_data_v1 /* Stat Data on disk (reiserfs version of UFS disk inode minus the address blocks) */ struct stat_data { - __le16 sd_mode; /* file type, permissions */ - __le16 sd_attrs; /* persistent inode flags */ - __le32 sd_nlink; /* number of hard links */ - __le64 sd_size; /* file size */ - __le32 sd_uid; /* owner */ - __le32 sd_gid; /* group */ - __le32 sd_atime; /* time of last access */ - __le32 sd_mtime; /* time file was last modified */ - __le32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ - __le32 sd_blocks; - union { - __le32 sd_rdev; - __le32 sd_generation; - //__le32 sd_first_direct_byte; - /* first byte of file which is stored in a - direct item: except that if it equals 1 - it is a symlink and if it equals - ~(__u32)0 there is no direct item. The - existence of this field really grates - on me. Let's replace it with a macro - based on sd_size and our tail - suppression policy? */ - } __attribute__ ((__packed__)) u; + __le16 sd_mode; /* file type, permissions */ + __le16 sd_attrs; /* persistent inode flags */ + __le32 sd_nlink; /* number of hard links */ + __le64 sd_size; /* file size */ + __le32 sd_uid; /* owner */ + __le32 sd_gid; /* group */ + __le32 sd_atime; /* time of last access */ + __le32 sd_mtime; /* time file was last modified */ + __le32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ + __le32 sd_blocks; + union { + __le32 sd_rdev; + __le32 sd_generation; + //__le32 sd_first_direct_byte; + /* first byte of file which is stored in a + direct item: except that if it equals 1 + it is a symlink and if it equals + ~(__u32)0 there is no direct item. The + existence of this field really grates + on me. Let's replace it with a macro + based on sd_size and our tail + suppression policy? */ + } __attribute__ ((__packed__)) u; } __attribute__ ((__packed__)); // // this is 44 bytes long @@ -919,7 +898,6 @@ struct stat_data { #define sd_v2_attrs(sdp) (le16_to_cpu((sdp)->sd_attrs)) #define set_sd_v2_attrs(sdp,v) ((sdp)->sd_attrs = cpu_to_le16(v)) - /***************************************************************************/ /* DIRECTORY STRUCTURE */ /***************************************************************************/ @@ -954,17 +932,14 @@ struct stat_data { /* NOT IMPLEMENTED: Directory will someday contain stat data of object */ - - -struct reiserfs_de_head -{ - __le32 deh_offset; /* third component of the directory entry key */ - __le32 deh_dir_id; /* objectid of the parent directory of the object, that is referenced - by directory entry */ - __le32 deh_objectid; /* objectid of the object, that is referenced by directory entry */ - __le16 deh_location; /* offset of name in the whole item */ - __le16 deh_state; /* whether 1) entry contains stat data (for future), and 2) whether - entry is hidden (unlinked) */ +struct reiserfs_de_head { + __le32 deh_offset; /* third component of the directory entry key */ + __le32 deh_dir_id; /* objectid of the parent directory of the object, that is referenced + by directory entry */ + __le32 deh_objectid; /* objectid of the object, that is referenced by directory entry */ + __le16 deh_location; /* offset of name in the whole item */ + __le16 deh_state; /* whether 1) entry contains stat data (for future), and 2) whether + entry is hidden (unlinked) */ } __attribute__ ((__packed__)); #define DEH_SIZE sizeof(struct reiserfs_de_head) #define deh_offset(p_deh) (le32_to_cpu((p_deh)->deh_offset)) @@ -986,7 +961,7 @@ struct reiserfs_de_head /* old format directories have this size when empty */ #define EMPTY_DIR_SIZE_V1 (DEH_SIZE * 2 + 3) -#define DEH_Statdata 0 /* not used now */ +#define DEH_Statdata 0 /* not used now */ #define DEH_Visible 2 /* 64 bit systems (and the S/390) need to be aligned explicitly -jdm */ @@ -1023,10 +998,10 @@ struct reiserfs_de_head #define de_visible(deh) test_bit_unaligned (DEH_Visible, &((deh)->deh_state)) #define de_hidden(deh) !test_bit_unaligned (DEH_Visible, &((deh)->deh_state)) -extern void make_empty_dir_item_v1 (char * body, __le32 dirid, __le32 objid, - __le32 par_dirid, __le32 par_objid); -extern void make_empty_dir_item (char * body, __le32 dirid, __le32 objid, - __le32 par_dirid, __le32 par_objid); +extern void make_empty_dir_item_v1(char *body, __le32 dirid, __le32 objid, + __le32 par_dirid, __le32 par_objid); +extern void make_empty_dir_item(char *body, __le32 dirid, __le32 objid, + __le32 par_dirid, __le32 par_objid); /* array of the entry headers */ /* get item body */ @@ -1043,53 +1018,48 @@ extern void make_empty_dir_item (char * body, __le32 dirid, __le32 objid, #define I_DEH_N_ENTRY_LENGTH(ih,deh,i) \ ((i) ? (deh_location((deh)-1) - deh_location((deh))) : (ih_item_len((ih)) - deh_location((deh)))) */ -static inline int entry_length (const struct buffer_head * bh, - const struct item_head * ih, int pos_in_item) +static inline int entry_length(const struct buffer_head *bh, + const struct item_head *ih, int pos_in_item) { - struct reiserfs_de_head * deh; + struct reiserfs_de_head *deh; - deh = B_I_DEH (bh, ih) + pos_in_item; - if (pos_in_item) - return deh_location(deh-1) - deh_location(deh); + deh = B_I_DEH(bh, ih) + pos_in_item; + if (pos_in_item) + return deh_location(deh - 1) - deh_location(deh); - return ih_item_len(ih) - deh_location(deh); + return ih_item_len(ih) - deh_location(deh); } - - /* number of entries in the directory item, depends on ENTRY_COUNT being at the start of directory dynamic data. */ #define I_ENTRY_COUNT(ih) (ih_entry_count((ih))) - /* name by bh, ih and entry_num */ #define B_I_E_NAME(bh,ih,entry_num) ((char *)(bh->b_data + ih_location(ih) + deh_location(B_I_DEH(bh,ih)+(entry_num)))) // two entries per block (at least) #define REISERFS_MAX_NAME(block_size) 255 - /* this structure is used for operations on directory entries. It is not a disk structure. */ /* When reiserfs_find_entry or search_by_entry_key find directory entry, they return filled reiserfs_dir_entry structure */ -struct reiserfs_dir_entry -{ - struct buffer_head * de_bh; - int de_item_num; - struct item_head * de_ih; - int de_entry_num; - struct reiserfs_de_head * de_deh; - int de_entrylen; - int de_namelen; - char * de_name; - char * de_gen_number_bit_string; - - __u32 de_dir_id; - __u32 de_objectid; - - struct cpu_key de_entry_key; +struct reiserfs_dir_entry { + struct buffer_head *de_bh; + int de_item_num; + struct item_head *de_ih; + int de_entry_num; + struct reiserfs_de_head *de_deh; + int de_entrylen; + int de_namelen; + char *de_name; + char *de_gen_number_bit_string; + + __u32 de_dir_id; + __u32 de_objectid; + + struct cpu_key de_entry_key; }; - + /* these defines are useful when a particular member of a reiserfs_dir_entry is needed */ /* pointer to file name, stored in entry */ @@ -1099,8 +1069,6 @@ struct reiserfs_dir_entry #define I_DEH_N_ENTRY_FILE_NAME_LENGTH(ih,deh,entry_num) \ (I_DEH_N_ENTRY_LENGTH (ih, deh, entry_num) - (de_with_sd (deh) ? SD_SIZE : 0)) - - /* hash value occupies bits from 7 up to 30 */ #define GET_HASH_VALUE(offset) ((offset) & 0x7fffff80LL) /* generation number occupies 7 bits starting from 0 up to 6 */ @@ -1109,7 +1077,6 @@ struct reiserfs_dir_entry #define SET_GENERATION_NUMBER(offset,gen_number) (GET_HASH_VALUE(offset)|(gen_number)) - /* * Picture represents an internal node of the reiserfs tree * ______________________________________________________ @@ -1125,9 +1092,9 @@ struct reiserfs_dir_entry /* Disk child pointer: The pointer from an internal node of the tree to a node that is on disk. */ struct disk_child { - __le32 dc_block_number; /* Disk child's block number. */ - __le16 dc_size; /* Disk child's used space. */ - __le16 dc_reserved; + __le32 dc_block_number; /* Disk child's block number. */ + __le16 dc_size; /* Disk child's used space. */ + __le16 dc_reserved; }; #define DC_SIZE (sizeof(struct disk_child)) @@ -1144,7 +1111,7 @@ struct disk_child { #define B_N_CHILD_NUM(p_s_bh,n_pos) (dc_block_number(B_N_CHILD(p_s_bh,n_pos))) #define PUT_B_N_CHILD_NUM(p_s_bh,n_pos, val) (put_dc_block_number(B_N_CHILD(p_s_bh,n_pos), val )) - /* maximal value of field child_size in structure disk_child */ + /* maximal value of field child_size in structure disk_child */ /* child size is the combined size of all items and their headers */ #define MAX_CHILD_SIZE(bh) ((int)( (bh)->b_size - BLKH_SIZE )) @@ -1159,7 +1126,6 @@ struct disk_child { /* PATH STRUCTURES AND DEFINES */ /***************************************************************************/ - /* Search_by_key fills up the path from the root to the leaf as it descends the tree looking for the key. It uses reiserfs_bread to try to find buffers in the cache given their block number. If it does not find them in the cache it reads them from disk. For each node search_by_key finds using @@ -1168,20 +1134,18 @@ struct disk_child { is looking through a leaf node bin_search will find the position of the item which has key either equal to given key, or which is the maximal key less than the given key. */ -struct path_element { - struct buffer_head * pe_buffer; /* Pointer to the buffer at the path in the tree. */ - int pe_position; /* Position in the tree node which is placed in the */ - /* buffer above. */ +struct path_element { + struct buffer_head *pe_buffer; /* Pointer to the buffer at the path in the tree. */ + int pe_position; /* Position in the tree node which is placed in the */ + /* buffer above. */ }; -#define MAX_HEIGHT 5 /* maximal height of a tree. don't change this without changing JOURNAL_PER_BALANCE_CNT */ -#define EXTENDED_MAX_HEIGHT 7 /* Must be equals MAX_HEIGHT + FIRST_PATH_ELEMENT_OFFSET */ -#define FIRST_PATH_ELEMENT_OFFSET 2 /* Must be equal to at least 2. */ - -#define ILLEGAL_PATH_ELEMENT_OFFSET 1 /* Must be equal to FIRST_PATH_ELEMENT_OFFSET - 1 */ -#define MAX_FEB_SIZE 6 /* this MUST be MAX_HEIGHT + 1. See about FEB below */ - +#define MAX_HEIGHT 5 /* maximal height of a tree. don't change this without changing JOURNAL_PER_BALANCE_CNT */ +#define EXTENDED_MAX_HEIGHT 7 /* Must be equals MAX_HEIGHT + FIRST_PATH_ELEMENT_OFFSET */ +#define FIRST_PATH_ELEMENT_OFFSET 2 /* Must be equal to at least 2. */ +#define ILLEGAL_PATH_ELEMENT_OFFSET 1 /* Must be equal to FIRST_PATH_ELEMENT_OFFSET - 1 */ +#define MAX_FEB_SIZE 6 /* this MUST be MAX_HEIGHT + 1. See about FEB below */ /* We need to keep track of who the ancestors of nodes are. When we perform a search we record which nodes were visited while @@ -1200,14 +1164,14 @@ excessive effort to avoid disturbing the precious VFS code.:-( The gods only know how we are going to SMP the code that uses them. znodes are the way! */ -#define PATH_READA 0x1 /* do read ahead */ -#define PATH_READA_BACK 0x2 /* read backwards */ +#define PATH_READA 0x1 /* do read ahead */ +#define PATH_READA_BACK 0x2 /* read backwards */ -struct path { - int path_length; /* Length of the array above. */ - int reada; - struct path_element path_elements[EXTENDED_MAX_HEIGHT]; /* Array of the path elements. */ - int pos_in_item; +struct path { + int path_length; /* Length of the array above. */ + int reada; + struct path_element path_elements[EXTENDED_MAX_HEIGHT]; /* Array of the path elements. */ + int pos_in_item; }; #define pos_in_item(path) ((path)->pos_in_item) @@ -1224,25 +1188,23 @@ struct path var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,} /* Get position in the element at the path by path and path position. */ #define PATH_OFFSET_POSITION(p_s_path,n_offset) (PATH_OFFSET_PELEMENT(p_s_path,n_offset)->pe_position) - #define PATH_PLAST_BUFFER(p_s_path) (PATH_OFFSET_PBUFFER((p_s_path), (p_s_path)->path_length)) /* you know, to the person who didn't - write this the macro name does not - at first suggest what it does. - Maybe POSITION_FROM_PATH_END? Or - maybe we should just focus on - dumping paths... -Hans */ + write this the macro name does not + at first suggest what it does. + Maybe POSITION_FROM_PATH_END? Or + maybe we should just focus on + dumping paths... -Hans */ #define PATH_LAST_POSITION(p_s_path) (PATH_OFFSET_POSITION((p_s_path), (p_s_path)->path_length)) - #define PATH_PITEM_HEAD(p_s_path) B_N_PITEM_HEAD(PATH_PLAST_BUFFER(p_s_path),PATH_LAST_POSITION(p_s_path)) /* in do_balance leaf has h == 0 in contrast with path structure, where root has level == 0. That is why we need these defines */ #define PATH_H_PBUFFER(p_s_path, h) PATH_OFFSET_PBUFFER (p_s_path, p_s_path->path_length - (h)) /* tb->S[h] */ -#define PATH_H_PPARENT(path, h) PATH_H_PBUFFER (path, (h) + 1) /* tb->F[h] or tb->S[0]->b_parent */ -#define PATH_H_POSITION(path, h) PATH_OFFSET_POSITION (path, path->path_length - (h)) -#define PATH_H_B_ITEM_ORDER(path, h) PATH_H_POSITION(path, h + 1) /* tb->S[h]->b_item_order */ +#define PATH_H_PPARENT(path, h) PATH_H_PBUFFER (path, (h) + 1) /* tb->F[h] or tb->S[0]->b_parent */ +#define PATH_H_POSITION(path, h) PATH_OFFSET_POSITION (path, path->path_length - (h)) +#define PATH_H_B_ITEM_ORDER(path, h) PATH_H_POSITION(path, h + 1) /* tb->S[h]->b_item_order */ #define PATH_H_PATH_OFFSET(p_s_path, n_h) ((p_s_path)->path_length - (n_h)) @@ -1253,7 +1215,6 @@ struct path var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,} #define item_moved(ih,path) comp_items(ih, path) #define path_changed(ih,path) comp_items (ih, path) - /***************************************************************************/ /* MISC */ /***************************************************************************/ @@ -1272,30 +1233,26 @@ struct path var = {.path_length = ILLEGAL_PATH_ELEMENT_OFFSET, .reada = 0,} // reiserfs version 2 has max offset 60 bits. Version 1 - 32 bit offset #define U32_MAX (~(__u32)0) -static inline loff_t max_reiserfs_offset (struct inode * inode) +static inline loff_t max_reiserfs_offset(struct inode *inode) { - if (get_inode_item_key_version(inode) == KEY_FORMAT_3_5) - return (loff_t)U32_MAX; + if (get_inode_item_key_version(inode) == KEY_FORMAT_3_5) + return (loff_t) U32_MAX; - return (loff_t)((~(__u64)0) >> 4); + return (loff_t) ((~(__u64) 0) >> 4); } - /*#define MAX_KEY_UNIQUENESS MAX_UL_INT*/ #define MAX_KEY_OBJECTID MAX_UL_INT - #define MAX_B_NUM MAX_UL_INT #define MAX_FC_NUM MAX_US_INT - /* the purpose is to detect overflow of an unsigned short */ #define REISERFS_LINK_MAX (MAX_US_INT - 1000) - /* The following defines are used in reiserfs_insert_item and reiserfs_append_item */ -#define REISERFS_KERNEL_MEM 0 /* reiserfs kernel memory mode */ -#define REISERFS_USER_MEM 1 /* reiserfs user memory mode */ +#define REISERFS_KERNEL_MEM 0 /* reiserfs kernel memory mode */ +#define REISERFS_USER_MEM 1 /* reiserfs user memory mode */ #define fs_generation(s) (REISERFS_SB(s)->s_generation_counter) #define get_generation(s) atomic_read (&fs_generation(s)) @@ -1303,7 +1260,6 @@ static inline loff_t max_reiserfs_offset (struct inode * inode) #define __fs_changed(gen,s) (gen != get_generation (s)) #define fs_changed(gen,s) ({cond_resched(); __fs_changed(gen, s);}) - /***************************************************************************/ /* FIXATE NODES */ /***************************************************************************/ @@ -1324,38 +1280,34 @@ static inline loff_t max_reiserfs_offset (struct inode * inode) calculating what we can shift to neighbors and how many nodes we have to have if we do not any shiftings, if we shift to left/right neighbor or to both. */ -struct virtual_item -{ - int vi_index; // index in the array of item operations - unsigned short vi_type; // left/right mergeability - unsigned short vi_item_len; /* length of item that it will have after balancing */ - struct item_head * vi_ih; - const char * vi_item; // body of item (old or new) - const void * vi_new_data; // 0 always but paste mode - void * vi_uarea; // item specific area +struct virtual_item { + int vi_index; // index in the array of item operations + unsigned short vi_type; // left/right mergeability + unsigned short vi_item_len; /* length of item that it will have after balancing */ + struct item_head *vi_ih; + const char *vi_item; // body of item (old or new) + const void *vi_new_data; // 0 always but paste mode + void *vi_uarea; // item specific area }; - -struct virtual_node -{ - char * vn_free_ptr; /* this is a pointer to the free space in the buffer */ - unsigned short vn_nr_item; /* number of items in virtual node */ - short vn_size; /* size of node , that node would have if it has unlimited size and no balancing is performed */ - short vn_mode; /* mode of balancing (paste, insert, delete, cut) */ - short vn_affected_item_num; - short vn_pos_in_item; - struct item_head * vn_ins_ih; /* item header of inserted item, 0 for other modes */ - const void * vn_data; - struct virtual_item * vn_vi; /* array of items (including a new one, excluding item to be deleted) */ +struct virtual_node { + char *vn_free_ptr; /* this is a pointer to the free space in the buffer */ + unsigned short vn_nr_item; /* number of items in virtual node */ + short vn_size; /* size of node , that node would have if it has unlimited size and no balancing is performed */ + short vn_mode; /* mode of balancing (paste, insert, delete, cut) */ + short vn_affected_item_num; + short vn_pos_in_item; + struct item_head *vn_ins_ih; /* item header of inserted item, 0 for other modes */ + const void *vn_data; + struct virtual_item *vn_vi; /* array of items (including a new one, excluding item to be deleted) */ }; /* used by directory items when creating virtual nodes */ struct direntry_uarea { - int flags; - __u16 entry_count; - __u16 entry_sizes[1]; -} __attribute__ ((__packed__)) ; - + int flags; + __u16 entry_count; + __u16 entry_sizes[1]; +} __attribute__ ((__packed__)); /***************************************************************************/ /* TREE BALANCE */ @@ -1378,73 +1330,72 @@ struct direntry_uarea { #define MAX_AMOUNT_NEEDED 2 /* someday somebody will prefix every field in this struct with tb_ */ -struct tree_balance -{ - int tb_mode; - int need_balance_dirty; - struct super_block * tb_sb; - struct reiserfs_transaction_handle *transaction_handle ; - struct path * tb_path; - struct buffer_head * L[MAX_HEIGHT]; /* array of left neighbors of nodes in the path */ - struct buffer_head * R[MAX_HEIGHT]; /* array of right neighbors of nodes in the path*/ - struct buffer_head * FL[MAX_HEIGHT]; /* array of fathers of the left neighbors */ - struct buffer_head * FR[MAX_HEIGHT]; /* array of fathers of the right neighbors */ - struct buffer_head * CFL[MAX_HEIGHT]; /* array of common parents of center node and its left neighbor */ - struct buffer_head * CFR[MAX_HEIGHT]; /* array of common parents of center node and its right neighbor */ - - struct buffer_head * FEB[MAX_FEB_SIZE]; /* array of empty buffers. Number of buffers in array equals - cur_blknum. */ - struct buffer_head * used[MAX_FEB_SIZE]; - struct buffer_head * thrown[MAX_FEB_SIZE]; - int lnum[MAX_HEIGHT]; /* array of number of items which must be - shifted to the left in order to balance the - current node; for leaves includes item that - will be partially shifted; for internal - nodes, it is the number of child pointers - rather than items. It includes the new item - being created. The code sometimes subtracts - one to get the number of wholly shifted - items for other purposes. */ - int rnum[MAX_HEIGHT]; /* substitute right for left in comment above */ - int lkey[MAX_HEIGHT]; /* array indexed by height h mapping the key delimiting L[h] and - S[h] to its item number within the node CFL[h] */ - int rkey[MAX_HEIGHT]; /* substitute r for l in comment above */ - int insert_size[MAX_HEIGHT]; /* the number of bytes by we are trying to add or remove from - S[h]. A negative value means removing. */ - int blknum[MAX_HEIGHT]; /* number of nodes that will replace node S[h] after - balancing on the level h of the tree. If 0 then S is - being deleted, if 1 then S is remaining and no new nodes - are being created, if 2 or 3 then 1 or 2 new nodes is - being created */ - - /* fields that are used only for balancing leaves of the tree */ - int cur_blknum; /* number of empty blocks having been already allocated */ - int s0num; /* number of items that fall into left most node when S[0] splits */ - int s1num; /* number of items that fall into first new node when S[0] splits */ - int s2num; /* number of items that fall into second new node when S[0] splits */ - int lbytes; /* number of bytes which can flow to the left neighbor from the left */ - /* most liquid item that cannot be shifted from S[0] entirely */ - /* if -1 then nothing will be partially shifted */ - int rbytes; /* number of bytes which will flow to the right neighbor from the right */ - /* most liquid item that cannot be shifted from S[0] entirely */ - /* if -1 then nothing will be partially shifted */ - int s1bytes; /* number of bytes which flow to the first new node when S[0] splits */ - /* note: if S[0] splits into 3 nodes, then items do not need to be cut */ - int s2bytes; - struct buffer_head * buf_to_free[MAX_FREE_BLOCK]; /* buffers which are to be freed after do_balance finishes by unfix_nodes */ - char * vn_buf; /* kmalloced memory. Used to create +struct tree_balance { + int tb_mode; + int need_balance_dirty; + struct super_block *tb_sb; + struct reiserfs_transaction_handle *transaction_handle; + struct path *tb_path; + struct buffer_head *L[MAX_HEIGHT]; /* array of left neighbors of nodes in the path */ + struct buffer_head *R[MAX_HEIGHT]; /* array of right neighbors of nodes in the path */ + struct buffer_head *FL[MAX_HEIGHT]; /* array of fathers of the left neighbors */ + struct buffer_head *FR[MAX_HEIGHT]; /* array of fathers of the right neighbors */ + struct buffer_head *CFL[MAX_HEIGHT]; /* array of common parents of center node and its left neighbor */ + struct buffer_head *CFR[MAX_HEIGHT]; /* array of common parents of center node and its right neighbor */ + + struct buffer_head *FEB[MAX_FEB_SIZE]; /* array of empty buffers. Number of buffers in array equals + cur_blknum. */ + struct buffer_head *used[MAX_FEB_SIZE]; + struct buffer_head *thrown[MAX_FEB_SIZE]; + int lnum[MAX_HEIGHT]; /* array of number of items which must be + shifted to the left in order to balance the + current node; for leaves includes item that + will be partially shifted; for internal + nodes, it is the number of child pointers + rather than items. It includes the new item + being created. The code sometimes subtracts + one to get the number of wholly shifted + items for other purposes. */ + int rnum[MAX_HEIGHT]; /* substitute right for left in comment above */ + int lkey[MAX_HEIGHT]; /* array indexed by height h mapping the key delimiting L[h] and + S[h] to its item number within the node CFL[h] */ + int rkey[MAX_HEIGHT]; /* substitute r for l in comment above */ + int insert_size[MAX_HEIGHT]; /* the number of bytes by we are trying to add or remove from + S[h]. A negative value means removing. */ + int blknum[MAX_HEIGHT]; /* number of nodes that will replace node S[h] after + balancing on the level h of the tree. If 0 then S is + being deleted, if 1 then S is remaining and no new nodes + are being created, if 2 or 3 then 1 or 2 new nodes is + being created */ + + /* fields that are used only for balancing leaves of the tree */ + int cur_blknum; /* number of empty blocks having been already allocated */ + int s0num; /* number of items that fall into left most node when S[0] splits */ + int s1num; /* number of items that fall into first new node when S[0] splits */ + int s2num; /* number of items that fall into second new node when S[0] splits */ + int lbytes; /* number of bytes which can flow to the left neighbor from the left */ + /* most liquid item that cannot be shifted from S[0] entirely */ + /* if -1 then nothing will be partially shifted */ + int rbytes; /* number of bytes which will flow to the right neighbor from the right */ + /* most liquid item that cannot be shifted from S[0] entirely */ + /* if -1 then nothing will be partially shifted */ + int s1bytes; /* number of bytes which flow to the first new node when S[0] splits */ + /* note: if S[0] splits into 3 nodes, then items do not need to be cut */ + int s2bytes; + struct buffer_head *buf_to_free[MAX_FREE_BLOCK]; /* buffers which are to be freed after do_balance finishes by unfix_nodes */ + char *vn_buf; /* kmalloced memory. Used to create virtual node and keep map of dirtied bitmap blocks */ - int vn_buf_size; /* size of the vn_buf */ - struct virtual_node * tb_vn; /* VN starts after bitmap of bitmap blocks */ + int vn_buf_size; /* size of the vn_buf */ + struct virtual_node *tb_vn; /* VN starts after bitmap of bitmap blocks */ - int fs_gen; /* saved value of `reiserfs_generation' counter - see FILESYSTEM_CHANGED() macro in reiserfs_fs.h */ + int fs_gen; /* saved value of `reiserfs_generation' counter + see FILESYSTEM_CHANGED() macro in reiserfs_fs.h */ #ifdef DISPLACE_NEW_PACKING_LOCALITIES - struct in_core_key key; /* key pointer, to pass to block allocator or - another low-level subsystem */ + struct in_core_key key; /* key pointer, to pass to block allocator or + another low-level subsystem */ #endif -} ; +}; /* These are modes of balancing */ @@ -1479,13 +1430,12 @@ struct tree_balance /* used in do_balance for passing parent of node information that has been gotten from tb struct */ struct buffer_info { - struct tree_balance * tb; - struct buffer_head * bi_bh; - struct buffer_head * bi_parent; - int bi_position; + struct tree_balance *tb; + struct buffer_head *bi_bh; + struct buffer_head *bi_parent; + int bi_position; }; - /* there are 4 types of items: stat data, directory item, indirect, direct. +-------------------+------------+--------------+------------+ | | k_offset | k_uniqueness | mergeable? | @@ -1503,24 +1453,24 @@ struct buffer_info { */ struct item_operations { - int (*bytes_number) (struct item_head * ih, int block_size); - void (*decrement_key) (struct cpu_key *); - int (*is_left_mergeable) (struct reiserfs_key * ih, unsigned long bsize); - void (*print_item) (struct item_head *, char * item); - void (*check_item) (struct item_head *, char * item); - - int (*create_vi) (struct virtual_node * vn, struct virtual_item * vi, - int is_affected, int insert_size); - int (*check_left) (struct virtual_item * vi, int free, - int start_skip, int end_skip); - int (*check_right) (struct virtual_item * vi, int free); - int (*part_size) (struct virtual_item * vi, int from, int to); - int (*unit_num) (struct virtual_item * vi); - void (*print_vi) (struct virtual_item * vi); + int (*bytes_number) (struct item_head * ih, int block_size); + void (*decrement_key) (struct cpu_key *); + int (*is_left_mergeable) (struct reiserfs_key * ih, + unsigned long bsize); + void (*print_item) (struct item_head *, char *item); + void (*check_item) (struct item_head *, char *item); + + int (*create_vi) (struct virtual_node * vn, struct virtual_item * vi, + int is_affected, int insert_size); + int (*check_left) (struct virtual_item * vi, int free, + int start_skip, int end_skip); + int (*check_right) (struct virtual_item * vi, int free); + int (*part_size) (struct virtual_item * vi, int from, int to); + int (*unit_num) (struct virtual_item * vi); + void (*print_vi) (struct virtual_item * vi); }; - -extern struct item_operations * item_ops [TYPE_ANY + 1]; +extern struct item_operations *item_ops[TYPE_ANY + 1]; #define op_bytes_number(ih,bsize) item_ops[le_ih_k_type (ih)]->bytes_number (ih, bsize) #define op_is_left_mergeable(key,bsize) item_ops[le_key_k_type (le_key_version (key), key)]->is_left_mergeable (key, bsize) @@ -1533,8 +1483,6 @@ extern struct item_operations * item_ops [TYPE_ANY + 1]; #define op_unit_num(vi) item_ops[(vi)->vi_index]->unit_num (vi) #define op_print_vi(vi) item_ops[(vi)->vi_index]->print_vi (vi) - - #define COMP_SHORT_KEYS comp_short_keys /* number of blocks pointed to by the indirect item */ @@ -1545,8 +1493,7 @@ extern struct item_operations * item_ops [TYPE_ANY + 1]; /* number of bytes contained by the direct item or the unformatted nodes the indirect item points to */ - -/* get the item header */ +/* get the item header */ #define B_N_PITEM_HEAD(bh,item_num) ( (struct item_head * )((bh)->b_data + BLKH_SIZE) + (item_num) ) /* get key */ @@ -1577,9 +1524,9 @@ extern struct item_operations * item_ops [TYPE_ANY + 1]; #define PUT_B_I_POS_UNFM_POINTER(bh,ih,pos, val) do {*(((unp_t *)B_I_PITEM(bh,ih)) + (pos)) = cpu_to_le32(val); } while (0) struct reiserfs_iget_args { - __u32 objectid ; - __u32 dirid ; -} ; + __u32 objectid; + __u32 dirid; +}; /***************************************************************************/ /* FUNCTION DECLARATIONS */ @@ -1595,11 +1542,11 @@ struct reiserfs_iget_args { /* first block written in a commit. */ struct reiserfs_journal_desc { - __le32 j_trans_id ; /* id of commit */ - __le32 j_len ; /* length of commit. len +1 is the commit block */ - __le32 j_mount_id ; /* mount id of this trans*/ - __le32 j_realblock[1] ; /* real locations for each block */ -} ; + __le32 j_trans_id; /* id of commit */ + __le32 j_len; /* length of commit. len +1 is the commit block */ + __le32 j_mount_id; /* mount id of this trans */ + __le32 j_realblock[1]; /* real locations for each block */ +}; #define get_desc_trans_id(d) le32_to_cpu((d)->j_trans_id) #define get_desc_trans_len(d) le32_to_cpu((d)->j_len) @@ -1611,10 +1558,10 @@ struct reiserfs_journal_desc { /* last block written in a commit */ struct reiserfs_journal_commit { - __le32 j_trans_id ; /* must match j_trans_id from the desc block */ - __le32 j_len ; /* ditto */ - __le32 j_realblock[1] ; /* real locations for each block */ -} ; + __le32 j_trans_id; /* must match j_trans_id from the desc block */ + __le32 j_len; /* ditto */ + __le32 j_realblock[1]; /* real locations for each block */ +}; #define get_commit_trans_id(c) le32_to_cpu((c)->j_trans_id) #define get_commit_trans_len(c) le32_to_cpu((c)->j_len) @@ -1628,19 +1575,19 @@ struct reiserfs_journal_commit { ** and this transaction does not need to be replayed. */ struct reiserfs_journal_header { - __le32 j_last_flush_trans_id ; /* id of last fully flushed transaction */ - __le32 j_first_unflushed_offset ; /* offset in the log of where to start replay after a crash */ - __le32 j_mount_id ; - /* 12 */ struct journal_params jh_journal; -} ; + __le32 j_last_flush_trans_id; /* id of last fully flushed transaction */ + __le32 j_first_unflushed_offset; /* offset in the log of where to start replay after a crash */ + __le32 j_mount_id; + /* 12 */ struct journal_params jh_journal; +}; /* biggest tunable defines are right here */ -#define JOURNAL_BLOCK_COUNT 8192 /* number of blocks in the journal */ -#define JOURNAL_TRANS_MAX_DEFAULT 1024 /* biggest possible single transaction, don't change for now (8/3/99) */ +#define JOURNAL_BLOCK_COUNT 8192 /* number of blocks in the journal */ +#define JOURNAL_TRANS_MAX_DEFAULT 1024 /* biggest possible single transaction, don't change for now (8/3/99) */ #define JOURNAL_TRANS_MIN_DEFAULT 256 -#define JOURNAL_MAX_BATCH_DEFAULT 900 /* max blocks to batch into one transaction, don't make this any bigger than 900 */ +#define JOURNAL_MAX_BATCH_DEFAULT 900 /* max blocks to batch into one transaction, don't make this any bigger than 900 */ #define JOURNAL_MIN_RATIO 2 -#define JOURNAL_MAX_COMMIT_AGE 30 +#define JOURNAL_MAX_COMMIT_AGE 30 #define JOURNAL_MAX_TRANS_AGE 30 #define JOURNAL_PER_BALANCE_CNT (3 * (MAX_HEIGHT-2) + 9) #ifdef CONFIG_QUOTA @@ -1664,10 +1611,10 @@ struct reiserfs_journal_header { ** the current number of nodes is > max, the node is freed, otherwise, ** it is put on a free list for faster use later. */ -#define REISERFS_MIN_BITMAP_NODES 10 -#define REISERFS_MAX_BITMAP_NODES 100 +#define REISERFS_MIN_BITMAP_NODES 10 +#define REISERFS_MAX_BITMAP_NODES 100 -#define JBH_HASH_SHIFT 13 /* these are based on journal hash size of 8192 */ +#define JBH_HASH_SHIFT 13 /* these are based on journal hash size of 8192 */ #define JBH_HASH_MASK 8191 #define _jhashfn(sb,block) \ @@ -1681,14 +1628,14 @@ struct reiserfs_journal_header { #define journal_bread(s, block) __bread(SB_JOURNAL(s)->j_dev_bd, block, s->s_blocksize) enum reiserfs_bh_state_bits { - BH_JDirty = BH_PrivateStart, /* buffer is in current transaction */ - BH_JDirty_wait, - BH_JNew, /* disk block was taken off free list before - * being in a finished transaction, or - * written to disk. Can be reused immed. */ - BH_JPrepared, - BH_JRestore_dirty, - BH_JTest, // debugging only will go away + BH_JDirty = BH_PrivateStart, /* buffer is in current transaction */ + BH_JDirty_wait, + BH_JNew, /* disk block was taken off free list before + * being in a finished transaction, or + * written to disk. Can be reused immed. */ + BH_JPrepared, + BH_JRestore_dirty, + BH_JTest, // debugging only will go away }; BUFFER_FNS(JDirty, journaled); @@ -1708,175 +1655,192 @@ TAS_BUFFER_FNS(JTest, journal_test); ** transaction handle which is passed around for all journal calls */ struct reiserfs_transaction_handle { - struct super_block *t_super ; /* super for this FS when journal_begin was - called. saves calls to reiserfs_get_super - also used by nested transactions to make - sure they are nesting on the right FS - _must_ be first in the handle - */ - int t_refcount; - int t_blocks_logged ; /* number of blocks this writer has logged */ - int t_blocks_allocated ; /* number of blocks this writer allocated */ - unsigned long t_trans_id ; /* sanity check, equals the current trans id */ - void *t_handle_save ; /* save existing current->journal_info */ - unsigned displace_new_blocks:1; /* if new block allocation occurres, that block - should be displaced from others */ - struct list_head t_list; -} ; + struct super_block *t_super; /* super for this FS when journal_begin was + called. saves calls to reiserfs_get_super + also used by nested transactions to make + sure they are nesting on the right FS + _must_ be first in the handle + */ + int t_refcount; + int t_blocks_logged; /* number of blocks this writer has logged */ + int t_blocks_allocated; /* number of blocks this writer allocated */ + unsigned long t_trans_id; /* sanity check, equals the current trans id */ + void *t_handle_save; /* save existing current->journal_info */ + unsigned displace_new_blocks:1; /* if new block allocation occurres, that block + should be displaced from others */ + struct list_head t_list; +}; /* used to keep track of ordered and tail writes, attached to the buffer * head through b_journal_head. */ struct reiserfs_jh { - struct reiserfs_journal_list *jl; - struct buffer_head *bh; - struct list_head list; + struct reiserfs_journal_list *jl; + struct buffer_head *bh; + struct list_head list; }; void reiserfs_free_jh(struct buffer_head *bh); int reiserfs_add_tail_list(struct inode *inode, struct buffer_head *bh); int reiserfs_add_ordered_list(struct inode *inode, struct buffer_head *bh); -int journal_mark_dirty(struct reiserfs_transaction_handle *, struct super_block *, struct buffer_head *bh) ; - -static inline int -reiserfs_file_data_log(struct inode *inode) { - if (reiserfs_data_log(inode->i_sb) || - (REISERFS_I(inode)->i_flags & i_data_log)) - return 1 ; - return 0 ; +int journal_mark_dirty(struct reiserfs_transaction_handle *, + struct super_block *, struct buffer_head *bh); + +static inline int reiserfs_file_data_log(struct inode *inode) +{ + if (reiserfs_data_log(inode->i_sb) || + (REISERFS_I(inode)->i_flags & i_data_log)) + return 1; + return 0; } -static inline int reiserfs_transaction_running(struct super_block *s) { - struct reiserfs_transaction_handle *th = current->journal_info ; - if (th && th->t_super == s) - return 1 ; - if (th && th->t_super == NULL) - BUG(); - return 0 ; +static inline int reiserfs_transaction_running(struct super_block *s) +{ + struct reiserfs_transaction_handle *th = current->journal_info; + if (th && th->t_super == s) + return 1; + if (th && th->t_super == NULL) + BUG(); + return 0; } int reiserfs_async_progress_wait(struct super_block *s); -struct reiserfs_transaction_handle * -reiserfs_persistent_transaction(struct super_block *, int count); +struct reiserfs_transaction_handle *reiserfs_persistent_transaction(struct + super_block + *, + int count); int reiserfs_end_persistent_transaction(struct reiserfs_transaction_handle *); int reiserfs_commit_page(struct inode *inode, struct page *page, - unsigned from, unsigned to); + unsigned from, unsigned to); int reiserfs_flush_old_commits(struct super_block *); -int reiserfs_commit_for_inode(struct inode *) ; -int reiserfs_inode_needs_commit(struct inode *) ; -void reiserfs_update_inode_transaction(struct inode *) ; -void reiserfs_wait_on_write_block(struct super_block *s) ; -void reiserfs_block_writes(struct reiserfs_transaction_handle *th) ; -void reiserfs_allow_writes(struct super_block *s) ; -void reiserfs_check_lock_depth(struct super_block *s, char *caller) ; -int reiserfs_prepare_for_journal(struct super_block *, struct buffer_head *bh, int wait) ; -void reiserfs_restore_prepared_buffer(struct super_block *, struct buffer_head *bh) ; -int journal_init(struct super_block *, const char * j_dev_name, int old_format, unsigned int) ; -int journal_release(struct reiserfs_transaction_handle*, struct super_block *) ; -int journal_release_error(struct reiserfs_transaction_handle*, struct super_block *) ; -int journal_end(struct reiserfs_transaction_handle *, struct super_block *, unsigned long) ; -int journal_end_sync(struct reiserfs_transaction_handle *, struct super_block *, unsigned long) ; -int journal_mark_freed(struct reiserfs_transaction_handle *, struct super_block *, b_blocknr_t blocknr) ; -int journal_transaction_should_end(struct reiserfs_transaction_handle *, int) ; -int reiserfs_in_journal(struct super_block *p_s_sb, int bmap_nr, int bit_nr, int searchall, b_blocknr_t *next) ; -int journal_begin(struct reiserfs_transaction_handle *, struct super_block *p_s_sb, unsigned long) ; -int journal_join_abort(struct reiserfs_transaction_handle *, struct super_block *p_s_sb, unsigned long) ; -void reiserfs_journal_abort (struct super_block *sb, int errno); -void reiserfs_abort (struct super_block *sb, int errno, const char *fmt, ...); -int reiserfs_allocate_list_bitmaps(struct super_block *s, struct reiserfs_list_bitmap *, int) ; - -void add_save_link (struct reiserfs_transaction_handle * th, - struct inode * inode, int truncate); -int remove_save_link (struct inode * inode, int truncate); +int reiserfs_commit_for_inode(struct inode *); +int reiserfs_inode_needs_commit(struct inode *); +void reiserfs_update_inode_transaction(struct inode *); +void reiserfs_wait_on_write_block(struct super_block *s); +void reiserfs_block_writes(struct reiserfs_transaction_handle *th); +void reiserfs_allow_writes(struct super_block *s); +void reiserfs_check_lock_depth(struct super_block *s, char *caller); +int reiserfs_prepare_for_journal(struct super_block *, struct buffer_head *bh, + int wait); +void reiserfs_restore_prepared_buffer(struct super_block *, + struct buffer_head *bh); +int journal_init(struct super_block *, const char *j_dev_name, int old_format, + unsigned int); +int journal_release(struct reiserfs_transaction_handle *, struct super_block *); +int journal_release_error(struct reiserfs_transaction_handle *, + struct super_block *); +int journal_end(struct reiserfs_transaction_handle *, struct super_block *, + unsigned long); +int journal_end_sync(struct reiserfs_transaction_handle *, struct super_block *, + unsigned long); +int journal_mark_freed(struct reiserfs_transaction_handle *, + struct super_block *, b_blocknr_t blocknr); +int journal_transaction_should_end(struct reiserfs_transaction_handle *, int); +int reiserfs_in_journal(struct super_block *p_s_sb, int bmap_nr, int bit_nr, + int searchall, b_blocknr_t * next); +int journal_begin(struct reiserfs_transaction_handle *, + struct super_block *p_s_sb, unsigned long); +int journal_join_abort(struct reiserfs_transaction_handle *, + struct super_block *p_s_sb, unsigned long); +void reiserfs_journal_abort(struct super_block *sb, int errno); +void reiserfs_abort(struct super_block *sb, int errno, const char *fmt, ...); +int reiserfs_allocate_list_bitmaps(struct super_block *s, + struct reiserfs_list_bitmap *, int); + +void add_save_link(struct reiserfs_transaction_handle *th, + struct inode *inode, int truncate); +int remove_save_link(struct inode *inode, int truncate); /* objectid.c */ -__u32 reiserfs_get_unused_objectid (struct reiserfs_transaction_handle *th); -void reiserfs_release_objectid (struct reiserfs_transaction_handle *th, __u32 objectid_to_release); -int reiserfs_convert_objectid_map_v1(struct super_block *) ; +__u32 reiserfs_get_unused_objectid(struct reiserfs_transaction_handle *th); +void reiserfs_release_objectid(struct reiserfs_transaction_handle *th, + __u32 objectid_to_release); +int reiserfs_convert_objectid_map_v1(struct super_block *); /* stree.c */ int B_IS_IN_TREE(const struct buffer_head *); -extern void copy_item_head(struct item_head * p_v_to, - const struct item_head * p_v_from); +extern void copy_item_head(struct item_head *p_v_to, + const struct item_head *p_v_from); // first key is in cpu form, second - le -extern int comp_short_keys (const struct reiserfs_key * le_key, - const struct cpu_key * cpu_key); -extern void le_key2cpu_key (struct cpu_key * to, const struct reiserfs_key * from); +extern int comp_short_keys(const struct reiserfs_key *le_key, + const struct cpu_key *cpu_key); +extern void le_key2cpu_key(struct cpu_key *to, const struct reiserfs_key *from); // both are in le form -extern int comp_le_keys (const struct reiserfs_key *, const struct reiserfs_key *); -extern int comp_short_le_keys (const struct reiserfs_key *, const struct reiserfs_key *); +extern int comp_le_keys(const struct reiserfs_key *, + const struct reiserfs_key *); +extern int comp_short_le_keys(const struct reiserfs_key *, + const struct reiserfs_key *); // // get key version from on disk key - kludge // -static inline int le_key_version (const struct reiserfs_key * key) +static inline int le_key_version(const struct reiserfs_key *key) { - int type; - - type = offset_v2_k_type( &(key->u.k_offset_v2)); - if (type != TYPE_DIRECT && type != TYPE_INDIRECT && type != TYPE_DIRENTRY) - return KEY_FORMAT_3_5; - - return KEY_FORMAT_3_6; - -} + int type; + type = offset_v2_k_type(&(key->u.k_offset_v2)); + if (type != TYPE_DIRECT && type != TYPE_INDIRECT + && type != TYPE_DIRENTRY) + return KEY_FORMAT_3_5; + + return KEY_FORMAT_3_6; -static inline void copy_key (struct reiserfs_key *to, const struct reiserfs_key *from) -{ - memcpy (to, from, KEY_SIZE); } +static inline void copy_key(struct reiserfs_key *to, + const struct reiserfs_key *from) +{ + memcpy(to, from, KEY_SIZE); +} -int comp_items (const struct item_head * stored_ih, const struct path * p_s_path); -const struct reiserfs_key * get_rkey (const struct path * p_s_chk_path, - const struct super_block * p_s_sb); -int search_by_key (struct super_block *, const struct cpu_key *, - struct path *, int); +int comp_items(const struct item_head *stored_ih, const struct path *p_s_path); +const struct reiserfs_key *get_rkey(const struct path *p_s_chk_path, + const struct super_block *p_s_sb); +int search_by_key(struct super_block *, const struct cpu_key *, + struct path *, int); #define search_item(s,key,path) search_by_key (s, key, path, DISK_LEAF_NODE_LEVEL) -int search_for_position_by_key (struct super_block * p_s_sb, - const struct cpu_key * p_s_cpu_key, - struct path * p_s_search_path); -extern void decrement_bcount (struct buffer_head * p_s_bh); -void decrement_counters_in_path (struct path * p_s_search_path); -void pathrelse (struct path * p_s_search_path); -int reiserfs_check_path(struct path *p) ; -void pathrelse_and_restore (struct super_block *s, struct path * p_s_search_path); - -int reiserfs_insert_item (struct reiserfs_transaction_handle *th, - struct path * path, - const struct cpu_key * key, - struct item_head * ih, - struct inode *inode, const char * body); - -int reiserfs_paste_into_item (struct reiserfs_transaction_handle *th, - struct path * path, - const struct cpu_key * key, - struct inode *inode, - const char * body, int paste_size); - -int reiserfs_cut_from_item (struct reiserfs_transaction_handle *th, - struct path * path, - struct cpu_key * key, - struct inode * inode, - struct page *page, - loff_t new_file_size); - -int reiserfs_delete_item (struct reiserfs_transaction_handle *th, - struct path * path, - const struct cpu_key * key, - struct inode * inode, - struct buffer_head * p_s_un_bh); - -void reiserfs_delete_solid_item (struct reiserfs_transaction_handle *th, - struct inode *inode, struct reiserfs_key * key); -int reiserfs_delete_object (struct reiserfs_transaction_handle *th, struct inode * p_s_inode); -int reiserfs_do_truncate (struct reiserfs_transaction_handle *th, - struct inode * p_s_inode, struct page *, - int update_timestamps); +int search_for_position_by_key(struct super_block *p_s_sb, + const struct cpu_key *p_s_cpu_key, + struct path *p_s_search_path); +extern void decrement_bcount(struct buffer_head *p_s_bh); +void decrement_counters_in_path(struct path *p_s_search_path); +void pathrelse(struct path *p_s_search_path); +int reiserfs_check_path(struct path *p); +void pathrelse_and_restore(struct super_block *s, struct path *p_s_search_path); + +int reiserfs_insert_item(struct reiserfs_transaction_handle *th, + struct path *path, + const struct cpu_key *key, + struct item_head *ih, + struct inode *inode, const char *body); + +int reiserfs_paste_into_item(struct reiserfs_transaction_handle *th, + struct path *path, + const struct cpu_key *key, + struct inode *inode, + const char *body, int paste_size); + +int reiserfs_cut_from_item(struct reiserfs_transaction_handle *th, + struct path *path, + struct cpu_key *key, + struct inode *inode, + struct page *page, loff_t new_file_size); + +int reiserfs_delete_item(struct reiserfs_transaction_handle *th, + struct path *path, + const struct cpu_key *key, + struct inode *inode, struct buffer_head *p_s_un_bh); + +void reiserfs_delete_solid_item(struct reiserfs_transaction_handle *th, + struct inode *inode, struct reiserfs_key *key); +int reiserfs_delete_object(struct reiserfs_transaction_handle *th, + struct inode *p_s_inode); +int reiserfs_do_truncate(struct reiserfs_transaction_handle *th, + struct inode *p_s_inode, struct page *, + int update_timestamps); #define i_block_size(inode) ((inode)->i_sb->s_blocksize) #define file_size(inode) ((inode)->i_size) @@ -1885,66 +1849,67 @@ int reiserfs_do_truncate (struct reiserfs_transaction_handle *th, #define tail_has_to_be_packed(inode) (have_large_tails ((inode)->i_sb)?\ !STORE_TAIL_IN_UNFM_S1(file_size (inode), tail_size(inode), inode->i_sb->s_blocksize):have_small_tails ((inode)->i_sb)?!STORE_TAIL_IN_UNFM_S2(file_size (inode), tail_size(inode), inode->i_sb->s_blocksize):0 ) -void padd_item (char * item, int total_length, int length); +void padd_item(char *item, int total_length, int length); /* inode.c */ /* args for the create parameter of reiserfs_get_block */ -#define GET_BLOCK_NO_CREATE 0 /* don't create new blocks or convert tails */ -#define GET_BLOCK_CREATE 1 /* add anything you need to find block */ -#define GET_BLOCK_NO_HOLE 2 /* return -ENOENT for file holes */ -#define GET_BLOCK_READ_DIRECT 4 /* read the tail if indirect item not found */ -#define GET_BLOCK_NO_ISEM 8 /* i_sem is not held, don't preallocate */ -#define GET_BLOCK_NO_DANGLE 16 /* don't leave any transactions running */ - -int restart_transaction(struct reiserfs_transaction_handle *th, struct inode *inode, struct path *path); -void reiserfs_read_locked_inode(struct inode * inode, struct reiserfs_iget_args *args) ; -int reiserfs_find_actor(struct inode * inode, void *p) ; -int reiserfs_init_locked_inode(struct inode * inode, void *p) ; -void reiserfs_delete_inode (struct inode * inode); -int reiserfs_write_inode (struct inode * inode, int) ; -int reiserfs_get_block (struct inode * inode, sector_t block, struct buffer_head * bh_result, int create); -struct dentry *reiserfs_get_dentry(struct super_block *, void *) ; -struct dentry *reiserfs_decode_fh(struct super_block *sb, __u32 *data, - int len, int fhtype, - int (*acceptable)(void *contect, struct dentry *de), - void *context) ; -int reiserfs_encode_fh( struct dentry *dentry, __u32 *data, int *lenp, - int connectable ); - -int reiserfs_truncate_file(struct inode *, int update_timestamps) ; -void make_cpu_key (struct cpu_key * cpu_key, struct inode * inode, loff_t offset, - int type, int key_length); -void make_le_item_head (struct item_head * ih, const struct cpu_key * key, - int version, - loff_t offset, int type, int length, int entry_count); -struct inode * reiserfs_iget (struct super_block * s, - const struct cpu_key * key); - - -int reiserfs_new_inode (struct reiserfs_transaction_handle *th, - struct inode * dir, int mode, - const char * symname, loff_t i_size, - struct dentry *dentry, struct inode *inode); - -void reiserfs_update_sd_size (struct reiserfs_transaction_handle *th, - struct inode * inode, loff_t size); +#define GET_BLOCK_NO_CREATE 0 /* don't create new blocks or convert tails */ +#define GET_BLOCK_CREATE 1 /* add anything you need to find block */ +#define GET_BLOCK_NO_HOLE 2 /* return -ENOENT for file holes */ +#define GET_BLOCK_READ_DIRECT 4 /* read the tail if indirect item not found */ +#define GET_BLOCK_NO_ISEM 8 /* i_sem is not held, don't preallocate */ +#define GET_BLOCK_NO_DANGLE 16 /* don't leave any transactions running */ + +int restart_transaction(struct reiserfs_transaction_handle *th, + struct inode *inode, struct path *path); +void reiserfs_read_locked_inode(struct inode *inode, + struct reiserfs_iget_args *args); +int reiserfs_find_actor(struct inode *inode, void *p); +int reiserfs_init_locked_inode(struct inode *inode, void *p); +void reiserfs_delete_inode(struct inode *inode); +int reiserfs_write_inode(struct inode *inode, int); +int reiserfs_get_block(struct inode *inode, sector_t block, + struct buffer_head *bh_result, int create); +struct dentry *reiserfs_get_dentry(struct super_block *, void *); +struct dentry *reiserfs_decode_fh(struct super_block *sb, __u32 * data, + int len, int fhtype, + int (*acceptable) (void *contect, + struct dentry * de), + void *context); +int reiserfs_encode_fh(struct dentry *dentry, __u32 * data, int *lenp, + int connectable); + +int reiserfs_truncate_file(struct inode *, int update_timestamps); +void make_cpu_key(struct cpu_key *cpu_key, struct inode *inode, loff_t offset, + int type, int key_length); +void make_le_item_head(struct item_head *ih, const struct cpu_key *key, + int version, + loff_t offset, int type, int length, int entry_count); +struct inode *reiserfs_iget(struct super_block *s, const struct cpu_key *key); + +int reiserfs_new_inode(struct reiserfs_transaction_handle *th, + struct inode *dir, int mode, + const char *symname, loff_t i_size, + struct dentry *dentry, struct inode *inode); + +void reiserfs_update_sd_size(struct reiserfs_transaction_handle *th, + struct inode *inode, loff_t size); static inline void reiserfs_update_sd(struct reiserfs_transaction_handle *th, - struct inode *inode) + struct inode *inode) { - reiserfs_update_sd_size(th, inode, inode->i_size) ; + reiserfs_update_sd_size(th, inode, inode->i_size); } -void sd_attrs_to_i_attrs( __u16 sd_attrs, struct inode *inode ); -void i_attrs_to_sd_attrs( struct inode *inode, __u16 *sd_attrs ); +void sd_attrs_to_i_attrs(__u16 sd_attrs, struct inode *inode); +void i_attrs_to_sd_attrs(struct inode *inode, __u16 * sd_attrs); int reiserfs_setattr(struct dentry *dentry, struct iattr *attr); /* namei.c */ -void set_de_name_and_namelen (struct reiserfs_dir_entry * de); -int search_by_entry_key (struct super_block * sb, const struct cpu_key * key, - struct path * path, - struct reiserfs_dir_entry * de); -struct dentry *reiserfs_get_parent(struct dentry *) ; +void set_de_name_and_namelen(struct reiserfs_dir_entry *de); +int search_by_entry_key(struct super_block *sb, const struct cpu_key *key, + struct path *path, struct reiserfs_dir_entry *de); +struct dentry *reiserfs_get_parent(struct dentry *); /* procfs.c */ #if defined( CONFIG_PROC_FS ) && defined( CONFIG_REISERFS_PROC_INFO ) @@ -1953,15 +1918,15 @@ struct dentry *reiserfs_get_parent(struct dentry *) ; #undef REISERFS_PROC_INFO #endif -int reiserfs_proc_info_init( struct super_block *sb ); -int reiserfs_proc_info_done( struct super_block *sb ); -struct proc_dir_entry *reiserfs_proc_register_global( char *name, - read_proc_t *func ); -void reiserfs_proc_unregister_global( const char *name ); -int reiserfs_proc_info_global_init( void ); -int reiserfs_proc_info_global_done( void ); -int reiserfs_global_version_in_proc( char *buffer, char **start, off_t offset, - int count, int *eof, void *data ); +int reiserfs_proc_info_init(struct super_block *sb); +int reiserfs_proc_info_done(struct super_block *sb); +struct proc_dir_entry *reiserfs_proc_register_global(char *name, + read_proc_t * func); +void reiserfs_proc_unregister_global(const char *name); +int reiserfs_proc_info_global_init(void); +int reiserfs_proc_info_global_done(void); +int reiserfs_global_version_in_proc(char *buffer, char **start, off_t offset, + int count, int *eof, void *data); #if defined( REISERFS_PROC_INFO ) @@ -1993,123 +1958,132 @@ extern struct inode_operations reiserfs_special_inode_operations; extern struct file_operations reiserfs_dir_operations; /* tail_conversion.c */ -int direct2indirect (struct reiserfs_transaction_handle *, struct inode *, struct path *, struct buffer_head *, loff_t); -int indirect2direct (struct reiserfs_transaction_handle *, struct inode *, struct page *, struct path *, const struct cpu_key *, loff_t, char *); -void reiserfs_unmap_buffer(struct buffer_head *) ; - +int direct2indirect(struct reiserfs_transaction_handle *, struct inode *, + struct path *, struct buffer_head *, loff_t); +int indirect2direct(struct reiserfs_transaction_handle *, struct inode *, + struct page *, struct path *, const struct cpu_key *, + loff_t, char *); +void reiserfs_unmap_buffer(struct buffer_head *); /* file.c */ extern struct inode_operations reiserfs_file_inode_operations; extern struct file_operations reiserfs_file_operations; -extern struct address_space_operations reiserfs_address_space_operations ; +extern struct address_space_operations reiserfs_address_space_operations; /* fix_nodes.c */ #ifdef CONFIG_REISERFS_CHECK -void * reiserfs_kmalloc (size_t size, int flags, struct super_block * s); -void reiserfs_kfree (const void * vp, size_t size, struct super_block * s); +void *reiserfs_kmalloc(size_t size, int flags, struct super_block *s); +void reiserfs_kfree(const void *vp, size_t size, struct super_block *s); #else static inline void *reiserfs_kmalloc(size_t size, int flags, - struct super_block *s) + struct super_block *s) { return kmalloc(size, flags); } static inline void reiserfs_kfree(const void *vp, size_t size, - struct super_block *s) + struct super_block *s) { kfree(vp); } #endif -int fix_nodes (int n_op_mode, struct tree_balance * p_s_tb, - struct item_head * p_s_ins_ih, const void *); -void unfix_nodes (struct tree_balance *); - +int fix_nodes(int n_op_mode, struct tree_balance *p_s_tb, + struct item_head *p_s_ins_ih, const void *); +void unfix_nodes(struct tree_balance *); /* prints.c */ -void reiserfs_panic (struct super_block * s, const char * fmt, ...) __attribute__ ( ( noreturn ) ); -void reiserfs_info (struct super_block *s, const char * fmt, ...); -void reiserfs_debug (struct super_block *s, int level, const char * fmt, ...); -void print_indirect_item (struct buffer_head * bh, int item_num); -void store_print_tb (struct tree_balance * tb); -void print_cur_tb (char * mes); -void print_de (struct reiserfs_dir_entry * de); -void print_bi (struct buffer_info * bi, char * mes); -#define PRINT_LEAF_ITEMS 1 /* print all items */ -#define PRINT_DIRECTORY_ITEMS 2 /* print directory items */ -#define PRINT_DIRECT_ITEMS 4 /* print contents of direct items */ -void print_block (struct buffer_head * bh, ...); -void print_bmap (struct super_block * s, int silent); -void print_bmap_block (int i, char * data, int size, int silent); +void reiserfs_panic(struct super_block *s, const char *fmt, ...) + __attribute__ ((noreturn)); +void reiserfs_info(struct super_block *s, const char *fmt, ...); +void reiserfs_debug(struct super_block *s, int level, const char *fmt, ...); +void print_indirect_item(struct buffer_head *bh, int item_num); +void store_print_tb(struct tree_balance *tb); +void print_cur_tb(char *mes); +void print_de(struct reiserfs_dir_entry *de); +void print_bi(struct buffer_info *bi, char *mes); +#define PRINT_LEAF_ITEMS 1 /* print all items */ +#define PRINT_DIRECTORY_ITEMS 2 /* print directory items */ +#define PRINT_DIRECT_ITEMS 4 /* print contents of direct items */ +void print_block(struct buffer_head *bh, ...); +void print_bmap(struct super_block *s, int silent); +void print_bmap_block(int i, char *data, int size, int silent); /*void print_super_block (struct super_block * s, char * mes);*/ -void print_objectid_map (struct super_block * s); -void print_block_head (struct buffer_head * bh, char * mes); -void check_leaf (struct buffer_head * bh); -void check_internal (struct buffer_head * bh); -void print_statistics (struct super_block * s); -char * reiserfs_hashname(int code); +void print_objectid_map(struct super_block *s); +void print_block_head(struct buffer_head *bh, char *mes); +void check_leaf(struct buffer_head *bh); +void check_internal(struct buffer_head *bh); +void print_statistics(struct super_block *s); +char *reiserfs_hashname(int code); /* lbalance.c */ -int leaf_move_items (int shift_mode, struct tree_balance * tb, int mov_num, int mov_bytes, struct buffer_head * Snew); -int leaf_shift_left (struct tree_balance * tb, int shift_num, int shift_bytes); -int leaf_shift_right (struct tree_balance * tb, int shift_num, int shift_bytes); -void leaf_delete_items (struct buffer_info * cur_bi, int last_first, int first, int del_num, int del_bytes); -void leaf_insert_into_buf (struct buffer_info * bi, int before, - struct item_head * inserted_item_ih, const char * inserted_item_body, int zeros_number); -void leaf_paste_in_buffer (struct buffer_info * bi, int pasted_item_num, - int pos_in_item, int paste_size, const char * body, int zeros_number); -void leaf_cut_from_buffer (struct buffer_info * bi, int cut_item_num, int pos_in_item, - int cut_size); -void leaf_paste_entries (struct buffer_head * bh, int item_num, int before, - int new_entry_count, struct reiserfs_de_head * new_dehs, const char * records, int paste_size); +int leaf_move_items(int shift_mode, struct tree_balance *tb, int mov_num, + int mov_bytes, struct buffer_head *Snew); +int leaf_shift_left(struct tree_balance *tb, int shift_num, int shift_bytes); +int leaf_shift_right(struct tree_balance *tb, int shift_num, int shift_bytes); +void leaf_delete_items(struct buffer_info *cur_bi, int last_first, int first, + int del_num, int del_bytes); +void leaf_insert_into_buf(struct buffer_info *bi, int before, + struct item_head *inserted_item_ih, + const char *inserted_item_body, int zeros_number); +void leaf_paste_in_buffer(struct buffer_info *bi, int pasted_item_num, + int pos_in_item, int paste_size, const char *body, + int zeros_number); +void leaf_cut_from_buffer(struct buffer_info *bi, int cut_item_num, + int pos_in_item, int cut_size); +void leaf_paste_entries(struct buffer_head *bh, int item_num, int before, + int new_entry_count, struct reiserfs_de_head *new_dehs, + const char *records, int paste_size); /* ibalance.c */ -int balance_internal (struct tree_balance * , int, int, struct item_head * , - struct buffer_head **); +int balance_internal(struct tree_balance *, int, int, struct item_head *, + struct buffer_head **); /* do_balance.c */ -void do_balance_mark_leaf_dirty (struct tree_balance * tb, - struct buffer_head * bh, int flag); +void do_balance_mark_leaf_dirty(struct tree_balance *tb, + struct buffer_head *bh, int flag); #define do_balance_mark_internal_dirty do_balance_mark_leaf_dirty #define do_balance_mark_sb_dirty do_balance_mark_leaf_dirty -void do_balance (struct tree_balance * tb, struct item_head * ih, - const char * body, int flag); -void reiserfs_invalidate_buffer (struct tree_balance * tb, struct buffer_head * bh); +void do_balance(struct tree_balance *tb, struct item_head *ih, + const char *body, int flag); +void reiserfs_invalidate_buffer(struct tree_balance *tb, + struct buffer_head *bh); -int get_left_neighbor_position (struct tree_balance * tb, int h); -int get_right_neighbor_position (struct tree_balance * tb, int h); -void replace_key (struct tree_balance * tb, struct buffer_head *, int, struct buffer_head *, int); -void make_empty_node (struct buffer_info *); -struct buffer_head * get_FEB (struct tree_balance *); +int get_left_neighbor_position(struct tree_balance *tb, int h); +int get_right_neighbor_position(struct tree_balance *tb, int h); +void replace_key(struct tree_balance *tb, struct buffer_head *, int, + struct buffer_head *, int); +void make_empty_node(struct buffer_info *); +struct buffer_head *get_FEB(struct tree_balance *); /* bitmap.c */ /* structure contains hints for block allocator, and it is a container for * arguments, such as node, search path, transaction_handle, etc. */ - struct __reiserfs_blocknr_hint { - struct inode * inode; /* inode passed to allocator, if we allocate unf. nodes */ - long block; /* file offset, in blocks */ - struct in_core_key key; - struct path * path; /* search path, used by allocator to deternine search_start by - * various ways */ - struct reiserfs_transaction_handle * th; /* transaction handle is needed to log super blocks and - * bitmap blocks changes */ - b_blocknr_t beg, end; - b_blocknr_t search_start; /* a field used to transfer search start value (block number) +struct __reiserfs_blocknr_hint { + struct inode *inode; /* inode passed to allocator, if we allocate unf. nodes */ + long block; /* file offset, in blocks */ + struct in_core_key key; + struct path *path; /* search path, used by allocator to deternine search_start by + * various ways */ + struct reiserfs_transaction_handle *th; /* transaction handle is needed to log super blocks and + * bitmap blocks changes */ + b_blocknr_t beg, end; + b_blocknr_t search_start; /* a field used to transfer search start value (block number) * between different block allocator procedures * (determine_search_start() and others) */ - int prealloc_size; /* is set in determine_prealloc_size() function, used by underlayed - * function that do actual allocation */ + int prealloc_size; /* is set in determine_prealloc_size() function, used by underlayed + * function that do actual allocation */ - unsigned formatted_node:1; /* the allocator uses different polices for getting disk space for + unsigned formatted_node:1; /* the allocator uses different polices for getting disk space for * formatted/unformatted blocks with/without preallocation */ - unsigned preallocate:1; + unsigned preallocate:1; }; typedef struct __reiserfs_blocknr_hint reiserfs_blocknr_hint_t; -int reiserfs_parse_alloc_options (struct super_block *, char *); -void reiserfs_init_alloc_options (struct super_block *s); +int reiserfs_parse_alloc_options(struct super_block *, char *); +void reiserfs_init_alloc_options(struct super_block *s); /* * given a directory, this will tell you what packing locality @@ -2118,68 +2092,72 @@ void reiserfs_init_alloc_options (struct super_block *s); */ __le32 reiserfs_choose_packing(struct inode *dir); -int is_reusable (struct super_block * s, b_blocknr_t block, int bit_value); -void reiserfs_free_block (struct reiserfs_transaction_handle *th, struct inode *, b_blocknr_t, int for_unformatted); -int reiserfs_allocate_blocknrs(reiserfs_blocknr_hint_t *, b_blocknr_t * , int, int); -extern inline int reiserfs_new_form_blocknrs (struct tree_balance * tb, - b_blocknr_t *new_blocknrs, int amount_needed) +int is_reusable(struct super_block *s, b_blocknr_t block, int bit_value); +void reiserfs_free_block(struct reiserfs_transaction_handle *th, struct inode *, + b_blocknr_t, int for_unformatted); +int reiserfs_allocate_blocknrs(reiserfs_blocknr_hint_t *, b_blocknr_t *, int, + int); +extern inline int reiserfs_new_form_blocknrs(struct tree_balance *tb, + b_blocknr_t * new_blocknrs, + int amount_needed) { - reiserfs_blocknr_hint_t hint = { - .th = tb->transaction_handle, - .path = tb->tb_path, - .inode = NULL, - .key = tb->key, - .block = 0, - .formatted_node = 1 - }; - return reiserfs_allocate_blocknrs(&hint, new_blocknrs, amount_needed, 0); + reiserfs_blocknr_hint_t hint = { + .th = tb->transaction_handle, + .path = tb->tb_path, + .inode = NULL, + .key = tb->key, + .block = 0, + .formatted_node = 1 + }; + return reiserfs_allocate_blocknrs(&hint, new_blocknrs, amount_needed, + 0); } -extern inline int reiserfs_new_unf_blocknrs (struct reiserfs_transaction_handle *th, - struct inode *inode, - b_blocknr_t *new_blocknrs, - struct path * path, long block) +extern inline int reiserfs_new_unf_blocknrs(struct reiserfs_transaction_handle + *th, struct inode *inode, + b_blocknr_t * new_blocknrs, + struct path *path, long block) { - reiserfs_blocknr_hint_t hint = { - .th = th, - .path = path, - .inode = inode, - .block = block, - .formatted_node = 0, - .preallocate = 0 - }; - return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0); + reiserfs_blocknr_hint_t hint = { + .th = th, + .path = path, + .inode = inode, + .block = block, + .formatted_node = 0, + .preallocate = 0 + }; + return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0); } #ifdef REISERFS_PREALLOCATE -extern inline int reiserfs_new_unf_blocknrs2(struct reiserfs_transaction_handle *th, - struct inode * inode, - b_blocknr_t *new_blocknrs, - struct path * path, long block) +extern inline int reiserfs_new_unf_blocknrs2(struct reiserfs_transaction_handle + *th, struct inode *inode, + b_blocknr_t * new_blocknrs, + struct path *path, long block) { - reiserfs_blocknr_hint_t hint = { - .th = th, - .path = path, - .inode = inode, - .block = block, - .formatted_node = 0, - .preallocate = 1 - }; - return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0); + reiserfs_blocknr_hint_t hint = { + .th = th, + .path = path, + .inode = inode, + .block = block, + .formatted_node = 0, + .preallocate = 1 + }; + return reiserfs_allocate_blocknrs(&hint, new_blocknrs, 1, 0); } -void reiserfs_discard_prealloc (struct reiserfs_transaction_handle *th, - struct inode * inode); -void reiserfs_discard_all_prealloc (struct reiserfs_transaction_handle *th); +void reiserfs_discard_prealloc(struct reiserfs_transaction_handle *th, + struct inode *inode); +void reiserfs_discard_all_prealloc(struct reiserfs_transaction_handle *th); #endif -void reiserfs_claim_blocks_to_be_allocated( struct super_block *sb, int blocks); -void reiserfs_release_claimed_blocks( struct super_block *sb, int blocks); +void reiserfs_claim_blocks_to_be_allocated(struct super_block *sb, int blocks); +void reiserfs_release_claimed_blocks(struct super_block *sb, int blocks); int reiserfs_can_fit_pages(struct super_block *sb); /* hashes.c */ -__u32 keyed_hash (const signed char *msg, int len); -__u32 yura_hash (const signed char *msg, int len); -__u32 r5_hash (const signed char *msg, int len); +__u32 keyed_hash(const signed char *msg, int len); +__u32 yura_hash(const signed char *msg, int len); +__u32 r5_hash(const signed char *msg, int len); /* the ext2 bit routines adjust for big or little endian as ** appropriate for the arch, so in our laziness we use them rather @@ -2199,11 +2177,10 @@ __u32 r5_hash (const signed char *msg, int len); absolutely safe */ #define SPARE_SPACE 500 - /* prototypes from ioctl.c */ -int reiserfs_ioctl (struct inode * inode, struct file * filp, - unsigned int cmd, unsigned long arg); - +int reiserfs_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + /* ioctl's command */ #define REISERFS_IOC_UNPACK _IOW(0xCD,1,long) /* define following flags to be the same as in ext2, so that chattr(1), @@ -2218,10 +2195,8 @@ int reiserfs_ioctl (struct inode * inode, struct file * filp, would evolve into real per-fs locks */ #define reiserfs_write_lock( sb ) lock_kernel() #define reiserfs_write_unlock( sb ) unlock_kernel() - + /* xattr stuff */ #define REISERFS_XATTR_DIR_SEM(s) (REISERFS_SB(s)->xattr_dir_sem) -#endif /* _LINUX_REISER_FS_H */ - - +#endif /* _LINUX_REISER_FS_H */ diff --git a/include/linux/reiserfs_fs_i.h b/include/linux/reiserfs_fs_i.h index e321eb050d65..149be8d9a0c9 100644 --- a/include/linux/reiserfs_fs_i.h +++ b/include/linux/reiserfs_fs_i.h @@ -10,54 +10,53 @@ typedef enum { /** this says what format of key do all items (but stat data) of an object have. If this is set, that format is 3.6 otherwise - 3.5 */ - i_item_key_version_mask = 0x0001, + i_item_key_version_mask = 0x0001, /** If this is unset, object has 3.5 stat data, otherwise, it has 3.6 stat data with 64bit size, 32bit nlink etc. */ - i_stat_data_version_mask = 0x0002, + i_stat_data_version_mask = 0x0002, /** file might need tail packing on close */ - i_pack_on_close_mask = 0x0004, + i_pack_on_close_mask = 0x0004, /** don't pack tail of file */ - i_nopack_mask = 0x0008, + i_nopack_mask = 0x0008, /** If those is set, "safe link" was created for this file during truncate or unlink. Safe link is used to avoid leakage of disk space on crash with some files open, but unlinked. */ - i_link_saved_unlink_mask = 0x0010, - i_link_saved_truncate_mask = 0x0020, - i_has_xattr_dir = 0x0040, - i_data_log = 0x0080, + i_link_saved_unlink_mask = 0x0010, + i_link_saved_truncate_mask = 0x0020, + i_has_xattr_dir = 0x0040, + i_data_log = 0x0080, } reiserfs_inode_flags; - struct reiserfs_inode_info { - __u32 i_key [4];/* key is still 4 32 bit integers */ + __u32 i_key[4]; /* key is still 4 32 bit integers */ /** transient inode flags that are never stored on disk. Bitmasks for this field are defined above. */ - __u32 i_flags; + __u32 i_flags; - __u32 i_first_direct_byte; // offset of first byte stored in direct item. + __u32 i_first_direct_byte; // offset of first byte stored in direct item. - /* copy of persistent inode flags read from sd_attrs. */ - __u32 i_attrs; + /* copy of persistent inode flags read from sd_attrs. */ + __u32 i_attrs; - int i_prealloc_block; /* first unused block of a sequence of unused blocks */ - int i_prealloc_count; /* length of that sequence */ - struct list_head i_prealloc_list; /* per-transaction list of inodes which - * have preallocated blocks */ + int i_prealloc_block; /* first unused block of a sequence of unused blocks */ + int i_prealloc_count; /* length of that sequence */ + struct list_head i_prealloc_list; /* per-transaction list of inodes which + * have preallocated blocks */ - unsigned new_packing_locality:1; /* new_packig_locality is created; new blocks - * for the contents of this directory should be - * displaced */ + unsigned new_packing_locality:1; /* new_packig_locality is created; new blocks + * for the contents of this directory should be + * displaced */ - /* we use these for fsync or O_SYNC to decide which transaction - ** needs to be committed in order for this inode to be properly - ** flushed */ - unsigned long i_trans_id ; - struct reiserfs_journal_list *i_jl; + /* we use these for fsync or O_SYNC to decide which transaction + ** needs to be committed in order for this inode to be properly + ** flushed */ + unsigned long i_trans_id; + struct reiserfs_journal_list *i_jl; - struct posix_acl *i_acl_access; - struct posix_acl *i_acl_default; - struct rw_semaphore xattr_sem; - struct inode vfs_inode; + struct posix_acl *i_acl_access; + struct posix_acl *i_acl_default; + struct rw_semaphore xattr_sem; + struct inode vfs_inode; }; #endif diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h index 31c709d0fe18..3e68592e52e9 100644 --- a/include/linux/reiserfs_fs_sb.h +++ b/include/linux/reiserfs_fs_sb.h @@ -10,7 +10,7 @@ #endif typedef enum { - reiserfs_attrs_cleared = 0x00000001, + reiserfs_attrs_cleared = 0x00000001, } reiserfs_super_block_flags; /* struct reiserfs_super_block accessors/mutators @@ -61,7 +61,7 @@ typedef enum { #define sb_umount_state(sbp) (le16_to_cpu((sbp)->s_v1.s_umount_state)) #define set_sb_umount_state(sbp,v) ((sbp)->s_v1.s_umount_state = cpu_to_le16(v)) #define sb_fs_state(sbp) (le16_to_cpu((sbp)->s_v1.s_fs_state)) -#define set_sb_fs_state(sbp,v) ((sbp)->s_v1.s_fs_state = cpu_to_le16(v)) +#define set_sb_fs_state(sbp,v) ((sbp)->s_v1.s_fs_state = cpu_to_le16(v)) #define sb_hash_function_code(sbp) \ (le32_to_cpu((sbp)->s_v1.s_hash_function_code)) #define set_sb_hash_function_code(sbp,v) \ @@ -103,10 +103,10 @@ typedef enum { /* don't mess with these for a while */ /* we have a node size define somewhere in reiserfs_fs.h. -Hans */ -#define JOURNAL_BLOCK_SIZE 4096 /* BUG gotta get rid of this */ -#define JOURNAL_MAX_CNODE 1500 /* max cnodes to allocate. */ -#define JOURNAL_HASH_SIZE 8192 -#define JOURNAL_NUM_BITMAPS 5 /* number of copies of the bitmaps to have floating. Must be >= 2 */ +#define JOURNAL_BLOCK_SIZE 4096 /* BUG gotta get rid of this */ +#define JOURNAL_MAX_CNODE 1500 /* max cnodes to allocate. */ +#define JOURNAL_HASH_SIZE 8192 +#define JOURNAL_NUM_BITMAPS 5 /* number of copies of the bitmaps to have floating. Must be >= 2 */ /* One of these for every block in every transaction ** Each one is in two hash tables. First, a hash of the current transaction, and after journal_end, a @@ -117,27 +117,27 @@ typedef enum { ** to a given transaction. */ struct reiserfs_journal_cnode { - struct buffer_head *bh ; /* real buffer head */ - struct super_block *sb ; /* dev of real buffer head */ - __u32 blocknr ; /* block number of real buffer head, == 0 when buffer on disk */ - long state ; - struct reiserfs_journal_list *jlist ; /* journal list this cnode lives in */ - struct reiserfs_journal_cnode *next ; /* next in transaction list */ - struct reiserfs_journal_cnode *prev ; /* prev in transaction list */ - struct reiserfs_journal_cnode *hprev ; /* prev in hash list */ - struct reiserfs_journal_cnode *hnext ; /* next in hash list */ + struct buffer_head *bh; /* real buffer head */ + struct super_block *sb; /* dev of real buffer head */ + __u32 blocknr; /* block number of real buffer head, == 0 when buffer on disk */ + long state; + struct reiserfs_journal_list *jlist; /* journal list this cnode lives in */ + struct reiserfs_journal_cnode *next; /* next in transaction list */ + struct reiserfs_journal_cnode *prev; /* prev in transaction list */ + struct reiserfs_journal_cnode *hprev; /* prev in hash list */ + struct reiserfs_journal_cnode *hnext; /* next in hash list */ }; struct reiserfs_bitmap_node { - int id ; - char *data ; - struct list_head list ; -} ; + int id; + char *data; + struct list_head list; +}; struct reiserfs_list_bitmap { - struct reiserfs_journal_list *journal_list ; - struct reiserfs_bitmap_node **bitmaps ; -} ; + struct reiserfs_journal_list *journal_list; + struct reiserfs_bitmap_node **bitmaps; +}; /* ** one of these for each transaction. The most important part here is the j_realblock. @@ -146,273 +146,269 @@ struct reiserfs_list_bitmap { ** and to make sure every real block in a transaction is on disk before allowing the log area ** to be overwritten */ struct reiserfs_journal_list { - unsigned long j_start ; - unsigned long j_state; - unsigned long j_len ; - atomic_t j_nonzerolen ; - atomic_t j_commit_left ; - atomic_t j_older_commits_done ; /* all commits older than this on disk*/ - struct semaphore j_commit_lock; - unsigned long j_trans_id ; - time_t j_timestamp ; - struct reiserfs_list_bitmap *j_list_bitmap ; - struct buffer_head *j_commit_bh ; /* commit buffer head */ - struct reiserfs_journal_cnode *j_realblock ; - struct reiserfs_journal_cnode *j_freedlist ; /* list of buffers that were freed during this trans. free each of these on flush */ - /* time ordered list of all active transactions */ - struct list_head j_list; - - /* time ordered list of all transactions we haven't tried to flush yet */ - struct list_head j_working_list; - - /* list of tail conversion targets in need of flush before commit */ - struct list_head j_tail_bh_list; - /* list of data=ordered buffers in need of flush before commit */ - struct list_head j_bh_list; - int j_refcount; -} ; + unsigned long j_start; + unsigned long j_state; + unsigned long j_len; + atomic_t j_nonzerolen; + atomic_t j_commit_left; + atomic_t j_older_commits_done; /* all commits older than this on disk */ + struct semaphore j_commit_lock; + unsigned long j_trans_id; + time_t j_timestamp; + struct reiserfs_list_bitmap *j_list_bitmap; + struct buffer_head *j_commit_bh; /* commit buffer head */ + struct reiserfs_journal_cnode *j_realblock; + struct reiserfs_journal_cnode *j_freedlist; /* list of buffers that were freed during this trans. free each of these on flush */ + /* time ordered list of all active transactions */ + struct list_head j_list; + + /* time ordered list of all transactions we haven't tried to flush yet */ + struct list_head j_working_list; + + /* list of tail conversion targets in need of flush before commit */ + struct list_head j_tail_bh_list; + /* list of data=ordered buffers in need of flush before commit */ + struct list_head j_bh_list; + int j_refcount; +}; struct reiserfs_journal { - struct buffer_head ** j_ap_blocks ; /* journal blocks on disk */ - struct reiserfs_journal_cnode *j_last ; /* newest journal block */ - struct reiserfs_journal_cnode *j_first ; /* oldest journal block. start here for traverse */ - - struct file *j_dev_file; - struct block_device *j_dev_bd; - int j_1st_reserved_block; /* first block on s_dev of reserved area journal */ - - long j_state ; - unsigned long j_trans_id ; - unsigned long j_mount_id ; - unsigned long j_start ; /* start of current waiting commit (index into j_ap_blocks) */ - unsigned long j_len ; /* lenght of current waiting commit */ - unsigned long j_len_alloc ; /* number of buffers requested by journal_begin() */ - atomic_t j_wcount ; /* count of writers for current commit */ - unsigned long j_bcount ; /* batch count. allows turning X transactions into 1 */ - unsigned long j_first_unflushed_offset ; /* first unflushed transactions offset */ - unsigned long j_last_flush_trans_id ; /* last fully flushed journal timestamp */ - struct buffer_head *j_header_bh ; - - time_t j_trans_start_time ; /* time this transaction started */ - struct semaphore j_lock; - struct semaphore j_flush_sem; - wait_queue_head_t j_join_wait ; /* wait for current transaction to finish before starting new one */ - atomic_t j_jlock ; /* lock for j_join_wait */ - int j_list_bitmap_index ; /* number of next list bitmap to use */ - int j_must_wait ; /* no more journal begins allowed. MUST sleep on j_join_wait */ - int j_next_full_flush ; /* next journal_end will flush all journal list */ - int j_next_async_flush ; /* next journal_end will flush all async commits */ - - int j_cnode_used ; /* number of cnodes on the used list */ - int j_cnode_free ; /* number of cnodes on the free list */ - - unsigned int j_trans_max ; /* max number of blocks in a transaction. */ - unsigned int j_max_batch ; /* max number of blocks to batch into a trans */ - unsigned int j_max_commit_age ; /* in seconds, how old can an async commit be */ - unsigned int j_max_trans_age ; /* in seconds, how old can a transaction be */ - unsigned int j_default_max_commit_age ; /* the default for the max commit age */ - - struct reiserfs_journal_cnode *j_cnode_free_list ; - struct reiserfs_journal_cnode *j_cnode_free_orig ; /* orig pointer returned from vmalloc */ - - struct reiserfs_journal_list *j_current_jl; - int j_free_bitmap_nodes ; - int j_used_bitmap_nodes ; - - int j_num_lists; /* total number of active transactions */ - int j_num_work_lists; /* number that need attention from kreiserfsd */ - - /* debugging to make sure things are flushed in order */ - int j_last_flush_id; - - /* debugging to make sure things are committed in order */ - int j_last_commit_id; - - struct list_head j_bitmap_nodes ; - struct list_head j_dirty_buffers ; - spinlock_t j_dirty_buffers_lock ; /* protects j_dirty_buffers */ - - /* list of all active transactions */ - struct list_head j_journal_list; - /* lists that haven't been touched by writeback attempts */ - struct list_head j_working_list; - - struct reiserfs_list_bitmap j_list_bitmap[JOURNAL_NUM_BITMAPS] ; /* array of bitmaps to record the deleted blocks */ - struct reiserfs_journal_cnode *j_hash_table[JOURNAL_HASH_SIZE] ; /* hash table for real buffer heads in current trans */ - struct reiserfs_journal_cnode *j_list_hash_table[JOURNAL_HASH_SIZE] ; /* hash table for all the real buffer heads in all - the transactions */ - struct list_head j_prealloc_list; /* list of inodes which have preallocated blocks */ - int j_persistent_trans; - unsigned long j_max_trans_size ; - unsigned long j_max_batch_size ; - - int j_errno; - - /* when flushing ordered buffers, throttle new ordered writers */ - struct work_struct j_work; - atomic_t j_async_throttle; + struct buffer_head **j_ap_blocks; /* journal blocks on disk */ + struct reiserfs_journal_cnode *j_last; /* newest journal block */ + struct reiserfs_journal_cnode *j_first; /* oldest journal block. start here for traverse */ + + struct file *j_dev_file; + struct block_device *j_dev_bd; + int j_1st_reserved_block; /* first block on s_dev of reserved area journal */ + + long j_state; + unsigned long j_trans_id; + unsigned long j_mount_id; + unsigned long j_start; /* start of current waiting commit (index into j_ap_blocks) */ + unsigned long j_len; /* lenght of current waiting commit */ + unsigned long j_len_alloc; /* number of buffers requested by journal_begin() */ + atomic_t j_wcount; /* count of writers for current commit */ + unsigned long j_bcount; /* batch count. allows turning X transactions into 1 */ + unsigned long j_first_unflushed_offset; /* first unflushed transactions offset */ + unsigned long j_last_flush_trans_id; /* last fully flushed journal timestamp */ + struct buffer_head *j_header_bh; + + time_t j_trans_start_time; /* time this transaction started */ + struct semaphore j_lock; + struct semaphore j_flush_sem; + wait_queue_head_t j_join_wait; /* wait for current transaction to finish before starting new one */ + atomic_t j_jlock; /* lock for j_join_wait */ + int j_list_bitmap_index; /* number of next list bitmap to use */ + int j_must_wait; /* no more journal begins allowed. MUST sleep on j_join_wait */ + int j_next_full_flush; /* next journal_end will flush all journal list */ + int j_next_async_flush; /* next journal_end will flush all async commits */ + + int j_cnode_used; /* number of cnodes on the used list */ + int j_cnode_free; /* number of cnodes on the free list */ + + unsigned int j_trans_max; /* max number of blocks in a transaction. */ + unsigned int j_max_batch; /* max number of blocks to batch into a trans */ + unsigned int j_max_commit_age; /* in seconds, how old can an async commit be */ + unsigned int j_max_trans_age; /* in seconds, how old can a transaction be */ + unsigned int j_default_max_commit_age; /* the default for the max commit age */ + + struct reiserfs_journal_cnode *j_cnode_free_list; + struct reiserfs_journal_cnode *j_cnode_free_orig; /* orig pointer returned from vmalloc */ + + struct reiserfs_journal_list *j_current_jl; + int j_free_bitmap_nodes; + int j_used_bitmap_nodes; + + int j_num_lists; /* total number of active transactions */ + int j_num_work_lists; /* number that need attention from kreiserfsd */ + + /* debugging to make sure things are flushed in order */ + int j_last_flush_id; + + /* debugging to make sure things are committed in order */ + int j_last_commit_id; + + struct list_head j_bitmap_nodes; + struct list_head j_dirty_buffers; + spinlock_t j_dirty_buffers_lock; /* protects j_dirty_buffers */ + + /* list of all active transactions */ + struct list_head j_journal_list; + /* lists that haven't been touched by writeback attempts */ + struct list_head j_working_list; + + struct reiserfs_list_bitmap j_list_bitmap[JOURNAL_NUM_BITMAPS]; /* array of bitmaps to record the deleted blocks */ + struct reiserfs_journal_cnode *j_hash_table[JOURNAL_HASH_SIZE]; /* hash table for real buffer heads in current trans */ + struct reiserfs_journal_cnode *j_list_hash_table[JOURNAL_HASH_SIZE]; /* hash table for all the real buffer heads in all + the transactions */ + struct list_head j_prealloc_list; /* list of inodes which have preallocated blocks */ + int j_persistent_trans; + unsigned long j_max_trans_size; + unsigned long j_max_batch_size; + + int j_errno; + + /* when flushing ordered buffers, throttle new ordered writers */ + struct work_struct j_work; + atomic_t j_async_throttle; }; enum journal_state_bits { - J_WRITERS_BLOCKED = 1, /* set when new writers not allowed */ - J_WRITERS_QUEUED, /* set when log is full due to too many writers */ - J_ABORTED, /* set when log is aborted */ + J_WRITERS_BLOCKED = 1, /* set when new writers not allowed */ + J_WRITERS_QUEUED, /* set when log is full due to too many writers */ + J_ABORTED, /* set when log is aborted */ }; +#define JOURNAL_DESC_MAGIC "ReIsErLB" /* ick. magic string to find desc blocks in the journal */ -#define JOURNAL_DESC_MAGIC "ReIsErLB" /* ick. magic string to find desc blocks in the journal */ +typedef __u32(*hashf_t) (const signed char *, int); -typedef __u32 (*hashf_t) (const signed char *, int); - -struct reiserfs_bitmap_info -{ - // FIXME: Won't work with block sizes > 8K - __u16 first_zero_hint; - __u16 free_count; - struct buffer_head *bh; /* the actual bitmap */ +struct reiserfs_bitmap_info { + // FIXME: Won't work with block sizes > 8K + __u16 first_zero_hint; + __u16 free_count; + struct buffer_head *bh; /* the actual bitmap */ }; struct proc_dir_entry; #if defined( CONFIG_PROC_FS ) && defined( CONFIG_REISERFS_PROC_INFO ) typedef unsigned long int stat_cnt_t; -typedef struct reiserfs_proc_info_data -{ - spinlock_t lock; - int exiting; - int max_hash_collisions; - - stat_cnt_t breads; - stat_cnt_t bread_miss; - stat_cnt_t search_by_key; - stat_cnt_t search_by_key_fs_changed; - stat_cnt_t search_by_key_restarted; - - stat_cnt_t insert_item_restarted; - stat_cnt_t paste_into_item_restarted; - stat_cnt_t cut_from_item_restarted; - stat_cnt_t delete_solid_item_restarted; - stat_cnt_t delete_item_restarted; - - stat_cnt_t leaked_oid; - stat_cnt_t leaves_removable; - - /* balances per level. Use explicit 5 as MAX_HEIGHT is not visible yet. */ - stat_cnt_t balance_at[ 5 ]; /* XXX */ - /* sbk == search_by_key */ - stat_cnt_t sbk_read_at[ 5 ]; /* XXX */ - stat_cnt_t sbk_fs_changed[ 5 ]; - stat_cnt_t sbk_restarted[ 5 ]; - stat_cnt_t items_at[ 5 ]; /* XXX */ - stat_cnt_t free_at[ 5 ]; /* XXX */ - stat_cnt_t can_node_be_removed[ 5 ]; /* XXX */ - long int lnum[ 5 ]; /* XXX */ - long int rnum[ 5 ]; /* XXX */ - long int lbytes[ 5 ]; /* XXX */ - long int rbytes[ 5 ]; /* XXX */ - stat_cnt_t get_neighbors[ 5 ]; - stat_cnt_t get_neighbors_restart[ 5 ]; - stat_cnt_t need_l_neighbor[ 5 ]; - stat_cnt_t need_r_neighbor[ 5 ]; - - stat_cnt_t free_block; - struct __scan_bitmap_stats { - stat_cnt_t call; - stat_cnt_t wait; - stat_cnt_t bmap; - stat_cnt_t retry; - stat_cnt_t in_journal_hint; - stat_cnt_t in_journal_nohint; - stat_cnt_t stolen; - } scan_bitmap; - struct __journal_stats { - stat_cnt_t in_journal; - stat_cnt_t in_journal_bitmap; - stat_cnt_t in_journal_reusable; - stat_cnt_t lock_journal; - stat_cnt_t lock_journal_wait; - stat_cnt_t journal_being; - stat_cnt_t journal_relock_writers; - stat_cnt_t journal_relock_wcount; - stat_cnt_t mark_dirty; - stat_cnt_t mark_dirty_already; - stat_cnt_t mark_dirty_notjournal; - stat_cnt_t restore_prepared; - stat_cnt_t prepare; - stat_cnt_t prepare_retry; - } journal; +typedef struct reiserfs_proc_info_data { + spinlock_t lock; + int exiting; + int max_hash_collisions; + + stat_cnt_t breads; + stat_cnt_t bread_miss; + stat_cnt_t search_by_key; + stat_cnt_t search_by_key_fs_changed; + stat_cnt_t search_by_key_restarted; + + stat_cnt_t insert_item_restarted; + stat_cnt_t paste_into_item_restarted; + stat_cnt_t cut_from_item_restarted; + stat_cnt_t delete_solid_item_restarted; + stat_cnt_t delete_item_restarted; + + stat_cnt_t leaked_oid; + stat_cnt_t leaves_removable; + + /* balances per level. Use explicit 5 as MAX_HEIGHT is not visible yet. */ + stat_cnt_t balance_at[5]; /* XXX */ + /* sbk == search_by_key */ + stat_cnt_t sbk_read_at[5]; /* XXX */ + stat_cnt_t sbk_fs_changed[5]; + stat_cnt_t sbk_restarted[5]; + stat_cnt_t items_at[5]; /* XXX */ + stat_cnt_t free_at[5]; /* XXX */ + stat_cnt_t can_node_be_removed[5]; /* XXX */ + long int lnum[5]; /* XXX */ + long int rnum[5]; /* XXX */ + long int lbytes[5]; /* XXX */ + long int rbytes[5]; /* XXX */ + stat_cnt_t get_neighbors[5]; + stat_cnt_t get_neighbors_restart[5]; + stat_cnt_t need_l_neighbor[5]; + stat_cnt_t need_r_neighbor[5]; + + stat_cnt_t free_block; + struct __scan_bitmap_stats { + stat_cnt_t call; + stat_cnt_t wait; + stat_cnt_t bmap; + stat_cnt_t retry; + stat_cnt_t in_journal_hint; + stat_cnt_t in_journal_nohint; + stat_cnt_t stolen; + } scan_bitmap; + struct __journal_stats { + stat_cnt_t in_journal; + stat_cnt_t in_journal_bitmap; + stat_cnt_t in_journal_reusable; + stat_cnt_t lock_journal; + stat_cnt_t lock_journal_wait; + stat_cnt_t journal_being; + stat_cnt_t journal_relock_writers; + stat_cnt_t journal_relock_wcount; + stat_cnt_t mark_dirty; + stat_cnt_t mark_dirty_already; + stat_cnt_t mark_dirty_notjournal; + stat_cnt_t restore_prepared; + stat_cnt_t prepare; + stat_cnt_t prepare_retry; + } journal; } reiserfs_proc_info_data_t; #else -typedef struct reiserfs_proc_info_data -{} reiserfs_proc_info_data_t; +typedef struct reiserfs_proc_info_data { +} reiserfs_proc_info_data_t; #endif /* reiserfs union of in-core super block data */ -struct reiserfs_sb_info -{ - struct buffer_head * s_sbh; /* Buffer containing the super block */ - /* both the comment and the choice of - name are unclear for s_rs -Hans */ - struct reiserfs_super_block * s_rs; /* Pointer to the super block in the buffer */ - struct reiserfs_bitmap_info * s_ap_bitmap; - struct reiserfs_journal *s_journal ; /* pointer to journal information */ - unsigned short s_mount_state; /* reiserfs state (valid, invalid) */ - - /* Comment? -Hans */ - void (*end_io_handler)(struct buffer_head *, int); - hashf_t s_hash_function; /* pointer to function which is used - to sort names in directory. Set on - mount */ - unsigned long s_mount_opt; /* reiserfs's mount options are set - here (currently - NOTAIL, NOLOG, - REPLAYONLY) */ - - struct { /* This is a structure that describes block allocator options */ - unsigned long bits; /* Bitfield for enable/disable kind of options */ - unsigned long large_file_size; /* size started from which we consider file to be a large one(in blocks) */ - int border; /* percentage of disk, border takes */ - int preallocmin; /* Minimal file size (in blocks) starting from which we do preallocations */ - int preallocsize; /* Number of blocks we try to prealloc when file - reaches preallocmin size (in blocks) or - prealloc_list is empty. */ - } s_alloc_options; - - /* Comment? -Hans */ - wait_queue_head_t s_wait; - /* To be obsoleted soon by per buffer seals.. -Hans */ - atomic_t s_generation_counter; // increased by one every time the - // tree gets re-balanced - unsigned long s_properties; /* File system properties. Currently holds - on-disk FS format */ - - /* session statistics */ - int s_kmallocs; - int s_disk_reads; - int s_disk_writes; - int s_fix_nodes; - int s_do_balance; - int s_unneeded_left_neighbor; - int s_good_search_by_key_reada; - int s_bmaps; - int s_bmaps_without_search; - int s_direct2indirect; - int s_indirect2direct; +struct reiserfs_sb_info { + struct buffer_head *s_sbh; /* Buffer containing the super block */ + /* both the comment and the choice of + name are unclear for s_rs -Hans */ + struct reiserfs_super_block *s_rs; /* Pointer to the super block in the buffer */ + struct reiserfs_bitmap_info *s_ap_bitmap; + struct reiserfs_journal *s_journal; /* pointer to journal information */ + unsigned short s_mount_state; /* reiserfs state (valid, invalid) */ + + /* Comment? -Hans */ + void (*end_io_handler) (struct buffer_head *, int); + hashf_t s_hash_function; /* pointer to function which is used + to sort names in directory. Set on + mount */ + unsigned long s_mount_opt; /* reiserfs's mount options are set + here (currently - NOTAIL, NOLOG, + REPLAYONLY) */ + + struct { /* This is a structure that describes block allocator options */ + unsigned long bits; /* Bitfield for enable/disable kind of options */ + unsigned long large_file_size; /* size started from which we consider file to be a large one(in blocks) */ + int border; /* percentage of disk, border takes */ + int preallocmin; /* Minimal file size (in blocks) starting from which we do preallocations */ + int preallocsize; /* Number of blocks we try to prealloc when file + reaches preallocmin size (in blocks) or + prealloc_list is empty. */ + } s_alloc_options; + + /* Comment? -Hans */ + wait_queue_head_t s_wait; + /* To be obsoleted soon by per buffer seals.. -Hans */ + atomic_t s_generation_counter; // increased by one every time the + // tree gets re-balanced + unsigned long s_properties; /* File system properties. Currently holds + on-disk FS format */ + + /* session statistics */ + int s_kmallocs; + int s_disk_reads; + int s_disk_writes; + int s_fix_nodes; + int s_do_balance; + int s_unneeded_left_neighbor; + int s_good_search_by_key_reada; + int s_bmaps; + int s_bmaps_without_search; + int s_direct2indirect; + int s_indirect2direct; /* set up when it's ok for reiserfs_read_inode2() to read from disk inode with nlink==0. Currently this is only used during finish_unfinished() processing at mount time */ - int s_is_unlinked_ok; - reiserfs_proc_info_data_t s_proc_info_data; - struct proc_dir_entry *procdir; - int reserved_blocks; /* amount of blocks reserved for further allocations */ - spinlock_t bitmap_lock; /* this lock on now only used to protect reserved_blocks variable */ - struct dentry *priv_root; /* root of /.reiserfs_priv */ - struct dentry *xattr_root; /* root of /.reiserfs_priv/.xa */ - struct rw_semaphore xattr_dir_sem; - - int j_errno; + int s_is_unlinked_ok; + reiserfs_proc_info_data_t s_proc_info_data; + struct proc_dir_entry *procdir; + int reserved_blocks; /* amount of blocks reserved for further allocations */ + spinlock_t bitmap_lock; /* this lock on now only used to protect reserved_blocks variable */ + struct dentry *priv_root; /* root of /.reiserfs_priv */ + struct dentry *xattr_root; /* root of /.reiserfs_priv/.xa */ + struct rw_semaphore xattr_dir_sem; + + int j_errno; #ifdef CONFIG_QUOTA - char *s_qf_names[MAXQUOTAS]; - int s_jquota_fmt; + char *s_qf_names[MAXQUOTAS]; + int s_jquota_fmt; #endif }; @@ -422,14 +418,14 @@ struct reiserfs_sb_info enum reiserfs_mount_options { /* Mount options */ - REISERFS_LARGETAIL, /* large tails will be created in a session */ - REISERFS_SMALLTAIL, /* small (for files less than block size) tails will be created in a session */ - REPLAYONLY, /* replay journal and return 0. Use by fsck */ - REISERFS_CONVERT, /* -o conv: causes conversion of old - format super block to the new - format. If not specified - old - partition will be dealt with in a - manner of 3.5.x */ + REISERFS_LARGETAIL, /* large tails will be created in a session */ + REISERFS_SMALLTAIL, /* small (for files less than block size) tails will be created in a session */ + REPLAYONLY, /* replay journal and return 0. Use by fsck */ + REISERFS_CONVERT, /* -o conv: causes conversion of old + format super block to the new + format. If not specified - old + partition will be dealt with in a + manner of 3.5.x */ /* -o hash={tea, rupasov, r5, detect} is meant for properly mounting ** reiserfs disks from 3.5.19 or earlier. 99% of the time, this option @@ -439,41 +435,41 @@ enum reiserfs_mount_options { ** the existing hash on the FS, so if you have a tea hash disk, and mount ** with -o hash=rupasov, the mount will fail. */ - FORCE_TEA_HASH, /* try to force tea hash on mount */ - FORCE_RUPASOV_HASH, /* try to force rupasov hash on mount */ - FORCE_R5_HASH, /* try to force rupasov hash on mount */ - FORCE_HASH_DETECT, /* try to detect hash function on mount */ + FORCE_TEA_HASH, /* try to force tea hash on mount */ + FORCE_RUPASOV_HASH, /* try to force rupasov hash on mount */ + FORCE_R5_HASH, /* try to force rupasov hash on mount */ + FORCE_HASH_DETECT, /* try to detect hash function on mount */ - REISERFS_DATA_LOG, - REISERFS_DATA_ORDERED, - REISERFS_DATA_WRITEBACK, + REISERFS_DATA_LOG, + REISERFS_DATA_ORDERED, + REISERFS_DATA_WRITEBACK, /* used for testing experimental features, makes benchmarking new features with and without more convenient, should never be used by users in any code shipped to users (ideally) */ - REISERFS_NO_BORDER, - REISERFS_NO_UNHASHED_RELOCATION, - REISERFS_HASHED_RELOCATION, - REISERFS_ATTRS, - REISERFS_XATTRS, - REISERFS_XATTRS_USER, - REISERFS_POSIXACL, - REISERFS_BARRIER_NONE, - REISERFS_BARRIER_FLUSH, - - /* Actions on error */ - REISERFS_ERROR_PANIC, - REISERFS_ERROR_RO, - REISERFS_ERROR_CONTINUE, - - REISERFS_QUOTA, /* Some quota option specified */ - - REISERFS_TEST1, - REISERFS_TEST2, - REISERFS_TEST3, - REISERFS_TEST4, - REISERFS_UNSUPPORTED_OPT, + REISERFS_NO_BORDER, + REISERFS_NO_UNHASHED_RELOCATION, + REISERFS_HASHED_RELOCATION, + REISERFS_ATTRS, + REISERFS_XATTRS, + REISERFS_XATTRS_USER, + REISERFS_POSIXACL, + REISERFS_BARRIER_NONE, + REISERFS_BARRIER_FLUSH, + + /* Actions on error */ + REISERFS_ERROR_PANIC, + REISERFS_ERROR_RO, + REISERFS_ERROR_CONTINUE, + + REISERFS_QUOTA, /* Some quota option specified */ + + REISERFS_TEST1, + REISERFS_TEST2, + REISERFS_TEST3, + REISERFS_TEST4, + REISERFS_UNSUPPORTED_OPT, }; #define reiserfs_r5_hash(s) (REISERFS_SB(s)->s_mount_opt & (1 << FORCE_R5_HASH)) @@ -504,18 +500,17 @@ enum reiserfs_mount_options { #define reiserfs_error_panic(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_ERROR_PANIC)) #define reiserfs_error_ro(s) (REISERFS_SB(s)->s_mount_opt & (1 << REISERFS_ERROR_RO)) -void reiserfs_file_buffer (struct buffer_head * bh, int list); +void reiserfs_file_buffer(struct buffer_head *bh, int list); extern struct file_system_type reiserfs_fs_type; -int reiserfs_resize(struct super_block *, unsigned long) ; +int reiserfs_resize(struct super_block *, unsigned long); #define CARRY_ON 0 #define SCHEDULE_OCCURRED 1 - #define SB_BUFFER_WITH_SB(s) (REISERFS_SB(s)->s_sbh) #define SB_JOURNAL(s) (REISERFS_SB(s)->s_journal) #define SB_JOURNAL_1st_RESERVED_BLOCK(s) (SB_JOURNAL(s)->j_1st_reserved_block) -#define SB_JOURNAL_LEN_FREE(s) (SB_JOURNAL(s)->j_journal_len_free) +#define SB_JOURNAL_LEN_FREE(s) (SB_JOURNAL(s)->j_journal_len_free) #define SB_AP_BITMAP(s) (REISERFS_SB(s)->s_ap_bitmap) #define SB_DISK_JOURNAL_HEAD(s) (SB_JOURNAL(s)->j_header_bh->) @@ -525,13 +520,14 @@ int reiserfs_resize(struct super_block *, unsigned long) ; */ static inline char *reiserfs_bdevname(struct super_block *s) { - return (s == NULL) ? "Null superblock" : s -> s_id; + return (s == NULL) ? "Null superblock" : s->s_id; } #define reiserfs_is_journal_aborted(journal) (unlikely (__reiserfs_is_journal_aborted (journal))) -static inline int __reiserfs_is_journal_aborted (struct reiserfs_journal *journal) +static inline int __reiserfs_is_journal_aborted(struct reiserfs_journal + *journal) { - return test_bit (J_ABORTED, &journal->j_state); + return test_bit(J_ABORTED, &journal->j_state); } -#endif /* _LINUX_REISER_FS_SB */ +#endif /* _LINUX_REISER_FS_SB */ diff --git a/include/linux/reiserfs_xattr.h b/include/linux/reiserfs_xattr.h index 9244c5748820..c84354e8374c 100644 --- a/include/linux/reiserfs_xattr.h +++ b/include/linux/reiserfs_xattr.h @@ -7,48 +7,48 @@ #include <linux/xattr.h> /* Magic value in header */ -#define REISERFS_XATTR_MAGIC 0x52465841 /* "RFXA" */ +#define REISERFS_XATTR_MAGIC 0x52465841 /* "RFXA" */ struct reiserfs_xattr_header { - __le32 h_magic; /* magic number for identification */ - __le32 h_hash; /* hash of the value */ + __le32 h_magic; /* magic number for identification */ + __le32 h_hash; /* hash of the value */ }; #ifdef __KERNEL__ struct reiserfs_xattr_handler { char *prefix; - int (*init)(void); - void (*exit)(void); - int (*get)(struct inode *inode, const char *name, void *buffer, - size_t size); - int (*set)(struct inode *inode, const char *name, const void *buffer, - size_t size, int flags); - int (*del)(struct inode *inode, const char *name); - int (*list)(struct inode *inode, const char *name, int namelen, char *out); - struct list_head handlers; + int (*init) (void); + void (*exit) (void); + int (*get) (struct inode * inode, const char *name, void *buffer, + size_t size); + int (*set) (struct inode * inode, const char *name, const void *buffer, + size_t size, int flags); + int (*del) (struct inode * inode, const char *name); + int (*list) (struct inode * inode, const char *name, int namelen, + char *out); + struct list_head handlers; }; - #ifdef CONFIG_REISERFS_FS_XATTR #define is_reiserfs_priv_object(inode) IS_PRIVATE(inode) #define has_xattr_dir(inode) (REISERFS_I(inode)->i_flags & i_has_xattr_dir) -ssize_t reiserfs_getxattr (struct dentry *dentry, const char *name, - void *buffer, size_t size); -int reiserfs_setxattr (struct dentry *dentry, const char *name, - const void *value, size_t size, int flags); -ssize_t reiserfs_listxattr (struct dentry *dentry, char *buffer, size_t size); -int reiserfs_removexattr (struct dentry *dentry, const char *name); -int reiserfs_delete_xattrs (struct inode *inode); -int reiserfs_chown_xattrs (struct inode *inode, struct iattr *attrs); -int reiserfs_xattr_init (struct super_block *sb, int mount_flags); -int reiserfs_permission (struct inode *inode, int mask, struct nameidata *nd); -int reiserfs_permission_locked (struct inode *inode, int mask, struct nameidata *nd); - -int reiserfs_xattr_del (struct inode *, const char *); -int reiserfs_xattr_get (const struct inode *, const char *, void *, size_t); -int reiserfs_xattr_set (struct inode *, const char *, const void *, - size_t, int); +ssize_t reiserfs_getxattr(struct dentry *dentry, const char *name, + void *buffer, size_t size); +int reiserfs_setxattr(struct dentry *dentry, const char *name, + const void *value, size_t size, int flags); +ssize_t reiserfs_listxattr(struct dentry *dentry, char *buffer, size_t size); +int reiserfs_removexattr(struct dentry *dentry, const char *name); +int reiserfs_delete_xattrs(struct inode *inode); +int reiserfs_chown_xattrs(struct inode *inode, struct iattr *attrs); +int reiserfs_xattr_init(struct super_block *sb, int mount_flags); +int reiserfs_permission(struct inode *inode, int mask, struct nameidata *nd); +int reiserfs_permission_locked(struct inode *inode, int mask, + struct nameidata *nd); + +int reiserfs_xattr_del(struct inode *, const char *); +int reiserfs_xattr_get(const struct inode *, const char *, void *, size_t); +int reiserfs_xattr_set(struct inode *, const char *, const void *, size_t, int); extern struct reiserfs_xattr_handler user_handler; extern struct reiserfs_xattr_handler trusted_handler; @@ -56,57 +56,48 @@ extern struct reiserfs_xattr_handler trusted_handler; extern struct reiserfs_xattr_handler security_handler; #endif -int reiserfs_xattr_register_handlers (void) __init; -void reiserfs_xattr_unregister_handlers (void); +int reiserfs_xattr_register_handlers(void) __init; +void reiserfs_xattr_unregister_handlers(void); -static inline void -reiserfs_write_lock_xattrs(struct super_block *sb) +static inline void reiserfs_write_lock_xattrs(struct super_block *sb) { - down_write (&REISERFS_XATTR_DIR_SEM(sb)); + down_write(&REISERFS_XATTR_DIR_SEM(sb)); } -static inline void -reiserfs_write_unlock_xattrs(struct super_block *sb) +static inline void reiserfs_write_unlock_xattrs(struct super_block *sb) { - up_write (&REISERFS_XATTR_DIR_SEM(sb)); + up_write(&REISERFS_XATTR_DIR_SEM(sb)); } -static inline void -reiserfs_read_lock_xattrs(struct super_block *sb) +static inline void reiserfs_read_lock_xattrs(struct super_block *sb) { - down_read (&REISERFS_XATTR_DIR_SEM(sb)); + down_read(&REISERFS_XATTR_DIR_SEM(sb)); } -static inline void -reiserfs_read_unlock_xattrs(struct super_block *sb) +static inline void reiserfs_read_unlock_xattrs(struct super_block *sb) { - up_read (&REISERFS_XATTR_DIR_SEM(sb)); + up_read(&REISERFS_XATTR_DIR_SEM(sb)); } -static inline void -reiserfs_write_lock_xattr_i(struct inode *inode) +static inline void reiserfs_write_lock_xattr_i(struct inode *inode) { - down_write (&REISERFS_I(inode)->xattr_sem); + down_write(&REISERFS_I(inode)->xattr_sem); } -static inline void -reiserfs_write_unlock_xattr_i(struct inode *inode) +static inline void reiserfs_write_unlock_xattr_i(struct inode *inode) { - up_write (&REISERFS_I(inode)->xattr_sem); + up_write(&REISERFS_I(inode)->xattr_sem); } -static inline void -reiserfs_read_lock_xattr_i(struct inode *inode) +static inline void reiserfs_read_lock_xattr_i(struct inode *inode) { - down_read (&REISERFS_I(inode)->xattr_sem); + down_read(&REISERFS_I(inode)->xattr_sem); } -static inline void -reiserfs_read_unlock_xattr_i(struct inode *inode) +static inline void reiserfs_read_unlock_xattr_i(struct inode *inode) { - up_read (&REISERFS_I(inode)->xattr_sem); + up_read(&REISERFS_I(inode)->xattr_sem); } -static inline void -reiserfs_mark_inode_private(struct inode *inode) +static inline void reiserfs_mark_inode_private(struct inode *inode) { - inode->i_flags |= S_PRIVATE; + inode->i_flags |= S_PRIVATE; } #else @@ -127,13 +118,20 @@ reiserfs_mark_inode_private(struct inode *inode) #define reiserfs_xattr_register_handlers() 0 #define reiserfs_xattr_unregister_handlers() -static inline int reiserfs_delete_xattrs (struct inode *inode) { return 0; }; -static inline int reiserfs_chown_xattrs (struct inode *inode, struct iattr *attrs) { return 0; }; -static inline int reiserfs_xattr_init (struct super_block *sb, int mount_flags) +static inline int reiserfs_delete_xattrs(struct inode *inode) +{ + return 0; +}; +static inline int reiserfs_chown_xattrs(struct inode *inode, + struct iattr *attrs) +{ + return 0; +}; +static inline int reiserfs_xattr_init(struct super_block *sb, int mount_flags) { - sb->s_flags = (sb->s_flags & ~MS_POSIXACL); /* to be sure */ - return 0; + sb->s_flags = (sb->s_flags & ~MS_POSIXACL); /* to be sure */ + return 0; }; #endif -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 657c05ab8f9e..c231e9a08f0b 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -826,9 +826,8 @@ enum #define TCA_RTA(r) ((struct rtattr*)(((char*)(r)) + NLMSG_ALIGN(sizeof(struct tcmsg)))) #define TCA_PAYLOAD(n) NLMSG_PAYLOAD(n,sizeof(struct tcmsg)) - -/* RTnetlink multicast groups */ - +#ifndef __KERNEL__ +/* RTnetlink multicast groups - backwards compatibility for userspace */ #define RTMGRP_LINK 1 #define RTMGRP_NOTIFY 2 #define RTMGRP_NEIGH 4 @@ -847,6 +846,43 @@ enum #define RTMGRP_DECnet_ROUTE 0x4000 #define RTMGRP_IPV6_PREFIX 0x20000 +#endif + +/* RTnetlink multicast groups */ +enum rtnetlink_groups { + RTNLGRP_NONE, +#define RTNLGRP_NONE RTNLGRP_NONE + RTNLGRP_LINK, +#define RTNLGRP_LINK RTNLGRP_LINK + RTNLGRP_NOTIFY, +#define RTNLGRP_NOTIFY RTNLGRP_NOTIFY + RTNLGRP_NEIGH, +#define RTNLGRP_NEIGH RTNLGRP_NEIGH + RTNLGRP_TC, +#define RTNLGRP_TC RTNLGRP_TC + RTNLGRP_IPV4_IFADDR, +#define RTNLGRP_IPV4_IFADDR RTNLGRP_IPV4_IFADDR + RTNLGRP_IPV4_MROUTE, +#define RTNLGRP_IPV4_MROUTE RTNLGRP_IPV4_MROUTE + RTNLGRP_IPV4_ROUTE, +#define RTNLGRP_IPV4_ROUTE RTNLGRP_IPV4_ROUTE + RTNLGRP_IPV6_IFADDR, +#define RTNLGRP_IPV6_IFADDR RTNLGRP_IPV6_IFADDR + RTNLGRP_IPV6_MROUTE, +#define RTNLGRP_IPV6_MROUTE RTNLGRP_IPV6_MROUTE + RTNLGRP_IPV6_ROUTE, +#define RTNLGRP_IPV6_ROUTE RTNLGRP_IPV6_ROUTE + RTNLGRP_IPV6_IFINFO, +#define RTNLGRP_IPV6_IFINFO RTNLGRP_IPV6_IFINFO + RTNLGRP_DECnet_IFADDR, +#define RTNLGRP_DECnet_IFADDR RTNLGRP_DECnet_IFADDR + RTNLGRP_DECnet_ROUTE, +#define RTNLGRP_DECnet_ROUTE RTNLGRP_DECnet_ROUTE + RTNLGRP_IPV6_PREFIX, +#define RTNLGRP_IPV6_PREFIX RTNLGRP_IPV6_PREFIX + __RTNLGRP_MAX +}; +#define RTNLGRP_MAX (__RTNLGRP_MAX - 1) /* TC action piece */ struct tcamsg diff --git a/include/linux/sched.h b/include/linux/sched.h index ff48815bd3a2..dec5827c7742 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -410,6 +410,10 @@ struct user_struct { atomic_t processes; /* How many processes does this user have? */ atomic_t files; /* How many open files does this user have? */ atomic_t sigpending; /* How many pending signals does this user have? */ +#ifdef CONFIG_INOTIFY + atomic_t inotify_watches; /* How many inotify watches does this user have? */ + atomic_t inotify_devs; /* How many inotify devs does this user have opened? */ +#endif /* protected by mq_lock */ unsigned long mq_bytes; /* How many bytes can be allocated to mqueue? */ unsigned long locked_shm; /* How many pages of mlocked shm ? */ diff --git a/include/linux/security.h b/include/linux/security.h index b42095a68b1c..7aab6ab7c57f 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -2727,7 +2727,8 @@ static inline int security_socket_getpeersec(struct socket *sock, char __user *o return security_ops->socket_getpeersec(sock, optval, optlen, len); } -static inline int security_sk_alloc(struct sock *sk, int family, int priority) +static inline int security_sk_alloc(struct sock *sk, int family, + unsigned int __nocast priority) { return security_ops->sk_alloc_security(sk, family, priority); } @@ -2844,7 +2845,8 @@ static inline int security_socket_getpeersec(struct socket *sock, char __user *o return -ENOPROTOOPT; } -static inline int security_sk_alloc(struct sock *sk, int family, int priority) +static inline int security_sk_alloc(struct sock *sk, int family, + unsigned int __nocast priority) { return 0; } diff --git a/include/linux/selinux_netlink.h b/include/linux/selinux_netlink.h index 957e6ebca4e6..bbf489decd84 100644 --- a/include/linux/selinux_netlink.h +++ b/include/linux/selinux_netlink.h @@ -20,10 +20,21 @@ enum { SELNL_MSG_MAX }; -/* Multicast groups */ +#ifndef __KERNEL__ +/* Multicast groups - backwards compatiblility for userspace */ #define SELNL_GRP_NONE 0x00000000 #define SELNL_GRP_AVC 0x00000001 /* AVC notifications */ #define SELNL_GRP_ALL 0xffffffff +#endif + +enum selinux_nlgroups { + SELNLGRP_NONE, +#define SELNLGRP_NONE SELNLGRP_NONE + SELNLGRP_AVC, +#define SELNLGRP_AVC SELNLGRP_AVC + __SELNLGRP_MAX +}; +#define SELNLGRP_MAX (__SELNLGRP_MAX - 1) /* Message structures */ struct selnl_msg_setenforce { diff --git a/include/linux/serial.h b/include/linux/serial.h index 00145822fb74..12cd9cf65e8f 100644 --- a/include/linux/serial.h +++ b/include/linux/serial.h @@ -174,9 +174,7 @@ struct serial_icounter_struct { #ifdef __KERNEL__ -/* Export to allow PCMCIA to use this - Dave Hinds */ -extern int register_serial(struct serial_struct *req); -extern void unregister_serial(int line); +#include <linux/compiler.h> /* Allow architectures to override entries in serial8250_ports[] at run time: */ struct uart_port; /* forward declaration */ diff --git a/include/linux/serialP.h b/include/linux/serialP.h index 2307f11d8a6b..2b9e6b9554d5 100644 --- a/include/linux/serialP.h +++ b/include/linux/serialP.h @@ -19,7 +19,6 @@ * For definitions of the flags field, see tty.h */ -#include <linux/version.h> #include <linux/config.h> #include <linux/termios.h> #include <linux/workqueue.h> @@ -141,44 +140,4 @@ struct rs_multiport_struct { #define ALPHA_KLUDGE_MCR 0 #endif -/* - * Definitions for PCI support. - */ -#define SPCI_FL_BASE_MASK 0x0007 -#define SPCI_FL_BASE0 0x0000 -#define SPCI_FL_BASE1 0x0001 -#define SPCI_FL_BASE2 0x0002 -#define SPCI_FL_BASE3 0x0003 -#define SPCI_FL_BASE4 0x0004 -#define SPCI_FL_GET_BASE(x) (x & SPCI_FL_BASE_MASK) - -#define SPCI_FL_IRQ_MASK (0x0007 << 4) -#define SPCI_FL_IRQBASE0 (0x0000 << 4) -#define SPCI_FL_IRQBASE1 (0x0001 << 4) -#define SPCI_FL_IRQBASE2 (0x0002 << 4) -#define SPCI_FL_IRQBASE3 (0x0003 << 4) -#define SPCI_FL_IRQBASE4 (0x0004 << 4) -#define SPCI_FL_GET_IRQBASE(x) ((x & SPCI_FL_IRQ_MASK) >> 4) - -/* Use successive BARs (PCI base address registers), - else use offset into some specified BAR */ -#define SPCI_FL_BASE_TABLE 0x0100 - -/* Use successive entries in the irq resource table */ -#define SPCI_FL_IRQ_TABLE 0x0200 - -/* Use the irq resource table instead of dev->irq */ -#define SPCI_FL_IRQRESOURCE 0x0400 - -/* Use the Base address register size to cap number of ports */ -#define SPCI_FL_REGION_SZ_CAP 0x0800 - -/* Do not use irq sharing for this device */ -#define SPCI_FL_NO_SHIRQ 0x1000 - -/* This is a PNP device */ -#define SPCI_FL_ISPNP 0x2000 - -#define SPCI_FL_PNPDEFAULT (SPCI_FL_IRQRESOURCE|SPCI_FL_ISPNP) - #endif /* _LINUX_SERIAL_H */ diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h index 3e3c1fa35b06..d8a023d804d4 100644 --- a/include/linux/serial_8250.h +++ b/include/linux/serial_8250.h @@ -14,6 +14,9 @@ #include <linux/serial_core.h> #include <linux/device.h> +/* + * This is the platform device platform_data structure + */ struct plat_serial8250_port { unsigned long iobase; /* io base address */ void __iomem *membase; /* ioremap cookie or NULL */ @@ -26,4 +29,17 @@ struct plat_serial8250_port { unsigned int flags; /* UPF_* flags */ }; +/* + * This should be used by drivers which want to register + * their own 8250 ports without registering their own + * platform device. Using these will make your driver + * dependent on the 8250 driver. + */ +struct uart_port; + +int serial8250_register_port(struct uart_port *); +void serial8250_unregister_port(int line); +void serial8250_suspend_port(int line); +void serial8250_resume_port(int line); + #endif diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index d6025af7efac..cf0f64ea2bc0 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -104,7 +104,7 @@ #define PORT_MPSC 63 /* TXX9 type number */ -#define PORT_TXX9 64 +#define PORT_TXX9 64 /* NEC VR4100 series SIU/DSIU */ #define PORT_VR41XX_SIU 65 @@ -122,6 +122,7 @@ #ifdef __KERNEL__ #include <linux/config.h> +#include <linux/compiler.h> #include <linux/interrupt.h> #include <linux/circ_buf.h> #include <linux/spinlock.h> @@ -141,8 +142,8 @@ struct uart_ops { unsigned int (*tx_empty)(struct uart_port *); void (*set_mctrl)(struct uart_port *, unsigned int mctrl); unsigned int (*get_mctrl)(struct uart_port *); - void (*stop_tx)(struct uart_port *, unsigned int tty_stop); - void (*start_tx)(struct uart_port *, unsigned int tty_start); + void (*stop_tx)(struct uart_port *); + void (*start_tx)(struct uart_port *); void (*send_xchar)(struct uart_port *, char ch); void (*stop_rx)(struct uart_port *); void (*enable_ms)(struct uart_port *); @@ -359,8 +360,6 @@ struct tty_driver *uart_console_device(struct console *co, int *index); */ int uart_register_driver(struct uart_driver *uart); void uart_unregister_driver(struct uart_driver *uart); -void uart_unregister_port(struct uart_driver *reg, int line); -int uart_register_port(struct uart_driver *reg, struct uart_port *port); int uart_add_one_port(struct uart_driver *reg, struct uart_port *port); int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port); int uart_match_port(struct uart_port *port1, struct uart_port *port2); @@ -467,13 +466,13 @@ uart_handle_cts_change(struct uart_port *port, unsigned int status) if (tty->hw_stopped) { if (status) { tty->hw_stopped = 0; - port->ops->start_tx(port, 0); + port->ops->start_tx(port); uart_write_wakeup(port); } } else { if (!status) { tty->hw_stopped = 1; - port->ops->stop_tx(port, 0); + port->ops->stop_tx(port); } } } diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 5d4a990d5577..42edce6abe23 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -155,16 +155,29 @@ struct skb_shared_info { #define SKB_DATAREF_SHIFT 16 #define SKB_DATAREF_MASK ((1 << SKB_DATAREF_SHIFT) - 1) +extern struct timeval skb_tv_base; + +struct skb_timeval { + u32 off_sec; + u32 off_usec; +}; + + +enum { + SKB_FCLONE_UNAVAILABLE, + SKB_FCLONE_ORIG, + SKB_FCLONE_CLONE, +}; + /** * struct sk_buff - socket buffer * @next: Next buffer in list * @prev: Previous buffer in list * @list: List we are on * @sk: Socket we are owned by - * @stamp: Time we arrived + * @tstamp: Time we arrived stored as offset to skb_tv_base * @dev: Device we arrived on/are leaving by * @input_dev: Device we arrived on - * @real_dev: The real device we are using * @h: Transport layer header * @nh: Network layer header * @mac: Link layer header @@ -190,14 +203,11 @@ struct skb_shared_info { * @end: End pointer * @destructor: Destruct function * @nfmark: Can be used for communication between hooks - * @nfcache: Cache info * @nfct: Associated connection, if any * @nfctinfo: Relationship of this skb to the connection * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c - * @private: Data which is private to the HIPPI implementation * @tc_index: Traffic control index * @tc_verd: traffic control verdict - * @tc_classid: traffic control classid */ struct sk_buff { @@ -205,12 +215,10 @@ struct sk_buff { struct sk_buff *next; struct sk_buff *prev; - struct sk_buff_head *list; struct sock *sk; - struct timeval stamp; + struct skb_timeval tstamp; struct net_device *dev; struct net_device *input_dev; - struct net_device *real_dev; union { struct tcphdr *th; @@ -252,33 +260,28 @@ struct sk_buff { __u8 local_df:1, cloned:1, ip_summed:2, - nohdr:1; - /* 3 bits spare */ - __u8 pkt_type; - __u16 protocol; + nohdr:1, + nfctinfo:3; + __u8 pkt_type:3, + fclone:2; + __be16 protocol; void (*destructor)(struct sk_buff *skb); #ifdef CONFIG_NETFILTER - unsigned long nfmark; - __u32 nfcache; - __u32 nfctinfo; + __u32 nfmark; struct nf_conntrack *nfct; +#if defined(CONFIG_IP_VS) || defined(CONFIG_IP_VS_MODULE) + __u8 ipvs_property:1; +#endif #ifdef CONFIG_BRIDGE_NETFILTER struct nf_bridge_info *nf_bridge; #endif #endif /* CONFIG_NETFILTER */ -#if defined(CONFIG_HIPPI) - union { - __u32 ifield; - } private; -#endif #ifdef CONFIG_NET_SCHED - __u32 tc_index; /* traffic control index */ + __u16 tc_index; /* traffic control index */ #ifdef CONFIG_NET_CLS_ACT - __u32 tc_verd; /* traffic control verdict */ - __u32 tc_classid; /* traffic control classid */ + __u16 tc_verd; /* traffic control verdict */ #endif - #endif @@ -300,8 +303,20 @@ struct sk_buff { #include <asm/system.h> extern void __kfree_skb(struct sk_buff *skb); -extern struct sk_buff *alloc_skb(unsigned int size, - unsigned int __nocast priority); +extern struct sk_buff *__alloc_skb(unsigned int size, + unsigned int __nocast priority, int fclone); +static inline struct sk_buff *alloc_skb(unsigned int size, + unsigned int __nocast priority) +{ + return __alloc_skb(size, priority, 0); +} + +static inline struct sk_buff *alloc_skb_fclone(unsigned int size, + unsigned int __nocast priority) +{ + return __alloc_skb(size, priority, 1); +} + extern struct sk_buff *alloc_skb_from_cache(kmem_cache_t *cp, unsigned int size, unsigned int __nocast priority); @@ -502,7 +517,8 @@ static inline struct sk_buff *skb_share_check(struct sk_buff *skb, * * %NULL is returned on a memory allocation failure. */ -static inline struct sk_buff *skb_unshare(struct sk_buff *skb, int pri) +static inline struct sk_buff *skb_unshare(struct sk_buff *skb, + unsigned int __nocast pri) { might_sleep_if(pri & __GFP_WAIT); if (skb_cloned(skb)) { @@ -596,7 +612,6 @@ static inline void __skb_queue_head(struct sk_buff_head *list, { struct sk_buff *prev, *next; - newsk->list = list; list->qlen++; prev = (struct sk_buff *)list; next = prev->next; @@ -621,7 +636,6 @@ static inline void __skb_queue_tail(struct sk_buff_head *list, { struct sk_buff *prev, *next; - newsk->list = list; list->qlen++; next = (struct sk_buff *)list; prev = next->prev; @@ -654,7 +668,6 @@ static inline struct sk_buff *__skb_dequeue(struct sk_buff_head *list) next->prev = prev; prev->next = next; result->next = result->prev = NULL; - result->list = NULL; } return result; } @@ -663,7 +676,7 @@ static inline struct sk_buff *__skb_dequeue(struct sk_buff_head *list) /* * Insert a packet on a list. */ -extern void skb_insert(struct sk_buff *old, struct sk_buff *newsk); +extern void skb_insert(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list); static inline void __skb_insert(struct sk_buff *newsk, struct sk_buff *prev, struct sk_buff *next, struct sk_buff_head *list) @@ -671,24 +684,23 @@ static inline void __skb_insert(struct sk_buff *newsk, newsk->next = next; newsk->prev = prev; next->prev = prev->next = newsk; - newsk->list = list; list->qlen++; } /* * Place a packet after a given packet in a list. */ -extern void skb_append(struct sk_buff *old, struct sk_buff *newsk); -static inline void __skb_append(struct sk_buff *old, struct sk_buff *newsk) +extern void skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list); +static inline void __skb_append(struct sk_buff *old, struct sk_buff *newsk, struct sk_buff_head *list) { - __skb_insert(newsk, old, old->next, old->list); + __skb_insert(newsk, old, old->next, list); } /* * remove sk_buff from list. _Must_ be called atomically, and with * the list known.. */ -extern void skb_unlink(struct sk_buff *skb); +extern void skb_unlink(struct sk_buff *skb, struct sk_buff_head *list); static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) { struct sk_buff *next, *prev; @@ -697,7 +709,6 @@ static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) next = skb->next; prev = skb->prev; skb->next = skb->prev = NULL; - skb->list = NULL; next->prev = prev; prev->next = next; } @@ -1212,6 +1223,8 @@ extern void skb_copy_and_csum_dev(const struct sk_buff *skb, u8 *to); extern void skb_split(struct sk_buff *skb, struct sk_buff *skb1, const u32 len); +extern void skb_release_data(struct sk_buff *skb); + static inline void *skb_header_pointer(const struct sk_buff *skb, int offset, int len, void *buffer) { @@ -1229,6 +1242,42 @@ static inline void *skb_header_pointer(const struct sk_buff *skb, int offset, extern void skb_init(void); extern void skb_add_mtu(int mtu); +/** + * skb_get_timestamp - get timestamp from a skb + * @skb: skb to get stamp from + * @stamp: pointer to struct timeval to store stamp in + * + * Timestamps are stored in the skb as offsets to a base timestamp. + * This function converts the offset back to a struct timeval and stores + * it in stamp. + */ +static inline void skb_get_timestamp(struct sk_buff *skb, struct timeval *stamp) +{ + stamp->tv_sec = skb->tstamp.off_sec; + stamp->tv_usec = skb->tstamp.off_usec; + if (skb->tstamp.off_sec) { + stamp->tv_sec += skb_tv_base.tv_sec; + stamp->tv_usec += skb_tv_base.tv_usec; + } +} + +/** + * skb_set_timestamp - set timestamp of a skb + * @skb: skb to set stamp of + * @stamp: pointer to struct timeval to get stamp from + * + * Timestamps are stored in the skb as offsets to a base timestamp. + * This function converts a struct timeval to an offset and stores + * it in the skb. + */ +static inline void skb_set_timestamp(struct sk_buff *skb, struct timeval *stamp) +{ + skb->tstamp.off_sec = stamp->tv_sec - skb_tv_base.tv_sec; + skb->tstamp.off_usec = stamp->tv_usec - skb_tv_base.tv_usec; +} + +extern void __net_timestamp(struct sk_buff *skb); + #ifdef CONFIG_NETFILTER static inline void nf_conntrack_put(struct nf_conntrack *nfct) { diff --git a/include/linux/slab.h b/include/linux/slab.h index 4c8e552471b0..80b2dfde2e80 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -111,7 +111,7 @@ static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int flags, int n { return kmem_cache_alloc(cachep, flags); } -static inline void *kmalloc_node(size_t size, int flags, int node) +static inline void *kmalloc_node(size_t size, unsigned int __nocast flags, int node) { return kmalloc(size, flags); } diff --git a/include/linux/socket.h b/include/linux/socket.h index a5c7d96e4d2e..1739c2d5b95b 100644 --- a/include/linux/socket.h +++ b/include/linux/socket.h @@ -26,6 +26,13 @@ struct __kernel_sockaddr_storage { #include <linux/types.h> /* pid_t */ #include <linux/compiler.h> /* __user */ +extern int sysctl_somaxconn; +extern void sock_init(void); +#ifdef CONFIG_PROC_FS +struct seq_file; +extern void socket_seq_show(struct seq_file *seq); +#endif + typedef unsigned short sa_family_t; /* @@ -271,6 +278,8 @@ struct ucred { #define SOL_IRDA 266 #define SOL_NETBEUI 267 #define SOL_LLC 268 +#define SOL_DCCP 269 +#define SOL_NETLINK 270 /* IPX options */ #define IPX_TYPE 1 diff --git a/include/linux/sound.h b/include/linux/sound.h index 428f59794f48..72b9af4c3fd4 100644 --- a/include/linux/sound.h +++ b/include/linux/sound.h @@ -29,7 +29,9 @@ * Sound core interface functions */ +struct device; extern int register_sound_special(struct file_operations *fops, int unit); +extern int register_sound_special_device(struct file_operations *fops, int unit, struct device *dev); extern int register_sound_mixer(struct file_operations *fops, int dev); extern int register_sound_midi(struct file_operations *fops, int dev); extern int register_sound_dsp(struct file_operations *fops, int dev); diff --git a/include/linux/sunrpc/xdr.h b/include/linux/sunrpc/xdr.h index 34ec3e8d99b3..23448d0fb5bc 100644 --- a/include/linux/sunrpc/xdr.h +++ b/include/linux/sunrpc/xdr.h @@ -177,6 +177,7 @@ typedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *desc, void *elem); struct xdr_array2_desc { unsigned int elem_size; unsigned int array_len; + unsigned int array_maxlen; xdr_xcode_elem_t xcode; }; diff --git a/include/linux/swap.h b/include/linux/swap.h index c75954f2d868..3c9ff0048153 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h @@ -7,6 +7,7 @@ #include <linux/mmzone.h> #include <linux/list.h> #include <linux/sched.h> + #include <asm/atomic.h> #include <asm/page.h> @@ -106,6 +107,8 @@ enum { SWP_USED = (1 << 0), /* is slot in swap_info[] used? */ SWP_WRITEOK = (1 << 1), /* ok to write to this swap? */ SWP_ACTIVE = (SWP_USED | SWP_WRITEOK), + /* add others here before... */ + SWP_SCANNING = (1 << 8), /* refcount in scan_swap_map */ }; #define SWAP_CLUSTER_MAX 32 @@ -115,16 +118,13 @@ enum { /* * The in-memory structure used to track swap areas. - * extent_list.prev points at the lowest-index extent. That list is - * sorted. */ struct swap_info_struct { unsigned int flags; - spinlock_t sdev_lock; + int prio; /* swap priority */ struct file *swap_file; struct block_device *bdev; struct list_head extent_list; - int nr_extents; struct swap_extent *curr_swap_extent; unsigned old_block_size; unsigned short * swap_map; @@ -132,10 +132,9 @@ struct swap_info_struct { unsigned int highest_bit; unsigned int cluster_next; unsigned int cluster_nr; - int prio; /* swap priority */ - int pages; - unsigned long max; - unsigned long inuse_pages; + unsigned int pages; + unsigned int max; + unsigned int inuse_pages; int next; /* next entry on swap list */ }; @@ -221,13 +220,7 @@ extern int can_share_swap_page(struct page *); extern int remove_exclusive_swap_page(struct page *); struct backing_dev_info; -extern struct swap_list_t swap_list; -extern spinlock_t swaplock; - -#define swap_list_lock() spin_lock(&swaplock) -#define swap_list_unlock() spin_unlock(&swaplock) -#define swap_device_lock(p) spin_lock(&p->sdev_lock) -#define swap_device_unlock(p) spin_unlock(&p->sdev_lock) +extern spinlock_t swap_lock; /* linux/mm/thrash.c */ extern struct mm_struct * swap_token_mm; @@ -253,6 +246,8 @@ static inline void put_swap_token(struct mm_struct *mm) #define si_swapinfo(val) \ do { (val)->freeswap = (val)->totalswap = 0; } while (0) +/* only sparc can not include linux/pagemap.h in this file + * so leave page_cache_release and release_pages undeclared... */ #define free_page_and_swap_cache(page) \ page_cache_release(page) #define free_pages_and_swap_cache(pages, nr) \ diff --git a/include/linux/swapops.h b/include/linux/swapops.h index d4c7db35e708..87b9d14c710d 100644 --- a/include/linux/swapops.h +++ b/include/linux/swapops.h @@ -4,7 +4,7 @@ * the low-order bits. * * We arrange the `type' and `offset' fields so that `type' is at the five - * high-order bits of the smp_entry_t and `offset' is right-aligned in the + * high-order bits of the swp_entry_t and `offset' is right-aligned in the * remaining bits. * * swp_entry_t's are *never* stored anywhere in their arch-dependent format. diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 5b5f434ac9a0..e82be96d4906 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -70,6 +70,14 @@ enum CTL_BUS_ISA=1 /* ISA */ }; +/* /proc/sys/fs/inotify/ */ +enum +{ + INOTIFY_MAX_USER_INSTANCES=1, /* max instances per user */ + INOTIFY_MAX_USER_WATCHES=2, /* max watches per user */ + INOTIFY_MAX_QUEUED_EVENTS=3 /* max queued events per instance */ +}; + /* CTL_KERN names: */ enum { @@ -137,6 +145,7 @@ enum KERN_BOOTLOADER_TYPE=67, /* int: boot loader type */ KERN_RANDOMIZE=68, /* int: randomize virtual address space */ KERN_SETUID_DUMPABLE=69, /* int: behaviour of dumps for setuid core */ + KERN_SPIN_RETRY=70, /* int: number of spinlock retries */ }; @@ -676,6 +685,7 @@ enum FS_XFS=17, /* struct: control xfs parameters */ FS_AIO_NR=18, /* current system-wide number of aio requests */ FS_AIO_MAX_NR=19, /* system-wide maximum number of aio requests */ + FS_INOTIFY=20, /* inotify submenu */ }; /* /proc/sys/fs/quota/ */ diff --git a/include/linux/tc_ematch/tc_em_meta.h b/include/linux/tc_ematch/tc_em_meta.h index bcb762d93123..081b1ee8516e 100644 --- a/include/linux/tc_ematch/tc_em_meta.h +++ b/include/linux/tc_ematch/tc_em_meta.h @@ -41,19 +41,14 @@ enum TCF_META_ID_LOADAVG_1, TCF_META_ID_LOADAVG_2, TCF_META_ID_DEV, - TCF_META_ID_INDEV, - TCF_META_ID_REALDEV, TCF_META_ID_PRIORITY, TCF_META_ID_PROTOCOL, - TCF_META_ID_SECURITY, /* obsolete */ TCF_META_ID_PKTTYPE, TCF_META_ID_PKTLEN, TCF_META_ID_DATALEN, TCF_META_ID_MACLEN, TCF_META_ID_NFMARK, TCF_META_ID_TCINDEX, - TCF_META_ID_TCVERDICT, - TCF_META_ID_TCCLASSID, TCF_META_ID_RTCLASSID, TCF_META_ID_RTIIF, TCF_META_ID_SK_FAMILY, diff --git a/include/linux/tcp.h b/include/linux/tcp.h index e4fd82e42104..ac4ca44c75ca 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -55,24 +55,6 @@ struct tcphdr { __u16 urg_ptr; }; - -enum { - TCP_ESTABLISHED = 1, - TCP_SYN_SENT, - TCP_SYN_RECV, - TCP_FIN_WAIT1, - TCP_FIN_WAIT2, - TCP_TIME_WAIT, - TCP_CLOSE, - TCP_CLOSE_WAIT, - TCP_LAST_ACK, - TCP_LISTEN, - TCP_CLOSING, /* now a valid state */ - - TCP_MAX_STATES /* Leave at the end! */ -}; - -#define TCP_STATE_MASK 0xF #define TCP_ACTION_FIN (1 << 7) enum { @@ -195,8 +177,9 @@ struct tcp_info #include <linux/config.h> #include <linux/skbuff.h> -#include <linux/ip.h> #include <net/sock.h> +#include <net/inet_connection_sock.h> +#include <net/inet_timewait_sock.h> /* This defines a selective acknowledgement block. */ struct tcp_sack_block { @@ -236,8 +219,8 @@ static inline struct tcp_request_sock *tcp_rsk(const struct request_sock *req) } struct tcp_sock { - /* inet_sock has to be the first member of tcp_sock */ - struct inet_sock inet; + /* inet_connection_sock has to be the first member of tcp_sock */ + struct inet_connection_sock inet_conn; int tcp_header_len; /* Bytes of tcp header to send */ /* @@ -258,19 +241,6 @@ struct tcp_sock { __u32 snd_sml; /* Last byte of the most recently transmitted small packet */ __u32 rcv_tstamp; /* timestamp of last received ACK (for keepalives) */ __u32 lsndtime; /* timestamp of last sent data packet (for restart window) */ - struct tcp_bind_bucket *bind_hash; - /* Delayed ACK control data */ - struct { - __u8 pending; /* ACK is pending */ - __u8 quick; /* Scheduled number of quick acks */ - __u8 pingpong; /* The session is interactive */ - __u8 blocked; /* Delayed ACK was blocked by socket lock*/ - __u32 ato; /* Predicted tick of soft clock */ - unsigned long timeout; /* Currently scheduled timeout */ - __u32 lrcvtime; /* timestamp of last received data packet*/ - __u16 last_seg_size; /* Size of last incoming segment */ - __u16 rcv_mss; /* MSS used for delayed ACK decisions */ - } ack; /* Data for direct copy to user */ struct { @@ -288,19 +258,15 @@ struct tcp_sock { __u32 mss_cache; /* Cached effective mss, not including SACKS */ __u16 xmit_size_goal; /* Goal for segmenting output packets */ __u16 ext_header_len; /* Network protocol overhead (IP/IPv6 options) */ - __u8 ca_state; /* State of fast-retransmit machine */ - __u8 retransmits; /* Number of unrecovered RTO timeouts. */ - __u16 advmss; /* Advertised MSS */ __u32 window_clamp; /* Maximal window to advertise */ __u32 rcv_ssthresh; /* Current window clamp */ __u32 frto_highmark; /* snd_nxt when RTO occurred */ __u8 reordering; /* Packet reordering metric. */ __u8 frto_counter; /* Number of new acks after RTO */ - - __u8 unused; - __u8 defer_accept; /* User waits for some data after accept() */ + __u8 nonagle; /* Disable Nagle algorithm? */ + __u8 keepalive_probes; /* num of allowed keep alive probes */ /* RTT measurement */ __u32 srtt; /* smoothed round trip time << 3 */ @@ -308,19 +274,13 @@ struct tcp_sock { __u32 mdev_max; /* maximal mdev for the last rtt period */ __u32 rttvar; /* smoothed mdev_max */ __u32 rtt_seq; /* sequence number to update rttvar */ - __u32 rto; /* retransmit timeout */ __u32 packets_out; /* Packets which are "in flight" */ __u32 left_out; /* Packets which leaved network */ __u32 retrans_out; /* Retransmitted packets out */ - __u8 backoff; /* backoff */ /* * Options received (usually on last packet, some only on SYN packets). */ - __u8 nonagle; /* Disable Nagle algorithm? */ - __u8 keepalive_probes; /* num of allowed keep alive probes */ - - __u8 probes_out; /* unanswered 0 window probes */ struct tcp_options_received rx_opt; /* @@ -333,11 +293,6 @@ struct tcp_sock { __u32 snd_cwnd_used; __u32 snd_cwnd_stamp; - /* Two commonly used timers in both sender and receiver paths. */ - unsigned long timeout; - struct timer_list retransmit_timer; /* Resend (no ack) */ - struct timer_list delack_timer; /* Ack delay */ - struct sk_buff_head out_of_order_queue; /* Out of order segments go here */ struct tcp_func *af_specific; /* Operations which are AF_INET{4,6} specific */ @@ -352,8 +307,7 @@ struct tcp_sock { struct tcp_sack_block duplicate_sack[1]; /* D-SACK block */ struct tcp_sack_block selective_acks[4]; /* The SACKS themselves*/ - __u8 syn_retries; /* num of allowed syn retries */ - __u8 ecn_flags; /* ECN status bits. */ + __u16 advmss; /* Advertised MSS */ __u16 prior_ssthresh; /* ssthresh saved at recovery start */ __u32 lost_out; /* Lost packets */ __u32 sacked_out; /* SACK'd packets */ @@ -367,14 +321,12 @@ struct tcp_sock { int undo_retrans; /* number of undoable retransmissions. */ __u32 urg_seq; /* Seq of received urgent pointer */ __u16 urg_data; /* Saved octet of OOB data and control flags */ - __u8 pending; /* Scheduled timer event */ __u8 urg_mode; /* In urgent mode */ + __u8 ecn_flags; /* ECN status bits. */ __u32 snd_up; /* Urgent pointer */ __u32 total_retrans; /* Total retransmits for entire connection */ - struct request_sock_queue accept_queue; /* FIFO of established children */ - unsigned int keepalive_time; /* time before keep alive takes place */ unsigned int keepalive_intvl; /* time interval between keep alive probes */ int linger2; @@ -394,11 +346,6 @@ struct tcp_sock { __u32 seq; __u32 time; } rcvq_space; - - /* Pluggable TCP congestion control hook */ - struct tcp_congestion_ops *ca_ops; - u32 ca_priv[16]; -#define TCP_CA_PRIV_SIZE (16*sizeof(u32)) }; static inline struct tcp_sock *tcp_sk(const struct sock *sk) @@ -406,9 +353,18 @@ static inline struct tcp_sock *tcp_sk(const struct sock *sk) return (struct tcp_sock *)sk; } -static inline void *tcp_ca(const struct tcp_sock *tp) +struct tcp_timewait_sock { + struct inet_timewait_sock tw_sk; + __u32 tw_rcv_nxt; + __u32 tw_snd_nxt; + __u32 tw_rcv_wnd; + __u32 tw_ts_recent; + long tw_ts_recent_stamp; +}; + +static inline struct tcp_timewait_sock *tcp_twsk(const struct sock *sk) { - return (void *) tp->ca_priv; + return (struct tcp_timewait_sock *)sk; } #endif diff --git a/include/linux/tcp_diag.h b/include/linux/tcp_diag.h deleted file mode 100644 index 7a5996743946..000000000000 --- a/include/linux/tcp_diag.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef _TCP_DIAG_H_ -#define _TCP_DIAG_H_ 1 - -/* Just some random number */ -#define TCPDIAG_GETSOCK 18 - -/* Socket identity */ -struct tcpdiag_sockid -{ - __u16 tcpdiag_sport; - __u16 tcpdiag_dport; - __u32 tcpdiag_src[4]; - __u32 tcpdiag_dst[4]; - __u32 tcpdiag_if; - __u32 tcpdiag_cookie[2]; -#define TCPDIAG_NOCOOKIE (~0U) -}; - -/* Request structure */ - -struct tcpdiagreq -{ - __u8 tcpdiag_family; /* Family of addresses. */ - __u8 tcpdiag_src_len; - __u8 tcpdiag_dst_len; - __u8 tcpdiag_ext; /* Query extended information */ - - struct tcpdiag_sockid id; - - __u32 tcpdiag_states; /* States to dump */ - __u32 tcpdiag_dbs; /* Tables to dump (NI) */ -}; - -enum -{ - TCPDIAG_REQ_NONE, - TCPDIAG_REQ_BYTECODE, -}; - -#define TCPDIAG_REQ_MAX TCPDIAG_REQ_BYTECODE - -/* Bytecode is sequence of 4 byte commands followed by variable arguments. - * All the commands identified by "code" are conditional jumps forward: - * to offset cc+"yes" or to offset cc+"no". "yes" is supposed to be - * length of the command and its arguments. - */ - -struct tcpdiag_bc_op -{ - unsigned char code; - unsigned char yes; - unsigned short no; -}; - -enum -{ - TCPDIAG_BC_NOP, - TCPDIAG_BC_JMP, - TCPDIAG_BC_S_GE, - TCPDIAG_BC_S_LE, - TCPDIAG_BC_D_GE, - TCPDIAG_BC_D_LE, - TCPDIAG_BC_AUTO, - TCPDIAG_BC_S_COND, - TCPDIAG_BC_D_COND, -}; - -struct tcpdiag_hostcond -{ - __u8 family; - __u8 prefix_len; - int port; - __u32 addr[0]; -}; - -/* Base info structure. It contains socket identity (addrs/ports/cookie) - * and, alas, the information shown by netstat. */ -struct tcpdiagmsg -{ - __u8 tcpdiag_family; - __u8 tcpdiag_state; - __u8 tcpdiag_timer; - __u8 tcpdiag_retrans; - - struct tcpdiag_sockid id; - - __u32 tcpdiag_expires; - __u32 tcpdiag_rqueue; - __u32 tcpdiag_wqueue; - __u32 tcpdiag_uid; - __u32 tcpdiag_inode; -}; - -/* Extensions */ - -enum -{ - TCPDIAG_NONE, - TCPDIAG_MEMINFO, - TCPDIAG_INFO, - TCPDIAG_VEGASINFO, - TCPDIAG_CONG, -}; - -#define TCPDIAG_MAX TCPDIAG_CONG - - -/* TCPDIAG_MEM */ - -struct tcpdiag_meminfo -{ - __u32 tcpdiag_rmem; - __u32 tcpdiag_wmem; - __u32 tcpdiag_fmem; - __u32 tcpdiag_tmem; -}; - -/* TCPDIAG_VEGASINFO */ - -struct tcpvegas_info { - __u32 tcpv_enabled; - __u32 tcpv_rttcnt; - __u32 tcpv_rtt; - __u32 tcpv_minrtt; -}; - -#endif /* _TCP_DIAG_H_ */ diff --git a/include/linux/types.h b/include/linux/types.h index dcb13f865df9..2b678c22ca4a 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -123,6 +123,9 @@ typedef __u64 u_int64_t; typedef __s64 int64_t; #endif +/* this is a special 64bit data type that is 8-byte aligned */ +#define aligned_u64 unsigned long long __attribute__((aligned(8))) + /* * The type used for indexing onto a disc or disc partition. * If required, asm/types.h can override it and define diff --git a/include/linux/uinput.h b/include/linux/uinput.h index 4c2c82336d10..84876077027f 100644 --- a/include/linux/uinput.h +++ b/include/linux/uinput.h @@ -42,8 +42,7 @@ struct uinput_request { int code; /* UI_FF_UPLOAD, UI_FF_ERASE */ int retval; - wait_queue_head_t waitq; - int completed; + struct completion done; union { int effect_id; @@ -62,7 +61,7 @@ struct uinput_device { struct uinput_request *requests[UINPUT_NUM_REQUESTS]; wait_queue_head_t requests_waitq; - struct semaphore requests_sem; + spinlock_t requests_lock; }; #endif /* __KERNEL__ */ diff --git a/include/linux/usb.h b/include/linux/usb.h index eb282b581546..724637792996 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -938,17 +938,17 @@ static inline void usb_fill_int_urb (struct urb *urb, } extern void usb_init_urb(struct urb *urb); -extern struct urb *usb_alloc_urb(int iso_packets, int mem_flags); +extern struct urb *usb_alloc_urb(int iso_packets, unsigned mem_flags); extern void usb_free_urb(struct urb *urb); #define usb_put_urb usb_free_urb extern struct urb *usb_get_urb(struct urb *urb); -extern int usb_submit_urb(struct urb *urb, int mem_flags); +extern int usb_submit_urb(struct urb *urb, unsigned mem_flags); extern int usb_unlink_urb(struct urb *urb); extern void usb_kill_urb(struct urb *urb); #define HAVE_USB_BUFFERS void *usb_buffer_alloc (struct usb_device *dev, size_t size, - int mem_flags, dma_addr_t *dma); + unsigned mem_flags, dma_addr_t *dma); void usb_buffer_free (struct usb_device *dev, size_t size, void *addr, dma_addr_t dma); @@ -1055,7 +1055,7 @@ int usb_sg_init ( struct scatterlist *sg, int nents, size_t length, - int mem_flags + unsigned mem_flags ); void usb_sg_cancel (struct usb_sg_request *io); void usb_sg_wait (struct usb_sg_request *io); diff --git a/include/linux/usb_cdc.h b/include/linux/usb_cdc.h index f22d6beecc73..ba617c372455 100644 --- a/include/linux/usb_cdc.h +++ b/include/linux/usb_cdc.h @@ -34,6 +34,7 @@ #define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */ #define USB_CDC_UNION_TYPE 0x06 /* union_desc */ #define USB_CDC_COUNTRY_TYPE 0x07 +#define USB_CDC_NETWORK_TERMINAL_TYPE 0x0a /* network_terminal_desc */ #define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */ #define USB_CDC_WHCM_TYPE 0x11 #define USB_CDC_MDLM_TYPE 0x12 /* mdlm_desc */ @@ -83,6 +84,18 @@ struct usb_cdc_union_desc { /* ... and there could be other slave interfaces */ } __attribute__ ((packed)); +/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */ +struct usb_cdc_network_terminal_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __u8 bEntityId; + __u8 iName; + __u8 bChannelIndex; + __u8 bPhysicalInterface; +} __attribute__ ((packed)); + /* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */ struct usb_cdc_ether_desc { __u8 bLength; diff --git a/include/linux/usb_gadget.h b/include/linux/usb_gadget.h index b00f127cb447..71e608607324 100644 --- a/include/linux/usb_gadget.h +++ b/include/linux/usb_gadget.h @@ -107,18 +107,18 @@ struct usb_ep_ops { int (*disable) (struct usb_ep *ep); struct usb_request *(*alloc_request) (struct usb_ep *ep, - int gfp_flags); + unsigned gfp_flags); void (*free_request) (struct usb_ep *ep, struct usb_request *req); void *(*alloc_buffer) (struct usb_ep *ep, unsigned bytes, - dma_addr_t *dma, int gfp_flags); + dma_addr_t *dma, unsigned gfp_flags); void (*free_buffer) (struct usb_ep *ep, void *buf, dma_addr_t dma, unsigned bytes); // NOTE: on 2.6, drivers may also use dma_map() and // dma_sync_single_*() to directly manage dma overhead. int (*queue) (struct usb_ep *ep, struct usb_request *req, - int gfp_flags); + unsigned gfp_flags); int (*dequeue) (struct usb_ep *ep, struct usb_request *req); int (*set_halt) (struct usb_ep *ep, int value); @@ -214,7 +214,7 @@ usb_ep_disable (struct usb_ep *ep) * Returns the request, or null if one could not be allocated. */ static inline struct usb_request * -usb_ep_alloc_request (struct usb_ep *ep, int gfp_flags) +usb_ep_alloc_request (struct usb_ep *ep, unsigned gfp_flags) { return ep->ops->alloc_request (ep, gfp_flags); } @@ -254,7 +254,7 @@ usb_ep_free_request (struct usb_ep *ep, struct usb_request *req) */ static inline void * usb_ep_alloc_buffer (struct usb_ep *ep, unsigned len, dma_addr_t *dma, - int gfp_flags) + unsigned gfp_flags) { return ep->ops->alloc_buffer (ep, len, dma, gfp_flags); } @@ -330,7 +330,7 @@ usb_ep_free_buffer (struct usb_ep *ep, void *buf, dma_addr_t dma, unsigned len) * reported when the usb peripheral is disconnected. */ static inline int -usb_ep_queue (struct usb_ep *ep, struct usb_request *req, int gfp_flags) +usb_ep_queue (struct usb_ep *ep, struct usb_request *req, unsigned gfp_flags) { return ep->ops->queue (ep, req, gfp_flags); } diff --git a/include/linux/usb_input.h b/include/linux/usb_input.h new file mode 100644 index 000000000000..716e0cc16043 --- /dev/null +++ b/include/linux/usb_input.h @@ -0,0 +1,25 @@ +#ifndef __USB_INPUT_H +#define __USB_INPUT_H + +/* + * Copyright (C) 2005 Dmitry Torokhov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#include <linux/usb.h> +#include <linux/input.h> +#include <asm/byteorder.h> + +static inline void +usb_to_input_id(const struct usb_device *dev, struct input_id *id) +{ + id->bustype = BUS_USB; + id->vendor = le16_to_cpu(dev->descriptor.idVendor); + id->product = le16_to_cpu(dev->descriptor.idProduct); + id->version = le16_to_cpu(dev->descriptor.bcdDevice); +} + +#endif diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h index 6409d9cf5965..b244f69ef682 100644 --- a/include/linux/vmalloc.h +++ b/include/linux/vmalloc.h @@ -10,6 +10,14 @@ #define VM_MAP 0x00000004 /* vmap()ed pages */ /* bits [20..32] reserved for arch specific ioremap internals */ +/* + * Maximum alignment for ioremap() regions. + * Can be overriden by arch-specific value. + */ +#ifndef IOREMAP_MAX_ORDER +#define IOREMAP_MAX_ORDER (7 + PAGE_SHIFT) /* 128 pages */ +#endif + struct vm_struct { void *addr; unsigned long size; diff --git a/include/linux/wanrouter.h b/include/linux/wanrouter.h index 3e89f0f15f49..1b6b76a4eb54 100644 --- a/include/linux/wanrouter.h +++ b/include/linux/wanrouter.h @@ -516,8 +516,7 @@ struct wan_device { /* Public functions available for device drivers */ extern int register_wan_device(struct wan_device *wandev); extern int unregister_wan_device(char *name); -unsigned short wanrouter_type_trans(struct sk_buff *skb, - struct net_device *dev); +__be16 wanrouter_type_trans(struct sk_buff *skb, struct net_device *dev); int wanrouter_encapsulate(struct sk_buff *skb, struct net_device *dev, unsigned short type); diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h index 88ba0d29f8c8..1192ed8f4fe8 100644 --- a/include/linux/watchdog.h +++ b/include/linux/watchdog.h @@ -47,4 +47,14 @@ struct watchdog_info { #define WDIOS_ENABLECARD 0x0002 /* Turn on the watchdog timer */ #define WDIOS_TEMPPANIC 0x0004 /* Kernel panic on temperature trip */ +#ifdef __KERNEL__ + +#ifdef CONFIG_WATCHDOG_NOWAYOUT +#define WATCHDOG_NOWAYOUT 1 +#else +#define WATCHDOG_NOWAYOUT 0 +#endif + +#endif /* __KERNEL__ */ + #endif /* ifndef _LINUX_WATCHDOG_H */ diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h index f0d423300d84..0fb077d68441 100644 --- a/include/linux/xfrm.h +++ b/include/linux/xfrm.h @@ -258,9 +258,27 @@ struct xfrm_usersa_flush { __u8 proto; }; +#ifndef __KERNEL__ +/* backwards compatibility for userspace */ #define XFRMGRP_ACQUIRE 1 #define XFRMGRP_EXPIRE 2 #define XFRMGRP_SA 4 #define XFRMGRP_POLICY 8 +#endif + +enum xfrm_nlgroups { + XFRMNLGRP_NONE, +#define XFRMNLGRP_NONE XFRMNLGRP_NONE + XFRMNLGRP_ACQUIRE, +#define XFRMNLGRP_ACQUIRE XFRMNLGRP_ACQUIRE + XFRMNLGRP_EXPIRE, +#define XFRMNLGRP_EXPIRE XFRMNLGRP_EXPIRE + XFRMNLGRP_SA, +#define XFRMNLGRP_SA XFRMNLGRP_SA + XFRMNLGRP_POLICY, +#define XFRMNLGRP_POLICY XFRMNLGRP_POLICY + __XFRMNLGRP_MAX +}; +#define XFRMNLGRP_MAX (__XFRMNLGRP_MAX - 1) #endif /* _LINUX_XFRM_H */ diff --git a/include/linux/zlib.h b/include/linux/zlib.h index 850076ea14d3..74f7b78c22d2 100644 --- a/include/linux/zlib.h +++ b/include/linux/zlib.h @@ -506,6 +506,11 @@ extern int zlib_deflateReset (z_streamp strm); stream state was inconsistent (such as zalloc or state being NULL). */ +static inline unsigned long deflateBound(unsigned long s) +{ + return s + ((s + 7) >> 3) + ((s + 63) >> 6) + 11; +} + extern int zlib_deflateParams (z_streamp strm, int level, int strategy); /* Dynamically update the compression level and compression strategy. The diff --git a/include/media/audiochip.h b/include/media/audiochip.h index f345a61c3bdb..cd831168fdc1 100644 --- a/include/media/audiochip.h +++ b/include/media/audiochip.h @@ -1,5 +1,5 @@ /* - * $Id: audiochip.h,v 1.3 2005/06/12 04:19:19 mchehab Exp $ + * $Id: audiochip.h,v 1.5 2005/06/16 22:59:16 hhackmann Exp $ */ #ifndef AUDIOCHIP_H @@ -35,5 +35,4 @@ /* misc stuff to pass around config info to i2c chips */ #define AUDC_CONFIG_PINNACLE _IOW('m',32,int) - #endif /* AUDIOCHIP_H */ diff --git a/include/media/id.h b/include/media/id.h index a39a6423914b..801ddef301aa 100644 --- a/include/media/id.h +++ b/include/media/id.h @@ -34,8 +34,3 @@ #ifndef I2C_DRIVERID_SAA6752HS # define I2C_DRIVERID_SAA6752HS I2C_DRIVERID_EXP0+8 #endif - -/* algorithms */ -#ifndef I2C_ALGO_SAA7134 -# define I2C_ALGO_SAA7134 0x090000 -#endif diff --git a/include/media/saa6752hs.h b/include/media/saa6752hs.h index 791bad2b86e9..3b8686ead80d 100644 --- a/include/media/saa6752hs.h +++ b/include/media/saa6752hs.h @@ -18,55 +18,6 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#if 0 /* ndef _SAA6752HS_H */ -#define _SAA6752HS_H - -enum mpeg_video_bitrate_mode { - MPEG_VIDEO_BITRATE_MODE_VBR = 0, /* Variable bitrate */ - MPEG_VIDEO_BITRATE_MODE_CBR = 1, /* Constant bitrate */ - - MPEG_VIDEO_BITRATE_MODE_MAX -}; - -enum mpeg_audio_bitrate { - MPEG_AUDIO_BITRATE_256 = 0, /* 256 kBit/sec */ - MPEG_AUDIO_BITRATE_384 = 1, /* 384 kBit/sec */ - - MPEG_AUDIO_BITRATE_MAX -}; - -enum mpeg_video_format { - MPEG_VIDEO_FORMAT_D1 = 0, - MPEG_VIDEO_FORMAT_2_3_D1 = 1, - MPEG_VIDEO_FORMAT_1_2_D1 = 2, - MPEG_VIDEO_FORMAT_SIF = 3, - - MPEG_VIDEO_FORMAT_MAX -}; - -#define MPEG_VIDEO_TARGET_BITRATE_MAX 27000 -#define MPEG_VIDEO_MAX_BITRATE_MAX 27000 -#define MPEG_TOTAL_BITRATE_MAX 27000 -#define MPEG_PID_MAX ((1 << 14) - 1) - -struct mpeg_params { - enum mpeg_video_bitrate_mode video_bitrate_mode; - unsigned int video_target_bitrate; - unsigned int video_max_bitrate; // only used for VBR - enum mpeg_audio_bitrate audio_bitrate; - unsigned int total_bitrate; - - unsigned int pmt_pid; - unsigned int video_pid; - unsigned int audio_pid; - unsigned int pcr_pid; - - enum mpeg_video_format video_format; -}; - -#define MPEG_SETPARAMS _IOW('6',100,struct mpeg_params) - -#endif // _SAA6752HS_H /* * Local variables: diff --git a/include/media/tuner.h b/include/media/tuner.h index 4794c5632360..eeaa15ddee85 100644 --- a/include/media/tuner.h +++ b/include/media/tuner.h @@ -1,5 +1,5 @@ -/* $Id: tuner.h,v 1.33 2005/06/21 14:58:08 mkrufky Exp $ +/* $Id: tuner.h,v 1.45 2005/07/28 18:41:21 mchehab Exp $ * tuner.h - definition for different tuners @@ -26,8 +26,6 @@ #include <linux/videodev2.h> -#include "id.h" - #define ADDR_UNSET (255) #define TUNER_TEMIC_PAL 0 /* 4002 FH5 (3X 7756, 9483) */ @@ -110,8 +108,8 @@ #define TUNER_TEA5767 62 /* Only FM Radio Tuner */ #define TUNER_PHILIPS_FMD1216ME_MK3 63 - -#define TEA5767_TUNER_NAME "Philips TEA5767HN FM Radio" +#define TUNER_LG_TDVS_H062F 64 /* DViCO FusionHDTV 5 */ +#define TUNER_YMEC_TVF66T5_B_DFF 65 /* Acorp Y878F */ #define NOTUNER 0 #define PAL 1 /* PAL_BG */ @@ -135,19 +133,8 @@ #define TCL 11 #define THOMSON 12 -enum v4l_radio_tuner { - TEA5767_LOW_LO_32768 = 0, - TEA5767_HIGH_LO_32768 = 1, - TEA5767_LOW_LO_13MHz = 2, - TEA5767_HIGH_LO_13MHz = 3, -}; - - -#define TUNER_SET_TYPE _IOW('t',1,int) /* set tuner type */ -#define TUNER_SET_TVFREQ _IOW('t',2,int) /* set tv freq */ -#define TUNER_SET_TYPE_ADDR _IOW('T',3,int) /* set tuner type and I2C addr */ - -#define TDA9887_SET_CONFIG _IOW('t',5,int) +#define TUNER_SET_TYPE_ADDR _IOW('T',3,int) +#define TDA9887_SET_CONFIG _IOW('t',5,int) /* tv card specific */ # define TDA9887_PRESENT (1<<0) @@ -169,25 +156,34 @@ enum v4l_radio_tuner { #define I2C_ADDR_TDA8290 0x4b #define I2C_ADDR_TDA8275 0x61 -struct tuner_addr { - enum v4l2_tuner_type v4l2_tuner; - unsigned int type; +enum tuner_mode { + T_UNINITIALIZED = 0, + T_RADIO = 1 << V4L2_TUNER_RADIO, + T_ANALOG_TV = 1 << V4L2_TUNER_ANALOG_TV, + T_DIGITAL_TV = 1 << V4L2_TUNER_DIGITAL_TV, + T_STANDBY = 1 << 31 +}; + +struct tuner_setup { unsigned short addr; + unsigned int type; + unsigned int mode_mask; }; struct tuner { /* device */ struct i2c_client i2c; - /* state + config */ - unsigned int initialized; unsigned int type; /* chip type */ + + unsigned int mode; + unsigned int mode_mask; /* Combination of allowable modes */ + unsigned int freq; /* keep track of the current settings */ + unsigned int audmode; v4l2_std_id std; - int using_v4l2; - enum v4l2_tuner_type mode; - unsigned int input; + int using_v4l2; /* used by MT2032 */ unsigned int xogc; @@ -197,15 +193,11 @@ struct tuner { unsigned char i2c_easy_mode[2]; unsigned char i2c_set_freq[8]; - /* used to keep track of audmode */ - unsigned int audmode; - /* function ptrs */ void (*tv_freq)(struct i2c_client *c, unsigned int freq); void (*radio_freq)(struct i2c_client *c, unsigned int freq); int (*has_signal)(struct i2c_client *c); int (*is_stereo)(struct i2c_client *c); - int (*set_tuner)(struct i2c_client *c, struct v4l2_tuner *v); }; extern unsigned int tuner_debug; @@ -215,6 +207,7 @@ extern int microtune_init(struct i2c_client *c); extern int tda8290_init(struct i2c_client *c); extern int tea5767_tuner_init(struct i2c_client *c); extern int default_tuner_init(struct i2c_client *c); +extern int tea5767_autodetection(struct i2c_client *c); #define tuner_warn(fmt, arg...) \ dev_printk(KERN_WARNING , &t->i2c.dev , fmt , ## arg) diff --git a/include/media/tveeprom.h b/include/media/tveeprom.h index 5c4fe30e8d1d..854a2c2f105b 100644 --- a/include/media/tveeprom.h +++ b/include/media/tveeprom.h @@ -24,4 +24,3 @@ void tveeprom_hauppauge_analog(struct tveeprom *tvee, unsigned char *eeprom_data); int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len); -int tveeprom_dump(unsigned char *eedata, int len); diff --git a/include/net/act_api.h b/include/net/act_api.h index ed00a995f576..b55eb7c7f033 100644 --- a/include/net/act_api.h +++ b/include/net/act_api.h @@ -63,7 +63,7 @@ struct tc_action_ops __u32 type; /* TBD to match kind */ __u32 capab; /* capabilities includes 4 bit version */ struct module *owner; - int (*act)(struct sk_buff **, struct tc_action *); + int (*act)(struct sk_buff **, struct tc_action *, struct tcf_result *); int (*get_stats)(struct sk_buff *, struct tc_action *); int (*dump)(struct sk_buff *, struct tc_action *,int , int); int (*cleanup)(struct tc_action *, int bind); diff --git a/include/net/addrconf.h b/include/net/addrconf.h index a0ed93672176..750e2508dd90 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -45,6 +45,7 @@ struct prefix_info { #ifdef __KERNEL__ +#include <linux/config.h> #include <linux/netdevice.h> #include <net/if_inet6.h> #include <net/ipv6.h> @@ -238,5 +239,10 @@ static inline int ipv6_addr_is_ll_all_routers(const struct in6_addr *addr) addr->s6_addr32[3] == htonl(0x00000002)); } +#ifdef CONFIG_PROC_FS +extern int if6_proc_init(void); +extern void if6_proc_exit(void); +#endif + #endif #endif diff --git a/include/net/af_unix.h b/include/net/af_unix.h index b60b3846b9d1..b5d785ab4a0e 100644 --- a/include/net/af_unix.h +++ b/include/net/af_unix.h @@ -1,5 +1,11 @@ #ifndef __LINUX_NET_AFUNIX_H #define __LINUX_NET_AFUNIX_H + +#include <linux/config.h> +#include <linux/socket.h> +#include <linux/un.h> +#include <net/sock.h> + extern void unix_inflight(struct file *fp); extern void unix_notinflight(struct file *fp); extern void unix_gc(void); @@ -74,5 +80,14 @@ struct unix_sock { wait_queue_head_t peer_wait; }; #define unix_sk(__sk) ((struct unix_sock *)__sk) + +#ifdef CONFIG_SYSCTL +extern int sysctl_unix_max_dgram_qlen; +extern void unix_sysctl_register(void); +extern void unix_sysctl_unregister(void); +#else +static inline void unix_sysctl_register(void) {} +static inline void unix_sysctl_unregister(void) {} +#endif #endif #endif diff --git a/include/net/arp.h b/include/net/arp.h index a1f09fad6a52..a13e30c35f42 100644 --- a/include/net/arp.h +++ b/include/net/arp.h @@ -11,7 +11,7 @@ extern struct neigh_table arp_tbl; extern void arp_init(void); extern int arp_rcv(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt); + struct packet_type *pt, struct net_device *orig_dev); extern int arp_find(unsigned char *haddr, struct sk_buff *skb); extern int arp_ioctl(unsigned int cmd, void __user *arg); extern void arp_send(int type, int ptype, u32 dest_ip, diff --git a/include/net/ax25.h b/include/net/ax25.h index 828a3a93dda1..926eed543023 100644 --- a/include/net/ax25.h +++ b/include/net/ax25.h @@ -139,11 +139,25 @@ enum { #define AX25_DEF_DS_TIMEOUT (3 * 60 * HZ) /* DAMA timeout 3 minutes */ typedef struct ax25_uid_assoc { - struct ax25_uid_assoc *next; + struct hlist_node uid_node; + atomic_t refcount; uid_t uid; ax25_address call; } ax25_uid_assoc; +#define ax25_uid_for_each(__ax25, node, list) \ + hlist_for_each_entry(__ax25, node, list, uid_node) + +#define ax25_uid_hold(ax25) \ + atomic_inc(&((ax25)->refcount)) + +static inline void ax25_uid_put(ax25_uid_assoc *assoc) +{ + if (atomic_dec_and_test(&assoc->refcount)) { + kfree(assoc); + } +} + typedef struct { ax25_address calls[AX25_MAX_DIGIS]; unsigned char repeated[AX25_MAX_DIGIS]; @@ -302,7 +316,7 @@ extern int ax25_protocol_is_registered(unsigned int); /* ax25_in.c */ extern int ax25_rx_iframe(ax25_cb *, struct sk_buff *); -extern int ax25_kiss_rcv(struct sk_buff *, struct net_device *, struct packet_type *); +extern int ax25_kiss_rcv(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *); /* ax25_ip.c */ extern int ax25_encapsulate(struct sk_buff *, struct net_device *, unsigned short, void *, void *, unsigned int); @@ -376,7 +390,7 @@ extern unsigned long ax25_display_timer(struct timer_list *); /* ax25_uid.c */ extern int ax25_uid_policy; -extern ax25_address *ax25_findbyuid(uid_t); +extern ax25_uid_assoc *ax25_findbyuid(uid_t); extern int ax25_uid_ioctl(int, struct sockaddr_ax25 *); extern struct file_operations ax25_uid_fops; extern void ax25_uid_free(void); diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h index 42a84c53678b..6dfa4a61ffd0 100644 --- a/include/net/bluetooth/bluetooth.h +++ b/include/net/bluetooth/bluetooth.h @@ -57,12 +57,6 @@ #define BT_DBG(fmt, arg...) printk(KERN_INFO "%s: " fmt "\n" , __FUNCTION__ , ## arg) #define BT_ERR(fmt, arg...) printk(KERN_ERR "%s: " fmt "\n" , __FUNCTION__ , ## arg) -#ifdef HCI_DATA_DUMP -#define BT_DMP(buf, len) bt_dump(__FUNCTION__, buf, len) -#else -#define BT_DMP(D...) -#endif - extern struct proc_dir_entry *proc_bt; /* Connection and socket states */ @@ -137,11 +131,12 @@ struct sock *bt_accept_dequeue(struct sock *parent, struct socket *newsock); /* Skb helpers */ struct bt_skb_cb { - int incoming; + __u8 pkt_type; + __u8 incoming; }; #define bt_cb(skb) ((struct bt_skb_cb *)(skb->cb)) -static inline struct sk_buff *bt_skb_alloc(unsigned int len, int how) +static inline struct sk_buff *bt_skb_alloc(unsigned int len, unsigned int __nocast how) { struct sk_buff *skb; @@ -174,8 +169,6 @@ static inline int skb_frags_no(struct sk_buff *skb) return n; } -void bt_dump(char *pref, __u8 *buf, int count); - int bt_err(__u16 code); #endif /* __BLUETOOTH_H */ diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h index 6f0706f4af68..371e7d3f2e6f 100644 --- a/include/net/bluetooth/hci.h +++ b/include/net/bluetooth/hci.h @@ -453,6 +453,15 @@ struct inquiry_info_with_rssi { __u16 clock_offset; __s8 rssi; } __attribute__ ((packed)); +struct inquiry_info_with_rssi_and_pscan_mode { + bdaddr_t bdaddr; + __u8 pscan_rep_mode; + __u8 pscan_period_mode; + __u8 pscan_mode; + __u8 dev_class[3]; + __u16 clock_offset; + __s8 rssi; +} __attribute__ ((packed)); #define HCI_EV_CONN_COMPLETE 0x03 struct hci_ev_conn_complete { @@ -584,6 +593,12 @@ struct hci_ev_clock_offset { __u16 clock_offset; } __attribute__ ((packed)); +#define HCI_EV_PSCAN_REP_MODE 0x20 +struct hci_ev_pscan_rep_mode { + bdaddr_t bdaddr; + __u8 pscan_rep_mode; +} __attribute__ ((packed)); + /* Internal events generated by Bluetooth stack */ #define HCI_EV_STACK_INTERNAL 0xFD struct hci_ev_stack_internal { diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index 6d63a47c731b..7f933f302078 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -404,7 +404,7 @@ static inline int hci_recv_frame(struct sk_buff *skb) bt_cb(skb)->incoming = 1; /* Time stamp */ - do_gettimeofday(&skb->stamp); + __net_timestamp(skb); /* Queue frame for rx task */ skb_queue_tail(&hdev->rx_q, skb); diff --git a/include/net/bluetooth/rfcomm.h b/include/net/bluetooth/rfcomm.h index 13669bad00b3..ffea9d54071f 100644 --- a/include/net/bluetooth/rfcomm.h +++ b/include/net/bluetooth/rfcomm.h @@ -80,9 +80,9 @@ #define RFCOMM_RPN_STOP_15 1 #define RFCOMM_RPN_PARITY_NONE 0x0 -#define RFCOMM_RPN_PARITY_ODD 0x4 -#define RFCOMM_RPN_PARITY_EVEN 0x5 -#define RFCOMM_RPN_PARITY_MARK 0x6 +#define RFCOMM_RPN_PARITY_ODD 0x1 +#define RFCOMM_RPN_PARITY_EVEN 0x3 +#define RFCOMM_RPN_PARITY_MARK 0x5 #define RFCOMM_RPN_PARITY_SPACE 0x7 #define RFCOMM_RPN_FLOW_NONE 0x00 @@ -223,8 +223,14 @@ struct rfcomm_dlc { #define RFCOMM_CFC_DISABLED 0 #define RFCOMM_CFC_ENABLED RFCOMM_MAX_CREDITS +/* ---- RFCOMM SEND RPN ---- */ +int rfcomm_send_rpn(struct rfcomm_session *s, int cr, u8 dlci, + u8 bit_rate, u8 data_bits, u8 stop_bits, + u8 parity, u8 flow_ctrl_settings, + u8 xon_char, u8 xoff_char, u16 param_mask); + /* ---- RFCOMM DLCs (channels) ---- */ -struct rfcomm_dlc *rfcomm_dlc_alloc(int prio); +struct rfcomm_dlc *rfcomm_dlc_alloc(unsigned int __nocast prio); void rfcomm_dlc_free(struct rfcomm_dlc *d); int rfcomm_dlc_open(struct rfcomm_dlc *d, bdaddr_t *src, bdaddr_t *dst, u8 channel); int rfcomm_dlc_close(struct rfcomm_dlc *d, int reason); diff --git a/include/net/datalink.h b/include/net/datalink.h index 5797ba3d2eb5..deb7ca75db48 100644 --- a/include/net/datalink.h +++ b/include/net/datalink.h @@ -9,7 +9,7 @@ struct datalink_proto { unsigned short header_length; int (*rcvfunc)(struct sk_buff *, struct net_device *, - struct packet_type *); + struct packet_type *, struct net_device *); int (*request)(struct datalink_proto *, struct sk_buff *, unsigned char *); struct list_head node; diff --git a/include/net/dn.h b/include/net/dn.h index 5551c46db397..c1dbbd222793 100644 --- a/include/net/dn.h +++ b/include/net/dn.h @@ -3,6 +3,7 @@ #include <linux/dn.h> #include <net/sock.h> +#include <net/tcp.h> #include <asm/byteorder.h> typedef unsigned short dn_address; diff --git a/include/net/icmp.h b/include/net/icmp.h index e5ef0d15fb45..6cdebeee5f96 100644 --- a/include/net/icmp.h +++ b/include/net/icmp.h @@ -57,4 +57,11 @@ static inline struct raw_sock *raw_sk(const struct sock *sk) return (struct raw_sock *)sk; } +extern int sysctl_icmp_echo_ignore_all; +extern int sysctl_icmp_echo_ignore_broadcasts; +extern int sysctl_icmp_ignore_bogus_error_responses; +extern int sysctl_icmp_errors_use_inbound_ifaddr; +extern int sysctl_icmp_ratelimit; +extern int sysctl_icmp_ratemask; + #endif /* _ICMP_H */ diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h index db09580ad14b..dc36b1be6745 100644 --- a/include/net/ieee80211.h +++ b/include/net/ieee80211.h @@ -20,18 +20,9 @@ */ #ifndef IEEE80211_H #define IEEE80211_H - #include <linux/if_ether.h> /* ETH_ALEN */ #include <linux/kernel.h> /* ARRAY_SIZE */ - -#if WIRELESS_EXT < 17 -#define IW_QUAL_QUAL_INVALID 0x10 -#define IW_QUAL_LEVEL_INVALID 0x20 -#define IW_QUAL_NOISE_INVALID 0x40 -#define IW_QUAL_QUAL_UPDATED 0x1 -#define IW_QUAL_LEVEL_UPDATED 0x2 -#define IW_QUAL_NOISE_UPDATED 0x4 -#endif +#include <linux/wireless.h> #define IEEE80211_DATA_LEN 2304 /* Maximum size for the MA-UNITDATA primitive, 802.11 standard section @@ -47,51 +38,22 @@ #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) struct ieee80211_hdr { - u16 frame_ctl; - u16 duration_id; + __le16 frame_ctl; + __le16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; - u16 seq_ctl; + __le16 seq_ctl; u8 addr4[ETH_ALEN]; } __attribute__ ((packed)); struct ieee80211_hdr_3addr { - u16 frame_ctl; - u16 duration_id; + __le16 frame_ctl; + __le16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; - u16 seq_ctl; -} __attribute__ ((packed)); - -enum eap_type { - EAP_PACKET = 0, - EAPOL_START, - EAPOL_LOGOFF, - EAPOL_KEY, - EAPOL_ENCAP_ASF_ALERT -}; - -static const char *eap_types[] = { - [EAP_PACKET] = "EAP-Packet", - [EAPOL_START] = "EAPOL-Start", - [EAPOL_LOGOFF] = "EAPOL-Logoff", - [EAPOL_KEY] = "EAPOL-Key", - [EAPOL_ENCAP_ASF_ALERT] = "EAPOL-Encap-ASF-Alert" -}; - -static inline const char *eap_get_type(int type) -{ - return (type >= ARRAY_SIZE(eap_types)) ? "Unknown" : eap_types[type]; -} - -struct eapol { - u8 snap[6]; - u16 ethertype; - u8 version; - u8 type; - u16 length; + __le16 seq_ctl; } __attribute__ ((packed)); #define IEEE80211_1ADDR_LEN 10 @@ -104,7 +66,7 @@ struct eapol { #define MAX_FRAG_THRESHOLD 2346U /* Frame control field constants */ -#define IEEE80211_FCTL_VERS 0x0002 +#define IEEE80211_FCTL_VERS 0x0003 #define IEEE80211_FCTL_FTYPE 0x000c #define IEEE80211_FCTL_STYPE 0x00f0 #define IEEE80211_FCTL_TODS 0x0100 @@ -112,8 +74,8 @@ struct eapol { #define IEEE80211_FCTL_MOREFRAGS 0x0400 #define IEEE80211_FCTL_RETRY 0x0800 #define IEEE80211_FCTL_PM 0x1000 -#define IEEE80211_FCTL_MOREDATA 0x2000 -#define IEEE80211_FCTL_WEP 0x4000 +#define IEEE80211_FCTL_MOREDATA 0x2000 +#define IEEE80211_FCTL_PROTECTED 0x4000 #define IEEE80211_FCTL_ORDER 0x8000 #define IEEE80211_FTYPE_MGMT 0x0000 @@ -132,6 +94,7 @@ struct eapol { #define IEEE80211_STYPE_DISASSOC 0x00A0 #define IEEE80211_STYPE_AUTH 0x00B0 #define IEEE80211_STYPE_DEAUTH 0x00C0 +#define IEEE80211_STYPE_ACTION 0x00D0 /* control */ #define IEEE80211_STYPE_PSPOLL 0x00A0 @@ -167,8 +130,19 @@ do { if (ieee80211_debug_level & (level)) \ #define IEEE80211_DEBUG(level, fmt, args...) do {} while (0) #endif /* CONFIG_IEEE80211_DEBUG */ + +/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ + +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] + +/* escape_essid() is intended to be used in debug (and possibly error) + * messages. It should never be used for passing essid to user space. */ +const char *escape_essid(const char *essid, u8 essid_len); + + /* - * To use the debug system; + * To use the debug system: * * If you are defining a new debug classification, simply add it to the #define * list here in the form of: @@ -184,11 +158,11 @@ do { if (ieee80211_debug_level & (level)) \ * * To add your debug level to the list of levels seen when you perform * - * % cat /proc/net/ipw/debug_level + * % cat /proc/net/ieee80211/debug_level * - * you simply need to add your entry to the ipw_debug_levels array. + * you simply need to add your entry to the ieee80211_debug_level array. * - * If you do not see debug_level in /proc/net/ipw then you do not have + * If you do not see debug_level in /proc/net/ieee80211 then you do not have * CONFIG_IEEE80211_DEBUG defined in your kernel configuration * */ @@ -199,7 +173,6 @@ do { if (ieee80211_debug_level & (level)) \ #define IEEE80211_DL_STATE (1<<3) #define IEEE80211_DL_MGMT (1<<4) #define IEEE80211_DL_FRAG (1<<5) -#define IEEE80211_DL_EAP (1<<6) #define IEEE80211_DL_DROP (1<<7) #define IEEE80211_DL_TX (1<<8) @@ -214,7 +187,6 @@ do { if (ieee80211_debug_level & (level)) \ #define IEEE80211_DEBUG_STATE(f, a...) IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a) #define IEEE80211_DEBUG_MGMT(f, a...) IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a) #define IEEE80211_DEBUG_FRAG(f, a...) IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a) -#define IEEE80211_DEBUG_EAP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_EAP, f, ## a) #define IEEE80211_DEBUG_DROP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a) #define IEEE80211_DEBUG_TX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a) #define IEEE80211_DEBUG_RX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a) @@ -223,9 +195,9 @@ do { if (ieee80211_debug_level & (level)) \ #include <linux/if_arp.h> /* ARPHRD_ETHER */ #ifndef WIRELESS_SPY -#define WIRELESS_SPY // enable iwspy support +#define WIRELESS_SPY /* enable iwspy support */ #endif -#include <net/iw_handler.h> // new driver API +#include <net/iw_handler.h> /* new driver API */ #ifndef ETH_P_PAE #define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ @@ -252,6 +224,7 @@ struct ieee80211_snap_hdr { #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) +#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS) #define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) #define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) @@ -264,7 +237,7 @@ struct ieee80211_snap_hdr { #define WLAN_AUTH_CHALLENGE_LEN 128 -#define WLAN_CAPABILITY_BSS (1<<0) +#define WLAN_CAPABILITY_ESS (1<<0) #define WLAN_CAPABILITY_IBSS (1<<1) #define WLAN_CAPABILITY_CF_POLLABLE (1<<2) #define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) @@ -272,34 +245,72 @@ struct ieee80211_snap_hdr { #define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) #define WLAN_CAPABILITY_PBCC (1<<6) #define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) +#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8) +#define WLAN_CAPABILITY_SHORT_SLOT_TIME (1<<10) +#define WLAN_CAPABILITY_OSSS_OFDM (1<<13) /* Status codes */ -#define WLAN_STATUS_SUCCESS 0 -#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 -#define WLAN_STATUS_CAPS_UNSUPPORTED 10 -#define WLAN_STATUS_REASSOC_NO_ASSOC 11 -#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 -#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 -#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 -#define WLAN_STATUS_CHALLENGE_FAIL 15 -#define WLAN_STATUS_AUTH_TIMEOUT 16 -#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 -#define WLAN_STATUS_ASSOC_DENIED_RATES 18 -/* 802.11b */ -#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 -#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 -#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 +enum ieee80211_statuscode { + WLAN_STATUS_SUCCESS = 0, + WLAN_STATUS_UNSPECIFIED_FAILURE = 1, + WLAN_STATUS_CAPS_UNSUPPORTED = 10, + WLAN_STATUS_REASSOC_NO_ASSOC = 11, + WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12, + WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13, + WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14, + WLAN_STATUS_CHALLENGE_FAIL = 15, + WLAN_STATUS_AUTH_TIMEOUT = 16, + WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17, + WLAN_STATUS_ASSOC_DENIED_RATES = 18, + /* 802.11b */ + WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19, + WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20, + WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21, + /* 802.11h */ + WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22, + WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23, + WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24, + /* 802.11g */ + WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25, + WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26, + /* 802.11i */ + WLAN_STATUS_INVALID_IE = 40, + WLAN_STATUS_INVALID_GROUP_CIPHER = 41, + WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42, + WLAN_STATUS_INVALID_AKMP = 43, + WLAN_STATUS_UNSUPP_RSN_VERSION = 44, + WLAN_STATUS_INVALID_RSN_IE_CAP = 45, + WLAN_STATUS_CIPHER_SUITE_REJECTED = 46, +}; /* Reason codes */ -#define WLAN_REASON_UNSPECIFIED 1 -#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 -#define WLAN_REASON_DEAUTH_LEAVING 3 -#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 -#define WLAN_REASON_DISASSOC_AP_BUSY 5 -#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 -#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 -#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 -#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +enum ieee80211_reasoncode { + WLAN_REASON_UNSPECIFIED = 1, + WLAN_REASON_PREV_AUTH_NOT_VALID = 2, + WLAN_REASON_DEAUTH_LEAVING = 3, + WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4, + WLAN_REASON_DISASSOC_AP_BUSY = 5, + WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6, + WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7, + WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8, + WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9, + /* 802.11h */ + WLAN_REASON_DISASSOC_BAD_POWER = 10, + WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11, + /* 802.11i */ + WLAN_REASON_INVALID_IE = 13, + WLAN_REASON_MIC_FAILURE = 14, + WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15, + WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16, + WLAN_REASON_IE_DIFFERENT = 17, + WLAN_REASON_INVALID_GROUP_CIPHER = 18, + WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19, + WLAN_REASON_INVALID_AKMP = 20, + WLAN_REASON_UNSUPP_RSN_VERSION = 21, + WLAN_REASON_INVALID_RSN_IE_CAP = 22, + WLAN_REASON_IEEE8021X_FAILED = 23, + WLAN_REASON_CIPHER_SUITE_REJECTED = 24, +}; #define IEEE80211_STATMASK_SIGNAL (1<<0) @@ -426,9 +437,7 @@ struct ieee80211_stats { struct ieee80211_device; -#if 0 /* for later */ #include "ieee80211_crypt.h" -#endif #define SEC_KEY_1 (1<<0) #define SEC_KEY_2 (1<<1) @@ -480,17 +489,34 @@ Total: 28-2340 bytes #define BEACON_PROBE_SSID_ID_POSITION 12 /* Management Frame Information Element Types */ -#define MFIE_TYPE_SSID 0 -#define MFIE_TYPE_RATES 1 -#define MFIE_TYPE_FH_SET 2 -#define MFIE_TYPE_DS_SET 3 -#define MFIE_TYPE_CF_SET 4 -#define MFIE_TYPE_TIM 5 -#define MFIE_TYPE_IBSS_SET 6 -#define MFIE_TYPE_CHALLENGE 16 -#define MFIE_TYPE_RSN 48 -#define MFIE_TYPE_RATES_EX 50 -#define MFIE_TYPE_GENERIC 221 +enum ieee80211_mfie { + MFIE_TYPE_SSID = 0, + MFIE_TYPE_RATES = 1, + MFIE_TYPE_FH_SET = 2, + MFIE_TYPE_DS_SET = 3, + MFIE_TYPE_CF_SET = 4, + MFIE_TYPE_TIM = 5, + MFIE_TYPE_IBSS_SET = 6, + MFIE_TYPE_COUNTRY = 7, + MFIE_TYPE_HOP_PARAMS = 8, + MFIE_TYPE_HOP_TABLE = 9, + MFIE_TYPE_REQUEST = 10, + MFIE_TYPE_CHALLENGE = 16, + MFIE_TYPE_POWER_CONSTRAINT = 32, + MFIE_TYPE_POWER_CAPABILITY = 33, + MFIE_TYPE_TPC_REQUEST = 34, + MFIE_TYPE_TPC_REPORT = 35, + MFIE_TYPE_SUPP_CHANNELS = 36, + MFIE_TYPE_CSA = 37, + MFIE_TYPE_MEASURE_REQUEST = 38, + MFIE_TYPE_MEASURE_REPORT = 39, + MFIE_TYPE_QUIET = 40, + MFIE_TYPE_IBSS_DFS = 41, + MFIE_TYPE_ERP_INFO = 42, + MFIE_TYPE_RSN = 48, + MFIE_TYPE_RATES_EX = 50, + MFIE_TYPE_GENERIC = 221, +}; struct ieee80211_info_element_hdr { u8 id; @@ -522,9 +548,9 @@ struct ieee80211_info_element { struct ieee80211_authentication { struct ieee80211_hdr_3addr header; - u16 algorithm; - u16 transaction; - u16 status; + __le16 algorithm; + __le16 transaction; + __le16 status; struct ieee80211_info_element info_element; } __attribute__ ((packed)); @@ -532,23 +558,23 @@ struct ieee80211_authentication { struct ieee80211_probe_response { struct ieee80211_hdr_3addr header; u32 time_stamp[2]; - u16 beacon_interval; - u16 capability; + __le16 beacon_interval; + __le16 capability; struct ieee80211_info_element info_element; } __attribute__ ((packed)); struct ieee80211_assoc_request_frame { - u16 capability; - u16 listen_interval; + __le16 capability; + __le16 listen_interval; u8 current_ap[ETH_ALEN]; struct ieee80211_info_element info_element; } __attribute__ ((packed)); struct ieee80211_assoc_response_frame { struct ieee80211_hdr_3addr header; - u16 capability; - u16 status; - u16 aid; + __le16 capability; + __le16 status; + __le16 aid; struct ieee80211_info_element info_element; /* supported rates */ } __attribute__ ((packed)); @@ -563,7 +589,7 @@ struct ieee80211_txb { }; -/* SWEEP TABLE ENTRIES NUMBER*/ +/* SWEEP TABLE ENTRIES NUMBER */ #define MAX_SWEEP_TAB_ENTRIES 42 #define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 /* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs @@ -624,8 +650,6 @@ enum ieee80211_state { #define DEFAULT_MAX_SCAN_AGE (15 * HZ) #define DEFAULT_FTS 2346 -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] #define CFG_IEEE80211_RESERVE_FCS (1<<0) @@ -793,8 +817,6 @@ extern struct net_device *alloc_ieee80211(int sizeof_priv); extern int ieee80211_set_encryption(struct ieee80211_device *ieee); /* ieee80211_tx.c */ - - extern int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev); extern void ieee80211_txb_free(struct ieee80211_txb *); @@ -807,7 +829,7 @@ extern void ieee80211_rx_mgt(struct ieee80211_device *ieee, struct ieee80211_hdr *header, struct ieee80211_rx_stats *stats); -/* iee80211_wx.c */ +/* ieee80211_wx.c */ extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee, struct iw_request_info *info, union iwreq_data *wrqu, char *key); @@ -829,28 +851,5 @@ extern inline int ieee80211_get_scans(struct ieee80211_device *ieee) return ieee->scans; } -static inline const char *escape_essid(const char *essid, u8 essid_len) { - static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; - const char *s = essid; - char *d = escaped; - - if (ieee80211_is_empty_essid(essid, essid_len)) { - memcpy(escaped, "<hidden>", sizeof("<hidden>")); - return escaped; - } - - essid_len = min(essid_len, (u8)IW_ESSID_MAX_SIZE); - while (essid_len--) { - if (*s == '\0') { - *d++ = '\\'; - *d++ = '0'; - s++; - } else { - *d++ = *s++; - } - } - *d = '\0'; - return escaped; -} #endif /* IEEE80211_H */ diff --git a/include/net/ieee80211_crypt.h b/include/net/ieee80211_crypt.h new file mode 100644 index 000000000000..b58a3bcc0dc0 --- /dev/null +++ b/include/net/ieee80211_crypt.h @@ -0,0 +1,86 @@ +/* + * Original code based on Host AP (software wireless LAN access point) driver + * for Intersil Prism2/2.5/3. + * + * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + * <jkmaline@cc.hut.fi> + * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + * + * Adaption to a generic IEEE 802.11 stack by James Ketrenos + * <jketreno@linux.intel.com> + * + * Copyright (c) 2004, Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +/* + * This file defines the interface to the ieee80211 crypto module. + */ +#ifndef IEEE80211_CRYPT_H +#define IEEE80211_CRYPT_H + +#include <linux/skbuff.h> + +struct ieee80211_crypto_ops { + const char *name; + + /* init new crypto context (e.g., allocate private data space, + * select IV, etc.); returns NULL on failure or pointer to allocated + * private data on success */ + void * (*init)(int keyidx); + + /* deinitialize crypto context and free allocated private data */ + void (*deinit)(void *priv); + + /* encrypt/decrypt return < 0 on error or >= 0 on success. The return + * value from decrypt_mpdu is passed as the keyidx value for + * decrypt_msdu. skb must have enough head and tail room for the + * encryption; if not, error will be returned; these functions are + * called for all MPDUs (i.e., fragments). + */ + int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); + int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); + + /* These functions are called for full MSDUs, i.e. full frames. + * These can be NULL if full MSDU operations are not needed. */ + int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv); + int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len, + void *priv); + + int (*set_key)(void *key, int len, u8 *seq, void *priv); + int (*get_key)(void *key, int len, u8 *seq, void *priv); + + /* procfs handler for printing out key information and possible + * statistics */ + char * (*print_stats)(char *p, void *priv); + + /* maximum number of bytes added by encryption; encrypt buf is + * allocated with extra_prefix_len bytes, copy of in_buf, and + * extra_postfix_len; encrypt need not use all this space, but + * the result must start at the beginning of the buffer and correct + * length must be returned */ + int extra_prefix_len, extra_postfix_len; + + struct module *owner; +}; + +struct ieee80211_crypt_data { + struct list_head list; /* delayed deletion list */ + struct ieee80211_crypto_ops *ops; + void *priv; + atomic_t refcnt; +}; + +int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops); +int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops); +struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name); +void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int); +void ieee80211_crypt_deinit_handler(unsigned long); +void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, + struct ieee80211_crypt_data **crypt); + +#endif diff --git a/include/net/inet6_hashtables.h b/include/net/inet6_hashtables.h new file mode 100644 index 000000000000..03df3b157960 --- /dev/null +++ b/include/net/inet6_hashtables.h @@ -0,0 +1,130 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * Authors: Lotsa people, from code originally in tcp + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef _INET6_HASHTABLES_H +#define _INET6_HASHTABLES_H + +#include <linux/config.h> + +#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) +#include <linux/in6.h> +#include <linux/ipv6.h> +#include <linux/types.h> + +#include <net/ipv6.h> + +struct inet_hashinfo; + +/* I have no idea if this is a good hash for v6 or not. -DaveM */ +static inline int inet6_ehashfn(const struct in6_addr *laddr, const u16 lport, + const struct in6_addr *faddr, const u16 fport, + const int ehash_size) +{ + int hashent = (lport ^ fport); + + hashent ^= (laddr->s6_addr32[3] ^ faddr->s6_addr32[3]); + hashent ^= hashent >> 16; + hashent ^= hashent >> 8; + return (hashent & (ehash_size - 1)); +} + +static inline int inet6_sk_ehashfn(const struct sock *sk, const int ehash_size) +{ + const struct inet_sock *inet = inet_sk(sk); + const struct ipv6_pinfo *np = inet6_sk(sk); + const struct in6_addr *laddr = &np->rcv_saddr; + const struct in6_addr *faddr = &np->daddr; + const __u16 lport = inet->num; + const __u16 fport = inet->dport; + return inet6_ehashfn(laddr, lport, faddr, fport, ehash_size); +} + +/* + * Sockets in TCP_CLOSE state are _always_ taken out of the hash, so + * we need not check it for TCP lookups anymore, thanks Alexey. -DaveM + * + * The sockhash lock must be held as a reader here. + */ +static inline struct sock * + __inet6_lookup_established(struct inet_hashinfo *hashinfo, + const struct in6_addr *saddr, + const u16 sport, + const struct in6_addr *daddr, + const u16 hnum, + const int dif) +{ + struct sock *sk; + const struct hlist_node *node; + const __u32 ports = INET_COMBINED_PORTS(sport, hnum); + /* Optimize here for direct hit, only listening connections can + * have wildcards anyways. + */ + const int hash = inet6_ehashfn(daddr, hnum, saddr, sport, + hashinfo->ehash_size); + struct inet_ehash_bucket *head = &hashinfo->ehash[hash]; + + read_lock(&head->lock); + sk_for_each(sk, node, &head->chain) { + /* For IPV6 do the cheaper port and family tests first. */ + if (INET6_MATCH(sk, saddr, daddr, ports, dif)) + goto hit; /* You sunk my battleship! */ + } + /* Must check for a TIME_WAIT'er before going to listener hash. */ + sk_for_each(sk, node, &(head + hashinfo->ehash_size)->chain) { + const struct inet_timewait_sock *tw = inet_twsk(sk); + + if(*((__u32 *)&(tw->tw_dport)) == ports && + sk->sk_family == PF_INET6) { + const struct tcp6_timewait_sock *tcp6tw = tcp6_twsk(sk); + + if (ipv6_addr_equal(&tcp6tw->tw_v6_daddr, saddr) && + ipv6_addr_equal(&tcp6tw->tw_v6_rcv_saddr, daddr) && + (!sk->sk_bound_dev_if || sk->sk_bound_dev_if == dif)) + goto hit; + } + } + read_unlock(&head->lock); + return NULL; + +hit: + sock_hold(sk); + read_unlock(&head->lock); + return sk; +} + +extern struct sock *inet6_lookup_listener(struct inet_hashinfo *hashinfo, + const struct in6_addr *daddr, + const unsigned short hnum, + const int dif); + +static inline struct sock *__inet6_lookup(struct inet_hashinfo *hashinfo, + const struct in6_addr *saddr, + const u16 sport, + const struct in6_addr *daddr, + const u16 hnum, + const int dif) +{ + struct sock *sk = __inet6_lookup_established(hashinfo, saddr, sport, + daddr, hnum, dif); + if (sk) + return sk; + + return inet6_lookup_listener(hashinfo, daddr, hnum, dif); +} + +extern struct sock *inet6_lookup(struct inet_hashinfo *hashinfo, + const struct in6_addr *saddr, const u16 sport, + const struct in6_addr *daddr, const u16 dport, + const int dif); +#endif /* defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) */ +#endif /* _INET6_HASHTABLES_H */ diff --git a/include/net/inet_common.h b/include/net/inet_common.h index fbc1f4d140d8..f943306ce5ff 100644 --- a/include/net/inet_common.h +++ b/include/net/inet_common.h @@ -8,6 +8,11 @@ extern struct proto_ops inet_dgram_ops; * INET4 prototypes used by INET6 */ +struct msghdr; +struct sock; +struct sockaddr; +struct socket; + extern void inet_remove_sock(struct sock *sk1); extern void inet_put_sock(unsigned short num, struct sock *sk); @@ -29,7 +34,6 @@ extern unsigned int inet_poll(struct file * file, struct socket *sock, struct p extern int inet_listen(struct socket *sock, int backlog); extern void inet_sock_destruct(struct sock *sk); -extern atomic_t inet_sock_nr; extern int inet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len); diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h new file mode 100644 index 000000000000..651f824c1008 --- /dev/null +++ b/include/net/inet_connection_sock.h @@ -0,0 +1,276 @@ +/* + * NET Generic infrastructure for INET connection oriented protocols. + * + * Definitions for inet_connection_sock + * + * Authors: Many people, see the TCP sources + * + * From code originally in TCP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef _INET_CONNECTION_SOCK_H +#define _INET_CONNECTION_SOCK_H + +#include <linux/ip.h> +#include <linux/string.h> +#include <linux/timer.h> +#include <net/request_sock.h> + +#define INET_CSK_DEBUG 1 + +/* Cancel timers, when they are not required. */ +#undef INET_CSK_CLEAR_TIMERS + +struct inet_bind_bucket; +struct inet_hashinfo; +struct tcp_congestion_ops; + +/** inet_connection_sock - INET connection oriented sock + * + * @icsk_accept_queue: FIFO of established children + * @icsk_bind_hash: Bind node + * @icsk_timeout: Timeout + * @icsk_retransmit_timer: Resend (no ack) + * @icsk_rto: Retransmit timeout + * @icsk_ca_ops Pluggable congestion control hook + * @icsk_ca_state: Congestion control state + * @icsk_retransmits: Number of unrecovered [RTO] timeouts + * @icsk_pending: Scheduled timer event + * @icsk_backoff: Backoff + * @icsk_syn_retries: Number of allowed SYN (or equivalent) retries + * @icsk_probes_out: unanswered 0 window probes + * @icsk_ack: Delayed ACK control data + */ +struct inet_connection_sock { + /* inet_sock has to be the first member! */ + struct inet_sock icsk_inet; + struct request_sock_queue icsk_accept_queue; + struct inet_bind_bucket *icsk_bind_hash; + unsigned long icsk_timeout; + struct timer_list icsk_retransmit_timer; + struct timer_list icsk_delack_timer; + __u32 icsk_rto; + struct tcp_congestion_ops *icsk_ca_ops; + __u8 icsk_ca_state; + __u8 icsk_retransmits; + __u8 icsk_pending; + __u8 icsk_backoff; + __u8 icsk_syn_retries; + __u8 icsk_probes_out; + /* 2 BYTES HOLE, TRY TO PACK! */ + struct { + __u8 pending; /* ACK is pending */ + __u8 quick; /* Scheduled number of quick acks */ + __u8 pingpong; /* The session is interactive */ + __u8 blocked; /* Delayed ACK was blocked by socket lock */ + __u32 ato; /* Predicted tick of soft clock */ + unsigned long timeout; /* Currently scheduled timeout */ + __u32 lrcvtime; /* timestamp of last received data packet */ + __u16 last_seg_size; /* Size of last incoming segment */ + __u16 rcv_mss; /* MSS used for delayed ACK decisions */ + } icsk_ack; + u32 icsk_ca_priv[16]; +#define ICSK_CA_PRIV_SIZE (16 * sizeof(u32)) +}; + +#define ICSK_TIME_RETRANS 1 /* Retransmit timer */ +#define ICSK_TIME_DACK 2 /* Delayed ack timer */ +#define ICSK_TIME_PROBE0 3 /* Zero window probe timer */ +#define ICSK_TIME_KEEPOPEN 4 /* Keepalive timer */ + +static inline struct inet_connection_sock *inet_csk(const struct sock *sk) +{ + return (struct inet_connection_sock *)sk; +} + +static inline void *inet_csk_ca(const struct sock *sk) +{ + return (void *)inet_csk(sk)->icsk_ca_priv; +} + +extern struct sock *inet_csk_clone(struct sock *sk, + const struct request_sock *req, + const unsigned int __nocast priority); + +enum inet_csk_ack_state_t { + ICSK_ACK_SCHED = 1, + ICSK_ACK_TIMER = 2, + ICSK_ACK_PUSHED = 4 +}; + +extern void inet_csk_init_xmit_timers(struct sock *sk, + void (*retransmit_handler)(unsigned long), + void (*delack_handler)(unsigned long), + void (*keepalive_handler)(unsigned long)); +extern void inet_csk_clear_xmit_timers(struct sock *sk); + +static inline void inet_csk_schedule_ack(struct sock *sk) +{ + inet_csk(sk)->icsk_ack.pending |= ICSK_ACK_SCHED; +} + +static inline int inet_csk_ack_scheduled(const struct sock *sk) +{ + return inet_csk(sk)->icsk_ack.pending & ICSK_ACK_SCHED; +} + +static inline void inet_csk_delack_init(struct sock *sk) +{ + memset(&inet_csk(sk)->icsk_ack, 0, sizeof(inet_csk(sk)->icsk_ack)); +} + +extern void inet_csk_delete_keepalive_timer(struct sock *sk); +extern void inet_csk_reset_keepalive_timer(struct sock *sk, unsigned long timeout); + +#ifdef INET_CSK_DEBUG +extern const char inet_csk_timer_bug_msg[]; +#endif + +static inline void inet_csk_clear_xmit_timer(struct sock *sk, const int what) +{ + struct inet_connection_sock *icsk = inet_csk(sk); + + if (what == ICSK_TIME_RETRANS || what == ICSK_TIME_PROBE0) { + icsk->icsk_pending = 0; +#ifdef INET_CSK_CLEAR_TIMERS + sk_stop_timer(sk, &icsk->icsk_retransmit_timer); +#endif + } else if (what == ICSK_TIME_DACK) { + icsk->icsk_ack.blocked = icsk->icsk_ack.pending = 0; +#ifdef INET_CSK_CLEAR_TIMERS + sk_stop_timer(sk, &icsk->icsk_delack_timer); +#endif + } +#ifdef INET_CSK_DEBUG + else { + pr_debug("%s", inet_csk_timer_bug_msg); + } +#endif +} + +/* + * Reset the retransmission timer + */ +static inline void inet_csk_reset_xmit_timer(struct sock *sk, const int what, + unsigned long when, + const unsigned long max_when) +{ + struct inet_connection_sock *icsk = inet_csk(sk); + + if (when > max_when) { +#ifdef INET_CSK_DEBUG + pr_debug("reset_xmit_timer: sk=%p %d when=0x%lx, caller=%p\n", + sk, what, when, current_text_addr()); +#endif + when = max_when; + } + + if (what == ICSK_TIME_RETRANS || what == ICSK_TIME_PROBE0) { + icsk->icsk_pending = what; + icsk->icsk_timeout = jiffies + when; + sk_reset_timer(sk, &icsk->icsk_retransmit_timer, icsk->icsk_timeout); + } else if (what == ICSK_TIME_DACK) { + icsk->icsk_ack.pending |= ICSK_ACK_TIMER; + icsk->icsk_ack.timeout = jiffies + when; + sk_reset_timer(sk, &icsk->icsk_delack_timer, icsk->icsk_ack.timeout); + } +#ifdef INET_CSK_DEBUG + else { + pr_debug("%s", inet_csk_timer_bug_msg); + } +#endif +} + +extern struct sock *inet_csk_accept(struct sock *sk, int flags, int *err); + +extern struct request_sock *inet_csk_search_req(const struct sock *sk, + struct request_sock ***prevp, + const __u16 rport, + const __u32 raddr, + const __u32 laddr); +extern int inet_csk_get_port(struct inet_hashinfo *hashinfo, + struct sock *sk, unsigned short snum); + +extern struct dst_entry* inet_csk_route_req(struct sock *sk, + const struct request_sock *req); + +static inline void inet_csk_reqsk_queue_add(struct sock *sk, + struct request_sock *req, + struct sock *child) +{ + reqsk_queue_add(&inet_csk(sk)->icsk_accept_queue, req, sk, child); +} + +extern void inet_csk_reqsk_queue_hash_add(struct sock *sk, + struct request_sock *req, + const unsigned timeout); + +static inline void inet_csk_reqsk_queue_removed(struct sock *sk, + struct request_sock *req) +{ + if (reqsk_queue_removed(&inet_csk(sk)->icsk_accept_queue, req) == 0) + inet_csk_delete_keepalive_timer(sk); +} + +static inline void inet_csk_reqsk_queue_added(struct sock *sk, + const unsigned long timeout) +{ + if (reqsk_queue_added(&inet_csk(sk)->icsk_accept_queue) == 0) + inet_csk_reset_keepalive_timer(sk, timeout); +} + +static inline int inet_csk_reqsk_queue_len(const struct sock *sk) +{ + return reqsk_queue_len(&inet_csk(sk)->icsk_accept_queue); +} + +static inline int inet_csk_reqsk_queue_young(const struct sock *sk) +{ + return reqsk_queue_len_young(&inet_csk(sk)->icsk_accept_queue); +} + +static inline int inet_csk_reqsk_queue_is_full(const struct sock *sk) +{ + return reqsk_queue_is_full(&inet_csk(sk)->icsk_accept_queue); +} + +static inline void inet_csk_reqsk_queue_unlink(struct sock *sk, + struct request_sock *req, + struct request_sock **prev) +{ + reqsk_queue_unlink(&inet_csk(sk)->icsk_accept_queue, req, prev); +} + +static inline void inet_csk_reqsk_queue_drop(struct sock *sk, + struct request_sock *req, + struct request_sock **prev) +{ + inet_csk_reqsk_queue_unlink(sk, req, prev); + inet_csk_reqsk_queue_removed(sk, req); + reqsk_free(req); +} + +extern void inet_csk_reqsk_queue_prune(struct sock *parent, + const unsigned long interval, + const unsigned long timeout, + const unsigned long max_rto); + +extern void inet_csk_destroy_sock(struct sock *sk); + +/* + * LISTEN is a special case for poll.. + */ +static inline unsigned int inet_csk_listen_poll(const struct sock *sk) +{ + return !reqsk_queue_empty(&inet_csk(sk)->icsk_accept_queue) ? + (POLLIN | POLLRDNORM) : 0; +} + +extern int inet_csk_listen_start(struct sock *sk, const int nr_table_entries); +extern void inet_csk_listen_stop(struct sock *sk); + +#endif /* _INET_CONNECTION_SOCK_H */ diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h new file mode 100644 index 000000000000..646b6ea7fe26 --- /dev/null +++ b/include/net/inet_hashtables.h @@ -0,0 +1,427 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * Authors: Lotsa people, from code originally in tcp + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef _INET_HASHTABLES_H +#define _INET_HASHTABLES_H + +#include <linux/config.h> + +#include <linux/interrupt.h> +#include <linux/ipv6.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/socket.h> +#include <linux/spinlock.h> +#include <linux/types.h> +#include <linux/wait.h> + +#include <net/inet_connection_sock.h> +#include <net/route.h> +#include <net/sock.h> +#include <net/tcp_states.h> + +#include <asm/atomic.h> +#include <asm/byteorder.h> + +/* This is for all connections with a full identity, no wildcards. + * New scheme, half the table is for TIME_WAIT, the other half is + * for the rest. I'll experiment with dynamic table growth later. + */ +struct inet_ehash_bucket { + rwlock_t lock; + struct hlist_head chain; +} __attribute__((__aligned__(8))); + +/* There are a few simple rules, which allow for local port reuse by + * an application. In essence: + * + * 1) Sockets bound to different interfaces may share a local port. + * Failing that, goto test 2. + * 2) If all sockets have sk->sk_reuse set, and none of them are in + * TCP_LISTEN state, the port may be shared. + * Failing that, goto test 3. + * 3) If all sockets are bound to a specific inet_sk(sk)->rcv_saddr local + * address, and none of them are the same, the port may be + * shared. + * Failing this, the port cannot be shared. + * + * The interesting point, is test #2. This is what an FTP server does + * all day. To optimize this case we use a specific flag bit defined + * below. As we add sockets to a bind bucket list, we perform a + * check of: (newsk->sk_reuse && (newsk->sk_state != TCP_LISTEN)) + * As long as all sockets added to a bind bucket pass this test, + * the flag bit will be set. + * The resulting situation is that tcp_v[46]_verify_bind() can just check + * for this flag bit, if it is set and the socket trying to bind has + * sk->sk_reuse set, we don't even have to walk the owners list at all, + * we return that it is ok to bind this socket to the requested local port. + * + * Sounds like a lot of work, but it is worth it. In a more naive + * implementation (ie. current FreeBSD etc.) the entire list of ports + * must be walked for each data port opened by an ftp server. Needless + * to say, this does not scale at all. With a couple thousand FTP + * users logged onto your box, isn't it nice to know that new data + * ports are created in O(1) time? I thought so. ;-) -DaveM + */ +struct inet_bind_bucket { + unsigned short port; + signed short fastreuse; + struct hlist_node node; + struct hlist_head owners; +}; + +#define inet_bind_bucket_for_each(tb, node, head) \ + hlist_for_each_entry(tb, node, head, node) + +struct inet_bind_hashbucket { + spinlock_t lock; + struct hlist_head chain; +}; + +/* This is for listening sockets, thus all sockets which possess wildcards. */ +#define INET_LHTABLE_SIZE 32 /* Yes, really, this is all you need. */ + +struct inet_hashinfo { + /* This is for sockets with full identity only. Sockets here will + * always be without wildcards and will have the following invariant: + * + * TCP_ESTABLISHED <= sk->sk_state < TCP_CLOSE + * + * First half of the table is for sockets not in TIME_WAIT, second half + * is for TIME_WAIT sockets only. + */ + struct inet_ehash_bucket *ehash; + + /* Ok, let's try this, I give up, we do need a local binding + * TCP hash as well as the others for fast bind/connect. + */ + struct inet_bind_hashbucket *bhash; + + int bhash_size; + int ehash_size; + + /* All sockets in TCP_LISTEN state will be in here. This is the only + * table where wildcard'd TCP sockets can exist. Hash function here + * is just local port number. + */ + struct hlist_head listening_hash[INET_LHTABLE_SIZE]; + + /* All the above members are written once at bootup and + * never written again _or_ are predominantly read-access. + * + * Now align to a new cache line as all the following members + * are often dirty. + */ + rwlock_t lhash_lock ____cacheline_aligned; + atomic_t lhash_users; + wait_queue_head_t lhash_wait; + spinlock_t portalloc_lock; + kmem_cache_t *bind_bucket_cachep; + int port_rover; +}; + +static inline int inet_ehashfn(const __u32 laddr, const __u16 lport, + const __u32 faddr, const __u16 fport, + const int ehash_size) +{ + int h = (laddr ^ lport) ^ (faddr ^ fport); + h ^= h >> 16; + h ^= h >> 8; + return h & (ehash_size - 1); +} + +static inline int inet_sk_ehashfn(const struct sock *sk, const int ehash_size) +{ + const struct inet_sock *inet = inet_sk(sk); + const __u32 laddr = inet->rcv_saddr; + const __u16 lport = inet->num; + const __u32 faddr = inet->daddr; + const __u16 fport = inet->dport; + + return inet_ehashfn(laddr, lport, faddr, fport, ehash_size); +} + +extern struct inet_bind_bucket * + inet_bind_bucket_create(kmem_cache_t *cachep, + struct inet_bind_hashbucket *head, + const unsigned short snum); +extern void inet_bind_bucket_destroy(kmem_cache_t *cachep, + struct inet_bind_bucket *tb); + +static inline int inet_bhashfn(const __u16 lport, const int bhash_size) +{ + return lport & (bhash_size - 1); +} + +extern void inet_bind_hash(struct sock *sk, struct inet_bind_bucket *tb, + const unsigned short snum); + +/* These can have wildcards, don't try too hard. */ +static inline int inet_lhashfn(const unsigned short num) +{ + return num & (INET_LHTABLE_SIZE - 1); +} + +static inline int inet_sk_listen_hashfn(const struct sock *sk) +{ + return inet_lhashfn(inet_sk(sk)->num); +} + +/* Caller must disable local BH processing. */ +static inline void __inet_inherit_port(struct inet_hashinfo *table, + struct sock *sk, struct sock *child) +{ + const int bhash = inet_bhashfn(inet_sk(child)->num, table->bhash_size); + struct inet_bind_hashbucket *head = &table->bhash[bhash]; + struct inet_bind_bucket *tb; + + spin_lock(&head->lock); + tb = inet_csk(sk)->icsk_bind_hash; + sk_add_bind_node(child, &tb->owners); + inet_csk(child)->icsk_bind_hash = tb; + spin_unlock(&head->lock); +} + +static inline void inet_inherit_port(struct inet_hashinfo *table, + struct sock *sk, struct sock *child) +{ + local_bh_disable(); + __inet_inherit_port(table, sk, child); + local_bh_enable(); +} + +extern void inet_put_port(struct inet_hashinfo *table, struct sock *sk); + +extern void inet_listen_wlock(struct inet_hashinfo *hashinfo); + +/* + * - We may sleep inside this lock. + * - If sleeping is not required (or called from BH), + * use plain read_(un)lock(&inet_hashinfo.lhash_lock). + */ +static inline void inet_listen_lock(struct inet_hashinfo *hashinfo) +{ + /* read_lock synchronizes to candidates to writers */ + read_lock(&hashinfo->lhash_lock); + atomic_inc(&hashinfo->lhash_users); + read_unlock(&hashinfo->lhash_lock); +} + +static inline void inet_listen_unlock(struct inet_hashinfo *hashinfo) +{ + if (atomic_dec_and_test(&hashinfo->lhash_users)) + wake_up(&hashinfo->lhash_wait); +} + +static inline void __inet_hash(struct inet_hashinfo *hashinfo, + struct sock *sk, const int listen_possible) +{ + struct hlist_head *list; + rwlock_t *lock; + + BUG_TRAP(sk_unhashed(sk)); + if (listen_possible && sk->sk_state == TCP_LISTEN) { + list = &hashinfo->listening_hash[inet_sk_listen_hashfn(sk)]; + lock = &hashinfo->lhash_lock; + inet_listen_wlock(hashinfo); + } else { + sk->sk_hashent = inet_sk_ehashfn(sk, hashinfo->ehash_size); + list = &hashinfo->ehash[sk->sk_hashent].chain; + lock = &hashinfo->ehash[sk->sk_hashent].lock; + write_lock(lock); + } + __sk_add_node(sk, list); + sock_prot_inc_use(sk->sk_prot); + write_unlock(lock); + if (listen_possible && sk->sk_state == TCP_LISTEN) + wake_up(&hashinfo->lhash_wait); +} + +static inline void inet_hash(struct inet_hashinfo *hashinfo, struct sock *sk) +{ + if (sk->sk_state != TCP_CLOSE) { + local_bh_disable(); + __inet_hash(hashinfo, sk, 1); + local_bh_enable(); + } +} + +static inline void inet_unhash(struct inet_hashinfo *hashinfo, struct sock *sk) +{ + rwlock_t *lock; + + if (sk_unhashed(sk)) + goto out; + + if (sk->sk_state == TCP_LISTEN) { + local_bh_disable(); + inet_listen_wlock(hashinfo); + lock = &hashinfo->lhash_lock; + } else { + struct inet_ehash_bucket *head = &hashinfo->ehash[sk->sk_hashent]; + lock = &head->lock; + write_lock_bh(&head->lock); + } + + if (__sk_del_node_init(sk)) + sock_prot_dec_use(sk->sk_prot); + write_unlock_bh(lock); +out: + if (sk->sk_state == TCP_LISTEN) + wake_up(&hashinfo->lhash_wait); +} + +static inline int inet_iif(const struct sk_buff *skb) +{ + return ((struct rtable *)skb->dst)->rt_iif; +} + +extern struct sock *__inet_lookup_listener(const struct hlist_head *head, + const u32 daddr, + const unsigned short hnum, + const int dif); + +/* Optimize the common listener case. */ +static inline struct sock * + inet_lookup_listener(struct inet_hashinfo *hashinfo, + const u32 daddr, + const unsigned short hnum, const int dif) +{ + struct sock *sk = NULL; + const struct hlist_head *head; + + read_lock(&hashinfo->lhash_lock); + head = &hashinfo->listening_hash[inet_lhashfn(hnum)]; + if (!hlist_empty(head)) { + const struct inet_sock *inet = inet_sk((sk = __sk_head(head))); + + if (inet->num == hnum && !sk->sk_node.next && + (!inet->rcv_saddr || inet->rcv_saddr == daddr) && + (sk->sk_family == PF_INET || !ipv6_only_sock(sk)) && + !sk->sk_bound_dev_if) + goto sherry_cache; + sk = __inet_lookup_listener(head, daddr, hnum, dif); + } + if (sk) { +sherry_cache: + sock_hold(sk); + } + read_unlock(&hashinfo->lhash_lock); + return sk; +} + +/* Socket demux engine toys. */ +#ifdef __BIG_ENDIAN +#define INET_COMBINED_PORTS(__sport, __dport) \ + (((__u32)(__sport) << 16) | (__u32)(__dport)) +#else /* __LITTLE_ENDIAN */ +#define INET_COMBINED_PORTS(__sport, __dport) \ + (((__u32)(__dport) << 16) | (__u32)(__sport)) +#endif + +#if (BITS_PER_LONG == 64) +#ifdef __BIG_ENDIAN +#define INET_ADDR_COOKIE(__name, __saddr, __daddr) \ + const __u64 __name = (((__u64)(__saddr)) << 32) | ((__u64)(__daddr)); +#else /* __LITTLE_ENDIAN */ +#define INET_ADDR_COOKIE(__name, __saddr, __daddr) \ + const __u64 __name = (((__u64)(__daddr)) << 32) | ((__u64)(__saddr)); +#endif /* __BIG_ENDIAN */ +#define INET_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\ + (((*((__u64 *)&(inet_sk(__sk)->daddr))) == (__cookie)) && \ + ((*((__u32 *)&(inet_sk(__sk)->dport))) == (__ports)) && \ + (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) +#define INET_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\ + (((*((__u64 *)&(inet_twsk(__sk)->tw_daddr))) == (__cookie)) && \ + ((*((__u32 *)&(inet_twsk(__sk)->tw_dport))) == (__ports)) && \ + (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) +#else /* 32-bit arch */ +#define INET_ADDR_COOKIE(__name, __saddr, __daddr) +#define INET_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif) \ + ((inet_sk(__sk)->daddr == (__saddr)) && \ + (inet_sk(__sk)->rcv_saddr == (__daddr)) && \ + ((*((__u32 *)&(inet_sk(__sk)->dport))) == (__ports)) && \ + (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) +#define INET_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif) \ + ((inet_twsk(__sk)->tw_daddr == (__saddr)) && \ + (inet_twsk(__sk)->tw_rcv_saddr == (__daddr)) && \ + ((*((__u32 *)&(inet_twsk(__sk)->tw_dport))) == (__ports)) && \ + (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) +#endif /* 64-bit arch */ + +/* + * Sockets in TCP_CLOSE state are _always_ taken out of the hash, so we need + * not check it for lookups anymore, thanks Alexey. -DaveM + * + * Local BH must be disabled here. + */ +static inline struct sock * + __inet_lookup_established(struct inet_hashinfo *hashinfo, + const u32 saddr, const u16 sport, + const u32 daddr, const u16 hnum, + const int dif) +{ + INET_ADDR_COOKIE(acookie, saddr, daddr) + const __u32 ports = INET_COMBINED_PORTS(sport, hnum); + struct sock *sk; + const struct hlist_node *node; + /* Optimize here for direct hit, only listening connections can + * have wildcards anyways. + */ + const int hash = inet_ehashfn(daddr, hnum, saddr, sport, hashinfo->ehash_size); + struct inet_ehash_bucket *head = &hashinfo->ehash[hash]; + + read_lock(&head->lock); + sk_for_each(sk, node, &head->chain) { + if (INET_MATCH(sk, acookie, saddr, daddr, ports, dif)) + goto hit; /* You sunk my battleship! */ + } + + /* Must check for a TIME_WAIT'er before going to listener hash. */ + sk_for_each(sk, node, &(head + hashinfo->ehash_size)->chain) { + if (INET_TW_MATCH(sk, acookie, saddr, daddr, ports, dif)) + goto hit; + } + sk = NULL; +out: + read_unlock(&head->lock); + return sk; +hit: + sock_hold(sk); + goto out; +} + +static inline struct sock *__inet_lookup(struct inet_hashinfo *hashinfo, + const u32 saddr, const u16 sport, + const u32 daddr, const u16 hnum, + const int dif) +{ + struct sock *sk = __inet_lookup_established(hashinfo, saddr, sport, daddr, + hnum, dif); + return sk ? : inet_lookup_listener(hashinfo, daddr, hnum, dif); +} + +static inline struct sock *inet_lookup(struct inet_hashinfo *hashinfo, + const u32 saddr, const u16 sport, + const u32 daddr, const u16 dport, + const int dif) +{ + struct sock *sk; + + local_bh_disable(); + sk = __inet_lookup(hashinfo, saddr, sport, daddr, ntohs(dport), dif); + local_bh_enable(); + + return sk; +} +#endif /* _INET_HASHTABLES_H */ diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h new file mode 100644 index 000000000000..3b070352e869 --- /dev/null +++ b/include/net/inet_timewait_sock.h @@ -0,0 +1,219 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * Definitions for a generic INET TIMEWAIT sock + * + * From code originally in net/tcp.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef _INET_TIMEWAIT_SOCK_ +#define _INET_TIMEWAIT_SOCK_ + +#include <linux/config.h> + +#include <linux/ip.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/types.h> +#include <linux/workqueue.h> + +#include <net/sock.h> +#include <net/tcp_states.h> + +#include <asm/atomic.h> + +struct inet_hashinfo; + +#define INET_TWDR_RECYCLE_SLOTS_LOG 5 +#define INET_TWDR_RECYCLE_SLOTS (1 << INET_TWDR_RECYCLE_SLOTS_LOG) + +/* + * If time > 4sec, it is "slow" path, no recycling is required, + * so that we select tick to get range about 4 seconds. + */ +#if HZ <= 16 || HZ > 4096 +# error Unsupported: HZ <= 16 or HZ > 4096 +#elif HZ <= 32 +# define INET_TWDR_RECYCLE_TICK (5 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#elif HZ <= 64 +# define INET_TWDR_RECYCLE_TICK (6 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#elif HZ <= 128 +# define INET_TWDR_RECYCLE_TICK (7 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#elif HZ <= 256 +# define INET_TWDR_RECYCLE_TICK (8 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#elif HZ <= 512 +# define INET_TWDR_RECYCLE_TICK (9 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#elif HZ <= 1024 +# define INET_TWDR_RECYCLE_TICK (10 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#elif HZ <= 2048 +# define INET_TWDR_RECYCLE_TICK (11 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#else +# define INET_TWDR_RECYCLE_TICK (12 + 2 - INET_TWDR_RECYCLE_SLOTS_LOG) +#endif + +/* TIME_WAIT reaping mechanism. */ +#define INET_TWDR_TWKILL_SLOTS 8 /* Please keep this a power of 2. */ + +#define INET_TWDR_TWKILL_QUOTA 100 + +struct inet_timewait_death_row { + /* Short-time timewait calendar */ + int twcal_hand; + int twcal_jiffie; + struct timer_list twcal_timer; + struct hlist_head twcal_row[INET_TWDR_RECYCLE_SLOTS]; + + spinlock_t death_lock; + int tw_count; + int period; + u32 thread_slots; + struct work_struct twkill_work; + struct timer_list tw_timer; + int slot; + struct hlist_head cells[INET_TWDR_TWKILL_SLOTS]; + struct inet_hashinfo *hashinfo; + int sysctl_tw_recycle; + int sysctl_max_tw_buckets; +}; + +extern void inet_twdr_hangman(unsigned long data); +extern void inet_twdr_twkill_work(void *data); +extern void inet_twdr_twcal_tick(unsigned long data); + +#if (BITS_PER_LONG == 64) +#define INET_TIMEWAIT_ADDRCMP_ALIGN_BYTES 8 +#else +#define INET_TIMEWAIT_ADDRCMP_ALIGN_BYTES 4 +#endif + +struct inet_bind_bucket; + +/* + * This is a TIME_WAIT sock. It works around the memory consumption + * problems of sockets in such a state on heavily loaded servers, but + * without violating the protocol specification. + */ +struct inet_timewait_sock { + /* + * Now struct sock also uses sock_common, so please just + * don't add nothing before this first member (__tw_common) --acme + */ + struct sock_common __tw_common; +#define tw_family __tw_common.skc_family +#define tw_state __tw_common.skc_state +#define tw_reuse __tw_common.skc_reuse +#define tw_bound_dev_if __tw_common.skc_bound_dev_if +#define tw_node __tw_common.skc_node +#define tw_bind_node __tw_common.skc_bind_node +#define tw_refcnt __tw_common.skc_refcnt +#define tw_prot __tw_common.skc_prot + volatile unsigned char tw_substate; + /* 3 bits hole, try to pack */ + unsigned char tw_rcv_wscale; + /* Socket demultiplex comparisons on incoming packets. */ + /* these five are in inet_sock */ + __u16 tw_sport; + __u32 tw_daddr __attribute__((aligned(INET_TIMEWAIT_ADDRCMP_ALIGN_BYTES))); + __u32 tw_rcv_saddr; + __u16 tw_dport; + __u16 tw_num; + /* And these are ours. */ + __u8 tw_ipv6only:1; + /* 31 bits hole, try to pack */ + int tw_hashent; + int tw_timeout; + unsigned long tw_ttd; + struct inet_bind_bucket *tw_tb; + struct hlist_node tw_death_node; +}; + +static inline void inet_twsk_add_node(struct inet_timewait_sock *tw, + struct hlist_head *list) +{ + hlist_add_head(&tw->tw_node, list); +} + +static inline void inet_twsk_add_bind_node(struct inet_timewait_sock *tw, + struct hlist_head *list) +{ + hlist_add_head(&tw->tw_bind_node, list); +} + +static inline int inet_twsk_dead_hashed(const struct inet_timewait_sock *tw) +{ + return tw->tw_death_node.pprev != NULL; +} + +static inline void inet_twsk_dead_node_init(struct inet_timewait_sock *tw) +{ + tw->tw_death_node.pprev = NULL; +} + +static inline void __inet_twsk_del_dead_node(struct inet_timewait_sock *tw) +{ + __hlist_del(&tw->tw_death_node); + inet_twsk_dead_node_init(tw); +} + +static inline int inet_twsk_del_dead_node(struct inet_timewait_sock *tw) +{ + if (inet_twsk_dead_hashed(tw)) { + __inet_twsk_del_dead_node(tw); + return 1; + } + return 0; +} + +#define inet_twsk_for_each(tw, node, head) \ + hlist_for_each_entry(tw, node, head, tw_node) + +#define inet_twsk_for_each_inmate(tw, node, jail) \ + hlist_for_each_entry(tw, node, jail, tw_death_node) + +#define inet_twsk_for_each_inmate_safe(tw, node, safe, jail) \ + hlist_for_each_entry_safe(tw, node, safe, jail, tw_death_node) + +static inline struct inet_timewait_sock *inet_twsk(const struct sock *sk) +{ + return (struct inet_timewait_sock *)sk; +} + +static inline u32 inet_rcv_saddr(const struct sock *sk) +{ + return likely(sk->sk_state != TCP_TIME_WAIT) ? + inet_sk(sk)->rcv_saddr : inet_twsk(sk)->tw_rcv_saddr; +} + +static inline void inet_twsk_put(struct inet_timewait_sock *tw) +{ + if (atomic_dec_and_test(&tw->tw_refcnt)) { +#ifdef SOCK_REFCNT_DEBUG + printk(KERN_DEBUG "%s timewait_sock %p released\n", + tw->tw_prot->name, tw); +#endif + kmem_cache_free(tw->tw_prot->twsk_slab, tw); + } +} + +extern struct inet_timewait_sock *inet_twsk_alloc(const struct sock *sk, + const int state); + +extern void __inet_twsk_kill(struct inet_timewait_sock *tw, + struct inet_hashinfo *hashinfo); + +extern void __inet_twsk_hashdance(struct inet_timewait_sock *tw, + struct sock *sk, + struct inet_hashinfo *hashinfo); + +extern void inet_twsk_schedule(struct inet_timewait_sock *tw, + struct inet_timewait_death_row *twdr, + const int timeo, const int timewait_len); +extern void inet_twsk_deschedule(struct inet_timewait_sock *tw, + struct inet_timewait_death_row *twdr); +#endif /* _INET_TIMEWAIT_SOCK_ */ diff --git a/include/net/ip.h b/include/net/ip.h index 32360bbe143f..e4563bbee6ea 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -86,7 +86,7 @@ extern int ip_build_and_send_pkt(struct sk_buff *skb, struct sock *sk, u32 saddr, u32 daddr, struct ip_options *opt); extern int ip_rcv(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt); + struct packet_type *pt, struct net_device *orig_dev); extern int ip_local_deliver(struct sk_buff *skb); extern int ip_mr_input(struct sk_buff *skb); extern int ip_output(struct sk_buff *skb); @@ -140,8 +140,6 @@ struct ip_reply_arg { void ip_send_reply(struct sock *sk, struct sk_buff *skb, struct ip_reply_arg *arg, unsigned int len); -extern int ip_finish_output(struct sk_buff *skb); - struct ipv4_config { int log_martians; @@ -165,6 +163,24 @@ extern int sysctl_local_port_range[2]; extern int sysctl_ip_default_ttl; extern int sysctl_ip_nonlocal_bind; +/* From ip_fragment.c */ +extern int sysctl_ipfrag_high_thresh; +extern int sysctl_ipfrag_low_thresh; +extern int sysctl_ipfrag_time; +extern int sysctl_ipfrag_secret_interval; + +/* From inetpeer.c */ +extern int inet_peer_threshold; +extern int inet_peer_minttl; +extern int inet_peer_maxttl; +extern int inet_peer_gc_mintime; +extern int inet_peer_gc_maxtime; + +/* From ip_output.c */ +extern int sysctl_ip_dynaddr; + +extern void ipfrag_init(void); + #ifdef CONFIG_INET /* The function in 2.2 was invalid, producing wrong result for * check=0xFEFF. It was noticed by Arthur Skawina _year_ ago. --ANK(000625) */ @@ -319,7 +335,10 @@ extern void ip_options_build(struct sk_buff *skb, struct ip_options *opt, u32 da extern int ip_options_echo(struct ip_options *dopt, struct sk_buff *skb); extern void ip_options_fragment(struct sk_buff *skb); extern int ip_options_compile(struct ip_options *opt, struct sk_buff *skb); -extern int ip_options_get(struct ip_options **optp, unsigned char *data, int optlen, int user); +extern int ip_options_get(struct ip_options **optp, + unsigned char *data, int optlen); +extern int ip_options_get_from_user(struct ip_options **optp, + unsigned char __user *data, int optlen); extern void ip_options_undo(struct ip_options * opt); extern void ip_forward_options(struct sk_buff *skb); extern int ip_options_rcv_srr(struct sk_buff *skb); @@ -350,5 +369,10 @@ int ipv4_doint_and_flush_strategy(ctl_table *table, int __user *name, int nlen, void __user *oldval, size_t __user *oldlenp, void __user *newval, size_t newlen, void **context); +#ifdef CONFIG_PROC_FS +extern int ip_misc_proc_init(void); +#endif + +extern struct ctl_table ipv4_table[]; #endif /* _IP_H */ diff --git a/include/net/ip6_route.h b/include/net/ip6_route.h index f920706d526b..1f2e428ca364 100644 --- a/include/net/ip6_route.h +++ b/include/net/ip6_route.h @@ -12,7 +12,6 @@ #include <net/flow.h> #include <net/ip6_fib.h> #include <net/sock.h> -#include <linux/tcp.h> #include <linux/ip.h> #include <linux/ipv6.h> diff --git a/include/net/ip_fib.h b/include/net/ip_fib.h index a4208a336ac0..14de4ebd1211 100644 --- a/include/net/ip_fib.h +++ b/include/net/ip_fib.h @@ -295,4 +295,9 @@ static inline void fib_res_put(struct fib_result *res) #endif } +#ifdef CONFIG_PROC_FS +extern int fib_proc_init(void); +extern void fib_proc_exit(void); +#endif + #endif /* _NET_FIB_H */ diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h index 52da5d26617a..e426641c519f 100644 --- a/include/net/ip_vs.h +++ b/include/net/ip_vs.h @@ -255,7 +255,6 @@ struct ip_vs_daemon_user { #include <asm/atomic.h> /* for struct atomic_t */ #include <linux/netdevice.h> /* for struct neighbour */ #include <net/dst.h> /* for struct dst_entry */ -#include <net/tcp.h> #include <net/udp.h> #include <linux/compiler.h> @@ -959,7 +958,7 @@ static __inline__ int ip_vs_todrop(void) */ #define IP_VS_FWD_METHOD(cp) (cp->flags & IP_VS_CONN_F_FWD_MASK) -extern __inline__ char ip_vs_fwd_tag(struct ip_vs_conn *cp) +static inline char ip_vs_fwd_tag(struct ip_vs_conn *cp) { char fwd; diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 69324465e8b3..3203eaff4bd4 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -104,6 +104,7 @@ struct frag_hdr { #ifdef __KERNEL__ +#include <linux/config.h> #include <net/sock.h> /* sysctls */ @@ -145,7 +146,6 @@ DECLARE_SNMP_STAT(struct udp_mib, udp_stats_in6); #define UDP6_INC_STATS(field) SNMP_INC_STATS(udp_stats_in6, field) #define UDP6_INC_STATS_BH(field) SNMP_INC_STATS_BH(udp_stats_in6, field) #define UDP6_INC_STATS_USER(field) SNMP_INC_STATS_USER(udp_stats_in6, field) -extern atomic_t inet6_sock_nr; int snmp6_register_dev(struct inet6_dev *idev); int snmp6_unregister_dev(struct inet6_dev *idev); @@ -346,7 +346,8 @@ static inline int ipv6_addr_any(const struct in6_addr *a) extern int ipv6_rcv(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt); + struct packet_type *pt, + struct net_device *orig_dev); /* * upper-layer output functions @@ -464,8 +465,38 @@ extern int sysctl_ip6frag_low_thresh; extern int sysctl_ip6frag_time; extern int sysctl_ip6frag_secret_interval; -#endif /* __KERNEL__ */ -#endif /* _NET_IPV6_H */ +extern struct proto_ops inet6_stream_ops; +extern struct proto_ops inet6_dgram_ops; + +extern int ip6_mc_source(int add, int omode, struct sock *sk, + struct group_source_req *pgsr); +extern int ip6_mc_msfilter(struct sock *sk, struct group_filter *gsf); +extern int ip6_mc_msfget(struct sock *sk, struct group_filter *gsf, + struct group_filter __user *optval, + int __user *optlen); + +#ifdef CONFIG_PROC_FS +extern int ac6_proc_init(void); +extern void ac6_proc_exit(void); +extern int raw6_proc_init(void); +extern void raw6_proc_exit(void); +extern int tcp6_proc_init(void); +extern void tcp6_proc_exit(void); +extern int udp6_proc_init(void); +extern void udp6_proc_exit(void); +extern int ipv6_misc_proc_init(void); +extern void ipv6_misc_proc_exit(void); + +extern struct rt6_statistics rt6_stats; +#endif +#ifdef CONFIG_SYSCTL +extern ctl_table ipv6_route_table[]; +extern ctl_table ipv6_icmp_table[]; +extern void ipv6_sysctl_register(void); +extern void ipv6_sysctl_unregister(void); +#endif +#endif /* __KERNEL__ */ +#endif /* _NET_IPV6_H */ diff --git a/include/net/irda/irlan_filter.h b/include/net/irda/irlan_filter.h index 3afeb6c94ea4..492dedaa8ac1 100644 --- a/include/net/irda/irlan_filter.h +++ b/include/net/irda/irlan_filter.h @@ -28,6 +28,6 @@ void irlan_check_command_param(struct irlan_cb *self, char *param, char *value); void irlan_filter_request(struct irlan_cb *self, struct sk_buff *skb); -int irlan_print_filter(struct seq_file *seq, int filter_type); +void irlan_print_filter(struct seq_file *seq, int filter_type); #endif /* IRLAN_FILTER_H */ diff --git a/include/net/llc.h b/include/net/llc.h index c9aed2a8b4e2..71769a5aeef3 100644 --- a/include/net/llc.h +++ b/include/net/llc.h @@ -46,7 +46,8 @@ struct llc_sap { unsigned char f_bit; int (*rcv_func)(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt); + struct packet_type *pt, + struct net_device *orig_dev); struct llc_addr laddr; struct list_head node; struct { @@ -64,7 +65,7 @@ extern rwlock_t llc_sap_list_lock; extern unsigned char llc_station_mac_sa[ETH_ALEN]; extern int llc_rcv(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt); + struct packet_type *pt, struct net_device *orig_dev); extern int llc_mac_hdr_init(struct sk_buff *skb, unsigned char *sa, unsigned char *da); @@ -78,7 +79,8 @@ extern void llc_set_station_handler(void (*handler)(struct sk_buff *skb)); extern struct llc_sap *llc_sap_open(unsigned char lsap, int (*rcv)(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt)); + struct packet_type *pt, + struct net_device *orig_dev)); extern void llc_sap_close(struct llc_sap *sap); extern struct llc_sap *llc_sap_find(unsigned char sap_value); diff --git a/include/net/neighbour.h b/include/net/neighbour.h index 89809891e5ab..34c07731933d 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -363,7 +363,14 @@ __neigh_lookup_errno(struct neigh_table *tbl, const void *pkey, return neigh_create(tbl, pkey, dev); } -#define LOCALLY_ENQUEUED -2 +struct neighbour_cb { + unsigned long sched_next; + unsigned int flags; +}; + +#define LOCALLY_ENQUEUED 0x1 + +#define NEIGH_CB(skb) ((struct neighbour_cb *)(skb)->cb) #endif #endif diff --git a/include/net/p8022.h b/include/net/p8022.h index 3c99a86c3581..42e9fac51b31 100644 --- a/include/net/p8022.h +++ b/include/net/p8022.h @@ -4,7 +4,10 @@ extern struct datalink_proto * register_8022_client(unsigned char type, int (*func)(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt)); + struct packet_type *pt, + struct net_device *orig_dev)); extern void unregister_8022_client(struct datalink_proto *proto); +extern struct datalink_proto *make_8023_client(void); +extern void destroy_8023_client(struct datalink_proto *dl); #endif diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h index 4abda6aec05a..b902d24a3256 100644 --- a/include/net/pkt_cls.h +++ b/include/net/pkt_cls.h @@ -352,10 +352,10 @@ tcf_change_indev(struct tcf_proto *tp, char *indev, struct rtattr *indev_tlv) static inline int tcf_match_indev(struct sk_buff *skb, char *indev) { - if (0 != indev[0]) { - if (NULL == skb->input_dev) + if (indev[0]) { + if (!skb->input_dev) return 0; - else if (0 != strcmp(indev, skb->input_dev->name)) + if (strcmp(indev, skb->input_dev->name)) return 0; } diff --git a/include/net/psnap.h b/include/net/psnap.h index 9c94e8f98b36..b2e01cc3fc8a 100644 --- a/include/net/psnap.h +++ b/include/net/psnap.h @@ -1,7 +1,7 @@ #ifndef _NET_PSNAP_H #define _NET_PSNAP_H -extern struct datalink_proto *register_snap_client(unsigned char *desc, int (*rcvfunc)(struct sk_buff *, struct net_device *, struct packet_type *)); +extern struct datalink_proto *register_snap_client(unsigned char *desc, int (*rcvfunc)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *orig_dev)); extern void unregister_snap_client(struct datalink_proto *proto); #endif diff --git a/include/net/raw.h b/include/net/raw.h index 1c411c45587a..f47917469b12 100644 --- a/include/net/raw.h +++ b/include/net/raw.h @@ -17,10 +17,10 @@ #ifndef _RAW_H #define _RAW_H +#include <linux/config.h> extern struct proto raw_prot; - extern void raw_err(struct sock *, struct sk_buff *, u32 info); extern int raw_rcv(struct sock *, struct sk_buff *); @@ -37,6 +37,11 @@ extern struct sock *__raw_v4_lookup(struct sock *sk, unsigned short num, unsigned long raddr, unsigned long laddr, int dif); -extern void raw_v4_input(struct sk_buff *skb, struct iphdr *iph, int hash); +extern int raw_v4_input(struct sk_buff *skb, struct iphdr *iph, int hash); + +#ifdef CONFIG_PROC_FS +extern int raw_proc_init(void); +extern void raw_proc_exit(void); +#endif #endif /* _RAW_H */ diff --git a/include/net/rawv6.h b/include/net/rawv6.h index 23fd9a6a221a..14476a71725e 100644 --- a/include/net/rawv6.h +++ b/include/net/rawv6.h @@ -7,10 +7,11 @@ extern struct hlist_head raw_v6_htable[RAWV6_HTABLE_SIZE]; extern rwlock_t raw_v6_lock; -extern void ipv6_raw_deliver(struct sk_buff *skb, int nexthdr); +extern int ipv6_raw_deliver(struct sk_buff *skb, int nexthdr); extern struct sock *__raw_v6_lookup(struct sock *sk, unsigned short num, - struct in6_addr *loc_addr, struct in6_addr *rmt_addr); + struct in6_addr *loc_addr, struct in6_addr *rmt_addr, + int dif); extern int rawv6_rcv(struct sock *sk, struct sk_buff *skb); diff --git a/include/net/request_sock.h b/include/net/request_sock.h index 72fd6f5e86b1..b52cc52ffe39 100644 --- a/include/net/request_sock.h +++ b/include/net/request_sock.h @@ -89,6 +89,7 @@ struct listen_sock { int qlen_young; int clock_hand; u32 hash_rnd; + u32 nr_table_entries; struct request_sock *syn_table[0]; }; @@ -96,6 +97,7 @@ struct listen_sock { * * @rskq_accept_head - FIFO head of established children * @rskq_accept_tail - FIFO tail of established children + * @rskq_defer_accept - User waits for some data after accept() * @syn_wait_lock - serializer * * %syn_wait_lock is necessary only to avoid proc interface having to grab the main @@ -111,6 +113,8 @@ struct request_sock_queue { struct request_sock *rskq_accept_head; struct request_sock *rskq_accept_tail; rwlock_t syn_wait_lock; + u8 rskq_defer_accept; + /* 3 bytes hole, try to pack */ struct listen_sock *listen_opt; }; @@ -129,11 +133,13 @@ static inline struct listen_sock *reqsk_queue_yank_listen_sk(struct request_sock return lopt; } -static inline void reqsk_queue_destroy(struct request_sock_queue *queue) +static inline void __reqsk_queue_destroy(struct request_sock_queue *queue) { kfree(reqsk_queue_yank_listen_sk(queue)); } +extern void reqsk_queue_destroy(struct request_sock_queue *queue); + static inline struct request_sock * reqsk_queue_yank_acceptq(struct request_sock_queue *queue) { @@ -221,17 +227,17 @@ static inline int reqsk_queue_added(struct request_sock_queue *queue) return prev_qlen; } -static inline int reqsk_queue_len(struct request_sock_queue *queue) +static inline int reqsk_queue_len(const struct request_sock_queue *queue) { return queue->listen_opt != NULL ? queue->listen_opt->qlen : 0; } -static inline int reqsk_queue_len_young(struct request_sock_queue *queue) +static inline int reqsk_queue_len_young(const struct request_sock_queue *queue) { return queue->listen_opt->qlen_young; } -static inline int reqsk_queue_is_full(struct request_sock_queue *queue) +static inline int reqsk_queue_is_full(const struct request_sock_queue *queue) { return queue->listen_opt->qlen >> queue->listen_opt->max_qlen_log; } diff --git a/include/net/route.h b/include/net/route.h index c3cd069a9aca..dbe79ca67d31 100644 --- a/include/net/route.h +++ b/include/net/route.h @@ -105,10 +105,6 @@ struct rt_cache_stat unsigned int out_hlist_search; }; -extern struct rt_cache_stat *rt_cache_stat; -#define RT_CACHE_STAT_INC(field) \ - (per_cpu_ptr(rt_cache_stat, raw_smp_processor_id())->field++) - extern struct ip_rt_acct *ip_rt_acct; struct in_device; @@ -199,4 +195,6 @@ static inline struct inet_peer *rt_get_peer(struct rtable *rt) return rt->peer; } +extern ctl_table ipv4_route_table[]; + #endif /* _ROUTE_H */ diff --git a/include/net/sctp/constants.h b/include/net/sctp/constants.h index 5999e5684bbf..c51541ee0247 100644 --- a/include/net/sctp/constants.h +++ b/include/net/sctp/constants.h @@ -47,10 +47,10 @@ #ifndef __sctp_constants_h__ #define __sctp_constants_h__ -#include <linux/tcp.h> /* For TCP states used in sctp_sock_state_t */ #include <linux/sctp.h> #include <linux/ipv6.h> /* For ipv6hdr. */ #include <net/sctp/user.h> +#include <net/tcp_states.h> /* For TCP states used in sctp_sock_state_t */ /* Value used for stream negotiation. */ enum { SCTP_MAX_STREAM = 0xffff }; diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h index ef2738159ab3..e1d5ec1c23c0 100644 --- a/include/net/sctp/sctp.h +++ b/include/net/sctp/sctp.h @@ -125,7 +125,8 @@ */ extern struct sock *sctp_get_ctl_sock(void); extern int sctp_copy_local_addr_list(struct sctp_bind_addr *, - sctp_scope_t, int gfp, int flags); + sctp_scope_t, unsigned int __nocast gfp, + int flags); extern struct sctp_pf *sctp_get_pf_specific(sa_family_t family); extern int sctp_register_pf(struct sctp_pf *, sa_family_t); @@ -166,15 +167,12 @@ void sctp_unhash_established(struct sctp_association *); void sctp_hash_endpoint(struct sctp_endpoint *); void sctp_unhash_endpoint(struct sctp_endpoint *); struct sock *sctp_err_lookup(int family, struct sk_buff *, - struct sctphdr *, struct sctp_endpoint **, - struct sctp_association **, + struct sctphdr *, struct sctp_association **, struct sctp_transport **); -void sctp_err_finish(struct sock *, struct sctp_endpoint *, - struct sctp_association *); +void sctp_err_finish(struct sock *, struct sctp_association *); void sctp_icmp_frag_needed(struct sock *, struct sctp_association *, struct sctp_transport *t, __u32 pmtu); void sctp_icmp_proto_unreachable(struct sock *sk, - struct sctp_endpoint *ep, struct sctp_association *asoc, struct sctp_transport *t); diff --git a/include/net/sctp/sm.h b/include/net/sctp/sm.h index 88d9fe5975d5..58462164d960 100644 --- a/include/net/sctp/sm.h +++ b/include/net/sctp/sm.h @@ -181,17 +181,17 @@ const sctp_sm_table_entry_t *sctp_sm_lookup_event(sctp_event_t, int sctp_chunk_iif(const struct sctp_chunk *); struct sctp_association *sctp_make_temp_asoc(const struct sctp_endpoint *, struct sctp_chunk *, - int gfp); + unsigned int __nocast gfp); __u32 sctp_generate_verification_tag(void); void sctp_populate_tie_tags(__u8 *cookie, __u32 curTag, __u32 hisTag); /* Prototypes for chunk-building functions. */ struct sctp_chunk *sctp_make_init(const struct sctp_association *, const struct sctp_bind_addr *, - int gfp, int vparam_len); + unsigned int __nocast gfp, int vparam_len); struct sctp_chunk *sctp_make_init_ack(const struct sctp_association *, const struct sctp_chunk *, - const int gfp, + const unsigned int __nocast gfp, const int unkparam_len); struct sctp_chunk *sctp_make_cookie_echo(const struct sctp_association *, const struct sctp_chunk *); @@ -265,7 +265,7 @@ int sctp_do_sm(sctp_event_t event_type, sctp_subtype_t subtype, struct sctp_endpoint *, struct sctp_association *asoc, void *event_arg, - int gfp); + unsigned int __nocast gfp); /* 2nd level prototypes */ void sctp_generate_t3_rtx_event(unsigned long peer); @@ -275,7 +275,8 @@ void sctp_ootb_pkt_free(struct sctp_packet *); struct sctp_association *sctp_unpack_cookie(const struct sctp_endpoint *, const struct sctp_association *, - struct sctp_chunk *, int gfp, int *err, + struct sctp_chunk *, + unsigned int __nocast gfp, int *err, struct sctp_chunk **err_chk_p); int sctp_addip_addr_config(struct sctp_association *, sctp_param_t, struct sockaddr_storage*, int); diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 7435528a1747..994009bbe3b4 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -445,7 +445,8 @@ struct sctp_ssnmap { int malloced; }; -struct sctp_ssnmap *sctp_ssnmap_new(__u16 in, __u16 out, int gfp); +struct sctp_ssnmap *sctp_ssnmap_new(__u16 in, __u16 out, + unsigned int __nocast gfp); void sctp_ssnmap_free(struct sctp_ssnmap *map); void sctp_ssnmap_clear(struct sctp_ssnmap *map); @@ -945,7 +946,8 @@ struct sctp_transport { } cacc; }; -struct sctp_transport *sctp_transport_new(const union sctp_addr *, int); +struct sctp_transport *sctp_transport_new(const union sctp_addr *, + unsigned int __nocast); void sctp_transport_set_owner(struct sctp_transport *, struct sctp_association *); void sctp_transport_route(struct sctp_transport *, union sctp_addr *, @@ -1093,9 +1095,10 @@ void sctp_bind_addr_init(struct sctp_bind_addr *, __u16 port); void sctp_bind_addr_free(struct sctp_bind_addr *); int sctp_bind_addr_copy(struct sctp_bind_addr *dest, const struct sctp_bind_addr *src, - sctp_scope_t scope, int gfp,int flags); + sctp_scope_t scope, unsigned int __nocast gfp, + int flags); int sctp_add_bind_addr(struct sctp_bind_addr *, union sctp_addr *, - int gfp); + unsigned int __nocast gfp); int sctp_del_bind_addr(struct sctp_bind_addr *, union sctp_addr *); int sctp_bind_addr_match(struct sctp_bind_addr *, const union sctp_addr *, struct sctp_sock *); @@ -1104,9 +1107,10 @@ union sctp_addr *sctp_find_unmatch_addr(struct sctp_bind_addr *bp, int addrcnt, struct sctp_sock *opt); union sctp_params sctp_bind_addrs_to_raw(const struct sctp_bind_addr *bp, - int *addrs_len, int gfp); + int *addrs_len, + unsigned int __nocast gfp); int sctp_raw_to_bind_addrs(struct sctp_bind_addr *bp, __u8 *raw, int len, - __u16 port, int gfp); + __u16 port, unsigned int __nocast gfp); sctp_scope_t sctp_scope(const union sctp_addr *); int sctp_in_scope(const union sctp_addr *addr, const sctp_scope_t scope); @@ -1235,7 +1239,7 @@ static inline struct sctp_endpoint *sctp_ep(struct sctp_ep_common *base) } /* These are function signatures for manipulating endpoints. */ -struct sctp_endpoint *sctp_endpoint_new(struct sock *, int); +struct sctp_endpoint *sctp_endpoint_new(struct sock *, unsigned int __nocast); void sctp_endpoint_free(struct sctp_endpoint *); void sctp_endpoint_put(struct sctp_endpoint *); void sctp_endpoint_hold(struct sctp_endpoint *); @@ -1256,7 +1260,7 @@ int sctp_verify_init(const struct sctp_association *asoc, sctp_cid_t, struct sctp_chunk **err_chunk); int sctp_process_init(struct sctp_association *, sctp_cid_t cid, const union sctp_addr *peer, - sctp_init_chunk_t *init, int gfp); + sctp_init_chunk_t *init, unsigned int __nocast gfp); __u32 sctp_generate_tag(const struct sctp_endpoint *); __u32 sctp_generate_tsn(const struct sctp_endpoint *); @@ -1719,7 +1723,7 @@ static inline struct sctp_association *sctp_assoc(struct sctp_ep_common *base) struct sctp_association * sctp_association_new(const struct sctp_endpoint *, const struct sock *, - sctp_scope_t scope, int gfp); + sctp_scope_t scope, unsigned int __nocast gfp); void sctp_association_free(struct sctp_association *); void sctp_association_put(struct sctp_association *); void sctp_association_hold(struct sctp_association *); @@ -1735,7 +1739,7 @@ int sctp_assoc_lookup_laddr(struct sctp_association *asoc, const union sctp_addr *laddr); struct sctp_transport *sctp_assoc_add_peer(struct sctp_association *, const union sctp_addr *address, - const int gfp, + const unsigned int __nocast gfp, const int peer_state); void sctp_assoc_del_peer(struct sctp_association *asoc, const union sctp_addr *addr); @@ -1759,9 +1763,11 @@ void sctp_assoc_rwnd_increase(struct sctp_association *, unsigned); void sctp_assoc_rwnd_decrease(struct sctp_association *, unsigned); void sctp_assoc_set_primary(struct sctp_association *, struct sctp_transport *); -int sctp_assoc_set_bind_addr_from_ep(struct sctp_association *, int); +int sctp_assoc_set_bind_addr_from_ep(struct sctp_association *, + unsigned int __nocast); int sctp_assoc_set_bind_addr_from_cookie(struct sctp_association *, - struct sctp_cookie*, int gfp); + struct sctp_cookie*, + unsigned int __nocast gfp); int sctp_cmp_addr_exact(const union sctp_addr *ss1, const union sctp_addr *ss2); diff --git a/include/net/sctp/ulpevent.h b/include/net/sctp/ulpevent.h index 1019d83a580a..90fe4bf6754f 100644 --- a/include/net/sctp/ulpevent.h +++ b/include/net/sctp/ulpevent.h @@ -88,7 +88,7 @@ struct sctp_ulpevent *sctp_ulpevent_make_assoc_change( __u16 error, __u16 outbound, __u16 inbound, - int gfp); + unsigned int __nocast gfp); struct sctp_ulpevent *sctp_ulpevent_make_peer_addr_change( const struct sctp_association *asoc, @@ -96,35 +96,35 @@ struct sctp_ulpevent *sctp_ulpevent_make_peer_addr_change( int flags, int state, int error, - int gfp); + unsigned int __nocast gfp); struct sctp_ulpevent *sctp_ulpevent_make_remote_error( const struct sctp_association *asoc, struct sctp_chunk *chunk, __u16 flags, - int gfp); + unsigned int __nocast gfp); struct sctp_ulpevent *sctp_ulpevent_make_send_failed( const struct sctp_association *asoc, struct sctp_chunk *chunk, __u16 flags, __u32 error, - int gfp); + unsigned int __nocast gfp); struct sctp_ulpevent *sctp_ulpevent_make_shutdown_event( const struct sctp_association *asoc, __u16 flags, - int gfp); + unsigned int __nocast gfp); struct sctp_ulpevent *sctp_ulpevent_make_pdapi( const struct sctp_association *asoc, - __u32 indication, int gfp); + __u32 indication, unsigned int __nocast gfp); struct sctp_ulpevent *sctp_ulpevent_make_adaption_indication( - const struct sctp_association *asoc, int gfp); + const struct sctp_association *asoc, unsigned int __nocast gfp); struct sctp_ulpevent *sctp_ulpevent_make_rcvmsg(struct sctp_association *asoc, struct sctp_chunk *chunk, - int gfp); + unsigned int __nocast gfp); void sctp_ulpevent_read_sndrcvinfo(const struct sctp_ulpevent *event, struct msghdr *); diff --git a/include/net/sctp/ulpqueue.h b/include/net/sctp/ulpqueue.h index 961736d29d21..1a60c6d943c1 100644 --- a/include/net/sctp/ulpqueue.h +++ b/include/net/sctp/ulpqueue.h @@ -62,19 +62,22 @@ struct sctp_ulpq *sctp_ulpq_init(struct sctp_ulpq *, void sctp_ulpq_free(struct sctp_ulpq *); /* Add a new DATA chunk for processing. */ -int sctp_ulpq_tail_data(struct sctp_ulpq *, struct sctp_chunk *, int); +int sctp_ulpq_tail_data(struct sctp_ulpq *, struct sctp_chunk *, + unsigned int __nocast); /* Add a new event for propagation to the ULP. */ int sctp_ulpq_tail_event(struct sctp_ulpq *, struct sctp_ulpevent *ev); /* Renege previously received chunks. */ -void sctp_ulpq_renege(struct sctp_ulpq *, struct sctp_chunk *, int); +void sctp_ulpq_renege(struct sctp_ulpq *, struct sctp_chunk *, + unsigned int __nocast); /* Perform partial delivery. */ -void sctp_ulpq_partial_delivery(struct sctp_ulpq *, struct sctp_chunk *, int); +void sctp_ulpq_partial_delivery(struct sctp_ulpq *, struct sctp_chunk *, + unsigned int __nocast); /* Abort the partial delivery. */ -void sctp_ulpq_abort_pd(struct sctp_ulpq *, int); +void sctp_ulpq_abort_pd(struct sctp_ulpq *, unsigned int __nocast); /* Clear the partial data delivery condition on this socket. */ int sctp_clear_pd(struct sock *sk); diff --git a/include/net/sock.h b/include/net/sock.h index a1042d08becd..8c48fbecb7cf 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -88,6 +88,7 @@ do { spin_lock_init(&((__sk)->sk_lock.slock)); \ } while(0) struct sock; +struct proto; /** * struct sock_common - minimal network layer representation of sockets @@ -98,10 +99,11 @@ struct sock; * @skc_node: main hash linkage for various protocol lookup tables * @skc_bind_node: bind hash linkage for various protocol lookup tables * @skc_refcnt: reference count + * @skc_prot: protocol handlers inside a network family * * This is the minimal network layer representation of sockets, the header - * for struct sock and struct tcp_tw_bucket. - */ + * for struct sock and struct inet_timewait_sock. + */ struct sock_common { unsigned short skc_family; volatile unsigned char skc_state; @@ -110,11 +112,12 @@ struct sock_common { struct hlist_node skc_node; struct hlist_node skc_bind_node; atomic_t skc_refcnt; + struct proto *skc_prot; }; /** * struct sock - network layer representation of sockets - * @__sk_common: shared layout with tcp_tw_bucket + * @__sk_common: shared layout with inet_timewait_sock * @sk_shutdown: mask of %SEND_SHUTDOWN and/or %RCV_SHUTDOWN * @sk_userlocks: %SO_SNDBUF and %SO_RCVBUF settings * @sk_lock: synchronizer @@ -136,11 +139,10 @@ struct sock_common { * @sk_no_check: %SO_NO_CHECK setting, wether or not checkup packets * @sk_route_caps: route capabilities (e.g. %NETIF_F_TSO) * @sk_lingertime: %SO_LINGER l_linger setting - * @sk_hashent: hash entry in several tables (e.g. tcp_ehash) + * @sk_hashent: hash entry in several tables (e.g. inet_hashinfo.ehash) * @sk_backlog: always used with the per-socket spinlock held * @sk_callback_lock: used with the callbacks in the end of this struct * @sk_error_queue: rarely used - * @sk_prot: protocol handlers inside a network family * @sk_prot_creator: sk_prot of original sock creator (see ipv6_setsockopt, IPV6_ADDRFORM for instance) * @sk_err: last error * @sk_err_soft: errors that don't cause failure but are the cause of a persistent failure not just 'timed out' @@ -173,7 +175,7 @@ struct sock_common { */ struct sock { /* - * Now struct tcp_tw_bucket also uses sock_common, so please just + * Now struct inet_timewait_sock also uses sock_common, so please just * don't add nothing before this first member (__sk_common) --acme */ struct sock_common __sk_common; @@ -184,6 +186,7 @@ struct sock { #define sk_node __sk_common.skc_node #define sk_bind_node __sk_common.skc_bind_node #define sk_refcnt __sk_common.skc_refcnt +#define sk_prot __sk_common.skc_prot unsigned char sk_shutdown : 2, sk_no_check : 2, sk_userlocks : 4; @@ -218,7 +221,6 @@ struct sock { struct sk_buff *tail; } sk_backlog; struct sk_buff_head sk_error_queue; - struct proto *sk_prot; struct proto *sk_prot_creator; rwlock_t sk_callback_lock; int sk_err, @@ -253,28 +255,28 @@ struct sock { /* * Hashed lists helper routines */ -static inline struct sock *__sk_head(struct hlist_head *head) +static inline struct sock *__sk_head(const struct hlist_head *head) { return hlist_entry(head->first, struct sock, sk_node); } -static inline struct sock *sk_head(struct hlist_head *head) +static inline struct sock *sk_head(const struct hlist_head *head) { return hlist_empty(head) ? NULL : __sk_head(head); } -static inline struct sock *sk_next(struct sock *sk) +static inline struct sock *sk_next(const struct sock *sk) { return sk->sk_node.next ? hlist_entry(sk->sk_node.next, struct sock, sk_node) : NULL; } -static inline int sk_unhashed(struct sock *sk) +static inline int sk_unhashed(const struct sock *sk) { return hlist_unhashed(&sk->sk_node); } -static inline int sk_hashed(struct sock *sk) +static inline int sk_hashed(const struct sock *sk) { return sk->sk_node.pprev != NULL; } @@ -384,6 +386,11 @@ enum sock_flags { SOCK_QUEUE_SHRUNK, /* write queue has been shrunk recently */ }; +static inline void sock_copy_flags(struct sock *nsk, struct sock *osk) +{ + nsk->sk_flags = osk->sk_flags; +} + static inline void sock_set_flag(struct sock *sk, enum sock_flags flag) { __set_bit(flag, &sk->sk_flags); @@ -549,6 +556,10 @@ struct proto { kmem_cache_t *slab; unsigned int obj_size; + kmem_cache_t *twsk_slab; + unsigned int twsk_obj_size; + atomic_t *orphan_count; + struct request_sock_ops *rsk_prot; struct module *owner; @@ -556,7 +567,9 @@ struct proto { char name[32]; struct list_head node; - +#ifdef SOCK_REFCNT_DEBUG + atomic_t socks; +#endif struct { int inuse; u8 __pad[SMP_CACHE_BYTES - sizeof(int)]; @@ -566,6 +579,31 @@ struct proto { extern int proto_register(struct proto *prot, int alloc_slab); extern void proto_unregister(struct proto *prot); +#ifdef SOCK_REFCNT_DEBUG +static inline void sk_refcnt_debug_inc(struct sock *sk) +{ + atomic_inc(&sk->sk_prot->socks); +} + +static inline void sk_refcnt_debug_dec(struct sock *sk) +{ + atomic_dec(&sk->sk_prot->socks); + printk(KERN_DEBUG "%s socket %p released, %d are still alive\n", + sk->sk_prot->name, sk, atomic_read(&sk->sk_prot->socks)); +} + +static inline void sk_refcnt_debug_release(const struct sock *sk) +{ + if (atomic_read(&sk->sk_refcnt) != 1) + printk(KERN_DEBUG "Destruction of the %s socket %p delayed, refcnt=%d\n", + sk->sk_prot->name, sk, atomic_read(&sk->sk_refcnt)); +} +#else /* SOCK_REFCNT_DEBUG */ +#define sk_refcnt_debug_inc(sk) do { } while (0) +#define sk_refcnt_debug_dec(sk) do { } while (0) +#define sk_refcnt_debug_release(sk) do { } while (0) +#endif /* SOCK_REFCNT_DEBUG */ + /* Called with local bh disabled */ static __inline__ void sock_prot_inc_use(struct proto *prot) { @@ -577,6 +615,15 @@ static __inline__ void sock_prot_dec_use(struct proto *prot) prot->stats[smp_processor_id()].inuse--; } +/* With per-bucket locks this operation is not-atomic, so that + * this version is not worse. + */ +static inline void __sk_prot_rehash(struct sock *sk) +{ + sk->sk_prot->unhash(sk); + sk->sk_prot->hash(sk); +} + /* About 10 seconds */ #define SOCK_DESTROY_TIME (10*HZ) @@ -662,6 +709,12 @@ static inline int sk_stream_rmem_schedule(struct sock *sk, struct sk_buff *skb) sk_stream_mem_schedule(sk, skb->truesize, 1); } +static inline int sk_stream_wmem_schedule(struct sock *sk, int size) +{ + return size <= sk->sk_forward_alloc || + sk_stream_mem_schedule(sk, size, 0); +} + /* Used by processes to "lock" a socket state, so that * interrupts and bottom half handlers won't change it * from under us. It essentially blocks any incoming @@ -688,6 +741,8 @@ extern struct sock *sk_alloc(int family, unsigned int __nocast priority, struct proto *prot, int zero_it); extern void sk_free(struct sock *sk); +extern struct sock *sk_clone(const struct sock *sk, + const unsigned int __nocast priority); extern struct sk_buff *sock_wmalloc(struct sock *sk, unsigned long size, int force, @@ -981,6 +1036,16 @@ sk_dst_check(struct sock *sk, u32 cookie) return dst; } +static inline void sk_setup_caps(struct sock *sk, struct dst_entry *dst) +{ + __sk_dst_set(sk, dst); + sk->sk_route_caps = dst->dev->features; + if (sk->sk_route_caps & NETIF_F_TSO) { + if (sock_flag(sk, SOCK_NO_LARGESEND) || dst->header_len) + sk->sk_route_caps &= ~NETIF_F_TSO; + } +} + static inline void sk_charge_skb(struct sock *sk, struct sk_buff *skb) { sk->sk_wmem_queued += skb->truesize; @@ -1141,11 +1206,10 @@ static inline struct sk_buff *sk_stream_alloc_pskb(struct sock *sk, int hdr_len; hdr_len = SKB_DATA_ALIGN(sk->sk_prot->max_header); - skb = alloc_skb(size + hdr_len, gfp); + skb = alloc_skb_fclone(size + hdr_len, gfp); if (skb) { skb->truesize += mem; - if (sk->sk_forward_alloc >= (int)skb->truesize || - sk_stream_mem_schedule(sk, skb->truesize, 0)) { + if (sk_stream_wmem_schedule(sk, skb->truesize)) { skb_reserve(skb, hdr_len); return skb; } @@ -1168,10 +1232,8 @@ static inline struct page *sk_stream_alloc_page(struct sock *sk) { struct page *page = NULL; - if (sk->sk_forward_alloc >= (int)PAGE_SIZE || - sk_stream_mem_schedule(sk, PAGE_SIZE, 0)) - page = alloc_pages(sk->sk_allocation, 0); - else { + page = alloc_pages(sk->sk_allocation, 0); + if (!page) { sk->sk_prot->enter_memory_pressure(); sk_stream_moderate_sndbuf(sk); } @@ -1223,16 +1285,19 @@ static inline int sock_intr_errno(long timeo) static __inline__ void sock_recv_timestamp(struct msghdr *msg, struct sock *sk, struct sk_buff *skb) { - struct timeval *stamp = &skb->stamp; + struct timeval stamp; + + skb_get_timestamp(skb, &stamp); if (sock_flag(sk, SOCK_RCVTSTAMP)) { /* Race occurred between timestamp enabling and packet receiving. Fill in the current time for now. */ - if (stamp->tv_sec == 0) - do_gettimeofday(stamp); + if (stamp.tv_sec == 0) + do_gettimeofday(&stamp); + skb_set_timestamp(skb, &stamp); put_cmsg(msg, SOL_SOCKET, SO_TIMESTAMP, sizeof(struct timeval), - stamp); + &stamp); } else - sk->sk_stamp = *stamp; + sk->sk_stamp = stamp; } /** @@ -1257,11 +1322,11 @@ extern int sock_get_timestamp(struct sock *, struct timeval __user *); */ #if 0 -#define NETDEBUG(x) do { } while (0) -#define LIMIT_NETDEBUG(x) do {} while(0) +#define NETDEBUG(fmt, args...) do { } while (0) +#define LIMIT_NETDEBUG(fmt, args...) do { } while(0) #else -#define NETDEBUG(x) do { x; } while (0) -#define LIMIT_NETDEBUG(x) do { if (net_ratelimit()) { x; } } while(0) +#define NETDEBUG(fmt, args...) printk(fmt,##args) +#define LIMIT_NETDEBUG(fmt, args...) do { if (net_ratelimit()) printk(fmt,##args); } while(0) #endif /* @@ -1308,4 +1373,15 @@ static inline int siocdevprivate_ioctl(unsigned int fd, unsigned int cmd, unsign } #endif +extern void sk_init(void); + +#ifdef CONFIG_SYSCTL +extern struct ctl_table core_table[]; +#endif + +extern int sysctl_optmem_max; + +extern __u32 sysctl_wmem_default; +extern __u32 sysctl_rmem_default; + #endif /* _SOCK_H */ diff --git a/include/net/tcp.h b/include/net/tcp.h index f4f9aba07ac2..97af77c4d096 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -21,360 +21,29 @@ #define TCP_DEBUG 1 #define FASTRETRANS_DEBUG 1 -/* Cancel timers, when they are not required. */ -#undef TCP_CLEAR_TIMERS - #include <linux/config.h> #include <linux/list.h> #include <linux/tcp.h> #include <linux/slab.h> #include <linux/cache.h> #include <linux/percpu.h> + +#include <net/inet_connection_sock.h> +#include <net/inet_timewait_sock.h> +#include <net/inet_hashtables.h> #include <net/checksum.h> #include <net/request_sock.h> #include <net/sock.h> #include <net/snmp.h> #include <net/ip.h> -#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) -#include <linux/ipv6.h> -#endif -#include <linux/seq_file.h> - -/* This is for all connections with a full identity, no wildcards. - * New scheme, half the table is for TIME_WAIT, the other half is - * for the rest. I'll experiment with dynamic table growth later. - */ -struct tcp_ehash_bucket { - rwlock_t lock; - struct hlist_head chain; -} __attribute__((__aligned__(8))); - -/* This is for listening sockets, thus all sockets which possess wildcards. */ -#define TCP_LHTABLE_SIZE 32 /* Yes, really, this is all you need. */ - -/* There are a few simple rules, which allow for local port reuse by - * an application. In essence: - * - * 1) Sockets bound to different interfaces may share a local port. - * Failing that, goto test 2. - * 2) If all sockets have sk->sk_reuse set, and none of them are in - * TCP_LISTEN state, the port may be shared. - * Failing that, goto test 3. - * 3) If all sockets are bound to a specific inet_sk(sk)->rcv_saddr local - * address, and none of them are the same, the port may be - * shared. - * Failing this, the port cannot be shared. - * - * The interesting point, is test #2. This is what an FTP server does - * all day. To optimize this case we use a specific flag bit defined - * below. As we add sockets to a bind bucket list, we perform a - * check of: (newsk->sk_reuse && (newsk->sk_state != TCP_LISTEN)) - * As long as all sockets added to a bind bucket pass this test, - * the flag bit will be set. - * The resulting situation is that tcp_v[46]_verify_bind() can just check - * for this flag bit, if it is set and the socket trying to bind has - * sk->sk_reuse set, we don't even have to walk the owners list at all, - * we return that it is ok to bind this socket to the requested local port. - * - * Sounds like a lot of work, but it is worth it. In a more naive - * implementation (ie. current FreeBSD etc.) the entire list of ports - * must be walked for each data port opened by an ftp server. Needless - * to say, this does not scale at all. With a couple thousand FTP - * users logged onto your box, isn't it nice to know that new data - * ports are created in O(1) time? I thought so. ;-) -DaveM - */ -struct tcp_bind_bucket { - unsigned short port; - signed short fastreuse; - struct hlist_node node; - struct hlist_head owners; -}; - -#define tb_for_each(tb, node, head) hlist_for_each_entry(tb, node, head, node) - -struct tcp_bind_hashbucket { - spinlock_t lock; - struct hlist_head chain; -}; - -static inline struct tcp_bind_bucket *__tb_head(struct tcp_bind_hashbucket *head) -{ - return hlist_entry(head->chain.first, struct tcp_bind_bucket, node); -} - -static inline struct tcp_bind_bucket *tb_head(struct tcp_bind_hashbucket *head) -{ - return hlist_empty(&head->chain) ? NULL : __tb_head(head); -} - -extern struct tcp_hashinfo { - /* This is for sockets with full identity only. Sockets here will - * always be without wildcards and will have the following invariant: - * - * TCP_ESTABLISHED <= sk->sk_state < TCP_CLOSE - * - * First half of the table is for sockets not in TIME_WAIT, second half - * is for TIME_WAIT sockets only. - */ - struct tcp_ehash_bucket *__tcp_ehash; - - /* Ok, let's try this, I give up, we do need a local binding - * TCP hash as well as the others for fast bind/connect. - */ - struct tcp_bind_hashbucket *__tcp_bhash; +#include <net/tcp_states.h> - int __tcp_bhash_size; - int __tcp_ehash_size; - - /* All sockets in TCP_LISTEN state will be in here. This is the only - * table where wildcard'd TCP sockets can exist. Hash function here - * is just local port number. - */ - struct hlist_head __tcp_listening_hash[TCP_LHTABLE_SIZE]; - - /* All the above members are written once at bootup and - * never written again _or_ are predominantly read-access. - * - * Now align to a new cache line as all the following members - * are often dirty. - */ - rwlock_t __tcp_lhash_lock ____cacheline_aligned; - atomic_t __tcp_lhash_users; - wait_queue_head_t __tcp_lhash_wait; - spinlock_t __tcp_portalloc_lock; -} tcp_hashinfo; - -#define tcp_ehash (tcp_hashinfo.__tcp_ehash) -#define tcp_bhash (tcp_hashinfo.__tcp_bhash) -#define tcp_ehash_size (tcp_hashinfo.__tcp_ehash_size) -#define tcp_bhash_size (tcp_hashinfo.__tcp_bhash_size) -#define tcp_listening_hash (tcp_hashinfo.__tcp_listening_hash) -#define tcp_lhash_lock (tcp_hashinfo.__tcp_lhash_lock) -#define tcp_lhash_users (tcp_hashinfo.__tcp_lhash_users) -#define tcp_lhash_wait (tcp_hashinfo.__tcp_lhash_wait) -#define tcp_portalloc_lock (tcp_hashinfo.__tcp_portalloc_lock) - -extern kmem_cache_t *tcp_bucket_cachep; -extern struct tcp_bind_bucket *tcp_bucket_create(struct tcp_bind_hashbucket *head, - unsigned short snum); -extern void tcp_bucket_destroy(struct tcp_bind_bucket *tb); -extern void tcp_bucket_unlock(struct sock *sk); -extern int tcp_port_rover; - -/* These are AF independent. */ -static __inline__ int tcp_bhashfn(__u16 lport) -{ - return (lport & (tcp_bhash_size - 1)); -} - -extern void tcp_bind_hash(struct sock *sk, struct tcp_bind_bucket *tb, - unsigned short snum); - -#if (BITS_PER_LONG == 64) -#define TCP_ADDRCMP_ALIGN_BYTES 8 -#else -#define TCP_ADDRCMP_ALIGN_BYTES 4 -#endif - -/* This is a TIME_WAIT bucket. It works around the memory consumption - * problems of sockets in such a state on heavily loaded servers, but - * without violating the protocol specification. - */ -struct tcp_tw_bucket { - /* - * Now struct sock also uses sock_common, so please just - * don't add nothing before this first member (__tw_common) --acme - */ - struct sock_common __tw_common; -#define tw_family __tw_common.skc_family -#define tw_state __tw_common.skc_state -#define tw_reuse __tw_common.skc_reuse -#define tw_bound_dev_if __tw_common.skc_bound_dev_if -#define tw_node __tw_common.skc_node -#define tw_bind_node __tw_common.skc_bind_node -#define tw_refcnt __tw_common.skc_refcnt - volatile unsigned char tw_substate; - unsigned char tw_rcv_wscale; - __u16 tw_sport; - /* Socket demultiplex comparisons on incoming packets. */ - /* these five are in inet_sock */ - __u32 tw_daddr - __attribute__((aligned(TCP_ADDRCMP_ALIGN_BYTES))); - __u32 tw_rcv_saddr; - __u16 tw_dport; - __u16 tw_num; - /* And these are ours. */ - int tw_hashent; - int tw_timeout; - __u32 tw_rcv_nxt; - __u32 tw_snd_nxt; - __u32 tw_rcv_wnd; - __u32 tw_ts_recent; - long tw_ts_recent_stamp; - unsigned long tw_ttd; - struct tcp_bind_bucket *tw_tb; - struct hlist_node tw_death_node; -#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) - struct in6_addr tw_v6_daddr; - struct in6_addr tw_v6_rcv_saddr; - int tw_v6_ipv6only; -#endif -}; - -static __inline__ void tw_add_node(struct tcp_tw_bucket *tw, - struct hlist_head *list) -{ - hlist_add_head(&tw->tw_node, list); -} - -static __inline__ void tw_add_bind_node(struct tcp_tw_bucket *tw, - struct hlist_head *list) -{ - hlist_add_head(&tw->tw_bind_node, list); -} - -static inline int tw_dead_hashed(struct tcp_tw_bucket *tw) -{ - return tw->tw_death_node.pprev != NULL; -} - -static __inline__ void tw_dead_node_init(struct tcp_tw_bucket *tw) -{ - tw->tw_death_node.pprev = NULL; -} - -static __inline__ void __tw_del_dead_node(struct tcp_tw_bucket *tw) -{ - __hlist_del(&tw->tw_death_node); - tw_dead_node_init(tw); -} - -static __inline__ int tw_del_dead_node(struct tcp_tw_bucket *tw) -{ - if (tw_dead_hashed(tw)) { - __tw_del_dead_node(tw); - return 1; - } - return 0; -} - -#define tw_for_each(tw, node, head) \ - hlist_for_each_entry(tw, node, head, tw_node) - -#define tw_for_each_inmate(tw, node, jail) \ - hlist_for_each_entry(tw, node, jail, tw_death_node) - -#define tw_for_each_inmate_safe(tw, node, safe, jail) \ - hlist_for_each_entry_safe(tw, node, safe, jail, tw_death_node) - -#define tcptw_sk(__sk) ((struct tcp_tw_bucket *)(__sk)) - -static inline u32 tcp_v4_rcv_saddr(const struct sock *sk) -{ - return likely(sk->sk_state != TCP_TIME_WAIT) ? - inet_sk(sk)->rcv_saddr : tcptw_sk(sk)->tw_rcv_saddr; -} - -#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -static inline struct in6_addr *__tcp_v6_rcv_saddr(const struct sock *sk) -{ - return likely(sk->sk_state != TCP_TIME_WAIT) ? - &inet6_sk(sk)->rcv_saddr : &tcptw_sk(sk)->tw_v6_rcv_saddr; -} - -static inline struct in6_addr *tcp_v6_rcv_saddr(const struct sock *sk) -{ - return sk->sk_family == AF_INET6 ? __tcp_v6_rcv_saddr(sk) : NULL; -} - -#define tcptw_sk_ipv6only(__sk) (tcptw_sk(__sk)->tw_v6_ipv6only) - -static inline int tcp_v6_ipv6only(const struct sock *sk) -{ - return likely(sk->sk_state != TCP_TIME_WAIT) ? - ipv6_only_sock(sk) : tcptw_sk_ipv6only(sk); -} -#else -# define __tcp_v6_rcv_saddr(__sk) NULL -# define tcp_v6_rcv_saddr(__sk) NULL -# define tcptw_sk_ipv6only(__sk) 0 -# define tcp_v6_ipv6only(__sk) 0 -#endif +#include <linux/seq_file.h> -extern kmem_cache_t *tcp_timewait_cachep; - -static inline void tcp_tw_put(struct tcp_tw_bucket *tw) -{ - if (atomic_dec_and_test(&tw->tw_refcnt)) { -#ifdef INET_REFCNT_DEBUG - printk(KERN_DEBUG "tw_bucket %p released\n", tw); -#endif - kmem_cache_free(tcp_timewait_cachep, tw); - } -} +extern struct inet_hashinfo tcp_hashinfo; extern atomic_t tcp_orphan_count; -extern int tcp_tw_count; extern void tcp_time_wait(struct sock *sk, int state, int timeo); -extern void tcp_tw_deschedule(struct tcp_tw_bucket *tw); - - -/* Socket demux engine toys. */ -#ifdef __BIG_ENDIAN -#define TCP_COMBINED_PORTS(__sport, __dport) \ - (((__u32)(__sport)<<16) | (__u32)(__dport)) -#else /* __LITTLE_ENDIAN */ -#define TCP_COMBINED_PORTS(__sport, __dport) \ - (((__u32)(__dport)<<16) | (__u32)(__sport)) -#endif - -#if (BITS_PER_LONG == 64) -#ifdef __BIG_ENDIAN -#define TCP_V4_ADDR_COOKIE(__name, __saddr, __daddr) \ - __u64 __name = (((__u64)(__saddr))<<32)|((__u64)(__daddr)); -#else /* __LITTLE_ENDIAN */ -#define TCP_V4_ADDR_COOKIE(__name, __saddr, __daddr) \ - __u64 __name = (((__u64)(__daddr))<<32)|((__u64)(__saddr)); -#endif /* __BIG_ENDIAN */ -#define TCP_IPV4_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\ - (((*((__u64 *)&(inet_sk(__sk)->daddr)))== (__cookie)) && \ - ((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports)) && \ - (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) -#define TCP_IPV4_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\ - (((*((__u64 *)&(tcptw_sk(__sk)->tw_daddr))) == (__cookie)) && \ - ((*((__u32 *)&(tcptw_sk(__sk)->tw_dport))) == (__ports)) && \ - (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) -#else /* 32-bit arch */ -#define TCP_V4_ADDR_COOKIE(__name, __saddr, __daddr) -#define TCP_IPV4_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\ - ((inet_sk(__sk)->daddr == (__saddr)) && \ - (inet_sk(__sk)->rcv_saddr == (__daddr)) && \ - ((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports)) && \ - (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) -#define TCP_IPV4_TW_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\ - ((tcptw_sk(__sk)->tw_daddr == (__saddr)) && \ - (tcptw_sk(__sk)->tw_rcv_saddr == (__daddr)) && \ - ((*((__u32 *)&(tcptw_sk(__sk)->tw_dport))) == (__ports)) && \ - (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) -#endif /* 64-bit arch */ - -#define TCP_IPV6_MATCH(__sk, __saddr, __daddr, __ports, __dif) \ - (((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports)) && \ - ((__sk)->sk_family == AF_INET6) && \ - ipv6_addr_equal(&inet6_sk(__sk)->daddr, (__saddr)) && \ - ipv6_addr_equal(&inet6_sk(__sk)->rcv_saddr, (__daddr)) && \ - (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif)))) - -/* These can have wildcards, don't try too hard. */ -static __inline__ int tcp_lhashfn(unsigned short num) -{ - return num & (TCP_LHTABLE_SIZE - 1); -} - -static __inline__ int tcp_sk_listen_hashfn(struct sock *sk) -{ - return tcp_lhashfn(inet_sk(sk)->num); -} #define MAX_TCP_HEADER (128 + MAX_HEADER) @@ -478,33 +147,6 @@ static __inline__ int tcp_sk_listen_hashfn(struct sock *sk) * timestamps. It must be less than * minimal timewait lifetime. */ - -#define TCP_TW_RECYCLE_SLOTS_LOG 5 -#define TCP_TW_RECYCLE_SLOTS (1<<TCP_TW_RECYCLE_SLOTS_LOG) - -/* If time > 4sec, it is "slow" path, no recycling is required, - so that we select tick to get range about 4 seconds. - */ - -#if HZ <= 16 || HZ > 4096 -# error Unsupported: HZ <= 16 or HZ > 4096 -#elif HZ <= 32 -# define TCP_TW_RECYCLE_TICK (5+2-TCP_TW_RECYCLE_SLOTS_LOG) -#elif HZ <= 64 -# define TCP_TW_RECYCLE_TICK (6+2-TCP_TW_RECYCLE_SLOTS_LOG) -#elif HZ <= 128 -# define TCP_TW_RECYCLE_TICK (7+2-TCP_TW_RECYCLE_SLOTS_LOG) -#elif HZ <= 256 -# define TCP_TW_RECYCLE_TICK (8+2-TCP_TW_RECYCLE_SLOTS_LOG) -#elif HZ <= 512 -# define TCP_TW_RECYCLE_TICK (9+2-TCP_TW_RECYCLE_SLOTS_LOG) -#elif HZ <= 1024 -# define TCP_TW_RECYCLE_TICK (10+2-TCP_TW_RECYCLE_SLOTS_LOG) -#elif HZ <= 2048 -# define TCP_TW_RECYCLE_TICK (11+2-TCP_TW_RECYCLE_SLOTS_LOG) -#else -# define TCP_TW_RECYCLE_TICK (12+2-TCP_TW_RECYCLE_SLOTS_LOG) -#endif /* * TCP option */ @@ -534,22 +176,18 @@ static __inline__ int tcp_sk_listen_hashfn(struct sock *sk) #define TCPOLEN_SACK_BASE_ALIGNED 4 #define TCPOLEN_SACK_PERBLOCK 8 -#define TCP_TIME_RETRANS 1 /* Retransmit timer */ -#define TCP_TIME_DACK 2 /* Delayed ack timer */ -#define TCP_TIME_PROBE0 3 /* Zero window probe timer */ -#define TCP_TIME_KEEPOPEN 4 /* Keepalive timer */ - /* Flags in tp->nonagle */ #define TCP_NAGLE_OFF 1 /* Nagle's algo is disabled */ #define TCP_NAGLE_CORK 2 /* Socket is corked */ #define TCP_NAGLE_PUSH 4 /* Cork is overriden for already queued data */ +extern struct inet_timewait_death_row tcp_death_row; + /* sysctl variables for tcp */ extern int sysctl_tcp_timestamps; extern int sysctl_tcp_window_scaling; extern int sysctl_tcp_sack; extern int sysctl_tcp_fin_timeout; -extern int sysctl_tcp_tw_recycle; extern int sysctl_tcp_keepalive_time; extern int sysctl_tcp_keepalive_probes; extern int sysctl_tcp_keepalive_intvl; @@ -564,7 +202,6 @@ extern int sysctl_tcp_stdurg; extern int sysctl_tcp_rfc1337; extern int sysctl_tcp_abort_on_overflow; extern int sysctl_tcp_max_orphans; -extern int sysctl_tcp_max_tw_buckets; extern int sysctl_tcp_fack; extern int sysctl_tcp_reordering; extern int sysctl_tcp_ecn; @@ -585,12 +222,6 @@ extern atomic_t tcp_memory_allocated; extern atomic_t tcp_sockets_allocated; extern int tcp_memory_pressure; -#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -#define TCP_INET_FAMILY(fam) ((fam) == AF_INET) -#else -#define TCP_INET_FAMILY(fam) 1 -#endif - /* * Pointers to address related TCP functions * (i.e. things that depend on the address family) @@ -671,9 +302,6 @@ DECLARE_SNMP_STAT(struct tcp_mib, tcp_statistics); #define TCP_ADD_STATS_BH(field, val) SNMP_ADD_STATS_BH(tcp_statistics, field, val) #define TCP_ADD_STATS_USER(field, val) SNMP_ADD_STATS_USER(tcp_statistics, field, val) -extern void tcp_put_port(struct sock *sk); -extern void tcp_inherit_port(struct sock *sk, struct sock *child); - extern void tcp_v4_err(struct sk_buff *skb, u32); extern void tcp_shutdown (struct sock *sk, int how); @@ -682,7 +310,7 @@ extern int tcp_v4_rcv(struct sk_buff *skb); extern int tcp_v4_remember_stamp(struct sock *sk); -extern int tcp_v4_tw_remember_stamp(struct tcp_tw_bucket *tw); +extern int tcp_v4_tw_remember_stamp(struct inet_timewait_sock *tw); extern int tcp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg, size_t size); @@ -704,42 +332,22 @@ extern int tcp_rcv_established(struct sock *sk, extern void tcp_rcv_space_adjust(struct sock *sk); -enum tcp_ack_state_t -{ - TCP_ACK_SCHED = 1, - TCP_ACK_TIMER = 2, - TCP_ACK_PUSHED= 4 -}; - -static inline void tcp_schedule_ack(struct tcp_sock *tp) +static inline void tcp_dec_quickack_mode(struct sock *sk, + const unsigned int pkts) { - tp->ack.pending |= TCP_ACK_SCHED; -} - -static inline int tcp_ack_scheduled(struct tcp_sock *tp) -{ - return tp->ack.pending&TCP_ACK_SCHED; -} - -static __inline__ void tcp_dec_quickack_mode(struct tcp_sock *tp, unsigned int pkts) -{ - if (tp->ack.quick) { - if (pkts >= tp->ack.quick) { - tp->ack.quick = 0; + struct inet_connection_sock *icsk = inet_csk(sk); + if (icsk->icsk_ack.quick) { + if (pkts >= icsk->icsk_ack.quick) { + icsk->icsk_ack.quick = 0; /* Leaving quickack mode we deflate ATO. */ - tp->ack.ato = TCP_ATO_MIN; + icsk->icsk_ack.ato = TCP_ATO_MIN; } else - tp->ack.quick -= pkts; + icsk->icsk_ack.quick -= pkts; } } -extern void tcp_enter_quickack_mode(struct tcp_sock *tp); - -static __inline__ void tcp_delack_init(struct tcp_sock *tp) -{ - memset(&tp->ack, 0, sizeof(tp->ack)); -} +extern void tcp_enter_quickack_mode(struct sock *sk); static inline void tcp_clear_options(struct tcp_options_received *rx_opt) { @@ -755,10 +363,9 @@ enum tcp_tw_status }; -extern enum tcp_tw_status tcp_timewait_state_process(struct tcp_tw_bucket *tw, +extern enum tcp_tw_status tcp_timewait_state_process(struct inet_timewait_sock *tw, struct sk_buff *skb, - struct tcphdr *th, - unsigned len); + const struct tcphdr *th); extern struct sock * tcp_check_req(struct sock *sk,struct sk_buff *skb, struct request_sock *req, @@ -773,7 +380,6 @@ extern void tcp_update_metrics(struct sock *sk); extern void tcp_close(struct sock *sk, long timeout); -extern struct sock * tcp_accept(struct sock *sk, int flags, int *err); extern unsigned int tcp_poll(struct file * file, struct socket *sock, struct poll_table_struct *wait); extern int tcp_getsockopt(struct sock *sk, int level, @@ -789,8 +395,6 @@ extern int tcp_recvmsg(struct kiocb *iocb, struct sock *sk, size_t len, int nonblock, int flags, int *addr_len); -extern int tcp_listen_start(struct sock *sk); - extern void tcp_parse_options(struct sk_buff *skb, struct tcp_options_received *opt_rx, int estab); @@ -799,11 +403,6 @@ extern void tcp_parse_options(struct sk_buff *skb, * TCP v4 functions exported for the inet6 API */ -extern int tcp_v4_rebuild_header(struct sock *sk); - -extern int tcp_v4_build_header(struct sock *sk, - struct sk_buff *skb); - extern void tcp_v4_send_check(struct sock *sk, struct tcphdr *th, int len, struct sk_buff *skb); @@ -855,6 +454,7 @@ extern int tcp_retransmit_skb(struct sock *, struct sk_buff *); extern void tcp_xmit_retransmit_queue(struct sock *); extern void tcp_simple_retransmit(struct sock *); extern int tcp_trim_head(struct sock *, struct sk_buff *, u32); +extern int tcp_fragment(struct sock *, struct sk_buff *, u32, unsigned int); extern void tcp_send_probe0(struct sock *); extern void tcp_send_partial(struct sock *); @@ -872,18 +472,15 @@ extern void tcp_cwnd_application_limited(struct sock *sk); /* tcp_timer.c */ extern void tcp_init_xmit_timers(struct sock *); -extern void tcp_clear_xmit_timers(struct sock *); +static inline void tcp_clear_xmit_timers(struct sock *sk) +{ + inet_csk_clear_xmit_timers(sk); +} -extern void tcp_delete_keepalive_timer(struct sock *); -extern void tcp_reset_keepalive_timer(struct sock *, unsigned long); extern unsigned int tcp_sync_mss(struct sock *sk, u32 pmtu); extern unsigned int tcp_current_mss(struct sock *sk, int large); -#ifdef TCP_DEBUG -extern const char tcp_timer_bug_msg[]; -#endif - -/* tcp_diag.c */ +/* tcp.c */ extern void tcp_get_info(struct sock *, struct tcp_info *); /* Read 'sendfile()'-style from a TCP socket */ @@ -892,72 +489,6 @@ typedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, extern int tcp_read_sock(struct sock *sk, read_descriptor_t *desc, sk_read_actor_t recv_actor); -static inline void tcp_clear_xmit_timer(struct sock *sk, int what) -{ - struct tcp_sock *tp = tcp_sk(sk); - - switch (what) { - case TCP_TIME_RETRANS: - case TCP_TIME_PROBE0: - tp->pending = 0; - -#ifdef TCP_CLEAR_TIMERS - sk_stop_timer(sk, &tp->retransmit_timer); -#endif - break; - case TCP_TIME_DACK: - tp->ack.blocked = 0; - tp->ack.pending = 0; - -#ifdef TCP_CLEAR_TIMERS - sk_stop_timer(sk, &tp->delack_timer); -#endif - break; - default: -#ifdef TCP_DEBUG - printk(tcp_timer_bug_msg); -#endif - return; - }; - -} - -/* - * Reset the retransmission timer - */ -static inline void tcp_reset_xmit_timer(struct sock *sk, int what, unsigned long when) -{ - struct tcp_sock *tp = tcp_sk(sk); - - if (when > TCP_RTO_MAX) { -#ifdef TCP_DEBUG - printk(KERN_DEBUG "reset_xmit_timer sk=%p %d when=0x%lx, caller=%p\n", sk, what, when, current_text_addr()); -#endif - when = TCP_RTO_MAX; - } - - switch (what) { - case TCP_TIME_RETRANS: - case TCP_TIME_PROBE0: - tp->pending = what; - tp->timeout = jiffies+when; - sk_reset_timer(sk, &tp->retransmit_timer, tp->timeout); - break; - - case TCP_TIME_DACK: - tp->ack.pending |= TCP_ACK_TIMER; - tp->ack.timeout = jiffies+when; - sk_reset_timer(sk, &tp->delack_timer, tp->ack.timeout); - break; - - default: -#ifdef TCP_DEBUG - printk(tcp_timer_bug_msg); -#endif - return; - }; -} - /* Initialize RCV_MSS value. * RCV_MSS is an our guess about MSS used by the peer. * We haven't any direct information about the MSS. @@ -975,7 +506,7 @@ static inline void tcp_initialize_rcv_mss(struct sock *sk) hint = min(hint, TCP_MIN_RCVMSS); hint = max(hint, TCP_MIN_MSS); - tp->ack.rcv_mss = hint; + inet_csk(sk)->icsk_ack.rcv_mss = hint; } static __inline__ void __tcp_fast_path_on(struct tcp_sock *tp, u32 snd_wnd) @@ -1110,7 +641,8 @@ static inline void tcp_packets_out_inc(struct sock *sk, tp->packets_out += tcp_skb_pcount(skb); if (!orig) - tcp_reset_xmit_timer(sk, TCP_TIME_RETRANS, tp->rto); + inet_csk_reset_xmit_timer(sk, ICSK_TIME_RETRANS, + inet_csk(sk)->icsk_rto, TCP_RTO_MAX); } static inline void tcp_packets_out_dec(struct tcp_sock *tp, @@ -1138,29 +670,29 @@ struct tcp_congestion_ops { struct list_head list; /* initialize private data (optional) */ - void (*init)(struct tcp_sock *tp); + void (*init)(struct sock *sk); /* cleanup private data (optional) */ - void (*release)(struct tcp_sock *tp); + void (*release)(struct sock *sk); /* return slow start threshold (required) */ - u32 (*ssthresh)(struct tcp_sock *tp); + u32 (*ssthresh)(struct sock *sk); /* lower bound for congestion window (optional) */ - u32 (*min_cwnd)(struct tcp_sock *tp); + u32 (*min_cwnd)(struct sock *sk); /* do new cwnd calculation (required) */ - void (*cong_avoid)(struct tcp_sock *tp, u32 ack, + void (*cong_avoid)(struct sock *sk, u32 ack, u32 rtt, u32 in_flight, int good_ack); /* round trip time sample per acked packet (optional) */ - void (*rtt_sample)(struct tcp_sock *tp, u32 usrtt); + void (*rtt_sample)(struct sock *sk, u32 usrtt); /* call before changing ca_state (optional) */ - void (*set_state)(struct tcp_sock *tp, u8 new_state); + void (*set_state)(struct sock *sk, u8 new_state); /* call when cwnd event occurs (optional) */ - void (*cwnd_event)(struct tcp_sock *tp, enum tcp_ca_event ev); + void (*cwnd_event)(struct sock *sk, enum tcp_ca_event ev); /* new value of cwnd after loss (optional) */ - u32 (*undo_cwnd)(struct tcp_sock *tp); + u32 (*undo_cwnd)(struct sock *sk); /* hook for packet ack accounting (optional) */ - void (*pkts_acked)(struct tcp_sock *tp, u32 num_acked); - /* get info for tcp_diag (optional) */ - void (*get_info)(struct tcp_sock *tp, u32 ext, struct sk_buff *skb); + void (*pkts_acked)(struct sock *sk, u32 num_acked); + /* get info for inet_diag (optional) */ + void (*get_info)(struct sock *sk, u32 ext, struct sk_buff *skb); char name[TCP_CA_NAME_MAX]; struct module *owner; @@ -1169,30 +701,34 @@ struct tcp_congestion_ops { extern int tcp_register_congestion_control(struct tcp_congestion_ops *type); extern void tcp_unregister_congestion_control(struct tcp_congestion_ops *type); -extern void tcp_init_congestion_control(struct tcp_sock *tp); -extern void tcp_cleanup_congestion_control(struct tcp_sock *tp); +extern void tcp_init_congestion_control(struct sock *sk); +extern void tcp_cleanup_congestion_control(struct sock *sk); extern int tcp_set_default_congestion_control(const char *name); extern void tcp_get_default_congestion_control(char *name); -extern int tcp_set_congestion_control(struct tcp_sock *tp, const char *name); +extern int tcp_set_congestion_control(struct sock *sk, const char *name); extern struct tcp_congestion_ops tcp_init_congestion_ops; -extern u32 tcp_reno_ssthresh(struct tcp_sock *tp); -extern void tcp_reno_cong_avoid(struct tcp_sock *tp, u32 ack, +extern u32 tcp_reno_ssthresh(struct sock *sk); +extern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 rtt, u32 in_flight, int flag); -extern u32 tcp_reno_min_cwnd(struct tcp_sock *tp); +extern u32 tcp_reno_min_cwnd(struct sock *sk); extern struct tcp_congestion_ops tcp_reno; -static inline void tcp_set_ca_state(struct tcp_sock *tp, u8 ca_state) +static inline void tcp_set_ca_state(struct sock *sk, const u8 ca_state) { - if (tp->ca_ops->set_state) - tp->ca_ops->set_state(tp, ca_state); - tp->ca_state = ca_state; + struct inet_connection_sock *icsk = inet_csk(sk); + + if (icsk->icsk_ca_ops->set_state) + icsk->icsk_ca_ops->set_state(sk, ca_state); + icsk->icsk_ca_state = ca_state; } -static inline void tcp_ca_event(struct tcp_sock *tp, enum tcp_ca_event event) +static inline void tcp_ca_event(struct sock *sk, const enum tcp_ca_event event) { - if (tp->ca_ops->cwnd_event) - tp->ca_ops->cwnd_event(tp, event); + const struct inet_connection_sock *icsk = inet_csk(sk); + + if (icsk->icsk_ca_ops->cwnd_event) + icsk->icsk_ca_ops->cwnd_event(sk, event); } /* This determines how many packets are "in the network" to the best @@ -1218,9 +754,10 @@ static __inline__ unsigned int tcp_packets_in_flight(const struct tcp_sock *tp) * The exception is rate halving phase, when cwnd is decreasing towards * ssthresh. */ -static inline __u32 tcp_current_ssthresh(struct tcp_sock *tp) +static inline __u32 tcp_current_ssthresh(const struct sock *sk) { - if ((1<<tp->ca_state)&(TCPF_CA_CWR|TCPF_CA_Recovery)) + const struct tcp_sock *tp = tcp_sk(sk); + if ((1 << inet_csk(sk)->icsk_ca_state) & (TCPF_CA_CWR | TCPF_CA_Recovery)) return tp->snd_ssthresh; else return max(tp->snd_ssthresh, @@ -1236,11 +773,14 @@ static inline void tcp_sync_left_out(struct tcp_sock *tp) tp->left_out = tp->sacked_out + tp->lost_out; } -/* Set slow start threshould and cwnd not falling to slow start */ -static inline void __tcp_enter_cwr(struct tcp_sock *tp) +/* Set slow start threshold and cwnd not falling to slow start */ +static inline void __tcp_enter_cwr(struct sock *sk) { + const struct inet_connection_sock *icsk = inet_csk(sk); + struct tcp_sock *tp = tcp_sk(sk); + tp->undo_marker = 0; - tp->snd_ssthresh = tp->ca_ops->ssthresh(tp); + tp->snd_ssthresh = icsk->icsk_ca_ops->ssthresh(sk); tp->snd_cwnd = min(tp->snd_cwnd, tcp_packets_in_flight(tp) + 1U); tp->snd_cwnd_cnt = 0; @@ -1249,12 +789,14 @@ static inline void __tcp_enter_cwr(struct tcp_sock *tp) TCP_ECN_queue_cwr(tp); } -static inline void tcp_enter_cwr(struct tcp_sock *tp) +static inline void tcp_enter_cwr(struct sock *sk) { + struct tcp_sock *tp = tcp_sk(sk); + tp->prior_ssthresh = 0; - if (tp->ca_state < TCP_CA_CWR) { - __tcp_enter_cwr(tp); - tcp_set_ca_state(tp, TCP_CA_CWR); + if (inet_csk(sk)->icsk_ca_state < TCP_CA_CWR) { + __tcp_enter_cwr(sk); + tcp_set_ca_state(sk, TCP_CA_CWR); } } @@ -1277,8 +819,10 @@ static __inline__ void tcp_minshall_update(struct tcp_sock *tp, int mss, static __inline__ void tcp_check_probe_timer(struct sock *sk, struct tcp_sock *tp) { - if (!tp->packets_out && !tp->pending) - tcp_reset_xmit_timer(sk, TCP_TIME_PROBE0, tp->rto); + const struct inet_connection_sock *icsk = inet_csk(sk); + if (!tp->packets_out && !icsk->icsk_pending) + inet_csk_reset_xmit_timer(sk, ICSK_TIME_PROBE0, + icsk->icsk_rto, TCP_RTO_MAX); } static __inline__ void tcp_push_pending_frames(struct sock *sk, @@ -1297,9 +841,6 @@ static __inline__ void tcp_update_wl(struct tcp_sock *tp, u32 ack, u32 seq) tp->snd_wl1 = seq; } -extern void tcp_destroy_sock(struct sock *sk); - - /* * Calculate(/check) TCP checksum */ @@ -1359,8 +900,10 @@ static __inline__ int tcp_prequeue(struct sock *sk, struct sk_buff *skb) tp->ucopy.memory = 0; } else if (skb_queue_len(&tp->ucopy.prequeue) == 1) { wake_up_interruptible(sk->sk_sleep); - if (!tcp_ack_scheduled(tp)) - tcp_reset_xmit_timer(sk, TCP_TIME_DACK, (3*TCP_RTO_MIN)/4); + if (!inet_csk_ack_scheduled(sk)) + inet_csk_reset_xmit_timer(sk, ICSK_TIME_DACK, + (3 * TCP_RTO_MIN) / 4, + TCP_RTO_MAX); } return 1; } @@ -1393,9 +936,9 @@ static __inline__ void tcp_set_state(struct sock *sk, int state) TCP_INC_STATS(TCP_MIB_ESTABRESETS); sk->sk_prot->unhash(sk); - if (tcp_sk(sk)->bind_hash && + if (inet_csk(sk)->icsk_bind_hash && !(sk->sk_userlocks & SOCK_BINDPORT_LOCK)) - tcp_put_port(sk); + inet_put_port(&tcp_hashinfo, sk); /* fall through */ default: if (oldstate==TCP_ESTABLISHED) @@ -1422,7 +965,7 @@ static __inline__ void tcp_done(struct sock *sk) if (!sock_flag(sk, SOCK_DEAD)) sk->sk_state_change(sk); else - tcp_destroy_sock(sk); + inet_csk_destroy_sock(sk); } static __inline__ void tcp_sack_reset(struct tcp_options_received *rx_opt) @@ -1524,54 +1067,6 @@ static inline int tcp_full_space(const struct sock *sk) return tcp_win_from_space(sk->sk_rcvbuf); } -static inline void tcp_acceptq_queue(struct sock *sk, struct request_sock *req, - struct sock *child) -{ - reqsk_queue_add(&tcp_sk(sk)->accept_queue, req, sk, child); -} - -static inline void -tcp_synq_removed(struct sock *sk, struct request_sock *req) -{ - if (reqsk_queue_removed(&tcp_sk(sk)->accept_queue, req) == 0) - tcp_delete_keepalive_timer(sk); -} - -static inline void tcp_synq_added(struct sock *sk) -{ - if (reqsk_queue_added(&tcp_sk(sk)->accept_queue) == 0) - tcp_reset_keepalive_timer(sk, TCP_TIMEOUT_INIT); -} - -static inline int tcp_synq_len(struct sock *sk) -{ - return reqsk_queue_len(&tcp_sk(sk)->accept_queue); -} - -static inline int tcp_synq_young(struct sock *sk) -{ - return reqsk_queue_len_young(&tcp_sk(sk)->accept_queue); -} - -static inline int tcp_synq_is_full(struct sock *sk) -{ - return reqsk_queue_is_full(&tcp_sk(sk)->accept_queue); -} - -static inline void tcp_synq_unlink(struct tcp_sock *tp, struct request_sock *req, - struct request_sock **prev) -{ - reqsk_queue_unlink(&tp->accept_queue, req, prev); -} - -static inline void tcp_synq_drop(struct sock *sk, struct request_sock *req, - struct request_sock **prev) -{ - tcp_synq_unlink(tcp_sk(sk), req, prev); - tcp_synq_removed(sk, req); - reqsk_free(req); -} - static __inline__ void tcp_openreq_init(struct request_sock *req, struct tcp_options_received *rx_opt, struct sk_buff *skb) @@ -1593,27 +1088,6 @@ static __inline__ void tcp_openreq_init(struct request_sock *req, extern void tcp_enter_memory_pressure(void); -extern void tcp_listen_wlock(void); - -/* - We may sleep inside this lock. - * - If sleeping is not required (or called from BH), - * use plain read_(un)lock(&tcp_lhash_lock). - */ - -static inline void tcp_listen_lock(void) -{ - /* read_lock synchronizes to candidates to writers */ - read_lock(&tcp_lhash_lock); - atomic_inc(&tcp_lhash_users); - read_unlock(&tcp_lhash_lock); -} - -static inline void tcp_listen_unlock(void) -{ - if (atomic_dec_and_test(&tcp_lhash_users)) - wake_up(&tcp_lhash_wait); -} - static inline int keepalive_intvl_when(const struct tcp_sock *tp) { return tp->keepalive_intvl ? : sysctl_tcp_keepalive_intvl; @@ -1624,12 +1098,13 @@ static inline int keepalive_time_when(const struct tcp_sock *tp) return tp->keepalive_time ? : sysctl_tcp_keepalive_time; } -static inline int tcp_fin_time(const struct tcp_sock *tp) +static inline int tcp_fin_time(const struct sock *sk) { - int fin_timeout = tp->linger2 ? : sysctl_tcp_fin_timeout; + int fin_timeout = tcp_sk(sk)->linger2 ? : sysctl_tcp_fin_timeout; + const int rto = inet_csk(sk)->icsk_rto; - if (fin_timeout < (tp->rto<<2) - (tp->rto>>1)) - fin_timeout = (tp->rto<<2) - (tp->rto>>1); + if (fin_timeout < (rto << 2) - (rto >> 1)) + fin_timeout = (rto << 2) - (rto >> 1); return fin_timeout; } @@ -1658,15 +1133,6 @@ static inline int tcp_paws_check(const struct tcp_options_received *rx_opt, int return 1; } -static inline void tcp_v4_setup_caps(struct sock *sk, struct dst_entry *dst) -{ - sk->sk_route_caps = dst->dev->features; - if (sk->sk_route_caps & NETIF_F_TSO) { - if (sock_flag(sk, SOCK_NO_LARGESEND) || dst->header_len) - sk->sk_route_caps &= ~NETIF_F_TSO; - } -} - #define TCP_CHECK_TIMER(sk) do { } while (0) static inline int tcp_use_frto(const struct sock *sk) @@ -1718,4 +1184,16 @@ struct tcp_iter_state { extern int tcp_proc_register(struct tcp_seq_afinfo *afinfo); extern void tcp_proc_unregister(struct tcp_seq_afinfo *afinfo); +extern struct request_sock_ops tcp_request_sock_ops; + +extern int tcp_v4_destroy_sock(struct sock *sk); + +#ifdef CONFIG_PROC_FS +extern int tcp4_proc_init(void); +extern void tcp4_proc_exit(void); +#endif + +extern void tcp_v4_init(struct net_proto_family *ops); +extern void tcp_init(void); + #endif /* _TCP_H */ diff --git a/include/net/tcp_ecn.h b/include/net/tcp_ecn.h index 64980ee8c92a..c6b84397448d 100644 --- a/include/net/tcp_ecn.h +++ b/include/net/tcp_ecn.h @@ -88,7 +88,7 @@ static inline void TCP_ECN_check_ce(struct tcp_sock *tp, struct sk_buff *skb) * it is surely retransmit. It is not in ECN RFC, * but Linux follows this rule. */ else if (INET_ECN_is_not_ect((TCP_SKB_CB(skb)->flags))) - tcp_enter_quickack_mode(tp); + tcp_enter_quickack_mode((struct sock *)tp); } } diff --git a/include/net/tcp_states.h b/include/net/tcp_states.h new file mode 100644 index 000000000000..b9d4176b2d15 --- /dev/null +++ b/include/net/tcp_states.h @@ -0,0 +1,34 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * Definitions for the TCP protocol sk_state field. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef _LINUX_TCP_STATES_H +#define _LINUX_TCP_STATES_H + +enum { + TCP_ESTABLISHED = 1, + TCP_SYN_SENT, + TCP_SYN_RECV, + TCP_FIN_WAIT1, + TCP_FIN_WAIT2, + TCP_TIME_WAIT, + TCP_CLOSE, + TCP_CLOSE_WAIT, + TCP_LAST_ACK, + TCP_LISTEN, + TCP_CLOSING, /* Now a valid state */ + + TCP_MAX_STATES /* Leave at the end! */ +}; + +#define TCP_STATE_MASK 0xF + +#endif /* _LINUX_TCP_STATES_H */ diff --git a/include/net/udp.h b/include/net/udp.h index ac229b761dbc..107b9d791a1f 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -94,6 +94,11 @@ struct udp_iter_state { struct seq_operations seq_ops; }; +#ifdef CONFIG_PROC_FS extern int udp_proc_register(struct udp_seq_afinfo *afinfo); extern void udp_proc_unregister(struct udp_seq_afinfo *afinfo); + +extern int udp4_proc_init(void); +extern void udp4_proc_exit(void); +#endif #endif /* _UDP_H */ diff --git a/include/net/x25.h b/include/net/x25.h index 8b39b98876e8..fee62ff8c194 100644 --- a/include/net/x25.h +++ b/include/net/x25.h @@ -175,7 +175,7 @@ extern void x25_kill_by_neigh(struct x25_neigh *); /* x25_dev.c */ extern void x25_send_frame(struct sk_buff *, struct x25_neigh *); -extern int x25_lapb_receive_frame(struct sk_buff *, struct net_device *, struct packet_type *); +extern int x25_lapb_receive_frame(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *); extern void x25_establish_link(struct x25_neigh *); extern void x25_terminate_link(struct x25_neigh *); diff --git a/include/net/x25device.h b/include/net/x25device.h index cf36a20ea3c5..1a318374faef 100644 --- a/include/net/x25device.h +++ b/include/net/x25device.h @@ -5,11 +5,9 @@ #include <linux/if_packet.h> #include <linux/skbuff.h> -static inline unsigned short x25_type_trans(struct sk_buff *skb, - struct net_device *dev) +static inline __be16 x25_type_trans(struct sk_buff *skb, struct net_device *dev) { skb->mac.raw = skb->data; - skb->input_dev = skb->dev = dev; skb->pkt_type = PACKET_HOST; return htons(ETH_P_X25); diff --git a/include/net/xfrm.h b/include/net/xfrm.h index 029522a4ceda..a9d0d8c5dfbf 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -803,7 +803,7 @@ struct xfrm_algo_desc { /* XFRM tunnel handlers. */ struct xfrm_tunnel { int (*handler)(struct sk_buff *skb); - void (*err_handler)(struct sk_buff *skb, void *info); + void (*err_handler)(struct sk_buff *skb, __u32 info); }; struct xfrm6_tunnel { @@ -818,7 +818,6 @@ extern void xfrm6_init(void); extern void xfrm6_fini(void); extern void xfrm_state_init(void); extern void xfrm4_state_init(void); -extern void xfrm4_state_fini(void); extern void xfrm6_state_init(void); extern void xfrm6_state_fini(void); diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h index 0190e766e1a7..b707a603351b 100644 --- a/include/pcmcia/ds.h +++ b/include/pcmcia/ds.h @@ -16,10 +16,13 @@ #ifndef _LINUX_DS_H #define _LINUX_DS_H +#ifdef __KERNEL__ +#include <linux/mod_devicetable.h> +#endif + #include <pcmcia/bulkmem.h> #include <pcmcia/cs_types.h> #include <pcmcia/device_id.h> -#include <linux/mod_devicetable.h> typedef struct tuple_parse_t { tuple_t tuple; diff --git a/include/rdma/ib_cache.h b/include/rdma/ib_cache.h new file mode 100644 index 000000000000..5bf9834f7dca --- /dev/null +++ b/include/rdma/ib_cache.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2004 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Intel Corporation. All rights reserved. + * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_cache.h 1349 2004-12-16 21:09:43Z roland $ + */ + +#ifndef _IB_CACHE_H +#define _IB_CACHE_H + +#include <rdma/ib_verbs.h> + +/** + * ib_get_cached_gid - Returns a cached GID table entry + * @device: The device to query. + * @port_num: The port number of the device to query. + * @index: The index into the cached GID table to query. + * @gid: The GID value found at the specified index. + * + * ib_get_cached_gid() fetches the specified GID table entry stored in + * the local software cache. + */ +int ib_get_cached_gid(struct ib_device *device, + u8 port_num, + int index, + union ib_gid *gid); + +/** + * ib_find_cached_gid - Returns the port number and GID table index where + * a specified GID value occurs. + * @device: The device to query. + * @gid: The GID value to search for. + * @port_num: The port number of the device where the GID value was found. + * @index: The index into the cached GID table where the GID was found. This + * parameter may be NULL. + * + * ib_find_cached_gid() searches for the specified GID value in + * the local software cache. + */ +int ib_find_cached_gid(struct ib_device *device, + union ib_gid *gid, + u8 *port_num, + u16 *index); + +/** + * ib_get_cached_pkey - Returns a cached PKey table entry + * @device: The device to query. + * @port_num: The port number of the device to query. + * @index: The index into the cached PKey table to query. + * @pkey: The PKey value found at the specified index. + * + * ib_get_cached_pkey() fetches the specified PKey table entry stored in + * the local software cache. + */ +int ib_get_cached_pkey(struct ib_device *device_handle, + u8 port_num, + int index, + u16 *pkey); + +/** + * ib_find_cached_pkey - Returns the PKey table index where a specified + * PKey value occurs. + * @device: The device to query. + * @port_num: The port number of the device to search for the PKey. + * @pkey: The PKey value to search for. + * @index: The index into the cached PKey table where the PKey was found. + * + * ib_find_cached_pkey() searches the specified PKey table in + * the local software cache. + */ +int ib_find_cached_pkey(struct ib_device *device, + u8 port_num, + u16 pkey, + u16 *index); + +#endif /* _IB_CACHE_H */ diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h new file mode 100644 index 000000000000..77fe9039209b --- /dev/null +++ b/include/rdma/ib_cm.h @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2004 Intel Corporation. All rights reserved. + * Copyright (c) 2004 Topspin Corporation. All rights reserved. + * Copyright (c) 2004 Voltaire Corporation. All rights reserved. + * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_cm.h 2730 2005-06-28 16:43:03Z sean.hefty $ + */ +#if !defined(IB_CM_H) +#define IB_CM_H + +#include <rdma/ib_mad.h> +#include <rdma/ib_sa.h> + +enum ib_cm_state { + IB_CM_IDLE, + IB_CM_LISTEN, + IB_CM_REQ_SENT, + IB_CM_REQ_RCVD, + IB_CM_MRA_REQ_SENT, + IB_CM_MRA_REQ_RCVD, + IB_CM_REP_SENT, + IB_CM_REP_RCVD, + IB_CM_MRA_REP_SENT, + IB_CM_MRA_REP_RCVD, + IB_CM_ESTABLISHED, + IB_CM_DREQ_SENT, + IB_CM_DREQ_RCVD, + IB_CM_TIMEWAIT, + IB_CM_SIDR_REQ_SENT, + IB_CM_SIDR_REQ_RCVD +}; + +enum ib_cm_lap_state { + IB_CM_LAP_IDLE, + IB_CM_LAP_SENT, + IB_CM_LAP_RCVD, + IB_CM_MRA_LAP_SENT, + IB_CM_MRA_LAP_RCVD, +}; + +enum ib_cm_event_type { + IB_CM_REQ_ERROR, + IB_CM_REQ_RECEIVED, + IB_CM_REP_ERROR, + IB_CM_REP_RECEIVED, + IB_CM_RTU_RECEIVED, + IB_CM_USER_ESTABLISHED, + IB_CM_DREQ_ERROR, + IB_CM_DREQ_RECEIVED, + IB_CM_DREP_RECEIVED, + IB_CM_TIMEWAIT_EXIT, + IB_CM_MRA_RECEIVED, + IB_CM_REJ_RECEIVED, + IB_CM_LAP_ERROR, + IB_CM_LAP_RECEIVED, + IB_CM_APR_RECEIVED, + IB_CM_SIDR_REQ_ERROR, + IB_CM_SIDR_REQ_RECEIVED, + IB_CM_SIDR_REP_RECEIVED +}; + +enum ib_cm_data_size { + IB_CM_REQ_PRIVATE_DATA_SIZE = 92, + IB_CM_MRA_PRIVATE_DATA_SIZE = 222, + IB_CM_REJ_PRIVATE_DATA_SIZE = 148, + IB_CM_REP_PRIVATE_DATA_SIZE = 196, + IB_CM_RTU_PRIVATE_DATA_SIZE = 224, + IB_CM_DREQ_PRIVATE_DATA_SIZE = 220, + IB_CM_DREP_PRIVATE_DATA_SIZE = 224, + IB_CM_REJ_ARI_LENGTH = 72, + IB_CM_LAP_PRIVATE_DATA_SIZE = 168, + IB_CM_APR_PRIVATE_DATA_SIZE = 148, + IB_CM_APR_INFO_LENGTH = 72, + IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE = 216, + IB_CM_SIDR_REP_PRIVATE_DATA_SIZE = 136, + IB_CM_SIDR_REP_INFO_LENGTH = 72 +}; + +struct ib_cm_id; + +struct ib_cm_req_event_param { + struct ib_cm_id *listen_id; + struct ib_device *device; + u8 port; + + struct ib_sa_path_rec *primary_path; + struct ib_sa_path_rec *alternate_path; + + __be64 remote_ca_guid; + u32 remote_qkey; + u32 remote_qpn; + enum ib_qp_type qp_type; + + u32 starting_psn; + u8 responder_resources; + u8 initiator_depth; + unsigned int local_cm_response_timeout:5; + unsigned int flow_control:1; + unsigned int remote_cm_response_timeout:5; + unsigned int retry_count:3; + unsigned int rnr_retry_count:3; + unsigned int srq:1; +}; + +struct ib_cm_rep_event_param { + __be64 remote_ca_guid; + u32 remote_qkey; + u32 remote_qpn; + u32 starting_psn; + u8 responder_resources; + u8 initiator_depth; + unsigned int target_ack_delay:5; + unsigned int failover_accepted:2; + unsigned int flow_control:1; + unsigned int rnr_retry_count:3; + unsigned int srq:1; +}; + +enum ib_cm_rej_reason { + IB_CM_REJ_NO_QP = 1, + IB_CM_REJ_NO_EEC = 2, + IB_CM_REJ_NO_RESOURCES = 3, + IB_CM_REJ_TIMEOUT = 4, + IB_CM_REJ_UNSUPPORTED = 5, + IB_CM_REJ_INVALID_COMM_ID = 6, + IB_CM_REJ_INVALID_COMM_INSTANCE = 7, + IB_CM_REJ_INVALID_SERVICE_ID = 8, + IB_CM_REJ_INVALID_TRANSPORT_TYPE = 9, + IB_CM_REJ_STALE_CONN = 10, + IB_CM_REJ_RDC_NOT_EXIST = 11, + IB_CM_REJ_INVALID_GID = 12, + IB_CM_REJ_INVALID_LID = 13, + IB_CM_REJ_INVALID_SL = 14, + IB_CM_REJ_INVALID_TRAFFIC_CLASS = 15, + IB_CM_REJ_INVALID_HOP_LIMIT = 16, + IB_CM_REJ_INVALID_PACKET_RATE = 17, + IB_CM_REJ_INVALID_ALT_GID = 18, + IB_CM_REJ_INVALID_ALT_LID = 19, + IB_CM_REJ_INVALID_ALT_SL = 20, + IB_CM_REJ_INVALID_ALT_TRAFFIC_CLASS = 21, + IB_CM_REJ_INVALID_ALT_HOP_LIMIT = 22, + IB_CM_REJ_INVALID_ALT_PACKET_RATE = 23, + IB_CM_REJ_PORT_CM_REDIRECT = 24, + IB_CM_REJ_PORT_REDIRECT = 25, + IB_CM_REJ_INVALID_MTU = 26, + IB_CM_REJ_INSUFFICIENT_RESP_RESOURCES = 27, + IB_CM_REJ_CONSUMER_DEFINED = 28, + IB_CM_REJ_INVALID_RNR_RETRY = 29, + IB_CM_REJ_DUPLICATE_LOCAL_COMM_ID = 30, + IB_CM_REJ_INVALID_CLASS_VERSION = 31, + IB_CM_REJ_INVALID_FLOW_LABEL = 32, + IB_CM_REJ_INVALID_ALT_FLOW_LABEL = 33 +}; + +struct ib_cm_rej_event_param { + enum ib_cm_rej_reason reason; + void *ari; + u8 ari_length; +}; + +struct ib_cm_mra_event_param { + u8 service_timeout; +}; + +struct ib_cm_lap_event_param { + struct ib_sa_path_rec *alternate_path; +}; + +enum ib_cm_apr_status { + IB_CM_APR_SUCCESS, + IB_CM_APR_INVALID_COMM_ID, + IB_CM_APR_UNSUPPORTED, + IB_CM_APR_REJECT, + IB_CM_APR_REDIRECT, + IB_CM_APR_IS_CURRENT, + IB_CM_APR_INVALID_QPN_EECN, + IB_CM_APR_INVALID_LID, + IB_CM_APR_INVALID_GID, + IB_CM_APR_INVALID_FLOW_LABEL, + IB_CM_APR_INVALID_TCLASS, + IB_CM_APR_INVALID_HOP_LIMIT, + IB_CM_APR_INVALID_PACKET_RATE, + IB_CM_APR_INVALID_SL +}; + +struct ib_cm_apr_event_param { + enum ib_cm_apr_status ap_status; + void *apr_info; + u8 info_len; +}; + +struct ib_cm_sidr_req_event_param { + struct ib_cm_id *listen_id; + struct ib_device *device; + u8 port; + u16 pkey; +}; + +enum ib_cm_sidr_status { + IB_SIDR_SUCCESS, + IB_SIDR_UNSUPPORTED, + IB_SIDR_REJECT, + IB_SIDR_NO_QP, + IB_SIDR_REDIRECT, + IB_SIDR_UNSUPPORTED_VERSION +}; + +struct ib_cm_sidr_rep_event_param { + enum ib_cm_sidr_status status; + u32 qkey; + u32 qpn; + void *info; + u8 info_len; + +}; + +struct ib_cm_event { + enum ib_cm_event_type event; + union { + struct ib_cm_req_event_param req_rcvd; + struct ib_cm_rep_event_param rep_rcvd; + /* No data for RTU received events. */ + struct ib_cm_rej_event_param rej_rcvd; + struct ib_cm_mra_event_param mra_rcvd; + struct ib_cm_lap_event_param lap_rcvd; + struct ib_cm_apr_event_param apr_rcvd; + /* No data for DREQ/DREP received events. */ + struct ib_cm_sidr_req_event_param sidr_req_rcvd; + struct ib_cm_sidr_rep_event_param sidr_rep_rcvd; + enum ib_wc_status send_status; + } param; + + void *private_data; +}; + +/** + * ib_cm_handler - User-defined callback to process communication events. + * @cm_id: Communication identifier associated with the reported event. + * @event: Information about the communication event. + * + * IB_CM_REQ_RECEIVED and IB_CM_SIDR_REQ_RECEIVED communication events + * generated as a result of listen requests result in the allocation of a + * new @cm_id. The new @cm_id is returned to the user through this callback. + * Clients are responsible for destroying the new @cm_id. For peer-to-peer + * IB_CM_REQ_RECEIVED and all other events, the returned @cm_id corresponds + * to a user's existing communication identifier. + * + * Users may not call ib_destroy_cm_id while in the context of this callback; + * however, returning a non-zero value instructs the communication manager to + * destroy the @cm_id after the callback completes. + */ +typedef int (*ib_cm_handler)(struct ib_cm_id *cm_id, + struct ib_cm_event *event); + +struct ib_cm_id { + ib_cm_handler cm_handler; + void *context; + __be64 service_id; + __be64 service_mask; + enum ib_cm_state state; /* internal CM/debug use */ + enum ib_cm_lap_state lap_state; /* internal CM/debug use */ + __be32 local_id; + __be32 remote_id; +}; + +/** + * ib_create_cm_id - Allocate a communication identifier. + * @cm_handler: Callback invoked to notify the user of CM events. + * @context: User specified context associated with the communication + * identifier. + * + * Communication identifiers are used to track connection states, service + * ID resolution requests, and listen requests. + */ +struct ib_cm_id *ib_create_cm_id(ib_cm_handler cm_handler, + void *context); + +/** + * ib_destroy_cm_id - Destroy a connection identifier. + * @cm_id: Connection identifier to destroy. + * + * This call blocks until the connection identifier is destroyed. + */ +void ib_destroy_cm_id(struct ib_cm_id *cm_id); + +#define IB_SERVICE_ID_AGN_MASK __constant_cpu_to_be64(0xFF00000000000000ULL) +#define IB_CM_ASSIGN_SERVICE_ID __constant_cpu_to_be64(0x0200000000000000ULL) + +/** + * ib_cm_listen - Initiates listening on the specified service ID for + * connection and service ID resolution requests. + * @cm_id: Connection identifier associated with the listen request. + * @service_id: Service identifier matched against incoming connection + * and service ID resolution requests. The service ID should be specified + * network-byte order. If set to IB_CM_ASSIGN_SERVICE_ID, the CM will + * assign a service ID to the caller. + * @service_mask: Mask applied to service ID used to listen across a + * range of service IDs. If set to 0, the service ID is matched + * exactly. This parameter is ignored if %service_id is set to + * IB_CM_ASSIGN_SERVICE_ID. + */ +int ib_cm_listen(struct ib_cm_id *cm_id, + __be64 service_id, + __be64 service_mask); + +struct ib_cm_req_param { + struct ib_sa_path_rec *primary_path; + struct ib_sa_path_rec *alternate_path; + __be64 service_id; + u32 qp_num; + enum ib_qp_type qp_type; + u32 starting_psn; + const void *private_data; + u8 private_data_len; + u8 peer_to_peer; + u8 responder_resources; + u8 initiator_depth; + u8 remote_cm_response_timeout; + u8 flow_control; + u8 local_cm_response_timeout; + u8 retry_count; + u8 rnr_retry_count; + u8 max_cm_retries; + u8 srq; +}; + +/** + * ib_send_cm_req - Sends a connection request to the remote node. + * @cm_id: Connection identifier that will be associated with the + * connection request. + * @param: Connection request information needed to establish the + * connection. + */ +int ib_send_cm_req(struct ib_cm_id *cm_id, + struct ib_cm_req_param *param); + +struct ib_cm_rep_param { + u32 qp_num; + u32 starting_psn; + const void *private_data; + u8 private_data_len; + u8 responder_resources; + u8 initiator_depth; + u8 target_ack_delay; + u8 failover_accepted; + u8 flow_control; + u8 rnr_retry_count; + u8 srq; +}; + +/** + * ib_send_cm_rep - Sends a connection reply in response to a connection + * request. + * @cm_id: Connection identifier that will be associated with the + * connection request. + * @param: Connection reply information needed to establish the + * connection. + */ +int ib_send_cm_rep(struct ib_cm_id *cm_id, + struct ib_cm_rep_param *param); + +/** + * ib_send_cm_rtu - Sends a connection ready to use message in response + * to a connection reply message. + * @cm_id: Connection identifier associated with the connection request. + * @private_data: Optional user-defined private data sent with the + * ready to use message. + * @private_data_len: Size of the private data buffer, in bytes. + */ +int ib_send_cm_rtu(struct ib_cm_id *cm_id, + const void *private_data, + u8 private_data_len); + +/** + * ib_send_cm_dreq - Sends a disconnection request for an existing + * connection. + * @cm_id: Connection identifier associated with the connection being + * released. + * @private_data: Optional user-defined private data sent with the + * disconnection request message. + * @private_data_len: Size of the private data buffer, in bytes. + */ +int ib_send_cm_dreq(struct ib_cm_id *cm_id, + const void *private_data, + u8 private_data_len); + +/** + * ib_send_cm_drep - Sends a disconnection reply to a disconnection request. + * @cm_id: Connection identifier associated with the connection being + * released. + * @private_data: Optional user-defined private data sent with the + * disconnection reply message. + * @private_data_len: Size of the private data buffer, in bytes. + * + * If the cm_id is in the correct state, the CM will transition the connection + * to the timewait state, even if an error occurs sending the DREP message. + */ +int ib_send_cm_drep(struct ib_cm_id *cm_id, + const void *private_data, + u8 private_data_len); + +/** + * ib_cm_establish - Forces a connection state to established. + * @cm_id: Connection identifier to transition to established. + * + * This routine should be invoked by users who receive messages on a + * connected QP before an RTU has been received. + */ +int ib_cm_establish(struct ib_cm_id *cm_id); + +/** + * ib_send_cm_rej - Sends a connection rejection message to the + * remote node. + * @cm_id: Connection identifier associated with the connection being + * rejected. + * @reason: Reason for the connection request rejection. + * @ari: Optional additional rejection information. + * @ari_length: Size of the additional rejection information, in bytes. + * @private_data: Optional user-defined private data sent with the + * rejection message. + * @private_data_len: Size of the private data buffer, in bytes. + */ +int ib_send_cm_rej(struct ib_cm_id *cm_id, + enum ib_cm_rej_reason reason, + void *ari, + u8 ari_length, + const void *private_data, + u8 private_data_len); + +/** + * ib_send_cm_mra - Sends a message receipt acknowledgement to a connection + * message. + * @cm_id: Connection identifier associated with the connection message. + * @service_timeout: The maximum time required for the sender to reply to + * to the connection message. + * @private_data: Optional user-defined private data sent with the + * message receipt acknowledgement. + * @private_data_len: Size of the private data buffer, in bytes. + */ +int ib_send_cm_mra(struct ib_cm_id *cm_id, + u8 service_timeout, + const void *private_data, + u8 private_data_len); + +/** + * ib_send_cm_lap - Sends a load alternate path request. + * @cm_id: Connection identifier associated with the load alternate path + * message. + * @alternate_path: A path record that identifies the alternate path to + * load. + * @private_data: Optional user-defined private data sent with the + * load alternate path message. + * @private_data_len: Size of the private data buffer, in bytes. + */ +int ib_send_cm_lap(struct ib_cm_id *cm_id, + struct ib_sa_path_rec *alternate_path, + const void *private_data, + u8 private_data_len); + +/** + * ib_cm_init_qp_attr - Initializes the QP attributes for use in transitioning + * to a specified QP state. + * @cm_id: Communication identifier associated with the QP attributes to + * initialize. + * @qp_attr: On input, specifies the desired QP state. On output, the + * mandatory and desired optional attributes will be set in order to + * modify the QP to the specified state. + * @qp_attr_mask: The QP attribute mask that may be used to transition the + * QP to the specified state. + * + * Users must set the @qp_attr->qp_state to the desired QP state. This call + * will set all required attributes for the given transition, along with + * known optional attributes. Users may override the attributes returned from + * this call before calling ib_modify_qp. + */ +int ib_cm_init_qp_attr(struct ib_cm_id *cm_id, + struct ib_qp_attr *qp_attr, + int *qp_attr_mask); + +/** + * ib_send_cm_apr - Sends an alternate path response message in response to + * a load alternate path request. + * @cm_id: Connection identifier associated with the alternate path response. + * @status: Reply status sent with the alternate path response. + * @info: Optional additional information sent with the alternate path + * response. + * @info_length: Size of the additional information, in bytes. + * @private_data: Optional user-defined private data sent with the + * alternate path response message. + * @private_data_len: Size of the private data buffer, in bytes. + */ +int ib_send_cm_apr(struct ib_cm_id *cm_id, + enum ib_cm_apr_status status, + void *info, + u8 info_length, + const void *private_data, + u8 private_data_len); + +struct ib_cm_sidr_req_param { + struct ib_sa_path_rec *path; + __be64 service_id; + int timeout_ms; + const void *private_data; + u8 private_data_len; + u8 max_cm_retries; + u16 pkey; +}; + +/** + * ib_send_cm_sidr_req - Sends a service ID resolution request to the + * remote node. + * @cm_id: Communication identifier that will be associated with the + * service ID resolution request. + * @param: Service ID resolution request information. + */ +int ib_send_cm_sidr_req(struct ib_cm_id *cm_id, + struct ib_cm_sidr_req_param *param); + +struct ib_cm_sidr_rep_param { + u32 qp_num; + u32 qkey; + enum ib_cm_sidr_status status; + const void *info; + u8 info_length; + const void *private_data; + u8 private_data_len; +}; + +/** + * ib_send_cm_sidr_rep - Sends a service ID resolution request to the + * remote node. + * @cm_id: Communication identifier associated with the received service ID + * resolution request. + * @param: Service ID resolution reply information. + */ +int ib_send_cm_sidr_rep(struct ib_cm_id *cm_id, + struct ib_cm_sidr_rep_param *param); + +#endif /* IB_CM_H */ diff --git a/include/rdma/ib_fmr_pool.h b/include/rdma/ib_fmr_pool.h new file mode 100644 index 000000000000..86b7e93f198b --- /dev/null +++ b/include/rdma/ib_fmr_pool.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2004 Topspin Corporation. All rights reserved. + * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_fmr_pool.h 2730 2005-06-28 16:43:03Z sean.hefty $ + */ + +#if !defined(IB_FMR_POOL_H) +#define IB_FMR_POOL_H + +#include <rdma/ib_verbs.h> + +struct ib_fmr_pool; + +/** + * struct ib_fmr_pool_param - Parameters for creating FMR pool + * @max_pages_per_fmr:Maximum number of pages per map request. + * @access:Access flags for FMRs in pool. + * @pool_size:Number of FMRs to allocate for pool. + * @dirty_watermark:Flush is triggered when @dirty_watermark dirty + * FMRs are present. + * @flush_function:Callback called when unmapped FMRs are flushed and + * more FMRs are possibly available for mapping + * @flush_arg:Context passed to user's flush function. + * @cache:If set, FMRs may be reused after unmapping for identical map + * requests. + */ +struct ib_fmr_pool_param { + int max_pages_per_fmr; + enum ib_access_flags access; + int pool_size; + int dirty_watermark; + void (*flush_function)(struct ib_fmr_pool *pool, + void * arg); + void *flush_arg; + unsigned cache:1; +}; + +struct ib_pool_fmr { + struct ib_fmr *fmr; + struct ib_fmr_pool *pool; + struct list_head list; + struct hlist_node cache_node; + int ref_count; + int remap_count; + u64 io_virtual_address; + int page_list_len; + u64 page_list[0]; +}; + +struct ib_fmr_pool *ib_create_fmr_pool(struct ib_pd *pd, + struct ib_fmr_pool_param *params); + +void ib_destroy_fmr_pool(struct ib_fmr_pool *pool); + +int ib_flush_fmr_pool(struct ib_fmr_pool *pool); + +struct ib_pool_fmr *ib_fmr_pool_map_phys(struct ib_fmr_pool *pool_handle, + u64 *page_list, + int list_len, + u64 *io_virtual_address); + +int ib_fmr_pool_unmap(struct ib_pool_fmr *fmr); + +#endif /* IB_FMR_POOL_H */ diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h new file mode 100644 index 000000000000..fc6b1c18ffc6 --- /dev/null +++ b/include/rdma/ib_mad.h @@ -0,0 +1,579 @@ +/* + * Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. + * Copyright (c) 2004 Infinicon Corporation. All rights reserved. + * Copyright (c) 2004 Intel Corporation. All rights reserved. + * Copyright (c) 2004 Topspin Corporation. All rights reserved. + * Copyright (c) 2004 Voltaire Corporation. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_mad.h 2775 2005-07-02 13:42:12Z halr $ + */ + +#if !defined( IB_MAD_H ) +#define IB_MAD_H + +#include <linux/pci.h> + +#include <rdma/ib_verbs.h> + +/* Management base version */ +#define IB_MGMT_BASE_VERSION 1 + +/* Management classes */ +#define IB_MGMT_CLASS_SUBN_LID_ROUTED 0x01 +#define IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE 0x81 +#define IB_MGMT_CLASS_SUBN_ADM 0x03 +#define IB_MGMT_CLASS_PERF_MGMT 0x04 +#define IB_MGMT_CLASS_BM 0x05 +#define IB_MGMT_CLASS_DEVICE_MGMT 0x06 +#define IB_MGMT_CLASS_CM 0x07 +#define IB_MGMT_CLASS_SNMP 0x08 +#define IB_MGMT_CLASS_VENDOR_RANGE2_START 0x30 +#define IB_MGMT_CLASS_VENDOR_RANGE2_END 0x4F + +#define IB_OPENIB_OUI (0x001405) + +/* Management methods */ +#define IB_MGMT_METHOD_GET 0x01 +#define IB_MGMT_METHOD_SET 0x02 +#define IB_MGMT_METHOD_GET_RESP 0x81 +#define IB_MGMT_METHOD_SEND 0x03 +#define IB_MGMT_METHOD_TRAP 0x05 +#define IB_MGMT_METHOD_REPORT 0x06 +#define IB_MGMT_METHOD_REPORT_RESP 0x86 +#define IB_MGMT_METHOD_TRAP_REPRESS 0x07 + +#define IB_MGMT_METHOD_RESP 0x80 + +#define IB_MGMT_MAX_METHODS 128 + +/* RMPP information */ +#define IB_MGMT_RMPP_VERSION 1 + +#define IB_MGMT_RMPP_TYPE_DATA 1 +#define IB_MGMT_RMPP_TYPE_ACK 2 +#define IB_MGMT_RMPP_TYPE_STOP 3 +#define IB_MGMT_RMPP_TYPE_ABORT 4 + +#define IB_MGMT_RMPP_FLAG_ACTIVE 1 +#define IB_MGMT_RMPP_FLAG_FIRST (1<<1) +#define IB_MGMT_RMPP_FLAG_LAST (1<<2) + +#define IB_MGMT_RMPP_NO_RESPTIME 0x1F + +#define IB_MGMT_RMPP_STATUS_SUCCESS 0 +#define IB_MGMT_RMPP_STATUS_RESX 1 +#define IB_MGMT_RMPP_STATUS_ABORT_MIN 118 +#define IB_MGMT_RMPP_STATUS_T2L 118 +#define IB_MGMT_RMPP_STATUS_BAD_LEN 119 +#define IB_MGMT_RMPP_STATUS_BAD_SEG 120 +#define IB_MGMT_RMPP_STATUS_BADT 121 +#define IB_MGMT_RMPP_STATUS_W2S 122 +#define IB_MGMT_RMPP_STATUS_S2B 123 +#define IB_MGMT_RMPP_STATUS_BAD_STATUS 124 +#define IB_MGMT_RMPP_STATUS_UNV 125 +#define IB_MGMT_RMPP_STATUS_TMR 126 +#define IB_MGMT_RMPP_STATUS_UNSPEC 127 +#define IB_MGMT_RMPP_STATUS_ABORT_MAX 127 + +#define IB_QP0 0 +#define IB_QP1 __constant_htonl(1) +#define IB_QP1_QKEY 0x80010000 +#define IB_QP_SET_QKEY 0x80000000 + +struct ib_mad_hdr { + u8 base_version; + u8 mgmt_class; + u8 class_version; + u8 method; + __be16 status; + __be16 class_specific; + __be64 tid; + __be16 attr_id; + __be16 resv; + __be32 attr_mod; +}; + +struct ib_rmpp_hdr { + u8 rmpp_version; + u8 rmpp_type; + u8 rmpp_rtime_flags; + u8 rmpp_status; + __be32 seg_num; + __be32 paylen_newwin; +}; + +typedef u64 __bitwise ib_sa_comp_mask; + +#define IB_SA_COMP_MASK(n) ((__force ib_sa_comp_mask) cpu_to_be64(1ull << n)) + +/* + * ib_sa_hdr and ib_sa_mad structures must be packed because they have + * 64-bit fields that are only 32-bit aligned. 64-bit architectures will + * lay them out wrong otherwise. (And unfortunately they are sent on + * the wire so we can't change the layout) + */ +struct ib_sa_hdr { + __be64 sm_key; + __be16 attr_offset; + __be16 reserved; + ib_sa_comp_mask comp_mask; +} __attribute__ ((packed)); + +struct ib_mad { + struct ib_mad_hdr mad_hdr; + u8 data[232]; +}; + +struct ib_rmpp_mad { + struct ib_mad_hdr mad_hdr; + struct ib_rmpp_hdr rmpp_hdr; + u8 data[220]; +}; + +struct ib_sa_mad { + struct ib_mad_hdr mad_hdr; + struct ib_rmpp_hdr rmpp_hdr; + struct ib_sa_hdr sa_hdr; + u8 data[200]; +} __attribute__ ((packed)); + +struct ib_vendor_mad { + struct ib_mad_hdr mad_hdr; + struct ib_rmpp_hdr rmpp_hdr; + u8 reserved; + u8 oui[3]; + u8 data[216]; +}; + +/** + * ib_mad_send_buf - MAD data buffer and work request for sends. + * @mad: References an allocated MAD data buffer. The size of the data + * buffer is specified in the @send_wr.length field. + * @mapping: DMA mapping information. + * @mad_agent: MAD agent that allocated the buffer. + * @context: User-controlled context fields. + * @send_wr: An initialized work request structure used when sending the MAD. + * The wr_id field of the work request is initialized to reference this + * data structure. + * @sge: A scatter-gather list referenced by the work request. + * + * Users are responsible for initializing the MAD buffer itself, with the + * exception of specifying the payload length field in any RMPP MAD. + */ +struct ib_mad_send_buf { + struct ib_mad *mad; + DECLARE_PCI_UNMAP_ADDR(mapping) + struct ib_mad_agent *mad_agent; + void *context[2]; + struct ib_send_wr send_wr; + struct ib_sge sge; +}; + +/** + * ib_get_rmpp_resptime - Returns the RMPP response time. + * @rmpp_hdr: An RMPP header. + */ +static inline u8 ib_get_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr) +{ + return rmpp_hdr->rmpp_rtime_flags >> 3; +} + +/** + * ib_get_rmpp_flags - Returns the RMPP flags. + * @rmpp_hdr: An RMPP header. + */ +static inline u8 ib_get_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr) +{ + return rmpp_hdr->rmpp_rtime_flags & 0x7; +} + +/** + * ib_set_rmpp_resptime - Sets the response time in an RMPP header. + * @rmpp_hdr: An RMPP header. + * @rtime: The response time to set. + */ +static inline void ib_set_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr, u8 rtime) +{ + rmpp_hdr->rmpp_rtime_flags = ib_get_rmpp_flags(rmpp_hdr) | (rtime << 3); +} + +/** + * ib_set_rmpp_flags - Sets the flags in an RMPP header. + * @rmpp_hdr: An RMPP header. + * @flags: The flags to set. + */ +static inline void ib_set_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr, u8 flags) +{ + rmpp_hdr->rmpp_rtime_flags = (rmpp_hdr->rmpp_rtime_flags & 0xF1) | + (flags & 0x7); +} + +struct ib_mad_agent; +struct ib_mad_send_wc; +struct ib_mad_recv_wc; + +/** + * ib_mad_send_handler - callback handler for a sent MAD. + * @mad_agent: MAD agent that sent the MAD. + * @mad_send_wc: Send work completion information on the sent MAD. + */ +typedef void (*ib_mad_send_handler)(struct ib_mad_agent *mad_agent, + struct ib_mad_send_wc *mad_send_wc); + +/** + * ib_mad_snoop_handler - Callback handler for snooping sent MADs. + * @mad_agent: MAD agent that snooped the MAD. + * @send_wr: Work request information on the sent MAD. + * @mad_send_wc: Work completion information on the sent MAD. Valid + * only for snooping that occurs on a send completion. + * + * Clients snooping MADs should not modify data referenced by the @send_wr + * or @mad_send_wc. + */ +typedef void (*ib_mad_snoop_handler)(struct ib_mad_agent *mad_agent, + struct ib_send_wr *send_wr, + struct ib_mad_send_wc *mad_send_wc); + +/** + * ib_mad_recv_handler - callback handler for a received MAD. + * @mad_agent: MAD agent requesting the received MAD. + * @mad_recv_wc: Received work completion information on the received MAD. + * + * MADs received in response to a send request operation will be handed to + * the user after the send operation completes. All data buffers given + * to registered agents through this routine are owned by the receiving + * client, except for snooping agents. Clients snooping MADs should not + * modify the data referenced by @mad_recv_wc. + */ +typedef void (*ib_mad_recv_handler)(struct ib_mad_agent *mad_agent, + struct ib_mad_recv_wc *mad_recv_wc); + +/** + * ib_mad_agent - Used to track MAD registration with the access layer. + * @device: Reference to device registration is on. + * @qp: Reference to QP used for sending and receiving MADs. + * @mr: Memory region for system memory usable for DMA. + * @recv_handler: Callback handler for a received MAD. + * @send_handler: Callback handler for a sent MAD. + * @snoop_handler: Callback handler for snooped sent MADs. + * @context: User-specified context associated with this registration. + * @hi_tid: Access layer assigned transaction ID for this client. + * Unsolicited MADs sent by this client will have the upper 32-bits + * of their TID set to this value. + * @port_num: Port number on which QP is registered + * @rmpp_version: If set, indicates the RMPP version used by this agent. + */ +struct ib_mad_agent { + struct ib_device *device; + struct ib_qp *qp; + struct ib_mr *mr; + ib_mad_recv_handler recv_handler; + ib_mad_send_handler send_handler; + ib_mad_snoop_handler snoop_handler; + void *context; + u32 hi_tid; + u8 port_num; + u8 rmpp_version; +}; + +/** + * ib_mad_send_wc - MAD send completion information. + * @wr_id: Work request identifier associated with the send MAD request. + * @status: Completion status. + * @vendor_err: Optional vendor error information returned with a failed + * request. + */ +struct ib_mad_send_wc { + u64 wr_id; + enum ib_wc_status status; + u32 vendor_err; +}; + +/** + * ib_mad_recv_buf - received MAD buffer information. + * @list: Reference to next data buffer for a received RMPP MAD. + * @grh: References a data buffer containing the global route header. + * The data refereced by this buffer is only valid if the GRH is + * valid. + * @mad: References the start of the received MAD. + */ +struct ib_mad_recv_buf { + struct list_head list; + struct ib_grh *grh; + struct ib_mad *mad; +}; + +/** + * ib_mad_recv_wc - received MAD information. + * @wc: Completion information for the received data. + * @recv_buf: Specifies the location of the received data buffer(s). + * @rmpp_list: Specifies a list of RMPP reassembled received MAD buffers. + * @mad_len: The length of the received MAD, without duplicated headers. + * + * For received response, the wr_id field of the wc is set to the wr_id + * for the corresponding send request. + */ +struct ib_mad_recv_wc { + struct ib_wc *wc; + struct ib_mad_recv_buf recv_buf; + struct list_head rmpp_list; + int mad_len; +}; + +/** + * ib_mad_reg_req - MAD registration request + * @mgmt_class: Indicates which management class of MADs should be receive + * by the caller. This field is only required if the user wishes to + * receive unsolicited MADs, otherwise it should be 0. + * @mgmt_class_version: Indicates which version of MADs for the given + * management class to receive. + * @oui: Indicates IEEE OUI when mgmt_class is a vendor class + * in the range from 0x30 to 0x4f. Otherwise not used. + * @method_mask: The caller will receive unsolicited MADs for any method + * where @method_mask = 1. + */ +struct ib_mad_reg_req { + u8 mgmt_class; + u8 mgmt_class_version; + u8 oui[3]; + DECLARE_BITMAP(method_mask, IB_MGMT_MAX_METHODS); +}; + +/** + * ib_register_mad_agent - Register to send/receive MADs. + * @device: The device to register with. + * @port_num: The port on the specified device to use. + * @qp_type: Specifies which QP to access. Must be either + * IB_QPT_SMI or IB_QPT_GSI. + * @mad_reg_req: Specifies which unsolicited MADs should be received + * by the caller. This parameter may be NULL if the caller only + * wishes to receive solicited responses. + * @rmpp_version: If set, indicates that the client will send + * and receive MADs that contain the RMPP header for the given version. + * If set to 0, indicates that RMPP is not used by this client. + * @send_handler: The completion callback routine invoked after a send + * request has completed. + * @recv_handler: The completion callback routine invoked for a received + * MAD. + * @context: User specified context associated with the registration. + */ +struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device, + u8 port_num, + enum ib_qp_type qp_type, + struct ib_mad_reg_req *mad_reg_req, + u8 rmpp_version, + ib_mad_send_handler send_handler, + ib_mad_recv_handler recv_handler, + void *context); + +enum ib_mad_snoop_flags { + /*IB_MAD_SNOOP_POSTED_SENDS = 1,*/ + /*IB_MAD_SNOOP_RMPP_SENDS = (1<<1),*/ + IB_MAD_SNOOP_SEND_COMPLETIONS = (1<<2), + /*IB_MAD_SNOOP_RMPP_SEND_COMPLETIONS = (1<<3),*/ + IB_MAD_SNOOP_RECVS = (1<<4) + /*IB_MAD_SNOOP_RMPP_RECVS = (1<<5),*/ + /*IB_MAD_SNOOP_REDIRECTED_QPS = (1<<6)*/ +}; + +/** + * ib_register_mad_snoop - Register to snoop sent and received MADs. + * @device: The device to register with. + * @port_num: The port on the specified device to use. + * @qp_type: Specifies which QP traffic to snoop. Must be either + * IB_QPT_SMI or IB_QPT_GSI. + * @mad_snoop_flags: Specifies information where snooping occurs. + * @send_handler: The callback routine invoked for a snooped send. + * @recv_handler: The callback routine invoked for a snooped receive. + * @context: User specified context associated with the registration. + */ +struct ib_mad_agent *ib_register_mad_snoop(struct ib_device *device, + u8 port_num, + enum ib_qp_type qp_type, + int mad_snoop_flags, + ib_mad_snoop_handler snoop_handler, + ib_mad_recv_handler recv_handler, + void *context); + +/** + * ib_unregister_mad_agent - Unregisters a client from using MAD services. + * @mad_agent: Corresponding MAD registration request to deregister. + * + * After invoking this routine, MAD services are no longer usable by the + * client on the associated QP. + */ +int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent); + +/** + * ib_post_send_mad - Posts MAD(s) to the send queue of the QP associated + * with the registered client. + * @mad_agent: Specifies the associated registration to post the send to. + * @send_wr: Specifies the information needed to send the MAD(s). + * @bad_send_wr: Specifies the MAD on which an error was encountered. + * + * Sent MADs are not guaranteed to complete in the order that they were posted. + * + * If the MAD requires RMPP, the data buffer should contain a single copy + * of the common MAD, RMPP, and class specific headers, followed by the class + * defined data. If the class defined data would not divide evenly into + * RMPP segments, then space must be allocated at the end of the referenced + * buffer for any required padding. To indicate the amount of class defined + * data being transferred, the paylen_newwin field in the RMPP header should + * be set to the size of the class specific header plus the amount of class + * defined data being transferred. The paylen_newwin field should be + * specified in network-byte order. + */ +int ib_post_send_mad(struct ib_mad_agent *mad_agent, + struct ib_send_wr *send_wr, + struct ib_send_wr **bad_send_wr); + +/** + * ib_coalesce_recv_mad - Coalesces received MAD data into a single buffer. + * @mad_recv_wc: Work completion information for a received MAD. + * @buf: User-provided data buffer to receive the coalesced buffers. The + * referenced buffer should be at least the size of the mad_len specified + * by @mad_recv_wc. + * + * This call copies a chain of received MAD segments into a single data buffer, + * removing duplicated headers. + */ +void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, void *buf); + +/** + * ib_free_recv_mad - Returns data buffers used to receive a MAD. + * @mad_recv_wc: Work completion information for a received MAD. + * + * Clients receiving MADs through their ib_mad_recv_handler must call this + * routine to return the work completion buffers to the access layer. + */ +void ib_free_recv_mad(struct ib_mad_recv_wc *mad_recv_wc); + +/** + * ib_cancel_mad - Cancels an outstanding send MAD operation. + * @mad_agent: Specifies the registration associated with sent MAD. + * @wr_id: Indicates the work request identifier of the MAD to cancel. + * + * MADs will be returned to the user through the corresponding + * ib_mad_send_handler. + */ +void ib_cancel_mad(struct ib_mad_agent *mad_agent, u64 wr_id); + +/** + * ib_modify_mad - Modifies an outstanding send MAD operation. + * @mad_agent: Specifies the registration associated with sent MAD. + * @wr_id: Indicates the work request identifier of the MAD to modify. + * @timeout_ms: New timeout value for sent MAD. + * + * This call will reset the timeout value for a sent MAD to the specified + * value. + */ +int ib_modify_mad(struct ib_mad_agent *mad_agent, u64 wr_id, u32 timeout_ms); + +/** + * ib_redirect_mad_qp - Registers a QP for MAD services. + * @qp: Reference to a QP that requires MAD services. + * @rmpp_version: If set, indicates that the client will send + * and receive MADs that contain the RMPP header for the given version. + * If set to 0, indicates that RMPP is not used by this client. + * @send_handler: The completion callback routine invoked after a send + * request has completed. + * @recv_handler: The completion callback routine invoked for a received + * MAD. + * @context: User specified context associated with the registration. + * + * Use of this call allows clients to use MAD services, such as RMPP, + * on user-owned QPs. After calling this routine, users may send + * MADs on the specified QP by calling ib_mad_post_send. + */ +struct ib_mad_agent *ib_redirect_mad_qp(struct ib_qp *qp, + u8 rmpp_version, + ib_mad_send_handler send_handler, + ib_mad_recv_handler recv_handler, + void *context); + +/** + * ib_process_mad_wc - Processes a work completion associated with a + * MAD sent or received on a redirected QP. + * @mad_agent: Specifies the registered MAD service using the redirected QP. + * @wc: References a work completion associated with a sent or received + * MAD segment. + * + * This routine is used to complete or continue processing on a MAD request. + * If the work completion is associated with a send operation, calling + * this routine is required to continue an RMPP transfer or to wait for a + * corresponding response, if it is a request. If the work completion is + * associated with a receive operation, calling this routine is required to + * process an inbound or outbound RMPP transfer, or to match a response MAD + * with its corresponding request. + */ +int ib_process_mad_wc(struct ib_mad_agent *mad_agent, + struct ib_wc *wc); + +/** + * ib_create_send_mad - Allocate and initialize a data buffer and work request + * for sending a MAD. + * @mad_agent: Specifies the registered MAD service to associate with the MAD. + * @remote_qpn: Specifies the QPN of the receiving node. + * @pkey_index: Specifies which PKey the MAD will be sent using. This field + * is valid only if the remote_qpn is QP 1. + * @ah: References the address handle used to transfer to the remote node. + * @rmpp_active: Indicates if the send will enable RMPP. + * @hdr_len: Indicates the size of the data header of the MAD. This length + * should include the common MAD header, RMPP header, plus any class + * specific header. + * @data_len: Indicates the size of any user-transferred data. The call will + * automatically adjust the allocated buffer size to account for any + * additional padding that may be necessary. + * @gfp_mask: GFP mask used for the memory allocation. + * + * This is a helper routine that may be used to allocate a MAD. Users are + * not required to allocate outbound MADs using this call. The returned + * MAD send buffer will reference a data buffer usable for sending a MAD, along + * with an initialized work request structure. Users may modify the returned + * MAD data buffer or work request before posting the send. + * + * The returned data buffer will be cleared. Users are responsible for + * initializing the common MAD and any class specific headers. If @rmpp_active + * is set, the RMPP header will be initialized for sending. + */ +struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent, + u32 remote_qpn, u16 pkey_index, + struct ib_ah *ah, int rmpp_active, + int hdr_len, int data_len, + unsigned int __nocast gfp_mask); + +/** + * ib_free_send_mad - Returns data buffers used to send a MAD. + * @send_buf: Previously allocated send data buffer. + */ +void ib_free_send_mad(struct ib_mad_send_buf *send_buf); + +#endif /* IB_MAD_H */ diff --git a/include/rdma/ib_pack.h b/include/rdma/ib_pack.h new file mode 100644 index 000000000000..f926020d6331 --- /dev/null +++ b/include/rdma/ib_pack.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2004 Topspin Corporation. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_pack.h 1349 2004-12-16 21:09:43Z roland $ + */ + +#ifndef IB_PACK_H +#define IB_PACK_H + +#include <rdma/ib_verbs.h> + +enum { + IB_LRH_BYTES = 8, + IB_GRH_BYTES = 40, + IB_BTH_BYTES = 12, + IB_DETH_BYTES = 8 +}; + +struct ib_field { + size_t struct_offset_bytes; + size_t struct_size_bytes; + int offset_words; + int offset_bits; + int size_bits; + char *field_name; +}; + +#define RESERVED \ + .field_name = "reserved" + +/* + * This macro cleans up the definitions of constants for BTH opcodes. + * It is used to define constants such as IB_OPCODE_UD_SEND_ONLY, + * which becomes IB_OPCODE_UD + IB_OPCODE_SEND_ONLY, and this gives + * the correct value. + * + * In short, user code should use the constants defined using the + * macro rather than worrying about adding together other constants. +*/ +#define IB_OPCODE(transport, op) \ + IB_OPCODE_ ## transport ## _ ## op = \ + IB_OPCODE_ ## transport + IB_OPCODE_ ## op + +enum { + /* transport types -- just used to define real constants */ + IB_OPCODE_RC = 0x00, + IB_OPCODE_UC = 0x20, + IB_OPCODE_RD = 0x40, + IB_OPCODE_UD = 0x60, + + /* operations -- just used to define real constants */ + IB_OPCODE_SEND_FIRST = 0x00, + IB_OPCODE_SEND_MIDDLE = 0x01, + IB_OPCODE_SEND_LAST = 0x02, + IB_OPCODE_SEND_LAST_WITH_IMMEDIATE = 0x03, + IB_OPCODE_SEND_ONLY = 0x04, + IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE = 0x05, + IB_OPCODE_RDMA_WRITE_FIRST = 0x06, + IB_OPCODE_RDMA_WRITE_MIDDLE = 0x07, + IB_OPCODE_RDMA_WRITE_LAST = 0x08, + IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE = 0x09, + IB_OPCODE_RDMA_WRITE_ONLY = 0x0a, + IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE = 0x0b, + IB_OPCODE_RDMA_READ_REQUEST = 0x0c, + IB_OPCODE_RDMA_READ_RESPONSE_FIRST = 0x0d, + IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE = 0x0e, + IB_OPCODE_RDMA_READ_RESPONSE_LAST = 0x0f, + IB_OPCODE_RDMA_READ_RESPONSE_ONLY = 0x10, + IB_OPCODE_ACKNOWLEDGE = 0x11, + IB_OPCODE_ATOMIC_ACKNOWLEDGE = 0x12, + IB_OPCODE_COMPARE_SWAP = 0x13, + IB_OPCODE_FETCH_ADD = 0x14, + + /* real constants follow -- see comment about above IB_OPCODE() + macro for more details */ + + /* RC */ + IB_OPCODE(RC, SEND_FIRST), + IB_OPCODE(RC, SEND_MIDDLE), + IB_OPCODE(RC, SEND_LAST), + IB_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE), + IB_OPCODE(RC, SEND_ONLY), + IB_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE), + IB_OPCODE(RC, RDMA_WRITE_FIRST), + IB_OPCODE(RC, RDMA_WRITE_MIDDLE), + IB_OPCODE(RC, RDMA_WRITE_LAST), + IB_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE), + IB_OPCODE(RC, RDMA_WRITE_ONLY), + IB_OPCODE(RC, RDMA_WRITE_ONLY_WITH_IMMEDIATE), + IB_OPCODE(RC, RDMA_READ_REQUEST), + IB_OPCODE(RC, RDMA_READ_RESPONSE_FIRST), + IB_OPCODE(RC, RDMA_READ_RESPONSE_MIDDLE), + IB_OPCODE(RC, RDMA_READ_RESPONSE_LAST), + IB_OPCODE(RC, RDMA_READ_RESPONSE_ONLY), + IB_OPCODE(RC, ACKNOWLEDGE), + IB_OPCODE(RC, ATOMIC_ACKNOWLEDGE), + IB_OPCODE(RC, COMPARE_SWAP), + IB_OPCODE(RC, FETCH_ADD), + + /* UC */ + IB_OPCODE(UC, SEND_FIRST), + IB_OPCODE(UC, SEND_MIDDLE), + IB_OPCODE(UC, SEND_LAST), + IB_OPCODE(UC, SEND_LAST_WITH_IMMEDIATE), + IB_OPCODE(UC, SEND_ONLY), + IB_OPCODE(UC, SEND_ONLY_WITH_IMMEDIATE), + IB_OPCODE(UC, RDMA_WRITE_FIRST), + IB_OPCODE(UC, RDMA_WRITE_MIDDLE), + IB_OPCODE(UC, RDMA_WRITE_LAST), + IB_OPCODE(UC, RDMA_WRITE_LAST_WITH_IMMEDIATE), + IB_OPCODE(UC, RDMA_WRITE_ONLY), + IB_OPCODE(UC, RDMA_WRITE_ONLY_WITH_IMMEDIATE), + + /* RD */ + IB_OPCODE(RD, SEND_FIRST), + IB_OPCODE(RD, SEND_MIDDLE), + IB_OPCODE(RD, SEND_LAST), + IB_OPCODE(RD, SEND_LAST_WITH_IMMEDIATE), + IB_OPCODE(RD, SEND_ONLY), + IB_OPCODE(RD, SEND_ONLY_WITH_IMMEDIATE), + IB_OPCODE(RD, RDMA_WRITE_FIRST), + IB_OPCODE(RD, RDMA_WRITE_MIDDLE), + IB_OPCODE(RD, RDMA_WRITE_LAST), + IB_OPCODE(RD, RDMA_WRITE_LAST_WITH_IMMEDIATE), + IB_OPCODE(RD, RDMA_WRITE_ONLY), + IB_OPCODE(RD, RDMA_WRITE_ONLY_WITH_IMMEDIATE), + IB_OPCODE(RD, RDMA_READ_REQUEST), + IB_OPCODE(RD, RDMA_READ_RESPONSE_FIRST), + IB_OPCODE(RD, RDMA_READ_RESPONSE_MIDDLE), + IB_OPCODE(RD, RDMA_READ_RESPONSE_LAST), + IB_OPCODE(RD, RDMA_READ_RESPONSE_ONLY), + IB_OPCODE(RD, ACKNOWLEDGE), + IB_OPCODE(RD, ATOMIC_ACKNOWLEDGE), + IB_OPCODE(RD, COMPARE_SWAP), + IB_OPCODE(RD, FETCH_ADD), + + /* UD */ + IB_OPCODE(UD, SEND_ONLY), + IB_OPCODE(UD, SEND_ONLY_WITH_IMMEDIATE) +}; + +enum { + IB_LNH_RAW = 0, + IB_LNH_IP = 1, + IB_LNH_IBA_LOCAL = 2, + IB_LNH_IBA_GLOBAL = 3 +}; + +struct ib_unpacked_lrh { + u8 virtual_lane; + u8 link_version; + u8 service_level; + u8 link_next_header; + __be16 destination_lid; + __be16 packet_length; + __be16 source_lid; +}; + +struct ib_unpacked_grh { + u8 ip_version; + u8 traffic_class; + __be32 flow_label; + __be16 payload_length; + u8 next_header; + u8 hop_limit; + union ib_gid source_gid; + union ib_gid destination_gid; +}; + +struct ib_unpacked_bth { + u8 opcode; + u8 solicited_event; + u8 mig_req; + u8 pad_count; + u8 transport_header_version; + __be16 pkey; + __be32 destination_qpn; + u8 ack_req; + __be32 psn; +}; + +struct ib_unpacked_deth { + __be32 qkey; + __be32 source_qpn; +}; + +struct ib_ud_header { + struct ib_unpacked_lrh lrh; + int grh_present; + struct ib_unpacked_grh grh; + struct ib_unpacked_bth bth; + struct ib_unpacked_deth deth; + int immediate_present; + __be32 immediate_data; +}; + +void ib_pack(const struct ib_field *desc, + int desc_len, + void *structure, + void *buf); + +void ib_unpack(const struct ib_field *desc, + int desc_len, + void *buf, + void *structure); + +void ib_ud_header_init(int payload_bytes, + int grh_present, + struct ib_ud_header *header); + +int ib_ud_header_pack(struct ib_ud_header *header, + void *buf); + +int ib_ud_header_unpack(void *buf, + struct ib_ud_header *header); + +#endif /* IB_PACK_H */ diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h new file mode 100644 index 000000000000..c022edfc49da --- /dev/null +++ b/include/rdma/ib_sa.h @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2004 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Voltaire, Inc. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_sa.h 2811 2005-07-06 18:11:43Z halr $ + */ + +#ifndef IB_SA_H +#define IB_SA_H + +#include <linux/compiler.h> + +#include <rdma/ib_verbs.h> +#include <rdma/ib_mad.h> + +enum { + IB_SA_CLASS_VERSION = 2, /* IB spec version 1.1/1.2 */ + + IB_SA_METHOD_GET_TABLE = 0x12, + IB_SA_METHOD_GET_TABLE_RESP = 0x92, + IB_SA_METHOD_DELETE = 0x15 +}; + +enum ib_sa_selector { + IB_SA_GTE = 0, + IB_SA_LTE = 1, + IB_SA_EQ = 2, + /* + * The meaning of "best" depends on the attribute: for + * example, for MTU best will return the largest available + * MTU, while for packet life time, best will return the + * smallest available life time. + */ + IB_SA_BEST = 3 +}; + +enum ib_sa_rate { + IB_SA_RATE_2_5_GBPS = 2, + IB_SA_RATE_5_GBPS = 5, + IB_SA_RATE_10_GBPS = 3, + IB_SA_RATE_20_GBPS = 6, + IB_SA_RATE_30_GBPS = 4, + IB_SA_RATE_40_GBPS = 7, + IB_SA_RATE_60_GBPS = 8, + IB_SA_RATE_80_GBPS = 9, + IB_SA_RATE_120_GBPS = 10 +}; + +static inline int ib_sa_rate_enum_to_int(enum ib_sa_rate rate) +{ + switch (rate) { + case IB_SA_RATE_2_5_GBPS: return 1; + case IB_SA_RATE_5_GBPS: return 2; + case IB_SA_RATE_10_GBPS: return 4; + case IB_SA_RATE_20_GBPS: return 8; + case IB_SA_RATE_30_GBPS: return 12; + case IB_SA_RATE_40_GBPS: return 16; + case IB_SA_RATE_60_GBPS: return 24; + case IB_SA_RATE_80_GBPS: return 32; + case IB_SA_RATE_120_GBPS: return 48; + default: return -1; + } +} + +/* + * Structures for SA records are named "struct ib_sa_xxx_rec." No + * attempt is made to pack structures to match the physical layout of + * SA records in SA MADs; all packing and unpacking is handled by the + * SA query code. + * + * For a record with structure ib_sa_xxx_rec, the naming convention + * for the component mask value for field yyy is IB_SA_XXX_REC_YYY (we + * never use different abbreviations or otherwise change the spelling + * of xxx/yyy between ib_sa_xxx_rec.yyy and IB_SA_XXX_REC_YYY). + * + * Reserved rows are indicated with comments to help maintainability. + */ + +/* reserved: 0 */ +/* reserved: 1 */ +#define IB_SA_PATH_REC_DGID IB_SA_COMP_MASK( 2) +#define IB_SA_PATH_REC_SGID IB_SA_COMP_MASK( 3) +#define IB_SA_PATH_REC_DLID IB_SA_COMP_MASK( 4) +#define IB_SA_PATH_REC_SLID IB_SA_COMP_MASK( 5) +#define IB_SA_PATH_REC_RAW_TRAFFIC IB_SA_COMP_MASK( 6) +/* reserved: 7 */ +#define IB_SA_PATH_REC_FLOW_LABEL IB_SA_COMP_MASK( 8) +#define IB_SA_PATH_REC_HOP_LIMIT IB_SA_COMP_MASK( 9) +#define IB_SA_PATH_REC_TRAFFIC_CLASS IB_SA_COMP_MASK(10) +#define IB_SA_PATH_REC_REVERSIBLE IB_SA_COMP_MASK(11) +#define IB_SA_PATH_REC_NUMB_PATH IB_SA_COMP_MASK(12) +#define IB_SA_PATH_REC_PKEY IB_SA_COMP_MASK(13) +/* reserved: 14 */ +#define IB_SA_PATH_REC_SL IB_SA_COMP_MASK(15) +#define IB_SA_PATH_REC_MTU_SELECTOR IB_SA_COMP_MASK(16) +#define IB_SA_PATH_REC_MTU IB_SA_COMP_MASK(17) +#define IB_SA_PATH_REC_RATE_SELECTOR IB_SA_COMP_MASK(18) +#define IB_SA_PATH_REC_RATE IB_SA_COMP_MASK(19) +#define IB_SA_PATH_REC_PACKET_LIFE_TIME_SELECTOR IB_SA_COMP_MASK(20) +#define IB_SA_PATH_REC_PACKET_LIFE_TIME IB_SA_COMP_MASK(21) +#define IB_SA_PATH_REC_PREFERENCE IB_SA_COMP_MASK(22) + +struct ib_sa_path_rec { + /* reserved */ + /* reserved */ + union ib_gid dgid; + union ib_gid sgid; + __be16 dlid; + __be16 slid; + int raw_traffic; + /* reserved */ + __be32 flow_label; + u8 hop_limit; + u8 traffic_class; + int reversible; + u8 numb_path; + __be16 pkey; + /* reserved */ + u8 sl; + u8 mtu_selector; + u8 mtu; + u8 rate_selector; + u8 rate; + u8 packet_life_time_selector; + u8 packet_life_time; + u8 preference; +}; + +#define IB_SA_MCMEMBER_REC_MGID IB_SA_COMP_MASK( 0) +#define IB_SA_MCMEMBER_REC_PORT_GID IB_SA_COMP_MASK( 1) +#define IB_SA_MCMEMBER_REC_QKEY IB_SA_COMP_MASK( 2) +#define IB_SA_MCMEMBER_REC_MLID IB_SA_COMP_MASK( 3) +#define IB_SA_MCMEMBER_REC_MTU_SELECTOR IB_SA_COMP_MASK( 4) +#define IB_SA_MCMEMBER_REC_MTU IB_SA_COMP_MASK( 5) +#define IB_SA_MCMEMBER_REC_TRAFFIC_CLASS IB_SA_COMP_MASK( 6) +#define IB_SA_MCMEMBER_REC_PKEY IB_SA_COMP_MASK( 7) +#define IB_SA_MCMEMBER_REC_RATE_SELECTOR IB_SA_COMP_MASK( 8) +#define IB_SA_MCMEMBER_REC_RATE IB_SA_COMP_MASK( 9) +#define IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME_SELECTOR IB_SA_COMP_MASK(10) +#define IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME IB_SA_COMP_MASK(11) +#define IB_SA_MCMEMBER_REC_SL IB_SA_COMP_MASK(12) +#define IB_SA_MCMEMBER_REC_FLOW_LABEL IB_SA_COMP_MASK(13) +#define IB_SA_MCMEMBER_REC_HOP_LIMIT IB_SA_COMP_MASK(14) +#define IB_SA_MCMEMBER_REC_SCOPE IB_SA_COMP_MASK(15) +#define IB_SA_MCMEMBER_REC_JOIN_STATE IB_SA_COMP_MASK(16) +#define IB_SA_MCMEMBER_REC_PROXY_JOIN IB_SA_COMP_MASK(17) + +struct ib_sa_mcmember_rec { + union ib_gid mgid; + union ib_gid port_gid; + __be32 qkey; + __be16 mlid; + u8 mtu_selector; + u8 mtu; + u8 traffic_class; + __be16 pkey; + u8 rate_selector; + u8 rate; + u8 packet_life_time_selector; + u8 packet_life_time; + u8 sl; + __be32 flow_label; + u8 hop_limit; + u8 scope; + u8 join_state; + int proxy_join; +}; + +/* Service Record Component Mask Sec 15.2.5.14 Ver 1.1 */ +#define IB_SA_SERVICE_REC_SERVICE_ID IB_SA_COMP_MASK( 0) +#define IB_SA_SERVICE_REC_SERVICE_GID IB_SA_COMP_MASK( 1) +#define IB_SA_SERVICE_REC_SERVICE_PKEY IB_SA_COMP_MASK( 2) +/* reserved: 3 */ +#define IB_SA_SERVICE_REC_SERVICE_LEASE IB_SA_COMP_MASK( 4) +#define IB_SA_SERVICE_REC_SERVICE_KEY IB_SA_COMP_MASK( 5) +#define IB_SA_SERVICE_REC_SERVICE_NAME IB_SA_COMP_MASK( 6) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_0 IB_SA_COMP_MASK( 7) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_1 IB_SA_COMP_MASK( 8) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_2 IB_SA_COMP_MASK( 9) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_3 IB_SA_COMP_MASK(10) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_4 IB_SA_COMP_MASK(11) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_5 IB_SA_COMP_MASK(12) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_6 IB_SA_COMP_MASK(13) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_7 IB_SA_COMP_MASK(14) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_8 IB_SA_COMP_MASK(15) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_9 IB_SA_COMP_MASK(16) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_10 IB_SA_COMP_MASK(17) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_11 IB_SA_COMP_MASK(18) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_12 IB_SA_COMP_MASK(19) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_13 IB_SA_COMP_MASK(20) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_14 IB_SA_COMP_MASK(21) +#define IB_SA_SERVICE_REC_SERVICE_DATA8_15 IB_SA_COMP_MASK(22) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_0 IB_SA_COMP_MASK(23) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_1 IB_SA_COMP_MASK(24) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_2 IB_SA_COMP_MASK(25) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_3 IB_SA_COMP_MASK(26) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_4 IB_SA_COMP_MASK(27) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_5 IB_SA_COMP_MASK(28) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_6 IB_SA_COMP_MASK(29) +#define IB_SA_SERVICE_REC_SERVICE_DATA16_7 IB_SA_COMP_MASK(30) +#define IB_SA_SERVICE_REC_SERVICE_DATA32_0 IB_SA_COMP_MASK(31) +#define IB_SA_SERVICE_REC_SERVICE_DATA32_1 IB_SA_COMP_MASK(32) +#define IB_SA_SERVICE_REC_SERVICE_DATA32_2 IB_SA_COMP_MASK(33) +#define IB_SA_SERVICE_REC_SERVICE_DATA32_3 IB_SA_COMP_MASK(34) +#define IB_SA_SERVICE_REC_SERVICE_DATA64_0 IB_SA_COMP_MASK(35) +#define IB_SA_SERVICE_REC_SERVICE_DATA64_1 IB_SA_COMP_MASK(36) + +#define IB_DEFAULT_SERVICE_LEASE 0xFFFFFFFF + +struct ib_sa_service_rec { + u64 id; + union ib_gid gid; + __be16 pkey; + /* reserved */ + u32 lease; + u8 key[16]; + u8 name[64]; + u8 data8[16]; + u16 data16[8]; + u32 data32[4]; + u64 data64[2]; +}; + +struct ib_sa_query; + +void ib_sa_cancel_query(int id, struct ib_sa_query *query); + +int ib_sa_path_rec_get(struct ib_device *device, u8 port_num, + struct ib_sa_path_rec *rec, + ib_sa_comp_mask comp_mask, + int timeout_ms, unsigned int __nocast gfp_mask, + void (*callback)(int status, + struct ib_sa_path_rec *resp, + void *context), + void *context, + struct ib_sa_query **query); + +int ib_sa_mcmember_rec_query(struct ib_device *device, u8 port_num, + u8 method, + struct ib_sa_mcmember_rec *rec, + ib_sa_comp_mask comp_mask, + int timeout_ms, unsigned int __nocast gfp_mask, + void (*callback)(int status, + struct ib_sa_mcmember_rec *resp, + void *context), + void *context, + struct ib_sa_query **query); + +int ib_sa_service_rec_query(struct ib_device *device, u8 port_num, + u8 method, + struct ib_sa_service_rec *rec, + ib_sa_comp_mask comp_mask, + int timeout_ms, unsigned int __nocast gfp_mask, + void (*callback)(int status, + struct ib_sa_service_rec *resp, + void *context), + void *context, + struct ib_sa_query **sa_query); + +/** + * ib_sa_mcmember_rec_set - Start an MCMember set query + * @device:device to send query on + * @port_num: port number to send query on + * @rec:MCMember Record to send in query + * @comp_mask:component mask to send in query + * @timeout_ms:time to wait for response + * @gfp_mask:GFP mask to use for internal allocations + * @callback:function called when query completes, times out or is + * canceled + * @context:opaque user context passed to callback + * @sa_query:query context, used to cancel query + * + * Send an MCMember Set query to the SA (eg to join a multicast + * group). The callback function will be called when the query + * completes (or fails); status is 0 for a successful response, -EINTR + * if the query is canceled, -ETIMEDOUT is the query timed out, or + * -EIO if an error occurred sending the query. The resp parameter of + * the callback is only valid if status is 0. + * + * If the return value of ib_sa_mcmember_rec_set() is negative, it is + * an error code. Otherwise it is a query ID that can be used to + * cancel the query. + */ +static inline int +ib_sa_mcmember_rec_set(struct ib_device *device, u8 port_num, + struct ib_sa_mcmember_rec *rec, + ib_sa_comp_mask comp_mask, + int timeout_ms, unsigned int __nocast gfp_mask, + void (*callback)(int status, + struct ib_sa_mcmember_rec *resp, + void *context), + void *context, + struct ib_sa_query **query) +{ + return ib_sa_mcmember_rec_query(device, port_num, + IB_MGMT_METHOD_SET, + rec, comp_mask, + timeout_ms, gfp_mask, callback, + context, query); +} + +/** + * ib_sa_mcmember_rec_delete - Start an MCMember delete query + * @device:device to send query on + * @port_num: port number to send query on + * @rec:MCMember Record to send in query + * @comp_mask:component mask to send in query + * @timeout_ms:time to wait for response + * @gfp_mask:GFP mask to use for internal allocations + * @callback:function called when query completes, times out or is + * canceled + * @context:opaque user context passed to callback + * @sa_query:query context, used to cancel query + * + * Send an MCMember Delete query to the SA (eg to leave a multicast + * group). The callback function will be called when the query + * completes (or fails); status is 0 for a successful response, -EINTR + * if the query is canceled, -ETIMEDOUT is the query timed out, or + * -EIO if an error occurred sending the query. The resp parameter of + * the callback is only valid if status is 0. + * + * If the return value of ib_sa_mcmember_rec_delete() is negative, it + * is an error code. Otherwise it is a query ID that can be used to + * cancel the query. + */ +static inline int +ib_sa_mcmember_rec_delete(struct ib_device *device, u8 port_num, + struct ib_sa_mcmember_rec *rec, + ib_sa_comp_mask comp_mask, + int timeout_ms, unsigned int __nocast gfp_mask, + void (*callback)(int status, + struct ib_sa_mcmember_rec *resp, + void *context), + void *context, + struct ib_sa_query **query) +{ + return ib_sa_mcmember_rec_query(device, port_num, + IB_SA_METHOD_DELETE, + rec, comp_mask, + timeout_ms, gfp_mask, callback, + context, query); +} + + +#endif /* IB_SA_H */ diff --git a/include/rdma/ib_smi.h b/include/rdma/ib_smi.h new file mode 100644 index 000000000000..87f60737f695 --- /dev/null +++ b/include/rdma/ib_smi.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. + * Copyright (c) 2004 Infinicon Corporation. All rights reserved. + * Copyright (c) 2004 Intel Corporation. All rights reserved. + * Copyright (c) 2004 Topspin Corporation. All rights reserved. + * Copyright (c) 2004 Voltaire Corporation. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_smi.h 1389 2004-12-27 22:56:47Z roland $ + */ + +#if !defined( IB_SMI_H ) +#define IB_SMI_H + +#include <rdma/ib_mad.h> + +#define IB_SMP_DATA_SIZE 64 +#define IB_SMP_MAX_PATH_HOPS 64 + +struct ib_smp { + u8 base_version; + u8 mgmt_class; + u8 class_version; + u8 method; + __be16 status; + u8 hop_ptr; + u8 hop_cnt; + __be64 tid; + __be16 attr_id; + __be16 resv; + __be32 attr_mod; + __be64 mkey; + __be16 dr_slid; + __be16 dr_dlid; + u8 reserved[28]; + u8 data[IB_SMP_DATA_SIZE]; + u8 initial_path[IB_SMP_MAX_PATH_HOPS]; + u8 return_path[IB_SMP_MAX_PATH_HOPS]; +} __attribute__ ((packed)); + +#define IB_SMP_DIRECTION __constant_htons(0x8000) + +/* Subnet management attributes */ +#define IB_SMP_ATTR_NOTICE __constant_htons(0x0002) +#define IB_SMP_ATTR_NODE_DESC __constant_htons(0x0010) +#define IB_SMP_ATTR_NODE_INFO __constant_htons(0x0011) +#define IB_SMP_ATTR_SWITCH_INFO __constant_htons(0x0012) +#define IB_SMP_ATTR_GUID_INFO __constant_htons(0x0014) +#define IB_SMP_ATTR_PORT_INFO __constant_htons(0x0015) +#define IB_SMP_ATTR_PKEY_TABLE __constant_htons(0x0016) +#define IB_SMP_ATTR_SL_TO_VL_TABLE __constant_htons(0x0017) +#define IB_SMP_ATTR_VL_ARB_TABLE __constant_htons(0x0018) +#define IB_SMP_ATTR_LINEAR_FORWARD_TABLE __constant_htons(0x0019) +#define IB_SMP_ATTR_RANDOM_FORWARD_TABLE __constant_htons(0x001A) +#define IB_SMP_ATTR_MCAST_FORWARD_TABLE __constant_htons(0x001B) +#define IB_SMP_ATTR_SM_INFO __constant_htons(0x0020) +#define IB_SMP_ATTR_VENDOR_DIAG __constant_htons(0x0030) +#define IB_SMP_ATTR_LED_INFO __constant_htons(0x0031) +#define IB_SMP_ATTR_VENDOR_MASK __constant_htons(0xFF00) + +static inline u8 +ib_get_smp_direction(struct ib_smp *smp) +{ + return ((smp->status & IB_SMP_DIRECTION) == IB_SMP_DIRECTION); +} + +#endif /* IB_SMI_H */ diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h new file mode 100644 index 000000000000..72182d16778b --- /dev/null +++ b/include/rdma/ib_user_cm.h @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2005 Topspin Communications. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_user_cm.h 2576 2005-06-09 17:00:30Z libor $ + */ + +#ifndef IB_USER_CM_H +#define IB_USER_CM_H + +#include <linux/types.h> + +#define IB_USER_CM_ABI_VERSION 1 + +enum { + IB_USER_CM_CMD_CREATE_ID, + IB_USER_CM_CMD_DESTROY_ID, + IB_USER_CM_CMD_ATTR_ID, + + IB_USER_CM_CMD_LISTEN, + IB_USER_CM_CMD_ESTABLISH, + + IB_USER_CM_CMD_SEND_REQ, + IB_USER_CM_CMD_SEND_REP, + IB_USER_CM_CMD_SEND_RTU, + IB_USER_CM_CMD_SEND_DREQ, + IB_USER_CM_CMD_SEND_DREP, + IB_USER_CM_CMD_SEND_REJ, + IB_USER_CM_CMD_SEND_MRA, + IB_USER_CM_CMD_SEND_LAP, + IB_USER_CM_CMD_SEND_APR, + IB_USER_CM_CMD_SEND_SIDR_REQ, + IB_USER_CM_CMD_SEND_SIDR_REP, + + IB_USER_CM_CMD_EVENT, +}; +/* + * command ABI structures. + */ +struct ib_ucm_cmd_hdr { + __u32 cmd; + __u16 in; + __u16 out; +}; + +struct ib_ucm_create_id { + __u64 response; +}; + +struct ib_ucm_create_id_resp { + __u32 id; +}; + +struct ib_ucm_destroy_id { + __u32 id; +}; + +struct ib_ucm_attr_id { + __u64 response; + __u32 id; +}; + +struct ib_ucm_attr_id_resp { + __be64 service_id; + __be64 service_mask; + __be32 local_id; + __be32 remote_id; +}; + +struct ib_ucm_listen { + __be64 service_id; + __be64 service_mask; + __u32 id; +}; + +struct ib_ucm_establish { + __u32 id; +}; + +struct ib_ucm_private_data { + __u64 data; + __u32 id; + __u8 len; + __u8 reserved[3]; +}; + +struct ib_ucm_path_rec { + __u8 dgid[16]; + __u8 sgid[16]; + __be16 dlid; + __be16 slid; + __u32 raw_traffic; + __be32 flow_label; + __u32 reversible; + __u32 mtu; + __be16 pkey; + __u8 hop_limit; + __u8 traffic_class; + __u8 numb_path; + __u8 sl; + __u8 mtu_selector; + __u8 rate_selector; + __u8 rate; + __u8 packet_life_time_selector; + __u8 packet_life_time; + __u8 preference; +}; + +struct ib_ucm_req { + __u32 id; + __u32 qpn; + __u32 qp_type; + __u32 psn; + __be64 sid; + __u64 data; + __u64 primary_path; + __u64 alternate_path; + __u8 len; + __u8 peer_to_peer; + __u8 responder_resources; + __u8 initiator_depth; + __u8 remote_cm_response_timeout; + __u8 flow_control; + __u8 local_cm_response_timeout; + __u8 retry_count; + __u8 rnr_retry_count; + __u8 max_cm_retries; + __u8 srq; + __u8 reserved[1]; +}; + +struct ib_ucm_rep { + __u64 data; + __u32 id; + __u32 qpn; + __u32 psn; + __u8 len; + __u8 responder_resources; + __u8 initiator_depth; + __u8 target_ack_delay; + __u8 failover_accepted; + __u8 flow_control; + __u8 rnr_retry_count; + __u8 srq; +}; + +struct ib_ucm_info { + __u32 id; + __u32 status; + __u64 info; + __u64 data; + __u8 info_len; + __u8 data_len; + __u8 reserved[2]; +}; + +struct ib_ucm_mra { + __u64 data; + __u32 id; + __u8 len; + __u8 timeout; + __u8 reserved[2]; +}; + +struct ib_ucm_lap { + __u64 path; + __u64 data; + __u32 id; + __u8 len; + __u8 reserved[3]; +}; + +struct ib_ucm_sidr_req { + __u32 id; + __u32 timeout; + __be64 sid; + __u64 data; + __u64 path; + __u16 pkey; + __u8 len; + __u8 max_cm_retries; +}; + +struct ib_ucm_sidr_rep { + __u32 id; + __u32 qpn; + __u32 qkey; + __u32 status; + __u64 info; + __u64 data; + __u8 info_len; + __u8 data_len; + __u8 reserved[2]; +}; +/* + * event notification ABI structures. + */ +struct ib_ucm_event_get { + __u64 response; + __u64 data; + __u64 info; + __u8 data_len; + __u8 info_len; + __u8 reserved[2]; +}; + +struct ib_ucm_req_event_resp { + __u32 listen_id; + /* device */ + /* port */ + struct ib_ucm_path_rec primary_path; + struct ib_ucm_path_rec alternate_path; + __be64 remote_ca_guid; + __u32 remote_qkey; + __u32 remote_qpn; + __u32 qp_type; + __u32 starting_psn; + __u8 responder_resources; + __u8 initiator_depth; + __u8 local_cm_response_timeout; + __u8 flow_control; + __u8 remote_cm_response_timeout; + __u8 retry_count; + __u8 rnr_retry_count; + __u8 srq; +}; + +struct ib_ucm_rep_event_resp { + __be64 remote_ca_guid; + __u32 remote_qkey; + __u32 remote_qpn; + __u32 starting_psn; + __u8 responder_resources; + __u8 initiator_depth; + __u8 target_ack_delay; + __u8 failover_accepted; + __u8 flow_control; + __u8 rnr_retry_count; + __u8 srq; + __u8 reserved[1]; +}; + +struct ib_ucm_rej_event_resp { + __u32 reason; + /* ari in ib_ucm_event_get info field. */ +}; + +struct ib_ucm_mra_event_resp { + __u8 timeout; + __u8 reserved[3]; +}; + +struct ib_ucm_lap_event_resp { + struct ib_ucm_path_rec path; +}; + +struct ib_ucm_apr_event_resp { + __u32 status; + /* apr info in ib_ucm_event_get info field. */ +}; + +struct ib_ucm_sidr_req_event_resp { + __u32 listen_id; + /* device */ + /* port */ + __u16 pkey; + __u8 reserved[2]; +}; + +struct ib_ucm_sidr_rep_event_resp { + __u32 status; + __u32 qkey; + __u32 qpn; + /* info in ib_ucm_event_get info field. */ +}; + +#define IB_UCM_PRES_DATA 0x01 +#define IB_UCM_PRES_INFO 0x02 +#define IB_UCM_PRES_PRIMARY 0x04 +#define IB_UCM_PRES_ALTERNATE 0x08 + +struct ib_ucm_event_resp { + __u32 id; + __u32 event; + __u32 present; + union { + struct ib_ucm_req_event_resp req_resp; + struct ib_ucm_rep_event_resp rep_resp; + struct ib_ucm_rej_event_resp rej_resp; + struct ib_ucm_mra_event_resp mra_resp; + struct ib_ucm_lap_event_resp lap_resp; + struct ib_ucm_apr_event_resp apr_resp; + + struct ib_ucm_sidr_req_event_resp sidr_req_resp; + struct ib_ucm_sidr_rep_event_resp sidr_rep_resp; + + __u32 send_status; + } u; +}; + +#endif /* IB_USER_CM_H */ diff --git a/include/rdma/ib_user_mad.h b/include/rdma/ib_user_mad.h new file mode 100644 index 000000000000..44537aa32e62 --- /dev/null +++ b/include/rdma/ib_user_mad.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2004 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Voltaire, Inc. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_user_mad.h 2814 2005-07-06 19:14:09Z halr $ + */ + +#ifndef IB_USER_MAD_H +#define IB_USER_MAD_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +/* + * Increment this value if any changes that break userspace ABI + * compatibility are made. + */ +#define IB_USER_MAD_ABI_VERSION 5 + +/* + * Make sure that all structs defined in this file remain laid out so + * that they pack the same way on 32-bit and 64-bit architectures (to + * avoid incompatibility between 32-bit userspace and 64-bit kernels). + */ + +/** + * ib_user_mad_hdr - MAD packet header + * @id - ID of agent MAD received with/to be sent with + * @status - 0 on successful receive, ETIMEDOUT if no response + * received (transaction ID in data[] will be set to TID of original + * request) (ignored on send) + * @timeout_ms - Milliseconds to wait for response (unset on receive) + * @retries - Number of automatic retries to attempt + * @qpn - Remote QP number received from/to be sent to + * @qkey - Remote Q_Key to be sent with (unset on receive) + * @lid - Remote lid received from/to be sent to + * @sl - Service level received with/to be sent with + * @path_bits - Local path bits received with/to be sent with + * @grh_present - If set, GRH was received/should be sent + * @gid_index - Local GID index to send with (unset on receive) + * @hop_limit - Hop limit in GRH + * @traffic_class - Traffic class in GRH + * @gid - Remote GID in GRH + * @flow_label - Flow label in GRH + */ +struct ib_user_mad_hdr { + __u32 id; + __u32 status; + __u32 timeout_ms; + __u32 retries; + __u32 length; + __be32 qpn; + __be32 qkey; + __be16 lid; + __u8 sl; + __u8 path_bits; + __u8 grh_present; + __u8 gid_index; + __u8 hop_limit; + __u8 traffic_class; + __u8 gid[16]; + __be32 flow_label; +}; + +/** + * ib_user_mad - MAD packet + * @hdr - MAD packet header + * @data - Contents of MAD + * + */ +struct ib_user_mad { + struct ib_user_mad_hdr hdr; + __u8 data[0]; +}; + +/** + * ib_user_mad_reg_req - MAD registration request + * @id - Set by the kernel; used to identify agent in future requests. + * @qpn - Queue pair number; must be 0 or 1. + * @method_mask - The caller will receive unsolicited MADs for any method + * where @method_mask = 1. + * @mgmt_class - Indicates which management class of MADs should be receive + * by the caller. This field is only required if the user wishes to + * receive unsolicited MADs, otherwise it should be 0. + * @mgmt_class_version - Indicates which version of MADs for the given + * management class to receive. + * @oui: Indicates IEEE OUI when mgmt_class is a vendor class + * in the range from 0x30 to 0x4f. Otherwise not used. + * @rmpp_version: If set, indicates the RMPP version used. + * + */ +struct ib_user_mad_reg_req { + __u32 id; + __u32 method_mask[4]; + __u8 qpn; + __u8 mgmt_class; + __u8 mgmt_class_version; + __u8 oui[3]; + __u8 rmpp_version; +}; + +#define IB_IOCTL_MAGIC 0x1b + +#define IB_USER_MAD_REGISTER_AGENT _IOWR(IB_IOCTL_MAGIC, 1, \ + struct ib_user_mad_reg_req) + +#define IB_USER_MAD_UNREGISTER_AGENT _IOW(IB_IOCTL_MAGIC, 2, __u32) + +#endif /* IB_USER_MAD_H */ diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h new file mode 100644 index 000000000000..7ebb01c8f996 --- /dev/null +++ b/include/rdma/ib_user_verbs.h @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2005 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_user_verbs.h 2708 2005-06-24 17:27:21Z roland $ + */ + +#ifndef IB_USER_VERBS_H +#define IB_USER_VERBS_H + +#include <linux/types.h> + +/* + * Increment this value if any changes that break userspace ABI + * compatibility are made. + */ +#define IB_USER_VERBS_ABI_VERSION 1 + +enum { + IB_USER_VERBS_CMD_QUERY_PARAMS, + IB_USER_VERBS_CMD_GET_CONTEXT, + IB_USER_VERBS_CMD_QUERY_DEVICE, + IB_USER_VERBS_CMD_QUERY_PORT, + IB_USER_VERBS_CMD_QUERY_GID, + IB_USER_VERBS_CMD_QUERY_PKEY, + IB_USER_VERBS_CMD_ALLOC_PD, + IB_USER_VERBS_CMD_DEALLOC_PD, + IB_USER_VERBS_CMD_CREATE_AH, + IB_USER_VERBS_CMD_MODIFY_AH, + IB_USER_VERBS_CMD_QUERY_AH, + IB_USER_VERBS_CMD_DESTROY_AH, + IB_USER_VERBS_CMD_REG_MR, + IB_USER_VERBS_CMD_REG_SMR, + IB_USER_VERBS_CMD_REREG_MR, + IB_USER_VERBS_CMD_QUERY_MR, + IB_USER_VERBS_CMD_DEREG_MR, + IB_USER_VERBS_CMD_ALLOC_MW, + IB_USER_VERBS_CMD_BIND_MW, + IB_USER_VERBS_CMD_DEALLOC_MW, + IB_USER_VERBS_CMD_CREATE_CQ, + IB_USER_VERBS_CMD_RESIZE_CQ, + IB_USER_VERBS_CMD_DESTROY_CQ, + IB_USER_VERBS_CMD_POLL_CQ, + IB_USER_VERBS_CMD_PEEK_CQ, + IB_USER_VERBS_CMD_REQ_NOTIFY_CQ, + IB_USER_VERBS_CMD_CREATE_QP, + IB_USER_VERBS_CMD_QUERY_QP, + IB_USER_VERBS_CMD_MODIFY_QP, + IB_USER_VERBS_CMD_DESTROY_QP, + IB_USER_VERBS_CMD_POST_SEND, + IB_USER_VERBS_CMD_POST_RECV, + IB_USER_VERBS_CMD_ATTACH_MCAST, + IB_USER_VERBS_CMD_DETACH_MCAST, + IB_USER_VERBS_CMD_CREATE_SRQ, + IB_USER_VERBS_CMD_MODIFY_SRQ, + IB_USER_VERBS_CMD_QUERY_SRQ, + IB_USER_VERBS_CMD_DESTROY_SRQ, + IB_USER_VERBS_CMD_POST_SRQ_RECV +}; + +/* + * Make sure that all structs defined in this file remain laid out so + * that they pack the same way on 32-bit and 64-bit architectures (to + * avoid incompatibility between 32-bit userspace and 64-bit kernels). + * In particular do not use pointer types -- pass pointers in __u64 + * instead. + */ + +struct ib_uverbs_async_event_desc { + __u64 element; + __u32 event_type; /* enum ib_event_type */ + __u32 reserved; +}; + +struct ib_uverbs_comp_event_desc { + __u64 cq_handle; +}; + +/* + * All commands from userspace should start with a __u32 command field + * followed by __u16 in_words and out_words fields (which give the + * length of the command block and response buffer if any in 32-bit + * words). The kernel driver will read these fields first and read + * the rest of the command struct based on these value. + */ + +struct ib_uverbs_cmd_hdr { + __u32 command; + __u16 in_words; + __u16 out_words; +}; + +/* + * No driver_data for "query params" command, since this is intended + * to be a core function with no possible device dependence. + */ +struct ib_uverbs_query_params { + __u64 response; +}; + +struct ib_uverbs_query_params_resp { + __u32 num_cq_events; +}; + +struct ib_uverbs_get_context { + __u64 response; + __u64 cq_fd_tab; + __u64 driver_data[0]; +}; + +struct ib_uverbs_get_context_resp { + __u32 async_fd; + __u32 reserved; +}; + +struct ib_uverbs_query_device { + __u64 response; + __u64 driver_data[0]; +}; + +struct ib_uverbs_query_device_resp { + __u64 fw_ver; + __be64 node_guid; + __be64 sys_image_guid; + __u64 max_mr_size; + __u64 page_size_cap; + __u32 vendor_id; + __u32 vendor_part_id; + __u32 hw_ver; + __u32 max_qp; + __u32 max_qp_wr; + __u32 device_cap_flags; + __u32 max_sge; + __u32 max_sge_rd; + __u32 max_cq; + __u32 max_cqe; + __u32 max_mr; + __u32 max_pd; + __u32 max_qp_rd_atom; + __u32 max_ee_rd_atom; + __u32 max_res_rd_atom; + __u32 max_qp_init_rd_atom; + __u32 max_ee_init_rd_atom; + __u32 atomic_cap; + __u32 max_ee; + __u32 max_rdd; + __u32 max_mw; + __u32 max_raw_ipv6_qp; + __u32 max_raw_ethy_qp; + __u32 max_mcast_grp; + __u32 max_mcast_qp_attach; + __u32 max_total_mcast_qp_attach; + __u32 max_ah; + __u32 max_fmr; + __u32 max_map_per_fmr; + __u32 max_srq; + __u32 max_srq_wr; + __u32 max_srq_sge; + __u16 max_pkeys; + __u8 local_ca_ack_delay; + __u8 phys_port_cnt; + __u8 reserved[4]; +}; + +struct ib_uverbs_query_port { + __u64 response; + __u8 port_num; + __u8 reserved[7]; + __u64 driver_data[0]; +}; + +struct ib_uverbs_query_port_resp { + __u32 port_cap_flags; + __u32 max_msg_sz; + __u32 bad_pkey_cntr; + __u32 qkey_viol_cntr; + __u32 gid_tbl_len; + __u16 pkey_tbl_len; + __u16 lid; + __u16 sm_lid; + __u8 state; + __u8 max_mtu; + __u8 active_mtu; + __u8 lmc; + __u8 max_vl_num; + __u8 sm_sl; + __u8 subnet_timeout; + __u8 init_type_reply; + __u8 active_width; + __u8 active_speed; + __u8 phys_state; + __u8 reserved[3]; +}; + +struct ib_uverbs_query_gid { + __u64 response; + __u8 port_num; + __u8 index; + __u8 reserved[6]; + __u64 driver_data[0]; +}; + +struct ib_uverbs_query_gid_resp { + __u8 gid[16]; +}; + +struct ib_uverbs_query_pkey { + __u64 response; + __u8 port_num; + __u8 index; + __u8 reserved[6]; + __u64 driver_data[0]; +}; + +struct ib_uverbs_query_pkey_resp { + __u16 pkey; + __u16 reserved; +}; + +struct ib_uverbs_alloc_pd { + __u64 response; + __u64 driver_data[0]; +}; + +struct ib_uverbs_alloc_pd_resp { + __u32 pd_handle; +}; + +struct ib_uverbs_dealloc_pd { + __u32 pd_handle; +}; + +struct ib_uverbs_reg_mr { + __u64 response; + __u64 start; + __u64 length; + __u64 hca_va; + __u32 pd_handle; + __u32 access_flags; + __u64 driver_data[0]; +}; + +struct ib_uverbs_reg_mr_resp { + __u32 mr_handle; + __u32 lkey; + __u32 rkey; +}; + +struct ib_uverbs_dereg_mr { + __u32 mr_handle; +}; + +struct ib_uverbs_create_cq { + __u64 response; + __u64 user_handle; + __u32 cqe; + __u32 event_handler; + __u64 driver_data[0]; +}; + +struct ib_uverbs_create_cq_resp { + __u32 cq_handle; + __u32 cqe; +}; + +struct ib_uverbs_destroy_cq { + __u32 cq_handle; +}; + +struct ib_uverbs_create_qp { + __u64 response; + __u64 user_handle; + __u32 pd_handle; + __u32 send_cq_handle; + __u32 recv_cq_handle; + __u32 srq_handle; + __u32 max_send_wr; + __u32 max_recv_wr; + __u32 max_send_sge; + __u32 max_recv_sge; + __u32 max_inline_data; + __u8 sq_sig_all; + __u8 qp_type; + __u8 is_srq; + __u8 reserved; + __u64 driver_data[0]; +}; + +struct ib_uverbs_create_qp_resp { + __u32 qp_handle; + __u32 qpn; +}; + +/* + * This struct needs to remain a multiple of 8 bytes to keep the + * alignment of the modify QP parameters. + */ +struct ib_uverbs_qp_dest { + __u8 dgid[16]; + __u32 flow_label; + __u16 dlid; + __u16 reserved; + __u8 sgid_index; + __u8 hop_limit; + __u8 traffic_class; + __u8 sl; + __u8 src_path_bits; + __u8 static_rate; + __u8 is_global; + __u8 port_num; +}; + +struct ib_uverbs_modify_qp { + struct ib_uverbs_qp_dest dest; + struct ib_uverbs_qp_dest alt_dest; + __u32 qp_handle; + __u32 attr_mask; + __u32 qkey; + __u32 rq_psn; + __u32 sq_psn; + __u32 dest_qp_num; + __u32 qp_access_flags; + __u16 pkey_index; + __u16 alt_pkey_index; + __u8 qp_state; + __u8 cur_qp_state; + __u8 path_mtu; + __u8 path_mig_state; + __u8 en_sqd_async_notify; + __u8 max_rd_atomic; + __u8 max_dest_rd_atomic; + __u8 min_rnr_timer; + __u8 port_num; + __u8 timeout; + __u8 retry_cnt; + __u8 rnr_retry; + __u8 alt_port_num; + __u8 alt_timeout; + __u8 reserved[2]; + __u64 driver_data[0]; +}; + +struct ib_uverbs_modify_qp_resp { +}; + +struct ib_uverbs_destroy_qp { + __u32 qp_handle; +}; + +struct ib_uverbs_attach_mcast { + __u8 gid[16]; + __u32 qp_handle; + __u16 mlid; + __u16 reserved; + __u64 driver_data[0]; +}; + +struct ib_uverbs_detach_mcast { + __u8 gid[16]; + __u32 qp_handle; + __u16 mlid; + __u16 reserved; + __u64 driver_data[0]; +}; + +struct ib_uverbs_create_srq { + __u64 response; + __u64 user_handle; + __u32 pd_handle; + __u32 max_wr; + __u32 max_sge; + __u32 srq_limit; + __u64 driver_data[0]; +}; + +struct ib_uverbs_create_srq_resp { + __u32 srq_handle; +}; + +struct ib_uverbs_modify_srq { + __u32 srq_handle; + __u32 attr_mask; + __u32 max_wr; + __u32 max_sge; + __u32 srq_limit; + __u32 reserved; + __u64 driver_data[0]; +}; + +struct ib_uverbs_destroy_srq { + __u32 srq_handle; +}; + +#endif /* IB_USER_VERBS_H */ diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h new file mode 100644 index 000000000000..e16cf94870f2 --- /dev/null +++ b/include/rdma/ib_verbs.h @@ -0,0 +1,1461 @@ +/* + * Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. + * Copyright (c) 2004 Infinicon Corporation. All rights reserved. + * Copyright (c) 2004 Intel Corporation. All rights reserved. + * Copyright (c) 2004 Topspin Corporation. All rights reserved. + * Copyright (c) 2004 Voltaire Corporation. All rights reserved. + * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * $Id: ib_verbs.h 1349 2004-12-16 21:09:43Z roland $ + */ + +#if !defined(IB_VERBS_H) +#define IB_VERBS_H + +#include <linux/types.h> +#include <linux/device.h> + +#include <asm/atomic.h> +#include <asm/scatterlist.h> +#include <asm/uaccess.h> + +union ib_gid { + u8 raw[16]; + struct { + __be64 subnet_prefix; + __be64 interface_id; + } global; +}; + +enum ib_node_type { + IB_NODE_CA = 1, + IB_NODE_SWITCH, + IB_NODE_ROUTER +}; + +enum ib_device_cap_flags { + IB_DEVICE_RESIZE_MAX_WR = 1, + IB_DEVICE_BAD_PKEY_CNTR = (1<<1), + IB_DEVICE_BAD_QKEY_CNTR = (1<<2), + IB_DEVICE_RAW_MULTI = (1<<3), + IB_DEVICE_AUTO_PATH_MIG = (1<<4), + IB_DEVICE_CHANGE_PHY_PORT = (1<<5), + IB_DEVICE_UD_AV_PORT_ENFORCE = (1<<6), + IB_DEVICE_CURR_QP_STATE_MOD = (1<<7), + IB_DEVICE_SHUTDOWN_PORT = (1<<8), + IB_DEVICE_INIT_TYPE = (1<<9), + IB_DEVICE_PORT_ACTIVE_EVENT = (1<<10), + IB_DEVICE_SYS_IMAGE_GUID = (1<<11), + IB_DEVICE_RC_RNR_NAK_GEN = (1<<12), + IB_DEVICE_SRQ_RESIZE = (1<<13), + IB_DEVICE_N_NOTIFY_CQ = (1<<14), +}; + +enum ib_atomic_cap { + IB_ATOMIC_NONE, + IB_ATOMIC_HCA, + IB_ATOMIC_GLOB +}; + +struct ib_device_attr { + u64 fw_ver; + __be64 node_guid; + __be64 sys_image_guid; + u64 max_mr_size; + u64 page_size_cap; + u32 vendor_id; + u32 vendor_part_id; + u32 hw_ver; + int max_qp; + int max_qp_wr; + int device_cap_flags; + int max_sge; + int max_sge_rd; + int max_cq; + int max_cqe; + int max_mr; + int max_pd; + int max_qp_rd_atom; + int max_ee_rd_atom; + int max_res_rd_atom; + int max_qp_init_rd_atom; + int max_ee_init_rd_atom; + enum ib_atomic_cap atomic_cap; + int max_ee; + int max_rdd; + int max_mw; + int max_raw_ipv6_qp; + int max_raw_ethy_qp; + int max_mcast_grp; + int max_mcast_qp_attach; + int max_total_mcast_qp_attach; + int max_ah; + int max_fmr; + int max_map_per_fmr; + int max_srq; + int max_srq_wr; + int max_srq_sge; + u16 max_pkeys; + u8 local_ca_ack_delay; +}; + +enum ib_mtu { + IB_MTU_256 = 1, + IB_MTU_512 = 2, + IB_MTU_1024 = 3, + IB_MTU_2048 = 4, + IB_MTU_4096 = 5 +}; + +static inline int ib_mtu_enum_to_int(enum ib_mtu mtu) +{ + switch (mtu) { + case IB_MTU_256: return 256; + case IB_MTU_512: return 512; + case IB_MTU_1024: return 1024; + case IB_MTU_2048: return 2048; + case IB_MTU_4096: return 4096; + default: return -1; + } +} + +enum ib_port_state { + IB_PORT_NOP = 0, + IB_PORT_DOWN = 1, + IB_PORT_INIT = 2, + IB_PORT_ARMED = 3, + IB_PORT_ACTIVE = 4, + IB_PORT_ACTIVE_DEFER = 5 +}; + +enum ib_port_cap_flags { + IB_PORT_SM = 1 << 1, + IB_PORT_NOTICE_SUP = 1 << 2, + IB_PORT_TRAP_SUP = 1 << 3, + IB_PORT_OPT_IPD_SUP = 1 << 4, + IB_PORT_AUTO_MIGR_SUP = 1 << 5, + IB_PORT_SL_MAP_SUP = 1 << 6, + IB_PORT_MKEY_NVRAM = 1 << 7, + IB_PORT_PKEY_NVRAM = 1 << 8, + IB_PORT_LED_INFO_SUP = 1 << 9, + IB_PORT_SM_DISABLED = 1 << 10, + IB_PORT_SYS_IMAGE_GUID_SUP = 1 << 11, + IB_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12, + IB_PORT_CM_SUP = 1 << 16, + IB_PORT_SNMP_TUNNEL_SUP = 1 << 17, + IB_PORT_REINIT_SUP = 1 << 18, + IB_PORT_DEVICE_MGMT_SUP = 1 << 19, + IB_PORT_VENDOR_CLASS_SUP = 1 << 20, + IB_PORT_DR_NOTICE_SUP = 1 << 21, + IB_PORT_CAP_MASK_NOTICE_SUP = 1 << 22, + IB_PORT_BOOT_MGMT_SUP = 1 << 23, + IB_PORT_LINK_LATENCY_SUP = 1 << 24, + IB_PORT_CLIENT_REG_SUP = 1 << 25 +}; + +enum ib_port_width { + IB_WIDTH_1X = 1, + IB_WIDTH_4X = 2, + IB_WIDTH_8X = 4, + IB_WIDTH_12X = 8 +}; + +static inline int ib_width_enum_to_int(enum ib_port_width width) +{ + switch (width) { + case IB_WIDTH_1X: return 1; + case IB_WIDTH_4X: return 4; + case IB_WIDTH_8X: return 8; + case IB_WIDTH_12X: return 12; + default: return -1; + } +} + +struct ib_port_attr { + enum ib_port_state state; + enum ib_mtu max_mtu; + enum ib_mtu active_mtu; + int gid_tbl_len; + u32 port_cap_flags; + u32 max_msg_sz; + u32 bad_pkey_cntr; + u32 qkey_viol_cntr; + u16 pkey_tbl_len; + u16 lid; + u16 sm_lid; + u8 lmc; + u8 max_vl_num; + u8 sm_sl; + u8 subnet_timeout; + u8 init_type_reply; + u8 active_width; + u8 active_speed; + u8 phys_state; +}; + +enum ib_device_modify_flags { + IB_DEVICE_MODIFY_SYS_IMAGE_GUID = 1 +}; + +struct ib_device_modify { + u64 sys_image_guid; +}; + +enum ib_port_modify_flags { + IB_PORT_SHUTDOWN = 1, + IB_PORT_INIT_TYPE = (1<<2), + IB_PORT_RESET_QKEY_CNTR = (1<<3) +}; + +struct ib_port_modify { + u32 set_port_cap_mask; + u32 clr_port_cap_mask; + u8 init_type; +}; + +enum ib_event_type { + IB_EVENT_CQ_ERR, + IB_EVENT_QP_FATAL, + IB_EVENT_QP_REQ_ERR, + IB_EVENT_QP_ACCESS_ERR, + IB_EVENT_COMM_EST, + IB_EVENT_SQ_DRAINED, + IB_EVENT_PATH_MIG, + IB_EVENT_PATH_MIG_ERR, + IB_EVENT_DEVICE_FATAL, + IB_EVENT_PORT_ACTIVE, + IB_EVENT_PORT_ERR, + IB_EVENT_LID_CHANGE, + IB_EVENT_PKEY_CHANGE, + IB_EVENT_SM_CHANGE, + IB_EVENT_SRQ_ERR, + IB_EVENT_SRQ_LIMIT_REACHED, + IB_EVENT_QP_LAST_WQE_REACHED +}; + +struct ib_event { + struct ib_device *device; + union { + struct ib_cq *cq; + struct ib_qp *qp; + struct ib_srq *srq; + u8 port_num; + } element; + enum ib_event_type event; +}; + +struct ib_event_handler { + struct ib_device *device; + void (*handler)(struct ib_event_handler *, struct ib_event *); + struct list_head list; +}; + +#define INIT_IB_EVENT_HANDLER(_ptr, _device, _handler) \ + do { \ + (_ptr)->device = _device; \ + (_ptr)->handler = _handler; \ + INIT_LIST_HEAD(&(_ptr)->list); \ + } while (0) + +struct ib_global_route { + union ib_gid dgid; + u32 flow_label; + u8 sgid_index; + u8 hop_limit; + u8 traffic_class; +}; + +struct ib_grh { + __be32 version_tclass_flow; + __be16 paylen; + u8 next_hdr; + u8 hop_limit; + union ib_gid sgid; + union ib_gid dgid; +}; + +enum { + IB_MULTICAST_QPN = 0xffffff +}; + +#define IB_LID_PERMISSIVE __constant_htons(0xFFFF) + +enum ib_ah_flags { + IB_AH_GRH = 1 +}; + +struct ib_ah_attr { + struct ib_global_route grh; + u16 dlid; + u8 sl; + u8 src_path_bits; + u8 static_rate; + u8 ah_flags; + u8 port_num; +}; + +enum ib_wc_status { + IB_WC_SUCCESS, + IB_WC_LOC_LEN_ERR, + IB_WC_LOC_QP_OP_ERR, + IB_WC_LOC_EEC_OP_ERR, + IB_WC_LOC_PROT_ERR, + IB_WC_WR_FLUSH_ERR, + IB_WC_MW_BIND_ERR, + IB_WC_BAD_RESP_ERR, + IB_WC_LOC_ACCESS_ERR, + IB_WC_REM_INV_REQ_ERR, + IB_WC_REM_ACCESS_ERR, + IB_WC_REM_OP_ERR, + IB_WC_RETRY_EXC_ERR, + IB_WC_RNR_RETRY_EXC_ERR, + IB_WC_LOC_RDD_VIOL_ERR, + IB_WC_REM_INV_RD_REQ_ERR, + IB_WC_REM_ABORT_ERR, + IB_WC_INV_EECN_ERR, + IB_WC_INV_EEC_STATE_ERR, + IB_WC_FATAL_ERR, + IB_WC_RESP_TIMEOUT_ERR, + IB_WC_GENERAL_ERR +}; + +enum ib_wc_opcode { + IB_WC_SEND, + IB_WC_RDMA_WRITE, + IB_WC_RDMA_READ, + IB_WC_COMP_SWAP, + IB_WC_FETCH_ADD, + IB_WC_BIND_MW, +/* + * Set value of IB_WC_RECV so consumers can test if a completion is a + * receive by testing (opcode & IB_WC_RECV). + */ + IB_WC_RECV = 1 << 7, + IB_WC_RECV_RDMA_WITH_IMM +}; + +enum ib_wc_flags { + IB_WC_GRH = 1, + IB_WC_WITH_IMM = (1<<1) +}; + +struct ib_wc { + u64 wr_id; + enum ib_wc_status status; + enum ib_wc_opcode opcode; + u32 vendor_err; + u32 byte_len; + __be32 imm_data; + u32 qp_num; + u32 src_qp; + int wc_flags; + u16 pkey_index; + u16 slid; + u8 sl; + u8 dlid_path_bits; + u8 port_num; /* valid only for DR SMPs on switches */ +}; + +enum ib_cq_notify { + IB_CQ_SOLICITED, + IB_CQ_NEXT_COMP +}; + +enum ib_srq_attr_mask { + IB_SRQ_MAX_WR = 1 << 0, + IB_SRQ_LIMIT = 1 << 1, +}; + +struct ib_srq_attr { + u32 max_wr; + u32 max_sge; + u32 srq_limit; +}; + +struct ib_srq_init_attr { + void (*event_handler)(struct ib_event *, void *); + void *srq_context; + struct ib_srq_attr attr; +}; + +struct ib_qp_cap { + u32 max_send_wr; + u32 max_recv_wr; + u32 max_send_sge; + u32 max_recv_sge; + u32 max_inline_data; +}; + +enum ib_sig_type { + IB_SIGNAL_ALL_WR, + IB_SIGNAL_REQ_WR +}; + +enum ib_qp_type { + /* + * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries + * here (and in that order) since the MAD layer uses them as + * indices into a 2-entry table. + */ + IB_QPT_SMI, + IB_QPT_GSI, + + IB_QPT_RC, + IB_QPT_UC, + IB_QPT_UD, + IB_QPT_RAW_IPV6, + IB_QPT_RAW_ETY +}; + +struct ib_qp_init_attr { + void (*event_handler)(struct ib_event *, void *); + void *qp_context; + struct ib_cq *send_cq; + struct ib_cq *recv_cq; + struct ib_srq *srq; + struct ib_qp_cap cap; + enum ib_sig_type sq_sig_type; + enum ib_qp_type qp_type; + u8 port_num; /* special QP types only */ +}; + +enum ib_rnr_timeout { + IB_RNR_TIMER_655_36 = 0, + IB_RNR_TIMER_000_01 = 1, + IB_RNR_TIMER_000_02 = 2, + IB_RNR_TIMER_000_03 = 3, + IB_RNR_TIMER_000_04 = 4, + IB_RNR_TIMER_000_06 = 5, + IB_RNR_TIMER_000_08 = 6, + IB_RNR_TIMER_000_12 = 7, + IB_RNR_TIMER_000_16 = 8, + IB_RNR_TIMER_000_24 = 9, + IB_RNR_TIMER_000_32 = 10, + IB_RNR_TIMER_000_48 = 11, + IB_RNR_TIMER_000_64 = 12, + IB_RNR_TIMER_000_96 = 13, + IB_RNR_TIMER_001_28 = 14, + IB_RNR_TIMER_001_92 = 15, + IB_RNR_TIMER_002_56 = 16, + IB_RNR_TIMER_003_84 = 17, + IB_RNR_TIMER_005_12 = 18, + IB_RNR_TIMER_007_68 = 19, + IB_RNR_TIMER_010_24 = 20, + IB_RNR_TIMER_015_36 = 21, + IB_RNR_TIMER_020_48 = 22, + IB_RNR_TIMER_030_72 = 23, + IB_RNR_TIMER_040_96 = 24, + IB_RNR_TIMER_061_44 = 25, + IB_RNR_TIMER_081_92 = 26, + IB_RNR_TIMER_122_88 = 27, + IB_RNR_TIMER_163_84 = 28, + IB_RNR_TIMER_245_76 = 29, + IB_RNR_TIMER_327_68 = 30, + IB_RNR_TIMER_491_52 = 31 +}; + +enum ib_qp_attr_mask { + IB_QP_STATE = 1, + IB_QP_CUR_STATE = (1<<1), + IB_QP_EN_SQD_ASYNC_NOTIFY = (1<<2), + IB_QP_ACCESS_FLAGS = (1<<3), + IB_QP_PKEY_INDEX = (1<<4), + IB_QP_PORT = (1<<5), + IB_QP_QKEY = (1<<6), + IB_QP_AV = (1<<7), + IB_QP_PATH_MTU = (1<<8), + IB_QP_TIMEOUT = (1<<9), + IB_QP_RETRY_CNT = (1<<10), + IB_QP_RNR_RETRY = (1<<11), + IB_QP_RQ_PSN = (1<<12), + IB_QP_MAX_QP_RD_ATOMIC = (1<<13), + IB_QP_ALT_PATH = (1<<14), + IB_QP_MIN_RNR_TIMER = (1<<15), + IB_QP_SQ_PSN = (1<<16), + IB_QP_MAX_DEST_RD_ATOMIC = (1<<17), + IB_QP_PATH_MIG_STATE = (1<<18), + IB_QP_CAP = (1<<19), + IB_QP_DEST_QPN = (1<<20) +}; + +enum ib_qp_state { + IB_QPS_RESET, + IB_QPS_INIT, + IB_QPS_RTR, + IB_QPS_RTS, + IB_QPS_SQD, + IB_QPS_SQE, + IB_QPS_ERR +}; + +enum ib_mig_state { + IB_MIG_MIGRATED, + IB_MIG_REARM, + IB_MIG_ARMED +}; + +struct ib_qp_attr { + enum ib_qp_state qp_state; + enum ib_qp_state cur_qp_state; + enum ib_mtu path_mtu; + enum ib_mig_state path_mig_state; + u32 qkey; + u32 rq_psn; + u32 sq_psn; + u32 dest_qp_num; + int qp_access_flags; + struct ib_qp_cap cap; + struct ib_ah_attr ah_attr; + struct ib_ah_attr alt_ah_attr; + u16 pkey_index; + u16 alt_pkey_index; + u8 en_sqd_async_notify; + u8 sq_draining; + u8 max_rd_atomic; + u8 max_dest_rd_atomic; + u8 min_rnr_timer; + u8 port_num; + u8 timeout; + u8 retry_cnt; + u8 rnr_retry; + u8 alt_port_num; + u8 alt_timeout; +}; + +enum ib_wr_opcode { + IB_WR_RDMA_WRITE, + IB_WR_RDMA_WRITE_WITH_IMM, + IB_WR_SEND, + IB_WR_SEND_WITH_IMM, + IB_WR_RDMA_READ, + IB_WR_ATOMIC_CMP_AND_SWP, + IB_WR_ATOMIC_FETCH_AND_ADD +}; + +enum ib_send_flags { + IB_SEND_FENCE = 1, + IB_SEND_SIGNALED = (1<<1), + IB_SEND_SOLICITED = (1<<2), + IB_SEND_INLINE = (1<<3) +}; + +struct ib_sge { + u64 addr; + u32 length; + u32 lkey; +}; + +struct ib_send_wr { + struct ib_send_wr *next; + u64 wr_id; + struct ib_sge *sg_list; + int num_sge; + enum ib_wr_opcode opcode; + int send_flags; + __be32 imm_data; + union { + struct { + u64 remote_addr; + u32 rkey; + } rdma; + struct { + u64 remote_addr; + u64 compare_add; + u64 swap; + u32 rkey; + } atomic; + struct { + struct ib_ah *ah; + struct ib_mad_hdr *mad_hdr; + u32 remote_qpn; + u32 remote_qkey; + int timeout_ms; /* valid for MADs only */ + int retries; /* valid for MADs only */ + u16 pkey_index; /* valid for GSI only */ + u8 port_num; /* valid for DR SMPs on switch only */ + } ud; + } wr; +}; + +struct ib_recv_wr { + struct ib_recv_wr *next; + u64 wr_id; + struct ib_sge *sg_list; + int num_sge; +}; + +enum ib_access_flags { + IB_ACCESS_LOCAL_WRITE = 1, + IB_ACCESS_REMOTE_WRITE = (1<<1), + IB_ACCESS_REMOTE_READ = (1<<2), + IB_ACCESS_REMOTE_ATOMIC = (1<<3), + IB_ACCESS_MW_BIND = (1<<4) +}; + +struct ib_phys_buf { + u64 addr; + u64 size; +}; + +struct ib_mr_attr { + struct ib_pd *pd; + u64 device_virt_addr; + u64 size; + int mr_access_flags; + u32 lkey; + u32 rkey; +}; + +enum ib_mr_rereg_flags { + IB_MR_REREG_TRANS = 1, + IB_MR_REREG_PD = (1<<1), + IB_MR_REREG_ACCESS = (1<<2) +}; + +struct ib_mw_bind { + struct ib_mr *mr; + u64 wr_id; + u64 addr; + u32 length; + int send_flags; + int mw_access_flags; +}; + +struct ib_fmr_attr { + int max_pages; + int max_maps; + u8 page_size; +}; + +struct ib_ucontext { + struct ib_device *device; + struct list_head pd_list; + struct list_head mr_list; + struct list_head mw_list; + struct list_head cq_list; + struct list_head qp_list; + struct list_head srq_list; + struct list_head ah_list; + spinlock_t lock; +}; + +struct ib_uobject { + u64 user_handle; /* handle given to us by userspace */ + struct ib_ucontext *context; /* associated user context */ + struct list_head list; /* link to context's list */ + u32 id; /* index into kernel idr */ +}; + +struct ib_umem { + unsigned long user_base; + unsigned long virt_base; + size_t length; + int offset; + int page_size; + int writable; + struct list_head chunk_list; +}; + +struct ib_umem_chunk { + struct list_head list; + int nents; + int nmap; + struct scatterlist page_list[0]; +}; + +struct ib_udata { + void __user *inbuf; + void __user *outbuf; + size_t inlen; + size_t outlen; +}; + +#define IB_UMEM_MAX_PAGE_CHUNK \ + ((PAGE_SIZE - offsetof(struct ib_umem_chunk, page_list)) / \ + ((void *) &((struct ib_umem_chunk *) 0)->page_list[1] - \ + (void *) &((struct ib_umem_chunk *) 0)->page_list[0])) + +struct ib_umem_object { + struct ib_uobject uobject; + struct ib_umem umem; +}; + +struct ib_pd { + struct ib_device *device; + struct ib_uobject *uobject; + atomic_t usecnt; /* count all resources */ +}; + +struct ib_ah { + struct ib_device *device; + struct ib_pd *pd; + struct ib_uobject *uobject; +}; + +typedef void (*ib_comp_handler)(struct ib_cq *cq, void *cq_context); + +struct ib_cq { + struct ib_device *device; + struct ib_uobject *uobject; + ib_comp_handler comp_handler; + void (*event_handler)(struct ib_event *, void *); + void * cq_context; + int cqe; + atomic_t usecnt; /* count number of work queues */ +}; + +struct ib_srq { + struct ib_device *device; + struct ib_pd *pd; + struct ib_uobject *uobject; + void (*event_handler)(struct ib_event *, void *); + void *srq_context; + atomic_t usecnt; +}; + +struct ib_qp { + struct ib_device *device; + struct ib_pd *pd; + struct ib_cq *send_cq; + struct ib_cq *recv_cq; + struct ib_srq *srq; + struct ib_uobject *uobject; + void (*event_handler)(struct ib_event *, void *); + void *qp_context; + u32 qp_num; + enum ib_qp_type qp_type; +}; + +struct ib_mr { + struct ib_device *device; + struct ib_pd *pd; + struct ib_uobject *uobject; + u32 lkey; + u32 rkey; + atomic_t usecnt; /* count number of MWs */ +}; + +struct ib_mw { + struct ib_device *device; + struct ib_pd *pd; + struct ib_uobject *uobject; + u32 rkey; +}; + +struct ib_fmr { + struct ib_device *device; + struct ib_pd *pd; + struct list_head list; + u32 lkey; + u32 rkey; +}; + +struct ib_mad; +struct ib_grh; + +enum ib_process_mad_flags { + IB_MAD_IGNORE_MKEY = 1, + IB_MAD_IGNORE_BKEY = 2, + IB_MAD_IGNORE_ALL = IB_MAD_IGNORE_MKEY | IB_MAD_IGNORE_BKEY +}; + +enum ib_mad_result { + IB_MAD_RESULT_FAILURE = 0, /* (!SUCCESS is the important flag) */ + IB_MAD_RESULT_SUCCESS = 1 << 0, /* MAD was successfully processed */ + IB_MAD_RESULT_REPLY = 1 << 1, /* Reply packet needs to be sent */ + IB_MAD_RESULT_CONSUMED = 1 << 2 /* Packet consumed: stop processing */ +}; + +#define IB_DEVICE_NAME_MAX 64 + +struct ib_cache { + rwlock_t lock; + struct ib_event_handler event_handler; + struct ib_pkey_cache **pkey_cache; + struct ib_gid_cache **gid_cache; +}; + +struct ib_device { + struct device *dma_device; + + char name[IB_DEVICE_NAME_MAX]; + + struct list_head event_handler_list; + spinlock_t event_handler_lock; + + struct list_head core_list; + struct list_head client_data_list; + spinlock_t client_data_lock; + + struct ib_cache cache; + + u32 flags; + + int (*query_device)(struct ib_device *device, + struct ib_device_attr *device_attr); + int (*query_port)(struct ib_device *device, + u8 port_num, + struct ib_port_attr *port_attr); + int (*query_gid)(struct ib_device *device, + u8 port_num, int index, + union ib_gid *gid); + int (*query_pkey)(struct ib_device *device, + u8 port_num, u16 index, u16 *pkey); + int (*modify_device)(struct ib_device *device, + int device_modify_mask, + struct ib_device_modify *device_modify); + int (*modify_port)(struct ib_device *device, + u8 port_num, int port_modify_mask, + struct ib_port_modify *port_modify); + struct ib_ucontext * (*alloc_ucontext)(struct ib_device *device, + struct ib_udata *udata); + int (*dealloc_ucontext)(struct ib_ucontext *context); + int (*mmap)(struct ib_ucontext *context, + struct vm_area_struct *vma); + struct ib_pd * (*alloc_pd)(struct ib_device *device, + struct ib_ucontext *context, + struct ib_udata *udata); + int (*dealloc_pd)(struct ib_pd *pd); + struct ib_ah * (*create_ah)(struct ib_pd *pd, + struct ib_ah_attr *ah_attr); + int (*modify_ah)(struct ib_ah *ah, + struct ib_ah_attr *ah_attr); + int (*query_ah)(struct ib_ah *ah, + struct ib_ah_attr *ah_attr); + int (*destroy_ah)(struct ib_ah *ah); + struct ib_srq * (*create_srq)(struct ib_pd *pd, + struct ib_srq_init_attr *srq_init_attr, + struct ib_udata *udata); + int (*modify_srq)(struct ib_srq *srq, + struct ib_srq_attr *srq_attr, + enum ib_srq_attr_mask srq_attr_mask); + int (*query_srq)(struct ib_srq *srq, + struct ib_srq_attr *srq_attr); + int (*destroy_srq)(struct ib_srq *srq); + int (*post_srq_recv)(struct ib_srq *srq, + struct ib_recv_wr *recv_wr, + struct ib_recv_wr **bad_recv_wr); + struct ib_qp * (*create_qp)(struct ib_pd *pd, + struct ib_qp_init_attr *qp_init_attr, + struct ib_udata *udata); + int (*modify_qp)(struct ib_qp *qp, + struct ib_qp_attr *qp_attr, + int qp_attr_mask); + int (*query_qp)(struct ib_qp *qp, + struct ib_qp_attr *qp_attr, + int qp_attr_mask, + struct ib_qp_init_attr *qp_init_attr); + int (*destroy_qp)(struct ib_qp *qp); + int (*post_send)(struct ib_qp *qp, + struct ib_send_wr *send_wr, + struct ib_send_wr **bad_send_wr); + int (*post_recv)(struct ib_qp *qp, + struct ib_recv_wr *recv_wr, + struct ib_recv_wr **bad_recv_wr); + struct ib_cq * (*create_cq)(struct ib_device *device, int cqe, + struct ib_ucontext *context, + struct ib_udata *udata); + int (*destroy_cq)(struct ib_cq *cq); + int (*resize_cq)(struct ib_cq *cq, int *cqe); + int (*poll_cq)(struct ib_cq *cq, int num_entries, + struct ib_wc *wc); + int (*peek_cq)(struct ib_cq *cq, int wc_cnt); + int (*req_notify_cq)(struct ib_cq *cq, + enum ib_cq_notify cq_notify); + int (*req_ncomp_notif)(struct ib_cq *cq, + int wc_cnt); + struct ib_mr * (*get_dma_mr)(struct ib_pd *pd, + int mr_access_flags); + struct ib_mr * (*reg_phys_mr)(struct ib_pd *pd, + struct ib_phys_buf *phys_buf_array, + int num_phys_buf, + int mr_access_flags, + u64 *iova_start); + struct ib_mr * (*reg_user_mr)(struct ib_pd *pd, + struct ib_umem *region, + int mr_access_flags, + struct ib_udata *udata); + int (*query_mr)(struct ib_mr *mr, + struct ib_mr_attr *mr_attr); + int (*dereg_mr)(struct ib_mr *mr); + int (*rereg_phys_mr)(struct ib_mr *mr, + int mr_rereg_mask, + struct ib_pd *pd, + struct ib_phys_buf *phys_buf_array, + int num_phys_buf, + int mr_access_flags, + u64 *iova_start); + struct ib_mw * (*alloc_mw)(struct ib_pd *pd); + int (*bind_mw)(struct ib_qp *qp, + struct ib_mw *mw, + struct ib_mw_bind *mw_bind); + int (*dealloc_mw)(struct ib_mw *mw); + struct ib_fmr * (*alloc_fmr)(struct ib_pd *pd, + int mr_access_flags, + struct ib_fmr_attr *fmr_attr); + int (*map_phys_fmr)(struct ib_fmr *fmr, + u64 *page_list, int list_len, + u64 iova); + int (*unmap_fmr)(struct list_head *fmr_list); + int (*dealloc_fmr)(struct ib_fmr *fmr); + int (*attach_mcast)(struct ib_qp *qp, + union ib_gid *gid, + u16 lid); + int (*detach_mcast)(struct ib_qp *qp, + union ib_gid *gid, + u16 lid); + int (*process_mad)(struct ib_device *device, + int process_mad_flags, + u8 port_num, + struct ib_wc *in_wc, + struct ib_grh *in_grh, + struct ib_mad *in_mad, + struct ib_mad *out_mad); + + struct module *owner; + struct class_device class_dev; + struct kobject ports_parent; + struct list_head port_list; + + enum { + IB_DEV_UNINITIALIZED, + IB_DEV_REGISTERED, + IB_DEV_UNREGISTERED + } reg_state; + + u8 node_type; + u8 phys_port_cnt; +}; + +struct ib_client { + char *name; + void (*add) (struct ib_device *); + void (*remove)(struct ib_device *); + + struct list_head list; +}; + +struct ib_device *ib_alloc_device(size_t size); +void ib_dealloc_device(struct ib_device *device); + +int ib_register_device (struct ib_device *device); +void ib_unregister_device(struct ib_device *device); + +int ib_register_client (struct ib_client *client); +void ib_unregister_client(struct ib_client *client); + +void *ib_get_client_data(struct ib_device *device, struct ib_client *client); +void ib_set_client_data(struct ib_device *device, struct ib_client *client, + void *data); + +static inline int ib_copy_from_udata(void *dest, struct ib_udata *udata, size_t len) +{ + return copy_from_user(dest, udata->inbuf, len) ? -EFAULT : 0; +} + +static inline int ib_copy_to_udata(struct ib_udata *udata, void *src, size_t len) +{ + return copy_to_user(udata->outbuf, src, len) ? -EFAULT : 0; +} + +int ib_register_event_handler (struct ib_event_handler *event_handler); +int ib_unregister_event_handler(struct ib_event_handler *event_handler); +void ib_dispatch_event(struct ib_event *event); + +int ib_query_device(struct ib_device *device, + struct ib_device_attr *device_attr); + +int ib_query_port(struct ib_device *device, + u8 port_num, struct ib_port_attr *port_attr); + +int ib_query_gid(struct ib_device *device, + u8 port_num, int index, union ib_gid *gid); + +int ib_query_pkey(struct ib_device *device, + u8 port_num, u16 index, u16 *pkey); + +int ib_modify_device(struct ib_device *device, + int device_modify_mask, + struct ib_device_modify *device_modify); + +int ib_modify_port(struct ib_device *device, + u8 port_num, int port_modify_mask, + struct ib_port_modify *port_modify); + +/** + * ib_alloc_pd - Allocates an unused protection domain. + * @device: The device on which to allocate the protection domain. + * + * A protection domain object provides an association between QPs, shared + * receive queues, address handles, memory regions, and memory windows. + */ +struct ib_pd *ib_alloc_pd(struct ib_device *device); + +/** + * ib_dealloc_pd - Deallocates a protection domain. + * @pd: The protection domain to deallocate. + */ +int ib_dealloc_pd(struct ib_pd *pd); + +/** + * ib_create_ah - Creates an address handle for the given address vector. + * @pd: The protection domain associated with the address handle. + * @ah_attr: The attributes of the address vector. + * + * The address handle is used to reference a local or global destination + * in all UD QP post sends. + */ +struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); + +/** + * ib_create_ah_from_wc - Creates an address handle associated with the + * sender of the specified work completion. + * @pd: The protection domain associated with the address handle. + * @wc: Work completion information associated with a received message. + * @grh: References the received global route header. This parameter is + * ignored unless the work completion indicates that the GRH is valid. + * @port_num: The outbound port number to associate with the address. + * + * The address handle is used to reference a local or global destination + * in all UD QP post sends. + */ +struct ib_ah *ib_create_ah_from_wc(struct ib_pd *pd, struct ib_wc *wc, + struct ib_grh *grh, u8 port_num); + +/** + * ib_modify_ah - Modifies the address vector associated with an address + * handle. + * @ah: The address handle to modify. + * @ah_attr: The new address vector attributes to associate with the + * address handle. + */ +int ib_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr); + +/** + * ib_query_ah - Queries the address vector associated with an address + * handle. + * @ah: The address handle to query. + * @ah_attr: The address vector attributes associated with the address + * handle. + */ +int ib_query_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr); + +/** + * ib_destroy_ah - Destroys an address handle. + * @ah: The address handle to destroy. + */ +int ib_destroy_ah(struct ib_ah *ah); + +/** + * ib_create_srq - Creates a SRQ associated with the specified protection + * domain. + * @pd: The protection domain associated with the SRQ. + * @srq_init_attr: A list of initial attributes required to create the SRQ. + * + * srq_attr->max_wr and srq_attr->max_sge are read the determine the + * requested size of the SRQ, and set to the actual values allocated + * on return. If ib_create_srq() succeeds, then max_wr and max_sge + * will always be at least as large as the requested values. + */ +struct ib_srq *ib_create_srq(struct ib_pd *pd, + struct ib_srq_init_attr *srq_init_attr); + +/** + * ib_modify_srq - Modifies the attributes for the specified SRQ. + * @srq: The SRQ to modify. + * @srq_attr: On input, specifies the SRQ attributes to modify. On output, + * the current values of selected SRQ attributes are returned. + * @srq_attr_mask: A bit-mask used to specify which attributes of the SRQ + * are being modified. + * + * The mask may contain IB_SRQ_MAX_WR to resize the SRQ and/or + * IB_SRQ_LIMIT to set the SRQ's limit and request notification when + * the number of receives queued drops below the limit. + */ +int ib_modify_srq(struct ib_srq *srq, + struct ib_srq_attr *srq_attr, + enum ib_srq_attr_mask srq_attr_mask); + +/** + * ib_query_srq - Returns the attribute list and current values for the + * specified SRQ. + * @srq: The SRQ to query. + * @srq_attr: The attributes of the specified SRQ. + */ +int ib_query_srq(struct ib_srq *srq, + struct ib_srq_attr *srq_attr); + +/** + * ib_destroy_srq - Destroys the specified SRQ. + * @srq: The SRQ to destroy. + */ +int ib_destroy_srq(struct ib_srq *srq); + +/** + * ib_post_srq_recv - Posts a list of work requests to the specified SRQ. + * @srq: The SRQ to post the work request on. + * @recv_wr: A list of work requests to post on the receive queue. + * @bad_recv_wr: On an immediate failure, this parameter will reference + * the work request that failed to be posted on the QP. + */ +static inline int ib_post_srq_recv(struct ib_srq *srq, + struct ib_recv_wr *recv_wr, + struct ib_recv_wr **bad_recv_wr) +{ + return srq->device->post_srq_recv(srq, recv_wr, bad_recv_wr); +} + +/** + * ib_create_qp - Creates a QP associated with the specified protection + * domain. + * @pd: The protection domain associated with the QP. + * @qp_init_attr: A list of initial attributes required to create the QP. + */ +struct ib_qp *ib_create_qp(struct ib_pd *pd, + struct ib_qp_init_attr *qp_init_attr); + +/** + * ib_modify_qp - Modifies the attributes for the specified QP and then + * transitions the QP to the given state. + * @qp: The QP to modify. + * @qp_attr: On input, specifies the QP attributes to modify. On output, + * the current values of selected QP attributes are returned. + * @qp_attr_mask: A bit-mask used to specify which attributes of the QP + * are being modified. + */ +int ib_modify_qp(struct ib_qp *qp, + struct ib_qp_attr *qp_attr, + int qp_attr_mask); + +/** + * ib_query_qp - Returns the attribute list and current values for the + * specified QP. + * @qp: The QP to query. + * @qp_attr: The attributes of the specified QP. + * @qp_attr_mask: A bit-mask used to select specific attributes to query. + * @qp_init_attr: Additional attributes of the selected QP. + * + * The qp_attr_mask may be used to limit the query to gathering only the + * selected attributes. + */ +int ib_query_qp(struct ib_qp *qp, + struct ib_qp_attr *qp_attr, + int qp_attr_mask, + struct ib_qp_init_attr *qp_init_attr); + +/** + * ib_destroy_qp - Destroys the specified QP. + * @qp: The QP to destroy. + */ +int ib_destroy_qp(struct ib_qp *qp); + +/** + * ib_post_send - Posts a list of work requests to the send queue of + * the specified QP. + * @qp: The QP to post the work request on. + * @send_wr: A list of work requests to post on the send queue. + * @bad_send_wr: On an immediate failure, this parameter will reference + * the work request that failed to be posted on the QP. + */ +static inline int ib_post_send(struct ib_qp *qp, + struct ib_send_wr *send_wr, + struct ib_send_wr **bad_send_wr) +{ + return qp->device->post_send(qp, send_wr, bad_send_wr); +} + +/** + * ib_post_recv - Posts a list of work requests to the receive queue of + * the specified QP. + * @qp: The QP to post the work request on. + * @recv_wr: A list of work requests to post on the receive queue. + * @bad_recv_wr: On an immediate failure, this parameter will reference + * the work request that failed to be posted on the QP. + */ +static inline int ib_post_recv(struct ib_qp *qp, + struct ib_recv_wr *recv_wr, + struct ib_recv_wr **bad_recv_wr) +{ + return qp->device->post_recv(qp, recv_wr, bad_recv_wr); +} + +/** + * ib_create_cq - Creates a CQ on the specified device. + * @device: The device on which to create the CQ. + * @comp_handler: A user-specified callback that is invoked when a + * completion event occurs on the CQ. + * @event_handler: A user-specified callback that is invoked when an + * asynchronous event not associated with a completion occurs on the CQ. + * @cq_context: Context associated with the CQ returned to the user via + * the associated completion and event handlers. + * @cqe: The minimum size of the CQ. + * + * Users can examine the cq structure to determine the actual CQ size. + */ +struct ib_cq *ib_create_cq(struct ib_device *device, + ib_comp_handler comp_handler, + void (*event_handler)(struct ib_event *, void *), + void *cq_context, int cqe); + +/** + * ib_resize_cq - Modifies the capacity of the CQ. + * @cq: The CQ to resize. + * @cqe: The minimum size of the CQ. + * + * Users can examine the cq structure to determine the actual CQ size. + */ +int ib_resize_cq(struct ib_cq *cq, int cqe); + +/** + * ib_destroy_cq - Destroys the specified CQ. + * @cq: The CQ to destroy. + */ +int ib_destroy_cq(struct ib_cq *cq); + +/** + * ib_poll_cq - poll a CQ for completion(s) + * @cq:the CQ being polled + * @num_entries:maximum number of completions to return + * @wc:array of at least @num_entries &struct ib_wc where completions + * will be returned + * + * Poll a CQ for (possibly multiple) completions. If the return value + * is < 0, an error occurred. If the return value is >= 0, it is the + * number of completions returned. If the return value is + * non-negative and < num_entries, then the CQ was emptied. + */ +static inline int ib_poll_cq(struct ib_cq *cq, int num_entries, + struct ib_wc *wc) +{ + return cq->device->poll_cq(cq, num_entries, wc); +} + +/** + * ib_peek_cq - Returns the number of unreaped completions currently + * on the specified CQ. + * @cq: The CQ to peek. + * @wc_cnt: A minimum number of unreaped completions to check for. + * + * If the number of unreaped completions is greater than or equal to wc_cnt, + * this function returns wc_cnt, otherwise, it returns the actual number of + * unreaped completions. + */ +int ib_peek_cq(struct ib_cq *cq, int wc_cnt); + +/** + * ib_req_notify_cq - Request completion notification on a CQ. + * @cq: The CQ to generate an event for. + * @cq_notify: If set to %IB_CQ_SOLICITED, completion notification will + * occur on the next solicited event. If set to %IB_CQ_NEXT_COMP, + * notification will occur on the next completion. + */ +static inline int ib_req_notify_cq(struct ib_cq *cq, + enum ib_cq_notify cq_notify) +{ + return cq->device->req_notify_cq(cq, cq_notify); +} + +/** + * ib_req_ncomp_notif - Request completion notification when there are + * at least the specified number of unreaped completions on the CQ. + * @cq: The CQ to generate an event for. + * @wc_cnt: The number of unreaped completions that should be on the + * CQ before an event is generated. + */ +static inline int ib_req_ncomp_notif(struct ib_cq *cq, int wc_cnt) +{ + return cq->device->req_ncomp_notif ? + cq->device->req_ncomp_notif(cq, wc_cnt) : + -ENOSYS; +} + +/** + * ib_get_dma_mr - Returns a memory region for system memory that is + * usable for DMA. + * @pd: The protection domain associated with the memory region. + * @mr_access_flags: Specifies the memory access rights. + */ +struct ib_mr *ib_get_dma_mr(struct ib_pd *pd, int mr_access_flags); + +/** + * ib_reg_phys_mr - Prepares a virtually addressed memory region for use + * by an HCA. + * @pd: The protection domain associated assigned to the registered region. + * @phys_buf_array: Specifies a list of physical buffers to use in the + * memory region. + * @num_phys_buf: Specifies the size of the phys_buf_array. + * @mr_access_flags: Specifies the memory access rights. + * @iova_start: The offset of the region's starting I/O virtual address. + */ +struct ib_mr *ib_reg_phys_mr(struct ib_pd *pd, + struct ib_phys_buf *phys_buf_array, + int num_phys_buf, + int mr_access_flags, + u64 *iova_start); + +/** + * ib_rereg_phys_mr - Modifies the attributes of an existing memory region. + * Conceptually, this call performs the functions deregister memory region + * followed by register physical memory region. Where possible, + * resources are reused instead of deallocated and reallocated. + * @mr: The memory region to modify. + * @mr_rereg_mask: A bit-mask used to indicate which of the following + * properties of the memory region are being modified. + * @pd: If %IB_MR_REREG_PD is set in mr_rereg_mask, this field specifies + * the new protection domain to associated with the memory region, + * otherwise, this parameter is ignored. + * @phys_buf_array: If %IB_MR_REREG_TRANS is set in mr_rereg_mask, this + * field specifies a list of physical buffers to use in the new + * translation, otherwise, this parameter is ignored. + * @num_phys_buf: If %IB_MR_REREG_TRANS is set in mr_rereg_mask, this + * field specifies the size of the phys_buf_array, otherwise, this + * parameter is ignored. + * @mr_access_flags: If %IB_MR_REREG_ACCESS is set in mr_rereg_mask, this + * field specifies the new memory access rights, otherwise, this + * parameter is ignored. + * @iova_start: The offset of the region's starting I/O virtual address. + */ +int ib_rereg_phys_mr(struct ib_mr *mr, + int mr_rereg_mask, + struct ib_pd *pd, + struct ib_phys_buf *phys_buf_array, + int num_phys_buf, + int mr_access_flags, + u64 *iova_start); + +/** + * ib_query_mr - Retrieves information about a specific memory region. + * @mr: The memory region to retrieve information about. + * @mr_attr: The attributes of the specified memory region. + */ +int ib_query_mr(struct ib_mr *mr, struct ib_mr_attr *mr_attr); + +/** + * ib_dereg_mr - Deregisters a memory region and removes it from the + * HCA translation table. + * @mr: The memory region to deregister. + */ +int ib_dereg_mr(struct ib_mr *mr); + +/** + * ib_alloc_mw - Allocates a memory window. + * @pd: The protection domain associated with the memory window. + */ +struct ib_mw *ib_alloc_mw(struct ib_pd *pd); + +/** + * ib_bind_mw - Posts a work request to the send queue of the specified + * QP, which binds the memory window to the given address range and + * remote access attributes. + * @qp: QP to post the bind work request on. + * @mw: The memory window to bind. + * @mw_bind: Specifies information about the memory window, including + * its address range, remote access rights, and associated memory region. + */ +static inline int ib_bind_mw(struct ib_qp *qp, + struct ib_mw *mw, + struct ib_mw_bind *mw_bind) +{ + /* XXX reference counting in corresponding MR? */ + return mw->device->bind_mw ? + mw->device->bind_mw(qp, mw, mw_bind) : + -ENOSYS; +} + +/** + * ib_dealloc_mw - Deallocates a memory window. + * @mw: The memory window to deallocate. + */ +int ib_dealloc_mw(struct ib_mw *mw); + +/** + * ib_alloc_fmr - Allocates a unmapped fast memory region. + * @pd: The protection domain associated with the unmapped region. + * @mr_access_flags: Specifies the memory access rights. + * @fmr_attr: Attributes of the unmapped region. + * + * A fast memory region must be mapped before it can be used as part of + * a work request. + */ +struct ib_fmr *ib_alloc_fmr(struct ib_pd *pd, + int mr_access_flags, + struct ib_fmr_attr *fmr_attr); + +/** + * ib_map_phys_fmr - Maps a list of physical pages to a fast memory region. + * @fmr: The fast memory region to associate with the pages. + * @page_list: An array of physical pages to map to the fast memory region. + * @list_len: The number of pages in page_list. + * @iova: The I/O virtual address to use with the mapped region. + */ +static inline int ib_map_phys_fmr(struct ib_fmr *fmr, + u64 *page_list, int list_len, + u64 iova) +{ + return fmr->device->map_phys_fmr(fmr, page_list, list_len, iova); +} + +/** + * ib_unmap_fmr - Removes the mapping from a list of fast memory regions. + * @fmr_list: A linked list of fast memory regions to unmap. + */ +int ib_unmap_fmr(struct list_head *fmr_list); + +/** + * ib_dealloc_fmr - Deallocates a fast memory region. + * @fmr: The fast memory region to deallocate. + */ +int ib_dealloc_fmr(struct ib_fmr *fmr); + +/** + * ib_attach_mcast - Attaches the specified QP to a multicast group. + * @qp: QP to attach to the multicast group. The QP must be type + * IB_QPT_UD. + * @gid: Multicast group GID. + * @lid: Multicast group LID in host byte order. + * + * In order to send and receive multicast packets, subnet + * administration must have created the multicast group and configured + * the fabric appropriately. The port associated with the specified + * QP must also be a member of the multicast group. + */ +int ib_attach_mcast(struct ib_qp *qp, union ib_gid *gid, u16 lid); + +/** + * ib_detach_mcast - Detaches the specified QP from a multicast group. + * @qp: QP to detach from the multicast group. + * @gid: Multicast group GID. + * @lid: Multicast group LID in host byte order. + */ +int ib_detach_mcast(struct ib_qp *qp, union ib_gid *gid, u16 lid); + +#endif /* IB_VERBS_H */ diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h index 1fb233741513..b361172b576c 100644 --- a/include/scsi/scsi.h +++ b/include/scsi/scsi.h @@ -28,7 +28,7 @@ extern const unsigned char scsi_command_size[8]; * SCSI device types */ -#define MAX_SCSI_DEVICE_CODE 14 +#define MAX_SCSI_DEVICE_CODE 15 extern const char *const scsi_device_types[MAX_SCSI_DEVICE_CODE]; /* @@ -211,8 +211,8 @@ static inline int scsi_status_is_good(int status) * - treated as TYPE_DISK */ #define TYPE_MEDIUM_CHANGER 0x08 #define TYPE_COMM 0x09 /* Communications device */ -#define TYPE_ENCLOSURE 0x0d /* Enclosure Services Device */ #define TYPE_RAID 0x0c +#define TYPE_ENCLOSURE 0x0d /* Enclosure Services Device */ #define TYPE_RBC 0x0e #define TYPE_NO_LUN 0x7f diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h index 07f5c699eaa7..9957f16dcc5d 100644 --- a/include/scsi/scsi_cmnd.h +++ b/include/scsi/scsi_cmnd.h @@ -31,14 +31,11 @@ struct scsi_cmnd { int sc_magic; struct scsi_device *device; - unsigned short state; - unsigned short owner; struct scsi_request *sc_request; struct list_head list; /* scsi_cmnd participates in queue lists */ struct list_head eh_entry; /* entry for the host eh_cmd_q */ - int eh_state; /* Used for state tracking in error handlr */ int eh_eflags; /* Used by error handlr */ void (*done) (struct scsi_cmnd *); /* Mid-level done function */ @@ -80,8 +77,6 @@ struct scsi_cmnd { * sense info */ unsigned short use_sg; /* Number of pieces of scatter-gather */ unsigned short sglist_len; /* size of malloc'd scatter-gather list */ - unsigned short abort_reason; /* If the mid-level code requests an - * abort, this is the reason. */ unsigned bufflen; /* Size of data buffer */ void *buffer; /* Data buffer */ diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h index 63c91dd85ca1..835af8ecbb7c 100644 --- a/include/scsi/scsi_device.h +++ b/include/scsi/scsi_device.h @@ -9,7 +9,7 @@ struct request_queue; struct scsi_cmnd; struct scsi_mode_data; - +struct scsi_lun; /* * sdev state: If you alter this, you also need to alter scsi_sysfs.c @@ -243,6 +243,7 @@ extern void scsi_target_reap(struct scsi_target *); extern void scsi_target_block(struct device *); extern void scsi_target_unblock(struct device *); extern void scsi_remove_target(struct device *); +extern void int_to_scsilun(unsigned int, struct scsi_lun *); extern const char *scsi_device_state_name(enum scsi_device_state); extern int scsi_is_sdev_device(const struct device *); extern int scsi_is_target_device(const struct device *); diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h index db9914adeac9..81d5234f6771 100644 --- a/include/scsi/scsi_host.h +++ b/include/scsi/scsi_host.h @@ -641,12 +641,6 @@ static inline void scsi_assign_lock(struct Scsi_Host *shost, spinlock_t *lock) shost->host_lock = lock; } -static inline void scsi_set_device(struct Scsi_Host *shost, - struct device *dev) -{ - shost->shost_gendev.parent = dev; -} - static inline struct device *scsi_get_device(struct Scsi_Host *shost) { return shost->shost_gendev.parent; diff --git a/include/scsi/scsi_transport.h b/include/scsi/scsi_transport.h index a4f1837a33b1..f6e0bb484c63 100644 --- a/include/scsi/scsi_transport.h +++ b/include/scsi/scsi_transport.h @@ -29,6 +29,14 @@ struct scsi_transport_template { struct transport_container target_attrs; struct transport_container device_attrs; + /* + * If set, call target_parent prior to allocating a scsi_target, + * so we get the appropriate parent for the target. This function + * is required for transports like FC and iSCSI that do not put the + * scsi_target under scsi_host. + */ + struct device *(*target_parent)(struct Scsi_Host *, int, uint); + /* The size of the specific transport attribute structure (a * space of this size will be left at the end of the * scsi_* structure */ diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h index 1309c12b8f71..2857cf0472df 100644 --- a/include/sound/ac97_codec.h +++ b/include/sound/ac97_codec.h @@ -26,6 +26,7 @@ */ #include <linux/bitops.h> +#include <linux/device.h> #include "pcm.h" #include "control.h" #include "info.h" @@ -374,6 +375,9 @@ #define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */ #define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */ #define AC97_HAS_NO_CD (1<<14) /* no CD volume */ +#define AC97_HAS_NO_MIC (1<<15) /* no MIC volume */ +#define AC97_HAS_NO_TONE (1<<16) /* no Tone volume */ +#define AC97_HAS_NO_STD_PCM (1<<17) /* no standard AC97 PCM volume and mute */ /* rates indexes */ #define AC97_RATES_FRONT_DAC 0 @@ -520,6 +524,7 @@ struct _snd_ac97 { /* jack-sharing info */ unsigned char indep_surround; unsigned char channel_mode; + struct device dev; }; /* conditions */ @@ -599,4 +604,8 @@ struct ac97_enum { unsigned short mask; const char **texts; }; + +/* ad hoc AC97 device driver access */ +extern struct bus_type ac97_bus_type; + #endif /* __SOUND_AC97_CODEC_H */ diff --git a/include/sound/ad1816a.h b/include/sound/ad1816a.h index 395978e375cf..ca2e0e4fa937 100644 --- a/include/sound/ad1816a.h +++ b/include/sound/ad1816a.h @@ -138,6 +138,7 @@ struct _snd_ad1816a { spinlock_t lock; unsigned short mode; + unsigned int clock_freq; snd_card_t *card; snd_pcm_t *pcm; diff --git a/include/sound/asound.h b/include/sound/asound.h index 9974f83cca44..8e552d627fa5 100644 --- a/include/sound/asound.h +++ b/include/sound/asound.h @@ -560,7 +560,7 @@ enum { * Timer section - /dev/snd/timer */ -#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 4) +#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 5) enum sndrv_timer_class { SNDRV_TIMER_CLASS_NONE = -1, @@ -693,11 +693,15 @@ enum sndrv_timer_event { SNDRV_TIMER_EVENT_CONTINUE, /* val = resolution in ns */ SNDRV_TIMER_EVENT_PAUSE, /* val = 0 */ SNDRV_TIMER_EVENT_EARLY, /* val = 0, early event */ + SNDRV_TIMER_EVENT_SUSPEND, /* val = 0 */ + SNDRV_TIMER_EVENT_RESUME, /* val = resolution in ns */ /* master timer events for slave timer instances */ SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10, SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10, SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10, SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10, + SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10, + SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, }; struct sndrv_timer_tread { diff --git a/include/sound/core.h b/include/sound/core.h index f8c4ef0aa352..f72b3ef515e2 100644 --- a/include/sound/core.h +++ b/include/sound/core.h @@ -126,25 +126,26 @@ struct snd_monitor_file { struct snd_monitor_file *next; }; -struct snd_shutdown_f_ops; /* define it later */ +struct snd_shutdown_f_ops; /* define it later in init.c */ /* main structure for soundcard */ struct _snd_card { - int number; /* number of soundcard (index to snd_cards) */ + int number; /* number of soundcard (index to + snd_cards) */ char id[16]; /* id string of this card */ char driver[16]; /* driver name */ char shortname[32]; /* short name of this soundcard */ char longname[80]; /* name of this soundcard */ char mixername[80]; /* mixer name */ - char components[80]; /* card components delimited with space */ - + char components[80]; /* card components delimited with + space */ struct module *module; /* top-level module */ void *private_data; /* private data for soundcard */ - void (*private_free) (snd_card_t *card); /* callback for freeing of private data */ - + void (*private_free) (snd_card_t *card); /* callback for freeing of + private data */ struct list_head devices; /* devices */ unsigned int last_numid; /* last used numeric ID */ @@ -160,7 +161,8 @@ struct _snd_card { struct proc_dir_entry *proc_root_link; /* number link to real id */ struct snd_monitor_file *files; /* all files associated to this card */ - struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown state */ + struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown + state */ spinlock_t files_lock; /* lock the files for this card */ int shutdown; /* this card is going down */ wait_queue_head_t shutdown_sleep; @@ -196,8 +198,6 @@ static inline void snd_power_unlock(snd_card_t *card) up(&card->power_lock); } -int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file); - static inline unsigned int snd_power_get_state(snd_card_t *card) { return card->power_state; @@ -208,6 +208,10 @@ static inline void snd_power_change_state(snd_card_t *card, unsigned int state) card->power_state = state; wake_up(&card->power_sleep); } + +/* init.c */ +int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file); + int snd_card_set_pm_callback(snd_card_t *card, int (*suspend)(snd_card_t *, pm_message_t), int (*resume)(snd_card_t *), @@ -238,15 +242,14 @@ static inline int snd_power_wait(snd_card_t *card, unsigned int state, struct fi #endif /* CONFIG_PM */ -/* device.c */ - struct _snd_minor { struct list_head list; /* list of all minors per card */ int number; /* minor number */ int device; /* device number */ const char *comment; /* for /proc/asound/devices */ struct file_operations *f_ops; /* file operations */ - char name[0]; /* device name (keep at the end of structure) */ + char name[0]; /* device name (keep at the end of + structure) */ }; typedef struct _snd_minor snd_minor_t; @@ -287,12 +290,12 @@ void snd_memory_init(void); void snd_memory_done(void); int snd_memory_info_init(void); int snd_memory_info_done(void); -void *snd_hidden_kmalloc(size_t size, int flags); -void *snd_hidden_kcalloc(size_t n, size_t size, int flags); +void *snd_hidden_kmalloc(size_t size, unsigned int __nocast flags); +void *snd_hidden_kcalloc(size_t n, size_t size, unsigned int __nocast flags); void snd_hidden_kfree(const void *obj); void *snd_hidden_vmalloc(unsigned long size); void snd_hidden_vfree(void *obj); -char *snd_hidden_kstrdup(const char *s, int flags); +char *snd_hidden_kstrdup(const char *s, unsigned int __nocast flags); #define kmalloc(size, flags) snd_hidden_kmalloc(size, flags) #define kcalloc(n, size, flags) snd_hidden_kcalloc(n, size, flags) #define kfree(obj) snd_hidden_kfree(obj) @@ -357,11 +360,13 @@ int snd_device_free_all(snd_card_t *card, snd_device_cmd_t cmd); /* isadma.c */ +#ifdef CONFIG_ISA_DMA_API #define DMA_MODE_NO_ENABLE 0x0100 void snd_dma_program(unsigned long dma, unsigned long addr, unsigned int size, unsigned short mode); void snd_dma_disable(unsigned long dma); unsigned int snd_dma_pointer(unsigned long dma, unsigned int size); +#endif /* misc.c */ @@ -411,7 +416,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...) printk(fmt ,##args) #endif /** - * snd_assert - run-time assersion macro + * snd_assert - run-time assertion macro * @expr: expression * @args...: the action * @@ -427,7 +432,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...) }\ } while (0) /** - * snd_runtime_check - run-time assersion macro + * snd_runtime_check - run-time assertion macro * @expr: expression * @args...: the action * diff --git a/include/sound/cs46xx.h b/include/sound/cs46xx.h index 182dd276ee74..9b94510eda60 100644 --- a/include/sound/cs46xx.h +++ b/include/sound/cs46xx.h @@ -1748,7 +1748,7 @@ int snd_cs46xx_pcm(cs46xx_t *chip, int device, snd_pcm_t **rpcm); int snd_cs46xx_pcm_rear(cs46xx_t *chip, int device, snd_pcm_t **rpcm); int snd_cs46xx_pcm_iec958(cs46xx_t *chip, int device, snd_pcm_t **rpcm); int snd_cs46xx_pcm_center_lfe(cs46xx_t *chip, int device, snd_pcm_t **rpcm); -int snd_cs46xx_mixer(cs46xx_t *chip); +int snd_cs46xx_mixer(cs46xx_t *chip, int spdif_device); int snd_cs46xx_midi(cs46xx_t *chip, int device, snd_rawmidi_t **rmidi); int snd_cs46xx_start_dsp(cs46xx_t *chip); int snd_cs46xx_gameport(cs46xx_t *chip); diff --git a/include/sound/driver.h b/include/sound/driver.h index 948e9a1aebef..0d12456ec3ae 100644 --- a/include/sound/driver.h +++ b/include/sound/driver.h @@ -51,7 +51,7 @@ #ifdef CONFIG_SND_DEBUG_MEMORY #include <linux/slab.h> #include <linux/vmalloc.h> -void *snd_wrapper_kmalloc(size_t, int); +void *snd_wrapper_kmalloc(size_t, unsigned int __nocast); #undef kmalloc void snd_wrapper_kfree(const void *); #undef kfree diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h index c50b91958ff9..4e3993dfcefe 100644 --- a/include/sound/emu10k1.h +++ b/include/sound/emu10k1.h @@ -1167,6 +1167,7 @@ int snd_emu10k1_create(snd_card_t * card, unsigned short extout_mask, long max_cache_bytes, int enable_ir, + uint subsystem, emu10k1_t ** remu); int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm); @@ -1177,7 +1178,7 @@ int snd_p16v_free(emu10k1_t * emu); int snd_p16v_mixer(emu10k1_t * emu); int snd_emu10k1_pcm_multi(emu10k1_t * emu, int device, snd_pcm_t ** rpcm); int snd_emu10k1_fx8010_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm); -int snd_emu10k1_mixer(emu10k1_t * emu); +int snd_emu10k1_mixer(emu10k1_t * emu, int pcm_device, int multi_device); int snd_emu10k1_timer(emu10k1_t * emu, int device); int snd_emu10k1_fx8010_new(emu10k1_t *emu, int device, snd_hwdep_t ** rhwdep); diff --git a/include/sound/gus.h b/include/sound/gus.h index b4b461ca173d..7000d9d9199d 100644 --- a/include/sound/gus.h +++ b/include/sound/gus.h @@ -512,13 +512,13 @@ extern void snd_gf1_ctrl_stop(snd_gus_card_t * gus, unsigned char reg); extern void snd_gf1_write8(snd_gus_card_t * gus, unsigned char reg, unsigned char data); extern unsigned char snd_gf1_look8(snd_gus_card_t * gus, unsigned char reg); -extern inline unsigned char snd_gf1_read8(snd_gus_card_t * gus, unsigned char reg) +static inline unsigned char snd_gf1_read8(snd_gus_card_t * gus, unsigned char reg) { return snd_gf1_look8(gus, reg | 0x80); } extern void snd_gf1_write16(snd_gus_card_t * gus, unsigned char reg, unsigned int data); extern unsigned short snd_gf1_look16(snd_gus_card_t * gus, unsigned char reg); -extern inline unsigned short snd_gf1_read16(snd_gus_card_t * gus, unsigned char reg) +static inline unsigned short snd_gf1_read16(snd_gus_card_t * gus, unsigned char reg) { return snd_gf1_look16(gus, reg | 0x80); } @@ -532,12 +532,12 @@ extern void snd_gf1_i_ctrl_stop(snd_gus_card_t * gus, unsigned char reg); extern void snd_gf1_i_write8(snd_gus_card_t * gus, unsigned char reg, unsigned char data); extern unsigned char snd_gf1_i_look8(snd_gus_card_t * gus, unsigned char reg); extern void snd_gf1_i_write16(snd_gus_card_t * gus, unsigned char reg, unsigned int data); -extern inline unsigned char snd_gf1_i_read8(snd_gus_card_t * gus, unsigned char reg) +static inline unsigned char snd_gf1_i_read8(snd_gus_card_t * gus, unsigned char reg) { return snd_gf1_i_look8(gus, reg | 0x80); } extern unsigned short snd_gf1_i_look16(snd_gus_card_t * gus, unsigned char reg); -extern inline unsigned short snd_gf1_i_read16(snd_gus_card_t * gus, unsigned char reg) +static inline unsigned short snd_gf1_i_read16(snd_gus_card_t * gus, unsigned char reg) { return snd_gf1_i_look16(gus, reg | 0x80); } diff --git a/include/sound/pcm.h b/include/sound/pcm.h index d935417575b5..fa23ebfb857a 100644 --- a/include/sound/pcm.h +++ b/include/sound/pcm.h @@ -379,7 +379,6 @@ struct _snd_pcm_substream { unsigned int dma_buf_id; size_t dma_max; /* -- hardware operations -- */ - unsigned int open_flag: 1; /* lowlevel device has been opened */ snd_pcm_ops_t *ops; /* -- runtime information -- */ snd_pcm_runtime_t *runtime; diff --git a/include/sound/version.h b/include/sound/version.h index 46acfa8c9988..8d19bfabb7e0 100644 --- a/include/sound/version.h +++ b/include/sound/version.h @@ -1,3 +1,3 @@ /* include/version.h. Generated by configure. */ -#define CONFIG_SND_VERSION "1.0.9" -#define CONFIG_SND_DATE " (Sun May 29 07:31:02 2005 UTC)" +#define CONFIG_SND_VERSION "1.0.10rc1" +#define CONFIG_SND_DATE " (Tue Aug 30 05:31:08 2005 UTC)" diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h index a7e29933f2d0..7a60a3888667 100644 --- a/include/sound/vx_core.h +++ b/include/sound/vx_core.h @@ -233,37 +233,37 @@ irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs); /* * lowlevel functions */ -inline static int vx_test_and_ack(vx_core_t *chip) +static inline int vx_test_and_ack(vx_core_t *chip) { snd_assert(chip->ops->test_and_ack, return -ENXIO); return chip->ops->test_and_ack(chip); } -inline static void vx_validate_irq(vx_core_t *chip, int enable) +static inline void vx_validate_irq(vx_core_t *chip, int enable) { snd_assert(chip->ops->validate_irq, return); chip->ops->validate_irq(chip, enable); } -inline static unsigned char snd_vx_inb(vx_core_t *chip, int reg) +static inline unsigned char snd_vx_inb(vx_core_t *chip, int reg) { snd_assert(chip->ops->in8, return 0); return chip->ops->in8(chip, reg); } -inline static unsigned int snd_vx_inl(vx_core_t *chip, int reg) +static inline unsigned int snd_vx_inl(vx_core_t *chip, int reg) { snd_assert(chip->ops->in32, return 0); return chip->ops->in32(chip, reg); } -inline static void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val) +static inline void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val) { snd_assert(chip->ops->out8, return); chip->ops->out8(chip, reg, val); } -inline static void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val) +static inline void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val) { snd_assert(chip->ops->out32, return); chip->ops->out32(chip, reg, val); @@ -303,14 +303,14 @@ int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time); /* * pseudo-DMA transfer */ -inline static void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime, +static inline void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime, vx_pipe_t *pipe, int count) { snd_assert(chip->ops->dma_write, return); chip->ops->dma_write(chip, runtime, pipe, count); } -inline static void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime, +static inline void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime, vx_pipe_t *pipe, int count) { snd_assert(chip->ops->dma_read, return); diff --git a/include/sound/ymfpci.h b/include/sound/ymfpci.h index 4b570684a6aa..9a3c1e6c820a 100644 --- a/include/sound/ymfpci.h +++ b/include/sound/ymfpci.h @@ -295,6 +295,7 @@ struct _snd_ymfpci_pcm { unsigned int running: 1; unsigned int output_front: 1; unsigned int output_rear: 1; + unsigned int update_pcm_vol; u32 period_size; /* cached from runtime->period_size */ u32 buffer_size; /* cached from runtime->buffer_size */ u32 period_pos; @@ -367,6 +368,11 @@ struct _snd_ymfpci { int mode_dup4ch; int rear_opened; int spdif_opened; + struct { + u16 left; + u16 right; + snd_kcontrol_t *ctl; + } pcm_mixer[32]; spinlock_t reg_lock; spinlock_t voice_lock; diff --git a/include/video/pmag-ba-fb.h b/include/video/pmag-ba-fb.h index cebef073b9a3..fceb6c0f6583 100644 --- a/include/video/pmag-ba-fb.h +++ b/include/video/pmag-ba-fb.h @@ -1,24 +1,27 @@ /* - * linux/drivers/video/pmag-ba-fb.h + * linux/include/video/pmag-ba-fb.h * - * TurboChannel PMAG-BA framebuffer card support, - * Copyright (C) 1999,2000,2001 by - * Michael Engel <engel@unix-ag.org>, - * Karsten Merker <merker@linuxtag.org> - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - */ - -/* - * Bt459 RAM DAC register base offset (rel. to TC slot base address) + * TURBOchannel PMAG-BA Color Frame Buffer (CFB) card support, + * Copyright (C) 1999, 2000, 2001 by + * Michael Engel <engel@unix-ag.org>, + * Karsten Merker <merker@linuxtag.org> + * Copyright (c) 2005 Maciej W. Rozycki + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. */ -#define PMAG_BA_BT459_OFFSET 0x00200000 - -/* - * Begin of PMAG-BA framebuffer memory relative to TC slot address, - * resolution is 1024x864x8 - */ +/* IOmem resource offsets. */ +#define PMAG_BA_FBMEM 0x000000 /* frame buffer */ +#define PMAG_BA_BT459 0x200000 /* Bt459 RAMDAC */ +#define PMAG_BA_IRQ 0x300000 /* IRQ acknowledge */ +#define PMAG_BA_ROM 0x380000 /* REX option ROM */ +#define PMAG_BA_BT438 0x380000 /* Bt438 clock chip reset */ +#define PMAG_BA_SIZE 0x400000 /* address space size */ -#define PMAG_BA_ONBOARD_FBMEM_OFFSET 0x00000000 +/* Bt459 register offsets, byte-wide registers. */ +#define BT459_ADDR_LO 0x0 /* address low */ +#define BT459_ADDR_HI 0x4 /* address high */ +#define BT459_DATA 0x8 /* data window register */ +#define BT459_CMAP 0xc /* color map window register */ diff --git a/include/video/pmagb-b-fb.h b/include/video/pmagb-b-fb.h index 87b81a555139..7539b9087a80 100644 --- a/include/video/pmagb-b-fb.h +++ b/include/video/pmagb-b-fb.h @@ -1,32 +1,58 @@ /* - * linux/drivers/video/pmagb-b-fb.h + * linux/include/video/pmagb-b-fb.h * - * TurboChannel PMAGB-B framebuffer card support, - * Copyright (C) 1999, 2000, 2001 by - * Michael Engel <engel@unix-ag.org> and - * Karsten Merker <merker@linuxtag.org> - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. + * TURBOchannel PMAGB-B Smart Frame Buffer (SFB) card support, + * Copyright (C) 1999, 2000, 2001 by + * Michael Engel <engel@unix-ag.org> and + * Karsten Merker <merker@linuxtag.org> + * Copyright (c) 2005 Maciej W. Rozycki + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. */ +/* IOmem resource offsets. */ +#define PMAGB_B_ROM 0x000000 /* REX option ROM */ +#define PMAGB_B_SFB 0x100000 /* SFB ASIC */ +#define PMAGB_B_GP0 0x140000 /* general purpose output 0 */ +#define PMAGB_B_GP1 0x180000 /* general purpose output 1 */ +#define PMAGB_B_BT459 0x1c0000 /* Bt459 RAMDAC */ +#define PMAGB_B_FBMEM 0x200000 /* frame buffer */ +#define PMAGB_B_SIZE 0x400000 /* address space size */ -/* - * Bt459 RAM DAC register base offset (rel. to TC slot base address) - */ -#define PMAGB_B_BT459_OFFSET 0x001C0000 +/* IOmem register offsets. */ +#define SFB_REG_VID_HOR 0x64 /* video horizontal setup */ +#define SFB_REG_VID_VER 0x68 /* video vertical setup */ +#define SFB_REG_VID_BASE 0x6c /* video base address */ +#define SFB_REG_TCCLK_COUNT 0x78 /* TURBOchannel clock count */ +#define SFB_REG_VIDCLK_COUNT 0x7c /* video clock count */ -/* - * Begin of PMAGB-B framebuffer memory, resolution is configurable: - * 1024x864x8 or 1280x1024x8, settable by jumper on the card - */ -#define PMAGB_B_ONBOARD_FBMEM_OFFSET 0x00201000 +/* Video horizontal setup register constants. All bits are r/w. */ +#define SFB_VID_HOR_BP_SHIFT 0x15 /* back porch */ +#define SFB_VID_HOR_BP_MASK 0x7f +#define SFB_VID_HOR_SYN_SHIFT 0x0e /* sync pulse */ +#define SFB_VID_HOR_SYN_MASK 0x7f +#define SFB_VID_HOR_FP_SHIFT 0x09 /* front porch */ +#define SFB_VID_HOR_FP_MASK 0x1f +#define SFB_VID_HOR_PIX_SHIFT 0x00 /* active video */ +#define SFB_VID_HOR_PIX_MASK 0x1ff -/* - * Bt459 register offsets, byte-wide registers - */ +/* Video vertical setup register constants. All bits are r/w. */ +#define SFB_VID_VER_BP_SHIFT 0x16 /* back porch */ +#define SFB_VID_VER_BP_MASK 0x3f +#define SFB_VID_VER_SYN_SHIFT 0x10 /* sync pulse */ +#define SFB_VID_VER_SYN_MASK 0x3f +#define SFB_VID_VER_FP_SHIFT 0x0b /* front porch */ +#define SFB_VID_VER_FP_MASK 0x1f +#define SFB_VID_VER_SL_SHIFT 0x00 /* active scan lines */ +#define SFB_VID_VER_SL_MASK 0x7ff + +/* Video base address register constants. All bits are r/w. */ +#define SFB_VID_BASE_MASK 0x1ff /* video base row address */ -#define BT459_ADR_LOW BT459_OFFSET + 0x00 /* addr. low */ -#define BT459_ADR_HIGH BT459_OFFSET + 0x04 /* addr. high */ -#define BT459_DATA BT459_OFFSET + 0x08 /* r/w data */ -#define BT459_CMAP BT459_OFFSET + 0x0C /* color map */ +/* Bt459 register offsets, byte-wide registers. */ +#define BT459_ADDR_LO 0x0 /* address low */ +#define BT459_ADDR_HI 0x4 /* address high */ +#define BT459_DATA 0x8 /* data window register */ +#define BT459_CMAP 0xc /* color map window register */ |