diff options
Diffstat (limited to 'include')
191 files changed, 24170 insertions, 77 deletions
diff --git a/include/crypto/drbg.h b/include/crypto/drbg.h index 22f884c97387..8f941102af36 100644 --- a/include/crypto/drbg.h +++ b/include/crypto/drbg.h @@ -126,8 +126,7 @@ struct drbg_state { __u8 *ctr_null_value; /* CTR mode aligned zero buf */ __u8 *outscratchpadbuf; /* CTR mode output scratchpad */ __u8 *outscratchpad; /* CTR mode aligned outbuf */ - struct completion ctr_completion; /* CTR mode async handler */ - int ctr_async_err; /* CTR mode async error */ + struct crypto_wait ctr_wait; /* CTR mode async wait obj */ bool seeded; /* DRBG fully seeded? */ bool pr; /* Prediction resistance enabled? */ diff --git a/include/crypto/if_alg.h b/include/crypto/if_alg.h index ac0eae8372ab..f38227a78eae 100644 --- a/include/crypto/if_alg.h +++ b/include/crypto/if_alg.h @@ -41,11 +41,6 @@ struct alg_sock { void *private; }; -struct af_alg_completion { - struct completion completion; - int err; -}; - struct af_alg_control { struct af_alg_iv *iv; int op; @@ -153,7 +148,7 @@ struct af_alg_ctx { void *iv; size_t aead_assoclen; - struct af_alg_completion completion; + struct crypto_wait wait; size_t used; atomic_t rcvused; @@ -178,19 +173,11 @@ void af_alg_link_sg(struct af_alg_sgl *sgl_prev, struct af_alg_sgl *sgl_new); int af_alg_cmsg_send(struct msghdr *msg, struct af_alg_control *con); -int af_alg_wait_for_completion(int err, struct af_alg_completion *completion); -void af_alg_complete(struct crypto_async_request *req, int err); - static inline struct alg_sock *alg_sk(struct sock *sk) { return (struct alg_sock *)sk; } -static inline void af_alg_init_completion(struct af_alg_completion *completion) -{ - init_completion(&completion->completion); -} - /** * Size of available buffer for sending data from user space to kernel. * diff --git a/include/drm/bridge/nwl_dsi.h b/include/drm/bridge/nwl_dsi.h new file mode 100644 index 000000000000..df5f25b18fdb --- /dev/null +++ b/include/drm/bridge/nwl_dsi.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __NWL_DSI__ +#define __NWL_DSI__ + +#include <drm/drmP.h> +#include <drm/drm_mipi_dsi.h> +#include <linux/phy/phy.h> + +/* + * RGB bit distribution within the 24-bit data bus, + * as specified by the DPI specification + */ +enum dpi_interface_color_coding { + DPI_16_BIT_565_PACKED, /* 0x0 cfg1 */ + DPI_16_BIT_565_ALIGNED, /* 0x1 cfg 2 */ + DPI_16_BIT_565_SHIFTED, /* 0x2 cfg 3 */ + DPI_18_BIT_PACKED, /* 0x3 cfg1 */ + DPI_18_BIT_ALIGNED, /* 0x4* cfg2 */ + DPI_24_BIT /* 0x5 */ +}; + +/* DSI packet type of pixels, as specified by the DPI specification */ +enum dpi_pixel_format { + DPI_FMT_16_BIT, /* 0x0 */ + DPI_FMT_18_BIT, /* 0x1 */ + DPI_FMT_18_BIT_LOOSELY_PACKED, /* 0x2 */ + DPI_FMT_24_BIT /* 0x3 */ +}; + +#endif /* __NWL_DSI_H__ */ diff --git a/include/drm/bridge/sec_mipi_dsim.h b/include/drm/bridge/sec_mipi_dsim.h new file mode 100644 index 000000000000..2f9233563ee6 --- /dev/null +++ b/include/drm/bridge/sec_mipi_dsim.h @@ -0,0 +1,112 @@ +/* + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SEC_MIPI_DSIM_H__ +#define __SEC_MIPI_DSIM_H__ + +#include <drm/drmP.h> +#include <linux/bsearch.h> + +struct sec_mipi_dsim_dphy_timing; +struct sec_mipi_dsim_pll; + +struct sec_mipi_dsim_plat_data { + uint32_t version; + uint32_t max_data_lanes; + uint64_t max_data_rate; + const struct sec_mipi_dsim_dphy_timing *dphy_timing; + uint32_t num_dphy_timing; + const struct sec_mipi_dsim_pll *dphy_pll; + int (*dphy_timing_cmp)(const void *key, const void *elt); + enum drm_mode_status (*mode_valid)(struct drm_connector *connector, + struct drm_display_mode *mode); +}; + +/* DPHY PLL structure */ +struct sec_mipi_dsim_range { + uint32_t min; + uint32_t max; +}; + +struct sec_mipi_dsim_pll { + struct sec_mipi_dsim_range p; + struct sec_mipi_dsim_range m; + struct sec_mipi_dsim_range s; + struct sec_mipi_dsim_range k; + struct sec_mipi_dsim_range fin; + struct sec_mipi_dsim_range fpref; + struct sec_mipi_dsim_range fvco; +}; + +/* DPHY timings structure */ +struct sec_mipi_dsim_dphy_timing { + uint32_t bit_clk; /* MHz */ + + uint32_t clk_prepare; + uint32_t clk_zero; + uint32_t clk_post; + uint32_t clk_trail; + + uint32_t hs_prepare; + uint32_t hs_zero; + uint32_t hs_trail; + + uint32_t lpx; + uint32_t hs_exit; +}; + +#define DSIM_DPHY_TIMING(bclk, cpre, czero, cpost, ctrail, \ + hpre, hzero, htrail, lp, hexit) \ + .bit_clk = bclk, \ + .clk_prepare = cpre, \ + .clk_zero = czero, \ + .clk_post = cpost, \ + .clk_trail = ctrail, \ + .hs_prepare = hpre, \ + .hs_zero = hzero, \ + .hs_trail = htrail, \ + .lpx = lp, \ + .hs_exit = hexit + +static inline int dphy_timing_default_cmp(const void *key, const void *elt) +{ + const struct sec_mipi_dsim_dphy_timing *_key = key; + const struct sec_mipi_dsim_dphy_timing *_elt = elt; + + /* find an element whose 'bit_clk' is equal to the + * the key's 'bit_clk' value or, the difference + * between them is less than 5. + */ + if (abs((int)(_elt->bit_clk - _key->bit_clk)) <= 5) + return 0; + + if (_key->bit_clk < _elt->bit_clk) + /* search bottom half */ + return 1; + else + /* search top half */ + return -1; +} + +int sec_mipi_dsim_check_pll_out(void *driver_private, + const struct drm_display_mode *mode); +int sec_mipi_dsim_bind(struct device *dev, struct device *master, void *data, + struct drm_encoder *encoder, struct resource *res, + int irq, const struct sec_mipi_dsim_plat_data *pdata); +void sec_mipi_dsim_unbind(struct device *dev, struct device *master, void *data); + +void sec_mipi_dsim_suspend(struct device *dev); +void sec_mipi_dsim_resume(struct device *dev); + +#endif diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 7277783a4ff0..59be1232d005 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -136,6 +136,7 @@ struct pci_controller; #define DRM_UT_ATOMIC 0x10 #define DRM_UT_VBL 0x20 #define DRM_UT_STATE 0x40 +#define DRM_UT_LEASE 0x80 /***********************************************************************/ /** \name DRM template customization defaults */ @@ -250,6 +251,9 @@ struct pci_controller; #define DRM_DEBUG_VBL(fmt, ...) \ drm_printk(KERN_DEBUG, DRM_UT_VBL, fmt, ##__VA_ARGS__) +#define DRM_DEBUG_LEASE(fmt, ...) \ + drm_printk(KERN_DEBUG, DRM_UT_LEASE, fmt, ##__VA_ARGS__) + #define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, level, fmt, args...) \ ({ \ static DEFINE_RATELIMIT_STATE(_rs, \ diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h index d2b56cc657e9..f82529ca23b0 100644 --- a/include/drm/drm_atomic_helper.h +++ b/include/drm/drm_atomic_helper.h @@ -149,6 +149,8 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state); void drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state); +void __drm_atomic_helper_plane_reset(struct drm_plane *plane, + struct drm_plane_state *state); void drm_atomic_helper_plane_reset(struct drm_plane *plane); void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, struct drm_plane_state *state); diff --git a/include/drm/drm_auth.h b/include/drm/drm_auth.h index 81a40c2a9a3e..86bff9841b54 100644 --- a/include/drm/drm_auth.h +++ b/include/drm/drm_auth.h @@ -52,6 +52,12 @@ struct drm_lock_data { * @dev: Link back to the DRM device * @lock: DRI1 lock information. * @driver_priv: Pointer to driver-private information. + * @lessor: Lease holder + * @lessee_id: id for lessees. Owners always have id 0 + * @lessee_list: other lessees of the same master + * @lessees: drm_masters leasing from this one + * @leases: Objects leased to this drm_master. + * @lessee_idr: All lessees under this owner (only used where lessor == NULL) * * Note that master structures are only relevant for the legacy/primary device * nodes, hence there can only be one per device, not one per drm_minor. @@ -76,10 +82,25 @@ struct drm_master { struct idr magic_map; struct drm_lock_data lock; void *driver_priv; + + /* Tree of display resource leases, each of which is a drm_master struct + * All of these get activated simultaneously, so drm_device master points + * at the top of the tree (for which lessor is NULL). Protected by + * &drm_device.mode_config.idr_mutex. + */ + + struct drm_master *lessor; + int lessee_id; + struct list_head lessee_list; + struct list_head lessees; + struct idr leases; + struct idr lessee_idr; }; struct drm_master *drm_master_get(struct drm_master *master); void drm_master_put(struct drm_master **master); bool drm_is_current_master(struct drm_file *fpriv); +struct drm_master *drm_master_create(struct drm_device *dev); + #endif diff --git a/include/drm/drm_blend.h b/include/drm/drm_blend.h index 17606026590b..88bdfec3bd88 100644 --- a/include/drm/drm_blend.h +++ b/include/drm/drm_blend.h @@ -27,6 +27,10 @@ #include <linux/ctype.h> #include <drm/drm_mode.h> +#define DRM_MODE_BLEND_PREMULTI 0 +#define DRM_MODE_BLEND_COVERAGE 1 +#define DRM_MODE_BLEND_PIXEL_NONE 2 + struct drm_device; struct drm_atomic_state; struct drm_plane; @@ -36,6 +40,9 @@ static inline bool drm_rotation_90_or_270(unsigned int rotation) return rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270); } +#define DRM_BLEND_ALPHA_OPAQUE 0xffff + +int drm_plane_create_alpha_property(struct drm_plane *plane); int drm_plane_create_rotation_property(struct drm_plane *plane, unsigned int rotation, unsigned int supported_rotations); @@ -49,4 +56,6 @@ int drm_plane_create_zpos_immutable_property(struct drm_plane *plane, unsigned int zpos); int drm_atomic_normalize_zpos(struct drm_device *dev, struct drm_atomic_state *state); +int drm_plane_create_blend_mode_property(struct drm_plane *plane, + unsigned int supported_modes); #endif diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 03a59cbce621..b3b6d302ca8c 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -26,6 +26,7 @@ #include <linux/ctype.h> struct drm_crtc; +struct drm_plane; uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); @@ -37,4 +38,22 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, int gamma_size); +enum drm_color_encoding { + DRM_COLOR_YCBCR_BT601, + DRM_COLOR_YCBCR_BT709, + DRM_COLOR_YCBCR_BT2020, + DRM_COLOR_ENCODING_MAX, +}; + +enum drm_color_range { + DRM_COLOR_YCBCR_LIMITED_RANGE, + DRM_COLOR_YCBCR_FULL_RANGE, + DRM_COLOR_RANGE_MAX, +}; + +int drm_plane_create_color_properties(struct drm_plane *plane, + u32 supported_encodings, + u32 supported_ranges, + enum drm_color_encoding default_encoding, + enum drm_color_range default_range); #endif diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index ea8da401c93c..e9e6fb0ba56d 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -157,6 +157,11 @@ struct drm_hdmi_info { /** @y420_dc_modes: bitmap of deep color support index */ u8 y420_dc_modes; + + /* Colorimerty info from EDID */ + u32 colorimetry; + /* Panel HDR capabilities */ + struct hdr_static_metadata hdr_panel_metadata; }; /** @@ -281,6 +286,11 @@ struct drm_display_info { u8 cea_rev; /** + * @non_desktop: Non desktop display (HMD) + */ + bool non_desktop; + + /** * @hdmi: advance features of a HDMI sink. */ struct drm_hdmi_info hdmi; @@ -359,10 +369,30 @@ struct drm_connector_state { enum hdmi_picture_aspect picture_aspect_ratio; /** + * @content_type: Connector property to control the + * HDMI infoframe content type setting. + * The %DRM_MODE_CONTENT_TYPE_\* values much + * match the values. + */ + unsigned int content_type; + + /** * @scaling_mode: Connector property to control the * upscaling, mostly used for built-in panels. */ unsigned int scaling_mode; + + /** + * @metadata_blob_ptr: + * DRM blob property for HDR metadata + */ + struct drm_property_blob *hdr_source_metadata_blob_ptr; + bool hdr_metadata_changed : 1; + /** + * @content_protection: Connector property to request content + * protection. This is most commonly used for HDCP. + */ + unsigned int content_protection; }; /** @@ -711,6 +741,7 @@ struct drm_cmdline_mode { * @tile_h_size: horizontal size of this tile. * @tile_v_size: vertical size of this tile. * @scaling_mode_property: Optional atomic property to control the upscaling. + * @content_protection_property: Optional property to control content protection * * Each connector may be connected to one or more CRTCs, or may be clonable by * another connector if they can share a CRTC. Each connector also has a specific @@ -802,6 +833,12 @@ struct drm_connector { struct drm_property *scaling_mode_property; /** + * @content_protection_property: DRM ENUM property for content + * protection + */ + struct drm_property *content_protection_property; + + /** * @path_blob_ptr: * * DRM blob property data for the DP MST path property. @@ -905,6 +942,9 @@ struct drm_connector { uint8_t num_h_tile, num_v_tile; uint8_t tile_h_loc, tile_v_loc; uint16_t tile_h_size, tile_v_size; + + /* HDR metdata */ + struct hdr_static_metadata *hdr_source_metadata; }; #define obj_to_connector(x) container_of(x, struct drm_connector, base) @@ -933,10 +973,11 @@ static inline unsigned drm_connector_index(struct drm_connector *connector) * add takes a reference to it. */ static inline struct drm_connector *drm_connector_lookup(struct drm_device *dev, + struct drm_file *file_priv, uint32_t id) { struct drm_mode_object *mo; - mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CONNECTOR); + mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_CONNECTOR); return mo ? obj_to_connector(mo) : NULL; } @@ -994,15 +1035,23 @@ const char *drm_get_dvi_i_subconnector_name(int val); const char *drm_get_dvi_i_select_name(int val); const char *drm_get_tv_subconnector_name(int val); const char *drm_get_tv_select_name(int val); +const char *drm_get_content_protection_name(int val); int drm_mode_create_dvi_i_properties(struct drm_device *dev); int drm_mode_create_tv_properties(struct drm_device *dev, unsigned int num_modes, const char * const modes[]); int drm_mode_create_scaling_mode_property(struct drm_device *dev); +int drm_connector_attach_content_type_property(struct drm_connector *dev); int drm_connector_attach_scaling_mode_property(struct drm_connector *connector, u32 scaling_mode_mask); +int drm_connector_attach_content_protection_property( + struct drm_connector *connector); int drm_mode_create_aspect_ratio_property(struct drm_device *dev); +int drm_mode_create_content_type_property(struct drm_device *dev); +void drm_hdmi_avi_infoframe_content_type(struct hdmi_avi_infoframe *frame, + const struct drm_connector_state *conn_state); + int drm_mode_create_suggested_offset_properties(struct drm_device *dev); int drm_mode_connector_set_path_property(struct drm_connector *connector, diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 1a642020e306..1577e32da695 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -944,10 +944,11 @@ struct drm_crtc *drm_crtc_from_index(struct drm_device *dev, int idx); * userspace interface should be done using &drm_property. */ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, - uint32_t id) + struct drm_file *file_priv, + uint32_t id) { struct drm_mode_object *mo; - mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CRTC); + mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_CRTC); return mo ? obj_to_crtc(mo) : NULL; } diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h index e21af87a2f3c..7c4fa32f3fc6 100644 --- a/include/drm/drm_device.h +++ b/include/drm/drm_device.h @@ -17,6 +17,7 @@ struct drm_vblank_crtc; struct drm_sg_mem; struct drm_local_map; struct drm_vma_offset_manager; +struct drm_fb_helper; struct inode; @@ -185,6 +186,14 @@ struct drm_device { struct drm_vma_offset_manager *vma_offset_manager; /*@} */ int switch_power_state; + + /** + * @fb_helper: + * + * Pointer to the fbdev emulation structure. + * Set by drm_fb_helper_init() and cleared by drm_fb_helper_fini(). + */ + struct drm_fb_helper *fb_helper; }; #endif diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8fd7cb5297ab..8508b8dbf9aa 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -805,6 +805,74 @@ #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +# define DP_BCAPS_REPEATER_PRESENT BIT(1) +# define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS 0x68029 +# define DP_BSTATUS_REAUTH_REQ BIT(3) +# define DP_BSTATUS_LINK_FAILURE BIT(2) +# define DP_BSTATUS_R0_PRIME_READY BIT(1) +# define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + +/* DP HDCP2.2 parameter offsets in DPCD address space */ +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 +#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + +/* DP HDCP message start offsets in DPCD address space */ +#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET +#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ + DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET +#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET + +#define HDCP_2_2_DP_RXSTATUS_LEN 1 +#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) +#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) +#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) + /* DP 1.2 Sideband message defines */ /* peer device type - DP 1.2a Table 2-92 */ #define DP_PEER_DEVICE_NONE 0x0 diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 267e0426c479..6f1410b113fc 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -372,6 +372,10 @@ static inline int drm_eld_mnl(const uint8_t *eld) return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; } +int +drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, + void *hdr_source_metadata); + /** * drm_eld_sad - Get ELD SAD structures. * @eld: pointer to an eld memory structure with sad_count set diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h index 8d8245ec0181..86db0da8bdcb 100644 --- a/include/drm/drm_encoder.h +++ b/include/drm/drm_encoder.h @@ -214,11 +214,12 @@ static inline bool drm_encoder_crtc_ok(struct drm_encoder *encoder, * drm_mode_object_find(). */ static inline struct drm_encoder *drm_encoder_find(struct drm_device *dev, + struct drm_file *file_priv, uint32_t id) { struct drm_mode_object *mo; - mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_ENCODER); + mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_ENCODER); return mo ? obj_to_encoder(mo) : NULL; } diff --git a/include/drm/drm_framebuffer.h b/include/drm/drm_framebuffer.h index b6996ddb19d6..4c5ee4ae54df 100644 --- a/include/drm/drm_framebuffer.h +++ b/include/drm/drm_framebuffer.h @@ -205,6 +205,7 @@ int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb, const struct drm_framebuffer_funcs *funcs); struct drm_framebuffer *drm_framebuffer_lookup(struct drm_device *dev, + struct drm_file *file_priv, uint32_t id); void drm_framebuffer_remove(struct drm_framebuffer *fb); void drm_framebuffer_cleanup(struct drm_framebuffer *fb); diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h new file mode 100644 index 000000000000..a6de09c5e47f --- /dev/null +++ b/include/drm/drm_hdcp.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2017 Google, Inc. + * + * Authors: + * Sean Paul <seanpaul@chromium.org> + */ + +#ifndef _DRM_HDCP_H_INCLUDED_ +#define _DRM_HDCP_H_INCLUDED_ + +/* Period of hdcp checks (to ensure we're still authenticated) */ +#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) + +/* Shared lengths/masks between HDMI/DVI/DisplayPort */ +#define DRM_HDCP_AN_LEN 8 +#define DRM_HDCP_BSTATUS_LEN 2 +#define DRM_HDCP_KSV_LEN 5 +#define DRM_HDCP_RI_LEN 2 +#define DRM_HDCP_V_PRIME_PART_LEN 4 +#define DRM_HDCP_V_PRIME_NUM_PARTS 5 +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f) +#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3)) +#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7)) + +/* Slave address for the HDCP registers in the receiver */ +#define DRM_HDCP_DDC_ADDR 0x3A + +/* HDCP register offsets for HDMI/DVI devices */ +#define DRM_HDCP_DDC_BKSV 0x00 +#define DRM_HDCP_DDC_RI_PRIME 0x08 +#define DRM_HDCP_DDC_AKSV 0x10 +#define DRM_HDCP_DDC_AN 0x18 +#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4) +#define DRM_HDCP_DDC_BCAPS 0x40 +#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) +#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) +#define DRM_HDCP_DDC_BSTATUS 0x41 +#define DRM_HDCP_DDC_KSV_FIFO 0x43 + +#define DRM_HDCP_1_4_SRM_ID 0x8 +#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 +#define DRM_HDCP_1_4_DCP_SIG_SIZE 40 + +/* Protocol message definition for HDCP2.2 specification */ +/* + * Protected content streams are classified into 2 types: + * - Type0: Can be transmitted with HDCP 1.4+ + * - Type1: Can be transmitted with HDCP 2.2+ + */ +#define HDCP_STREAM_TYPE0 0x00 +#define HDCP_STREAM_TYPE1 0x01 + +/* HDCP2.2 Msg IDs */ +#define HDCP_2_2_NULL_MSG 1 +#define HDCP_2_2_AKE_INIT 2 +#define HDCP_2_2_AKE_SEND_CERT 3 +#define HDCP_2_2_AKE_NO_STORED_KM 4 +#define HDCP_2_2_AKE_STORED_KM 5 +#define HDCP_2_2_AKE_SEND_HPRIME 7 +#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8 +#define HDCP_2_2_LC_INIT 9 +#define HDCP_2_2_LC_SEND_LPRIME 10 +#define HDCP_2_2_SKE_SEND_EKS 11 +#define HDCP_2_2_REP_SEND_RECVID_LIST 12 +#define HDCP_2_2_REP_SEND_ACK 15 +#define HDCP_2_2_REP_STREAM_MANAGE 16 +#define HDCP_2_2_REP_STREAM_READY 17 +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 + +#define HDCP_2_2_RTX_LEN 8 +#define HDCP_2_2_RRX_LEN 8 + +#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128 +#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3 +#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \ + HDCP_2_2_K_PUB_RX_EXP_E_LEN) + +#define HDCP_2_2_DCP_LLC_SIG_LEN 384 + +#define HDCP_2_2_E_KPUB_KM_LEN 128 +#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16) +#define HDCP_2_2_H_PRIME_LEN 32 +#define HDCP_2_2_E_KH_KM_LEN 16 +#define HDCP_2_2_RN_LEN 8 +#define HDCP_2_2_L_PRIME_LEN 32 +#define HDCP_2_2_E_DKEY_KS_LEN 16 +#define HDCP_2_2_RIV_LEN 8 +#define HDCP_2_2_SEQ_NUM_LEN 3 +#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2) +#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN +#define HDCP_2_2_MAX_DEVICE_COUNT 31 +#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \ + HDCP_2_2_MAX_DEVICE_COUNT) +#define HDCP_2_2_MPRIME_LEN 32 + +/* Following Macros take a byte at a time for bit(s) masking */ +/* + * TODO: This has to be changed for DP MST, as multiple stream on + * same port is possible. + * For HDCP2.2 on HDMI and DP SST this value is always 1. + */ +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_TXCAP_MASK_LEN 2 +#define HDCP_2_2_RXCAPS_LEN 3 +#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) +#define HDCP_2_2_RXINFO_LEN 2 + +/* HDCP1.x compliant device in downstream */ +#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) + +/* HDCP2.0 Compliant repeater in downstream */ +#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) +#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) +#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) +#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4) +#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) +#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1) + +struct hdcp2_cert_rx { + u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN]; + u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN]; + u8 reserved[2]; + u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN]; +} __packed; + +struct hdcp2_streamid_type { + u8 stream_id; + u8 stream_type; +} __packed; + +/* + * The TxCaps field specified in the HDCP HDMI, DP specs + * This field is big endian as specified in the errata. + */ +struct hdcp2_tx_caps { + /* Transmitter must set this to 0x2 */ + u8 version; + + /* Reserved for HDCP and DP Spec. Read as Zero */ + u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN]; +} __packed; + +/* Main structures for HDCP2.2 protocol communication */ +struct hdcp2_ake_init { + u8 msg_id; + u8 r_tx[HDCP_2_2_RTX_LEN]; + struct hdcp2_tx_caps tx_caps; +} __packed; + +struct hdcp2_ake_send_cert { + u8 msg_id; + struct hdcp2_cert_rx cert_rx; + u8 r_rx[HDCP_2_2_RRX_LEN]; + u8 rx_caps[HDCP_2_2_RXCAPS_LEN]; +} __packed; + +struct hdcp2_ake_no_stored_km { + u8 msg_id; + u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; +} __packed; + +struct hdcp2_ake_stored_km { + u8 msg_id; + u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; +} __packed; + +struct hdcp2_ake_send_hprime { + u8 msg_id; + u8 h_prime[HDCP_2_2_H_PRIME_LEN]; +} __packed; + +struct hdcp2_ake_send_pairing_info { + u8 msg_id; + u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN]; +} __packed; + +struct hdcp2_lc_init { + u8 msg_id; + u8 r_n[HDCP_2_2_RN_LEN]; +} __packed; + +struct hdcp2_lc_send_lprime { + u8 msg_id; + u8 l_prime[HDCP_2_2_L_PRIME_LEN]; +} __packed; + +struct hdcp2_ske_send_eks { + u8 msg_id; + u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN]; + u8 riv[HDCP_2_2_RIV_LEN]; +} __packed; + +struct hdcp2_rep_send_receiverid_list { + u8 msg_id; + u8 rx_info[HDCP_2_2_RXINFO_LEN]; + u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN]; + u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN]; + u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN]; +} __packed; + +struct hdcp2_rep_send_ack { + u8 msg_id; + u8 v[HDCP_2_2_V_PRIME_HALF_LEN]; +} __packed; + +struct hdcp2_rep_stream_manage { + u8 msg_id; + u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN]; + __be16 k; + struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT]; +} __packed; + +struct hdcp2_rep_stream_ready { + u8 msg_id; + u8 m_prime[HDCP_2_2_MPRIME_LEN]; +} __packed; + +struct hdcp2_dp_errata_stream_type { + u8 msg_id; + u8 stream_type; +} __packed; + +/* HDCP2.2 TIMEOUTs in mSec */ +#define HDCP_2_2_CERT_TIMEOUT_MS 100 +#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 +#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 +#define HDCP_2_2_PAIRING_TIMEOUT_MS 200 +#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 +#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 +#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 +#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 + +/* HDMI HDCP2.2 Register Offsets */ +#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 +#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 +#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 +#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 +#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 + +#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) +#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 +#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF +#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 + +/* Below macros take a byte at a time and mask the bit(s) */ +#define HDCP_2_2_HDMI_RXSTATUS_LEN 2 +#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) +#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) +#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) + +#endif diff --git a/include/drm/drm_lease.h b/include/drm/drm_lease.h new file mode 100644 index 000000000000..fbc0ab54855b --- /dev/null +++ b/include/drm/drm_lease.h @@ -0,0 +1,46 @@ +/* + * Copyright © 2017 Keith Packard <keithp@keithp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef _DRM_LEASE_H_ +#define _DRM_LEASE_H_ + +struct drm_file; +struct drm_device; +struct drm_master; + +struct drm_master *drm_lease_owner(struct drm_master *master); + +void drm_lease_destroy(struct drm_master *lessee); + +bool drm_lease_held(struct drm_file *file_priv, int id); + +bool _drm_lease_held(struct drm_file *file_priv, int id); + +void drm_lease_revoke(struct drm_master *master); + +uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs); + +int drm_mode_create_lease_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); + +int drm_mode_list_lessees_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); + +int drm_mode_get_lease_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); + +int drm_mode_revoke_lease_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); + +#endif /* _DRM_LEASE_H_ */ diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 1b37368416c8..bb037f6bee60 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -703,6 +703,11 @@ struct drm_mode_config { */ struct drm_property *aspect_ratio_property; /** + * @content_type_property: Optional connector property to control the + * HDMI infoframe content type setting. + */ + struct drm_property *content_type_property; + /** * @degamma_lut_property: Optional CRTC property to set the LUT used to * convert the framebuffer's colors to linear gamma. */ @@ -735,12 +740,26 @@ struct drm_mode_config { * the position of the output on the host's screen. */ struct drm_property *suggested_x_property; + + /** + * @non_desktop_property: Optional connector property with a hint + * that device isn't a standard display, and the console/desktop + * should not be displayed on it. + */ + struct drm_property *non_desktop_property; + /** * @suggested_y_property: Optional connector property with a hint for * the position of the output on the host's screen. */ struct drm_property *suggested_y_property; + /** + * hdr_metadata_property: Connector property containing hdr metatda + * This will be provided by userspace compositors based on HDR content + */ + struct drm_property *hdr_source_metadata_property; + /* dumb ioctl parameters */ uint32_t preferred_depth, prefer_shadow; @@ -766,6 +785,15 @@ struct drm_mode_config { /* cursor size */ uint32_t cursor_width, cursor_height; + /** + * @suspend_state: + * + * Atomic state when suspended. + * Set by drm_mode_config_helper_suspend() and cleared by + * drm_mode_config_helper_resume(). + */ + struct drm_atomic_state *suspend_state; + const struct drm_mode_config_helper_funcs *helper_private; }; diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h index a767b4a30a6d..7ba3913f30b5 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -24,9 +24,11 @@ #define __DRM_MODESET_H__ #include <linux/kref.h> +#include <drm/drm_lease.h> struct drm_object_properties; struct drm_property; struct drm_device; +struct drm_file; /** * struct drm_mode_object - base structure for modeset objects @@ -113,6 +115,7 @@ struct drm_object_properties { } struct drm_mode_object *drm_mode_object_find(struct drm_device *dev, + struct drm_file *file_priv, uint32_t id, uint32_t type); void drm_mode_object_get(struct drm_mode_object *obj); void drm_mode_object_put(struct drm_mode_object *obj); @@ -151,4 +154,6 @@ int drm_object_property_get_value(struct drm_mode_object *obj, void drm_object_attach_property(struct drm_mode_object *obj, struct drm_property *property, uint64_t init_val); + +bool drm_mode_object_lease_required(uint32_t type); #endif diff --git a/include/drm/drm_modeset_helper.h b/include/drm/drm_modeset_helper.h index cb0ec92e11e6..efa337f03129 100644 --- a/include/drm/drm_modeset_helper.h +++ b/include/drm/drm_modeset_helper.h @@ -34,4 +34,7 @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, int drm_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, const struct drm_crtc_funcs *funcs); +int drm_mode_config_helper_suspend(struct drm_device *dev); +int drm_mode_config_helper_resume(struct drm_device *dev); + #endif diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h index 4f835490d77a..c0bd3dff0191 100644 --- a/include/drm/drm_of.h +++ b/include/drm/drm_of.h @@ -4,6 +4,7 @@ #include <linux/of_graph.h> +struct component_match; struct component_master_ops; struct component_match; struct device; @@ -20,6 +21,10 @@ void drm_of_component_match_add(struct device *master, struct component_match **matchptr, int (*compare)(struct device *, void *), struct device_node *node); +extern int drm_of_component_probe_with_match(struct device *dev, + struct component_match *match, + int (*compare_of)(struct device *, void *), + const struct component_master_ops *m_ops); int drm_of_component_probe(struct device *dev, int (*compare_of)(struct device *, void *), const struct component_master_ops *m_ops); @@ -45,6 +50,14 @@ drm_of_component_match_add(struct device *master, { } +static int drm_of_component_probe_with_match(struct device *dev, + struct component_match *match, + int (*compare_of)(struct device *, void *), + const struct component_master_ops *m_ops) +{ + return -EINVAL; +} + static inline int drm_of_component_probe(struct device *dev, int (*compare_of)(struct device *, void *), diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 73f90f9d057f..878ae9996510 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -26,6 +26,7 @@ #include <linux/list.h> #include <linux/ctype.h> #include <drm/drm_mode_object.h> +#include <drm/drm_color_mgmt.h> struct drm_crtc; struct drm_printer; @@ -42,6 +43,7 @@ struct drm_modeset_acquire_ctx; * plane (in 16.16) * @src_w: width of visible portion of plane (in 16.16) * @src_h: height of visible portion of plane (in 16.16) + * @alpha: opacity of the plane * @rotation: rotation of the plane * @zpos: priority of the given plane on crtc (optional) * Note that multiple active planes on the same crtc can have an identical @@ -105,6 +107,10 @@ struct drm_plane_state { uint32_t src_x, src_y; uint32_t src_h, src_w; + /* Plane opacity */ + u16 alpha; + uint16_t pixel_blend_mode; + /* Plane rotation */ unsigned int rotation; @@ -112,6 +118,20 @@ struct drm_plane_state { unsigned int zpos; unsigned int normalized_zpos; + /** + * @color_encoding: + * + * Color encoding for non RGB formats + */ + enum drm_color_encoding color_encoding; + + /** + * @color_range: + * + * Color range for non RGB formats + */ + enum drm_color_range color_range; + /* Clipped coordinates */ struct drm_rect src, dst; @@ -473,6 +493,7 @@ enum drm_plane_type { * @funcs: helper functions * @properties: property tracking for this plane * @type: type of plane (overlay, primary, cursor) + * @alpha_property: alpha property for this plane * @zpos_property: zpos property for this plane * @rotation_property: rotation property for this plane * @helper_private: mid-layer private data @@ -515,6 +536,9 @@ struct drm_plane { enum drm_plane_type type; + /* Value of true:1 means HDR is supported */ + bool hdr_supported; + /** * @index: Position inside the mode_config.list, can be used as an array * index. It is invariant over the lifetime of the plane. @@ -538,8 +562,34 @@ struct drm_plane { */ struct drm_plane_state *state; + struct drm_property *alpha_property; struct drm_property *zpos_property; struct drm_property *rotation_property; + /** + * @blend_mode_property: + * Optional "pixel blend mode" enum property for this plane. + * Blend mode property represents the alpha blending equation selection, + * describing how the pixels from the current plane are composited with + * the background. + */ + struct drm_property *blend_mode_property; + + /** + * @color_encoding_property: + * + * Optional "COLOR_ENCODING" enum property for specifying + * color encoding for non RGB formats. + * See drm_plane_create_color_properties(). + */ + struct drm_property *color_encoding_property; + /** + * @color_range_property: + * + * Optional "COLOR_RANGE" enum property for specifying + * color range for non RGB formats. + * See drm_plane_create_color_properties(). + */ + struct drm_property *color_range_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -589,10 +639,11 @@ int drm_mode_plane_set_obj_prop(struct drm_plane *plane, * drm_mode_object_find(). */ static inline struct drm_plane *drm_plane_find(struct drm_device *dev, + struct drm_file *file_priv, uint32_t id) { struct drm_mode_object *mo; - mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PLANE); + mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_PLANE); return mo ? obj_to_plane(mo) : NULL; } diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h index 37355c623e6c..43fedd76957a 100644 --- a/include/drm/drm_property.h +++ b/include/drm/drm_property.h @@ -209,7 +209,7 @@ struct drm_property_blob { struct list_head head_global; struct list_head head_file; size_t length; - unsigned char data[]; + void *data; }; struct drm_prop_enum_list { @@ -237,28 +237,30 @@ static inline bool drm_property_type_is(struct drm_property *property, return property->flags & type; } -struct drm_property *drm_property_create(struct drm_device *dev, int flags, - const char *name, int num_values); -struct drm_property *drm_property_create_enum(struct drm_device *dev, int flags, - const char *name, +struct drm_property *drm_property_create(struct drm_device *dev, + u32 flags, const char *name, + int num_values); +struct drm_property *drm_property_create_enum(struct drm_device *dev, + u32 flags, const char *name, const struct drm_prop_enum_list *props, int num_values); struct drm_property *drm_property_create_bitmask(struct drm_device *dev, - int flags, const char *name, + u32 flags, const char *name, const struct drm_prop_enum_list *props, int num_props, uint64_t supported_bits); -struct drm_property *drm_property_create_range(struct drm_device *dev, int flags, - const char *name, +struct drm_property *drm_property_create_range(struct drm_device *dev, + u32 flags, const char *name, uint64_t min, uint64_t max); struct drm_property *drm_property_create_signed_range(struct drm_device *dev, - int flags, const char *name, + u32 flags, const char *name, int64_t min, int64_t max); struct drm_property *drm_property_create_object(struct drm_device *dev, - int flags, const char *name, uint32_t type); -struct drm_property *drm_property_create_bool(struct drm_device *dev, int flags, - const char *name); -int drm_property_add_enum(struct drm_property *property, int index, + u32 flags, const char *name, + uint32_t type); +struct drm_property *drm_property_create_bool(struct drm_device *dev, + u32 flags, const char *name); +int drm_property_add_enum(struct drm_property *property, uint64_t value, const char *name); void drm_property_destroy(struct drm_device *dev, struct drm_property *property); @@ -312,10 +314,11 @@ drm_property_unreference_blob(struct drm_property_blob *blob) * This function looks up the property object specified by id and returns it. */ static inline struct drm_property *drm_property_find(struct drm_device *dev, + struct drm_file *file_priv, uint32_t id) { struct drm_mode_object *mo; - mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PROPERTY); + mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_PROPERTY); return mo ? obj_to_property(mo) : NULL; } diff --git a/include/drm/drm_simple_kms_helper.h b/include/drm/drm_simple_kms_helper.h index 6d9adbb46293..d9e4c3c3f009 100644 --- a/include/drm/drm_simple_kms_helper.h +++ b/include/drm/drm_simple_kms_helper.h @@ -22,6 +22,20 @@ struct drm_simple_display_pipe; */ struct drm_simple_display_pipe_funcs { /** + * @mode_valid: + * + * This function is called to filter out valid modes from the + * suggestions suggested by the bridge or display. This optional + * hook is passed in when initializing the pipeline. + * + * RETURNS: + * + * drm_mode_status Enum + */ + enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc, + const struct drm_display_mode *mode); + + /** * @enable: * * This function should be used to enable the pipeline. diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index da59fd9cdb5e..2a25fdb2d9b8 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -271,6 +271,13 @@ #define IMX6QDL_CLK_PRE_AXI 258 #define IMX6QDL_CLK_MLB_SEL 259 #define IMX6QDL_CLK_MLB_PODF 260 -#define IMX6QDL_CLK_END 261 +#define IMX6QDL_CLK_AXI_ALT_SEL 261 +#define IMX6QDL_CLK_LDB_DI0_DIV_7 262 +#define IMX6QDL_CLK_LDB_DI1_DIV_7 263 +#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 264 +#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 265 +#define IMX6QDL_CLK_DCIC1 266 +#define IMX6QDL_CLK_DCIC2 267 +#define IMX6QDL_CLK_END 268 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index e14573e293c5..6bc731e00a89 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h @@ -175,6 +175,7 @@ #define IMX6SL_CLK_SSI2_IPG 162 #define IMX6SL_CLK_SSI3_IPG 163 #define IMX6SL_CLK_SPDIF_GCLK 164 -#define IMX6SL_CLK_END 165 +#define IMX6SL_CLK_UART_OSC_4M 165 +#define IMX6SL_CLK_END 166 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h new file mode 100644 index 000000000000..b68a89ee82cd --- /dev/null +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H +#define __DT_BINDINGS_CLOCK_IMX6SLL_H + +#define IMX6SLL_CLK_DUMMY 0 +#define IMX6SLL_CLK_CKIL 1 +#define IMX6SLL_CLK_OSC 2 +#define IMX6SLL_PLL1_BYPASS_SRC 3 +#define IMX6SLL_PLL2_BYPASS_SRC 4 +#define IMX6SLL_PLL3_BYPASS_SRC 5 +#define IMX6SLL_PLL4_BYPASS_SRC 6 +#define IMX6SLL_PLL5_BYPASS_SRC 7 +#define IMX6SLL_PLL6_BYPASS_SRC 8 +#define IMX6SLL_PLL7_BYPASS_SRC 9 +#define IMX6SLL_CLK_PLL1 10 +#define IMX6SLL_CLK_PLL2 11 +#define IMX6SLL_CLK_PLL3 12 +#define IMX6SLL_CLK_PLL4 13 +#define IMX6SLL_CLK_PLL5 14 +#define IMX6SLL_CLK_PLL6 15 +#define IMX6SLL_CLK_PLL7 16 +#define IMX6SLL_PLL1_BYPASS 17 +#define IMX6SLL_PLL2_BYPASS 18 +#define IMX6SLL_PLL3_BYPASS 19 +#define IMX6SLL_PLL4_BYPASS 20 +#define IMX6SLL_PLL5_BYPASS 21 +#define IMX6SLL_PLL6_BYPASS 22 +#define IMX6SLL_PLL7_BYPASS 23 +#define IMX6SLL_CLK_PLL1_SYS 24 +#define IMX6SLL_CLK_PLL2_BUS 25 +#define IMX6SLL_CLK_PLL3_USB_OTG 26 +#define IMX6SLL_CLK_PLL4_AUDIO 27 +#define IMX6SLL_CLK_PLL5_VIDEO 28 +#define IMX6SLL_CLK_PLL6_ENET 29 +#define IMX6SLL_CLK_PLL7_USB_HOST 30 +#define IMX6SLL_CLK_USBPHY1 31 +#define IMX6SLL_CLK_USBPHY2 32 +#define IMX6SLL_CLK_USBPHY1_GATE 33 +#define IMX6SLL_CLK_USBPHY2_GATE 34 +#define IMX6SLL_CLK_PLL2_PFD0 35 +#define IMX6SLL_CLK_PLL2_PFD1 36 +#define IMX6SLL_CLK_PLL2_PFD2 37 +#define IMX6SLL_CLK_PLL2_PFD3 38 +#define IMX6SLL_CLK_PLL3_PFD0 39 +#define IMX6SLL_CLK_PLL3_PFD1 40 +#define IMX6SLL_CLK_PLL3_PFD2 41 +#define IMX6SLL_CLK_PLL3_PFD3 42 +#define IMX6SLL_CLK_PLL4_POST_DIV 43 +#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 +#define IMX6SLL_CLK_PLL5_POST_DIV 45 +#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 +#define IMX6SLL_CLK_PLL2_198M 47 +#define IMX6SLL_CLK_PLL3_120M 48 +#define IMX6SLL_CLK_PLL3_80M 49 +#define IMX6SLL_CLK_PLL3_60M 50 +#define IMX6SLL_CLK_STEP 51 +#define IMX6SLL_CLK_PLL1_SW 52 +#define IMX6SLL_CLK_AXI_ALT_SEL 53 +#define IMX6SLL_CLK_AXI_SEL 54 +#define IMX6SLL_CLK_PERIPH_PRE 55 +#define IMX6SLL_CLK_PERIPH2_PRE 56 +#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 +#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 +#define IMX6SLL_CLK_PERCLK_SEL 59 +#define IMX6SLL_CLK_USDHC1_SEL 60 +#define IMX6SLL_CLK_USDHC2_SEL 61 +#define IMX6SLL_CLK_USDHC3_SEL 62 +#define IMX6SLL_CLK_SSI1_SEL 63 +#define IMX6SLL_CLK_SSI2_SEL 64 +#define IMX6SLL_CLK_SSI3_SEL 65 +#define IMX6SLL_CLK_PXP_SEL 66 +#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 +#define IMX6SLL_CLK_LCDIF_SEL 68 +#define IMX6SLL_CLK_EPDC_PRE_SEL 69 +#define IMX6SLL_CLK_SPDIF_SEL 70 +#define IMX6SLL_CLK_ECSPI_SEL 71 +#define IMX6SLL_CLK_UART_SEL 72 +#define IMX6SLL_CLK_ARM 73 +#define IMX6SLL_CLK_PERIPH 74 +#define IMX6SLL_CLK_PERIPH2 75 +#define IMX6SLL_CLK_PERIPH2_CLK2 76 +#define IMX6SLL_CLK_PERIPH_CLK2 77 +#define IMX6SLL_CLK_MMDC_PODF 78 +#define IMX6SLL_CLK_AXI_PODF 79 +#define IMX6SLL_CLK_AHB 80 +#define IMX6SLL_CLK_IPG 81 +#define IMX6SLL_CLK_PERCLK 82 +#define IMX6SLL_CLK_USDHC1_PODF 83 +#define IMX6SLL_CLK_USDHC2_PODF 84 +#define IMX6SLL_CLK_USDHC3_PODF 85 +#define IMX6SLL_CLK_SSI1_PRED 86 +#define IMX6SLL_CLK_SSI2_PRED 87 +#define IMX6SLL_CLK_SSI3_PRED 88 +#define IMX6SLL_CLK_SSI1_PODF 89 +#define IMX6SLL_CLK_SSI2_PODF 90 +#define IMX6SLL_CLK_SSI3_PODF 91 +#define IMX6SLL_CLK_PXP_PODF 92 +#define IMX6SLL_CLK_LCDIF_PRED 93 +#define IMX6SLL_CLK_LCDIF_PODF 94 +#define IMX6SLL_CLK_EPDC_SEL 95 +#define IMX6SLL_CLK_EPDC_PODF 96 +#define IMX6SLL_CLK_SPDIF_PRED 97 +#define IMX6SLL_CLK_SPDIF_PODF 98 +#define IMX6SLL_CLK_ECSPI_PODF 99 +#define IMX6SLL_CLK_UART_PODF 100 + +/* CCGR 0 */ +#define IMX6SLL_CLK_AIPSTZ1 101 +#define IMX6SLL_CLK_AIPSTZ2 102 +#define IMX6SLL_CLK_DCP 103 +#define IMX6SLL_CLK_UART2_IPG 104 +#define IMX6SLL_CLK_UART2_SERIAL 105 + +/* CCGR 1 */ +#define IMX6SLL_CLK_ECSPI1 106 +#define IMX6SLL_CLK_ECSPI2 107 +#define IMX6SLL_CLK_ECSPI3 108 +#define IMX6SLL_CLK_ECSPI4 109 +#define IMX6SLL_CLK_UART3_IPG 110 +#define IMX6SLL_CLK_UART3_SERIAL 111 +#define IMX6SLL_CLK_UART4_IPG 112 +#define IMX6SLL_CLK_UART4_SERIAL 113 +#define IMX6SLL_CLK_EPIT1 114 +#define IMX6SLL_CLK_EPIT2 115 +#define IMX6SLL_CLK_GPT_BUS 116 +#define IMX6SLL_CLK_GPT_SERIAL 117 + +/* CCGR2 */ +#define IMX6SLL_CLK_CSI 118 +#define IMX6SLL_CLK_I2C1 119 +#define IMX6SLL_CLK_I2C2 120 +#define IMX6SLL_CLK_I2C3 121 +#define IMX6SLL_CLK_OCOTP 122 +#define IMX6SLL_CLK_LCDIF_APB 123 +#define IMX6SLL_CLK_PXP 124 + +/* CCGR3 */ +#define IMX6SLL_CLK_UART5_IPG 125 +#define IMX6SLL_CLK_UART5_SERIAL 126 +#define IMX6SLL_CLK_EPDC_AXI 127 +#define IMX6SLL_CLK_EPDC_PIX 128 +#define IMX6SLL_CLK_LCDIF_PIX 129 +#define IMX6SLL_CLK_WDOG1 130 +#define IMX6SLL_CLK_MMDC_P0_FAST 131 +#define IMX6SLL_CLK_MMDC_P0_IPG 132 +#define IMX6SLL_CLK_OCRAM 133 + +/* CCGR4 */ +#define IMX6SLL_CLK_PWM1 134 +#define IMX6SLL_CLK_PWM2 135 +#define IMX6SLL_CLK_PWM3 136 +#define IMX6SLL_CLK_PWM4 137 + +/* CCGR 5 */ +#define IMX6SLL_CLK_ROM 138 +#define IMX6SLL_CLK_SDMA 139 +#define IMX6SLL_CLK_KPP 140 +#define IMX6SLL_CLK_WDOG2 141 +#define IMX6SLL_CLK_SPBA 142 +#define IMX6SLL_CLK_SPDIF 143 +#define IMX6SLL_CLK_SPDIF_GCLK 144 +#define IMX6SLL_CLK_SSI1 145 +#define IMX6SLL_CLK_SSI1_IPG 146 +#define IMX6SLL_CLK_SSI2 147 +#define IMX6SLL_CLK_SSI2_IPG 148 +#define IMX6SLL_CLK_SSI3 149 +#define IMX6SLL_CLK_SSI3_IPG 150 +#define IMX6SLL_CLK_UART1_IPG 151 +#define IMX6SLL_CLK_UART1_SERIAL 152 + +/* CCGR 6 */ +#define IMX6SLL_CLK_USBOH3 153 +#define IMX6SLL_CLK_USDHC1 154 +#define IMX6SLL_CLK_USDHC2 155 +#define IMX6SLL_CLK_USDHC3 156 + +#define IMX6SLL_CLK_IPP_DI0 157 +#define IMX6SLL_CLK_IPP_DI1 158 +#define IMX6SLL_CLK_LDB_DI0_SEL 159 +#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 +#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 +#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 +#define IMX6SLL_CLK_LDB_DI0 163 +#define IMX6SLL_CLK_LDB_DI1_SEL 164 +#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 +#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 +#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 +#define IMX6SLL_CLK_LDB_DI1 168 +#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 +#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 +#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 +#define IMX6SLL_CLK_EXTERN_AUDIO 172 +#define IMX6SLL_CLK_GPT_3M 173 + +#define IMX6SLL_CLK_END 174 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h index 36f0324902a5..a248f928a30a 100644 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ b/include/dt-bindings/clock/imx6sx-clock.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -275,6 +275,10 @@ #define IMX6SX_PLL6_BYPASS 262 #define IMX6SX_PLL7_BYPASS 263 #define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_CLK_END 265 +#define IMX6SX_CLK_LVDS2_SEL 265 +#define IMX6SX_CLK_LVDS2_OUT 266 +#define IMX6SX_CLK_LVDS2_IN 267 +#define IMX6SX_CLK_ANACLK2 268 +#define IMX6SX_CLK_CLK_END 269 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index de62a83b6c80..6b5d908d303e 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -80,10 +81,10 @@ #define IMX7D_ARM_M4_ROOT_SRC 67 #define IMX7D_ARM_M4_ROOT_CG 68 #define IMX7D_ARM_M4_ROOT_DIV 69 -#define IMX7D_ARM_M0_ROOT_CLK 70 -#define IMX7D_ARM_M0_ROOT_SRC 71 -#define IMX7D_ARM_M0_ROOT_CG 72 -#define IMX7D_ARM_M0_ROOT_DIV 73 +#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ +#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ +#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ +#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ #define IMX7D_MAIN_AXI_ROOT_CLK 74 #define IMX7D_MAIN_AXI_ROOT_SRC 75 #define IMX7D_MAIN_AXI_ROOT_CG 76 @@ -452,5 +453,11 @@ #define IMX7D_OCOTP_CLK 439 #define IMX7D_NAND_RAWNAND_CLK 440 #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_CLK_END 442 +#define IMX7D_CAAM_CLK 442 +#define IMX7D_PXP_IPG_CLK 443 +#define IMX7D_PXP_AXI_CLK 444 +#define IMX7D_ENET1_IPG_ROOT_CLK 445 +#define IMX7D_ENET2_IPG_ROOT_CLK 446 +#define IMX7D_CLK_END 447 + #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h new file mode 100644 index 000000000000..28413e25bc67 --- /dev/null +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H +#define __DT_BINDINGS_CLOCK_IMX7ULP_H + +#define IMX7ULP_CLK_DUMMY 0 +#define IMX7ULP_CLK_ROSC 1 +#define IMX7ULP_CLK_SOSC 2 +#define IMX7ULP_CLK_FIRC 3 + +/* SCG1 */ +#define IMX7ULP_CLK_SPLL_PRE_SEL 4 +#define IMX7ULP_CLK_SPLL_PRE_DIV 5 +#define IMX7ULP_CLK_SPLL 6 +#define IMX7ULP_CLK_SPLL_POST_DIV1 7 +#define IMX7ULP_CLK_SPLL_POST_DIV2 8 +#define IMX7ULP_CLK_SPLL_PFD0 9 +#define IMX7ULP_CLK_SPLL_PFD1 10 +#define IMX7ULP_CLK_SPLL_PFD2 11 +#define IMX7ULP_CLK_SPLL_PFD3 12 +#define IMX7ULP_CLK_SPLL_PFD_SEL 13 +#define IMX7ULP_CLK_SPLL_SEL 14 +#define IMX7ULP_CLK_APLL_PRE_SEL 15 +#define IMX7ULP_CLK_APLL_PRE_DIV 16 +#define IMX7ULP_CLK_APLL 17 +#define IMX7ULP_CLK_APLL_POST_DIV1 18 +#define IMX7ULP_CLK_APLL_POST_DIV2 19 +#define IMX7ULP_CLK_APLL_PFD0 20 +#define IMX7ULP_CLK_APLL_PFD1 21 +#define IMX7ULP_CLK_APLL_PFD2 22 +#define IMX7ULP_CLK_APLL_PFD3 23 +#define IMX7ULP_CLK_APLL_PFD_SEL 24 +#define IMX7ULP_CLK_APLL_SEL 25 +#define IMX7ULP_CLK_UPLL 26 +#define IMX7ULP_CLK_SYS_SEL 27 +#define IMX7ULP_CLK_CORE_DIV 28 +#define IMX7ULP_CLK_BUS_DIV 29 +#define IMX7ULP_CLK_PLAT_DIV 30 +#define IMX7ULP_CLK_DDR_SEL 31 +#define IMX7ULP_CLK_DDR_DIV 32 +#define IMX7ULP_CLK_NIC_SEL 33 +#define IMX7ULP_CLK_NIC0_DIV 34 +#define IMX7ULP_CLK_GPU_DIV 35 +#define IMX7ULP_CLK_NIC1_DIV 36 +#define IMX7ULP_CLK_NIC1_BUS_DIV 37 +#define IMX7ULP_CLK_NIC1_EXT_DIV 38 + +/* PCG2 */ +#define IMX7ULP_CLK_DMA1 39 +#define IMX7ULP_CLK_RGPIO2P1 40 +#define IMX7ULP_CLK_FLEXBUS 41 +#define IMX7ULP_CLK_SEMA42_1 42 +#define IMX7ULP_CLK_DMA_MUX1 43 +#define IMX7ULP_CLK_SNVS 44 +#define IMX7ULP_CLK_CAAM 45 +#define IMX7ULP_CLK_LPTPM4 46 +#define IMX7ULP_CLK_LPTPM5 47 +#define IMX7ULP_CLK_LPIT1 48 +#define IMX7ULP_CLK_LPSPI2 49 +#define IMX7ULP_CLK_LPSPI3 50 +#define IMX7ULP_CLK_LPI2C4 51 +#define IMX7ULP_CLK_LPI2C5 52 +#define IMX7ULP_CLK_LPUART4 53 +#define IMX7ULP_CLK_LPUART5 54 +#define IMX7ULP_CLK_FLEXIO1 55 +#define IMX7ULP_CLK_USB0 56 +#define IMX7ULP_CLK_USB1 57 +#define IMX7ULP_CLK_USB_PHY 58 +#define IMX7ULP_CLK_USB_PL301 59 +#define IMX7ULP_CLK_USDHC0 60 +#define IMX7ULP_CLK_USDHC1 61 +#define IMX7ULP_CLK_WDG1 62 +#define IMX7ULP_CLK_WDG2 63 + +/* PCG3 */ +#define IMX7ULP_CLK_LPTPM6 64 +#define IMX7ULP_CLK_LPTPM7 65 +#define IMX7ULP_CLK_LPI2C6 66 +#define IMX7ULP_CLK_LPI2C7 67 +#define IMX7ULP_CLK_LPUART6 68 +#define IMX7ULP_CLK_LPUART7 69 +#define IMX7ULP_CLK_VIU 70 +#define IMX7ULP_CLK_DSI 71 +#define IMX7ULP_CLK_LCDIF 72 +#define IMX7ULP_CLK_MMDC 73 +#define IMX7ULP_CLK_PCTLC 74 +#define IMX7ULP_CLK_PCTLD 75 +#define IMX7ULP_CLK_PCTLE 76 +#define IMX7ULP_CLK_PCTLF 77 +#define IMX7ULP_CLK_GPU3D 78 +#define IMX7ULP_CLK_GPU2D 79 + +#define IMX7ULP_CLK_MIPI_PLL 80 +#define IMX7ULP_CLK_SIRC 81 + +#define IMX7ULP_CLK_SCG1_CLKOUT 82 +#define IMX7ULP_CLK_HSRUN_SYS_SEL 83 +#define IMX7ULP_CLK_HSRUN_CORE 84 +#define IMX7ULP_CLK_ARM 85 + +#define IMX7ULP_CLK_SOSC_BUS_CLK 86 +#define IMX7ULP_CLK_FIRC_BUS_CLK 87 +#define IMX7ULP_CLK_SPLL_BUS_CLK 88 + +#define IMX7ULP_CLK_END 89 + +/*cm4 clocks*/ +#define IMX7ULP_CM4_CLK_DUMMY 0 +#define IMX7ULP_CM4_CLK_ROSC 1 +#define IMX7ULP_CM4_CLK_SOSC 2 +#define IMX7ULP_CM4_CLK_FIRC 3 +#define IMX7ULP_CM4_CLK_SIRC 4 + +/* SCG0 */ +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5 +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6 +#define IMX7ULP_CM4_CLK_SPLL 7 +#define IMX7ULP_CM4_CLK_SPLL_VCO 8 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10 +#define IMX7ULP_CM4_CLK_SPLL_PFD0 11 +#define IMX7ULP_CM4_CLK_SPLL_PFD1 12 +#define IMX7ULP_CM4_CLK_SPLL_PFD2 13 +#define IMX7ULP_CM4_CLK_SPLL_PFD3 14 +#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15 +#define IMX7ULP_CM4_CLK_SPLL_PFD 16 +#define IMX7ULP_CM4_CLK_SPLL_SEL 17 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19 +#define IMX7ULP_CM4_CLK_APLL 20 +#define IMX7ULP_CM4_CLK_APLL_VCO 21 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23 +#define IMX7ULP_CM4_CLK_APLL_PFD0 24 +#define IMX7ULP_CM4_CLK_APLL_PFD1 25 +#define IMX7ULP_CM4_CLK_APLL_PFD2 26 +#define IMX7ULP_CM4_CLK_APLL_PFD3 27 +#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28 +#define IMX7ULP_CM4_CLK_APLL_PFD 29 +#define IMX7ULP_CM4_CLK_APLL_SEL 30 +#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31 +#define IMX7ULP_CM4_CLK_SYS_SEL 32 +#define IMX7ULP_CM4_CLK_CORE_DIV 33 +#define IMX7ULP_CM4_CLK_BUS_DIV 34 +#define IMX7ULP_CM4_CLK_PLAT_DIV 35 +#define IMX7ULP_CM4_CLK_SLOW_DIV 36 + +#define IMX7ULP_CM4_CLK_SAI0_SEL 37 +#define IMX7ULP_CM4_CLK_SAI0_DIV 38 +#define IMX7ULP_CM4_CLK_SAI0_ROOT 39 +#define IMX7ULP_CM4_CLK_SAI0_IPG 40 +#define IMX7ULP_CM4_CLK_SAI1_SEL 41 +#define IMX7ULP_CM4_CLK_SAI1_DIV 42 +#define IMX7ULP_CM4_CLK_SAI1_ROOT 43 +#define IMX7ULP_CM4_CLK_SAI1_IPG 44 + +#define IMX7ULP_CLK_SCG0_CLKOUT 45 + +#define IMX7ULP_CM4_CLK_END 46 + +#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h new file mode 100644 index 000000000000..45fcb1e9ba22 --- /dev/null +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H +#define __DT_BINDINGS_CLOCK_IMX8MM_H + +#define IMX8MM_CLK_DUMMY 0 +#define IMX8MM_CLK_32K 1 +#define IMX8MM_CLK_24M 2 +#define IMX8MM_OSC_HDMI_CLK 3 +#define IMX8MM_CLK_EXT1 4 +#define IMX8MM_CLK_EXT2 5 +#define IMX8MM_CLK_EXT3 6 +#define IMX8MM_CLK_EXT4 7 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_DRAM_PLL_REF_SEL 11 +#define IMX8MM_GPU_PLL_REF_SEL 12 +#define IMX8MM_VPU_PLL_REF_SEL 13 +#define IMX8MM_ARM_PLL_REF_SEL 14 +#define IMX8MM_SYS_PLL1_REF_SEL 15 +#define IMX8MM_SYS_PLL2_REF_SEL 16 +#define IMX8MM_SYS_PLL3_REF_SEL 17 +#define IMX8MM_AUDIO_PLL1 18 +#define IMX8MM_AUDIO_PLL2 19 +#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_DRAM_PLL 21 +#define IMX8MM_GPU_PLL 22 +#define IMX8MM_VPU_PLL 23 +#define IMX8MM_ARM_PLL 24 +#define IMX8MM_SYS_PLL1 25 +#define IMX8MM_SYS_PLL2 26 +#define IMX8MM_SYS_PLL3 27 +#define IMX8MM_AUDIO_PLL1_BYPASS 28 +#define IMX8MM_AUDIO_PLL2_BYPASS 29 +#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_DRAM_PLL_BYPASS 31 +#define IMX8MM_GPU_PLL_BYPASS 32 +#define IMX8MM_VPU_PLL_BYPASS 33 +#define IMX8MM_ARM_PLL_BYPASS 34 +#define IMX8MM_SYS_PLL1_BYPASS 35 +#define IMX8MM_SYS_PLL2_BYPASS 36 +#define IMX8MM_SYS_PLL3_BYPASS 37 +#define IMX8MM_AUDIO_PLL1_OUT 38 +#define IMX8MM_AUDIO_PLL2_OUT 39 +#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_DRAM_PLL_OUT 41 +#define IMX8MM_GPU_PLL_OUT 42 +#define IMX8MM_VPU_PLL_OUT 43 +#define IMX8MM_ARM_PLL_OUT 44 +#define IMX8MM_SYS_PLL1_OUT 45 +#define IMX8MM_SYS_PLL2_OUT 46 +#define IMX8MM_SYS_PLL3_OUT 47 +#define IMX8MM_SYS_PLL1_40M 48 +#define IMX8MM_SYS_PLL1_80M 49 +#define IMX8MM_SYS_PLL1_100M 50 +#define IMX8MM_SYS_PLL1_133M 51 +#define IMX8MM_SYS_PLL1_160M 52 +#define IMX8MM_SYS_PLL1_200M 53 +#define IMX8MM_SYS_PLL1_266M 54 +#define IMX8MM_SYS_PLL1_400M 55 +#define IMX8MM_SYS_PLL1_800M 56 +#define IMX8MM_SYS_PLL2_50M 57 +#define IMX8MM_SYS_PLL2_100M 58 +#define IMX8MM_SYS_PLL2_125M 59 +#define IMX8MM_SYS_PLL2_166M 60 +#define IMX8MM_SYS_PLL2_200M 61 +#define IMX8MM_SYS_PLL2_250M 62 +#define IMX8MM_SYS_PLL2_333M 63 +#define IMX8MM_SYS_PLL2_500M 64 +#define IMX8MM_SYS_PLL2_1000M 65 + +/* core */ +#define IMX8MM_CLK_A53_SRC 66 +#define IMX8MM_CLK_M4_SRC 67 +#define IMX8MM_CLK_VPU_SRC 68 +#define IMX8MM_CLK_GPU3D_SRC 69 +#define IMX8MM_CLK_GPU2D_SRC 70 +#define IMX8MM_CLK_A53_CG 71 +#define IMX8MM_CLK_M4_CG 72 +#define IMX8MM_CLK_VPU_CG 73 +#define IMX8MM_CLK_GPU3D_CG 74 +#define IMX8MM_CLK_GPU2D_CG 75 +#define IMX8MM_CLK_A53_DIV 76 +#define IMX8MM_CLK_M4_DIV 77 +#define IMX8MM_CLK_VPU_DIV 78 +#define IMX8MM_CLK_GPU3D_DIV 79 +#define IMX8MM_CLK_GPU2D_DIV 80 + +/* bus */ +#define IMX8MM_CLK_MAIN_AXI 81 +#define IMX8MM_CLK_ENET_AXI 82 +#define IMX8MM_CLK_NAND_USDHC_BUS 83 +#define IMX8MM_CLK_VPU_BUS 84 +#define IMX8MM_CLK_DISP_AXI 85 +#define IMX8MM_CLK_DISP_APB 86 +#define IMX8MM_CLK_DISP_RTRM 87 +#define IMX8MM_CLK_USB_BUS 88 +#define IMX8MM_CLK_GPU_AXI 89 +#define IMX8MM_CLK_GPU_AHB 90 +#define IMX8MM_CLK_NOC 91 +#define IMX8MM_CLK_NOC_APB 92 + +#define IMX8MM_CLK_AHB 93 +#define IMX8MM_CLK_AUDIO_AHB 94 +#define IMX8MM_CLK_IPG_ROOT 95 +#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 + +#define IMX8MM_CLK_DRAM_ALT 97 +#define IMX8MM_CLK_DRAM_APB 98 +#define IMX8MM_CLK_VPU_G1 99 +#define IMX8MM_CLK_VPU_G2 100 +#define IMX8MM_CLK_DISP_DTRC 101 +#define IMX8MM_CLK_DISP_DC8000 102 +#define IMX8MM_CLK_PCIE1_CTRL 103 +#define IMX8MM_CLK_PCIE1_PHY 104 +#define IMX8MM_CLK_PCIE1_AUX 105 +#define IMX8MM_CLK_DC_PIXEL 106 +#define IMX8MM_CLK_LCDIF_PIXEL 107 +#define IMX8MM_CLK_SAI1 108 +#define IMX8MM_CLK_SAI2 109 +#define IMX8MM_CLK_SAI3 110 +#define IMX8MM_CLK_SAI4 111 +#define IMX8MM_CLK_SAI5 112 +#define IMX8MM_CLK_SAI6 113 +#define IMX8MM_CLK_SPDIF1 114 +#define IMX8MM_CLK_SPDIF2 115 +#define IMX8MM_CLK_ENET_REF 116 +#define IMX8MM_CLK_ENET_TIMER 117 +#define IMX8MM_CLK_ENET_PHY_REF 118 +#define IMX8MM_CLK_NAND 119 +#define IMX8MM_CLK_QSPI 120 +#define IMX8MM_CLK_USDHC1 121 +#define IMX8MM_CLK_USDHC2 122 +#define IMX8MM_CLK_I2C1 123 +#define IMX8MM_CLK_I2C2 124 +#define IMX8MM_CLK_I2C3 125 +#define IMX8MM_CLK_I2C4 126 +#define IMX8MM_CLK_UART1 127 +#define IMX8MM_CLK_UART2 128 +#define IMX8MM_CLK_UART3 129 +#define IMX8MM_CLK_UART4 130 +#define IMX8MM_CLK_USB_CORE_REF 131 +#define IMX8MM_CLK_USB_PHY_REF 132 +#define IMX8MM_CLK_ECSPI1 133 +#define IMX8MM_CLK_ECSPI2 134 +#define IMX8MM_CLK_PWM1 135 +#define IMX8MM_CLK_PWM2 136 +#define IMX8MM_CLK_PWM3 137 +#define IMX8MM_CLK_PWM4 138 +#define IMX8MM_CLK_GPT1 139 +#define IMX8MM_CLK_WDOG 140 +#define IMX8MM_CLK_WRCLK 141 +#define IMX8MM_CLK_DSI_CORE 142 +#define IMX8MM_CLK_DSI_PHY_REF 143 +#define IMX8MM_CLK_DSI_DBI 144 +#define IMX8MM_CLK_USDHC3 145 +#define IMX8MM_CLK_CSI1_CORE 146 +#define IMX8MM_CLK_CSI1_PHY_REF 147 +#define IMX8MM_CLK_CSI1_ESC 148 +#define IMX8MM_CLK_CSI2_CORE 149 +#define IMX8MM_CLK_CSI2_PHY_REF 150 +#define IMX8MM_CLK_CSI2_ESC 151 +#define IMX8MM_CLK_PCIE2_CTRL 152 +#define IMX8MM_CLK_PCIE2_PHY 153 +#define IMX8MM_CLK_PCIE2_AUX 154 +#define IMX8MM_CLK_ECSPI3 155 +#define IMX8MM_CLK_PDM 156 +#define IMX8MM_CLK_VPU_H1 157 +#define IMX8MM_CLK_CLKO1 158 + +#define IMX8MM_CLK_ECSPI1_ROOT 159 +#define IMX8MM_CLK_ECSPI2_ROOT 160 +#define IMX8MM_CLK_ECSPI3_ROOT 161 +#define IMX8MM_CLK_ENET1_ROOT 162 +#define IMX8MM_CLK_GPT1_ROOT 163 +#define IMX8MM_CLK_I2C1_ROOT 164 +#define IMX8MM_CLK_I2C2_ROOT 165 +#define IMX8MM_CLK_I2C3_ROOT 166 +#define IMX8MM_CLK_I2C4_ROOT 167 +#define IMX8MM_CLK_OCOTP_ROOT 168 +#define IMX8MM_CLK_PCIE1_ROOT 169 +#define IMX8MM_CLK_PWM1_ROOT 170 +#define IMX8MM_CLK_PWM2_ROOT 171 +#define IMX8MM_CLK_PWM3_ROOT 172 +#define IMX8MM_CLK_PWM4_ROOT 173 +#define IMX8MM_CLK_QSPI_ROOT 174 +#define IMX8MM_CLK_NAND_ROOT 175 +#define IMX8MM_CLK_SAI1_ROOT 176 +#define IMX8MM_CLK_SAI1_IPG 177 +#define IMX8MM_CLK_SAI2_ROOT 178 +#define IMX8MM_CLK_SAI2_IPG 179 +#define IMX8MM_CLK_SAI3_ROOT 180 +#define IMX8MM_CLK_SAI3_IPG 181 +#define IMX8MM_CLK_SAI4_ROOT 182 +#define IMX8MM_CLK_SAI4_IPG 183 +#define IMX8MM_CLK_SAI5_ROOT 184 +#define IMX8MM_CLK_SAI5_IPG 185 +#define IMX8MM_CLK_SAI6_ROOT 186 +#define IMX8MM_CLK_SAI6_IPG 187 +#define IMX8MM_CLK_UART1_ROOT 188 +#define IMX8MM_CLK_UART2_ROOT 189 +#define IMX8MM_CLK_UART3_ROOT 190 +#define IMX8MM_CLK_UART4_ROOT 191 +#define IMX8MM_CLK_USB1_CTRL_ROOT 192 +#define IMX8MM_CLK_GPU3D_ROOT 193 +#define IMX8MM_CLK_USDHC1_ROOT 194 +#define IMX8MM_CLK_USDHC2_ROOT 195 +#define IMX8MM_CLK_WDOG1_ROOT 196 +#define IMX8MM_CLK_WDOG2_ROOT 197 +#define IMX8MM_CLK_WDOG3_ROOT 198 +#define IMX8MM_CLK_VPU_G1_ROOT 199 +#define IMX8MM_CLK_GPU_BUS_ROOT 200 +#define IMX8MM_CLK_VPU_H1_ROOT 201 +#define IMX8MM_CLK_VPU_G2_ROOT 202 +#define IMX8MM_CLK_PDM_ROOT 203 +#define IMX8MM_CLK_DISP_ROOT 204 +#define IMX8MM_CLK_DISP_AXI_ROOT 205 +#define IMX8MM_CLK_DISP_APB_ROOT 206 +#define IMX8MM_CLK_DISP_RTRM_ROOT 207 +#define IMX8MM_CLK_USDHC3_ROOT 208 +#define IMX8MM_CLK_TMU_ROOT 209 +#define IMX8MM_CLK_VPU_DEC_ROOT 210 +#define IMX8MM_CLK_SDMA1_ROOT 211 +#define IMX8MM_CLK_SDMA2_ROOT 212 +#define IMX8MM_CLK_SDMA3_ROOT 213 +#define IMX8MM_CLK_GPT_3M 214 +#define IMX8MM_CLK_ARM 215 +#define IMX8MM_CLK_PDM_IPG 216 +#define IMX8MM_CLK_GPU2D_ROOT 217 +#define IMX8MM_CLK_MU_ROOT 218 +#define IMX8MM_CLK_CSI1_ROOT 219 + +#define IMX8MM_CLK_DRAM_CORE 220 +#define IMX8MM_CLK_DRAM_ALT_ROOT 221 + +#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 + +#define IMX8MM_CLK_SIM_HSIO 223 + +#define IMX8MM_CLK_END 224 + +#endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h new file mode 100644 index 000000000000..afd99a31124e --- /dev/null +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -0,0 +1,217 @@ +/* + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H +#define __DT_BINDINGS_CLOCK_IMX8MN_H + +#define IMX8MN_CLK_DUMMY 0 +#define IMX8MN_CLK_32K 1 +#define IMX8MN_CLK_24M 2 +#define IMX8MN_OSC_HDMI_CLK 3 +#define IMX8MN_CLK_EXT1 4 +#define IMX8MN_CLK_EXT2 5 +#define IMX8MN_CLK_EXT3 6 +#define IMX8MN_CLK_EXT4 7 +#define IMX8MN_AUDIO_PLL1_REF_SEL 8 +#define IMX8MN_AUDIO_PLL2_REF_SEL 9 +#define IMX8MN_VIDEO_PLL1_REF_SEL 10 +#define IMX8MN_DRAM_PLL_REF_SEL 11 +#define IMX8MN_GPU_PLL_REF_SEL 12 +#define IMX8MN_VPU_PLL_REF_SEL 13 +#define IMX8MN_ARM_PLL_REF_SEL 14 +#define IMX8MN_SYS_PLL1_REF_SEL 15 +#define IMX8MN_SYS_PLL2_REF_SEL 16 +#define IMX8MN_SYS_PLL3_REF_SEL 17 +#define IMX8MN_AUDIO_PLL1 18 +#define IMX8MN_AUDIO_PLL2 19 +#define IMX8MN_VIDEO_PLL1 20 +#define IMX8MN_DRAM_PLL 21 +#define IMX8MN_GPU_PLL 22 +#define IMX8MN_VPU_PLL 23 +#define IMX8MN_ARM_PLL 24 +#define IMX8MN_SYS_PLL1 25 +#define IMX8MN_SYS_PLL2 26 +#define IMX8MN_SYS_PLL3 27 +#define IMX8MN_AUDIO_PLL1_BYPASS 28 +#define IMX8MN_AUDIO_PLL2_BYPASS 29 +#define IMX8MN_VIDEO_PLL1_BYPASS 30 +#define IMX8MN_DRAM_PLL_BYPASS 31 +#define IMX8MN_GPU_PLL_BYPASS 32 +#define IMX8MN_VPU_PLL_BYPASS 33 +#define IMX8MN_ARM_PLL_BYPASS 34 +#define IMX8MN_SYS_PLL1_BYPASS 35 +#define IMX8MN_SYS_PLL2_BYPASS 36 +#define IMX8MN_SYS_PLL3_BYPASS 37 +#define IMX8MN_AUDIO_PLL1_OUT 38 +#define IMX8MN_AUDIO_PLL2_OUT 39 +#define IMX8MN_VIDEO_PLL1_OUT 40 +#define IMX8MN_DRAM_PLL_OUT 41 +#define IMX8MN_GPU_PLL_OUT 42 +#define IMX8MN_VPU_PLL_OUT 43 +#define IMX8MN_ARM_PLL_OUT 44 +#define IMX8MN_SYS_PLL1_OUT 45 +#define IMX8MN_SYS_PLL2_OUT 46 +#define IMX8MN_SYS_PLL3_OUT 47 +#define IMX8MN_SYS_PLL1_40M 48 +#define IMX8MN_SYS_PLL1_80M 49 +#define IMX8MN_SYS_PLL1_100M 50 +#define IMX8MN_SYS_PLL1_133M 51 +#define IMX8MN_SYS_PLL1_160M 52 +#define IMX8MN_SYS_PLL1_200M 53 +#define IMX8MN_SYS_PLL1_266M 54 +#define IMX8MN_SYS_PLL1_400M 55 +#define IMX8MN_SYS_PLL1_800M 56 +#define IMX8MN_SYS_PLL2_50M 57 +#define IMX8MN_SYS_PLL2_100M 58 +#define IMX8MN_SYS_PLL2_125M 59 +#define IMX8MN_SYS_PLL2_166M 60 +#define IMX8MN_SYS_PLL2_200M 61 +#define IMX8MN_SYS_PLL2_250M 62 +#define IMX8MN_SYS_PLL2_333M 63 +#define IMX8MN_SYS_PLL2_500M 64 +#define IMX8MN_SYS_PLL2_1000M 65 + +/* CORE CLOCK ROOT */ +#define IMX8MN_CLK_A53_SRC 66 +#define IMX8MN_CLK_GPU_CORE_SRC 67 +#define IMX8MN_CLK_GPU_SHADER_SRC 68 +#define IMX8MN_CLK_A53_CG 69 +#define IMX8MN_CLK_GPU_CORE_CG 70 +#define IMX8MN_CLK_GPU_SHADER_CG 71 +#define IMX8MN_CLK_A53_DIV 72 +#define IMX8MN_CLK_GPU_CORE_DIV 73 +#define IMX8MN_CLK_GPU_SHADER_DIV 74 + +/* BUS CLOCK ROOT */ +#define IMX8MN_CLK_MAIN_AXI 75 +#define IMX8MN_CLK_ENET_AXI 76 +#define IMX8MN_CLK_NAND_USDHC_BUS 77 +#define IMX8MN_CLK_DISP_AXI 78 +#define IMX8MN_CLK_DISP_APB 79 +#define IMX8MN_CLK_USB_BUS 80 +#define IMX8MN_CLK_GPU_AXI 81 +#define IMX8MN_CLK_GPU_AHB 82 +#define IMX8MN_CLK_NOC 83 +#define IMX8MN_CLK_AHB 84 +#define IMX8MN_CLK_AUDIO_AHB 85 + +/* IPG CLOCK ROOT */ +#define IMX8MN_CLK_IPG_ROOT 86 +#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 +/* IP */ +#define IMX8MN_CLK_DRAM_CORE 88 +#define IMX8MN_CLK_DRAM_ALT 89 +#define IMX8MN_CLK_DRAM_APB 90 +#define IMX8MN_CLK_DRAM_ALT_ROOT 91 +#define IMX8MN_CLK_DISP_PIXEL 92 +#define IMX8MN_CLK_SAI2 93 +#define IMX8MN_CLK_SAI3 94 +#define IMX8MN_CLK_SAI5 95 +#define IMX8MN_CLK_SAI6 96 +#define IMX8MN_CLK_SPDIF1 97 +#define IMX8MN_CLK_ENET_REF 98 +#define IMX8MN_CLK_ENET_TIMER 99 +#define IMX8MN_CLK_ENET_PHY_REF 100 +#define IMX8MN_CLK_NAND 101 +#define IMX8MN_CLK_QSPI 102 +#define IMX8MN_CLK_USDHC1 103 +#define IMX8MN_CLK_USDHC2 104 +#define IMX8MN_CLK_I2C1 105 +#define IMX8MN_CLK_I2C2 106 +#define IMX8MN_CLK_I2C3 107 +#define IMX8MN_CLK_I2C4 108 +#define IMX8MN_CLK_UART1 109 +#define IMX8MN_CLK_UART2 110 +#define IMX8MN_CLK_UART3 111 +#define IMX8MN_CLK_UART4 112 +#define IMX8MN_CLK_USB_CORE_REF 113 +#define IMX8MN_CLK_USB_PHY_REF 114 +#define IMX8MN_CLK_ECSPI1 115 +#define IMX8MN_CLK_ECSPI2 116 +#define IMX8MN_CLK_PWM1 117 +#define IMX8MN_CLK_PWM2 118 +#define IMX8MN_CLK_PWM3 119 +#define IMX8MN_CLK_PWM4 120 +#define IMX8MN_CLK_WDOG 121 +#define IMX8MN_CLK_WRCLK 122 +#define IMX8MN_CLK_CLKO1 123 +#define IMX8MN_CLK_CLKO2 124 +#define IMX8MN_CLK_DSI_CORE 125 +#define IMX8MN_CLK_DSI_PHY_REF 126 +#define IMX8MN_CLK_DSI_DBI 127 +#define IMX8MN_CLK_USDHC3 128 +#define IMX8MN_CLK_CAMERA_PIXEL 129 +#define IMX8MN_CLK_CSI1_PHY_REF 130 +#define IMX8MN_CLK_CSI2_PHY_REF 131 +#define IMX8MN_CLK_CSI2_ESC 132 +#define IMX8MN_CLK_ECSPI3 133 +#define IMX8MN_CLK_PDM 134 +#define IMX8MN_CLK_SAI7 135 + +#define IMX8MN_CLK_ECSPI1_ROOT 136 +#define IMX8MN_CLK_ECSPI2_ROOT 137 +#define IMX8MN_CLK_ECSPI3_ROOT 138 +#define IMX8MN_CLK_ENET1_ROOT 139 +#define IMX8MN_CLK_GPIO1_ROOT 140 +#define IMX8MN_CLK_GPIO2_ROOT 141 +#define IMX8MN_CLK_GPIO3_ROOT 142 +#define IMX8MN_CLK_GPIO4_ROOT 143 +#define IMX8MN_CLK_GPIO5_ROOT 144 +#define IMX8MN_CLK_I2C1_ROOT 145 +#define IMX8MN_CLK_I2C2_ROOT 146 +#define IMX8MN_CLK_I2C3_ROOT 147 +#define IMX8MN_CLK_I2C4_ROOT 148 +#define IMX8MN_CLK_MU_ROOT 149 +#define IMX8MN_CLK_OCOTP_ROOT 150 +#define IMX8MN_CLK_PWM1_ROOT 151 +#define IMX8MN_CLK_PWM2_ROOT 152 +#define IMX8MN_CLK_PWM3_ROOT 153 +#define IMX8MN_CLK_PWM4_ROOT 154 +#define IMX8MN_CLK_QSPI_ROOT 155 +#define IMX8MN_CLK_NAND_ROOT 156 +#define IMX8MN_CLK_SAI2_ROOT 157 +#define IMX8MN_CLK_SAI2_IPG 158 +#define IMX8MN_CLK_SAI3_ROOT 159 +#define IMX8MN_CLK_SAI3_IPG 160 +#define IMX8MN_CLK_SAI5_ROOT 161 +#define IMX8MN_CLK_SAI5_IPG 162 +#define IMX8MN_CLK_SAI6_ROOT 163 +#define IMX8MN_CLK_SAI6_IPG 164 +#define IMX8MN_CLK_SAI7_ROOT 165 +#define IMX8MN_CLK_SAI7_IPG 166 +#define IMX8MN_CLK_SDMA1_ROOT 167 +#define IMX8MN_CLK_SDMA2_ROOT 168 +#define IMX8MN_CLK_UART1_ROOT 169 +#define IMX8MN_CLK_UART2_ROOT 170 +#define IMX8MN_CLK_UART3_ROOT 171 +#define IMX8MN_CLK_UART4_ROOT 172 +#define IMX8MN_CLK_USB1_CTRL_ROOT 173 +#define IMX8MN_CLK_USDHC1_ROOT 174 +#define IMX8MN_CLK_USDHC2_ROOT 175 +#define IMX8MN_CLK_WDOG1_ROOT 176 +#define IMX8MN_CLK_WDOG2_ROOT 177 +#define IMX8MN_CLK_WDOG3_ROOT 178 +#define IMX8MN_CLK_GPU_BUS_ROOT 179 +#define IMX8MN_CLK_ASRC_ROOT 180 +#define IMX8MN_CLK_GPU3D_ROOT 181 +#define IMX8MN_CLK_PDM_ROOT 182 +#define IMX8MN_CLK_PDM_IPG 183 +#define IMX8MN_CLK_DISP_AXI_ROOT 184 +#define IMX8MN_CLK_DISP_APB_ROOT 185 +#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 +#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 +#define IMX8MN_CLK_USDHC3_ROOT 188 +#define IMX8MN_CLK_SDMA3_ROOT 189 +#define IMX8MN_CLK_TMU_ROOT 190 +#define IMX8MN_CLK_ARM 191 +#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 +#define IMX8MN_CLK_GPU_CORE_ROOT 193 + +#define IMX8MN_CLK_END 194 + +#endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h new file mode 100644 index 000000000000..e05eea7ce1e7 --- /dev/null +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -0,0 +1,410 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H +#define __DT_BINDINGS_CLOCK_IMX8MQ_H + +#define IMX8MQ_CLK_DUMMY 0 +#define IMX8MQ_CLK_32K 1 +#define IMX8MQ_CLK_25M 2 +#define IMX8MQ_CLK_27M 3 +#define IMX8MQ_CLK_EXT1 4 +#define IMX8MQ_CLK_EXT2 5 +#define IMX8MQ_CLK_EXT3 6 +#define IMX8MQ_CLK_EXT4 7 + +/* ANAMIX PLL clocks */ +/* FRAC PLLs */ +/* ARM PLL */ +#define IMX8MQ_ARM_PLL_REF_SEL 8 +#define IMX8MQ_ARM_PLL_REF_DIV 9 +#define IMX8MQ_ARM_PLL 10 +#define IMX8MQ_ARM_PLL_BYPASS 11 +#define IMX8MQ_ARM_PLL_OUT 12 + +/* GPU PLL */ +#define IMX8MQ_GPU_PLL_REF_SEL 13 +#define IMX8MQ_GPU_PLL_REF_DIV 14 +#define IMX8MQ_GPU_PLL 15 +#define IMX8MQ_GPU_PLL_BYPASS 16 +#define IMX8MQ_GPU_PLL_OUT 17 + +/* VPU PLL */ +#define IMX8MQ_VPU_PLL_REF_SEL 18 +#define IMX8MQ_VPU_PLL_REF_DIV 19 +#define IMX8MQ_VPU_PLL 20 +#define IMX8MQ_VPU_PLL_BYPASS 21 +#define IMX8MQ_VPU_PLL_OUT 22 + +/* AUDIO PLL1 */ +#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +#define IMX8MQ_AUDIO_PLL1 25 +#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +#define IMX8MQ_AUDIO_PLL1_OUT 27 + +/* AUDIO PLL2 */ +#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +#define IMX8MQ_AUDIO_PLL2 30 +#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +#define IMX8MQ_AUDIO_PLL2_OUT 32 + +/* VIDEO PLL1 */ +#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +#define IMX8MQ_VIDEO_PLL1 35 +#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +#define IMX8MQ_VIDEO_PLL1_OUT 37 + +/* SYS1 PLL */ +#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +#define IMX8MQ_SYS1_PLL1 40 +#define IMX8MQ_SYS1_PLL1_OUT 41 +#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +#define IMX8MQ_SYS1_PLL2 43 +#define IMX8MQ_SYS1_PLL2_DIV 44 +#define IMX8MQ_SYS1_PLL2_OUT 45 + +/* SYS2 PLL */ +#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +#define IMX8MQ_SYS2_PLL1 48 +#define IMX8MQ_SYS2_PLL1_OUT 49 +#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +#define IMX8MQ_SYS2_PLL2 51 +#define IMX8MQ_SYS2_PLL2_DIV 52 +#define IMX8MQ_SYS2_PLL2_OUT 53 + +/* SYS3 PLL */ +#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +#define IMX8MQ_SYS3_PLL1 56 +#define IMX8MQ_SYS3_PLL1_OUT 57 +#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +#define IMX8MQ_SYS3_PLL2 59 +#define IMX8MQ_SYS3_PLL2_DIV 60 +#define IMX8MQ_SYS3_PLL2_OUT 61 + +/* DRAM PLL */ +#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +#define IMX8MQ_DRAM_PLL1 64 +#define IMX8MQ_DRAM_PLL1_OUT 65 +#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +#define IMX8MQ_DRAM_PLL2 67 +#define IMX8MQ_DRAM_PLL2_DIV 68 +#define IMX8MQ_DRAM_PLL2_OUT 69 + +/* SYS PLL DIV */ +#define IMX8MQ_SYS1_PLL_40M 70 +#define IMX8MQ_SYS1_PLL_80M 71 +#define IMX8MQ_SYS1_PLL_100M 72 +#define IMX8MQ_SYS1_PLL_133M 73 +#define IMX8MQ_SYS1_PLL_160M 74 +#define IMX8MQ_SYS1_PLL_200M 75 +#define IMX8MQ_SYS1_PLL_266M 76 +#define IMX8MQ_SYS1_PLL_400M 77 +#define IMX8MQ_SYS1_PLL_800M 78 + +#define IMX8MQ_SYS2_PLL_50M 79 +#define IMX8MQ_SYS2_PLL_100M 80 +#define IMX8MQ_SYS2_PLL_125M 81 +#define IMX8MQ_SYS2_PLL_166M 82 +#define IMX8MQ_SYS2_PLL_200M 83 +#define IMX8MQ_SYS2_PLL_250M 84 +#define IMX8MQ_SYS2_PLL_333M 85 +#define IMX8MQ_SYS2_PLL_500M 86 +#define IMX8MQ_SYS2_PLL_1000M 87 + +/* CCM ROOT clocks */ +/* A53 */ +#define IMX8MQ_CLK_A53_SRC 88 +#define IMX8MQ_CLK_A53_CG 89 +#define IMX8MQ_CLK_A53_DIV 90 +/* M4 */ +#define IMX8MQ_CLK_M4_SRC 91 +#define IMX8MQ_CLK_M4_CG 92 +#define IMX8MQ_CLK_M4_DIV 93 +/* VPU */ +#define IMX8MQ_CLK_VPU_SRC 94 +#define IMX8MQ_CLK_VPU_CG 95 +#define IMX8MQ_CLK_VPU_DIV 96 +/* GPU CORE */ +#define IMX8MQ_CLK_GPU_CORE_SRC 97 +#define IMX8MQ_CLK_GPU_CORE_CG 98 +#define IMX8MQ_CLK_GPU_CORE_DIV 99 +/* GPU SHADER */ +#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +#define IMX8MQ_CLK_GPU_SHADER_CG 101 +#define IMX8MQ_CLK_GPU_SHADER_DIV 102 + +/* BUS TYPE */ +/* MAIN AXI */ +#define IMX8MQ_CLK_MAIN_AXI 103 +/* ENET AXI */ +#define IMX8MQ_CLK_ENET_AXI 104 +/* NAND_USDHC_BUS */ +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 +/* VPU BUS */ +#define IMX8MQ_CLK_VPU_BUS 106 +/* DISP_AXI */ +#define IMX8MQ_CLK_DISP_AXI 107 +/* DISP APB */ +#define IMX8MQ_CLK_DISP_APB 108 +/* DISP RTRM */ +#define IMX8MQ_CLK_DISP_RTRM 109 +/* USB_BUS */ +#define IMX8MQ_CLK_USB_BUS 110 +/* GPU_AXI */ +#define IMX8MQ_CLK_GPU_AXI 111 +/* GPU_AHB */ +#define IMX8MQ_CLK_GPU_AHB 112 +/* NOC */ +#define IMX8MQ_CLK_NOC 113 +/* NOC_APB */ +#define IMX8MQ_CLK_NOC_APB 114 + +/* AHB */ +#define IMX8MQ_CLK_AHB 115 +/* AUDIO AHB */ +#define IMX8MQ_CLK_AUDIO_AHB 116 + +/* DRAM_ALT */ +#define IMX8MQ_CLK_DRAM_ALT 117 +/* DRAM APB */ +#define IMX8MQ_CLK_DRAM_APB 118 +/* VPU_G1 */ +#define IMX8MQ_CLK_VPU_G1 119 +/* VPU_G2 */ +#define IMX8MQ_CLK_VPU_G2 120 +/* DISP_DTRC */ +#define IMX8MQ_CLK_DISP_DTRC 121 +/* DISP_DC8000 */ +#define IMX8MQ_CLK_DISP_DC8000 122 +/* PCIE_CTRL */ +#define IMX8MQ_CLK_PCIE1_CTRL 123 +/* PCIE_PHY */ +#define IMX8MQ_CLK_PCIE1_PHY 124 +/* PCIE_AUX */ +#define IMX8MQ_CLK_PCIE1_AUX 125 +/* DC_PIXEL */ +#define IMX8MQ_CLK_DC_PIXEL 126 +/* LCDIF_PIXEL */ +#define IMX8MQ_CLK_LCDIF_PIXEL 127 +/* SAI1~6 */ +#define IMX8MQ_CLK_SAI1 128 + +#define IMX8MQ_CLK_SAI2 129 + +#define IMX8MQ_CLK_SAI3 130 + +#define IMX8MQ_CLK_SAI4 131 + +#define IMX8MQ_CLK_SAI5 132 + +#define IMX8MQ_CLK_SAI6 133 +/* SPDIF1 */ +#define IMX8MQ_CLK_SPDIF1 134 +/* SPDIF2 */ +#define IMX8MQ_CLK_SPDIF2 135 +/* ENET_REF */ +#define IMX8MQ_CLK_ENET_REF 136 +/* ENET_TIMER */ +#define IMX8MQ_CLK_ENET_TIMER 137 +/* ENET_PHY */ +#define IMX8MQ_CLK_ENET_PHY_REF 138 +/* NAND */ +#define IMX8MQ_CLK_NAND 139 +/* QSPI */ +#define IMX8MQ_CLK_QSPI 140 +/* USDHC1 */ +#define IMX8MQ_CLK_USDHC1 141 +/* USDHC2 */ +#define IMX8MQ_CLK_USDHC2 142 +/* I2C1 */ +#define IMX8MQ_CLK_I2C1 143 +/* I2C2 */ +#define IMX8MQ_CLK_I2C2 144 +/* I2C3 */ +#define IMX8MQ_CLK_I2C3 145 +/* I2C4 */ +#define IMX8MQ_CLK_I2C4 146 +/* UART1 */ +#define IMX8MQ_CLK_UART1 148 +/* UART2 */ +#define IMX8MQ_CLK_UART2 149 +/* UART3 */ +#define IMX8MQ_CLK_UART3 150 +/* UART4 */ +#define IMX8MQ_CLK_UART4 151 +/* USB_CORE_REF */ +#define IMX8MQ_CLK_USB_CORE_REF 152 +/* USB_PHY_REF */ +#define IMX8MQ_CLK_USB_PHY_REF 153 +/* ECSPI1 */ +#define IMX8MQ_CLK_ECSPI1 154 +/* ECSPI2 */ +#define IMX8MQ_CLK_ECSPI2 155 +/* PWM1 */ +#define IMX8MQ_CLK_PWM1 156 +/* PWM2 */ +#define IMX8MQ_CLK_PWM2 157 +/* PWM3 */ +#define IMX8MQ_CLK_PWM3 158 +/* PWM4 */ +#define IMX8MQ_CLK_PWM4 159 +/* GPT1 */ +#define IMX8MQ_CLK_GPT1 160 +/* WDOG */ +#define IMX8MQ_CLK_WDOG 161 +/* WRCLK */ +#define IMX8MQ_CLK_WRCLK 162 +/* DSI_CORE */ +#define IMX8MQ_CLK_DSI_CORE 163 +/* DSI_PHY */ +#define IMX8MQ_CLK_DSI_PHY_REF 164 +/* DSI_DBI */ +#define IMX8MQ_CLK_DSI_DBI 165 +/*DSI_ESC */ +#define IMX8MQ_CLK_DSI_ESC 166 +/* CSI1_CORE */ +#define IMX8MQ_CLK_CSI1_CORE 167 +/* CSI1_PHY */ +#define IMX8MQ_CLK_CSI1_PHY_REF 168 +/* CSI_ESC */ +#define IMX8MQ_CLK_CSI1_ESC 169 +/* CSI2_CORE */ +#define IMX8MQ_CLK_CSI2_CORE 170 +/* CSI2_PHY */ +#define IMX8MQ_CLK_CSI2_PHY_REF 171 +/* CSI2_ESC */ +#define IMX8MQ_CLK_CSI2_ESC 172 +/* PCIE2_CTRL */ +#define IMX8MQ_CLK_PCIE2_CTRL 173 +/* PCIE2_PHY */ +#define IMX8MQ_CLK_PCIE2_PHY 174 +/* PCIE2_AUX */ +#define IMX8MQ_CLK_PCIE2_AUX 175 +/* ECSPI3 */ +#define IMX8MQ_CLK_ECSPI3 176 + +/* CCGR clocks */ +#define IMX8MQ_CLK_A53_ROOT 191 +#define IMX8MQ_CLK_DRAM_ROOT 192 +#define IMX8MQ_CLK_ECSPI1_ROOT 193 +#define IMX8MQ_CLK_ECSPI2_ROOT 194 +#define IMX8MQ_CLK_ECSPI3_ROOT 195 +#define IMX8MQ_CLK_ENET1_ROOT 196 +#define IMX8MQ_CLK_GPT1_ROOT 197 +#define IMX8MQ_CLK_I2C1_ROOT 198 +#define IMX8MQ_CLK_I2C2_ROOT 199 +#define IMX8MQ_CLK_I2C3_ROOT 200 +#define IMX8MQ_CLK_I2C4_ROOT 201 +#define IMX8MQ_CLK_M4_ROOT 202 +#define IMX8MQ_CLK_PCIE1_ROOT 203 +#define IMX8MQ_CLK_PCIE2_ROOT 204 +#define IMX8MQ_CLK_PWM1_ROOT 205 +#define IMX8MQ_CLK_PWM2_ROOT 206 +#define IMX8MQ_CLK_PWM3_ROOT 207 +#define IMX8MQ_CLK_PWM4_ROOT 208 +#define IMX8MQ_CLK_QSPI_ROOT 209 +#define IMX8MQ_CLK_SAI1_ROOT 210 +#define IMX8MQ_CLK_SAI2_ROOT 211 +#define IMX8MQ_CLK_SAI3_ROOT 212 +#define IMX8MQ_CLK_SAI4_ROOT 213 +#define IMX8MQ_CLK_SAI5_ROOT 214 +#define IMX8MQ_CLK_SAI6_ROOT 215 +#define IMX8MQ_CLK_UART1_ROOT 216 +#define IMX8MQ_CLK_UART2_ROOT 217 +#define IMX8MQ_CLK_UART3_ROOT 218 +#define IMX8MQ_CLK_UART4_ROOT 219 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 220 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 221 +#define IMX8MQ_CLK_USB1_PHY_ROOT 222 +#define IMX8MQ_CLK_USB2_PHY_ROOT 223 +#define IMX8MQ_CLK_USDHC1_ROOT 224 +#define IMX8MQ_CLK_USDHC2_ROOT 225 +#define IMX8MQ_CLK_WDOG1_ROOT 226 +#define IMX8MQ_CLK_WDOG2_ROOT 227 +#define IMX8MQ_CLK_WDOG3_ROOT 228 +#define IMX8MQ_CLK_GPU_ROOT 229 +#define IMX8MQ_CLK_HEVC_ROOT 230 +#define IMX8MQ_CLK_AVC_ROOT 231 +#define IMX8MQ_CLK_VP9_ROOT 232 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 233 +#define IMX8MQ_CLK_DISP_ROOT 234 +#define IMX8MQ_CLK_HDMI_ROOT 235 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 236 +#define IMX8MQ_CLK_VPU_DEC_ROOT 237 +#define IMX8MQ_CLK_CSI1_ROOT 238 +#define IMX8MQ_CLK_CSI2_ROOT 239 +#define IMX8MQ_CLK_RAWNAND_ROOT 240 +#define IMX8MQ_CLK_SDMA1_ROOT 241 +#define IMX8MQ_CLK_SDMA2_ROOT 242 +#define IMX8MQ_CLK_VPU_G1_ROOT 243 +#define IMX8MQ_CLK_VPU_G2_ROOT 244 + +/* SCCG PLL GATE */ +#define IMX8MQ_SYS1_PLL_OUT 245 +#define IMX8MQ_SYS2_PLL_OUT 246 +#define IMX8MQ_SYS3_PLL_OUT 247 +#define IMX8MQ_DRAM_PLL_OUT 248 + +#define IMX8MQ_GPT_3M_CLK 249 + +#define IMX8MQ_CLK_IPG_ROOT 250 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 251 +#define IMX8MQ_CLK_SAI1_IPG 252 +#define IMX8MQ_CLK_SAI2_IPG 253 +#define IMX8MQ_CLK_SAI3_IPG 254 +#define IMX8MQ_CLK_SAI4_IPG 255 +#define IMX8MQ_CLK_SAI5_IPG 256 +#define IMX8MQ_CLK_SAI6_IPG 257 + +/* DSI AHB/IPG clocks */ +/* rxesc clock */ +#define IMX8MQ_CLK_DSI_AHB 258 +/* txesc clock */ +#define IMX8MQ_CLK_DSI_IPG_DIV 259 + +/* VIDEO2 PLL */ +#define IMX8MQ_VIDEO2_PLL1_REF_SEL 260 +#define IMX8MQ_VIDEO2_PLL1_REF_DIV 261 +#define IMX8MQ_VIDEO2_PLL1 262 +#define IMX8MQ_VIDEO2_PLL1_OUT 263 +#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 264 +#define IMX8MQ_VIDEO2_PLL2 265 +#define IMX8MQ_VIDEO2_PLL2_DIV 266 +#define IMX8MQ_VIDEO2_PLL2_OUT 267 +#define IMX8MQ_CLK_TMU_ROOT 268 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 269 +#define IMX8MQ_CLK_DISP_APB_ROOT 270 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 271 + +#define IMX8MQ_CLK_OCOTP_ROOT 272 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 273 +#define IMX8MQ_CLK_DRAM_CORE 274 + +#define IMX8MQ_CLK_MU_ROOT 275 +#define IMX8MQ_VIDEO2_PLL_OUT 276 + +#define IMX8MQ_CLK_CLKO2 277 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 278 + +#define IMX8MQ_CLK_PHY_27MHZ 279 + +#define IMX8MQ_CLK_END 280 + +#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h new file mode 100644 index 000000000000..43870b236f4c --- /dev/null +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -0,0 +1,861 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H +#define __DT_BINDINGS_CLOCK_IMX8QM_H + +#define IMX8QM_CLK_DUMMY 0 + +#define IMX8QM_A53_DIV 1 +#define IMX8QM_A53_CLK 2 +#define IMX8QM_A72_DIV 3 +#define IMX8QM_A72_CLK 4 + +/* SC Clocks. */ +#define IMX8QM_SC_I2C_DIV 5 +#define IMX8QM_SC_I2C_CLK 6 +#define IMX8QM_SC_PID0_DIV 7 +#define IMX8QM_SC_PID0_CLK 8 +#define IMX8QM_SC_PIT_DIV 9 +#define IMX8QM_SC_PIT_CLK 10 +#define IMX8QM_SC_TPM_DIV 11 +#define IMX8QM_SC_TPM_CLK 12 +#define IMX8QM_SC_UART_DIV 13 +#define IMX8QM_SC_UART_CLK 14 + +/* LSIO */ +#define IMX8QM_PWM0_DIV 15 +#define IMX8QM_PWM0_CLK 16 +#define IMX8QM_PWM1_DIV 17 +#define IMX8QM_PWM1_CLK 18 +#define IMX8QM_PWM2_DIV 19 +#define IMX8QM_PWM2_CLK 20 +#define IMX8QM_PWM3_DIV 21 +#define IMX8QM_PWM3_CLK 22 +#define IMX8QM_PWM4_DIV 23 +#define IMX8QM_PWM4_CLK 24 +#define IMX8QM_PWM5_DIV 26 +#define IMX8QM_PWM5_CLK 27 +#define IMX8QM_PWM6_DIV 28 +#define IMX8QM_PWM6_CLK 29 +#define IMX8QM_PWM7_DIV 30 +#define IMX8QM_PWM7_CLK 31 +#define IMX8QM_FSPI0_DIV 32 +#define IMX8QM_FSPI0_CLK 33 +#define IMX8QM_FSPI1_DIV 34 +#define IMX8QM_FSPI1_CLK 35 +#define IMX8QM_GPT0_DIV 36 +#define IMX8QM_GPT0_CLK 37 +#define IMX8QM_GPT1_DIV 38 +#define IMX8QM_GPT1_CLK 39 +#define IMX8QM_GPT2_DIV 40 +#define IMX8QM_GPT2_CLK 41 +#define IMX8QM_GPT3_DIV 42 +#define IMX8QM_GPT3_CLK 43 +#define IMX8QM_GPT4_DIV 44 +#define IMX8QM_GPT4_CLK 45 + +/* Connectivity */ +#define IMX8QM_APBHDMA_CLK 46 +#define IMX8QM_GPMI_APB_CLK 47 +#define IMX8QM_GPMI_APB_BCH_CLK 48 +#define IMX8QM_GPMI_BCH_IO_DIV 49 +#define IMX8QM_GPMI_BCH_IO_CLK 50 +#define IMX8QM_GPMI_BCH_DIV 51 +#define IMX8QM_GPMI_BCH_CLK 52 +#define IMX8QM_SDHC0_IPG_CLK 53 +#define IMX8QM_SDHC0_DIV 54 +#define IMX8QM_SDHC0_CLK 55 +#define IMX8QM_SDHC1_IPG_CLK 56 +#define IMX8QM_SDHC1_DIV 57 +#define IMX8QM_SDHC1_CLK 58 +#define IMX8QM_SDHC2_IPG_CLK 59 +#define IMX8QM_SDHC2_DIV 60 +#define IMX8QM_SDHC2_CLK 61 +#define IMX8QM_USB2_OH_AHB_CLK 62 +#define IMX8QM_USB2_OH_IPG_S_CLK 63 +#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64 +#define IMX8QM_USB2_PHY_IPG_CLK 65 +#define IMX8QM_USB3_IPG_CLK 66 +#define IMX8QM_USB3_CORE_PCLK 67 +#define IMX8QM_USB3_PHY_CLK 68 +#define IMX8QM_USB3_ACLK_DIV 69 +#define IMX8QM_USB3_ACLK 70 +#define IMX8QM_USB3_BUS_DIV 71 +#define IMX8QM_USB3_BUS_CLK 72 +#define IMX8QM_USB3_LPM_DIV 73 +#define IMX8QM_USB3_LPM_CLK 74 +#define IMX8QM_ENET0_AHB_CLK 75 +#define IMX8QM_ENET0_IPG_S_CLK 76 +#define IMX8QM_ENET0_IPG_CLK 77 +#define IMX8QM_ENET0_RGMII_DIV 78 +#define IMX8QM_ENET0_RGMII_TX_CLK 79 +#define IMX8QM_ENET0_ROOT_DIV 80 +#define IMX8QM_ENET0_TX_CLK 81 +#define IMX8QM_ENET0_ROOT_CLK 82 +#define IMX8QM_ENET0_PTP_CLK 83 +#define IMX8QM_ENET0_BYPASS_DIV 84 +#define IMX8QM_ENET1_AHB_CLK 85 +#define IMX8QM_ENET1_IPG_S_CLK 86 +#define IMX8QM_ENET1_IPG_CLK 87 +#define IMX8QM_ENET1_RGMII_DIV 88 +#define IMX8QM_ENET1_RGMII_TX_CLK 89 +#define IMX8QM_ENET1_ROOT_DIV 90 +#define IMX8QM_ENET1_TX_CLK 91 +#define IMX8QM_ENET1_ROOT_CLK 92 +#define IMX8QM_ENET1_PTP_CLK 93 +#define IMX8QM_ENET1_BYPASS_DIV 94 +#define IMX8QM_MLB_CLK 95 +#define IMX8QM_MLB_HCLK 96 +#define IMX8QM_MLB_IPG_CLK 97 +#define IMX8QM_EDMA_CLK 98 +#define IMX8QM_EDMA_IPG_CLK 99 + +/* DMA */ +#define IMX8QM_SPI0_IPG_CLK 100 +#define IMX8QM_SPI0_DIV 101 +#define IMX8QM_SPI0_CLK 102 +#define IMX8QM_SPI1_IPG_CLK 103 +#define IMX8QM_SPI1_DIV 104 +#define IMX8QM_SPI1_CLK 105 +#define IMX8QM_SPI2_IPG_CLK 106 +#define IMX8QM_SPI2_DIV 107 +#define IMX8QM_SPI2_CLK 108 +#define IMX8QM_SPI3_IPG_CLK 109 +#define IMX8QM_SPI3_DIV 110 +#define IMX8QM_SPI3_CLK 111 +#define IMX8QM_UART0_IPG_CLK 112 +#define IMX8QM_UART0_DIV 113 +#define IMX8QM_UART0_CLK 114 +#define IMX8QM_UART1_IPG_CLK 115 +#define IMX8QM_UART1_DIV 116 +#define IMX8QM_UART1_CLK 117 +#define IMX8QM_UART2_IPG_CLK 118 +#define IMX8QM_UART2_DIV 119 +#define IMX8QM_UART2_CLK 120 +#define IMX8QM_UART3_IPG_CLK 121 +#define IMX8QM_UART3_DIV 122 +#define IMX8QM_UART3_CLK 123 +#define IMX8QM_UART4_IPG_CLK 124 +#define IMX8QM_UART4_DIV 125 +#define IMX8QM_EMVSIM0_IPG_CLK 126 +#define IMX8QM_UART4_CLK 127 +#define IMX8QM_EMVSIM0_DIV 128 +#define IMX8QM_EMVSIM0_CLK 129 +#define IMX8QM_EMVSIM1_IPG_CLK 130 +#define IMX8QM_EMVSIM1_DIV 131 +#define IMX8QM_EMVSIM1_CLK 132 +#define IMX8QM_CAN0_IPG_CHI_CLK 133 +#define IMX8QM_CAN0_IPG_CLK 134 +#define IMX8QM_CAN0_DIV 135 +#define IMX8QM_CAN0_CLK 136 +#define IMX8QM_CAN1_IPG_CHI_CLK 137 +#define IMX8QM_CAN1_IPG_CLK 138 +#define IMX8QM_CAN1_DIV 139 +#define IMX8QM_CAN1_CLK 140 +#define IMX8QM_CAN2_IPG_CHI_CLK 141 +#define IMX8QM_CAN2_IPG_CLK 142 +#define IMX8QM_CAN2_DIV 143 +#define IMX8QM_CAN2_CLK 144 +#define IMX8QM_I2C0_IPG_CLK 145 +#define IMX8QM_I2C0_DIV 146 +#define IMX8QM_I2C0_CLK 147 +#define IMX8QM_I2C1_IPG_CLK 148 +#define IMX8QM_I2C1_DIV 149 +#define IMX8QM_I2C1_CLK 150 +#define IMX8QM_I2C2_IPG_CLK 151 +#define IMX8QM_I2C2_DIV 152 +#define IMX8QM_I2C2_CLK 153 +#define IMX8QM_I2C3_IPG_CLK 154 +#define IMX8QM_I2C3_DIV 155 +#define IMX8QM_I2C3_CLK 156 +#define IMX8QM_I2C4_IPG_CLK 157 +#define IMX8QM_I2C4_DIV 158 +#define IMX8QM_I2C4_CLK 159 +#define IMX8QM_FTM0_IPG_CLK 160 +#define IMX8QM_FTM0_DIV 161 +#define IMX8QM_FTM0_CLK 162 +#define IMX8QM_FTM1_IPG_CLK 163 +#define IMX8QM_FTM1_DIV 164 +#define IMX8QM_FTM1_CLK 165 +#define IMX8QM_ADC0_IPG_CLK 166 +#define IMX8QM_ADC0_DIV 167 +#define IMX8QM_ADC0_CLK 168 +#define IMX8QM_ADC1_IPG_CLK 169 +#define IMX8QM_ADC1_DIV 170 +#define IMX8QM_ADC1_CLK 171 + +/* Audio */ +#define IMX8QM_AUD_PLL0_DIV 172 +#define IMX8QM_AUD_PLL0 173 +#define IMX8QM_AUD_PLL1_DIV 174 +#define IMX8QM_AUD_PLL1 175 +#define IMX8QM_AUD_AMIX_IPG 182 +#define IMX8QM_AUD_ESAI_0_IPG 183 +#define IMX8QM_AUD_ESAI_1_IPG 184 +#define IMX8QM_AUD_ESAI_0_EXTAL_IPG 185 +#define IMX8QM_AUD_ESAI_1_EXTAL_IPG 186 +#define IMX8QM_AUD_SAI_0_IPG 187 +#define IMX8QM_AUD_SAI_0_IPG_S 188 +#define IMX8QM_AUD_SAI_0_MCLK 189 +#define IMX8QM_AUD_SAI_1_IPG 190 +#define IMX8QM_AUD_SAI_1_IPG_S 191 +#define IMX8QM_AUD_SAI_1_MCLK 192 +#define IMX8QM_AUD_SAI_2_IPG 193 +#define IMX8QM_AUD_SAI_2_IPG_S 194 +#define IMX8QM_AUD_SAI_2_MCLK 195 +#define IMX8QM_AUD_SAI_3_IPG 196 +#define IMX8QM_AUD_SAI_3_IPG_S 197 +#define IMX8QM_AUD_SAI_3_MCLK 198 +#define IMX8QM_AUD_SAI_6_IPG 199 +#define IMX8QM_AUD_SAI_6_IPG_S 200 +#define IMX8QM_AUD_SAI_6_MCLK 201 +#define IMX8QM_AUD_SAI_7_IPG 202 +#define IMX8QM_AUD_SAI_7_IPG_S 203 +#define IMX8QM_AUD_SAI_7_MCLK 204 +#define IMX8QM_AUD_SAI_HDMIRX0_IPG 205 +#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S 206 +#define IMX8QM_AUD_SAI_HDMIRX0_MCLK 207 +#define IMX8QM_AUD_SAI_HDMITX0_IPG 208 +#define IMX8QM_AUD_SAI_HDMITX0_IPG_S 209 +#define IMX8QM_AUD_SAI_HDMITX0_MCLK 210 +#define IMX8QM_AUD_MQS_IPG 211 +#define IMX8QM_AUD_MQS_HMCLK 212 +#define IMX8QM_AUD_GPT5_IPG_S 213 +#define IMX8QM_AUD_GPT5_CLKIN 214 +#define IMX8QM_AUD_GPT5_24M_CLK 215 +#define IMX8QM_AUD_GPT6_IPG_S 216 +#define IMX8QM_AUD_GPT6_CLKIN 217 +#define IMX8QM_AUD_GPT6_24M_CLK 218 +#define IMX8QM_AUD_GPT7_IPG_S 219 +#define IMX8QM_AUD_GPT7_CLKIN 220 +#define IMX8QM_AUD_GPT7_24M_CLK 221 +#define IMX8QM_AUD_GPT8_IPG_S 222 +#define IMX8QM_AUD_GPT8_CLKIN 223 +#define IMX8QM_AUD_GPT8_24M_CLK 224 +#define IMX8QM_AUD_GPT9_IPG_S 225 +#define IMX8QM_AUD_GPT9_CLKIN 226 +#define IMX8QM_AUD_GPT9_24M_CLK 227 +#define IMX8QM_AUD_GPT10_IPG_S 228 +#define IMX8QM_AUD_GPT10_CLKIN 229 +#define IMX8QM_AUD_GPT10_24M_CLK 230 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV 232 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK 233 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV 234 +#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK 235 +#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV 236 +#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK 237 +#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV 238 +#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK 239 +#define IMX8QM_AUD_MCLKOUT0 240 +#define IMX8QM_AUD_MCLKOUT1 241 +#define IMX8QM_AUD_SPDIF_0_TX_CLK 242 +#define IMX8QM_AUD_SPDIF_0_GCLKW 243 +#define IMX8QM_AUD_SPDIF_0_IPG_S 244 +#define IMX8QM_AUD_SPDIF_1_TX_CLK 245 +#define IMX8QM_AUD_SPDIF_1_GCLKW 246 +#define IMX8QM_AUD_SPDIF_1_IPG_S 247 +#define IMX8QM_AUD_ASRC_0_IPG 248 +#define IMX8QM_AUD_ASRC_0_MEM 249 +#define IMX8QM_AUD_ASRC_1_IPG 250 +#define IMX8QM_AUD_ASRC_1_MEM 251 + + +/* VPU */ +#define IMX8QM_VPU_CORE_DIV 252 +#define IMX8QM_VPU_CORE_CLK 253 +#define IMX8QM_VPU_UART_DIV 254 +#define IMX8QM_VPU_UART_CLK 255 +#define IMX8QM_VPU_DDR_DIV 256 +#define IMX8QM_VPU_DDR_CLK 257 +#define IMX8QM_VPU_SYS_DIV 258 +#define IMX8QM_VPU_SYS_CLK 259 +#define IMX8QM_VPU_XUVI_DIV 260 +#define IMX8QM_VPU_XUVI_CLK 261 + +/* GPU Clocks. */ +#define IMX8QM_GPU0_CORE_DIV 262 +#define IMX8QM_GPU0_CORE_CLK 263 +#define IMX8QM_GPU0_SHADER_DIV 264 +#define IMX8QM_GPU0_SHADER_CLK 265 +#define IMX8QM_GPU1_CORE_DIV 266 +#define IMX8QM_GPU1_CORE_CLK 267 +#define IMX8QM_GPU1_SHADER_DIV 268 +#define IMX8QM_GPU1_SHADER_CLK 269 + + +/* MIPI CSI */ +#define IMX8QM_CSI0_IPG_CLK_S 270 +#define IMX8QM_CSI0_LIS_IPG_CLK 271 +#define IMX8QM_CSI0_APB_CLK 272 +#define IMX8QM_CSI0_I2C0_DIV 273 +#define IMX8QM_CSI0_I2C0_CLK 274 +#define IMX8QM_CSI0_PWM0_DIV 275 +#define IMX8QM_CSI0_PWM0_CLK 276 +#define IMX8QM_CSI0_CORE_DIV 277 +#define IMX8QM_CSI0_CORE_CLK 278 +#define IMX8QM_CSI0_ESC_DIV 279 +#define IMX8QM_CSI0_ESC_CLK 280 +#define IMX8QM_CSI1_IPG_CLK_S 281 +#define IMX8QM_CSI1_LIS_IPG_CLK 282 +#define IMX8QM_CSI1_APB_CLK 283 +#define IMX8QM_CSI1_I2C0_DIV 284 +#define IMX8QM_CSI1_I2C0_CLK 285 +#define IMX8QM_CSI1_PWM0_DIV 286 +#define IMX8QM_CSI1_PWM0_CLK 287 +#define IMX8QM_CSI1_CORE_DIV 288 +#define IMX8QM_CSI1_CORE_CLK 289 +#define IMX8QM_CSI1_ESC_DIV 290 +#define IMX8QM_CSI1_ESC_CLK 291 + + +/* Display */ +#define IMX8QM_DC0_PLL0_DIV 292 +#define IMX8QM_DC0_PLL0_CLK 293 +#define IMX8QM_DC0_PLL1_DIV 294 +#define IMX8QM_DC0_PLL1_CLK 295 +#define IMX8QM_DC0_DISP0_DIV 296 +#define IMX8QM_DC0_DISP0_CLK 297 +#define IMX8QM_DC0_DISP1_DIV 298 +#define IMX8QM_DC0_DISP1_CLK 299 +#define IMX8QM_DC0_BYPASS_0_DIV 300 +#define IMX8QM_DC0_BYPASS_1_DIV 301 +#define IMX8QM_DC0_IRIS_AXI_CLK 302 +#define IMX8AM_DC0_IRIS_MVPL_CLK 303 +#define IMX8QM_DC0_DISP0_MSI_CLK 304 +#define IMX8QM_DC0_LIS_IPG_CLK 305 +#define IMX8QM_DC0_PXL_CMB_APB_CLK 306 +#define IMX8QM_DC0_PRG0_RTRAM_CLK 307 +#define IMX8QM_DC0_PRG1_RTRAM_CLK 308 +#define IMX8QM_DC0_PRG2_RTRAM_CLK 309 +#define IMX8QM_DC0_PRG3_RTRAM_CLK 310 +#define IMX8QM_DC0_PRG4_RTRAM_CLK 311 +#define IMX8QM_DC0_PRG5_RTRAM_CLK 312 +#define IMX8QM_DC0_PRG6_RTRAM_CLK 313 +#define IMX8QM_DC0_PRG7_RTRAM_CLK 314 +#define IMX8QM_DC0_PRG8_RTRAM_CLK 315 +#define IMX8QM_DC0_PRG0_APB_CLK 316 +#define IMX8QM_DC0_PRG1_APB_CLK 317 +#define IMX8QM_DC0_PRG2_APB_CLK 318 +#define IMX8QM_DC0_PRG3_APB_CLK 319 +#define IMX8QM_DC0_PRG4_APB_CLK 320 +#define IMX8QM_DC0_PRG5_APB_CLK 321 +#define IMX8QM_DC0_PRG6_APB_CLK 322 +#define IMX8QM_DC0_PRG7_APB_CLK 323 +#define IMX8QM_DC0_PRG8_APB_CLK 324 +#define IMX8QM_DC0_DPR0_APB_CLK 325 +#define IMX8QM_DC0_DPR1_APB_CLK 326 +#define IMX8QM_DC0_RTRAM0_CLK 327 +#define IMX8QM_DC0_RTRAM1_CLK 328 +#define IMX8QM_DC1_PLL0_DIV 329 +#define IMX8QM_DC1_PLL0_CLK 330 +#define IMX8QM_DC1_PLL1_DIV 331 +#define IMX8QM_DC1_PLL1_CLK 332 +#define IMX8QM_DC1_DISP0_DIV 333 +#define IMX8QM_DC1_DISP0_CLK 334 +#define IMX8QM_DC1_BYPASS_0_DIV 335 +#define IMX8QM_DC1_BYPASS_1_DIV 336 +#define IMX8QM_DC1_DISP1_DIV 337 +#define IMX8QM_DC1_DISP1_CLK 338 +#define IMX8QM_DC1_IRIS_AXI_CLK 339 +#define IMX8AM_DC1_IRIS_MVPL_CLK 340 +#define IMX8QM_DC1_DISP0_MSI_CLK 341 +#define IMX8QM_DC1_LIS_IPG_CLK 342 +#define IMX8QM_DC1_PXL_CMB_APB_CLK 343 +#define IMX8QM_DC1_PRG0_RTRAM_CLK 344 +#define IMX8QM_DC1_PRG1_RTRAM_CLK 345 +#define IMX8QM_DC1_PRG2_RTRAM_CLK 346 +#define IMX8QM_DC1_PRG3_RTRAM_CLK 347 +#define IMX8QM_DC1_PRG4_RTRAM_CLK 348 +#define IMX8QM_DC1_PRG5_RTRAM_CLK 349 +#define IMX8QM_DC1_PRG6_RTRAM_CLK 350 +#define IMX8QM_DC1_PRG7_RTRAM_CLK 351 +#define IMX8QM_DC1_PRG8_RTRAM_CLK 352 +#define IMX8QM_DC1_PRG0_APB_CLK 353 +#define IMX8QM_DC1_PRG1_APB_CLK 354 +#define IMX8QM_DC1_PRG2_APB_CLK 355 +#define IMX8QM_DC1_PRG3_APB_CLK 356 +#define IMX8QM_DC1_PRG4_APB_CLK 357 +#define IMX8QM_DC1_PRG5_APB_CLK 358 +#define IMX8QM_DC1_PRG6_APB_CLK 359 +#define IMX8QM_DC1_PRG7_APB_CLK 360 +#define IMX8QM_DC1_PRG8_APB_CLK 361 +#define IMX8QM_DC1_DPR0_APB_CLK 362 +#define IMX8QM_DC1_DPR1_APB_CLK 363 +#define IMX8QM_DC1_RTRAM0_CLK 364 +#define IMX8QM_DC1_RTRAM1_CLK 365 + +/* DRC */ +#define IMX8QM_DRC0_PLL0_DIV 366 +#define IMX8QM_DRC0_PLL0_CLK 367 +#define IMX8QM_DRC0_DIV 368 +#define IMX8QM_DRC0_CLK 369 +#define IMX8QM_DRC1_PLL0_DIV 370 +#define IMX8QM_DRC1_PLL0_CLK 371 +#define IMX8QM_DRC1_DIV 372 +#define IMX8QM_DRC1_CLK 373 + +/* HDMI */ +#define IMX8QM_HDMI_AV_PLL_DIV 374 +#define IMX8QM_HDMI_AV_PLL_CLK 375 +#define IMX8QM_HDMI_I2S_BYPASS_CLK 376 +#define IMX8QM_HDMI_I2C0_DIV 377 +#define IMX8QM_HDMI_I2C0_CLK 378 +#define IMX8QM_HDMI_PXL_DIV 379 +#define IMX8QM_HDMI_PXL_CLK 380 +#define IMX8QM_HDMI_PXL_LINK_DIV 381 +#define IMX8QM_HDMI_PXL_LINK_CLK 382 +#define IMX8QM_HDMI_PXL_MUX_DIV 383 +#define IMX8QM_HDMI_PXL_MUX_CLK 384 +#define IMX8QM_HDMI_I2S_DIV 385 +#define IMX8QM_HDMI_I2S_CLK 386 +#define IMX8QM_HDMI_HDP_CORE_DIV 387 +#define IMX8QM_HDMI_HDP_CORE_CLK 388 +#define IMX8QM_HDMI_I2C_IPG_S_CLK 389 +#define IMX8QM_HDMI_I2C_IPG_CLK 390 +#define IMX8QM_HDMI_PWM_IPG_S_CLK 391 +#define IMX8QM_HDMI_PWM_IPG_CLK 392 +#define IMX8QM_HDMI_PWM_32K_CLK 393 +#define IMX8QM_HDMI_GPIO_IPG_CLK 394 +#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK 395 +#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK 396 +#define IMX8QM_HDMI_LIS_IPG_CLK 397 +#define IMX8QM_HDMI_MSI_HCLK 398 +#define IMX8QM_HDMI_PXL_EVEN_CLK 399 +#define IMX8QM_HDMI_HDP_CLK 400 +#define IMX8QM_HDMI_PXL_DBL_CLK 401 +#define IMX8QM_HDMI_APB_CLK 402 +#define IMX8QM_HDMI_PXL_LPCG_CLK 403 +#define IMX8QM_HDMI_HDP_PHY_CLK 404 +#define IMX8QM_HDMI_IPG_DIV 405 +#define IMX8QM_HDMI_VIF_CLK 406 +#define IMX8QM_HDMI_DIG_PLL_DIV 407 +#define IMX8QM_HDMI_DIG_PLL_CLK 408 +#define IMX8QM_HDMI_APB_MUX_CSR_CLK 409 +#define IMX8QM_HDMI_APB_MUX_CTRL_CLK 410 + +/* RX-HDMI */ +#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK 411 +#define IMX8QM_HDMI_RX_BYPASS_CLK 412 +#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK 413 +#define IMX8QM_HDMI_RX_I2C0_DIV 414 +#define IMX8QM_HDMI_RX_I2C0_CLK 415 +#define IMX8QM_HDMI_RX_SPDIF_DIV 416 +#define IMX8QM_HDMI_RX_SPDIF_CLK 417 +#define IMX8QM_HDMI_RX_HD_REF_DIV 418 +#define IMX8QM_HDMI_RX_HD_REF_CLK 419 +#define IMX8QM_HDMI_RX_HD_CORE_DIV 420 +#define IMX8QM_HDMI_RX_HD_CORE_CLK 421 +#define IMX8QM_HDMI_RX_PXL_DIV 422 +#define IMX8QM_HDMI_RX_PXL_CLK 423 +#define IMX8QM_HDMI_RX_I2S_DIV 424 +#define IMX8QM_HDMI_RX_I2S_CLK 425 +#define IMX8QM_HDMI_RX_PWM_DIV 426 +#define IMX8QM_HDMI_RX_PWM_CLK 427 + +/* LVDS */ +#define IMX8QM_LVDS0_BYPASS_CLK 428 +#define IMX8QM_LVDS0_PIXEL_DIV 429 +#define IMX8QM_LVDS0_PIXEL_CLK 430 +#define IMX8QM_LVDS0_PHY_DIV 431 +#define IMX8QM_LVDS0_PHY_CLK 432 +#define IMX8QM_LVDS0_I2C0_IPG_CLK 433 +#define IMX8QM_LVDS0_I2C0_DIV 434 +#define IMX8QM_LVDS0_I2C0_CLK 435 +#define IMX8QM_LVDS0_I2C1_IPG_CLK 436 +#define IMX8QM_LVDS0_I2C1_DIV 437 +#define IMX8QM_LVDS0_I2C1_CLK 438 +#define IMX8QM_LVDS0_PWM0_IPG_CLK 439 +#define IMX8QM_LVDS0_PWM0_DIV 440 +#define IMX8QM_LVDS0_PWM0_CLK 441 +#define IMX8QM_LVDS0_GPIO_IPG_CLK 444 +#define IMX8QM_LVDS1_BYPASS_DIV 445 +#define IMX8QM_LVDS1_BYPASS_CLK 446 +#define IMX8QM_LVDS1_PIXEL_DIV 447 +#define IMX8QM_LVDS1_PIXEL_CLK 448 +#define IMX8QM_LVDS1_PHY_DIV 449 +#define IMX8QM_LVDS1_PHY_CLK 450 +#define IMX8QM_LVDS1_I2C0_IPG_CLK 451 +#define IMX8QM_LVDS1_I2C0_DIV 452 +#define IMX8QM_LVDS1_I2C0_CLK 453 +#define IMX8QM_LVDS1_I2C1_IPG_CLK 454 +#define IMX8QM_LVDS1_I2C1_DIV 455 +#define IMX8QM_LVDS1_I2C1_CLK 456 +#define IMX8QM_LVDS1_PWM0_IPG_CLK 457 +#define IMX8QM_LVDS1_PWM0_DIV 458 +#define IMX8QM_LVDS1_PWM0_CLK 459 +#define IMX8QM_LVDS1_GPIO_IPG_CLK 462 + +/* MIPI */ +#define IMX8QM_MIPI0_BYPASS_CLK 465 +#define IMX8QM_MIPI0_I2C0_DIV 466 +#define IMX8QM_MIPI0_I2C0_CLK 467 +#define IMX8QM_MIPI0_I2C1_DIV 468 +#define IMX8QM_MIPI0_I2C1_CLK 469 +#define IMX8QM_MIPI0_PWM0_DIV 470 +#define IMX8QM_MIPI0_PWM0_CLK 471 +#define IMX8QM_MIPI0_DSI_TX_ESC_DIV 472 +#define IMX8QM_MIPI0_DSI_TX_ESC_CLK 473 +#define IMX8QM_MIPI0_DSI_RX_ESC_DIV 474 +#define IMX8QM_MIPI0_DSI_RX_ESC_CLK 475 +#define IMX8QM_MIPI0_PXL_DIV 476 +#define IMX8QM_MIPI0_PXL_CLK 477 +#define IMX8QM_MIPI1_BYPASS_CLK 479 +#define IMX8QM_MIPI1_I2C0_DIV 480 +#define IMX8QM_MIPI1_I2C0_CLK 481 +#define IMX8QM_MIPI1_I2C1_DIV 482 +#define IMX8QM_MIPI1_I2C1_CLK 483 +#define IMX8QM_MIPI1_PWM0_DIV 484 +#define IMX8QM_MIPI1_PWM0_CLK 485 +#define IMX8QM_MIPI1_DSI_TX_ESC_DIV 486 +#define IMX8QM_MIPI1_DSI_TX_ESC_CLK 487 +#define IMX8QM_MIPI1_DSI_RX_ESC_DIV 488 +#define IMX8QM_MIPI1_DSI_RX_ESC_CLK 489 +#define IMX8QM_MIPI1_PXL_DIV 490 +#define IMX8QM_MIPI1_PXL_CLK 491 + +/* Imaging */ +#define IMX8QM_IMG_JPEG_ENC_IPG_CLK 492 +#define IMX8QM_IMG_JPEG_ENC_CLK 493 +#define IMX8QM_IMG_JPEG_DEC_IPG_CLK 494 +#define IMX8QM_IMG_JPEG_DEC_CLK 495 +#define IMX8QM_IMG_PXL_LINK_DC0_CLK 496 +#define IMX8QM_IMG_PXL_LINK_DC1_CLK 497 +#define IMX8QM_IMG_PXL_LINK_CSI0_CLK 498 +#define IMX8QM_IMG_PXL_LINK_CSI1_CLK 499 +#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK 500 +#define IMX8QM_IMG_PDMA_0_CLK 501 +#define IMX8QM_IMG_PDMA_1_CLK 502 +#define IMX8QM_IMG_PDMA_2_CLK 503 +#define IMX8QM_IMG_PDMA_3_CLK 504 +#define IMX8QM_IMG_PDMA_4_CLK 505 +#define IMX8QM_IMG_PDMA_5_CLK 506 +#define IMX8QM_IMG_PDMA_6_CLK 507 +#define IMX8QM_IMG_PDMA_7_CLK 508 + +/* HSIO */ +#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK 509 +#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK 510 +#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK 511 +#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK 512 +#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK 513 +#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK 514 +#define IMX8QM_HSIO_PCIE_X1_PER_CLK 515 +#define IMX8QM_HSIO_PCIE_X2_PER_CLK 516 +#define IMX8QM_HSIO_SATA_PER_CLK 517 +#define IMX8QM_HSIO_PHY_X1_PER_CLK 518 +#define IMX8QM_HSIO_PHY_X2_PER_CLK 519 +#define IMX8QM_HSIO_MISC_PER_CLK 520 +#define IMX8QM_HSIO_PHY_X1_APB_CLK 521 +#define IMX8QM_HSIO_PHY_X2_APB_0_CLK 522 +#define IMX8QM_HSIO_PHY_X2_APB_1_CLK 523 +#define IMX8QM_HSIO_SATA_CLK 524 +#define IMX8QM_HSIO_GPIO_CLK 525 +#define IMX8QM_HSIO_PHY_X1_PCLK 526 +#define IMX8QM_HSIO_PHY_X2_PCLK_0 527 +#define IMX8QM_HSIO_PHY_X2_PCLK_1 528 +#define IMX8QM_HSIO_SATA_EPCS_RX_CLK 529 +#define IMX8QM_HSIO_SATA_EPCS_TX_CLK 530 + + +/* M4 */ +#define IMX8QM_M4_0_CORE_DIV 531 +#define IMX8QM_M4_0_CORE_CLK 532 +#define IMX8QM_M4_0_I2C_DIV 533 +#define IMX8QM_M4_0_I2C_CLK 534 +#define IMX8QM_M4_0_PIT_DIV 535 +#define IMX8QM_M4_0_PIT_CLK 536 +#define IMX8QM_M4_0_TPM_DIV 537 +#define IMX8QM_M4_0_TPM_CLK 538 +#define IMX8QM_M4_0_UART_DIV 539 +#define IMX8QM_M4_0_UART_CLK 540 +#define IMX8QM_M4_0_WDOG_DIV 541 +#define IMX8QM_M4_0_WDOG_CLK 542 +#define IMX8QM_M4_1_CORE_DIV 543 +#define IMX8QM_M4_1_CORE_CLK 544 +#define IMX8QM_M4_1_I2C_DIV 545 +#define IMX8QM_M4_1_I2C_CLK 546 +#define IMX8QM_M4_1_PIT_DIV 547 +#define IMX8QM_M4_1_PIT_CLK 548 +#define IMX8QM_M4_1_TPM_DIV 549 +#define IMX8QM_M4_1_TPM_CLK 550 +#define IMX8QM_M4_1_UART_DIV 551 +#define IMX8QM_M4_1_UART_CLK 552 +#define IMX8QM_M4_1_WDOG_DIV 553 +#define IMX8QM_M4_1_WDOG_CLK 554 + +/* IPG clocks */ +#define IMX8QM_24MHZ 555 +#define IMX8QM_GPT_3M 556 +#define IMX8QM_IPG_DMA_CLK_ROOT 557 +#define IMX8QM_IPG_AUD_CLK_ROOT 558 +#define IMX8QM_IPG_CONN_CLK_ROOT 559 +#define IMX8QM_AHB_CONN_CLK_ROOT 560 +#define IMX8QM_AXI_CONN_CLK_ROOT 561 +#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT 562 +#define IMX8QM_DC_AXI_EXT_CLK 563 +#define IMX8QM_DC_AXI_INT_CLK 564 +#define IMX8QM_DC_CFG_CLK 565 +#define IMX8QM_HDMI_IPG_CLK 566 +#define IMX8QM_LVDS_IPG_CLK 567 +#define IMX8QM_IMG_AXI_CLK 568 +#define IMX8QM_IMG_IPG_CLK 569 +#define IMX8QM_IMG_PXL_CLK 570 +#define IMX8QM_CSI0_I2C0_IPG_CLK 571 +#define IMX8QM_CSI0_PWM0_IPG_CLK 572 +#define IMX8QM_CSI1_I2C0_IPG_CLK 573 +#define IMX8QM_CSI1_PWM0_IPG_CLK 574 +#define IMX8QM_DC0_DPR0_B_CLK 575 +#define IMX8QM_DC0_DPR1_B_CLK 576 +#define IMX8QM_DC1_DPR0_B_CLK 577 +#define IMX8QM_DC1_DPR1_B_CLK 578 +#define IMX8QM_32KHZ 579 +#define IMX8QM_HSIO_AXI_CLK 580 +#define IMX8QM_HSIO_PER_CLK 581 +#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK 582 +#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK 583 +#define IMX8QM_HDMI_RX_PWM_IPG_CLK 584 +#define IMX8QM_HDMI_RX_I2C_DIV_CLK 585 +#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK 586 +#define IMX8QM_HDMI_RX_I2C_IPG_CLK 587 +#define IMX8QM_HDMI_RX_SINK_PCLK 588 +#define IMX8QM_HDMI_RX_SINK_SCLK 589 +#define IMX8QM_HDMI_RX_PXL_ENC_CLK 590 +#define IMX8QM_HDMI_RX_IPG_CLK 591 + +/* ACM */ +#define IMX8QM_HDMI_RX_MCLK 592 +#define IMX8QM_EXT_AUD_MCLK0 593 +#define IMX8QM_EXT_AUD_MCLK1 594 +#define IMX8QM_ESAI0_RX_CLK 595 +#define IMX8QM_ESAI0_RX_HF_CLK 596 +#define IMX8QM_ESAI0_TX_CLK 597 +#define IMX8QM_ESAI0_TX_HF_CLK 598 +#define IMX8QM_ESAI1_RX_CLK 599 +#define IMX8QM_ESAI1_RX_HF_CLK 600 +#define IMX8QM_ESAI1_TX_CLK 601 +#define IMX8QM_ESAI1_TX_HF_CLK 602 +#define IMX8QM_SPDIF0_RX 603 +#define IMX8QM_SPDIF1_RX 604 +#define IMX8QM_SAI0_RX_BCLK 605 +#define IMX8QM_SAI0_TX_BCLK 606 +#define IMX8QM_SAI1_RX_BCLK 607 +#define IMX8QM_SAI1_TX_BCLK 608 +#define IMX8QM_SAI2_RX_BCLK 609 +#define IMX8QM_SAI3_RX_BCLK 610 +#define IMX8QM_HDMI_RX_SAI0_RX_BCLK 611 +#define IMX8QM_SAI6_RX_BCLK 612 +#define IMX8QM_HDMI_TX_SAI0_TX_BCLK 613 + +#define IMX8QM_ACM_AUD_CLK0_SEL 614 +#define IMX8QM_ACM_AUD_CLK1_SEL 616 +#define IMX8QM_ACM_MCLKOUT0_SEL 618 +#define IMX8QM_ACM_MCLKOUT0_CLK 619 +#define IMX8QM_ACM_MCLKOUT1_SEL 620 +#define IMX8QM_ACM_MCLKOUT1_CLK 621 +#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL 622 +#define IMX8QM_ACM_ESAI0_MCLK_SEL 626 +#define IMX8QM_ACM_ESAI0_MCLK_CLK 627 +#define IMX8QM_ACM_ESAI1_MCLK_SEL 628 +#define IMX8QM_ACM_ESAI1_MCLK_CLK 629 +#define IMX8QM_ACM_GPT0_MUX_CLK_SEL 630 +#define IMX8QM_ACM_GPT0_MUX_CLK_CLK 631 +#define IMX8QM_ACM_GPT1_MUX_CLK_SEL 632 +#define IMX8QM_ACM_GPT1_MUX_CLK_CLK 633 +#define IMX8QM_ACM_GPT2_MUX_CLK_SEL 634 +#define IMX8QM_ACM_GPT2_MUX_CLK_CLK 635 +#define IMX8QM_ACM_GPT3_MUX_CLK_SEL 636 +#define IMX8QM_ACM_GPT3_MUX_CLK_CLK 637 +#define IMX8QM_ACM_GPT4_MUX_CLK_SEL 638 +#define IMX8QM_ACM_GPT4_MUX_CLK_CLK 639 +#define IMX8QM_ACM_GPT5_MUX_CLK_SEL 640 +#define IMX8QM_ACM_GPT5_MUX_CLK_CLK 641 +#define IMX8QM_ACM_SAI0_MCLK_SEL 642 +#define IMX8QM_ACM_SAI0_MCLK_CLK 643 +#define IMX8QM_ACM_SAI1_MCLK_SEL 644 +#define IMX8QM_ACM_SAI1_MCLK_CLK 645 +#define IMX8QM_ACM_SAI2_MCLK_SEL 646 +#define IMX8QM_ACM_SAI2_MCLK_CLK 647 +#define IMX8QM_ACM_SAI3_MCLK_SEL 648 +#define IMX8QM_ACM_SAI3_MCLK_CLK 649 +#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL 650 +#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK 651 +#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL 652 +#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK 653 +#define IMX8QM_ACM_SAI6_MCLK_SEL 654 +#define IMX8QM_ACM_SAI6_MCLK_CLK 655 +#define IMX8QM_ACM_SAI7_MCLK_SEL 656 +#define IMX8QM_ACM_SAI7_MCLK_CLK 657 +#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL 658 +#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK 659 +#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL 660 +#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK 661 +#define IMX8QM_ACM_MQS_TX_CLK_SEL 662 +#define IMX8QM_ACM_MQS_TX_CLK_CLK 663 + +#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL 664 +#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK 665 +#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL 666 +#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK 667 +#define IMX8QM_ENET0_REF_50MHZ_CLK 668 +#define IMX8QM_ENET1_REF_50MHZ_CLK 669 +#define IMX8QM_ENET_25MHZ_CLK 670 +#define IMX8QM_ENET_125MHZ_CLK 671 +#define IMX8QM_ENET0_REF_DIV 672 +#define IMX8QM_ENET0_REF_CLK 673 +#define IMX8QM_ENET1_REF_DIV 674 +#define IMX8QM_ENET1_REF_CLK 675 +#define IMX8QM_ENET0_RMII_TX_CLK 676 +#define IMX8QM_ENET1_RMII_TX_CLK 677 +#define IMX8QM_ENET0_RMII_TX_SEL 678 +#define IMX8QM_ENET1_RMII_TX_SEL 679 +#define IMX8QM_ENET0_RMII_RX_CLK 680 +#define IMX8QM_ENET1_RMII_RX_CLK 681 + +#define IMX8QM_KPP_CLK 683 +#define IMX8QM_GPT0_HF_CLK 684 +#define IMX8QM_GPT0_IPG_S_CLK 685 +#define IMX8QM_GPT0_IPG_SLV_CLK 686 +#define IMX8QM_GPT0_IPG_MSTR_CLK 687 +#define IMX8QM_GPT1_HF_CLK 688 +#define IMX8QM_GPT1_IPG_S_CLK 689 +#define IMX8QM_GPT1_IPG_SLV_CLK 690 +#define IMX8QM_GPT1_IPG_MSTR_CLK 691 +#define IMX8QM_GPT2_HF_CLK 692 +#define IMX8QM_GPT2_IPG_S_CLK 693 +#define IMX8QM_GPT2_IPG_SLV_CLK 694 +#define IMX8QM_GPT2_IPG_MSTR_CLK 695 +#define IMX8QM_GPT3_HF_CLK 696 +#define IMX8QM_GPT3_IPG_S_CLK 697 +#define IMX8QM_GPT3_IPG_SLV_CLK 698 +#define IMX8QM_GPT3_IPG_MSTR_CLK 699 +#define IMX8QM_GPT4_HF_CLK 700 +#define IMX8QM_GPT4_IPG_S_CLK 701 +#define IMX8QM_GPT4_IPG_SLV_CLK 702 +#define IMX8QM_GPT4_IPG_MSTR_CLK 703 +#define IMX8QM_PWM0_HF_CLK 704 +#define IMX8QM_PWM0_IPG_S_CLK 705 +#define IMX8QM_PWM0_IPG_SLV_CLK 706 +#define IMX8QM_PWM0_IPG_MSTR_CLK 707 +#define IMX8QM_PWM1_HF_CLK 708 +#define IMX8QM_PWM1_IPG_S_CLK 709 +#define IMX8QM_PWM1_IPG_SLV_CLK 710 +#define IMX8QM_PWM1_IPG_MSTR_CLK 711 +#define IMX8QM_PWM2_HF_CLK 712 +#define IMX8QM_PWM2_IPG_S_CLK 713 +#define IMX8QM_PWM2_IPG_SLV_CLK 714 +#define IMX8QM_PWM2_IPG_MSTR_CLK 715 +#define IMX8QM_PWM3_HF_CLK 716 +#define IMX8QM_PWM3_IPG_S_CLK 717 +#define IMX8QM_PWM3_IPG_SLV_CLK 718 +#define IMX8QM_PWM3_IPG_MSTR_CLK 719 +#define IMX8QM_PWM4_HF_CLK 720 +#define IMX8QM_PWM4_IPG_S_CLK 721 +#define IMX8QM_PWM4_IPG_SLV_CLK 722 +#define IMX8QM_PWM4_IPG_MSTR_CLK 723 +#define IMX8QM_PWM5_HF_CLK 724 +#define IMX8QM_PWM5_IPG_S_CLK 725 +#define IMX8QM_PWM5_IPG_SLV_CLK 726 +#define IMX8QM_PWM5_IPG_MSTR_CLK 727 +#define IMX8QM_PWM6_HF_CLK 728 +#define IMX8QM_PWM6_IPG_S_CLK 729 +#define IMX8QM_PWM6_IPG_SLV_CLK 730 +#define IMX8QM_PWM6_IPG_MSTR_CLK 731 +#define IMX8QM_PWM7_HF_CLK 732 +#define IMX8QM_PWM7_IPG_S_CLK 733 +#define IMX8QM_PWM7_IPG_SLV_CLK 734 +#define IMX8QM_PWM7_IPG_MSTR_CLK 735 +#define IMX8QM_FSPI0_HCLK 736 +#define IMX8QM_FSPI0_IPG_CLK 737 +#define IMX8QM_FSPI0_IPG_S_CLK 738 +#define IMX8QM_FSPI1_HCLK 736 +#define IMX8QM_FSPI1_IPG_CLK 737 +#define IMX8QM_FSPI1_IPG_S_CLK 738 +#define IMX8QM_GPIO0_IPG_S_CLK 739 +#define IMX8QM_GPIO1_IPG_S_CLK 740 +#define IMX8QM_GPIO2_IPG_S_CLK 741 +#define IMX8QM_GPIO3_IPG_S_CLK 742 +#define IMX8QM_GPIO4_IPG_S_CLK 743 +#define IMX8QM_GPIO5_IPG_S_CLK 744 +#define IMX8QM_GPIO6_IPG_S_CLK 745 +#define IMX8QM_GPIO7_IPG_S_CLK 746 +#define IMX8QM_ROMCP_CLK 747 +#define IMX8QM_ROMCP_REG_CLK 748 +#define IMX8QM_96KROM_CLK 749 +#define IMX8QM_OCRAM_MEM_CLK 750 +#define IMX8QM_OCRAM_CTRL_CLK 751 +#define IMX8QM_LSIO_BUS_CLK 752 +#define IMX8QM_LSIO_MEM_CLK 753 +#define IMX8QM_LVDS0_LIS_IPG_CLK 754 +#define IMX8QM_LVDS1_LIS_IPG_CLK 755 +#define IMX8QM_MIPI0_LIS_IPG_CLK 756 +#define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757 +#define IMX8QM_MIPI0_I2C0_IPG_CLK 758 +#define IMX8QM_MIPI0_I2C1_IPG_S_CLK 759 +#define IMX8QM_MIPI0_I2C1_IPG_CLK 760 +#define IMX8QM_MIPI0_CLK_ROOT 761 +#define IMX8QM_MIPI1_LIS_IPG_CLK 762 +#define IMX8QM_MIPI1_I2C0_IPG_S_CLK 763 +#define IMX8QM_MIPI1_I2C0_IPG_CLK 764 +#define IMX8QM_MIPI1_I2C1_IPG_S_CLK 765 +#define IMX8QM_MIPI1_I2C1_IPG_CLK 766 +#define IMX8QM_MIPI1_CLK_ROOT 767 +#define IMX8QM_DC0_DISP0_SEL 768 +#define IMX8QM_DC0_DISP1_SEL 769 +#define IMX8QM_DC1_DISP0_SEL 770 +#define IMX8QM_DC1_DISP1_SEL 771 + +/* CM40 */ +#define IMX8QM_CM40_IPG_CLK 772 +#define IMX8QM_CM40_I2C_DIV 773 +#define IMX8QM_CM40_I2C_CLK 774 +#define IMX8QM_CM40_I2C_IPG_CLK 775 + +/* CM41 */ +#define IMX8QM_CM41_IPG_CLK 776 +#define IMX8QM_CM41_I2C_DIV 777 +#define IMX8QM_CM41_I2C_CLK 778 +#define IMX8QM_CM41_I2C_IPG_CLK 779 + +#define IMX8QM_HDMI_PXL_SEL 780 +#define IMX8QM_HDMI_PXL_LINK_SEL 781 +#define IMX8QM_HDMI_PXL_MUX_SEL 782 +#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK 783 + +#define IMX8QM_HDMI_RX_PXL_SEL 784 +#define IMX8QM_HDMI_RX_HD_REF_SEL 785 +#define IMX8QM_HDMI_RX_HD_CORE_SEL 786 +#define IMX8QM_HDMI_RX_DIG_PLL_CLK 787 + +#define IMX8QM_LSIO_MU5A_IPG_S_CLK 788 +#define IMX8QM_LSIO_MU5A_IPG_CLK 789 +#define IMX8QM_LSIO_MU6A_IPG_S_CLK 790 +#define IMX8QM_LSIO_MU6A_IPG_CLK 791 + +/* DSP */ +#define IMX8QM_AUD_DSP_ADB_ACLK 792 +#define IMX8QM_AUD_DSP_IPG 793 +#define IMX8QM_AUD_DSP_CORE_CLK 794 +#define IMX8QM_AUD_OCRAM_IPG 795 + +/* MIPI DSI */ +#define IMX8QM_MIPI0_DSI_PHY_DIV 796 +#define IMX8QM_MIPI0_DSI_PHY_CLK 797 +#define IMX8QM_MIPI1_DSI_PHY_DIV 798 +#define IMX8QM_MIPI1_DSI_PHY_CLK 799 + +#define IMX8QM_CLK_END 800 + +#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */ diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h new file mode 100644 index 000000000000..9eaf644ac7e3 --- /dev/null +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -0,0 +1,591 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H +#define __DT_BINDINGS_CLOCK_IMX8QXP_H + +#define IMX8QXP_CLK_DUMMY 0 + +#define IMX8QXP_UART0_IPG_CLK 1 +#define IMX8QXP_UART0_DIV 2 +#define IMX8QXP_UART0_CLK 3 + +#define IMX8QXP_IPG_DMA_CLK_ROOT 4 + +/* GPU Clocks. */ +#define IMX8QXP_GPU0_CORE_DIV 5 +#define IMX8QXP_GPU0_CORE_CLK 6 +#define IMX8QXP_GPU0_SHADER_DIV 7 +#define IMX8QXP_GPU0_SHADER_CLK 8 + +#define IMX8QXP_24MHZ 9 +#define IMX8QXP_GPT_3M 10 +#define IMX8QXP_32KHZ 11 + +/* LSIO SS */ +#define IMX8QXP_LSIO_MEM_CLK 12 +#define IMX8QXP_LSIO_BUS_CLK 13 +#define IMX8QXP_LSIO_PWM0_DIV 14 +#define IMX8QXP_LSIO_PWM0_IPG_S_CLK 15 +#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16 +#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17 +#define IMX8QXP_LSIO_PWM0_HF_CLK 18 +#define IMX8QXP_LSIO_PWM0_CLK 19 +#define IMX8QXP_LSIO_PWM1_DIV 20 +#define IMX8QXP_LSIO_PWM1_IPG_S_CLK 21 +#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22 +#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23 +#define IMX8QXP_LSIO_PWM1_HF_CLK 24 +#define IMX8QXP_LSIO_PWM1_CLK 25 +#define IMX8QXP_LSIO_PWM2_DIV 26 +#define IMX8QXP_LSIO_PWM2_IPG_S_CLK 27 +#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_PWM2_HF_CLK 30 +#define IMX8QXP_LSIO_PWM2_CLK 31 +#define IMX8QXP_LSIO_PWM3_DIV 32 +#define IMX8QXP_LSIO_PWM3_IPG_S_CLK 33 +#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34 +#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35 +#define IMX8QXP_LSIO_PWM3_HF_CLK 36 +#define IMX8QXP_LSIO_PWM3_CLK 37 +#define IMX8QXP_LSIO_PWM4_DIV 38 +#define IMX8QXP_LSIO_PWM4_IPG_S_CLK 39 +#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40 +#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42 +#define IMX8QXP_LSIO_PWM4_HF_CLK 43 +#define IMX8QXP_LSIO_PWM4_CLK 44 +#define IMX8QXP_LSIO_PWM5_DIV 45 +#define IMX8QXP_LSIO_PWM5_IPG_S_CLK 46 +#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47 +#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48 +#define IMX8QXP_LSIO_PWM5_HF_CLK 49 +#define IMX8QXP_LSIO_PWM5_CLK 50 +#define IMX8QXP_LSIO_PWM6_DIV 51 +#define IMX8QXP_LSIO_PWM6_IPG_S_CLK 52 +#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_PWM6_HF_CLK 55 +#define IMX8QXP_LSIO_PWM6_CLK 56 +#define IMX8QXP_LSIO_PWM7_DIV 57 +#define IMX8QXP_LSIO_PWM7_IPG_S_CLK 58 +#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59 +#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60 +#define IMX8QXP_LSIO_PWM7_HF_CLK 61 +#define IMX8QXP_LSIO_PWM7_CLK 62 +#define IMX8QXP_LSIO_GPT0_DIV 63 +#define IMX8QXP_LSIO_GPT0_IPG_S_CLK 64 +#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK 65 +#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK 66 +#define IMX8QXP_LSIO_GPT0_HF_CLK 67 +#define IMX8QXP_LSIO_GPT0_CLK 68 +#define IMX8QXP_LSIO_GPT1_DIV 69 +#define IMX8QXP_LSIO_GPT1_IPG_S_CLK 70 +#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK 71 +#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK 72 +#define IMX8QXP_LSIO_GPT1_HF_CLK 73 +#define IMX8QXP_LSIO_GPT1_CLK 74 +#define IMX8QXP_LSIO_GPT2_DIV 75 +#define IMX8QXP_LSIO_GPT2_IPG_S_CLK 76 +#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK 77 +#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK 78 +#define IMX8QXP_LSIO_GPT2_HF_CLK 79 +#define IMX8QXP_LSIO_GPT2_CLK 80 +#define IMX8QXP_LSIO_GPT3_DIV 81 +#define IMX8QXP_LSIO_GPT3_IPG_S_CLK 82 +#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK 83 +#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK 84 +#define IMX8QXP_LSIO_GPT3_HF_CLK 85 +#define IMX8QXP_LSIO_GPT3_CLK 86 +#define IMX8QXP_LSIO_GPT4_DIV 87 +#define IMX8QXP_LSIO_GPT4_IPG_S_CLK 88 +#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK 89 +#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK 90 +#define IMX8QXP_LSIO_GPT4_HF_CLK 91 +#define IMX8QXP_LSIO_GPT4_CLK 92 +#define IMX8QXP_LSIO_FSPI0_DIV 93 +#define IMX8QXP_LSIO_FSPI0_HCLK 94 +#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK 95 +#define IMX8QXP_LSIO_FSPI0_IPG_CLK 96 +#define IMX8QXP_LSIO_FSPI0_CLK 97 +#define IMX8QXP_LSIO_FSPI1_DIV 98 +#define IMX8QXP_LSIO_FSPI1_HCLK 99 +#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK 100 +#define IMX8QXP_LSIO_FSPI1_IPG_CLK 101 +#define IMX8QXP_LSIO_FSPI1_CLK 102 +#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK 103 +#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK 104 +#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK 105 +#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK 106 +#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK 107 +#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK 108 +#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK 109 +#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK 110 +#define IMX8QXP_LSIO_ROMCP_REG_CLK 111 +#define IMX8QXP_LSIO_ROMCP_CLK 112 +#define IMX8QXP_LSIO_96KROM_CLK 113 +#define IMX8QXP_LSIO_OCRAM_MEM_CLK 114 +#define IMX8QXP_LSIO_OCRAM_CTRL_CLK 115 + +/* ADMA SS */ +#define IMX8QXP_UART1_IPG_CLK 116 +#define IMX8QXP_UART2_IPG_CLK 117 +#define IMX8QXP_UART3_IPG_CLK 118 +#define IMX8QXP_UART1_DIV 119 +#define IMX8QXP_UART2_DIV 120 +#define IMX8QXP_UART3_DIV 121 +#define IMX8QXP_UART1_CLK 122 +#define IMX8QXP_UART2_CLK 123 +#define IMX8QXP_UART3_CLK 124 +#define IMX8QXP_SPI0_IPG_CLK 125 +#define IMX8QXP_SPI1_IPG_CLK 126 +#define IMX8QXP_SPI2_IPG_CLK 127 +#define IMX8QXP_SPI3_IPG_CLK 128 +#define IMX8QXP_SPI0_DIV 129 +#define IMX8QXP_SPI1_DIV 130 +#define IMX8QXP_SPI2_DIV 131 +#define IMX8QXP_SPI3_DIV 132 +#define IMX8QXP_SPI0_CLK 133 +#define IMX8QXP_SPI1_CLK 134 +#define IMX8QXP_SPI2_CLK 135 +#define IMX8QXP_SPI3_CLK 136 +#define IMX8QXP_CAN0_IPG_CHI_CLK 137 +#define IMX8QXP_CAN1_IPG_CHI_CLK 138 +#define IMX8QXP_CAN2_IPG_CHI_CLK 139 +#define IMX8QXP_CAN0_IPG_CLK 140 +#define IMX8QXP_CAN1_IPG_CLK 141 +#define IMX8QXP_CAN2_IPG_CLK 142 +#define IMX8QXP_CAN0_DIV 143 +#define IMX8QXP_CAN1_DIV 144 +#define IMX8QXP_CAN2_DIV 145 +#define IMX8QXP_CAN0_CLK 146 +#define IMX8QXP_CAN1_CLK 147 +#define IMX8QXP_CAN2_CLK 148 +#define IMX8QXP_I2C0_IPG_CLK 149 +#define IMX8QXP_I2C1_IPG_CLK 150 +#define IMX8QXP_I2C2_IPG_CLK 151 +#define IMX8QXP_I2C3_IPG_CLK 152 +#define IMX8QXP_I2C0_DIV 153 +#define IMX8QXP_I2C1_DIV 154 +#define IMX8QXP_I2C2_DIV 155 +#define IMX8QXP_I2C3_DIV 156 +#define IMX8QXP_I2C0_CLK 157 +#define IMX8QXP_I2C1_CLK 158 +#define IMX8QXP_I2C2_CLK 159 +#define IMX8QXP_I2C3_CLK 160 +#define IMX8QXP_FTM0_IPG_CLK 161 +#define IMX8QXP_FTM1_IPG_CLK 162 +#define IMX8QXP_FTM0_DIV 163 +#define IMX8QXP_FTM1_DIV 164 +#define IMX8QXP_FTM0_CLK 165 +#define IMX8QXP_FTM1_CLK 166 +#define IMX8QXP_ADC0_IPG_CLK 167 +#define IMX8QXP_ADC0_DIV 168 +#define IMX8QXP_ADC0_CLK 169 +#define IMX8QXP_PWM_IPG_CLK 170 +#define IMX8QXP_PWM_DIV 171 +#define IMX8QXP_PWM_CLK 172 +#define IMX8QXP_LCD_IPG_CLK 173 +#define IMX8QXP_LCD_DIV 174 +#define IMX8QXP_LCD_CLK 175 + +/* Connectivity SS */ +#define IMX8QXP_AXI_CONN_CLK_ROOT 176 +#define IMX8QXP_AHB_CONN_CLK_ROOT 177 +#define IMX8QXP_IPG_CONN_CLK_ROOT 178 +#define IMX8QXP_SDHC0_IPG_CLK 179 +#define IMX8QXP_SDHC1_IPG_CLK 180 +#define IMX8QXP_SDHC2_IPG_CLK 181 +#define IMX8QXP_SDHC0_DIV 182 +#define IMX8QXP_SDHC1_DIV 183 +#define IMX8QXP_SDHC2_DIV 184 +#define IMX8QXP_SDHC0_CLK 185 +#define IMX8QXP_SDHC1_CLK 186 +#define IMX8QXP_SDHC2_CLK 187 +#define IMX8QXP_ENET0_ROOT_DIV 188 +#define IMX8QXP_ENET0_REF_DIV 189 +#define IMX8QXP_ENET1_REF_DIV 190 +#define IMX8QXP_ENET0_BYPASS_DIV 191 +#define IMX8QXP_ENET0_RGMII_DIV 192 +#define IMX8QXP_ENET1_ROOT_DIV 193 +#define IMX8QXP_ENET1_BYPASS_DIV 194 +#define IMX8QXP_ENET1_RGMII_DIV 195 +#define IMX8QXP_ENET0_AHB_CLK 196 +#define IMX8QXP_ENET0_IPG_S_CLK 197 +#define IMX8QXP_ENET0_IPG_CLK 198 +#define IMX8QXP_ENET1_AHB_CLK 199 +#define IMX8QXP_ENET1_IPG_S_CLK 200 +#define IMX8QXP_ENET1_IPG_CLK 201 +#define IMX8QXP_ENET0_ROOT_CLK 202 +#define IMX8QXP_ENET1_ROOT_CLK 203 +#define IMX8QXP_ENET0_TX_CLK 204 +#define IMX8QXP_ENET1_TX_CLK 205 +#define IMX8QXP_ENET0_PTP_CLK 206 +#define IMX8QXP_ENET1_PTP_CLK 207 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL 208 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL 209 +#define IMX8QXP_ENET0_RMII_TX_SEL 210 +#define IMX8QXP_ENET1_RMII_TX_SEL 211 +#define IMX8QXP_ENET0_RGMII_TX_CLK 212 +#define IMX8QXP_ENET1_RGMII_TX_CLK 213 +#define IMX8QXP_ENET0_RMII_RX_CLK 214 +#define IMX8QXP_ENET1_RMII_RX_CLK 215 +#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK 216 +#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK 217 +#define IMX8QXP_ENET0_REF_50MHZ_CLK 218 +#define IMX8QXP_ENET1_REF_50MHZ_CLK 219 +#define IMX8QXP_GPMI_BCH_IO_DIV 220 +#define IMX8QXP_GPMI_BCH_DIV 221 +#define IMX8QXP_GPMI_APB_CLK 222 +#define IMX8QXP_GPMI_APB_BCH_CLK 223 +#define IMX8QXP_GPMI_BCH_IO_CLK 224 +#define IMX8QXP_GPMI_BCH_CLK 225 +#define IMX8QXP_APBHDMA_CLK 226 +#define IMX8QXP_USB3_ACLK_DIV 227 +#define IMX8QXP_USB3_BUS_DIV 228 +#define IMX8QXP_USB3_LPM_DIV 229 +#define IMX8QXP_USB3_IPG_CLK 230 +#define IMX8QXP_USB3_CORE_PCLK 231 +#define IMX8QXP_USB3_PHY_CLK 232 +#define IMX8QXP_USB3_ACLK 233 +#define IMX8QXP_USB3_BUS_CLK 234 +#define IMX8QXP_USB3_LPM_CLK 235 +#define IMX8QXP_USB2_OH_AHB_CLK 236 +#define IMX8QXP_USB2_OH_IPG_S_CLK 237 +#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK 238 +#define IMX8QXP_USB2_PHY_IPG_CLK 239 +#define IMX8QXP_EDMA_CLK 240 +#define IMX8QXP_EDMA_IPG_CLK 241 +#define IMX8QXP_MLB_HCLK 242 +#define IMX8QXP_MLB_CLK 243 +#define IMX8QXP_MLB_IPG_CLK 244 + +/* Display controller SS */ +/* DC part1 */ +#define IMX8QXP_DC_AXI_EXT_CLK 245 +#define IMX8QXP_DC_AXI_INT_CLK 246 +#define IMX8QXP_DC_CFG_CLK 247 +#define IMX8QXP_DC0_DISP0_CLK 248 +#define IMX8QXP_DC0_DISP1_CLK 249 +#define IMX8QXP_DC0_PRG0_RTRAM_CLK 250 +#define IMX8QXP_DC0_PRG0_APB_CLK 251 +#define IMX8QXP_DC0_PRG1_RTRAM_CLK 252 +#define IMX8QXP_DC0_PRG1_APB_CLK 253 +#define IMX8QXP_DC0_PRG2_RTRAM_CLK 254 +#define IMX8QXP_DC0_PRG2_APB_CLK 255 +#define IMX8QXP_DC0_PRG3_RTRAM_CLK 256 +#define IMX8QXP_DC0_PRG3_APB_CLK 257 +#define IMX8QXP_DC0_PRG4_RTRAM_CLK 258 +#define IMX8QXP_DC0_PRG4_APB_CLK 259 +#define IMX8QXP_DC0_PRG5_RTRAM_CLK 260 +#define IMX8QXP_DC0_PRG5_APB_CLK 261 +#define IMX8QXP_DC0_PRG6_RTRAM_CLK 262 +#define IMX8QXP_DC0_PRG6_APB_CLK 263 +#define IMX8QXP_DC0_PRG7_RTRAM_CLK 264 +#define IMX8QXP_DC0_PRG7_APB_CLK 265 +#define IMX8QXP_DC0_PRG8_RTRAM_CLK 266 +#define IMX8QXP_DC0_PRG8_APB_CLK 267 +#define IMX8QXP_DC0_DPR0_APB_CLK 268 +#define IMX8QXP_DC0_DPR0_B_CLK 269 +#define IMX8QXP_DC0_RTRAM0_CLK 270 +#define IMX8QXP_DC0_RTRAM1_CLK 271 + +/* MIPI-LVDS part1 */ +#define IMX8QXP_MIPI_IPG_CLK 272 +#define IMX8QXP_MIPI0_I2C0_DIV 273 +#define IMX8QXP_MIPI0_I2C1_DIV 274 +#define IMX8QXP_MIPI0_I2C0_CLK 275 +#define IMX8QXP_MIPI0_I2C1_CLK 276 +#define IMX8QXP_MIPI0_I2C0_IPG_CLK 278 +#define IMX8QXP_MIPI0_I2C1_IPG_CLK 280 +#define IMX8QXP_MIPI0_PWM_IPG_CLK 282 +#define IMX8QXP_MIPI0_PWM_32K_CLK 283 +#define IMX8QXP_MIPI0_GPIO_IPG_CLK 284 + +#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK 285 +#define IMX8QXP_IMG_JPEG_ENC_CLK 286 +#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK 287 +#define IMX8QXP_IMG_JPEG_DEC_CLK 288 +#define IMX8QXP_IMG_PXL_LINK_DC0_CLK 289 +#define IMX8QXP_IMG_PXL_LINK_DC1_CLK 290 +#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK 291 +#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK 292 +#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK 293 +#define IMX8QXP_IMG_PDMA_0_CLK 294 +#define IMX8QXP_IMG_PDMA_1_CLK 295 +#define IMX8QXP_IMG_PDMA_2_CLK 296 +#define IMX8QXP_IMG_PDMA_3_CLK 297 +#define IMX8QXP_IMG_PDMA_4_CLK 298 +#define IMX8QXP_IMG_PDMA_5_CLK 299 +#define IMX8QXP_IMG_PDMA_6_CLK 300 +#define IMX8QXP_IMG_PDMA_7_CLK 301 +#define IMX8QXP_IMG_AXI_CLK 302 +#define IMX8QXP_IMG_IPG_CLK 303 +#define IMX8QXP_IMG_PXL_CLK 304 + +#define IMX8QXP_CSI0_I2C0_DIV 305 +#define IMX8QXP_CSI0_PWM0_DIV 306 +#define IMX8QXP_CSI0_CORE_DIV 307 +#define IMX8QXP_CSI0_ESC_DIV 308 +#define IMX8QXP_CSI0_IPG_CLK_S 309 +#define IMX8QXP_CSI0_IPG_CLK 310 +#define IMX8QXP_CSI0_APB_CLK 311 +#define IMX8QXP_CSI0_I2C0_IPG_CLK 312 +#define IMX8QXP_CSI0_I2C0_CLK 313 +#define IMX8QXP_CSI0_PWM0_IPG_CLK 314 +#define IMX8QXP_CSI0_PWM0_CLK 315 +#define IMX8QXP_CSI0_CORE_CLK 316 +#define IMX8QXP_CSI0_ESC_CLK 317 + +#define IMX8QXP_HSIO_AXI_CLK 318 +#define IMX8QXP_HSIO_PER_CLK 319 +#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK 320 +#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK 321 +#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK 322 +#define IMX8QXP_HSIO_PCIE_X1_PER_CLK 323 +#define IMX8QXP_HSIO_PHY_X1_PER_CLK 324 +#define IMX8QXP_HSIO_MISC_PER_CLK 325 +#define IMX8QXP_HSIO_PHY_X1_APB_CLK 326 +#define IMX8QXP_HSIO_GPIO_CLK 327 +#define IMX8QXP_HSIO_PHY_X1_PCLK 328 + +#define IMX8QXP_A35_DIV 329 + +/* ACM */ +#define IMX8QXP_EXT_AUD_MCLK0 330 +#define IMX8QXP_EXT_AUD_MCLK1 331 +#define IMX8QXP_ESAI0_RX_CLK 332 +#define IMX8QXP_ESAI0_RX_HF_CLK 333 +#define IMX8QXP_ESAI0_TX_CLK 334 +#define IMX8QXP_ESAI0_TX_HF_CLK 335 +#define IMX8QXP_SPDIF0_RX 336 +#define IMX8QXP_SAI0_RX_BCLK 337 +#define IMX8QXP_SAI0_TX_BCLK 338 +#define IMX8QXP_SAI1_RX_BCLK 339 +#define IMX8QXP_SAI1_TX_BCLK 340 +#define IMX8QXP_SAI2_RX_BCLK 341 +#define IMX8QXP_SAI3_RX_BCLK 342 +#define IMX8QXP_SAI4_RX_BCLK 343 + +#define IMX8QXP_ACM_AUD_CLK0_SEL 344 +#define IMX8QXP_ACM_AUD_CLK1_SEL 346 +#define IMX8QXP_ACM_MCLKOUT0_SEL 348 +#define IMX8QXP_ACM_MCLKOUT0_CLK 349 +#define IMX8QXP_ACM_MCLKOUT1_SEL 350 +#define IMX8QXP_ACM_MCLKOUT1_CLK 351 +#define IMX8QXP_ACM_ESAI0_MCLK_SEL 352 +#define IMX8QXP_ACM_ESAI0_MCLK_CLK 353 +#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL 354 +#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK 355 +#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL 356 +#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK 357 +#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL 358 +#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK 359 +#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL 360 +#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK 361 +#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL 362 +#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK 363 +#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL 364 +#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK 365 +#define IMX8QXP_ACM_SAI0_MCLK_SEL 366 +#define IMX8QXP_ACM_SAI0_MCLK_CLK 367 +#define IMX8QXP_ACM_SAI1_MCLK_SEL 368 +#define IMX8QXP_ACM_SAI1_MCLK_CLK 369 +#define IMX8QXP_ACM_SAI2_MCLK_SEL 370 +#define IMX8QXP_ACM_SAI2_MCLK_CLK 371 +#define IMX8QXP_ACM_SAI3_MCLK_SEL 372 +#define IMX8QXP_ACM_SAI3_MCLK_CLK 373 +#define IMX8QXP_ACM_SAI4_MCLK_SEL 374 +#define IMX8QXP_ACM_SAI4_MCLK_CLK 375 +#define IMX8QXP_ACM_SAI5_MCLK_SEL 376 +#define IMX8QXP_ACM_SAI5_MCLK_CLK 377 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL 378 +#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK 379 +#define IMX8QXP_ACM_MQS_TX_CLK_SEL 380 +#define IMX8QXP_ACM_MQS_TX_CLK_CLK 381 + +#define IMX8QXP_IPG_AUD_CLK_ROOT 386 + +/* Audio */ +#define IMX8QXP_AUD_PLL0_DIV 387 +#define IMX8QXP_AUD_PLL0 388 +#define IMX8QXP_AUD_PLL1_DIV 389 +#define IMX8QXP_AUD_PLL1 390 +#define IMX8QXP_AUD_AMIX_IPG 391 +#define IMX8QXP_AUD_ESAI_0_IPG 392 +#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG 393 +#define IMX8QXP_AUD_SAI_0_IPG 394 +#define IMX8QXP_AUD_SAI_0_MCLK 395 +#define IMX8QXP_AUD_SAI_1_IPG 396 +#define IMX8QXP_AUD_SAI_1_MCLK 397 +#define IMX8QXP_AUD_SAI_2_IPG 398 +#define IMX8QXP_AUD_SAI_2_MCLK 399 +#define IMX8QXP_AUD_SAI_3_IPG 400 +#define IMX8QXP_AUD_SAI_3_MCLK 401 +#define IMX8QXP_AUD_SAI_4_IPG 402 +#define IMX8QXP_AUD_SAI_4_MCLK 403 +#define IMX8QXP_AUD_SAI_5_IPG 404 +#define IMX8QXP_AUD_SAI_5_MCLK 405 +#define IMX8QXP_AUD_MQS_IPG 406 +#define IMX8QXP_AUD_MQS_HMCLK 407 +#define IMX8QXP_AUD_GPT5_IPG 408 +#define IMX8QXP_AUD_GPT5_CLKIN 409 +#define IMX8QXP_AUD_GPT6_IPG 410 +#define IMX8QXP_AUD_GPT6_CLKIN 411 +#define IMX8QXP_AUD_GPT7_IPG 412 +#define IMX8QXP_AUD_GPT7_CLKIN 413 +#define IMX8QXP_AUD_GPT8_IPG 414 +#define IMX8QXP_AUD_GPT8_CLKIN 415 +#define IMX8QXP_AUD_GPT9_IPG 416 +#define IMX8QXP_AUD_GPT9_CLKIN 417 +#define IMX8QXP_AUD_GPT10_IPG 418 +#define IMX8QXP_AUD_GPT10_CLKIN 419 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV 420 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK 421 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV 422 +#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK 423 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV 424 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK 425 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV 426 +#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK 427 +#define IMX8QXP_AUD_MCLKOUT0 428 +#define IMX8QXP_AUD_MCLKOUT1 429 +#define IMX8QXP_AUD_SPDIF_0_TX_CLK 430 +#define IMX8QXP_AUD_SPDIF_0_GCLKW 431 +#define IMX8QXP_AUD_SPDIF_0_IPG 432 +#define IMX8QXP_AUD_ASRC_0_IPG 433 +#define IMX8QXP_AUD_ASRC_1_IPG 434 +#define IMX8QXP_AUD_DSP_ADB_ACLK 435 +#define IMX8QXP_AUD_DSP_IPG 436 +#define IMX8QXP_AUD_DSP_CORE_CLK 437 +#define IMX8QXP_AUD_OCRAM_IPG 438 + +/* DC part2 */ +#define IMX8QXP_DC0_DISP0_DIV 439 +#define IMX8QXP_DC0_DISP1_DIV 440 +#define IMX8QXP_DC0_BYPASS_0_DIV 441 +#define IMX8QXP_DC0_BYPASS_1_DIV 442 +#define IMX8QXP_DC0_PLL0_DIV 443 +#define IMX8QXP_DC0_PLL1_DIV 444 +#define IMX8QXP_DC0_PLL0_CLK 445 +#define IMX8QXP_DC0_PLL1_CLK 446 + +/* MIPI-LVDS part2 */ +#define IMX8QXP_MIPI0_BYPASS_CLK 447 +#define IMX8QXP_MIPI0_PIXEL_DIV 448 +#define IMX8QXP_MIPI0_PIXEL_CLK 449 +#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV 450 +#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 451 +#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 452 +#define IMX8QXP_MIPI0_LVDS_PHY_DIV 453 +#define IMX8QXP_MIPI0_LVDS_PHY_CLK 454 +#define IMX8QXP_MIPI0_DSI_TX_ESC_DIV 455 +#define IMX8QXP_MIPI0_DSI_RX_ESC_DIV 456 +#define IMX8QXP_MIPI0_DSI_TX_ESC_CLK 457 +#define IMX8QXP_MIPI0_DSI_RX_ESC_CLK 458 +#define IMX8QXP_MIPI0_LIS_IPG_CLK 459 +#define IMX8QXP_MIPI1_I2C0_DIV 460 +#define IMX8QXP_MIPI1_I2C1_DIV 461 +#define IMX8QXP_MIPI1_I2C0_CLK 462 +#define IMX8QXP_MIPI1_I2C1_CLK 463 +#define IMX8QXP_MIPI1_I2C0_IPG_CLK 465 +#define IMX8QXP_MIPI1_I2C1_IPG_CLK 467 +#define IMX8QXP_MIPI1_PWM_IPG_CLK 469 +#define IMX8QXP_MIPI1_PWM_32K_CLK 470 +#define IMX8QXP_MIPI1_GPIO_IPG_CLK 471 +#define IMX8QXP_MIPI1_BYPASS_CLK 472 +#define IMX8QXP_MIPI1_PIXEL_DIV 473 +#define IMX8QXP_MIPI1_PIXEL_CLK 474 +#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV 475 +#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 476 +#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 477 +#define IMX8QXP_MIPI1_LVDS_PHY_DIV 478 +#define IMX8QXP_MIPI1_LVDS_PHY_CLK 479 +#define IMX8QXP_MIPI1_DSI_TX_ESC_DIV 480 +#define IMX8QXP_MIPI1_DSI_RX_ESC_DIV 481 +#define IMX8QXP_MIPI1_DSI_TX_ESC_CLK 482 +#define IMX8QXP_MIPI1_DSI_RX_ESC_CLK 483 + +#define IMX8QXP_MIPI1_LIS_IPG_CLK 484 + +/* CM40 */ +#define IMX8QXP_CM40_IPG_CLK 485 +#define IMX8QXP_CM40_I2C_DIV 486 +#define IMX8QXP_CM40_I2C_CLK 487 +#define IMX8QXP_CM40_I2C_IPG_CLK 488 + +/* VPU clocks. */ +#define IMX8QXP_VPU_ENC_CLK 489 +#define IMX8QXP_VPU_DEC_CLK 490 + +/* MIPI-LVDS part3 */ +#define IMX8QXP_MIPI0_DSI_PLL_CLK 491 +#define IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK 492 +#define IMX8QXP_MIPI0_LVDS_PIXEL_SEL 493 +#define IMX8QXP_MIPI0_LVDS_PHY_SEL 494 +#define IMX8QXP_MIPI0_DSI_TX_ESC_SEL 495 +#define IMX8QXP_MIPI0_DSI_RX_ESC_SEL 496 +#define IMX8QXP_MIPI0_DSI_PHY_SEL 498 +#define IMX8QXP_MIPI0_DSI_PHY_DIV 499 +#define IMX8QXP_MIPI0_DSI_PHY_CLK 500 +#define IMX8QXP_MIPI1_DSI_PLL_CLK 501 +#define IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK 502 +#define IMX8QXP_MIPI1_LVDS_PIXEL_SEL 503 +#define IMX8QXP_MIPI1_LVDS_PHY_SEL 504 +#define IMX8QXP_MIPI1_DSI_TX_ESC_SEL 505 +#define IMX8QXP_MIPI1_DSI_RX_ESC_SEL 506 +#define IMX8QXP_MIPI1_DSI_PHY_SEL 507 +#define IMX8QXP_MIPI1_DSI_PHY_DIV 508 +#define IMX8QXP_MIPI1_DSI_PHY_CLK 509 + +/* DC part3 */ +#define IMX8QXP_DC0_DPR1_APB_CLK 510 +#define IMX8QXP_DC0_DPR1_B_CLK 511 + +#define IMX8QXP_CONN_PLL0_CLK 512 +#define IMX8QXP_CONN_PLL1_CLK 513 +#define IMX8QXP_SDHC0_SEL 514 +#define IMX8QXP_SDHC1_SEL 515 +#define IMX8QXP_SDHC2_SEL 516 + +/* PARALLER CSI */ +#define IMX8QXP_PARALLEL_CSI_CLK_DPLL 517 +#define IMX8QXP_PARALLEL_CSI_CLK_SEL 518 +#define IMX8QXP_PARALLEL_CSI_PER_CLK_DIV 519 +#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 520 +#define IMX8QXP_PARALLEL_CSI_IPG_CLK 521 +#define IMX8QXP_PARALLEL_CSI_MCLK_DIV 522 +#define IMX8QXP_PARALLEL_CSI_MISC0_CLK 523 + +#define IMX8QXP_MIPI0_PWM_DIV 524 +#define IMX8QXP_MIPI1_PWM_DIV 525 +#define IMX8QXP_MIPI0_PWM_CLK 526 +#define IMX8QXP_MIPI1_PWM_CLK 527 + +#define IMX8QXP_LSIO_MU5A_IPG_S_CLK 528 +#define IMX8QXP_LSIO_MU5A_IPG_CLK 529 + + +/* LCD part2 */ +#define IMX8QXP_LCD_PXL_BYPASS_DIV 530 +#define IMX8QXP_LCD_PXL_SEL 531 +#define IMX8QXP_LCD_PXL_DIV 532 +#define IMX8QXP_LCD_PXL_CLK 533 +#define IMX8QXP_ELCDIF_PLL_DIV 534 +#define IMX8QXP_ELCDIF_PLL 535 +#define IMX8QXP_LCD_SEL 536 + +#define IMX8QXP_CLK_END 537 +#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h index bcf0ae100f21..daa418607e8c 100644 --- a/include/dt-bindings/input/input.h +++ b/include/dt-bindings/input/input.h @@ -15,4 +15,7 @@ #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) +#define FT5416 0x54160002 +#define FT5426 0x54260002 + #endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h new file mode 100644 index 000000000000..d85cccfb3b35 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -0,0 +1,1002 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_SIM0_CLK 0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST 1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */ +#define SC_P_M40_I2C0_SCL 7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA 8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_00 9 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_01 10 /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL 11 /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA 12 /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_00 13 /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_01 14 /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK 15 /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE 16 /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE 17 /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK 18 /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE 19 /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE 20 /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX 21 /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX 22 /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23 /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24 /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX 25 /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX 26 /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27 /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28 /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /* */ +#define SC_P_SCU_PMIC_MEMC_ON 30 /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT 31 /* SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA 32 /* SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL 33 /* SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34 /* SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35 /* SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 36 /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_01 37 /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_02 38 /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_03 39 /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_04 40 /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +#define SC_P_SCU_GPIO0_05 41 /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +#define SC_P_SCU_GPIO0_06 42 /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +#define SC_P_SCU_GPIO0_07 43 /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +#define SC_P_SCU_BOOT_MODE0 44 /* SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45 /* SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46 /* SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47 /* SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48 /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49 /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50 /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51 /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52 /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53 /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54 /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55 /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56 /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57 /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58 /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59 /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60 /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61 /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /* */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63 /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64 /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 65 /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +#define SC_P_MIPI_DSI0_GPIO0_01 66 /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67 /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68 /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 69 /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +#define SC_P_MIPI_DSI1_GPIO0_01 70 /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /* */ +#define SC_P_MIPI_CSI0_MCLK_OUT 72 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 73 /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 74 /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_CSI0_GPIO0_00 75 /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_CSI0_GPIO0_01 76 /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77 /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78 /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79 /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80 /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81 /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82 /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83 /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /* */ +#define SC_P_ESAI1_FSR 85 /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86 /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87 /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT 88 /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ +#define SC_P_ESAI1_TX0 89 /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ +#define SC_P_ESAI1_TX1 90 /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ +#define SC_P_ESAI1_TX2_RX3 91 /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ +#define SC_P_ESAI1_TX3_RX2 92 /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ +#define SC_P_ESAI1_TX4_RX1 93 /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ +#define SC_P_ESAI1_TX5_RX0 94 /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ +#define SC_P_SPDIF0_RX 95 /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ +#define SC_P_SPDIF0_TX 96 /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ +#define SC_P_SPDIF0_EXT_CLK 97 /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ +#define SC_P_SPI3_SCK 98 /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ +#define SC_P_SPI3_SDO 99 /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ +#define SC_P_SPI3_SDI 100 /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ +#define SC_P_SPI3_CS0 101 /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ +#define SC_P_SPI3_CS1 102 /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /* */ +#define SC_P_ESAI0_FSR 104 /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ +#define SC_P_ESAI0_FST 105 /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ +#define SC_P_ESAI0_SCKR 106 /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ +#define SC_P_ESAI0_SCKT 107 /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ +#define SC_P_ESAI0_TX0 108 /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ +#define SC_P_ESAI0_TX1 109 /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ +#define SC_P_ESAI0_TX2_RX3 110 /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ +#define SC_P_ESAI0_TX3_RX2 111 /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ +#define SC_P_ESAI0_TX4_RX1 112 /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ +#define SC_P_ESAI0_TX5_RX0 113 /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ +#define SC_P_MCLK_IN0 114 /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */ +#define SC_P_MCLK_OUT0 115 /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /* */ +#define SC_P_SPI0_SCK 117 /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ +#define SC_P_SPI0_SDO 118 /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ +#define SC_P_SPI0_SDI 119 /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ +#define SC_P_SPI0_CS0 120 /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ +#define SC_P_SPI0_CS1 121 /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ +#define SC_P_SPI2_SCK 122 /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ +#define SC_P_SPI2_SDO 123 /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ +#define SC_P_SPI2_SDI 124 /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ +#define SC_P_SPI2_CS0 125 /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ +#define SC_P_SPI2_CS1 126 /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ +#define SC_P_SAI1_RXC 127 /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ +#define SC_P_SAI1_RXD 128 /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ +#define SC_P_SAI1_RXFS 129 /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ +#define SC_P_SAI1_TXC 130 /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ +#define SC_P_SAI1_TXD 131 /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ +#define SC_P_SAI1_TXFS 132 /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /* */ +#define SC_P_ADC_IN7 134 /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ +#define SC_P_ADC_IN6 135 /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ +#define SC_P_ADC_IN5 136 /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ +#define SC_P_ADC_IN4 137 /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ +#define SC_P_ADC_IN3 138 /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ +#define SC_P_ADC_IN2 139 /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ +#define SC_P_ADC_IN1 140 /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ +#define SC_P_ADC_IN0 141 /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ +#define SC_P_MLB_SIG 142 /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ +#define SC_P_MLB_CLK 143 /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ +#define SC_P_MLB_DATA 144 /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /* */ +#define SC_P_FLEXCAN0_RX 146 /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ +#define SC_P_FLEXCAN0_TX 147 /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ +#define SC_P_FLEXCAN1_RX 148 /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ +#define SC_P_FLEXCAN1_TX 149 /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ +#define SC_P_FLEXCAN2_RX 150 /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +#define SC_P_FLEXCAN2_TX 151 /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /* */ +#define SC_P_USB_SS3_TC0 153 /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 154 /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 155 /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 156 /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /* */ +#define SC_P_USDHC1_RESET_B 158 /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ +#define SC_P_USDHC1_VSELECT 159 /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ +#define SC_P_USDHC2_RESET_B 160 /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ +#define SC_P_USDHC2_VSELECT 161 /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ +#define SC_P_USDHC2_WP 162 /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ +#define SC_P_USDHC2_CD_B 163 /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /* */ +#define SC_P_ENET0_MDIO 165 /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ +#define SC_P_ENET0_MDC 166 /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ +#define SC_P_ENET0_REFCLK_125M_25M 167 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ +#define SC_P_ENET1_REFCLK_125M_25M 168 /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ +#define SC_P_ENET1_MDIO 169 /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ +#define SC_P_ENET1_MDC 170 /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /* */ +#define SC_P_QSPI1A_SS0_B 172 /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ +#define SC_P_QSPI1A_SS1_B 173 /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ +#define SC_P_QSPI1A_SCLK 174 /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ +#define SC_P_QSPI1A_DQS 175 /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_QSPI1A_DATA3 176 /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ +#define SC_P_QSPI1A_DATA2 177 /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ +#define SC_P_QSPI1A_DATA1 178 /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +#define SC_P_QSPI1A_DATA0 179 /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /* */ +#define SC_P_QSPI0A_DATA0 181 /* LSIO.QSPI0A.DATA0 */ +#define SC_P_QSPI0A_DATA1 182 /* LSIO.QSPI0A.DATA1 */ +#define SC_P_QSPI0A_DATA2 183 /* LSIO.QSPI0A.DATA2 */ +#define SC_P_QSPI0A_DATA3 184 /* LSIO.QSPI0A.DATA3 */ +#define SC_P_QSPI0A_DQS 185 /* LSIO.QSPI0A.DQS */ +#define SC_P_QSPI0A_SS0_B 186 /* LSIO.QSPI0A.SS0_B */ +#define SC_P_QSPI0A_SS1_B 187 /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ +#define SC_P_QSPI0A_SCLK 188 /* LSIO.QSPI0A.SCLK */ +#define SC_P_QSPI0B_SCLK 189 /* LSIO.QSPI0B.SCLK */ +#define SC_P_QSPI0B_DATA0 190 /* LSIO.QSPI0B.DATA0 */ +#define SC_P_QSPI0B_DATA1 191 /* LSIO.QSPI0B.DATA1 */ +#define SC_P_QSPI0B_DATA2 192 /* LSIO.QSPI0B.DATA2 */ +#define SC_P_QSPI0B_DATA3 193 /* LSIO.QSPI0B.DATA3 */ +#define SC_P_QSPI0B_DQS 194 /* LSIO.QSPI0B.DQS */ +#define SC_P_QSPI0B_SS0_B 195 /* LSIO.QSPI0B.SS0_B */ +#define SC_P_QSPI0B_SS1_B 196 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /* */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ +#define SC_P_PCIE_CTRL0_WAKE_B 199 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ +#define SC_P_PCIE_CTRL0_PERST_B 200 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ +#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */ +#define SC_P_PCIE_CTRL1_WAKE_B 202 /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */ +#define SC_P_PCIE_CTRL1_PERST_B 203 /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /* */ +#define SC_P_USB_HSIC0_DATA 205 /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ +#define SC_P_USB_HSIC0_STROBE 206 /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ +#define SC_P_CALIBRATION_0_HSIC 207 /* */ +#define SC_P_CALIBRATION_1_HSIC 208 /* */ +#define SC_P_EMMC0_CLK 209 /* CONN.EMMC0.CLK, CONN.NAND.READY_B */ +#define SC_P_EMMC0_CMD 210 /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ +#define SC_P_EMMC0_DATA0 211 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ +#define SC_P_EMMC0_DATA1 212 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ +#define SC_P_EMMC0_DATA2 213 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ +#define SC_P_EMMC0_DATA3 214 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ +#define SC_P_EMMC0_DATA4 215 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ +#define SC_P_EMMC0_DATA5 216 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ +#define SC_P_EMMC0_DATA6 217 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ +#define SC_P_EMMC0_DATA7 218 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ +#define SC_P_EMMC0_STROBE 219 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ +#define SC_P_EMMC0_RESET_B 220 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /* */ +#define SC_P_USDHC1_CLK 222 /* CONN.USDHC1.CLK, AUD.MQS.R */ +#define SC_P_USDHC1_CMD 223 /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ +#define SC_P_USDHC1_DATA0 224 /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ +#define SC_P_USDHC1_DATA1 225 /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ +#define SC_P_CTL_NAND_RE_P_N 226 /* */ +#define SC_P_USDHC1_DATA2 227 /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ +#define SC_P_USDHC1_DATA3 228 /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ +#define SC_P_CTL_NAND_DQS_P_N 229 /* */ +#define SC_P_USDHC1_DATA4 230 /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ +#define SC_P_USDHC1_DATA5 231 /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA6 232 /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ +#define SC_P_USDHC1_DATA7 233 /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */ +#define SC_P_USDHC1_STROBE 234 /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /* */ +#define SC_P_USDHC2_CLK 236 /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ +#define SC_P_USDHC2_CMD 237 /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ +#define SC_P_USDHC2_DATA0 238 /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ +#define SC_P_USDHC2_DATA1 239 /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ +#define SC_P_USDHC2_DATA2 240 /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ +#define SC_P_USDHC2_DATA3 241 /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /* */ +#define SC_P_ENET0_RGMII_TXC 243 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ +#define SC_P_ENET0_RGMII_TX_CTL 244 /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ +#define SC_P_ENET0_RGMII_TXD0 245 /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ +#define SC_P_ENET0_RGMII_TXD1 246 /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ +#define SC_P_ENET0_RGMII_TXD2 247 /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */ +#define SC_P_ENET0_RGMII_TXD3 248 /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ +#define SC_P_ENET0_RGMII_RXC 249 /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ +#define SC_P_ENET0_RGMII_RX_CTL 250 /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ +#define SC_P_ENET0_RGMII_RXD0 251 /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252 /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RXD2 253 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ +#define SC_P_ENET0_RGMII_RXD3 254 /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /* */ +#define SC_P_ENET1_RGMII_TXC 256 /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ +#define SC_P_ENET1_RGMII_TX_CTL 257 /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ +#define SC_P_ENET1_RGMII_TXD0 258 /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ +#define SC_P_ENET1_RGMII_TXD1 259 /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ +#define SC_P_ENET1_RGMII_TXD2 260 /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */ +#define SC_P_ENET1_RGMII_TXD3 261 /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ +#define SC_P_ENET1_RGMII_RXC 262 /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ +#define SC_P_ENET1_RGMII_RX_CTL 263 /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ +#define SC_P_ENET1_RGMII_RXD0 264 /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265 /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ +#define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0 +#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3 +#define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0 +#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 SC_P_SIM0_RST 3 +#define SC_P_SIM0_IO_DMA_SIM0_IO SC_P_SIM0_IO 0 +#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 SC_P_SIM0_IO 3 +#define SC_P_SIM0_PD_DMA_SIM0_PD SC_P_SIM0_PD 0 +#define SC_P_SIM0_PD_DMA_I2C3_SCL SC_P_SIM0_PD 1 +#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 SC_P_SIM0_PD 3 +#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN SC_P_SIM0_POWER_EN 0 +#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA SC_P_SIM0_POWER_EN 1 +#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 SC_P_SIM0_POWER_EN 3 +#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN SC_P_SIM0_GPIO0_00 0 +#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 SC_P_SIM0_GPIO0_00 3 +#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL SC_P_M40_I2C0_SCL 0 +#define SC_P_M40_I2C0_SCL_M40_UART0_RX SC_P_M40_I2C0_SCL 1 +#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 SC_P_M40_I2C0_SCL 2 +#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 SC_P_M40_I2C0_SCL 3 +#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA SC_P_M40_I2C0_SDA 0 +#define SC_P_M40_I2C0_SDA_M40_UART0_TX SC_P_M40_I2C0_SDA 1 +#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 SC_P_M40_I2C0_SDA 2 +#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 SC_P_M40_I2C0_SDA 3 +#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 SC_P_M40_GPIO0_00 0 +#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 SC_P_M40_GPIO0_00 1 +#define SC_P_M40_GPIO0_00_DMA_UART4_RX SC_P_M40_GPIO0_00 2 +#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 SC_P_M40_GPIO0_00 3 +#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 SC_P_M40_GPIO0_01 0 +#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 SC_P_M40_GPIO0_01 1 +#define SC_P_M40_GPIO0_01_DMA_UART4_TX SC_P_M40_GPIO0_01 2 +#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 SC_P_M40_GPIO0_01 3 +#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL SC_P_M41_I2C0_SCL 0 +#define SC_P_M41_I2C0_SCL_M41_UART0_RX SC_P_M41_I2C0_SCL 1 +#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 SC_P_M41_I2C0_SCL 2 +#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 SC_P_M41_I2C0_SCL 3 +#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA SC_P_M41_I2C0_SDA 0 +#define SC_P_M41_I2C0_SDA_M41_UART0_TX SC_P_M41_I2C0_SDA 1 +#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 SC_P_M41_I2C0_SDA 2 +#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 SC_P_M41_I2C0_SDA 3 +#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 SC_P_M41_GPIO0_00 0 +#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 SC_P_M41_GPIO0_00 1 +#define SC_P_M41_GPIO0_00_DMA_UART3_RX SC_P_M41_GPIO0_00 2 +#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 SC_P_M41_GPIO0_00 3 +#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 SC_P_M41_GPIO0_01 0 +#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 SC_P_M41_GPIO0_01 1 +#define SC_P_M41_GPIO0_01_DMA_UART3_TX SC_P_M41_GPIO0_01 2 +#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 SC_P_M41_GPIO0_01 3 +#define SC_P_GPT0_CLK_LSIO_GPT0_CLK SC_P_GPT0_CLK 0 +#define SC_P_GPT0_CLK_DMA_I2C1_SCL SC_P_GPT0_CLK 1 +#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 SC_P_GPT0_CLK 2 +#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 SC_P_GPT0_CLK 3 +#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE SC_P_GPT0_CAPTURE 0 +#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA SC_P_GPT0_CAPTURE 1 +#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 SC_P_GPT0_CAPTURE 2 +#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 SC_P_GPT0_CAPTURE 3 +#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE SC_P_GPT0_COMPARE 0 +#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT SC_P_GPT0_COMPARE 1 +#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 SC_P_GPT0_COMPARE 2 +#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 SC_P_GPT0_COMPARE 3 +#define SC_P_GPT1_CLK_LSIO_GPT1_CLK SC_P_GPT1_CLK 0 +#define SC_P_GPT1_CLK_DMA_I2C2_SCL SC_P_GPT1_CLK 1 +#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 SC_P_GPT1_CLK 2 +#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 SC_P_GPT1_CLK 3 +#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE SC_P_GPT1_CAPTURE 0 +#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA SC_P_GPT1_CAPTURE 1 +#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 SC_P_GPT1_CAPTURE 2 +#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 SC_P_GPT1_CAPTURE 3 +#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE SC_P_GPT1_COMPARE 0 +#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT SC_P_GPT1_COMPARE 1 +#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 SC_P_GPT1_COMPARE 2 +#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 SC_P_GPT1_COMPARE 3 +#define SC_P_UART0_RX_DMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 1 +#define SC_P_UART0_RX_LSIO_GPIO0_IO20 SC_P_UART0_RX 3 +#define SC_P_UART0_TX_DMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 1 +#define SC_P_UART0_TX_LSIO_GPIO0_IO21 SC_P_UART0_TX 3 +#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B SC_P_UART0_RTS_B 0 +#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT SC_P_UART0_RTS_B 1 +#define SC_P_UART0_RTS_B_DMA_UART2_RX SC_P_UART0_RTS_B 2 +#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 SC_P_UART0_RTS_B 3 +#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B SC_P_UART0_CTS_B 0 +#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT SC_P_UART0_CTS_B 1 +#define SC_P_UART0_CTS_B_DMA_UART2_TX SC_P_UART0_CTS_B 2 +#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 SC_P_UART0_CTS_B 3 +#define SC_P_UART1_TX_DMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_DMA_SPI3_SCK SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPIO0_IO24 SC_P_UART1_TX 3 +#define SC_P_UART1_RX_DMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_DMA_SPI3_SDO SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPIO0_IO25 SC_P_UART1_RX 3 +#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_DMA_SPI3_SDI SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 SC_P_UART1_RTS_B 3 +#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 SC_P_UART1_CTS_B 3 +#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON SC_P_SCU_PMIC_MEMC_ON 0 +#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT SC_P_SCU_WDOG_OUT 0 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING SC_P_PMIC_EARLY_WARNING 0 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 SC_P_SCU_GPIO0_02 0 +#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON SC_P_SCU_GPIO0_02 1 +#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 SC_P_SCU_GPIO0_02 3 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 SC_P_SCU_GPIO0_03 0 +#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON SC_P_SCU_GPIO0_03 1 +#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 SC_P_SCU_GPIO0_03 3 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 SC_P_SCU_GPIO0_04 0 +#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON SC_P_SCU_GPIO0_04 1 +#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 SC_P_SCU_GPIO0_04 3 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 SC_P_SCU_GPIO0_05 0 +#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON SC_P_SCU_GPIO0_05 1 +#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 SC_P_SCU_GPIO0_05 3 +#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 SC_P_SCU_GPIO0_06 0 +#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 SC_P_SCU_GPIO0_06 1 +#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 SC_P_SCU_GPIO0_06 3 +#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 SC_P_SCU_GPIO0_07 0 +#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 SC_P_SCU_GPIO0_07 1 +#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_GPIO0_07 2 +#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 SC_P_SCU_GPIO0_07 3 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 SC_P_SCU_BOOT_MODE4 0 +#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE4 1 +#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 SC_P_SCU_BOOT_MODE5 0 +#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE5 1 +#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 SC_P_LVDS0_GPIO00 0 +#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT SC_P_LVDS0_GPIO00 1 +#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 SC_P_LVDS0_GPIO00 3 +#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 SC_P_LVDS0_GPIO01 0 +#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 SC_P_LVDS0_GPIO01 3 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL SC_P_LVDS0_I2C0_SCL 0 +#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 SC_P_LVDS0_I2C0_SCL 1 +#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 SC_P_LVDS0_I2C0_SCL 3 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA SC_P_LVDS0_I2C0_SDA 0 +#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 SC_P_LVDS0_I2C0_SDA 1 +#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 SC_P_LVDS0_I2C0_SDA 3 +#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL SC_P_LVDS0_I2C1_SCL 0 +#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX SC_P_LVDS0_I2C1_SCL 1 +#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 SC_P_LVDS0_I2C1_SCL 3 +#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA SC_P_LVDS0_I2C1_SDA 0 +#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX SC_P_LVDS0_I2C1_SDA 1 +#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 SC_P_LVDS0_I2C1_SDA 3 +#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 SC_P_LVDS1_GPIO00 0 +#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT SC_P_LVDS1_GPIO00 1 +#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 SC_P_LVDS1_GPIO00 3 +#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 SC_P_LVDS1_GPIO01 0 +#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 SC_P_LVDS1_GPIO01 3 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL SC_P_LVDS1_I2C0_SCL 0 +#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 SC_P_LVDS1_I2C0_SCL 1 +#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 SC_P_LVDS1_I2C0_SCL 3 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA SC_P_LVDS1_I2C0_SDA 0 +#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 SC_P_LVDS1_I2C0_SDA 1 +#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 SC_P_LVDS1_I2C0_SDA 3 +#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL SC_P_LVDS1_I2C1_SCL 0 +#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX SC_P_LVDS1_I2C1_SCL 1 +#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 SC_P_LVDS1_I2C1_SCL 3 +#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA SC_P_LVDS1_I2C1_SDA 0 +#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX SC_P_LVDS1_I2C1_SDA 1 +#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 SC_P_LVDS1_I2C1_SDA 3 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 SC_P_MIPI_DSI0_I2C0_SCL 3 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 SC_P_MIPI_DSI0_I2C0_SDA 3 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 SC_P_MIPI_DSI0_GPIO0_00 3 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 SC_P_MIPI_DSI0_GPIO0_01 3 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 SC_P_MIPI_DSI1_I2C0_SCL 3 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 SC_P_MIPI_DSI1_I2C0_SDA 3 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 SC_P_MIPI_DSI1_GPIO0_00 3 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 SC_P_MIPI_DSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 SC_P_MIPI_CSI0_MCLK_OUT 3 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_CSI0_I2C0_SCL 3 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_CSI0_I2C0_SDA 3 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 2 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_CSI0_GPIO0_00 3 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 2 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_CSI0_GPIO0_01 3 +#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT SC_P_MIPI_CSI1_MCLK_OUT 0 +#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 SC_P_MIPI_CSI1_MCLK_OUT 3 +#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 SC_P_MIPI_CSI1_GPIO0_00 0 +#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX SC_P_MIPI_CSI1_GPIO0_00 1 +#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 SC_P_MIPI_CSI1_GPIO0_00 3 +#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 SC_P_MIPI_CSI1_GPIO0_01 0 +#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX SC_P_MIPI_CSI1_GPIO0_01 1 +#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 SC_P_MIPI_CSI1_GPIO0_01 3 +#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI1_I2C0_SCL 0 +#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 SC_P_MIPI_CSI1_I2C0_SCL 3 +#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI1_I2C0_SDA 0 +#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 SC_P_MIPI_CSI1_I2C0_SDA 3 +#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 0 +#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 1 +#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 SC_P_HDMI_TX0_TS_SCL 3 +#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 0 +#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 1 +#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 SC_P_HDMI_TX0_TS_SDA 3 +#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR SC_P_ESAI1_FSR 0 +#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 SC_P_ESAI1_FSR 3 +#define SC_P_ESAI1_FST_AUD_ESAI1_FST SC_P_ESAI1_FST 0 +#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_FST 1 +#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 SC_P_ESAI1_FST 3 +#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR SC_P_ESAI1_SCKR 0 +#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 SC_P_ESAI1_SCKR 3 +#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT SC_P_ESAI1_SCKT 0 +#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC SC_P_ESAI1_SCKT 1 +#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_SCKT 2 +#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 SC_P_ESAI1_SCKT 3 +#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 SC_P_ESAI1_TX0 0 +#define SC_P_ESAI1_TX0_AUD_SAI2_RXD SC_P_ESAI1_TX0 1 +#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX SC_P_ESAI1_TX0 2 +#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 SC_P_ESAI1_TX0 3 +#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 SC_P_ESAI1_TX1 0 +#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS SC_P_ESAI1_TX1 1 +#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX SC_P_ESAI1_TX1 2 +#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 SC_P_ESAI1_TX1 3 +#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 SC_P_ESAI1_TX2_RX3 0 +#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX SC_P_ESAI1_TX2_RX3 1 +#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 SC_P_ESAI1_TX2_RX3 3 +#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 SC_P_ESAI1_TX3_RX2 0 +#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX SC_P_ESAI1_TX3_RX2 1 +#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 SC_P_ESAI1_TX3_RX2 3 +#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 SC_P_ESAI1_TX4_RX1 0 +#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 SC_P_ESAI1_TX4_RX1 3 +#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 SC_P_ESAI1_TX5_RX0 0 +#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 SC_P_ESAI1_TX5_RX0 3 +#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_AUD_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_AUD_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 SC_P_SPDIF0_EXT_CLK 1 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPI3_SCK_DMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 SC_P_SPI3_SCK 3 +#define SC_P_SPI3_SDO_DMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_DMA_FTM_CH0 SC_P_SPI3_SDO 1 +#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 SC_P_SPI3_SDO 3 +#define SC_P_SPI3_SDI_DMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_DMA_FTM_CH1 SC_P_SPI3_SDI 1 +#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 SC_P_SPI3_SDI 3 +#define SC_P_SPI3_CS0_DMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_DMA_FTM_CH2 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 SC_P_SPI3_CS0 3 +#define SC_P_SPI3_CS1_DMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 SC_P_SPI3_CS1 3 +#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FST_AUD_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 SC_P_MCLK_IN0 3 +#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 SC_P_MCLK_OUT0 3 +#define SC_P_SPI0_SCK_DMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_AUD_SAI0_RXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SDO_DMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_AUD_SAI0_TXD SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDI_DMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_AUD_SAI0_RXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_CS0_DMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_AUD_SAI0_RXFS SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS1_DMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_AUD_SAI0_TXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 SC_P_SPI0_CS1 3 +#define SC_P_SPI2_SCK_DMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 SC_P_SPI2_SCK 3 +#define SC_P_SPI2_SDO_DMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 SC_P_SPI2_SDO 3 +#define SC_P_SPI2_SDI_DMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 SC_P_SPI2_SDI 3 +#define SC_P_SPI2_CS0_DMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 SC_P_SPI2_CS0 3 +#define SC_P_SPI2_CS1_DMA_SPI2_CS1 SC_P_SPI2_CS1 0 +#define SC_P_SPI2_CS1_AUD_SAI0_TXFS SC_P_SPI2_CS1 1 +#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 SC_P_SPI2_CS1 3 +#define SC_P_SAI1_RXC_AUD_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_AUD_SAI0_TXD SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXD_AUD_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_AUD_SAI0_TXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_AUD_SAI0_RXD SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_TXC_AUD_SAI1_TXC SC_P_SAI1_TXC 0 +#define SC_P_SAI1_TXC_AUD_SAI0_TXC SC_P_SAI1_TXC 1 +#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 SC_P_SAI1_TXC 3 +#define SC_P_SAI1_TXD_AUD_SAI1_TXD SC_P_SAI1_TXD 0 +#define SC_P_SAI1_TXD_AUD_SAI1_RXC SC_P_SAI1_TXD 1 +#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 SC_P_SAI1_TXD 3 +#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS SC_P_SAI1_TXFS 0 +#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS SC_P_SAI1_TXFS 1 +#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 SC_P_SAI1_TXFS 3 +#define SC_P_ADC_IN7_DMA_ADC1_IN3 SC_P_ADC_IN7 0 +#define SC_P_ADC_IN7_DMA_SPI1_CS1 SC_P_ADC_IN7 1 +#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 SC_P_ADC_IN7 2 +#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 SC_P_ADC_IN7 3 +#define SC_P_ADC_IN6_DMA_ADC1_IN2 SC_P_ADC_IN6 0 +#define SC_P_ADC_IN6_DMA_SPI1_CS0 SC_P_ADC_IN6 1 +#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 SC_P_ADC_IN6 2 +#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 SC_P_ADC_IN6 3 +#define SC_P_ADC_IN5_DMA_ADC1_IN1 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_DMA_SPI1_SDI SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 SC_P_ADC_IN5 3 +#define SC_P_ADC_IN4_DMA_ADC1_IN0 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_DMA_SPI1_SDO SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 SC_P_ADC_IN4 3 +#define SC_P_ADC_IN3_DMA_ADC0_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_DMA_SPI1_SCK SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_LSIO_KPP0_COL3 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN2_DMA_ADC0_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_LSIO_KPP0_COL2 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN1_DMA_ADC0_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_LSIO_KPP0_COL1 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 SC_P_ADC_IN1 3 +#define SC_P_ADC_IN0_DMA_ADC0_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_LSIO_KPP0_COL0 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 SC_P_ADC_IN0 3 +#define SC_P_MLB_SIG_CONN_MLB_SIG SC_P_MLB_SIG 0 +#define SC_P_MLB_SIG_AUD_SAI3_RXC SC_P_MLB_SIG 1 +#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 SC_P_MLB_SIG 3 +#define SC_P_MLB_CLK_CONN_MLB_CLK SC_P_MLB_CLK 0 +#define SC_P_MLB_CLK_AUD_SAI3_RXFS SC_P_MLB_CLK 1 +#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 SC_P_MLB_CLK 3 +#define SC_P_MLB_DATA_CONN_MLB_DATA SC_P_MLB_DATA 0 +#define SC_P_MLB_DATA_AUD_SAI3_RXD SC_P_MLB_DATA 1 +#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 SC_P_MLB_DATA 3 +#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 SC_P_FLEXCAN2_TX 3 +#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 3 +#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 3 +#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 3 +#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 3 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 SC_P_USDHC1_RESET_B 3 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B SC_P_USDHC2_RESET_B 0 +#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 SC_P_USDHC2_RESET_B 3 +#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT SC_P_USDHC2_VSELECT 0 +#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 SC_P_USDHC2_VSELECT 3 +#define SC_P_USDHC2_WP_CONN_USDHC2_WP SC_P_USDHC2_WP 0 +#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 SC_P_USDHC2_WP 3 +#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B SC_P_USDHC2_CD_B 0 +#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 SC_P_USDHC2_CD_B 3 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_DMA_I2C4_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 SC_P_ENET0_MDIO 3 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_DMA_I2C4_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 SC_P_ENET0_MDC 3 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 SC_P_ENET0_REFCLK_125M_25M 3 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 0 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET1_REFCLK_125M_25M 1 +#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 SC_P_ENET1_REFCLK_125M_25M 3 +#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO SC_P_ENET1_MDIO 0 +#define SC_P_ENET1_MDIO_DMA_I2C4_SDA SC_P_ENET1_MDIO 1 +#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 SC_P_ENET1_MDIO 3 +#define SC_P_ENET1_MDC_CONN_ENET1_MDC SC_P_ENET1_MDC 0 +#define SC_P_ENET1_MDC_DMA_I2C4_SCL SC_P_ENET1_MDC 1 +#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 SC_P_ENET1_MDC 3 +#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI1A_SS0_B 0 +#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 SC_P_QSPI1A_SS0_B 3 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI1A_SS1_B 0 +#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 SC_P_QSPI1A_SS1_B 1 +#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 SC_P_QSPI1A_SS1_B 3 +#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI1A_SCLK 0 +#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 SC_P_QSPI1A_SCLK 3 +#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS SC_P_QSPI1A_DQS 0 +#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 SC_P_QSPI1A_DQS 3 +#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI1A_DATA3 0 +#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA SC_P_QSPI1A_DATA3 1 +#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC SC_P_QSPI1A_DATA3 2 +#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 SC_P_QSPI1A_DATA3 3 +#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI1A_DATA2 0 +#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL SC_P_QSPI1A_DATA2 1 +#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR SC_P_QSPI1A_DATA2 2 +#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 SC_P_QSPI1A_DATA2 3 +#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI1A_DATA1 0 +#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA SC_P_QSPI1A_DATA1 1 +#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC SC_P_QSPI1A_DATA1 2 +#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 SC_P_QSPI1A_DATA1 3 +#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI1A_DATA0 0 +#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 SC_P_QSPI1A_DATA0 3 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 SC_P_QSPI0A_SS1_B 1 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 SC_P_QSPI0B_SS1_B 1 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 SC_P_PCIE_CTRL0_CLKREQ_B 3 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 SC_P_PCIE_CTRL0_WAKE_B 3 +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 SC_P_PCIE_CTRL0_PERST_B 3 +#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B SC_P_PCIE_CTRL1_CLKREQ_B 0 +#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA SC_P_PCIE_CTRL1_CLKREQ_B 1 +#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC SC_P_PCIE_CTRL1_CLKREQ_B 2 +#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 SC_P_PCIE_CTRL1_CLKREQ_B 3 +#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B SC_P_PCIE_CTRL1_WAKE_B 0 +#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_WAKE_B 1 +#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR SC_P_PCIE_CTRL1_WAKE_B 2 +#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 SC_P_PCIE_CTRL1_WAKE_B 3 +#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B SC_P_PCIE_CTRL1_PERST_B 0 +#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_PERST_B 1 +#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR SC_P_PCIE_CTRL1_PERST_B 2 +#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 SC_P_PCIE_CTRL1_PERST_B 3 +#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA SC_P_USB_HSIC0_DATA 0 +#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA SC_P_USB_HSIC0_DATA 1 +#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 SC_P_USB_HSIC0_DATA 3 +#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE SC_P_USB_HSIC0_STROBE 0 +#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL SC_P_USB_HSIC0_STROBE 1 +#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 SC_P_USB_HSIC0_STROBE 3 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_AUD_MQS_R SC_P_EMMC0_CMD 2 +#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 SC_P_EMMC0_CMD 3 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 SC_P_EMMC0_DATA0 3 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 SC_P_EMMC0_DATA1 3 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 SC_P_EMMC0_DATA2 3 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 SC_P_EMMC0_DATA3 3 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT SC_P_EMMC0_RESET_B 2 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 SC_P_EMMC0_RESET_B 3 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_AUD_MQS_R SC_P_USDHC1_CLK 1 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_AUD_MQS_L SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 SC_P_USDHC1_CMD 3 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 SC_P_USDHC1_DATA0 3 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 SC_P_USDHC1_DATA1 3 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 SC_P_USDHC1_DATA2 3 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 SC_P_USDHC1_DATA3 3 +#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 SC_P_USDHC1_DATA4 0 +#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B SC_P_USDHC1_DATA4 1 +#define SC_P_USDHC1_DATA4_AUD_MQS_R SC_P_USDHC1_DATA4 2 +#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 SC_P_USDHC1_DATA4 3 +#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 SC_P_USDHC1_DATA5 0 +#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B SC_P_USDHC1_DATA5 1 +#define SC_P_USDHC1_DATA5_AUD_MQS_L SC_P_USDHC1_DATA5 2 +#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 SC_P_USDHC1_DATA5 3 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 SC_P_USDHC1_DATA6 0 +#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B SC_P_USDHC1_DATA6 1 +#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP SC_P_USDHC1_DATA6 2 +#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 SC_P_USDHC1_DATA6 3 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 SC_P_USDHC1_DATA7 0 +#define SC_P_USDHC1_DATA7_CONN_NAND_ALE SC_P_USDHC1_DATA7 1 +#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B SC_P_USDHC1_DATA7 2 +#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 SC_P_USDHC1_DATA7 3 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE SC_P_USDHC1_STROBE 0 +#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B SC_P_USDHC1_STROBE 1 +#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B SC_P_USDHC1_STROBE 2 +#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 SC_P_USDHC1_STROBE 3 +#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK SC_P_USDHC2_CLK 0 +#define SC_P_USDHC2_CLK_AUD_MQS_R SC_P_USDHC2_CLK 1 +#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 SC_P_USDHC2_CLK 3 +#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD SC_P_USDHC2_CMD 0 +#define SC_P_USDHC2_CMD_AUD_MQS_L SC_P_USDHC2_CMD 1 +#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 SC_P_USDHC2_CMD 3 +#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 SC_P_USDHC2_DATA0 0 +#define SC_P_USDHC2_DATA0_DMA_UART4_RX SC_P_USDHC2_DATA0 1 +#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 SC_P_USDHC2_DATA0 3 +#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 SC_P_USDHC2_DATA1 0 +#define SC_P_USDHC2_DATA1_DMA_UART4_TX SC_P_USDHC2_DATA1 1 +#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 SC_P_USDHC2_DATA1 3 +#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 SC_P_USDHC2_DATA2 0 +#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B SC_P_USDHC2_DATA2 1 +#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 SC_P_USDHC2_DATA2 3 +#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 SC_P_USDHC2_DATA3 0 +#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B SC_P_USDHC2_DATA3 1 +#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 SC_P_USDHC2_DATA3 3 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 SC_P_ENET0_RGMII_TXD3 3 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET0_RGMII_RX_CTL 2 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET0_RGMII_RXD0 2 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET0_RGMII_RXD1 2 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET0_RGMII_RXD2 2 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX SC_P_ENET0_RGMII_RXD3 1 +#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC SC_P_ENET1_RGMII_TXC 0 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1 +#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN SC_P_ENET1_RGMII_TXC 2 +#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 SC_P_ENET1_RGMII_TXC 3 +#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 0 +#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 SC_P_ENET1_RGMII_TX_CTL 3 +#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 0 +#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 SC_P_ENET1_RGMII_TXD0 3 +#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 0 +#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 SC_P_ENET1_RGMII_TXD1 3 +#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 0 +#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX SC_P_ENET1_RGMII_TXD2 1 +#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET1_RGMII_TXD2 2 +#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 SC_P_ENET1_RGMII_TXD2 3 +#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 0 +#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET1_RGMII_TXD3 1 +#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET1_RGMII_TXD3 2 +#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 SC_P_ENET1_RGMII_TXD3 3 +#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC SC_P_ENET1_RGMII_RXC 0 +#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET1_RGMII_RXC 1 +#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET1_RGMII_RXC 2 +#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 SC_P_ENET1_RGMII_RXC 3 +#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 0 +#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET1_RGMII_RX_CTL 2 +#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 SC_P_ENET1_RGMII_RX_CTL 3 +#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 0 +#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET1_RGMII_RXD0 2 +#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 SC_P_ENET1_RGMII_RXD0 3 +#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 0 +#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET1_RGMII_RXD1 2 +#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 SC_P_ENET1_RGMII_RXD1 3 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 0 +#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER SC_P_ENET1_RGMII_RXD2 1 +#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET1_RGMII_RXD2 2 +#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 SC_P_ENET1_RGMII_RXD2 3 +#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 0 +#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 +#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 +#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 +/*@}*/ + +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO_PAD SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 +/*@}*/ + +#endif /* SC_PADS_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h new file mode 100644 index 000000000000..fb2c052735bd --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -0,0 +1,793 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */ +#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */ +#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */ +#define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */ +#define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25 /* */ +#define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N 28 /* */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */ +#define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */ +#define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */ +#define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ +#define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */ +#define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */ +#define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */ +#define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */ +#define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */ +#define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */ +#define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */ +#define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */ +#define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */ +#define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */ +#define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */ +#define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */ +#define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */ +#define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ +#define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ +#define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ +#define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */ +#define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ +#define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */ +#define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */ +#define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */ +#define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */ +#define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */ +#define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */ +#define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */ +#define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */ +#define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */ +#define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */ +#define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */ +#define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */ +#define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */ +#define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */ +#define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */ +#define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */ +#define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */ +#define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */ +#define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */ +#define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */ +#define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */ +#define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */ +#define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */ +#define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */ +#define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */ +#define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */ +#define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */ +#define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */ +#define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */ +#define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */ +#define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */ +#define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */ +#define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */ +#define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */ +#define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */ +#define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */ +#define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ +#define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */ +#define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */ +#define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */ +#define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */ +#define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */ +#define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */ +#define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */ +#define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */ +#define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */ +#define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */ +#define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */ +#define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */ +#define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */ +#define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */ +#define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */ +#define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */ +#define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ +#define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4 +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4 +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4 +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4 +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3 +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3 +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3 +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3 +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3 +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1 +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1 +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4 +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0 +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1 +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2 +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4 +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1 +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3 +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4 +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0 +#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2 +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4 +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0 +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1 +#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2 +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4 +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0 +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1 +#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2 +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4 +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0 +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1 +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2 +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4 +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0 +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1 +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2 +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4 +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0 +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1 +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2 +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1 +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1 +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1 +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2 +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2 +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4 +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1 +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2 +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3 +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4 +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0 +#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1 +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2 +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3 +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4 +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0 +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2 +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3 +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4 +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0 +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1 +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2 +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3 +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4 +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0 +#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1 +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2 +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3 +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4 +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0 +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2 +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3 +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4 +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1 +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2 +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3 +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4 +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0 +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2 +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3 +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4 +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0 +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2 +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3 +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4 +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0 +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2 +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3 +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4 +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0 +#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1 +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2 +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3 +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4 +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0 +#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1 +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2 +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3 +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4 +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0 +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2 +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3 +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4 +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2 +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4 +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2 +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4 +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2 +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4 +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2 +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4 +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1 +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2 +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3 +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4 +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0 +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1 +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2 +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3 +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4 +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1 +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3 +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4 +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1 +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3 +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4 +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2 +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4 +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2 +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3 +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4 +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3 +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4 +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4 +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0 +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1 +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2 +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3 +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4 +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0 +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1 +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2 +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3 +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4 +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0 +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1 +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2 +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3 +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4 +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0 +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1 +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2 +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4 +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0 +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1 +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2 +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3 +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4 +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0 +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1 +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3 +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4 +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0 +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1 +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3 +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4 +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0 +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4 +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0 +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4 +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0 +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4 +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0 +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4 +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2 +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4 +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2 +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4 +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2 +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4 +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2 +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3 +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4 +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2 +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4 +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1 +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4 +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1 +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4 +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4 +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1 +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4 +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4 +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4 +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1 +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2 +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4 +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1 +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2 +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4 +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1 +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2 +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4 +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1 +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2 +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4 +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1 +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2 +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4 +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1 +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2 +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4 +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1 +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3 +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4 +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1 +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3 +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4 +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0 +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1 +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2 +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4 +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0 +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1 +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2 +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0 +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1 +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0 +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1 +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0 +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1 +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2 +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4 +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0 +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1 +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0 +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1 +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0 +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1 +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0 +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1 +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2 +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4 +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0 +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1 +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4 +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0 +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1 +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1 +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2 +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2 +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4 +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0 +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1 +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3 +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0 +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2 +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0 +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2 +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0 +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2 +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0 +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2 +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0 +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2 +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0 +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2 +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0 +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2 +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0 +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2 +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0 +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1 +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2 +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0 +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1 +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0 +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1 +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3 +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4 +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0 +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1 +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3 +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4 +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0 +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1 +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2 +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3 +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4 +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0 +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1 +#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2 +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3 +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4 +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0 +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0 +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1 +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0 +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1 +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4 +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0 +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1 +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4 +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0 +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1 +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4 +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0 +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1 +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2 +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1 +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2 +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1 +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2 +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1 +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2 +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1 +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2 +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1 +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2 +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1 +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2 +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0 +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1 +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2 +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 +/*@}*/ + +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 +/*@}*/ + +#endif /* SC_PADS_H */ diff --git a/include/dt-bindings/pinctrl/pins-imx8mm.h b/include/dt-bindings/pinctrl/pins-imx8mm.h new file mode 100644 index 000000000000..a409b557f538 --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imx8mm.h @@ -0,0 +1,646 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_IMX8MM_PINFUNC_H +#define __DTS_IMX8MM_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ + +#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1B0 0x418 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_RX 0x1B0 0x418 0x4F4 0x4 0x2 +#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1B4 0x41C 0x4F4 0x4 0x3 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_TX 0x1B4 0x41C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_CTS_B 0x1B8 0x420 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_CTS_B 0x1BC 0x424 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 +#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 + +#endif /* __DTS_IMX8MM_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/pins-imx8mn.h b/include/dt-bindings/pinctrl/pins-imx8mn.h new file mode 100644 index 000000000000..559c542f44e2 --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imx8mn.h @@ -0,0 +1,648 @@ +/* + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, + * available at https://www.gnu.org/licenses/gpl-2.0.html. + * + */ +#ifndef __DTS_IMX8MN_PINFUNC_H +#define __DTS_IMX8MN_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x0020 0x025C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x0020 0x025C 0x055C 0x1 0x3 +#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x0024 0x0260 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x0024 0x0260 0x056C 0x1 0x3 +#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0028 0x0290 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x0028 0x0290 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0028 0x0290 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x0028 0x0290 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x002C 0x0294 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x002C 0x0294 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x002C 0x0294 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x002C 0x0294 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x0030 0x0298 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x0030 0x0298 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x0030 0x0298 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x0034 0x029C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x0034 0x029C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x0034 0x029C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x0034 0x029C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0038 0x02A0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0038 0x02A0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x0038 0x02A0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x0038 0x02A0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x003C 0x02A4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x003C 0x02A4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x003C 0x02A4 0x04BC 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x003C 0x02A4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0040 0x02A8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x0040 0x02A8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x0040 0x02A8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x0040 0x02A8 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0044 0x02AC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x0044 0x02AC 0x04C0 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x0044 0x02AC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x0044 0x02AC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0048 0x02B0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x0048 0x02B0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x0048 0x02B0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x0048 0x02B0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x0048 0x02B0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x004C 0x02B4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x004C 0x02B4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x004C 0x02B4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x004C 0x02B4 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x004C 0x02B4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x004C 0x02B4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0050 0x02B8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x0050 0x02B8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x0050 0x02B8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x0054 0x02BC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x0054 0x02BC 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x0054 0x02BC 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x0054 0x02BC 0x04BC 0x5 0x1 +#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x0054 0x02BC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x0058 0x02C0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x0058 0x02C0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x0058 0x02C0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x0058 0x02C0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x005C 0x02C4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x005C 0x02C4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x005C 0x02C4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x005C 0x02C4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0060 0x02C8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x0060 0x02C8 0x0598 0x4 0x2 +#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x0060 0x02C8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x0060 0x02C8 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0064 0x02CC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x0064 0x02CC 0x05B8 0x4 0x2 +#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x0064 0x02CC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x0064 0x02CC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x0068 0x02D0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x0068 0x02D0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x0068 0x02D0 0x0540 0x3 0x1 +#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x0068 0x02D0 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x0068 0x02D0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x0068 0x02D0 0x059C 0x6 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x006C 0x02D4 0x04C0 0x0 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x006C 0x02D4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x006C 0x02D4 0x053C 0x3 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x006C 0x02D4 0x05CC 0x4 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x006C 0x02D4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x006C 0x02D4 0x0550 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x0070 0x02D8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x0070 0x02D8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x0070 0x02D8 0x0538 0x3 0x1 +#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x0070 0x02D8 0x0568 0x4 0x1 +#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x0070 0x02D8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x0070 0x02D8 0x0584 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x0074 0x02DC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x0074 0x02DC 0x05A4 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0074 0x02DC 0x05A4 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x0074 0x02DC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x0074 0x02DC 0x0540 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x0074 0x02DC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x0074 0x02DC 0x054C 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x0078 0x02E0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x0078 0x02E0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x0078 0x02E0 0x053C 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x0078 0x02E0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x0078 0x02E0 0x0598 0x6 0x3 +#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x007C 0x02E4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x007C 0x02E4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x007C 0x02E4 0x0538 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x007C 0x02E4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x007C 0x02E4 0x05B8 0x6 0x3 +#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x0080 0x02E8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x0080 0x02E8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x0080 0x02E8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x0080 0x02E8 0x05B4 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x0084 0x02EC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x0084 0x02EC 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x0084 0x02EC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x0084 0x02EC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x0084 0x02EC 0x05B0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x0088 0x02F0 0x0574 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x0088 0x02F0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x0088 0x02F0 0x0540 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x0088 0x02F0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x0088 0x02F0 0x05E4 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x008C 0x02F4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x008C 0x02F4 0x05C8 0x1 0x0 +#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x008C 0x02F4 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x008C 0x02F4 0x053C 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x008C 0x02F4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x008C 0x02F4 0x05E0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x0090 0x02F8 0x057C 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x0090 0x02F8 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x0090 0x02F8 0x0538 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x0090 0x02F8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x0090 0x02F8 0x0558 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x0094 0x02FC 0x0554 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x0094 0x02FC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x0094 0x02FC 0x0534 0x3 0x1 +#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x0094 0x02FC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x0094 0x02FC 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x0098 0x0300 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x0098 0x0300 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x0098 0x0300 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x0098 0x0300 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x0098 0x0300 0x05A0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x009C 0x0304 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x009C 0x0304 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x009C 0x0304 0x05CC 0x3 0x5 +#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x009C 0x0304 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x009C 0x0304 0x05DC 0x6 0x1 +#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x00A0 0x0308 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x00A0 0x0308 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x00A0 0x0308 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x00A0 0x0308 0x04F4 0x4 0x4 +#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x00A0 0x0308 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x00A4 0x030C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x00A4 0x030C 0x04C0 0x1 0x3 +#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x00A4 0x030C 0x04F4 0x4 0x5 +#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x00A4 0x030C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x00A4 0x030C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x00A8 0x0310 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x00A8 0x0310 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x00A8 0x0310 0x04F0 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x00A8 0x0310 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x00A8 0x0310 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x00AC 0x0314 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x00AC 0x0314 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x00AC 0x0314 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x00AC 0x0314 0x04F0 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x00AC 0x0314 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x00B0 0x0318 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x00B0 0x0318 0x057C 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x00B0 0x0318 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x00B0 0x0318 0x04FC 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x00B0 0x0318 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x00B4 0x031C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x00B4 0x031C 0x0554 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x00B4 0x031C 0x04FC 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x00B4 0x031C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x00B4 0x031C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x00B8 0x0320 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x00B8 0x0320 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x00B8 0x0320 0x055C 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x00B8 0x0320 0x04F8 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x00B8 0x0320 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00B8 0x0320 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x00BC 0x0324 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x00BC 0x0324 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x00BC 0x0324 0x056C 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x00BC 0x0324 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x00BC 0x0324 0x04F8 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00BC 0x0324 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x00C0 0x0328 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x00C0 0x0328 0x0574 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x00C0 0x0328 0x05D0 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x00C0 0x0328 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x00C0 0x0328 0x0504 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00C0 0x0328 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x00C4 0x032C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x00C4 0x032C 0x05C8 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x00C4 0x032C 0x0560 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x00C4 0x032C 0x0504 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x00C4 0x032C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00C4 0x032C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x00C8 0x0330 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x00C8 0x0330 0x05A4 0x1 0x1 +#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x00C8 0x0330 0x05A4 0x1 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x00C8 0x0330 0x0588 0x3 0x1 +#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x00C8 0x0330 0x0500 0x4 0x2 +#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x00C8 0x0330 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x00C8 0x0330 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x00CC 0x0334 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x00CC 0x0334 0x05BC 0x3 0x1 +#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x00CC 0x0334 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x00CC 0x0334 0x0500 0x4 0x3 +#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x00CC 0x0334 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x00D0 0x0338 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x00D0 0x0338 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x00D0 0x0338 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x00D4 0x033C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x00D4 0x033C 0x04E4 0x1 0x1 +#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x00D4 0x033C 0x0580 0x2 0x1 +#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x00D4 0x033C 0x050C 0x3 0x4 +#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x00D4 0x033C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x00D4 0x033C 0x0594 0x4 0x1 +#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x00D4 0x033C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x00D4 0x033C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x00D8 0x0340 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x00D8 0x0340 0x04D0 0x1 0x1 +#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x00D8 0x0340 0x0590 0x2 0x1 +#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x00D8 0x0340 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x00D8 0x0340 0x050C 0x3 0x5 +#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x00D8 0x0340 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x00D8 0x0340 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x00D8 0x0340 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x00DC 0x0344 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x00DC 0x0344 0x04D4 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x00DC 0x0344 0x058C 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x00DC 0x0344 0x04FC 0x3 0x6 +#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x00DC 0x0344 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x00DC 0x0344 0x0534 0x4 0x2 +#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x00DC 0x0344 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x00DC 0x0344 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x00E0 0x0348 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x00E0 0x0348 0x04EC 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x00E0 0x0348 0x05D4 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x00E0 0x0348 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x00E0 0x0348 0x04FC 0x3 0x7 +#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x00E0 0x0348 0x0538 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x00E0 0x0348 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x00E0 0x0348 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x00E4 0x034C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x00E4 0x034C 0x04E8 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x00E4 0x034C 0x0570 0x2 0x2 +#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x00E4 0x034C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x00E4 0x034C 0x053C 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x00E4 0x034C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x00E4 0x034C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x00E8 0x0350 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x00E8 0x0350 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x00E8 0x0350 0x0578 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x00E8 0x0350 0x05CC 0x3 0x2 +#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x00E8 0x0350 0x0540 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x00E8 0x0350 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x00E8 0x0350 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x00EC 0x0354 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x00EC 0x0354 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x00EC 0x0354 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x00F0 0x0358 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x00F0 0x0358 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x00F0 0x0358 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00F4 0x035C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x00F4 0x035C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x00F4 0x035C 0x0534 0x3 0x3 +#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x00F4 0x035C 0x0504 0x4 0x6 +#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x00F4 0x035C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x00F4 0x035C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x00F4 0x035C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00F8 0x0360 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x00F8 0x0360 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x00F8 0x0360 0x0538 0x3 0x5 +#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x00F8 0x0360 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x00F8 0x0360 0x0504 0x4 0x7 +#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00F8 0x0360 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x00F8 0x0360 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00FC 0x0364 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x00FC 0x0364 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x00FC 0x0364 0x059C 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x00FC 0x0364 0x0534 0x3 0x4 +#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x00FC 0x0364 0x05D4 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x00FC 0x0364 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x00FC 0x0364 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x0100 0x0368 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x0100 0x0368 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x0100 0x0368 0x0550 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x0100 0x0368 0x0538 0x3 0x6 +#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x0100 0x0368 0x058C 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x0100 0x0368 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x0100 0x0368 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x0104 0x036C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x0104 0x036C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x0104 0x036C 0x0584 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x0104 0x036C 0x053C 0x3 0x5 +#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x0104 0x036C 0x05BC 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x0104 0x036C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x0104 0x036C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x0108 0x0370 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x0108 0x0370 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x0108 0x0370 0x054C 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x0108 0x0370 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x0108 0x0370 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x010C 0x0374 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x010C 0x0374 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x010C 0x0374 0x053C 0x3 0x6 +#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x010C 0x0374 0x050C 0x4 0x6 +#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x010C 0x0374 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x010C 0x0374 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x010C 0x0374 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x0110 0x0378 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x0110 0x0378 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x0110 0x0378 0x0540 0x3 0x5 +#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x0110 0x0378 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x0110 0x0378 0x050C 0x4 0x7 +#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x0110 0x0378 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x0110 0x0378 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x0114 0x037C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x0114 0x037C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x0114 0x037C 0x0598 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x0114 0x037C 0x058C 0x4 0x3 +#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0114 0x037C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x0114 0x037C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x0118 0x0380 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x0118 0x0380 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x0118 0x0380 0x05B8 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0118 0x0380 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x0118 0x0380 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x011C 0x0384 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x011C 0x0384 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x011C 0x0384 0x05B4 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x011C 0x0384 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x011C 0x0384 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x0120 0x0388 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x0120 0x0388 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x0120 0x0388 0x05B0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x0120 0x0388 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x0120 0x0388 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x0124 0x038C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x0124 0x038C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x0124 0x038C 0x05E4 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x0124 0x038C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x0124 0x038C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x0128 0x0390 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x0128 0x0390 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x0128 0x0390 0x05E0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x0128 0x0390 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x0128 0x0390 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x012C 0x0394 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x012C 0x0394 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x012C 0x0394 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x012C 0x0394 0x0588 0x4 0x2 +#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x012C 0x0394 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x012C 0x0394 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x0130 0x0398 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x0130 0x0398 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x0130 0x0398 0x0558 0x2 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x0130 0x0398 0x0538 0x3 0x7 +#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x0130 0x0398 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x0130 0x0398 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x0134 0x039C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x0134 0x039C 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x0134 0x039C 0x0540 0x3 0x6 +#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x0134 0x039C 0x0588 0x4 0x3 +#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x0134 0x039C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x0134 0x039C 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x0138 0x03A0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x0138 0x03A0 0x05A0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x0138 0x03A0 0x05BC 0x4 0x3 +#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x0138 0x03A0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x0138 0x03A0 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x013C 0x03A4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x013C 0x03A4 0x05DC 0x2 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x013C 0x03A4 0x058C 0x4 0x4 +#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x013C 0x03A4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x013C 0x03A4 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x0140 0x03A8 0x04E4 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0140 0x03A8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x0144 0x03AC 0x04D0 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x0144 0x03AC 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x0144 0x03AC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0148 0x03B0 0x04D4 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x0148 0x03B0 0x0534 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x0148 0x03B0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x014C 0x03B4 0x04D8 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x014C 0x03B4 0x04EC 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x014C 0x03B4 0x0538 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x014C 0x03B4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x0150 0x03B8 0x04DC 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x0150 0x03B8 0x04E8 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x0150 0x03B8 0x053C 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x0150 0x03B8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x0154 0x03BC 0x04E0 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x0154 0x03BC 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x0154 0x03BC 0x0540 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x0154 0x03BC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x0158 0x03C0 0x0594 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0158 0x03C0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x01B0 0x0418 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x01B0 0x0418 0x04EC 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x01B0 0x0418 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x01B0 0x0418 0x05AC 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x01B0 0x0418 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x01B0 0x0418 0x04F4 0x4 0x2 +#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x01B0 0x0418 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x01B0 0x0418 0x053C 0x6 0x7 +#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x01B4 0x041C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x01B4 0x041C 0x04E8 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x01B4 0x041C 0x04F4 0x4 0x3 +#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x01B4 0x041C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x01B4 0x041C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x01B4 0x041C 0x0538 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x01B8 0x0420 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x01B8 0x0420 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x01B8 0x0420 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x01B8 0x0420 0x04F0 0x4 0x2 +#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x01B8 0x0420 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x01B8 0x0420 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x01B8 0x0420 0x0540 0x6 0x7 +#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x01BC 0x0424 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x01BC 0x0424 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x01BC 0x0424 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x01BC 0x0424 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x01BC 0x0424 0x04F0 0x4 0x3 +#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x01BC 0x0424 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x01BC 0x0424 0x053C 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x01C0 0x0428 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x01C0 0x0428 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x01C0 0x0428 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x01C0 0x0428 0x0538 0x6 0x9 +#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x01C4 0x042C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x01C4 0x042C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x01C4 0x042C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x01C4 0x042C 0x0540 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x01C8 0x0430 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x01C8 0x0430 0x0594 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x01C8 0x0430 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x01C8 0x0430 0x05C0 0x6 0x1 +#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x01CC 0x0434 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x01CC 0x0434 0x05F0 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x01CC 0x0434 0x04E4 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x01CC 0x0434 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x01CC 0x0434 0x05CC 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x01CC 0x0434 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x01CC 0x0434 0x0534 0x6 0x5 +#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x01D0 0x0438 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x01D0 0x0438 0x05E8 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x01D0 0x0438 0x04D0 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x01D0 0x0438 0x05AC 0x3 0x2 +#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x01D0 0x0438 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x01D0 0x0438 0x04F8 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x01D0 0x0438 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x01D0 0x0438 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x01D4 0x043C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x01D4 0x043C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x01D4 0x043C 0x04D4 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x01D4 0x043C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x01D4 0x043C 0x04F8 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x01D4 0x043C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x01D4 0x043C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x01D4 0x043C 0x0538 0x6 0x10 +#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x01D8 0x0440 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x01D8 0x0440 0x05EC 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x01D8 0x0440 0x04D8 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x01D8 0x0440 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x01D8 0x0440 0x04FC 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x01D8 0x0440 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x01D8 0x0440 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x01D8 0x0440 0x0540 0x6 0x9 +#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x01DC 0x0444 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x01DC 0x0444 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x01DC 0x0444 0x04DC 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x01DC 0x0444 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x01DC 0x0444 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x01DC 0x0444 0x04FC 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x01DC 0x0444 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x01DC 0x0444 0x053C 0x6 0x9 +#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x01E0 0x0448 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x01E0 0x0448 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x01E0 0x0448 0x04E0 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x01E0 0x0448 0x0568 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x01E0 0x0448 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x01E0 0x0448 0x0000 0x6 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x01E4 0x044C 0x05C0 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x01E4 0x044C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x01E4 0x044C 0x0594 0x2 0x3 +#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x01E4 0x044C 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x01E4 0x044C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x01E4 0x044C 0x05CC 0x6 0x4 +#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x01E8 0x0450 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x01E8 0x0450 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x01E8 0x0450 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x01EC 0x0454 0x05CC 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x01EC 0x0454 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x01EC 0x0454 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x01F0 0x0458 0x0568 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x01F0 0x0458 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x01F0 0x0458 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x01F4 0x045C 0x05D8 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x01F4 0x045C 0x0504 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x01F4 0x045C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x01F4 0x045C 0x055C 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x01F4 0x045C 0x04DC 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x01F4 0x045C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x01F8 0x0460 0x05A8 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x01F8 0x0460 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x01F8 0x0460 0x0504 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x01F8 0x0460 0x056C 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x01F8 0x0460 0x04D0 0x3 0x3 +#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x01F8 0x0460 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x01FC 0x0464 0x05C4 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x01FC 0x0464 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x01FC 0x0464 0x0500 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x01FC 0x0464 0x05D0 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x01FC 0x0464 0x04D4 0x3 0x3 +#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x01FC 0x0464 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x0200 0x0468 0x0564 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x0200 0x0468 0x0500 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x0200 0x0468 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x0200 0x0468 0x0560 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x0200 0x0468 0x04D8 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x0200 0x0468 0x04EC 0x4 0x3 +#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0200 0x0468 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0204 0x046C 0x0580 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x0204 0x046C 0x050C 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x0204 0x046C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x0204 0x046C 0x0588 0x2 0x4 +#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x0204 0x046C 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x0204 0x046C 0x04E8 0x4 0x3 +#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x0204 0x046C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0208 0x0470 0x0590 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x0208 0x0470 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x0208 0x0470 0x050C 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x0208 0x0470 0x05BC 0x2 0x4 +#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x0208 0x0470 0x04E0 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x0208 0x0470 0x0000 0x4 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x0208 0x0470 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x020C 0x0474 0x0578 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x020C 0x0474 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x020C 0x0474 0x0508 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x020C 0x0474 0x05D4 0x2 0x3 +#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x020C 0x0474 0x0594 0x3 0x4 +#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x020C 0x0474 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x0210 0x0478 0x0570 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x0210 0x0478 0x0508 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x0210 0x0478 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x0210 0x0478 0x058C 0x2 0x5 +#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0210 0x0478 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x0214 0x047C 0x055C 0x0 0x0 +#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x0214 0x047C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x0214 0x047C 0x05D8 0x3 0x1 +#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x0214 0x047C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x0218 0x0480 0x056C 0x0 0x0 +#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x0218 0x0480 0x04C0 0x1 0x2 +#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x0218 0x0480 0x05A8 0x3 0x1 +#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x0218 0x0480 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x021C 0x0484 0x05D0 0x0 0x0 +#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x021C 0x0484 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x021C 0x0484 0x0598 0x2 0x1 +#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x021C 0x0484 0x05C4 0x3 0x1 +#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x021C 0x0484 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x0220 0x0488 0x0560 0x0 0x0 +#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x0220 0x0488 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x0220 0x0488 0x05B8 0x2 0x1 +#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x0220 0x0488 0x0564 0x3 0x1 +#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x0220 0x0488 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x0224 0x048C 0x0588 0x0 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x0224 0x048C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x0224 0x048C 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x0224 0x048C 0x0580 0x3 0x2 +#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x0224 0x048C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x0228 0x0490 0x05BC 0x0 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x0228 0x0490 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x0228 0x0490 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x0228 0x0490 0x0590 0x3 0x2 +#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x0228 0x0490 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x022C 0x0494 0x05D4 0x0 0x0 +#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x022C 0x0494 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x022C 0x0494 0x0578 0x3 0x2 +#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x022C 0x0494 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x0230 0x0498 0x058C 0x0 0x0 +#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x0230 0x0498 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x0230 0x0498 0x0570 0x3 0x1 +#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x0230 0x0498 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x0234 0x049C 0x04F4 0x0 0x0 +#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x0234 0x049C 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x0234 0x049C 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x0234 0x049C 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x0238 0x04A0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x0238 0x04A0 0x04F4 0x0 0x1 +#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x0238 0x04A0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x0238 0x04A0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x023C 0x04A4 0x04FC 0x0 0x0 +#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x023C 0x04A4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x023C 0x04A4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x023C 0x04A4 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x023C 0x04A4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x0240 0x04A8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x0240 0x04A8 0x04FC 0x0 0x1 +#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x0240 0x04A8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x0240 0x04A8 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x0240 0x04A8 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x0244 0x04AC 0x0504 0x0 0x2 +#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x0244 0x04AC 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x0244 0x04AC 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x0244 0x04AC 0x04F0 0x1 0x0 +#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x0244 0x04AC 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x0244 0x04AC 0x05EC 0x3 0x1 +#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x0244 0x04AC 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x0248 0x04B0 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x0248 0x04B0 0x0504 0x0 0x3 +#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x0248 0x04B0 0x04F0 0x1 0x1 +#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x0248 0x04B0 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x0248 0x04B0 0x0000 0x2 0x0 +#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x0248 0x04B0 0x05E8 0x3 0x1 +#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x0248 0x04B0 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x024C 0x04B4 0x050C 0x0 0x2 +#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x024C 0x04B4 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x024C 0x04B4 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x024C 0x04B4 0x04F8 0x1 0x0 +#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x024C 0x04B4 0x0000 0x3 0x0 +#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x024C 0x04B4 0x0000 0x5 0x0 +#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0250 0x04B8 0x0000 0x0 0x0 +#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x0250 0x04B8 0x050C 0x0 0x3 +#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x0250 0x04B8 0x04F8 0x1 0x1 +#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x0250 0x04B8 0x0000 0x1 0x0 +#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x0250 0x04B8 0x05F0 0x3 0x1 +#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x0250 0x04B8 0x0000 0x5 0x0 + +#endif /* __DTS_IMX8MN_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/pins-imx8mq.h b/include/dt-bindings/pinctrl/pins-imx8mq.h new file mode 100644 index 000000000000..498b76f11989 --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imx8mq.h @@ -0,0 +1,632 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_IMX8MQ_PINFUNC_H +#define __DTS_IMX8MQ_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ + +#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 +#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 +#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 +#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 +#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 +#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x12 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 +#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 +#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 +#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 + +#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/include/dt-bindings/reset/imx8mm-dispmix.h b/include/dt-bindings/reset/imx8mm-dispmix.h new file mode 100644 index 000000000000..3af137b1bfe2 --- /dev/null +++ b/include/dt-bindings/reset/imx8mm-dispmix.h @@ -0,0 +1,49 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __IMX8MM_DISPMIX_H__ +#define __IMX8MM_DISPMIX_H__ + +/* DISPMIX soft reset */ +#define IMX8MM_CSI_BRIDGE_CHIP_RESET 0 +#define IMX8MM_CSI_BRIDGE_IPG_HARD_ASYNC_RESET 1 +#define IMX8MM_CSI_BRIDGE_CSI_HRESET 2 +#define IMX8MM_CAMERA_PIXEL_RESET 3 +#define IMX8MM_MIPI_CSI_I_PRESET 4 +#define IMX8MM_MIPI_DSI_I_PRESET 5 +#define IMX8MM_BUS_RSTN_BLK_SYNC 6 +#define IMX8MM_DISPMIX_SFT_RSTN_NUM 7 + +/* DISPMIX clock soft enable */ +#define IMX8MM_CSI_BRIDGE_CSI_HCLK_EN 0 +#define IMX8MM_CSI_BRIDGE_SPU_CLK_EN 1 +#define IMX8MM_CSI_BRIDGE_MEM_WRAPPER_CLK_EN 2 +#define IMX8MM_CSI_BRIDGE_IPG_CLK_EN 3 +#define IMX8MM_CSI_BRIDGE_IPG_CLK_S_EN 4 +#define IMX8MM_CSI_BRIDGE_IPG_CLK_S_RAW_EN 5 +#define IMX8MM_LCDIF_APB_CLK_EN 6 +#define IMX8MM_LCDIF_PIXEL_CLK_EN 7 +#define IMX8MM_MIPI_DSI_PCLK_EN 8 +#define IMX8MM_MIPI_DSI_CLKREF_EN 9 +#define IMX8MM_MIPI_CSI_ACLK_EN 10 +#define IMX8MM_MIPI_CSI_PCLK_EN 11 +#define IMX8MM_BUS_BLK_CLK_EN 12 +#define IMX8MM_DISPMIX_CLK_EN_NUM 13 + +/* MIPI reset */ +#define IMX8MM_MIPI_S_RESET 0 +#define IMX8MM_MIPI_M_RESET 1 +#define IMX8MM_MIPI_RESET_NUM 2 + +#endif diff --git a/include/dt-bindings/reset/imx8mn-dispmix.h b/include/dt-bindings/reset/imx8mn-dispmix.h new file mode 100644 index 000000000000..8703ebe7d4b2 --- /dev/null +++ b/include/dt-bindings/reset/imx8mn-dispmix.h @@ -0,0 +1,47 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __IMX8MN_DISPMIX_H__ +#define __IMX8MN_DISPMIX_H__ + +/* DISPMIX soft reset */ +#define IMX8MN_MIPI_DSI_PCLK_RESET 0 +#define IMX8MN_MIPI_DSI_CLKREF_RESET 1 +#define IMX8MN_MIPI_CSI_PCLK_RESET 2 +#define IMX8MN_MIPI_CSI_ACLK_RESET 3 +#define IMX8MN_LCDIF_PIXEL_CLK_RESET 4 +#define IMX8MN_LCDIF_APB_CLK_RESET 5 +#define IMX8MN_ISI_PROC_CLK_RESET 6 +#define IMX8MN_ISI_APB_CLK_RESET 7 +#define IMX8MN_BUS_BLK_CLK_RESET 8 +#define IMX8MN_DISPMIX_SFT_RSTN_NUM 9 + +/* DISPMIX clock soft enable */ +#define IMX8MN_MIPI_DSI_PCLK_EN 0 +#define IMX8MN_MIPI_DSI_CLKREF_EN 1 +#define IMX8MN_MIPI_CSI_PCLK_EN 2 +#define IMX8MN_MIPI_CSI_ACLK_EN 3 +#define IMX8MN_LCDIF_PIXEL_CLK_EN 4 +#define IMX8MN_LCDIF_APB_CLK_EN 5 +#define IMX8MN_ISI_PROC_CLK_EN 6 +#define IMX8MN_ISI_APB_CLK_EN 7 +#define IMX8MN_BUS_BLK_CLK_EN 8 +#define IMX8MN_DISPMIX_CLK_EN_NUM 9 + +/* MIPI reset */ +#define IMX8MN_MIPI_S_RESET 0 +#define IMX8MN_MIPI_M_RESET 1 +#define IMX8MN_MIPI_RESET_NUM 2 + +#endif diff --git a/include/dt-bindings/soc/imx8_hsio.h b/include/dt-bindings/soc/imx8_hsio.h new file mode 100644 index 000000000000..a237ceb82620 --- /dev/null +++ b/include/dt-bindings/soc/imx8_hsio.h @@ -0,0 +1,31 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IMX8_HSIO_H +#define __DT_BINDINGS_IMX8_HSIO_H + +/* + * imx8qm hsio has pciea, pcieb and sata modules, and hsio + * can be configured to the following different work modes. + * 1 - pciea 2 lanes and one sata ahci port. + * 2 - pciea 1 lane, pcieb 1 lane and one sata ahci port. + * 3 - pciea 2 lanes, pcieb 1 lane. + * Choose one mode, refer to the exact hardware board design. + */ +#define PCIEAX2SATA 1 +#define PCIEAX1PCIEBX1SATA 2 +#define PCIEAX2PCIEBX1 3 + +#endif /* __DT_BINDINGS_IMX8_HSIO_H */ + diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h new file mode 100644 index 000000000000..f5348fd80ad1 --- /dev/null +++ b/include/dt-bindings/soc/imx8_pd.h @@ -0,0 +1,221 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IMX8_PD_H +#define __DT_BINDINGS_IMX8_PD_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 +#define PD_LVDS0 lvds0_power_domain +#define PD_LVDS0_I2C0 lvds0_i2c0 +#define PD_LVDS0_I2C1 lvds0_i2c1 +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_PWM lvds0_pwm +#define PD_LVDS0_GPIO lvds0_gpio +#define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 +#define PD_LVDS1 lvds1_power_domain +#define PD_LVDS1_I2C0 lvds1_i2c0 +#define PD_LVDS1_I2C1 lvds1_i2c1 +#define PD_LVDS1_PWM lvds1_pwm +#define PD_LVDS1_GPIO lvds1_gpio + +#define PD_DMA dma_power_domain +#define PD_DMA_SPI_0 dma_spi0 +#define PD_DMA_SPI_1 dma_spi1 +#define PD_DMA_SPI_2 dma_spi2 +#define PD_DMA_SPI_3 dma_spi3 +#define PD_DMA_UART0 dma_lpuart0 +#define PD_DMA_UART1 dma_lpuart1 +#define PD_DMA_UART2 dma_lpuart2 +#define PD_DMA_UART3 dma_lpuart3 +#define PD_DMA_UART4 dma_lpuart4 +#define PD_DMA_EMVSIM_0 dma_emvsim0 +#define PD_DMA_EMVSIM_1 dma_emvsim1 +#define PD_DMA_I2C_0 dma_lpi2c0 +#define PD_DMA_I2C_1 dma_lpi2c1 +#define PD_DMA_I2C_2 dma_lpi2c2 +#define PD_DMA_I2C_3 dma_lpi2c3 +#define PD_DMA_I2C_4 dma_lpi2c4 +#define PD_DMA_ADC_0 dma_adc0 +#define PD_DMA_ADC_1 dma_adc1 +#define PD_DMA_FTM_0 dma_ftm0 +#define PD_DMA_FTM_1 dma_ftm1 +#define PD_DMA_CAN_0 dma_flexcan0 +#define PD_DMA_CAN_1 dma_flexcan1 +#define PD_DMA_CAN_2 dma_flexcan2 +#define PD_DMA_PWM_0 dma_pwm0 +#define PD_DMA_LCD_0 dma_lcd0 +#define PD_DMA_ELCDIF_PLL dma_elcdif_pll + +#define PD_HSIO hsio_power_domain +#define PD_HSIO_PCIE_A hsio_pcie0 +#define PD_HSIO_PCIE_B hsio_pcie1 +#define PD_HSIO_SATA_0 hsio_sata0 +#define PD_HSIO_GPIO hsio_gpio +#define PD_HSIO_SERDES_0 hsio_serdes_0 +#define PD_HSIO_SERDES_1 hsio_serdes_1 + +#define PD_LCD_0 lcd0_power_domain +#define PD_LCD_0_I2C_0 lcd0_i2c0 +#define PD_LCD_0_I2C_1 lcd0_i2c1 +#define PD_LCD_PWM_0 lcd0_pwm0 + +#define PD_LSIO lsio_power_domain +#define PD_LSIO_GPIO_0 lsio_gpio0 +#define PD_LSIO_GPIO_1 lsio_gpio1 +#define PD_LSIO_GPIO_2 lsio_gpio2 +#define PD_LSIO_GPIO_3 lsio_gpio3 +#define PD_LSIO_GPIO_4 lsio_gpio4 +#define PD_LSIO_GPIO_5 lsio_gpio5 +#define PD_LSIO_GPIO_6 lsio_gpio6 +#define PD_LSIO_GPIO_7 lsio_gpio7 +#define PD_LSIO_GPT_0 lsio_gpt0 +#define PD_LSIO_GPT_1 lsio_gpt1 +#define PD_LSIO_GPT_2 lsio_gpt2 +#define PD_LSIO_GPT_3 lsio_gpt3 +#define PD_LSIO_GPT_4 lsio_gpt4 +#define PD_LSIO_KPP lsio_kpp +#define PD_LSIO_FSPI_0 lsio_fspi0 +#define PD_LSIO_FSPI_1 lsio_fspi1 +#define PD_LSIO_PWM_0 lsio_pwm0 +#define PD_LSIO_PWM_1 lsio_pwm1 +#define PD_LSIO_PWM_2 lsio_pwm2 +#define PD_LSIO_PWM_3 lsio_pwm3 +#define PD_LSIO_PWM_4 lsio_pwm4 +#define PD_LSIO_PWM_5 lsio_pwm5 +#define PD_LSIO_PWM_6 lsio_pwm6 +#define PD_LSIO_PWM_7 lsio_pwm7 +#define PD_LSIO_MU5A lsio_mu5a +#define PD_LSIO_MU6A lsio_mu6a + +#define PD_CONN connectivity_power_domain +#define PD_CONN_SDHC_0 conn_sdhc0 +#define PD_CONN_SDHC_1 conn_sdhc1 +#define PD_CONN_SDHC_2 conn_sdhc2 +#define PD_CONN_ENET_0 conn_enet0 +#define PD_CONN_ENET_1 conn_enet1 +#define PD_CONN_MLB_0 conn_mlb0 +#define PD_CONN_DMA_4_CH0 conn_dma4_ch0 +#define PD_CONN_DMA_4_CH1 conn_dma4_ch1 +#define PD_CONN_DMA_4_CH2 conn_dma4_ch2 +#define PD_CONN_DMA_4_CH3 conn_dma4_ch3 +#define PD_CONN_DMA_4_CH4 conn_dma4_ch4 +#define PD_CONN_USB_0 conn_usb0 +#define PD_CONN_USB_1 conn_usb1 +#define PD_CONN_USB_0_PHY conn_usb0_phy +#define PD_CONN_USB_2 conn_usb2 +#define PD_CONN_USB_2_PHY conn_usb2_phy +#define PD_CONN_NAND conn_nand + +#define PD_AUDIO audio_power_domain +#define PD_AUD_SAI_0 audio_sai0 +#define PD_AUD_SAI_1 audio_sai1 +#define PD_AUD_SAI_2 audio_sai2 +#define PD_AUD_ASRC_0 audio_asrc0 +#define PD_AUD_ASRC_1 audio_asrc1 +#define PD_AUD_ESAI_0 audio_esai0 +#define PD_AUD_ESAI_1 audio_esai1 +#define PD_AUD_SPDIF_0 audio_spdif0 +#define PD_AUD_SPDIF_1 audio_spdif1 +#define PD_AUD_SAI_3 audio_sai3 +#define PD_AUD_SAI_4 audio_sai4 +#define PD_AUD_SAI_5 audio_sai5 +#define PD_AUD_SAI_6 audio_sai6 +#define PD_AUD_SAI_7 audio_sai7 +#define PD_AUD_GPT_5 audio_gpt5 +#define PD_AUD_GPT_6 audio_gpt6 +#define PD_AUD_GPT_7 audio_gpt7 +#define PD_AUD_GPT_8 audio_gpt8 +#define PD_AUD_GPT_9 audio_gpt9 +#define PD_AUD_GPT_10 audio_gpt10 +#define PD_AUD_AMIX audio_amix +#define PD_AUD_MQS_0 audio_mqs0 +#define PD_AUD_DSP audio_dsp +#define PD_AUD_OCRAM audio_ocram +#define PD_AUD_MCLK_OUT_0 audio_mclkout0 +#define PD_AUD_MCLK_OUT_1 audio_mclkout1 +#define PD_AUD_AUDIO_PLL_0 audio_audiopll0 +#define PD_AUD_AUDIO_PLL_1 audio_audiopll1 +#define PD_AUD_AUDIO_CLK_0 audio_audioclk0 +#define PD_AUD_AUDIO_CLK_1 audio_audioclk1 + +#define PD_IMAGING imaging_power_domain +#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec +#define PD_IMAGING_JPEG_ENC imaging_jpeg_enc +#define PD_IMAGING_PDMA0 PD_IMAGING +#define PD_IMAGING_PDMA1 imaging_pdma1 +#define PD_IMAGING_PDMA2 imaging_pdma2 +#define PD_IMAGING_PDMA3 imaging_pdma3 +#define PD_IMAGING_PDMA4 imaging_pdma4 +#define PD_IMAGING_PDMA5 imaging_pdma5 +#define PD_IMAGING_PDMA6 imaging_pdma6 +#define PD_IMAGING_PDMA7 imaging_pdma7 + +#define PD_MIPI_0_DSI mipi0_dsi_power_domain +#define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0 +#define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1 +#define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0 +#define PD_MIPI_1_DSI mipi1_dsi_power_domain +#define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0 +#define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1 +#define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0 + +#define PD_MIPI_CSI0 mipi_csi0_power_domain +#define PD_MIPI_CSI0_PWM mipi_csi0_pwm +#define PD_MIPI_CSI0_I2C0 mipi_csi0_i2c0 +#define PD_MIPI_CSI1 mipi_csi1_power_domain +#define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm +#define PD_MIPI_CSI1_I2C0 mipi_csi1_i2c0 + +#define PD_PARALLEL_CSI parallel_csi_power_domain +#define PD_PARALLEL_CSI_I2C parallel_csi_i2c +#define PD_PARALLEL_CSI_PWM parallel_csi_pwm +#define PD_PARALLEL_CSI_PLL parallel_csi_pll + +#define PD_HDMI hdmi_power_domain +#define PD_HDMI_PLL_0 hdmi_pll0 +#define PD_HDMI_PLL_1 hdmi_pll1 +#define PD_HDMI_I2C_0 hdmi_i2c +#define PD_HDMI_I2S_0 hdmi_i2s +#define PD_HDMI_PWM_0 hdmi_pwm +#define PD_HDMI_GPIO_0 hdmi_gpio + +#define PD_HDMI_RX hdmi_rx_power_domain +#define PD_HDMI_RX_BYPASS hdmi_rx_bypass +#define PD_HDMI_RX_I2C hdmi_rx_i2c +#define PD_HDMI_RX_PWM hdmi_rx_pwm + +#define PD_CM40 cm40_power_domain +#define PD_CM40_I2C cm40_i2c +#define PD_CM40_INTMUX cm40_intmux +#define PD_CM41 cm41_power_domain +#define PD_CM41_I2C cm41_i2c +#define PD_CM41_INTMUX cm41_intmux + +#define PD_CAAM caam_power_domain +#define PD_CAAM_JR1 caam_job_ring1 +#define PD_CAAM_JR2 caam_job_ring2 +#define PD_CAAM_JR3 caam_job_ring3 + +#endif /* __DT_BINDINGS_IMX8_PD_H */ + diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h new file mode 100644 index 000000000000..9a20839f5806 --- /dev/null +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -0,0 +1,565 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef DT_BINDINGS_RSCRC_IMX_H +#define DT_BINDINGS_RSCRC_IMX_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define SC_R_A53 0 +#define SC_R_A53_0 1 +#define SC_R_A53_1 2 +#define SC_R_A53_2 3 +#define SC_R_A53_3 4 +#define SC_R_A72 5 +#define SC_R_A72_0 6 +#define SC_R_A72_1 7 +#define SC_R_A72_2 8 +#define SC_R_A72_3 9 +#define SC_R_CCI 10 +#define SC_R_DB 11 +#define SC_R_DRC_0 12 +#define SC_R_DRC_1 13 +#define SC_R_GIC_SMMU 14 +#define SC_R_IRQSTR_M4_0 15 +#define SC_R_IRQSTR_M4_1 16 +#define SC_R_SMMU 17 +#define SC_R_GIC 18 +#define SC_R_DC_0_BLIT0 19 +#define SC_R_DC_0_BLIT1 20 +#define SC_R_DC_0_BLIT2 21 +#define SC_R_DC_0_BLIT_OUT 22 +#define SC_R_PERF 23 +#define SC_R_USB_1_PHY 24 +#define SC_R_DC_0_WARP 25 +#define SC_R_V2X_MU_0 26 +#define SC_R_V2X_MU_1 27 +#define SC_R_DC_0_VIDEO0 28 +#define SC_R_DC_0_VIDEO1 29 +#define SC_R_DC_0_FRAC0 30 +#define SC_R_V2X_MU_2 31 +#define SC_R_DC_0 32 +#define SC_R_GPU_2_PID0 33 +#define SC_R_DC_0_PLL_0 34 +#define SC_R_DC_0_PLL_1 35 +#define SC_R_DC_1_BLIT0 36 +#define SC_R_DC_1_BLIT1 37 +#define SC_R_DC_1_BLIT2 38 +#define SC_R_DC_1_BLIT_OUT 39 +#define SC_R_V2X_MU_3 40 +#define SC_R_V2X_MU_4 41 +#define SC_R_DC_1_WARP 42 +#define SC_R_TBU_CTL 43 +#define SC_R_SECVIO 44 +#define SC_R_DC_1_VIDEO0 45 +#define SC_R_DC_1_VIDEO1 46 +#define SC_R_DC_1_FRAC0 47 +#define SC_R_UNUSED13 48 +#define SC_R_DC_1 49 +#define SC_R_UNUSED14 50 +#define SC_R_DC_1_PLL_0 51 +#define SC_R_DC_1_PLL_1 52 +#define SC_R_SPI_0 53 +#define SC_R_SPI_1 54 +#define SC_R_SPI_2 55 +#define SC_R_SPI_3 56 +#define SC_R_UART_0 57 +#define SC_R_UART_1 58 +#define SC_R_UART_2 59 +#define SC_R_UART_3 60 +#define SC_R_UART_4 61 +#define SC_R_EMVSIM_0 62 +#define SC_R_EMVSIM_1 63 +#define SC_R_DMA_0_CH0 64 +#define SC_R_DMA_0_CH1 65 +#define SC_R_DMA_0_CH2 66 +#define SC_R_DMA_0_CH3 67 +#define SC_R_DMA_0_CH4 68 +#define SC_R_DMA_0_CH5 69 +#define SC_R_DMA_0_CH6 70 +#define SC_R_DMA_0_CH7 71 +#define SC_R_DMA_0_CH8 72 +#define SC_R_DMA_0_CH9 73 +#define SC_R_DMA_0_CH10 74 +#define SC_R_DMA_0_CH11 75 +#define SC_R_DMA_0_CH12 76 +#define SC_R_DMA_0_CH13 77 +#define SC_R_DMA_0_CH14 78 +#define SC_R_DMA_0_CH15 79 +#define SC_R_DMA_0_CH16 80 +#define SC_R_DMA_0_CH17 81 +#define SC_R_DMA_0_CH18 82 +#define SC_R_DMA_0_CH19 83 +#define SC_R_DMA_0_CH20 84 +#define SC_R_DMA_0_CH21 85 +#define SC_R_DMA_0_CH22 86 +#define SC_R_DMA_0_CH23 87 +#define SC_R_DMA_0_CH24 88 +#define SC_R_DMA_0_CH25 89 +#define SC_R_DMA_0_CH26 90 +#define SC_R_DMA_0_CH27 91 +#define SC_R_DMA_0_CH28 92 +#define SC_R_DMA_0_CH29 93 +#define SC_R_DMA_0_CH30 94 +#define SC_R_DMA_0_CH31 95 +#define SC_R_I2C_0 96 +#define SC_R_I2C_1 97 +#define SC_R_I2C_2 98 +#define SC_R_I2C_3 99 +#define SC_R_I2C_4 100 +#define SC_R_ADC_0 101 +#define SC_R_ADC_1 102 +#define SC_R_FTM_0 103 +#define SC_R_FTM_1 104 +#define SC_R_CAN_0 105 +#define SC_R_CAN_1 106 +#define SC_R_CAN_2 107 +#define SC_R_DMA_1_CH0 108 +#define SC_R_DMA_1_CH1 109 +#define SC_R_DMA_1_CH2 110 +#define SC_R_DMA_1_CH3 111 +#define SC_R_DMA_1_CH4 112 +#define SC_R_DMA_1_CH5 113 +#define SC_R_DMA_1_CH6 114 +#define SC_R_DMA_1_CH7 115 +#define SC_R_DMA_1_CH8 116 +#define SC_R_DMA_1_CH9 117 +#define SC_R_DMA_1_CH10 118 +#define SC_R_DMA_1_CH11 119 +#define SC_R_DMA_1_CH12 120 +#define SC_R_DMA_1_CH13 121 +#define SC_R_DMA_1_CH14 122 +#define SC_R_DMA_1_CH15 123 +#define SC_R_DMA_1_CH16 124 +#define SC_R_DMA_1_CH17 125 +#define SC_R_DMA_1_CH18 126 +#define SC_R_DMA_1_CH19 127 +#define SC_R_DMA_1_CH20 128 +#define SC_R_DMA_1_CH21 129 +#define SC_R_DMA_1_CH22 130 +#define SC_R_DMA_1_CH23 131 +#define SC_R_DMA_1_CH24 132 +#define SC_R_DMA_1_CH25 133 +#define SC_R_DMA_1_CH26 134 +#define SC_R_DMA_1_CH27 135 +#define SC_R_DMA_1_CH28 136 +#define SC_R_DMA_1_CH29 137 +#define SC_R_DMA_1_CH30 138 +#define SC_R_DMA_1_CH31 139 +#define SC_R_V2X_PID0 140 +#define SC_R_V2X_PID1 141 +#define SC_R_V2X_PID2 142 +#define SC_R_V2X_PID3 143 +#define SC_R_GPU_0_PID0 144 +#define SC_R_GPU_0_PID1 145 +#define SC_R_GPU_0_PID2 146 +#define SC_R_GPU_0_PID3 147 +#define SC_R_GPU_1_PID0 148 +#define SC_R_GPU_1_PID1 149 +#define SC_R_GPU_1_PID2 150 +#define SC_R_GPU_1_PID3 151 +#define SC_R_PCIE_A 152 +#define SC_R_SERDES_0 153 +#define SC_R_MATCH_0 154 +#define SC_R_MATCH_1 155 +#define SC_R_MATCH_2 156 +#define SC_R_MATCH_3 157 +#define SC_R_MATCH_4 158 +#define SC_R_MATCH_5 159 +#define SC_R_MATCH_6 160 +#define SC_R_MATCH_7 161 +#define SC_R_MATCH_8 162 +#define SC_R_MATCH_9 163 +#define SC_R_MATCH_10 164 +#define SC_R_MATCH_11 165 +#define SC_R_MATCH_12 166 +#define SC_R_MATCH_13 167 +#define SC_R_MATCH_14 168 +#define SC_R_PCIE_B 169 +#define SC_R_SATA_0 170 +#define SC_R_SERDES_1 171 +#define SC_R_HSIO_GPIO 172 +#define SC_R_MATCH_15 173 +#define SC_R_MATCH_16 174 +#define SC_R_MATCH_17 175 +#define SC_R_MATCH_18 176 +#define SC_R_MATCH_19 177 +#define SC_R_MATCH_20 178 +#define SC_R_MATCH_21 179 +#define SC_R_MATCH_22 180 +#define SC_R_MATCH_23 181 +#define SC_R_MATCH_24 182 +#define SC_R_MATCH_25 183 +#define SC_R_MATCH_26 184 +#define SC_R_MATCH_27 185 +#define SC_R_MATCH_28 186 +#define SC_R_LCD_0 187 +#define SC_R_LCD_0_PWM_0 188 +#define SC_R_LCD_0_I2C_0 189 +#define SC_R_LCD_0_I2C_1 190 +#define SC_R_PWM_0 191 +#define SC_R_PWM_1 192 +#define SC_R_PWM_2 193 +#define SC_R_PWM_3 194 +#define SC_R_PWM_4 195 +#define SC_R_PWM_5 196 +#define SC_R_PWM_6 197 +#define SC_R_PWM_7 198 +#define SC_R_GPIO_0 199 +#define SC_R_GPIO_1 200 +#define SC_R_GPIO_2 201 +#define SC_R_GPIO_3 202 +#define SC_R_GPIO_4 203 +#define SC_R_GPIO_5 204 +#define SC_R_GPIO_6 205 +#define SC_R_GPIO_7 206 +#define SC_R_GPT_0 207 +#define SC_R_GPT_1 208 +#define SC_R_GPT_2 209 +#define SC_R_GPT_3 210 +#define SC_R_GPT_4 211 +#define SC_R_KPP 212 +#define SC_R_MU_0A 213 +#define SC_R_MU_1A 214 +#define SC_R_MU_2A 215 +#define SC_R_MU_3A 216 +#define SC_R_MU_4A 217 +#define SC_R_MU_5A 218 +#define SC_R_MU_6A 219 +#define SC_R_MU_7A 220 +#define SC_R_MU_8A 221 +#define SC_R_MU_9A 222 +#define SC_R_MU_10A 223 +#define SC_R_MU_11A 224 +#define SC_R_MU_12A 225 +#define SC_R_MU_13A 226 +#define SC_R_MU_5B 227 +#define SC_R_MU_6B 228 +#define SC_R_MU_7B 229 +#define SC_R_MU_8B 230 +#define SC_R_MU_9B 231 +#define SC_R_MU_10B 232 +#define SC_R_MU_11B 233 +#define SC_R_MU_12B 234 +#define SC_R_MU_13B 235 +#define SC_R_ROM_0 236 +#define SC_R_FSPI_0 237 +#define SC_R_FSPI_1 238 +#define SC_R_IEE 239 +#define SC_R_IEE_R0 240 +#define SC_R_IEE_R1 241 +#define SC_R_IEE_R2 242 +#define SC_R_IEE_R3 243 +#define SC_R_IEE_R4 244 +#define SC_R_IEE_R5 245 +#define SC_R_IEE_R6 246 +#define SC_R_IEE_R7 247 +#define SC_R_SDHC_0 248 +#define SC_R_SDHC_1 249 +#define SC_R_SDHC_2 250 +#define SC_R_ENET_0 251 +#define SC_R_ENET_1 252 +#define SC_R_MLB_0 253 +#define SC_R_DMA_2_CH0 254 +#define SC_R_DMA_2_CH1 255 +#define SC_R_DMA_2_CH2 256 +#define SC_R_DMA_2_CH3 257 +#define SC_R_DMA_2_CH4 258 +#define SC_R_USB_0 259 +#define SC_R_USB_1 260 +#define SC_R_USB_0_PHY 261 +#define SC_R_USB_2 262 +#define SC_R_USB_2_PHY 263 +#define SC_R_DTCP 264 +#define SC_R_NAND 265 +#define SC_R_LVDS_0 266 +#define SC_R_LVDS_0_PWM_0 267 +#define SC_R_LVDS_0_I2C_0 268 +#define SC_R_LVDS_0_I2C_1 269 +#define SC_R_LVDS_1 270 +#define SC_R_LVDS_1_PWM_0 271 +#define SC_R_LVDS_1_I2C_0 272 +#define SC_R_LVDS_1_I2C_1 273 +#define SC_R_LVDS_2 274 +#define SC_R_LVDS_2_PWM_0 275 +#define SC_R_LVDS_2_I2C_0 276 +#define SC_R_LVDS_2_I2C_1 277 +#define SC_R_M4_0_PID0 278 +#define SC_R_M4_0_PID1 279 +#define SC_R_M4_0_PID2 280 +#define SC_R_M4_0_PID3 281 +#define SC_R_M4_0_PID4 282 +#define SC_R_M4_0_RGPIO 283 +#define SC_R_M4_0_SEMA42 284 +#define SC_R_M4_0_TPM 285 +#define SC_R_M4_0_PIT 286 +#define SC_R_M4_0_UART 287 +#define SC_R_M4_0_I2C 288 +#define SC_R_M4_0_INTMUX 289 +#define SC_R_ENET_0_A0 290 +#define SC_R_ENET_0_A1 291 +#define SC_R_M4_0_MU_0B 292 +#define SC_R_M4_0_MU_0A0 293 +#define SC_R_M4_0_MU_0A1 294 +#define SC_R_M4_0_MU_0A2 295 +#define SC_R_M4_0_MU_0A3 296 +#define SC_R_M4_0_MU_1A 297 +#define SC_R_M4_1_PID0 298 +#define SC_R_M4_1_PID1 299 +#define SC_R_M4_1_PID2 300 +#define SC_R_M4_1_PID3 301 +#define SC_R_M4_1_PID4 302 +#define SC_R_M4_1_RGPIO 303 +#define SC_R_M4_1_SEMA42 304 +#define SC_R_M4_1_TPM 305 +#define SC_R_M4_1_PIT 306 +#define SC_R_M4_1_UART 307 +#define SC_R_M4_1_I2C 308 +#define SC_R_M4_1_INTMUX 309 +#define SC_R_UNUSED17 310 +#define SC_R_UNUSED18 311 +#define SC_R_M4_1_MU_0B 312 +#define SC_R_M4_1_MU_0A0 313 +#define SC_R_M4_1_MU_0A1 314 +#define SC_R_M4_1_MU_0A2 315 +#define SC_R_M4_1_MU_0A3 316 +#define SC_R_M4_1_MU_1A 317 +#define SC_R_SAI_0 318 +#define SC_R_SAI_1 319 +#define SC_R_SAI_2 320 +#define SC_R_IRQSTR_SCU2 321 +#define SC_R_IRQSTR_DSP 322 +#define SC_R_ELCDIF_PLL 323 +#define SC_R_OCRAM 324 +#define SC_R_AUDIO_PLL_0 325 +#define SC_R_PI_0 326 +#define SC_R_PI_0_PWM_0 327 +#define SC_R_PI_0_PWM_1 328 +#define SC_R_PI_0_I2C_0 329 +#define SC_R_PI_0_PLL 330 +#define SC_R_PI_1 331 +#define SC_R_PI_1_PWM_0 332 +#define SC_R_PI_1_PWM_1 333 +#define SC_R_PI_1_I2C_0 334 +#define SC_R_PI_1_PLL 335 +#define SC_R_SC_PID0 336 +#define SC_R_SC_PID1 337 +#define SC_R_SC_PID2 338 +#define SC_R_SC_PID3 339 +#define SC_R_SC_PID4 340 +#define SC_R_SC_SEMA42 341 +#define SC_R_SC_TPM 342 +#define SC_R_SC_PIT 343 +#define SC_R_SC_UART 344 +#define SC_R_SC_I2C 345 +#define SC_R_SC_MU_0B 346 +#define SC_R_SC_MU_0A0 347 +#define SC_R_SC_MU_0A1 348 +#define SC_R_SC_MU_0A2 349 +#define SC_R_SC_MU_0A3 350 +#define SC_R_SC_MU_1A 351 +#define SC_R_SYSCNT_RD 352 +#define SC_R_SYSCNT_CMP 353 +#define SC_R_DEBUG 354 +#define SC_R_SYSTEM 355 +#define SC_R_SNVS 356 +#define SC_R_OTP 357 +#define SC_R_VPU_PID0 358 +#define SC_R_VPU_PID1 359 +#define SC_R_VPU_PID2 360 +#define SC_R_VPU_PID3 361 +#define SC_R_VPU_PID4 362 +#define SC_R_VPU_PID5 363 +#define SC_R_VPU_PID6 364 +#define SC_R_VPU_PID7 365 +#define SC_R_ENET_0_A2 366 +#define SC_R_ENET_1_A0 367 +#define SC_R_ENET_1_A1 368 +#define SC_R_ENET_1_A2 369 +#define SC_R_ENET_1_A3 370 +#define SC_R_ENET_1_A4 371 +#define SC_R_DMA_4_CH0 372 +#define SC_R_DMA_4_CH1 373 +#define SC_R_DMA_4_CH2 374 +#define SC_R_DMA_4_CH3 375 +#define SC_R_DMA_4_CH4 376 +#define SC_R_ISI_CH0 377 +#define SC_R_ISI_CH1 378 +#define SC_R_ISI_CH2 379 +#define SC_R_ISI_CH3 380 +#define SC_R_ISI_CH4 381 +#define SC_R_ISI_CH5 382 +#define SC_R_ISI_CH6 383 +#define SC_R_ISI_CH7 384 +#define SC_R_MJPEG_DEC_S0 385 +#define SC_R_MJPEG_DEC_S1 386 +#define SC_R_MJPEG_DEC_S2 387 +#define SC_R_MJPEG_DEC_S3 388 +#define SC_R_MJPEG_ENC_S0 389 +#define SC_R_MJPEG_ENC_S1 390 +#define SC_R_MJPEG_ENC_S2 391 +#define SC_R_MJPEG_ENC_S3 392 +#define SC_R_MIPI_0 393 +#define SC_R_MIPI_0_PWM_0 394 +#define SC_R_MIPI_0_I2C_0 395 +#define SC_R_MIPI_0_I2C_1 396 +#define SC_R_MIPI_1 397 +#define SC_R_MIPI_1_PWM_0 398 +#define SC_R_MIPI_1_I2C_0 399 +#define SC_R_MIPI_1_I2C_1 400 +#define SC_R_CSI_0 401 +#define SC_R_CSI_0_PWM_0 402 +#define SC_R_CSI_0_I2C_0 403 +#define SC_R_CSI_1 404 +#define SC_R_CSI_1_PWM_0 405 +#define SC_R_CSI_1_I2C_0 406 +#define SC_R_HDMI 407 +#define SC_R_HDMI_I2S 408 +#define SC_R_HDMI_I2C_0 409 +#define SC_R_HDMI_PLL_0 410 +#define SC_R_HDMI_RX 411 +#define SC_R_HDMI_RX_BYPASS 412 +#define SC_R_HDMI_RX_I2C_0 413 +#define SC_R_ASRC_0 414 +#define SC_R_ESAI_0 415 +#define SC_R_SPDIF_0 416 +#define SC_R_SPDIF_1 417 +#define SC_R_SAI_3 418 +#define SC_R_SAI_4 419 +#define SC_R_SAI_5 420 +#define SC_R_GPT_5 421 +#define SC_R_GPT_6 422 +#define SC_R_GPT_7 423 +#define SC_R_GPT_8 424 +#define SC_R_GPT_9 425 +#define SC_R_GPT_10 426 +#define SC_R_DMA_2_CH5 427 +#define SC_R_DMA_2_CH6 428 +#define SC_R_DMA_2_CH7 429 +#define SC_R_DMA_2_CH8 430 +#define SC_R_DMA_2_CH9 431 +#define SC_R_DMA_2_CH10 432 +#define SC_R_DMA_2_CH11 433 +#define SC_R_DMA_2_CH12 434 +#define SC_R_DMA_2_CH13 435 +#define SC_R_DMA_2_CH14 436 +#define SC_R_DMA_2_CH15 437 +#define SC_R_DMA_2_CH16 438 +#define SC_R_DMA_2_CH17 439 +#define SC_R_DMA_2_CH18 440 +#define SC_R_DMA_2_CH19 441 +#define SC_R_DMA_2_CH20 442 +#define SC_R_DMA_2_CH21 443 +#define SC_R_DMA_2_CH22 444 +#define SC_R_DMA_2_CH23 445 +#define SC_R_DMA_2_CH24 446 +#define SC_R_DMA_2_CH25 447 +#define SC_R_DMA_2_CH26 448 +#define SC_R_DMA_2_CH27 449 +#define SC_R_DMA_2_CH28 450 +#define SC_R_DMA_2_CH29 451 +#define SC_R_DMA_2_CH30 452 +#define SC_R_DMA_2_CH31 453 +#define SC_R_ASRC_1 454 +#define SC_R_ESAI_1 455 +#define SC_R_SAI_6 456 +#define SC_R_SAI_7 457 +#define SC_R_AMIX 458 +#define SC_R_MQS_0 459 +#define SC_R_DMA_3_CH0 460 +#define SC_R_DMA_3_CH1 461 +#define SC_R_DMA_3_CH2 462 +#define SC_R_DMA_3_CH3 463 +#define SC_R_DMA_3_CH4 464 +#define SC_R_DMA_3_CH5 465 +#define SC_R_DMA_3_CH6 466 +#define SC_R_DMA_3_CH7 467 +#define SC_R_DMA_3_CH8 468 +#define SC_R_DMA_3_CH9 469 +#define SC_R_DMA_3_CH10 470 +#define SC_R_DMA_3_CH11 471 +#define SC_R_DMA_3_CH12 472 +#define SC_R_DMA_3_CH13 473 +#define SC_R_DMA_3_CH14 474 +#define SC_R_DMA_3_CH15 475 +#define SC_R_DMA_3_CH16 476 +#define SC_R_DMA_3_CH17 477 +#define SC_R_DMA_3_CH18 478 +#define SC_R_DMA_3_CH19 479 +#define SC_R_DMA_3_CH20 480 +#define SC_R_DMA_3_CH21 481 +#define SC_R_DMA_3_CH22 482 +#define SC_R_DMA_3_CH23 483 +#define SC_R_DMA_3_CH24 484 +#define SC_R_DMA_3_CH25 485 +#define SC_R_DMA_3_CH26 486 +#define SC_R_DMA_3_CH27 487 +#define SC_R_DMA_3_CH28 488 +#define SC_R_DMA_3_CH29 489 +#define SC_R_DMA_3_CH30 490 +#define SC_R_DMA_3_CH31 491 +#define SC_R_AUDIO_PLL_1 492 +#define SC_R_AUDIO_CLK_0 493 +#define SC_R_AUDIO_CLK_1 494 +#define SC_R_MCLK_OUT_0 495 +#define SC_R_MCLK_OUT_1 496 +#define SC_R_PMIC_0 497 +#define SC_R_PMIC_1 498 +#define SC_R_SECO 499 +#define SC_R_CAAM_JR1 500 +#define SC_R_CAAM_JR2 501 +#define SC_R_CAAM_JR3 502 +#define SC_R_SECO_MU_2 503 +#define SC_R_SECO_MU_3 504 +#define SC_R_SECO_MU_4 505 +#define SC_R_HDMI_RX_PWM_0 506 +#define SC_R_A35 507 +#define SC_R_A35_0 508 +#define SC_R_A35_1 509 +#define SC_R_A35_2 510 +#define SC_R_A35_3 511 +#define SC_R_DSP 512 +#define SC_R_DSP_RAM 513 +#define SC_R_CAAM_JR1_OUT 514 +#define SC_R_CAAM_JR2_OUT 515 +#define SC_R_CAAM_JR3_OUT 516 +#define SC_R_VPU_DEC_0 517 +#define SC_R_VPU_ENC_0 518 +#define SC_R_CAAM_JR0 519 +#define SC_R_CAAM_JR0_OUT 520 +#define SC_R_PMIC_2 521 +#define SC_R_DBLOGIC 522 +#define SC_R_HDMI_PLL_1 523 +#define SC_R_BOARD_R0 524 +#define SC_R_BOARD_R1 525 +#define SC_R_BOARD_R2 526 +#define SC_R_BOARD_R3 527 +#define SC_R_BOARD_R4 528 +#define SC_R_BOARD_R5 529 +#define SC_R_BOARD_R6 530 +#define SC_R_BOARD_R7 531 +#define SC_R_MJPEG_DEC_MP 532 +#define SC_R_MJPEG_ENC_MP 533 +#define SC_R_VPU_TS_0 534 +#define SC_R_VPU_MU_0 535 +#define SC_R_VPU_MU_1 536 +#define SC_R_VPU_MU_2 537 +#define SC_R_VPU_MU_3 538 +#define SC_R_VPU_ENC_1 539 +#define SC_R_VPU 540 +#define SC_R_DMA_5_CH0 541 +#define SC_R_DMA_5_CH1 542 +#define SC_R_DMA_5_CH2 543 +#define SC_R_DMA_5_CH3 544 +#define SC_R_ATTESTATION 545 +#define SC_R_LAST 546 +#define SC_R_NONE 0xFFF0 + +#endif /* DT_BINDINGS_RSCRC_IMX_H */ diff --git a/include/linux/backlight.h b/include/linux/backlight.h index af7003548593..ace825e2ca2d 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -130,6 +130,38 @@ static inline int backlight_update_status(struct backlight_device *bd) return ret; } +/** + * backlight_enable - Enable backlight + * @bd: the backlight device to enable + */ +static inline int backlight_enable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + bd->props.state &= ~BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + +/** + * backlight_disable - Disable backlight + * @bd: the backlight device to disable + */ +static inline int backlight_disable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_POWERDOWN; + bd->props.fb_blank = FB_BLANK_POWERDOWN; + bd->props.state |= BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + extern struct backlight_device *backlight_device_register(const char *name, struct device *dev, void *devdata, const struct backlight_ops *ops, const struct backlight_properties *props); diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h index 91072b68dc38..86173bafcd39 100644 --- a/include/linux/blk_types.h +++ b/include/linux/blk_types.h @@ -229,11 +229,14 @@ enum req_flag_bits { __REQ_PREFLUSH, /* request for cache flush */ __REQ_RAHEAD, /* read ahead, can fail anytime */ __REQ_BACKGROUND, /* background IO */ + __REQ_NOWAIT, /* Don't wait if request will block */ /* command specific flags for REQ_OP_WRITE_ZEROES: */ __REQ_NOUNMAP, /* do not free blocks when zeroing */ - __REQ_NOWAIT, /* Don't wait if request will block */ + /* for driver use */ + __REQ_DRV, + __REQ_NR_BITS, /* stops here */ }; @@ -250,9 +253,11 @@ enum req_flag_bits { #define REQ_PREFLUSH (1ULL << __REQ_PREFLUSH) #define REQ_RAHEAD (1ULL << __REQ_RAHEAD) #define REQ_BACKGROUND (1ULL << __REQ_BACKGROUND) +#define REQ_NOWAIT (1ULL << __REQ_NOWAIT) #define REQ_NOUNMAP (1ULL << __REQ_NOUNMAP) -#define REQ_NOWAIT (1ULL << __REQ_NOWAIT) + +#define REQ_DRV (1ULL << __REQ_DRV) #define REQ_FAILFAST_MASK \ (REQ_FAILFAST_DEV | REQ_FAILFAST_TRANSPORT | REQ_FAILFAST_DRIVER) diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index ad940102451c..12c9cf2c390d 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -284,6 +284,7 @@ struct blk_queue_ctx; typedef void (request_fn_proc) (struct request_queue *q); typedef blk_qc_t (make_request_fn) (struct request_queue *q, struct bio *bio); +typedef bool (poll_q_fn) (struct request_queue *q, blk_qc_t); typedef int (prep_rq_fn) (struct request_queue *, struct request *); typedef void (unprep_rq_fn) (struct request_queue *, struct request *); @@ -426,6 +427,7 @@ struct request_queue { request_fn_proc *request_fn; make_request_fn *make_request_fn; + poll_q_fn *poll_fn; prep_rq_fn *prep_rq_fn; unprep_rq_fn *unprep_rq_fn; softirq_done_fn *softirq_done_fn; @@ -954,6 +956,7 @@ do { \ extern int blk_register_queue(struct gendisk *disk); extern void blk_unregister_queue(struct gendisk *disk); extern blk_qc_t generic_make_request(struct bio *bio); +extern blk_qc_t direct_make_request(struct bio *bio); extern void blk_rq_init(struct request_queue *q, struct request *rq); extern void blk_init_request_from_bio(struct request *req, struct bio *bio); extern void blk_put_request(struct request *); @@ -1008,7 +1011,7 @@ extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *, int blk_status_to_errno(blk_status_t status); blk_status_t errno_to_blk_status(int errno); -bool blk_mq_poll(struct request_queue *q, blk_qc_t cookie); +bool blk_poll(struct request_queue *q, blk_qc_t cookie); static inline struct request_queue *bdev_get_queue(struct block_device *bdev) { @@ -1127,6 +1130,8 @@ extern struct request *blk_peek_request(struct request_queue *q); extern void blk_start_request(struct request *rq); extern struct request *blk_fetch_request(struct request_queue *q); +void blk_steal_bios(struct bio_list *list, struct request *rq); + /* * Request completion related functions. * diff --git a/include/linux/busfreq-imx.h b/include/linux/busfreq-imx.h new file mode 100644 index 000000000000..17b8991d69bd --- /dev/null +++ b/include/linux/busfreq-imx.h @@ -0,0 +1,77 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BUSFREQ_H__ +#define __ASM_ARCH_MXC_BUSFREQ_H__ + +#include <linux/notifier.h> +#include <linux/regulator/consumer.h> + +/* + * This enumerates busfreq low power mode entry and exit. + */ +enum busfreq_event { + LOW_BUSFREQ_ENTER, + LOW_BUSFREQ_EXIT, +}; + +/* + * This enumerates the system bus and ddr frequencies in various modes. + * BUS_FREQ_HIGH - DDR @ 528MHz, AHB @ 132MHz. + * BUS_FREQ_MED - DDR @ 400MHz, AHB @ 132MHz + * BUS_FREQ_AUDIO - DDR @ 50MHz/100MHz, AHB @ 24MHz. + * BUS_FREQ_LOW - DDR @ 24MHz, AHB @ 24MHz. + * BUS_FREQ_ULTRA_LOW - DDR @ 1MHz, AHB - 3MHz. + * + * Drivers need to request/release the bus/ddr frequencies based on + * their performance requirements. Drivers cannot request/release + * BUS_FREQ_ULTRA_LOW mode as this mode is automatically entered from + * either BUS_FREQ_AUDIO or BUS_FREQ_LOW + * modes. + */ +enum bus_freq_mode { + BUS_FREQ_HIGH, + BUS_FREQ_MED, + BUS_FREQ_AUDIO, + BUS_FREQ_LOW, + BUS_FREQ_ULTRA_LOW, +}; + +#if defined(CONFIG_CPU_FREQ) && !defined(CONFIG_ARM64) +extern struct regulator *arm_reg; +extern struct regulator *soc_reg; +void request_bus_freq(enum bus_freq_mode mode); +void release_bus_freq(enum bus_freq_mode mode); +int register_busfreq_notifier(struct notifier_block *nb); +int unregister_busfreq_notifier(struct notifier_block *nb); +int get_bus_freq_mode(void); +#elif defined(CONFIG_ARCH_FSL_IMX8MQ) +void request_bus_freq(enum bus_freq_mode mode); +void release_bus_freq(enum bus_freq_mode mode); +int get_bus_freq_mode(void); +#else +static inline void request_bus_freq(enum bus_freq_mode mode) +{ +} +static inline void release_bus_freq(enum bus_freq_mode mode) +{ +} +static inline int register_busfreq_notifier(struct notifier_block *nb) +{ + return 0; +} +static inline int unregister_busfreq_notifier(struct notifier_block *nb) +{ + return 0; +} +static inline int get_bus_freq_mode(void) +{ + return BUS_FREQ_HIGH; +} +#endif +#endif diff --git a/include/linux/can/platform/flexcan.h b/include/linux/can/platform/flexcan.h new file mode 100644 index 000000000000..fdfe76f16ea7 --- /dev/null +++ b/include/linux/can/platform/flexcan.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This file is released under the GPLv2 + * + */ + +#ifndef __CAN_PLATFORM_FLEXCAN_H +#define __CAN_PLATFORM_FLEXCAN_H + +/** + * struct flexcan_platform_data - flex CAN controller platform data + * @transceiver_enable: - called to power on/off the transceiver + * + */ +struct flexcan_platform_data { + void (*transceiver_switch)(int enable); +}; + +#endif /* __CAN_PLATFORM_FLEXCAN_H */ diff --git a/include/linux/can/rx-offload.h b/include/linux/can/rx-offload.h index 8268811a697e..c54d80ef4314 100644 --- a/include/linux/can/rx-offload.h +++ b/include/linux/can/rx-offload.h @@ -23,8 +23,9 @@ struct can_rx_offload { struct net_device *dev; - unsigned int (*mailbox_read)(struct can_rx_offload *offload, struct can_frame *cf, - u32 *timestamp, unsigned int mb); + unsigned int (*mailbox_read)(struct can_rx_offload *offload, bool drop, + struct sk_buff **skb, u32 *timestamp, + unsigned int mb); struct sk_buff_head skb_queue; u32 skb_queue_len_max; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 3eb3376f1cc8..9ae6613db10c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -35,6 +35,7 @@ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) +#define CLK_SET_PARENT_NOCACHE BIT(13) /* do not use the cached clk parent */ struct clk; struct clk_hw; @@ -358,6 +359,7 @@ struct clk_div_table { * @shift: shift to the divider bit field * @width: width of the divider bit field * @table: array of value/divider pairs, last entry should have div = 0 + * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements @@ -386,6 +388,12 @@ struct clk_div_table { * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. + * CLK_DIVIDER_ZERO_GATE - For dividers when the value read from the register + * is zero, it means the divisor is gated. For this case, the cached_val + * will be used to store the intermediate div for the normal rate + * operation, like set_rate/get_rate/recalc_rate. When the divider is + * ungated, the driver will actually program the hardware to have the + * requested divider value. */ struct clk_divider { struct clk_hw hw; @@ -394,6 +402,7 @@ struct clk_divider { u8 width; u8 flags; const struct clk_div_table *table; + u32 cached_val; spinlock_t *lock; }; @@ -406,6 +415,7 @@ struct clk_divider { #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_ZERO_GATE BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; @@ -555,6 +565,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. */ struct clk_fractional_divider { struct clk_hw hw; @@ -574,6 +590,8 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index cad1eb50d668..b9c6fff3cc9f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -548,6 +548,18 @@ struct gov_attr_set { int usage_count; }; +#define gov_attr_ro(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0444, show_##_name, NULL) + +#define gov_attr_wo(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0200, NULL, store_##_name) + +#define gov_attr_rw(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0644, show_##_name, store_##_name) + /* sysfs ops for cpufreq governors */ extern const struct sysfs_ops governor_sysfs_ops; diff --git a/include/linux/crypto.h b/include/linux/crypto.h index de96913306cb..5e14fac088d5 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -24,6 +24,7 @@ #include <linux/slab.h> #include <linux/string.h> #include <linux/uaccess.h> +#include <linux/completion.h> /* * Autoloaded crypto modules should only use a prefixed name to avoid allowing @@ -481,6 +482,45 @@ struct crypto_alg { } CRYPTO_MINALIGN_ATTR; /* + * A helper struct for waiting for completion of async crypto ops + */ +struct crypto_wait { + struct completion completion; + int err; +}; + +/* + * Macro for declaring a crypto op async wait object on stack + */ +#define DECLARE_CRYPTO_WAIT(_wait) \ + struct crypto_wait _wait = { \ + COMPLETION_INITIALIZER_ONSTACK((_wait).completion), 0 } + +/* + * Async ops completion helper functioons + */ +void crypto_req_done(struct crypto_async_request *req, int err); + +static inline int crypto_wait_req(int err, struct crypto_wait *wait) +{ + switch (err) { + case -EINPROGRESS: + case -EBUSY: + wait_for_completion(&wait->completion); + reinit_completion(&wait->completion); + err = wait->err; + break; + }; + + return err; +} + +static inline void crypto_init_wait(struct crypto_wait *wait) +{ + init_completion(&wait->completion); +} + +/* * Algorithm registration interface. */ int crypto_register_alg(struct crypto_alg *alg); diff --git a/include/linux/device_cooling.h b/include/linux/device_cooling.h new file mode 100644 index 000000000000..18d9e3b90ed9 --- /dev/null +++ b/include/linux/device_cooling.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DEVICE_THERMAL_H__ +#define __DEVICE_THERMAL_H__ + +#include <linux/thermal.h> + +#ifdef CONFIG_DEVICE_THERMAL +int register_devfreq_cooling_notifier(struct notifier_block *nb); +int unregister_devfreq_cooling_notifier(struct notifier_block *nb); +struct thermal_cooling_device *devfreq_cooling_register(void); +void devfreq_cooling_unregister(struct thermal_cooling_device *cdev); +#else +static inline +int register_devfreq_cooling_notifier(struct notifier_block *nb) +{ + return 0; +} + +static inline +int unregister_devfreq_cooling_notifier(struct notifier_block *nb) +{ + return 0; +} + +static inline +struct thermal_cooling_device *devfreq_cooling_register(void) +{ + return NULL; +} + +static inline +void devfreq_cooling_unregister(struct thermal_cooling_device *cdev) +{ + return; +} +#endif +#endif /* __DEVICE_THERMAL_H__ */ diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 087cbe776868..edcbdb22bed0 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -345,6 +345,8 @@ enum dma_slave_buswidth { * loops in this area in order to transfer the data. * @dst_port_window_size: same as src_port_window_size but for the destination * port. + * @src_fifo_num: bit 0-7 is the fifo number, bit:8-11 is the fifo offset; + * @dst_fifo_num: same as src_fifo_num * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill * with 'true' if peripheral should be flow controller. Direction will be * selected at Runtime. @@ -374,6 +376,8 @@ struct dma_slave_config { u32 dst_maxburst; u32 src_port_window_size; u32 dst_port_window_size; + u32 src_fifo_num; + u32 dst_fifo_num; bool device_fc; unsigned int slave_id; }; diff --git a/include/linux/genhd.h b/include/linux/genhd.h index 550fa358893a..4ed6f5256710 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -141,6 +141,7 @@ struct hd_struct { #define GENHD_FL_NATIVE_CAPACITY 128 #define GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE 256 #define GENHD_FL_NO_PART_SCAN 512 +#define GENHD_FL_HIDDEN 1024 enum { DISK_EVENT_MEDIA_CHANGE = 1 << 0, /* media changed */ @@ -235,7 +236,7 @@ static inline bool disk_part_scan_enabled(struct gendisk *disk) static inline dev_t disk_devt(struct gendisk *disk) { - return disk_to_dev(disk)->devt; + return MKDEV(disk->major, disk->first_minor); } static inline dev_t part_devt(struct hd_struct *part) @@ -395,6 +396,11 @@ static inline void add_disk(struct gendisk *disk) { device_add_disk(NULL, disk); } +extern void device_add_disk_no_queue_reg(struct device *parent, struct gendisk *disk); +static inline void add_disk_no_queue_reg(struct gendisk *disk) +{ + device_add_disk_no_queue_reg(NULL, disk); +} extern void del_gendisk(struct gendisk *gp); extern struct gendisk *get_gendisk(dev_t dev, int *partno); diff --git a/include/linux/hantrodec.h b/include/linux/hantrodec.h new file mode 100755 index 000000000000..f423ea82a04e --- /dev/null +++ b/include/linux/hantrodec.h @@ -0,0 +1,29 @@ +/***************************************************************************** +* +* The GPL License (GPL) +* +* Copyright (c) 2015-2017, VeriSilicon Inc. +* Copyright (c) 2011-2014, Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software Foundation, +* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +* +*****************************************************************************/ + +#ifndef _HANTRODEC_H_ +#define _HANTRODEC_H_ + +#include <uapi/linux/hantrodec.h> + +#endif /* !_HANTRODEC_H_ */ diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index d271ff23984f..e367de96076b 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -32,6 +32,7 @@ enum hdmi_infoframe_type { HDMI_INFOFRAME_TYPE_AVI = 0x82, HDMI_INFOFRAME_TYPE_SPD = 0x83, HDMI_INFOFRAME_TYPE_AUDIO = 0x84, + HDMI_INFOFRAME_TYPE_DRM = 0x87, }; #define HDMI_IEEE_OUI 0x000c03 @@ -160,10 +161,28 @@ struct hdmi_avi_infoframe { unsigned short right_bar; }; +struct hdmi_drm_infoframe { + enum hdmi_infoframe_type type; + unsigned char version; + unsigned char length; + uint8_t eotf; + uint8_t metadata_type; + uint16_t display_primaries_x[3]; + uint16_t display_primaries_y[3]; + uint16_t white_point_x; + uint16_t white_point_y; + uint16_t max_mastering_display_luminance; + uint16_t min_mastering_display_luminance; + uint16_t max_fall; + uint16_t max_cll; +}; + int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame); ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, size_t size); +int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame); + enum hdmi_spd_sdi { HDMI_SPD_SDI_UNKNOWN, HDMI_SPD_SDI_DSTB, @@ -328,6 +347,7 @@ union hdmi_infoframe { struct hdmi_spd_infoframe spd; union hdmi_vendor_any_infoframe vendor; struct hdmi_audio_infoframe audio; + struct hdmi_drm_infoframe drm; }; ssize_t diff --git a/include/linux/hx280enc.h b/include/linux/hx280enc.h new file mode 100755 index 000000000000..186a00e3446f --- /dev/null +++ b/include/linux/hx280enc.h @@ -0,0 +1,31 @@ +/***************************************************************************** + * Encoder device driver (kernel module header) + * + * Copyright (C) 2012 Google Finland Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * +-------------------------------------------------------------------------------- +-- +-- Abstract : 6280/7280/8270/8290/H1 Encoder device driver (kernel module) +-- +*****************************************************************************/ + +#ifndef _HX280ENC_H_ +#define _HX280ENC_H_ + +#include <uapi/linux/hx280enc.h> + +#endif /* !_HX280ENC_H_ */ diff --git a/include/linux/imx_gpc.h b/include/linux/imx_gpc.h new file mode 100644 index 000000000000..0eb38224c438 --- /dev/null +++ b/include/linux/imx_gpc.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/imx_gpc.h + * + * @brief Global header file for imx GPC + * + * @ingroup GPC + */ +#ifndef __LINUX_IMX_GPC_H__ +#define __LINUX_IMX_GPC_H__ + +#ifdef CONFIG_HAVE_IMX_GPC +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on); +#else +static inline int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) { return 0; } +#endif + +#endif /* __LINUX_IMX_GPC_H__ */ diff --git a/include/linux/imx_rpmsg.h b/include/linux/imx_rpmsg.h new file mode 100644 index 000000000000..cabb6d6e03ce --- /dev/null +++ b/include/linux/imx_rpmsg.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/imx_rpmsg.h + * + * @brief Global header file for imx RPMSG + * + * @ingroup RPMSG + */ +#ifndef __LINUX_IMX_RPMSG_H__ +#define __LINUX_IMX_RPMSG_H__ + +/* Category define */ +#define IMX_RMPSG_LIFECYCLE 1 +#define IMX_RPMSG_PMIC 2 +#define IMX_RPMSG_AUDIO 3 +#define IMX_RPMSG_KEY 4 +#define IMX_RPMSG_GPIO 5 +#define IMX_RPMSG_RTC 6 +#define IMX_RPMSG_SENSOR 7 +/* rpmsg version */ +#define IMX_RMPSG_MAJOR 1 +#define IMX_RMPSG_MINOR 0 + +struct imx_rpmsg_head { + u8 cate; + u8 major; + u8 minor; + u8 type; + u8 cmd; + u8 reserved[5]; +} __attribute__ ((packed)); + +#endif /* __LINUX_IMX_RPMSG_H__ */ diff --git a/include/linux/imx_sema4.h b/include/linux/imx_sema4.h new file mode 100644 index 000000000000..19850ae7742b --- /dev/null +++ b/include/linux/imx_sema4.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_IMX_SEMA4_H__ +#define __LINUX_IMX_SEMA4_H__ + +#define SEMA4_NUM_DEVICES 1 +#define SEMA4_NUM_GATES 16 + +#define SEMA4_UNLOCK 0x00 +#define SEMA4_A9_LOCK 0x01 +#define SEMA4_GATE_MASK 0x03 + +#define CORE_MUTEX_VALID (('c'<<24)|('m'<<24)|('t'<<24)|'x') + +/* + * The enumerates + */ +enum { + /* sema4 registers offset */ + SEMA4_CP0INE = 0x40, + SEMA4_CP1INE = 0x48, + SEMA4_CP0NTF = 0x80, + SEMA4_CP1NTF = 0x88, +}; + +static const unsigned int idx_sema4[SEMA4_NUM_GATES] = { + 1 << 7, 1 << 6, 1 << 5, 1 << 4, + 1 << 3, 1 << 2, 1 << 1, 1 << 0, + 1 << 15, 1 << 14, 1 << 13, 1 << 12, + 1 << 11, 1 << 10, 1 << 9, 1 << 8, +}; + +struct imx_sema4_mutex { + u32 valid; + u32 gate_num; + unsigned char gate_val; + wait_queue_head_t wait_q; +}; + +struct imx_sema4_mutex_device { + struct device *dev; + u16 cpntf_val; + u16 cpine_val; + void __iomem *ioaddr; /* Mapped address */ + spinlock_t lock; /* Mutex */ + int irq; + + u16 alloced; + struct imx_sema4_mutex *mutex_ptr[SEMA4_NUM_GATES]; +}; + +struct imx_sema4_mutex * + imx_sema4_mutex_create(u32 dev_num, u32 mutex_num); +#ifdef CONFIG_IMX_SEMA4 +int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr); +#else +static inline int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +#endif +#endif /* __LINUX_IMX_SEMA4_H__ */ diff --git a/include/linux/ipu-v3-pre.h b/include/linux/ipu-v3-pre.h new file mode 100644 index 000000000000..f5a26e5eadbf --- /dev/null +++ b/include/linux/ipu-v3-pre.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_IPU_V3_PRE_H_ +#define __LINUX_IPU_V3_PRE_H_ + +#define IPU_PRE_MAX_WIDTH 1920 +#define IPU_PRE_MAX_BPP 4 +#define IPU_PRE_SMALL_LINE 9 /* to workaround errata ERR009624*/ + +struct ipu_rect { + int left; + int top; + int width; + int height; +}; + +struct ipu_pre_context { + bool repeat; + bool vflip; + bool handshake_en; + bool hsk_abort_en; + unsigned int hsk_line_num; + bool sdw_update; + unsigned int block_size; + unsigned int interlaced; + unsigned int prefetch_mode; + + unsigned long cur_buf; + unsigned long next_buf; + + unsigned int tile_fmt; + + unsigned int read_burst; + unsigned int prefetch_input_bpp; + unsigned int prefetch_input_pixel_fmt; + unsigned int prefetch_shift_offset; + unsigned int prefetch_shift_width; + bool shift_bypass; + bool field_inverse; + bool tpr_coor_offset_en; + /* the output of prefetch is + * also the input of store + */ + struct ipu_rect prefetch_output_size; + unsigned int prefetch_input_active_width; + unsigned int prefetch_input_width; + unsigned int prefetch_input_height; + unsigned int store_pitch; + int interlace_offset; + + bool store_en; + unsigned int write_burst; + unsigned int store_output_bpp; + + unsigned int sec_buf_off; + unsigned int trd_buf_off; + + /* return for IPU fb caller */ + unsigned long store_addr; +}; + +/* + * In order to workaround the PRE SoC bug recorded by errata ERR009624, + * the software cannot write the PRE_CTRL register when the PRE writes + * the PRE_CTRL register automatically to set the ENABLE bit(bit0) to 1 + * in the PRE repeat mode. + * The software mechanism to set the PRE_CTRL register is different for + * PRE Y resolution higher than 9 lines and lower or equal to 9 lines. + * Use this helper to check the Y resolution. + */ +static inline bool ipu_pre_yres_is_small(unsigned int yres) +{ + return yres <= IPU_PRE_SMALL_LINE; +} + +#ifdef CONFIG_MXC_IPU_V3_PRE +int ipu_pre_alloc(int ipu_id, ipu_channel_t ipu_ch); +void ipu_pre_free(unsigned int *id); +unsigned long ipu_pre_alloc_double_buffer(unsigned int id, unsigned int size); +void ipu_pre_free_double_buffer(unsigned int id); +int ipu_pre_config(int id, struct ipu_pre_context *config); +int ipu_pre_set_ctrl(unsigned int id, struct ipu_pre_context *config); +int ipu_pre_enable(int id); +void ipu_pre_disable(int id); +int ipu_pre_set_fb_buffer(int id, bool resolve, + unsigned long fb_paddr, + unsigned int y_res, + unsigned int x_crop, + unsigned int y_crop, + unsigned int sec_buf_off, + unsigned int trd_buf_off); +int ipu_pre_sdw_update(int id); +#else +int ipu_pre_alloc(int ipu_id, ipu_channel_t channel) +{ + return -ENODEV; +} + +void ipu_pre_free(unsigned int *id) +{ +} + +unsigned long ipu_pre_alloc_double_buffer(unsigned int id, unsigned int size) +{ + return -ENODEV; +} + +void ipu_pre_free_double_buffer(unsigned int id) +{ +} + +int ipu_pre_config(int id, struct ipu_pre_context *config) +{ + return -ENODEV; +} + +int ipu_pre_set_ctrl(unsigned int id, struct ipu_pre_context *config) +{ + return -ENODEV; +} + +int ipu_pre_enable(int id) +{ + return -ENODEV; +} + +void ipu_pre_disable(int id) +{ + return; +} + +int ipu_pre_set_fb_buffer(int id, bool resolve, + unsigned long fb_paddr, + unsigned int y_res, + unsigned int x_crop, + unsigned int y_crop, + unsigned int sec_buf_off, + unsigned int trd_buf_off) +{ + return -ENODEV; +} +int ipu_pre_sdw_update(int id) +{ + return -ENODEV; +} +#endif +#endif /* __LINUX_IPU_V3_PRE_H_ */ diff --git a/include/linux/ipu-v3-prg.h b/include/linux/ipu-v3-prg.h new file mode 100644 index 000000000000..2ab803a6699f --- /dev/null +++ b/include/linux/ipu-v3-prg.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_IPU_V3_PRG_H_ +#define __LINUX_IPU_V3_PRG_H_ + +#include <linux/ipu-v3.h> + +#define PRG_SO_INTERLACE 1 +#define PRG_SO_PROGRESSIVE 0 +#define PRG_BLOCK_MODE 1 +#define PRG_SCAN_MODE 0 + +struct ipu_prg_config { + unsigned int id; + unsigned int pre_num; + ipu_channel_t ipu_ch; + unsigned int stride; + unsigned int height; + unsigned int ipu_height; + unsigned int crop_line; + unsigned int so; + unsigned int ilo; + unsigned int block_mode; + bool vflip; + u32 baddr; + u32 offset; +}; + +#ifdef CONFIG_MXC_IPU_V3_PRG +int ipu_prg_config(struct ipu_prg_config *config); +int ipu_prg_disable(unsigned int ipu_id, unsigned int pre_num); +int ipu_prg_wait_buf_ready(unsigned int ipu_id, unsigned int pre_num, + unsigned int hsk_line_num, + int pre_store_out_height); +#else +int ipu_prg_config(struct ipu_prg_config *config) +{ + return -ENODEV; +} + +int ipu_prg_disable(unsigned int ipu_id, unsigned int pre_num) +{ + return -ENODEV; +} + +int ipu_prg_wait_buf_ready(unsigned int ipu_id, unsigned int pre_num, + unsigned int hsk_line_num, + int pre_store_out_height) +{ + return -ENODEV; +} +#endif +#endif /* __LINUX_IPU_V3_PRG_H_ */ diff --git a/include/linux/ipu-v3.h b/include/linux/ipu-v3.h new file mode 100644 index 000000000000..ae09614a2257 --- /dev/null +++ b/include/linux/ipu-v3.h @@ -0,0 +1,770 @@ +/* + * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __LINUX_IPU_V3_H_ +#define __LINUX_IPU_V3_H_ + +#include <linux/ipu.h> + +/* IPU Driver channels definitions. */ +/* Note these are different from IDMA channels */ +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 +/*! + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, + MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48), + MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49), + MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50), + + MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20), + MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21), + MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22), + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0), + CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1), + CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2), + CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3), + + CSI_MEM = CSI_MEM0, + + CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20), + CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21), + + /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/ + MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21), + MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21), + MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21), + + /* for vdi mem->vdi->mem */ + MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5), + + /* fake channel for vdoa to link with IPU */ + MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + MEM_PP_ADC = CHAN_NONE, + ADC_SYS2 = CHAN_NONE, + +} ipu_channel_t; + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +/*! + * Enumeration of ADC channel operation mode. + */ +typedef enum { + Disable, + WriteTemplateNonSeq, + ReadTemplateNonSeq, + WriteTemplateUnCon, + ReadTemplateUnCon, + WriteDataWithRS, + WriteDataWoRS, + WriteCmd +} mcu_mode_t; + +/*! + * Enumeration of ADC channel addressing mode. + */ +typedef enum { + FullWoBE, + FullWithBE, + XY +} display_addressing_t; + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + bool interlaced; + } csi_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + } mem_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + } mem_rot_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } csi_prp_vf_adc; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + } mem_prp_vf_mem; + struct { + uint32_t temp; + } mem_prp_vf_adc; + struct { + uint32_t temp; + } mem_rot_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + } mem_pp_mem; + struct { + uint32_t temp; + } mem_rot_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } mem_pp_adc; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_fg_sync; + struct { + uint32_t di; + } direct_async; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys1; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys2; +} ipu_channel_params_t; + +/* + * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished. + */ +#define IPU_IRQF_NONE 0x00000000 +#define IPU_IRQF_ONESHOT 0x00000001 + +/*! + * Enumeration of IPU interrupt sources. + */ +enum ipu_irq_line { + IPU_IRQ_CSI0_OUT_EOF = 0, + IPU_IRQ_CSI1_OUT_EOF = 1, + IPU_IRQ_CSI2_OUT_EOF = 2, + IPU_IRQ_CSI3_OUT_EOF = 3, + IPU_IRQ_VDIC_OUT_EOF = 5, + IPU_IRQ_VDI_P_IN_EOF = 8, + IPU_IRQ_VDI_C_IN_EOF = 9, + IPU_IRQ_VDI_N_IN_EOF = 10, + IPU_IRQ_PP_IN_EOF = 11, + IPU_IRQ_PRP_IN_EOF = 12, + IPU_IRQ_PRP_GRAPH_IN_EOF = 14, + IPU_IRQ_PP_GRAPH_IN_EOF = 15, + IPU_IRQ_PRP_ALPHA_IN_EOF = 17, + IPU_IRQ_PP_ALPHA_IN_EOF = 18, + IPU_IRQ_PRP_ENC_OUT_EOF = 20, + IPU_IRQ_PRP_VF_OUT_EOF = 21, + IPU_IRQ_PP_OUT_EOF = 22, + IPU_IRQ_BG_SYNC_EOF = 23, + IPU_IRQ_BG_ASYNC_EOF = 24, + IPU_IRQ_FG_SYNC_EOF = 27, + IPU_IRQ_DC_SYNC_EOF = 28, + IPU_IRQ_FG_ASYNC_EOF = 29, + IPU_IRQ_FG_ALPHA_SYNC_EOF = 31, + + IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33, + IPU_IRQ_DC_READ_EOF = 40, + IPU_IRQ_DC_ASYNC_EOF = 41, + IPU_IRQ_DC_CMD1_EOF = 42, + IPU_IRQ_DC_CMD2_EOF = 43, + IPU_IRQ_DC_MASK_EOF = 44, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 46, + IPU_IRQ_PP_ROT_IN_EOF = 47, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49, + IPU_IRQ_PP_ROT_OUT_EOF = 50, + IPU_IRQ_BG_ALPHA_SYNC_EOF = 51, + IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52, + + IPU_IRQ_BG_SYNC_NFACK = 64 + 23, + IPU_IRQ_FG_SYNC_NFACK = 64 + 27, + IPU_IRQ_DC_SYNC_NFACK = 64 + 28, + + IPU_IRQ_DP_SF_START = 448 + 2, + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END, + IPU_IRQ_DC_FC_0 = 448 + 8, + IPU_IRQ_DC_FC_1 = 448 + 9, + IPU_IRQ_DC_FC_2 = 448 + 10, + IPU_IRQ_DC_FC_3 = 448 + 11, + IPU_IRQ_DC_FC_4 = 448 + 12, + IPU_IRQ_DC_FC_6 = 448 + 13, + IPU_IRQ_VSYNC_PRE_0 = 448 + 14, + IPU_IRQ_VSYNC_PRE_1 = 448 + 15, + + IPU_IRQ_COUNT +}; + +/*! + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned int_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +/*! + * Bitfield of CSI signal polarities and modes. + */ + +typedef struct { + unsigned data_width:4; + unsigned clk_mode:3; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; + unsigned pack_tight:1; + unsigned force_eof:1; + unsigned data_en_pol:1; + unsigned data_fmt; + unsigned csi; + unsigned mclk; +} ipu_csi_signal_cfg_t; + +/*! + * Enumeration of CSI data bus widths. + */ +enum { + IPU_CSI_DATA_WIDTH_4 = 0, + IPU_CSI_DATA_WIDTH_8 = 1, + IPU_CSI_DATA_WIDTH_10 = 3, + IPU_CSI_DATA_WIDTH_16 = 9, +}; + +/*! + * Enumeration of CSI clock modes. + */ +enum { + IPU_CSI_CLK_MODE_GATED_CLK, + IPU_CSI_CLK_MODE_NONGATED_CLK, + IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, + IPU_CSI_CLK_MODE_CCIR656_INTERLACED, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, +}; + +enum { + IPU_CSI_MIPI_DI0, + IPU_CSI_MIPI_DI1, + IPU_CSI_MIPI_DI2, + IPU_CSI_MIPI_DI3, +}; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/*! + * Enumeration of ADC vertical sync mode. + */ +typedef enum { + VsyncNone, + VsyncInternal, + VsyncCSI, + VsyncExternal +} vsync_t; + +typedef enum { + DAT, + CMD +} cmddata_t; + +/*! + * Enumeration of ADC display update mode. + */ +typedef enum { + IPU_ADC_REFRESH_NONE, + IPU_ADC_AUTO_REFRESH, + IPU_ADC_AUTO_REFRESH_SNOOP, + IPU_ADC_SNOOPING, +} ipu_adc_update_mode_t; + +/*! + * Enumeration of ADC display interface types (serial or parallel). + */ +enum { + IPU_ADC_IFC_MODE_SYS80_TYPE1, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + IPU_ADC_IFC_MODE_SYS68K_TYPE1, + IPU_ADC_IFC_MODE_SYS68K_TYPE2, + IPU_ADC_IFC_MODE_3WIRE_SERIAL, + IPU_ADC_IFC_MODE_4WIRE_SERIAL, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS, +}; + +enum { + IPU_ADC_IFC_WIDTH_8, + IPU_ADC_IFC_WIDTH_16, +}; + +/*! + * Enumeration of ADC display interface burst mode. + */ +enum { + IPU_ADC_BURST_WCS, + IPU_ADC_BURST_WBLCK, + IPU_ADC_BURST_NONE, + IPU_ADC_BURST_SERIAL, +}; + +/*! + * Enumeration of ADC display interface RW signal timing modes. + */ +enum { + IPU_ADC_SER_NO_RW, + IPU_ADC_SER_RW_BEFORE_RS, + IPU_ADC_SER_RW_AFTER_RS, +}; + +/*! + * Bitfield of ADC signal polarities and modes. + */ +typedef struct { + unsigned data_pol:1; + unsigned clk_pol:1; + unsigned cs_pol:1; + unsigned rs_pol:1; + unsigned addr_pol:1; + unsigned read_pol:1; + unsigned write_pol:1; + unsigned Vsync_pol:1; + unsigned burst_pol:1; + unsigned burst_mode:2; + unsigned ifc_mode:3; + unsigned ifc_width:5; + unsigned ser_preamble_len:4; + unsigned ser_preamble:8; + unsigned ser_rw_mode:2; +} ipu_adc_sig_cfg_t; + +/*! + * Enumeration of ADC template commands. + */ +enum { + RD_DATA, + RD_ACK, + RD_WAIT, + WR_XADDR, + WR_YADDR, + WR_ADDR, + WR_CMND, + WR_DATA, +}; + +/*! + * Enumeration of ADC template command flow control. + */ +enum { + SINGLE_STEP, + PAUSE, + STOP, +}; + + +/*Define template constants*/ +#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */ +#define TEMPLATE_BUF_SIZE 0x20 /*size of template */ + +/*! + * Define to create ADC template command entry. + */ +#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \ + ((oc) << 24) | (dat)) + +typedef struct { + u32 reg; + u32 value; +} ipu_lpmc_reg_t; + +#define IPU_LPMC_REG_READ 0x80000000L + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +struct ipu_soc; +/* Common IPU API */ +struct ipu_soc *ipu_get_soc(int id); +int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel); +void ipu_disable_hsp_clk(struct ipu_soc *ipu); + +static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) +{ +#ifdef CONFIG_MXC_IPU_V3D + return (rot < IPU_ROTATE_HORIZ_FLIP); +#else + return (rot < IPU_ROTATE_90_RIGHT); +#endif +} + +int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + dma_addr_t phyaddr_2, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset); + +int32_t ipu_get_channel_offset(uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset, + uint32_t *u_offset, uint32_t *v_offset); + +int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t bufNum); +int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum); + +int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); +int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); + +int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop); +int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch); +uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel); + +int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi); +int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi); + +int ipu_lowpwr_display_enable(void); +int ipu_lowpwr_display_disable(void); + +int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq); +int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id); +void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id); +bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq); +void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]); +int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t band_height); + +/* two stripe calculations */ +struct stripe_param{ + unsigned int input_width; /* width of the input stripe */ + unsigned int output_width; /* width of the output stripe */ + unsigned int input_column; /* the first column on the input stripe */ + unsigned int output_column; /* the first column on the output stripe */ + unsigned int idr; + /* inverse downisizing ratio parameter; expressed as a power of 2 */ + unsigned int irr; + /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */ +}; +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + unsigned int output_frame_width, + const unsigned int maximal_stripe_width, + const unsigned long long cirr, + const unsigned int equal_stripes, + u32 input_pixelformat, + u32 output_pixelformat, + struct stripe_param *left, + struct stripe_param *right); + +/* SDC API */ +int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp); + +int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos, + int16_t y_pos); +int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos, + int16_t *y_pos); +int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + int constk[], int slopek[]); + +int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig); +void ipu_reset_disp_panel(struct ipu_soc *ipu); + +/* CMOS Sensor Interface API */ +int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, + uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig); + +int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi); + +int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait); + +static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi, + bool flag, bool wait) +{ + return ipu_csi_enable_mclk(ipu, csi, flag, wait); +} + +int ipu_csi_read_mclk_flag(void); + +void ipu_csi_flash_strobe(bool flag); + +void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi); + +void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi); + +void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi); + +uint32_t bytes_per_pixel(uint32_t fmt); + +bool ipu_ch_param_bad_alpha_pos(uint32_t fmt); +int ipu_ch_param_get_axi_id(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +ipu_color_space_t format_to_colorspace(uint32_t fmt); +bool ipu_pixel_format_is_gpu_tile(uint32_t fmt); +bool ipu_pixel_format_is_split_gpu_tile(uint32_t fmt); +bool ipu_pixel_format_is_pre_yuv(uint32_t fmt); +bool ipu_pixel_format_is_multiplanar_yuv(uint32_t fmt); + +struct ipuv3_fb_platform_data { + char disp_dev[32]; + u32 interface_pix_fmt; + char *mode_str; + int default_bpp; + bool int_clk; + + /* reserved mem */ + resource_size_t res_base[2]; + resource_size_t res_size[2]; + + /* + * Late init to avoid display channel being + * re-initialized as we've probably setup the + * channel in bootloader. + */ + bool late_init; + + /* Enable prefetch engine or not? */ + bool prefetch; + + /* Enable the PRE resolve engine or not? */ + bool resolve; +}; + +#endif /* __LINUX_IPU_V3_H_ */ diff --git a/include/linux/ipu.h b/include/linux/ipu.h new file mode 100644 index 000000000000..1090ac65f24b --- /dev/null +++ b/include/linux/ipu.h @@ -0,0 +1,38 @@ +/* + * Copyright 2005-2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup IPU MXC Image Processing Unit (IPU) Driver + */ +/*! + * @file linux/ipu.h + * + * @brief This file contains the IPU driver API declarations. + * + * @ingroup IPU + */ + +#ifndef __LINUX_IPU_H__ +#define __LINUX_IPU_H__ + +#include <linux/interrupt.h> +#include <uapi/linux/ipu.h> + +unsigned int fmt_to_bpp(unsigned int pixelformat); +cs_t colorspaceofpixel(int fmt); +int need_csc(int ifmt, int ofmt); + +int ipu_queue_task(struct ipu_task *task); +int ipu_check_task(struct ipu_task *task); + +#endif diff --git a/include/linux/isl29023.h b/include/linux/isl29023.h new file mode 100644 index 000000000000..5c84566b7b21 --- /dev/null +++ b/include/linux/isl29023.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ISL29023_H__ +#define __ISL29023_H__ + +#include <linux/types.h> + +#define ISL29023_PD_MODE 0x0 +#define ISL29023_ALS_ONCE_MODE 0x1 +#define ISL29023_IR_ONCE_MODE 0x2 +#define ISL29023_ALS_CONT_MODE 0x5 +#define ISL29023_IR_CONT_MODE 0x6 + +#define ISL29023_INT_PERSISTS_1 0x0 +#define ISL29023_INT_PERSISTS_4 0x1 +#define ISL29023_INT_PERSISTS_8 0x2 +#define ISL29023_INT_PERSISTS_16 0x3 + +#define ISL29023_RES_16 0x0 +#define ISL29023_RES_12 0x1 +#define ISL29023_RES_8 0x2 +#define ISL29023_RES_4 0x3 + +#define ISL29023_RANGE_1K 0x0 +#define ISL29023_RANGE_4K 0x1 +#define ISL29023_RANGE_16K 0x2 +#define ISL29023_RANGE_64K 0x3 + +#endif diff --git a/include/linux/mfd/bd71837.h b/include/linux/mfd/bd71837.h new file mode 100644 index 000000000000..3cd51f314b20 --- /dev/null +++ b/include/linux/mfd/bd71837.h @@ -0,0 +1,413 @@ +/** + * @file bd71837.h ROHM BD71837MWV header file + * + * Copyright 2017 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * @author cpham2403@gmail.com + */ + +#ifndef __LINUX_MFD_BD71837_H +#define __LINUX_MFD_BD71837_H + +#include <linux/regmap.h> + +enum { + BD71837_BUCK1 = 0, + BD71837_BUCK2, + BD71837_BUCK3, + BD71837_BUCK4, + BD71837_BUCK5, + BD71837_BUCK6, + BD71837_BUCK7, + BD71837_BUCK8, + // General Purpose + BD71837_LDO1, + BD71837_LDO2, + BD71837_LDO3, + BD71837_LDO4, + BD71837_LDO5, + BD71837_LDO6, + BD71837_LDO7, + BD71837_REGULATOR_CNT, +}; + +#define BD71837_SUPPLY_STATE_ENABLED 0x1 + +#define BD71837_BUCK1_VOLTAGE_NUM 0x40 +#define BD71837_BUCK2_VOLTAGE_NUM 0x40 +#define BD71837_BUCK3_VOLTAGE_NUM 0x40 +#define BD71837_BUCK4_VOLTAGE_NUM 0x40 + +#define BD71837_BUCK5_VOLTAGE_NUM 0x08 +#define BD71837_BUCK6_VOLTAGE_NUM 0x04 +#define BD71837_BUCK7_VOLTAGE_NUM 0x08 +#define BD71837_BUCK8_VOLTAGE_NUM 0x40 + +#define BD71837_LDO1_VOLTAGE_NUM 0x04 +#define BD71837_LDO2_VOLTAGE_NUM 0x02 +#define BD71837_LDO3_VOLTAGE_NUM 0x10 +#define BD71837_LDO4_VOLTAGE_NUM 0x10 +#define BD71837_LDO5_VOLTAGE_NUM 0x10 +#define BD71837_LDO6_VOLTAGE_NUM 0x10 +#define BD71837_LDO7_VOLTAGE_NUM 0x10 + +enum { + BD71837_REG_REV = 0x00, + BD71837_REG_SWRESET = 0x01, + BD71837_REG_I2C_DEV = 0x02, + BD71837_REG_PWRCTRL0 = 0x03, + BD71837_REG_PWRCTRL1 = 0x04, + BD71837_REG_BUCK1_CTRL = 0x05, + BD71837_REG_BUCK2_CTRL = 0x06, + BD71837_REG_BUCK3_CTRL = 0x07, + BD71837_REG_BUCK4_CTRL = 0x08, + BD71837_REG_BUCK5_CTRL = 0x09, + BD71837_REG_BUCK6_CTRL = 0x0A, + BD71837_REG_BUCK7_CTRL = 0x0B, + BD71837_REG_BUCK8_CTRL = 0x0C, + BD71837_REG_BUCK1_VOLT_RUN = 0x0D, + BD71837_REG_BUCK1_VOLT_IDLE = 0x0E, + BD71837_REG_BUCK1_VOLT_SUSP = 0x0F, + BD71837_REG_BUCK2_VOLT_RUN = 0x10, + BD71837_REG_BUCK2_VOLT_IDLE = 0x11, + BD71837_REG_BUCK3_VOLT_RUN = 0x12, + BD71837_REG_BUCK4_VOLT_RUN = 0x13, + BD71837_REG_BUCK5_VOLT = 0x14, + BD71837_REG_BUCK6_VOLT = 0x15, + BD71837_REG_BUCK7_VOLT = 0x16, + BD71837_REG_BUCK8_VOLT = 0x17, + BD71837_REG_LDO1_VOLT = 0x18, + BD71837_REG_LDO2_VOLT = 0x19, + BD71837_REG_LDO3_VOLT = 0x1A, + BD71837_REG_LDO4_VOLT = 0x1B, + BD71837_REG_LDO5_VOLT = 0x1C, + BD71837_REG_LDO6_VOLT = 0x1D, + BD71837_REG_LDO7_VOLT = 0x1E, + BD71837_REG_TRANS_COND0 = 0x1F, + BD71837_REG_TRANS_COND1 = 0x20, + BD71837_REG_VRFAULTEN = 0x21, + BD71837_REG_MVRFLTMASK0 = 0x22, + BD71837_REG_MVRFLTMASK1 = 0x23, + BD71837_REG_MVRFLTMASK2 = 0x24, + BD71837_REG_RCVCFG = 0x25, + BD71837_REG_RCVNUM = 0x26, + BD71837_REG_PWRONCONFIG0 = 0x27, + BD71837_REG_PWRONCONFIG1 = 0x28, + BD71837_REG_RESETSRC = 0x29, + BD71837_REG_MIRQ = 0x2A, + BD71837_REG_IRQ = 0x2B, + BD71837_REG_IN_MON = 0x2C, + BD71837_REG_POW_STATE = 0x2D, + BD71837_REG_OUT32K = 0x2E, + BD71837_REG_REGLOCK = 0x2F, + BD71837_REG_OTPVER = 0xFF, + BD71837_MAX_REGISTER = 0x100, +}; + +/* BD71837_REG_BUCK1_CTRL bits */ +#define BUCK1_RAMPRATE_MASK 0xC0 +#define BUCK1_RAMPRATE_10P00MV 0x0 +#define BUCK1_RAMPRATE_5P00MV 0x1 +#define BUCK1_RAMPRATE_2P50MV 0x2 +#define BUCK1_RAMPRATE_1P25MV 0x3 +#define BUCK1_SEL 0x02 +#define BUCK1_EN 0x01 + +/* BD71837_REG_BUCK2_CTRL bits */ +#define BUCK2_RAMPRATE_MASK 0xC0 +#define BUCK2_RAMPRATE_10P00MV 0x0 +#define BUCK2_RAMPRATE_5P00MV 0x1 +#define BUCK2_RAMPRATE_2P50MV 0x2 +#define BUCK2_RAMPRATE_1P25MV 0x3 +#define BUCK2_SEL 0x02 +#define BUCK2_EN 0x01 + +/* BD71837_REG_BUCK3_CTRL bits */ +#define BUCK3_RAMPRATE_MASK 0xC0 +#define BUCK3_RAMPRATE_10P00MV 0x0 +#define BUCK3_RAMPRATE_5P00MV 0x1 +#define BUCK3_RAMPRATE_2P50MV 0x2 +#define BUCK3_RAMPRATE_1P25MV 0x3 +#define BUCK3_SEL 0x02 +#define BUCK3_EN 0x01 + +/* BD71837_REG_BUCK4_CTRL bits */ +#define BUCK4_RAMPRATE_MASK 0xC0 +#define BUCK4_RAMPRATE_10P00MV 0x0 +#define BUCK4_RAMPRATE_5P00MV 0x1 +#define BUCK4_RAMPRATE_2P50MV 0x2 +#define BUCK4_RAMPRATE_1P25MV 0x3 +#define BUCK4_SEL 0x02 +#define BUCK4_EN 0x01 + +/* BD71837_REG_BUCK5_CTRL bits */ +#define BUCK5_SEL 0x02 +#define BUCK5_EN 0x01 + +/* BD71837_REG_BUCK6_CTRL bits */ +#define BUCK6_SEL 0x02 +#define BUCK6_EN 0x01 + +/* BD71837_REG_BUCK7_CTRL bits */ +#define BUCK7_SEL 0x02 +#define BUCK7_EN 0x01 + +/* BD71837_REG_BUCK8_CTRL bits */ +#define BUCK8_SEL 0x02 +#define BUCK8_EN 0x01 + +/* BD71837_REG_BUCK1_VOLT_RUN bits */ +#define BUCK1_RUN_MASK 0x3F +#define BUCK1_RUN_DEFAULT 0x14 + +/* BD71837_REG_BUCK1_VOLT_SUSP bits */ +#define BUCK1_SUSP_MASK 0x3F +#define BUCK1_SUSP_DEFAULT 0x14 + +/* BD71837_REG_BUCK1_VOLT_IDLE bits */ +#define BUCK1_IDLE_MASK 0x3F +#define BUCK1_IDLE_DEFAULT 0x14 + +/* BD71837_REG_BUCK2_VOLT_RUN bits */ +#define BUCK2_RUN_MASK 0x3F +#define BUCK2_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK2_VOLT_IDLE bits */ +#define BUCK2_IDLE_MASK 0x3F +#define BUCK2_IDLE_DEFAULT 0x14 + +/* BD71837_REG_BUCK3_VOLT_RUN bits */ +#define BUCK3_RUN_MASK 0x3F +#define BUCK3_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK4_VOLT_RUN bits */ +#define BUCK4_RUN_MASK 0x3F +#define BUCK4_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK5_VOLT bits */ +#define BUCK5_MASK 0x07 +#define BUCK5_DEFAULT 0x02 + +/* BD71837_REG_BUCK6_VOLT bits */ +#define BUCK6_MASK 0x03 +#define BUCK6_DEFAULT 0x03 + +/* BD71837_REG_BUCK7_VOLT bits */ +#define BUCK7_MASK 0x07 +#define BUCK7_DEFAULT 0x03 + +/* BD71837_REG_BUCK8_VOLT bits */ +#define BUCK8_MASK 0x3F +#define BUCK8_DEFAULT 0x1E + +/* BD71837_REG_IRQ bits */ +#define IRQ_SWRST 0x40 +#define IRQ_PWRON_S 0x20 +#define IRQ_PWRON_L 0x10 +#define IRQ_PWRON 0x08 +#define IRQ_WDOG 0x04 +#define IRQ_ON_REQ 0x02 +#define IRQ_STBY_REQ 0x01 + +/* BD71837_REG_OUT32K bits */ +#define OUT32K_EN 0x01 + +/* BD71837 interrupt masks */ +enum { + BD71837_INT_MASK = 0x7F, +}; +/* BD71837 interrupt irqs */ +enum { + BD71837_IRQ = 0x0, +}; + +/* BD71837_REG_LDO1_VOLT bits */ +#define LDO1_SEL 0x80 +#define LDO1_EN 0x40 +#define LDO1_MASK 0x03 + +/* BD71837_REG_LDO2_VOLT bits */ +#define LDO2_SEL 0x80 +#define LDO2_EN 0x40 + +/* BD71837_REG_LDO3_VOLT bits */ +#define LDO3_SEL 0x80 +#define LDO3_EN 0x40 +#define LDO3_MASK 0x0F + +/* BD71837_REG_LDO4_VOLT bits */ +#define LDO4_SEL 0x80 +#define LDO4_EN 0x40 +#define LDO4_MASK 0x0F + +/* BD71837_REG_LDO5_VOLT bits */ +#define LDO5_EN 0x40 +#define LDO5_MASK 0x0F + +/* BD71837_REG_LDO6_VOLT bits */ +#define LDO6_EN 0x40 +#define LDO6_MASK 0x0F + +/* BD71837_REG_LDO7_VOLT bits */ +#define LDO7_EN 0x40 +#define LDO7_MASK 0x0F + +/** @brief charge state enumuration */ +enum CHG_STATE { + CHG_STATE_SUSPEND = 0x0, /**< suspend state */ + CHG_STATE_TRICKLE_CHARGE, /**< trickle charge state */ + CHG_STATE_PRE_CHARGE, /**< precharge state */ + CHG_STATE_FAST_CHARGE, /**< fast charge state */ + CHG_STATE_TOP_OFF, /**< top off state */ + CHG_STATE_DONE, /**< charge complete */ +}; + +struct bd71837; + +/** + * @brief Board platform data may be used to initialize regulators. + */ + +struct bd71837_board { + struct regulator_init_data *init_data[BD71837_REGULATOR_CNT]; + /**< regulator initialize data */ + int gpio_intr; /**< gpio connected to bd71837 INTB */ + int irq_base; /**< bd71837 sub irqs base # */ +}; + +/** + * @brief bd71837 sub-driver chip access routines + */ + +struct bd71837 { + struct device *dev; + struct i2c_client *i2c_client; + struct regmap *regmap; + struct mutex io_mutex; + unsigned int id; + + /* IRQ Handling */ + int chip_irq; /**< bd71837 irq to host cpu */ + struct regmap_irq_chip_data *irq_data; + + /* Client devices */ + struct bd71837_pmic *pmic; /**< client device regulator */ + struct bd71837_power *power; /**< client device battery */ + + struct bd71837_board *of_plat_data; + /**< Device node parsed board data */ +}; + +static inline int bd71837_chip_id(struct bd71837 *bd71837) +{ + return bd71837->id; +} + + +/** + * @brief bd71837_reg_read + * read single register's value of bd71837 + * @param bd71837 device to read + * @param reg register address + * @return register value if success + * error number if fail + */ +static inline int bd71837_reg_read(struct bd71837 *bd71837, u8 reg) +{ + int r, val; + + r = regmap_read(bd71837->regmap, reg, &val); + if (r < 0) { + return r; + } + return val; +} + +/** + * @brief bd71837_reg_write + * write single register of bd71837 + * @param bd71837 device to write + * @param reg register address + * @param val value to write + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_reg_write(struct bd71837 *bd71837, u8 reg, + unsigned int val) +{ + return regmap_write(bd71837->regmap, reg, val); +} + +/** + * @brief bd71837_set_bits + * set bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ +static inline int bd71837_set_bits(struct bd71837 *bd71837, u8 reg, u8 mask) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, mask); +} + +/** + * @brief bd71837_clear_bits + * clear bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_clear_bits(struct bd71837 *bd71837, u8 reg, + u8 mask) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, 0); +} + +/** + * @brief bd71837_update_bits + * update bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @param val value to update + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_update_bits(struct bd71837 *bd71837, u8 reg, + u8 mask, u8 val) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, val); +} + +/** + * @brief bd71837 platform data type + */ +struct bd71837_gpo_plat_data { + u32 drv; ///< gpo output drv + int gpio_base; ///< base gpio number in system +}; + +u8 ext_bd71837_reg_read8(u8 reg); +int ext_bd71837_reg_write8(int reg, u8 val); + +#define BD71837_DBG0 0x0001 +#define BD71837_DBG1 0x0002 +#define BD71837_DBG2 0x0004 +#define BD71837_DBG3 0x0008 + +extern unsigned int bd71837_debug_mask; +#define bd71837_debug(debug, fmt, arg...) do { if (debug & bd71837_debug_mask) printk("BD71837:" fmt, ##arg); } while (0) + +#endif /* __LINUX_MFD_BD71837_H */ diff --git a/include/linux/mfd/max17135.h b/include/linux/mfd/max17135.h new file mode 100644 index 000000000000..e3b8777c8630 --- /dev/null +++ b/include/linux/mfd/max17135.h @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __LINUX_REGULATOR_MAX17135_H_ +#define __LINUX_REGULATOR_MAX17135_H_ + +/* + * PMIC Register Addresses + */ +enum { + REG_MAX17135_EXT_TEMP = 0x0, + REG_MAX17135_CONFIG, + REG_MAX17135_INT_TEMP = 0x4, + REG_MAX17135_STATUS, + REG_MAX17135_PRODUCT_REV, + REG_MAX17135_PRODUCT_ID, + REG_MAX17135_DVR, + REG_MAX17135_ENABLE, + REG_MAX17135_FAULT, /*0x0A*/ + REG_MAX17135_HVINP, + REG_MAX17135_PRGM_CTRL, + REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */ + REG_MAX17135_TIMING2, + REG_MAX17135_TIMING3, + REG_MAX17135_TIMING4, + REG_MAX17135_TIMING5, + REG_MAX17135_TIMING6, + REG_MAX17135_TIMING7, + REG_MAX17135_TIMING8, +}; +#define MAX17135_REG_NUM 21 +#define MAX17135_MAX_REGISTER 0xFF + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Shift and width values for each register bitfield + */ +#define EXT_TEMP_LSH 7 +#define EXT_TEMP_WID 9 + +#define THERMAL_SHUTDOWN_LSH 0 +#define THERMAL_SHUTDOWN_WID 1 + +#define INT_TEMP_LSH 7 +#define INT_TEMP_WID 9 + +#define STAT_BUSY_LSH 0 +#define STAT_BUSY_WID 1 +#define STAT_OPEN_LSH 1 +#define STAT_OPEN_WID 1 +#define STAT_SHRT_LSH 2 +#define STAT_SHRT_WID 1 + +#define PROD_REV_LSH 0 +#define PROD_REV_WID 8 + +#define PROD_ID_LSH 0 +#define PROD_ID_WID 8 + +#define DVR_LSH 0 +#define DVR_WID 8 + +#define ENABLE_LSH 0 +#define ENABLE_WID 1 +#define VCOM_ENABLE_LSH 1 +#define VCOM_ENABLE_WID 1 + +#define FAULT_FBPG_LSH 0 +#define FAULT_FBPG_WID 1 +#define FAULT_HVINP_LSH 1 +#define FAULT_HVINP_WID 1 +#define FAULT_HVINN_LSH 2 +#define FAULT_HVINN_WID 1 +#define FAULT_FBNG_LSH 3 +#define FAULT_FBNG_WID 1 +#define FAULT_HVINPSC_LSH 4 +#define FAULT_HVINPSC_WID 1 +#define FAULT_HVINNSC_LSH 5 +#define FAULT_HVINNSC_WID 1 +#define FAULT_OT_LSH 6 +#define FAULT_OT_WID 1 +#define FAULT_POK_LSH 7 +#define FAULT_POK_WID 1 + +#define HVINP_LSH 0 +#define HVINP_WID 4 + +#define CTRL_DVR_LSH 0 +#define CTRL_DVR_WID 1 +#define CTRL_TIMING_LSH 1 +#define CTRL_TIMING_WID 1 + +#define TIMING1_LSH 0 +#define TIMING1_WID 8 +#define TIMING2_LSH 0 +#define TIMING2_WID 8 +#define TIMING3_LSH 0 +#define TIMING3_WID 8 +#define TIMING4_LSH 0 +#define TIMING4_WID 8 +#define TIMING5_LSH 0 +#define TIMING5_WID 8 +#define TIMING6_LSH 0 +#define TIMING6_WID 8 +#define TIMING7_LSH 0 +#define TIMING7_WID 8 +#define TIMING8_LSH 0 +#define TIMING8_WID 8 + +struct max17135 { + /* chip revision */ + int rev; + + struct device *dev; + struct max17135_platform_data *pdata; + + /* Platform connection */ + struct i2c_client *i2c_client; + + /* Timings */ + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + + /* GPIOs */ + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_v3p3; + int gpio_pmic_intr; + + /* MAX17135 part variables */ + int pass_num; + int vcom_uV; + + /* One-time VCOM setup marker */ + bool vcom_setup; + + /* powerup/powerdown wait time */ + int max_wait; +}; + +enum { + /* In alphabetical order */ + MAX17135_DISPLAY, /* virtual master enable */ + MAX17135_GVDD, + MAX17135_GVEE, + MAX17135_HVINN, + MAX17135_HVINP, + MAX17135_VCOM, + MAX17135_VNEG, + MAX17135_VPOS, + MAX17135_V3P3, + MAX17135_NUM_REGULATORS, +}; + +/* + * Declarations + */ +struct regulator_init_data; +struct max17135_regulator_data; + +struct max17135_platform_data { + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_v3p3; + int gpio_pmic_intr; + int pass_num; + int vcom_uV; + + /* PMIC */ + struct max17135_regulator_data *regulators; + int num_regulators; +}; + +struct max17135_regulator_data { + int id; + struct regulator_init_data *initdata; + struct device_node *reg_node; +}; + +int max17135_reg_read(int reg_num, unsigned int *reg_val); +int max17135_reg_write(int reg_num, const unsigned int reg_val); + +#endif diff --git a/include/linux/mfd/mxc-hdmi-core.h b/include/linux/mfd/mxc-hdmi-core.h new file mode 100644 index 000000000000..b2696b951f43 --- /dev/null +++ b/include/linux/mfd/mxc-hdmi-core.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_MXC_HDMI_CORE_H_ +#define __LINUX_MXC_HDMI_CORE_H_ + +#include <video/mxc_edid.h> + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> + +#define IRQ_DISABLE_SUCCEED 0 +#define IRQ_DISABLE_FAIL 1 + +bool hdmi_check_overflow(void); + +u8 hdmi_readb(unsigned int reg); +void hdmi_writeb(u8 value, unsigned int reg); +void hdmi_mask_writeb(u8 data, unsigned int addr, u8 shift, u8 mask); +unsigned int hdmi_read4(unsigned int reg); +void hdmi_write4(unsigned int value, unsigned int reg); + +void hdmi_irq_init(void); +void hdmi_irq_enable(int irq); +unsigned int hdmi_irq_disable(int irq); + +void hdmi_set_sample_rate(unsigned int rate); +void hdmi_set_dma_mode(unsigned int dma_running); +void hdmi_init_clk_regenerator(void); +void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock); + +void hdmi_set_edid_cfg(struct mxc_edid_cfg *cfg); +void hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg); + +extern int mxc_hdmi_ipu_id; +extern int mxc_hdmi_disp_id; + +void hdmi_set_registered(int registered); +int hdmi_get_registered(void); +int mxc_hdmi_abort_stream(void); +int mxc_hdmi_register_audio(struct snd_pcm_substream *substream); +void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream); +unsigned int hdmi_set_cable_state(unsigned int state); +unsigned int hdmi_set_blank_state(unsigned int state); +int check_hdmi_state(void); + +#endif diff --git a/include/linux/mfd/pca9450.h b/include/linux/mfd/pca9450.h new file mode 100644 index 000000000000..b689c2dd3b94 --- /dev/null +++ b/include/linux/mfd/pca9450.h @@ -0,0 +1,355 @@ +/** + * @file pca9450.h NXP PCA9450 header file + * + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_PCA9450_H +#define __LINUX_MFD_PCA9450_H + +#include <linux/regmap.h> + +enum { + PCA9450_BUCK1 = 0, + PCA9450_BUCK2, + PCA9450_BUCK3, + PCA9450_BUCK4, + PCA9450_BUCK5, + PCA9450_BUCK6, + PCA9450_LDO1, + PCA9450_LDO2, + PCA9450_LDO3, + PCA9450_LDO4, + PCA9450_LDO5, + PCA9450_REGULATOR_CNT, +}; + +#define PCA9450_SUPPLY_STATE_ENABLED 0x1 + +#define PCA9450_BUCK1_VOLTAGE_NUM 0x80 +#define PCA9450_BUCK2_VOLTAGE_NUM 0x80 +#define PCA9450_BUCK3_VOLTAGE_NUM 0x80 +#define PCA9450_BUCK4_VOLTAGE_NUM 0x80 + +#define PCA9450_BUCK5_VOLTAGE_NUM 0x80 +#define PCA9450_BUCK6_VOLTAGE_NUM 0x80 + +#define PCA9450_LDO1_VOLTAGE_NUM 0x08 +#define PCA9450_LDO2_VOLTAGE_NUM 0x08 +#define PCA9450_LDO3_VOLTAGE_NUM 0x20 +#define PCA9450_LDO4_VOLTAGE_NUM 0x20 +#define PCA9450_LDO5_VOLTAGE_NUM 0x10 + +enum { + PCA9450_REG_DEV_ID = 0x00, + PCA9450_INT1 = 0x01, + PCA9450_INT1_MSK = 0x02, + PCA9450_STATUS1 = 0x03, + PCA9450_STATUS2 = 0x04, + PCA9450_PWRON_STAT = 0x05, + PCA9450_SW_RST = 0x06, + PCA9450_PWR_CTRL = 0x07, + PCA9450_RESET_CTRL = 0x08, + PCA9450_CONFIG1 = 0x09, + PCA9450_CONFIG2 = 0x0A, + PCA9450_BUCK123_DVS = 0x0C, + PCA9450_BUCK1OUT_LIMIT = 0x0D, + PCA9450_BUCK2OUT_LIMIT = 0x0E, + PCA9450_BUCK3OUT_LIMIT = 0x0F, + PCA9450_BUCK1CTRL = 0x10, + PCA9450_BUCK1OUT_DVS0 = 0x11, + PCA9450_BUCK1OUT_DVS1 = 0x12, + PCA9450_BUCK2CTRL = 0x13, + PCA9450_BUCK2OUT_DVS0 = 0x14, + PCA9450_BUCK2OUT_DVS1 = 0x15, + PCA9450_BUCK3CTRL = 0x16, + PCA9450_BUCK3OUT_DVS0 = 0x17, + PCA9450_BUCK3OUT_DVS1 = 0x18, + PCA9450_BUCK4CTRL = 0x19, + PCA9450_BUCK4OUT = 0x1A, + PCA9450_BUCK5CTRL = 0x1B, + PCA9450_BUCK5OUT = 0x1C, + PCA9450_BUCK6CTRL = 0x1D, + PCA9450_BUCK6OUT = 0x1E, + PCA9450_LDO_AD_CTRL = 0x20, + PCA9450_LDO1CTRL = 0x21, + PCA9450_LDO2CTRL = 0x22, + PCA9450_LDO3CTRL = 0x23, + PCA9450_LDO4CTRL = 0x24, + PCA9450_LDO5CTRL_L = 0x25, + PCA9450_LDO5CTRL_H = 0x26, + PCA9450_LOADSW_CTRL = 0x2A, + PCA9450_VRFLT1_STS = 0x2B, + PCA9450_VRFLT2_STS = 0x2C, + PCA9450_VRFLT1_MASK = 0x2D, + PCA9450_VRFLT2_MASK = 0x2E, + PCA9450_MAX_REGISTER = 0x2F, +}; + +/* PCA9450 BUCK ENMODE bits */ +#define BUCK_ENMODE_OFF 0x00 +#define BUCK_ENMODE_ONREQ 0x01 +#define BUCK_ENMODE_ONREQ_STBYREQ 0x02 +#define BUCK_ENMODE_ON 0x03 + +/* PCA9450_REG_BUCK1_CTRL bits */ +#define BUCK1_RAMP_MASK 0xC0 +#define BUCK1_RAMP_25MV 0x0 +#define BUCK1_RAMP_12P5MV 0x1 +#define BUCK1_RAMP_6P25MV 0x2 +#define BUCK1_RAMP_3P125MV 0x3 +#define BUCK1_DVS_CTRL 0x10 +#define BUCK1_AD 0x08 +#define BUCK1_FPWM 0x04 +#define BUCK1_ENMODE_MASK 0x03 + +/* PCA9450_REG_BUCK2_CTRL bits */ +#define BUCK2_RAMP_MASK 0xC0 +#define BUCK2_RAMP_25MV 0x0 +#define BUCK2_RAMP_12P5MV 0x1 +#define BUCK2_RAMP_6P25MV 0x2 +#define BUCK2_RAMP_3P125MV 0x3 +#define BUCK2_DVS_CTRL 0x10 +#define BUCK2_AD 0x08 +#define BUCK2_FPWM 0x04 +#define BUCK2_ENMODE_MASK 0x03 + +/* PCA9450_REG_BUCK3_CTRL bits */ +#define BUCK3_RAMP_MASK 0xC0 +#define BUCK3_RAMP_25MV 0x0 +#define BUCK3_RAMP_12P5MV 0x1 +#define BUCK3_RAMP_6P25MV 0x2 +#define BUCK3_RAMP_3P125MV 0x3 +#define BUCK3_DVS_CTRL 0x10 +#define BUCK3_AD 0x08 +#define BUCK3_FPWM 0x04 +#define BUCK3_ENMODE_MASK 0x03 + +/* PCA9450_REG_BUCK4_CTRL bits */ +#define BUCK4_AD 0x08 +#define BUCK4_FPWM 0x04 +#define BUCK4_ENMODE_MASK 0x03 + +/* PCA9450_REG_BUCK5_CTRL bits */ +#define BUCK5_AD 0x08 +#define BUCK5_FPWM 0x04 +#define BUCK5_ENMODE_MASK 0x03 + +/* PCA9450_REG_BUCK6_CTRL bits */ +#define BUCK6_AD 0x08 +#define BUCK6_FPWM 0x04 +#define BUCK6_ENMODE_MASK 0x03 + +/* PCA9450_BUCK1OUT_DVS0 bits */ +#define BUCK1OUT_DVS0_MASK 0x7F +#define BUCK1OUT_DVS0_DEFAULT 0x14 + +/* PCA9450_BUCK1OUT_DVS1 bits */ +#define BUCK1OUT_DVS1_MASK 0x7F +#define BUCK1OUT_DVS1_DEFAULT 0x14 + +/* PCA9450_BUCK2OUT_DVS0 bits */ +#define BUCK2OUT_DVS0_MASK 0x7F +#define BUCK2OUT_DVS0_DEFAULT 0x14 + +/* PCA9450_BUCK2OUT_DVS1 bits */ +#define BUCK2OUT_DVS1_MASK 0x7F +#define BUCK2OUT_DVS1_DEFAULT 0x14 + +/* PCA9450_BUCK3OUT_DVS0 bits */ +#define BUCK3OUT_DVS0_MASK 0x7F +#define BUCK3OUT_DVS0_DEFAULT 0x14 + +/* PCA9450_BUCK3OUT_DVS1 bits */ +#define BUCK3OUT_DVS1_MASK 0x7F +#define BUCK3OUT_DVS1_DEFAULT 0x14 + +/* PCA9450_REG_BUCK4OUT bits */ +#define BUCK4OUT_MASK 0x7F +#define BUCK4OUT_DEFAULT 0x6C + +/* PCA9450_REG_BUCK5OUT bits */ +#define BUCK5OUT_MASK 0x7F +#define BUCK5OUT_DEFAULT 0x30 + +/* PCA9450_REG_BUCK6OUT bits */ +#define BUCK6OUT_MASK 0x7F +#define BUCK6OUT_DEFAULT 0x14 + +/* PCA9450_REG_IRQ bits */ +#define IRQ_PWRON 0x80 +#define IRQ_WDOGB 0x40 +#define IRQ_VR_FLT1 0x10 +#define IRQ_VR_FLT2 0x08 +#define IRQ_LOWVSYS 0x04 +#define IRQ_THERM_105 0x02 +#define IRQ_THERM_125 0x01 + +/* PCA9450 interrupt masks */ +enum { + PCA9450_INT_MASK = 0xDF, +}; +/* PCA9450 interrupt irqs */ +enum { + PCA9450_IRQ = 0x0, +}; + +/* PCA9450_REG_LDO1_VOLT bits */ +#define LDO1_EN_MASK 0xC0 +#define LDO1OUT_MASK 0x07 + +/* PCA9450_REG_LDO2_VOLT bits */ +#define LDO2_EN_MASK 0xC0 +#define LDO2OUT_MASK 0x07 + +/* PCA9450_REG_LDO3_VOLT bits */ +#define LDO3_EN_MASK 0xC0 +#define LDO3OUT_MASK 0x0F + +/* PCA9450_REG_LDO4_VOLT bits */ +#define LDO4_EN_MASK 0xC0 +#define LDO4OUT_MASK 0x0F + +/* PCA9450_REG_LDO5_VOLT bits */ +#define LDO5L_EN_MASK 0xC0 +#define LDO5LOUT_MASK 0x0F + +#define LDO5H_EN_MASK 0xC0 +#define LDO5HOUT_MASK 0x0F + +/* + * @brief Board platform data may be used to initialize regulators. + */ + +struct pca9450_board { + struct regulator_init_data *init_data[PCA9450_REGULATOR_CNT]; + int gpio_intr; + int irq_base; +}; + +/* + * @brief pca9450 sub-driver chip access routines + */ + +struct pca9450 { + struct device *dev; + struct i2c_client *i2c_client; + struct regmap *regmap; + struct mutex io_mutex; + unsigned int id; + + /* IRQ Handling */ + int chip_irq; + struct regmap_irq_chip_data *irq_data; + + /* Client devices */ + struct pca9450_pmic *pmic; + struct pca9450_power *power; + + struct pca9450_board *of_plat_data; +}; + +static inline int pca9450_chip_id(struct pca9450 *pca9450) +{ + return pca9450->id; +} + +/* + * @brief pca9450_reg_read + * read single register's value of pca9450 + * @param pca9450 device to read + * @param reg register address + * @return register value if success + * error number if fail + */ +static inline int pca9450_reg_read(struct pca9450 *pca9450, u8 reg) +{ + int r, val; + + r = regmap_read(pca9450->regmap, reg, &val); + if (r < 0) + return r; + + return val; +} + +/* + * @brief pca9450_reg_write + * write single register of pca9450 + * @param pca9450 device to write + * @param reg register address + * @param val value to write + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int pca9450_reg_write(struct pca9450 *pca9450, u8 reg, + unsigned int val) +{ + return regmap_write(pca9450->regmap, reg, val); +} + +/* + * @brief pca9450_set_bits + * set bits in one register of pca9450 + * @param pca9450 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ +static inline int pca9450_set_bits(struct pca9450 *pca9450, u8 reg, u8 mask) +{ + return regmap_update_bits(pca9450->regmap, reg, mask, mask); +} + +/* + * @brief pca9450_clear_bits + * clear bits in one register of pca9450 + * @param pca9450 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int pca9450_clear_bits(struct pca9450 *pca9450, u8 reg, + u8 mask) +{ + return regmap_update_bits(pca9450->regmap, reg, mask, 0); +} + +/* + * @brief pca9450_update_bits + * update bits in one register of pca9450 + * @param pca9450 device to read + * @param reg register address + * @param mask mask bits + * @param val value to update + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int pca9450_update_bits(struct pca9450 *pca9450, u8 reg, + u8 mask, u8 val) +{ + return regmap_update_bits(pca9450->regmap, reg, mask, val); +} + +/* + * @brief pca9450 platform data type + */ +struct pca9450_gpo_plat_data { + u32 drv; + int gpio_base; +}; + +u8 ext_pca9450_reg_read8(u8 reg); +int ext_pca9450_reg_write8(int reg, u8 val); +#endif /* __LINUX_MFD_PCA9450_H */ diff --git a/include/linux/mfd/pf1550.h b/include/linux/mfd/pf1550.h new file mode 100644 index 000000000000..7d0a13e1144a --- /dev/null +++ b/include/linux/mfd/pf1550.h @@ -0,0 +1,250 @@ +/* + * pf1550.h - mfd head file for PF1550 + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Robin Gong <yibin.gong@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_MFD_PF1550_H +#define __LINUX_MFD_PF1550_H + +#include <linux/i2c.h> + +enum chips { PF1550 = 1, }; + +enum pf1550_pmic_reg { + /* PMIC regulator part */ + PF1550_PMIC_REG_DEVICE_ID = 0x00, + PF1550_PMIC_REG_OTP_FLAVOR = 0x01, + PF1550_PMIC_REG_SILICON_REV = 0x02, + + PF1550_PMIC_REG_INT_CATEGORY = 0x06, + PF1550_PMIC_REG_SW_INT_STAT0 = 0x08, + PF1550_PMIC_REG_SW_INT_MASK0 = 0x09, + PF1550_PMIC_REG_SW_INT_SENSE0 = 0x0A, + PF1550_PMIC_REG_SW_INT_STAT1 = 0x0B, + PF1550_PMIC_REG_SW_INT_MASK1 = 0x0C, + PF1550_PMIC_REG_SW_INT_SENSE1 = 0x0D, + PF1550_PMIC_REG_SW_INT_STAT2 = 0x0E, + PF1550_PMIC_REG_SW_INT_MASK2 = 0x0F, + PF1550_PMIC_REG_SW_INT_SENSE2 = 0x10, + PF1550_PMIC_REG_LDO_INT_STAT0 = 0x18, + PF1550_PMIC_REG_LDO_INT_MASK0 = 0x19, + PF1550_PMIC_REG_LDO_INT_SENSE0 = 0x1A, + PF1550_PMIC_REG_TEMP_INT_STAT0 = 0x20, + PF1550_PMIC_REG_TEMP_INT_MASK0 = 0x21, + PF1550_PMIC_REG_TEMP_INT_SENSE0 = 0x22, + PF1550_PMIC_REG_ONKEY_INT_STAT0 = 0x24, + PF1550_PMIC_REG_ONKEY_INT_MASK0 = 0x25, + PF1550_PMIC_REG_ONKEY_INT_SENSE0 = 0x26, + PF1550_PMIC_REG_MISC_INT_STAT0 = 0x28, + PF1550_PMIC_REG_MISC_INT_MASK0 = 0x29, + PF1550_PMIC_REG_MISC_INT_SENSE0 = 0x2A, + + PF1550_PMIC_REG_COINCELL_CONTROL = 0x30, + + PF1550_PMIC_REG_SW1_VOLT = 0x32, + PF1550_PMIC_REG_SW1_STBY_VOLT = 0x33, + PF1550_PMIC_REG_SW1_SLP_VOLT = 0x34, + PF1550_PMIC_REG_SW1_CTRL = 0x35, + PF1550_PMIC_REG_SW1_CTRL1 = 0x36, + PF1550_PMIC_REG_SW2_VOLT = 0x38, + PF1550_PMIC_REG_SW2_STBY_VOLT = 0x39, + PF1550_PMIC_REG_SW2_SLP_VOLT = 0x3A, + PF1550_PMIC_REG_SW2_CTRL = 0x3B, + PF1550_PMIC_REG_SW2_CTRL1 = 0x3C, + PF1550_PMIC_REG_SW3_VOLT = 0x3E, + PF1550_PMIC_REG_SW3_STBY_VOLT = 0x3F, + PF1550_PMIC_REG_SW3_SLP_VOLT = 0x40, + PF1550_PMIC_REG_SW3_CTRL = 0x41, + PF1550_PMIC_REG_SW3_CTRL1 = 0x42, + PF1550_PMIC_REG_VSNVS_CTRL = 0x48, + PF1550_PMIC_REG_VREFDDR_CTRL = 0x4A, + PF1550_PMIC_REG_LDO1_VOLT = 0x4C, + PF1550_PMIC_REG_LDO1_CTRL = 0x4D, + PF1550_PMIC_REG_LDO2_VOLT = 0x4F, + PF1550_PMIC_REG_LDO2_CTRL = 0x50, + PF1550_PMIC_REG_LDO3_VOLT = 0x52, + PF1550_PMIC_REG_LDO3_CTRL = 0x53, + PF1550_PMIC_REG_PWRCTRL0 = 0x58, + PF1550_PMIC_REG_PWRCTRL1 = 0x59, + PF1550_PMIC_REG_PWRCTRL2 = 0x5A, + PF1550_PMIC_REG_PWRCTRL3 = 0x5B, + PF1550_PMIC_REG_SW1_PWRDN_SEQ = 0x5F, + PF1550_PMIC_REG_SW2_PWRDN_SEQ = 0x60, + PF1550_PMIC_REG_SW3_PWRDN_SEQ = 0x61, + PF1550_PMIC_REG_LDO1_PWRDN_SEQ = 0x62, + PF1550_PMIC_REG_LDO2_PWRDN_SEQ = 0x63, + PF1550_PMIC_REG_LDO3_PWRDN_SEQ = 0x64, + PF1550_PMIC_REG_VREFDDR_PWRDN_SEQ = 0x65, + + PF1550_PMIC_REG_STATE_INFO = 0x67, + PF1550_PMIC_REG_I2C_ADDR = 0x68, + PF1550_PMIC_REG_IO_DRV0 = 0x69, + PF1550_PMIC_REG_IO_DRV1 = 0x6A, + PF1550_PMIC_REG_RC_16MHZ = 0x6B, + PF1550_PMIC_REG_KEY = 0x6F, + + /* charger part */ + PF1550_CHARG_REG_CHG_INT = 0x80, + PF1550_CHARG_REG_CHG_INT_MASK = 0x82, + PF1550_CHARG_REG_CHG_INT_OK = 0x84, + PF1550_CHARG_REG_VBUS_SNS = 0x86, + PF1550_CHARG_REG_CHG_SNS = 0x87, + PF1550_CHARG_REG_BATT_SNS = 0x88, + PF1550_CHARG_REG_CHG_OPER = 0x89, + PF1550_CHARG_REG_CHG_TMR = 0x8A, + PF1550_CHARG_REG_CHG_EOC_CNFG = 0x8D, + PF1550_CHARG_REG_CHG_CURR_CNFG = 0x8E, + PF1550_CHARG_REG_BATT_REG = 0x8F, + PF1550_CHARG_REG_BATFET_CNFG = 0x91, + PF1550_CHARG_REG_THM_REG_CNFG = 0x92, + PF1550_CHARG_REG_VBUS_INLIM_CNFG = 0x94, + PF1550_CHARG_REG_VBUS_LIN_DPM = 0x95, + PF1550_CHARG_REG_USB_PHY_LDO_CNFG = 0x96, + PF1550_CHARG_REG_DBNC_DELAY_TIME = 0x98, + PF1550_CHARG_REG_CHG_INT_CNFG = 0x99, + PF1550_CHARG_REG_THM_ADJ_SETTING = 0x9A, + PF1550_CHARG_REG_VBUS2SYS_CNFG = 0x9B, + PF1550_CHARG_REG_LED_PWM = 0x9C, + PF1550_CHARG_REG_FAULT_BATFET_CNFG = 0x9D, + PF1550_CHARG_REG_LED_CNFG = 0x9E, + PF1550_CHARG_REG_CHGR_KEY2 = 0x9F, + + PF1550_TEST_REG_FMRADDR = 0xC4, + PF1550_TEST_REG_FMRDATA = 0xC5, + PF1550_TEST_REG_KEY3 = 0xDF, + + PF1550_PMIC_REG_END = 0xff, +}; + +#define PF1550_CHG_PRECHARGE 0 +#define PF1550_CHG_CONSTANT_CURRENT 1 +#define PF1550_CHG_CONSTANT_VOL 2 +#define PF1550_CHG_EOC 3 +#define PF1550_CHG_DONE 4 +#define PF1550_CHG_TIMER_FAULT 6 +#define PF1550_CHG_SUSPEND 7 +#define PF1550_CHG_OFF_INV 8 +#define PF1550_CHG_BAT_OVER 9 +#define PF1550_CHG_OFF_TEMP 10 +#define PF1550_CHG_LINEAR_ONLY 12 +#define PF1550_CHG_SNS_MASK 0xf + +#define PF1550_BAT_NO_VBUS 0 +#define PF1550_BAT_LOW_THAN_PRECHARG 1 +#define PF1550_BAT_CHARG_FAIL 2 +#define PF1550_BAT_HIGH_THAN_PRECHARG 4 +#define PF1550_BAT_OVER_VOL 5 +#define PF1550_BAT_NO_DETECT 6 +#define PF1550_BAT_SNS_MASK 0x7 + +#define PF1550_VBUS_UVLO BIT(2) +#define PF1550_VBUS_IN2SYS BIT(3) +#define PF1550_VBUS_OVLO BIT(4) +#define PF1550_VBUS_VALID BIT(5) + +#define PF1550_CHARG_REG_BATT_REG_CHGCV_MASK 0x3f +#define PF1550_CHARG_REG_BATT_REG_VMINSYS_SHIFT 6 +#define PF1550_CHARG_REG_BATT_REG_VMINSYS_MASK (0x3 << 6) +#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_SHIFT 2 +#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_MASK (0x3 << 2) + +#define PMIC_IRQ_SW1_LS BIT(0) +#define PMIC_IRQ_SW2_LS BIT(1) +#define PMIC_IRQ_SW3_LS BIT(2) +#define PMIC_IRQ_SW1_HS BIT(0) +#define PMIC_IRQ_SW2_HS BIT(1) +#define PMIC_IRQ_SW3_HS BIT(2) +#define PMIC_IRQ_LDO1_FAULT BIT(0) +#define PMIC_IRQ_LDO2_FAULT BIT(1) +#define PMIC_IRQ_LDO3_FAULT BIT(2) +#define PMIC_IRQ_TEMP_110 BIT(0) +#define PMIC_IRQ_TEMP_125 BIT(1) + +#define ONKEY_IRQ_PUSHI BIT(0) +#define ONKEY_IRQ_1SI BIT(1) +#define ONKEY_IRQ_2SI BIT(2) +#define ONKEY_IRQ_3SI BIT(3) +#define ONKEY_IRQ_4SI BIT(4) +#define ONKEY_IRQ_8SI BIT(5) + +#define CHARG_IRQ_BAT2SOCI BIT(1) +#define CHARG_IRQ_BATI BIT(2) +#define CHARG_IRQ_CHGI BIT(3) +#define CHARG_IRQ_VBUSI BIT(5) +#define CHARG_IRQ_DPMI BIT(6) +#define CHARG_IRQ_THMI BIT(7) + +enum pf1550_pmic_irq { + PF1550_PMIC_IRQ_SW1_LS, + PF1550_PMIC_IRQ_SW2_LS, + PF1550_PMIC_IRQ_SW3_LS, + PF1550_PMIC_IRQ_SW1_HS, + PF1550_PMIC_IRQ_SW2_HS, + PF1550_PMIC_IRQ_SW3_HS, + PF1550_PMIC_IRQ_LDO1_FAULT, + PF1550_PMIC_IRQ_LDO2_FAULT, + PF1550_PMIC_IRQ_LDO3_FAULT, + PF1550_PMIC_IRQ_TEMP_110, + PF1550_PMIC_IRQ_TEMP_125, +}; + +enum pf1550_onkey_irq { + PF1550_ONKEY_IRQ_PUSHI, + PF1550_ONKEY_IRQ_1SI, + PF1550_ONKEY_IRQ_2SI, + PF1550_ONKEY_IRQ_3SI, + PF1550_ONKEY_IRQ_4SI, + PF1550_ONKEY_IRQ_8SI, +}; + +enum pf1550_charg_irq { + PF1550_CHARG_IRQ_BAT2SOCI, + PF1550_CHARG_IRQ_BATI, + PF1550_CHARG_IRQ_CHGI, + PF1550_CHARG_IRQ_VBUSI, + PF1550_CHARG_IRQ_THMI, +}; + +enum pf1550_regulators { + PF1550_SW1, + PF1550_SW2, + PF1550_SW3, + PF1550_VREFDDR, + PF1550_LDO1, + PF1550_LDO2, + PF1550_LDO3, +}; + +struct pf1550_irq_info { + unsigned int irq; + const char *name; + unsigned int virq; +}; + +struct pf1550_dev { + struct device *dev; + struct i2c_client *i2c; + int type; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data_regulator; + struct regmap_irq_chip_data *irq_data_onkey; + struct regmap_irq_chip_data *irq_data_charger; + int irq; +}; + +int pf1550_read_otp(struct pf1550_dev *pf1550, unsigned int index, + unsigned int *val); + +#endif /* __LINUX_MFD_PF1550_H */ diff --git a/include/linux/mfd/si476x-core.h b/include/linux/mfd/si476x-core.h index 674b45d5a757..78a2b2c936f3 100644 --- a/include/linux/mfd/si476x-core.h +++ b/include/linux/mfd/si476x-core.h @@ -493,6 +493,8 @@ enum si476x_common_receiver_properties { SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202, SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT = 0x0203, + SI476X_PROP_AUDIO_MUTE = 0x0301, + SI476X_PROP_SEEK_BAND_BOTTOM = 0x1100, SI476X_PROP_SEEK_BAND_TOP = 0x1101, SI476X_PROP_SEEK_FREQUENCY_SPACING = 0x1102, diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c8e0164c5423..29f225235782 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -101,6 +101,7 @@ #define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26) #define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25) #define IMX6Q_GPR1_DPI_OFF BIT(24) +#define IMX6Q_GPR1_PCIE_SW_PERST BIT(23) #define IMX6Q_GPR1_EXC_MON_MASK BIT(22) #define IMX6Q_GPR1_EXC_MON_OKAY 0x0 #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) @@ -243,6 +244,23 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) +#define IMX6Q_GPR5_PRE_PRG_SEL0_MASK (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_SHIFT 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_MSB 13 +#define IMX6Q_GPR5_PRE_PRG_SEL0_LSB 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN1 (0x0 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN2 (0x1 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN1 (0x2 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN2 (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL1_MASK (0x3 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_SHIFT 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_MSB 15 +#define IMX6Q_GPR5_PRE_PRG_SEL1_LSB 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN1 (0x0 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN2 (0x1 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN1 (0x2 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN2 (0x3 << 14) #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) @@ -286,23 +304,25 @@ #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x0 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0 (0x1 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1 (0x2 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI (0x3 << 2) #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0 (0x1 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1 (0x2 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI (0x3 << 0) #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) +#define IMX6Q_GPR12_PCIE_PM_TURN_OFF BIT(16) #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) +#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) @@ -411,6 +431,15 @@ #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3) #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4) +#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK (0x1 << 26) +#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT (26) +#define IMX6SX_GPR2_MQS_EN_MASK (0x1 << 25) +#define IMX6SX_GPR2_MQS_EN_SHIFT (25) +#define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24) +#define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24) +#define IMX6SX_GPR2_MQS_CLK_DIV_MASK (0xFF << 16) +#define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT (16) + #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) @@ -423,6 +452,7 @@ #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26) #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26) #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26) +#define IMX6SX_GPR5_PCIE_PERST BIT(18) #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19) #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) @@ -437,10 +467,21 @@ #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30) #define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0) #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) +/* For imx6dl iomux gpr register field definitions */ +#define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF (0x2 << 8) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF (0x2 << 6) + /* For imx6ul iomux gpr register field define */ #define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) #define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) diff --git a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h index abbd52466573..af33fcb13339 100644 --- a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h @@ -34,6 +34,8 @@ #define IOMUXC_GPR22 0x58 /* For imx7d iomux gpr register field define */ +#define IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (0x3 << 7) + #define IMX7D_GPR1_IRQ_MASK (0x1 << 12) #define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13) #define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14) diff --git a/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file mode 100644 index 000000000000..cfb857774cf5 --- /dev/null +++ b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_IMX8MQ_IOMUXC_GPR_H +#define __LINUX_IMX8MQ_IOMUXC_GPR_H + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c +#define IOMUXC_GPR8 0x20 +#define IOMUXC_GPR9 0x24 +#define IOMUXC_GPR10 0x28 +#define IOMUXC_GPR11 0x2c +#define IOMUXC_GPR12 0x30 +#define IOMUXC_GPR13 0x34 +#define IOMUXC_GPR14 0x38 +#define IOMUXC_GPR15 0x3c +#define IOMUXC_GPR16 0x40 +#define IOMUXC_GPR17 0x44 +#define IOMUXC_GPR18 0x48 +#define IOMUXC_GPR19 0x4c +#define IOMUXC_GPR20 0x50 +#define IOMUXC_GPR21 0x54 +#define IOMUXC_GPR22 0x58 +#define IOMUXC_GPR23 0x5c +#define IOMUXC_GPR24 0x60 +#define IOMUXC_GPR25 0x64 +#define IOMUXC_GPR26 0x68 +#define IOMUXC_GPR27 0x6c +#define IOMUXC_GPR28 0x70 +#define IOMUXC_GPR29 0x74 +#define IOMUXC_GPR30 0x78 +#define IOMUXC_GPR31 0x7c +#define IOMUXC_GPR32 0x80 +#define IOMUXC_GPR33 0x84 +#define IOMUXC_GPR34 0x88 +#define IOMUXC_GPR35 0x8c +#define IOMUXC_GPR36 0x90 +#define IOMUXC_GPR37 0x94 +#define IOMUXC_GPR38 0x98 +#define IOMUXC_GPR39 0x9c +#define IOMUXC_GPR40 0xa0 +#define IOMUXC_GPR41 0xa4 +#define IOMUXC_GPR42 0xa8 +#define IOMUXC_GPR43 0xac +#define IOMUXC_GPR44 0xb0 +#define IOMUXC_GPR45 0xb4 +#define IOMUXC_GPR46 0xb8 +#define IOMUXC_GPR47 0xbc + +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2) + +#endif /* __LINUX_IMX8MQ_IOMUXC_GPR_H */ diff --git a/include/linux/mipi_csi2.h b/include/linux/mipi_csi2.h new file mode 100644 index 000000000000..7dc76fd293f8 --- /dev/null +++ b/include/linux/mipi_csi2.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_CSI2_H +#define __INCLUDE_MIPI_CSI2_H + +/* MIPI CSI2 registers */ +#define MIPI_CSI2_REG(offset) (offset) + +#define MIPI_CSI2_VERSION MIPI_CSI2_REG(0x000) +#define MIPI_CSI2_N_LANES MIPI_CSI2_REG(0x004) +#define MIPI_CSI2_PHY_SHUTDOWNZ MIPI_CSI2_REG(0x008) +#define MIPI_CSI2_DPHY_RSTZ MIPI_CSI2_REG(0x00c) +#define MIPI_CSI2_CSI2_RESETN MIPI_CSI2_REG(0x010) +#define MIPI_CSI2_PHY_STATE MIPI_CSI2_REG(0x014) +#define MIPI_CSI2_DATA_IDS_1 MIPI_CSI2_REG(0x018) +#define MIPI_CSI2_DATA_IDS_2 MIPI_CSI2_REG(0x01c) +#define MIPI_CSI2_ERR1 MIPI_CSI2_REG(0x020) +#define MIPI_CSI2_ERR2 MIPI_CSI2_REG(0x024) +#define MIPI_CSI2_MASK1 MIPI_CSI2_REG(0x028) +#define MIPI_CSI2_MASK2 MIPI_CSI2_REG(0x02c) +#define MIPI_CSI2_PHY_TST_CTRL0 MIPI_CSI2_REG(0x030) +#define MIPI_CSI2_PHY_TST_CTRL1 MIPI_CSI2_REG(0x034) +#define MIPI_CSI2_SFT_RESET MIPI_CSI2_REG(0xf00) + +/* mipi data type */ +#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */ +#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */ +#define MIPI_DT_YUV422 0x1e /* UYVY... */ +#define MIPI_DT_RGB444 0x20 +#define MIPI_DT_RGB555 0x21 +#define MIPI_DT_RGB565 0x22 +#define MIPI_DT_RGB666 0x23 +#define MIPI_DT_RGB888 0x24 +#define MIPI_DT_RAW6 0x28 +#define MIPI_DT_RAW7 0x29 +#define MIPI_DT_RAW8 0x2a +#define MIPI_DT_RAW10 0x2b +#define MIPI_DT_RAW12 0x2c +#define MIPI_DT_RAW14 0x2d + + +struct mipi_csi2_info; +/* mipi csi2 API */ +struct mipi_csi2_info *mipi_csi2_get_info(void); + +bool mipi_csi2_enable(struct mipi_csi2_info *info); + +bool mipi_csi2_disable(struct mipi_csi2_info *info); + +bool mipi_csi2_get_status(struct mipi_csi2_info *info); + +int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info, + unsigned int datatype); + +unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info); + +int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info); + +void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info); + +int mipi_csi2_reset(struct mipi_csi2_info *info); + +#endif diff --git a/include/linux/mipi_dsi.h b/include/linux/mipi_dsi.h new file mode 100644 index 000000000000..dbc249a38f68 --- /dev/null +++ b/include/linux/mipi_dsi.h @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_MIPI_DSI_H +#define __INCLUDE_MIPI_DSI_H + +#define MIPI_DSI_VERSION (0x000) +#define MIPI_DSI_PWR_UP (0x004) +#define MIPI_DSI_CLKMGR_CFG (0x008) +#define MIPI_DSI_DPI_CFG (0x00c) +#define MIPI_DSI_DBI_CFG (0x010) +#define MIPI_DSI_DBIS_CMDSIZE (0x014) +#define MIPI_DSI_PCKHDL_CFG (0x018) +#define MIPI_DSI_VID_MODE_CFG (0x01c) +#define MIPI_DSI_VID_PKT_CFG (0x020) +#define MIPI_DSI_CMD_MODE_CFG (0x024) +#define MIPI_DSI_TMR_LINE_CFG (0x028) +#define MIPI_DSI_VTIMING_CFG (0x02c) +#define MIPI_DSI_PHY_TMR_CFG (0x030) +#define MIPI_DSI_GEN_HDR (0x034) +#define MIPI_DSI_GEN_PLD_DATA (0x038) +#define MIPI_DSI_CMD_PKT_STATUS (0x03c) +#define MIPI_DSI_TO_CNT_CFG (0x040) +#define MIPI_DSI_ERROR_ST0 (0x044) +#define MIPI_DSI_ERROR_ST1 (0x048) +#define MIPI_DSI_ERROR_MSK0 (0x04c) +#define MIPI_DSI_ERROR_MSK1 (0x050) +#define MIPI_DSI_PHY_RSTZ (0x054) +#define MIPI_DSI_PHY_IF_CFG (0x058) +#define MIPI_DSI_PHY_IF_CTRL (0x05c) +#define MIPI_DSI_PHY_STATUS (0x060) +#define MIPI_DSI_PHY_TST_CTRL0 (0x064) +#define MIPI_DSI_PHY_TST_CTRL1 (0x068) + +#define DSI_PWRUP_RESET (0x0 << 0) +#define DSI_PWRUP_POWERUP (0x1 << 0) + +#define DSI_DPI_CFG_VID_SHIFT (0) +#define DSI_DPI_CFG_VID_MASK (0x3) +#define DSI_DPI_CFG_COLORCODE_SHIFT (2) +#define DSI_DPI_CFG_COLORCODE_MASK (0x7) +#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5) +#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5) +#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6) +#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6) +#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7) +#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7) +#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8) +#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8) +#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9) +#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9) +#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10) + +#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0) +#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1) +#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2) +#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3) +#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4) +#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3) +#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5) + +#define DSI_VID_MODE_CFG_EN (0x1 << 0) +#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1) +#define DSI_VID_MODE_CFG_TYPE_MASK (0x3) +#define DSI_VID_MODE_CFG_TYPE_SHIFT (1) +#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3) +#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4) +#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5) +#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6) +#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7) +#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8) +#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9) +#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10) +#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11) +#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \ + DSI_VID_MODE_CFG_EN_LP_VBP | \ + DSI_VID_MODE_CFG_EN_LP_VFP | \ + DSI_VID_MODE_CFG_EN_LP_HFP | \ + DSI_VID_MODE_CFG_EN_LP_HBP | \ + DSI_VID_MODE_CFG_EN_LP_VACT) + + + +#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff) +#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21) + +#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF) +#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0) + +#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0) +#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9) +#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff) +#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18) + +#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf) +#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0) +#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4) +#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10) +#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff) +#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16) + +#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff) +#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20) + +#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3) +#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0) +#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff) +#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2) + +#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2) +#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1) +#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0) +#define DSI_PHY_RSTZ_RST (0x0) + +#define DSI_PHY_STATUS_LOCK (0x1 << 0) +#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2) + +#define DSI_GEN_HDR_TYPE_MASK (0xff) +#define DSI_GEN_HDR_TYPE_SHIFT (0) +#define DSI_GEN_HDR_DATA_MASK (0xffff) +#define DSI_GEN_HDR_DATA_SHIFT (8) + +#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0) +#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3) +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4) +#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6) + +#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff) +#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff) + +#define DSI_PHY_IF_CTRL_RESET (0x0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1) +#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2) +#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3) +#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4) +#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF) +#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5) + +#define DSI_PHY_CLK_INIT_COMMAND (0x44) +#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4) +#endif diff --git a/include/linux/mipi_dsi_northwest.h b/include/linux/mipi_dsi_northwest.h new file mode 100644 index 000000000000..8cb379c85ef5 --- /dev/null +++ b/include/linux/mipi_dsi_northwest.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_DSI_NORTHWEST_H +#define __INCLUDE_MIPI_DSI_NORTHWEST_H + +/* ---------------------------- register offsets --------------------------- */ + +/* sim */ +#define SIM_SOPT1 0x0 +#define MIPI_ISO_DISABLE 0x8 + +#define SIM_SOPT1CFG 0x4 +#define DSI_RST_DPI_N 0x80000000 +#define DSI_RST_ESC_N 0x40000000 +#define DSI_RST_BYTE_N 0x20000000 +#define DSI_SD 0x200 +#define DSI_CM 0x100 +#define DSI_PLL_EN 0x80 + +/* SRC */ +#define SRC_MIPIPHY_RCR 0x28 +#define MIPI_DSI_RESET_BYTE_N 0x2 +#define MIPI_DSI_RESET_N 0x4 +#define MIPI_DSI_DPI_RESET_N 0x8 +#define MIPI_DSI_ESC_RESET_N 0x10 +#define MIPI_DSI_PCLK_RESET_N 0x20 + +/* GPR */ +#define IOMUXC_GPR_GPR13 0x34 +#define GPR_MIPI_MUX_SEL 0x4 + +/* dphy */ +#define DPHY_PD_DPHY 0x300 +#define DPHY_M_PRG_HS_PREPARE 0x304 +#define DPHY_MC_PRG_HS_PREPARE 0x308 +#define DPHY_M_PRG_HS_ZERO 0x30c +#define DPHY_MC_PRG_HS_ZERO 0x310 +#define DPHY_M_PRG_HS_TRAIL 0x314 +#define DPHY_MC_PRG_HS_TRAIL 0x318 +#define DPHY_PD_PLL 0x31c +#define DPHY_TST 0x320 +#define DPHY_CN 0x324 +#define DPHY_CM 0x328 +#define DPHY_CO 0x32c +#define DPHY_LOCK 0x330 +#define DPHY_LOCK_BYP 0x334 +#define DPHY_RTERM_SEL 0x338 +#define DPHY_AUTO_PD_EN 0x33c +#define DPHY_RXLPRP 0x340 +#define DPHY_RXCDRP 0x344 + +/* host */ +#define HOST_CFG_NUM_LANES 0x0 +#define HOST_CFG_NONCONTINUOUS_CLK 0x4 +#define HOST_CFG_T_PRE 0x8 +#define HOST_CFG_T_POST 0xc +#define HOST_CFG_TX_GAP 0x10 +#define HOST_CFG_AUTOINSERT_EOTP 0x14 +#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 +#define HOST_CFG_HTX_TO_COUNT 0x1c +#define HOST_CFG_LRX_H_TO_COUNT 0x20 +#define HOST_CFG_BTA_H_TO_COUNT 0x24 +#define HOST_CFG_TWAKEUP 0x28 +#define HOST_CFG_STATUS_OUT 0x2c +#define HOST_RX_ERROR_STATUS 0x30 + +/* dpi */ +#define DPI_PIXEL_PAYLOAD_SIZE 0x200 +#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204 +#define DPI_INTERFACE_COLOR_CODING 0x208 +#define DPI_PIXEL_FORMAT 0x20c +#define DPI_VSYNC_POLARITY 0x210 +#define DPI_HSYNC_POLARITY 0x214 +#define DPI_VIDEO_MODE 0x218 +#define DPI_HFP 0x21c +#define DPI_HBP 0x220 +#define DPI_HSA 0x224 +#define DPI_ENABLE_MULT_PKTS 0x228 +#define DPI_VBP 0x22c +#define DPI_VFP 0x230 +#define DPI_BLLP_MODE 0x234 +#define DPI_USE_NULL_PKT_BLLP 0x238 +#define DPI_VACTIVE 0x23c +#define DPI_VC 0x240 + +/* apb pkt */ +#define HOST_TX_PAYLOAD 0x280 + +#define HOST_PKT_CONTROL 0x284 +#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16) +#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18) +#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24) +#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25) +#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26) + +#define HOST_SEND_PACKET 0x288 +#define HOST_PKT_STATUS 0x28c +#define HOST_PKT_FIFO_WR_LEVEL 0x290 +#define HOST_PKT_FIFO_RD_LEVEL 0x294 +#define HOST_PKT_RX_PAYLOAD 0x298 + +#define HOST_PKT_RX_PKT_HEADER 0x29c +#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16) +#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22) + +#define HOST_IRQ_STATUS 0x2a0 +#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0) +#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1) +#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2) +#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3) +#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4) +#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5) +#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6) +#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7) +#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8) +#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29) +#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30) +#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31) + +#define HOST_IRQ_STATUS2 0x2a4 +#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0) +#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1) +#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2) + +#define HOST_IRQ_MASK 0x2a8 +#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0) +#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1) +#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2) +#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3) +#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4) +#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5) +#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6) +#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7) +#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8) +#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29) +#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30) +#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31) + +#define HOST_IRQ_MASK2 0x2ac +#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0) +#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1) +#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2) + +/* ------------------------------------- end -------------------------------- */ + +#endif diff --git a/include/linux/mipi_dsi_samsung.h b/include/linux/mipi_dsi_samsung.h new file mode 100644 index 000000000000..e58da9541cfb --- /dev/null +++ b/include/linux/mipi_dsi_samsung.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_DSI_SAMSUNG_H +#define __INCLUDE_MIPI_DSI_SAMSUNG_H + +#define MIPI_DSI_VERSION (0x000) +#define MIPI_DSI_STATUS (0x004) +#define MIPI_DSI_RGB_STATUS (0x008) +#define MIPI_DSI_SWRST (0x00c) +#define MIPI_DSI_CLKCTRL (0x010) +#define MIPI_DSI_TIMEOUT (0x014) +#define MIPI_DSI_CONFIG (0x018) +#define MIPI_DSI_ESCMODE (0x01c) +#define MIPI_DSI_MDRESOL (0x020) +#define MIPI_DSI_MVPORCH (0x024) +#define MIPI_DSI_MHPORCH (0x028) +#define MIPI_DSI_MSYNC (0x02c) +#define MIPI_DSI_SDRESOL (0x030) +#define MIPI_DSI_INTSRC (0x034) +#define MIPI_DSI_INTMSK (0x038) +#define MIPI_DSI_PKTHDR (0x03c) +#define MIPI_DSI_PAYLOAD (0x040) +#define MIPI_DSI_RXFIFO (0x044) +#define MIPI_DSI_FIFOTHLD (0x048) +#define MIPI_DSI_FIFOCTRL (0x04c) +#define MIPI_DSI_MEMACCHR (0x050) +#define MIPI_DSI_MULTI_PKT (0x078) +#define MIPI_DSI_PLLCTRL_1G (0x090) +#define MIPI_DSI_PLLCTRL (0x094) +#define MIPI_DSI_PLLCTRL1 (0x098) +#define MIPI_DSI_PLLCTRL2 (0x09c) +#define MIPI_DSI_PLLTMR (0x0a0) +#define MIPI_DSI_PHYCTRL_B1 (0x0a4) +#define MIPI_DSI_PHYCTRL_B2 (0x0a8) +#define MIPI_DSI_PHYCTRL_M1 (0x0a8) +#define MIPI_DSI_PHYCTRL_M2 (0x0ac) +#define MIPI_DSI_PHYTIMING (0x0b4) +#define MIPI_DSI_PHYTIMING1 (0x0b8) +#define MIPI_DSI_PHYTIMING2 (0x0bc) + +#define MIPI_DSI_SWRST_SWRST (0x1 << 0) +#define MIPI_DSI_SWRST_FUNCRST (0x1 << 16) +#define MIPI_DSI_MAIN_HRESOL(x) (((x) & 0x7ff) << 0) +#define MIPI_DSI_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) +#define MIPI_DSI_MAIN_STANDBY(x) (((x) & 0x1) << 31) +#define MIPI_DSI_MAIN_VBP(x) (((x) & 0x7ff) << 0) +#define MIPI_DSI_STABLE_VFP(x) (((x) & 0x7ff) << 16) +#define MIPI_DSI_CMDALLOW(x) (((x) & 0xf) << 28) +#define MIPI_DSI_MAIN_HBP(x) (((x) & 0xffff) << 0) +#define MIPI_DSI_MAIN_HFP(x) (((x) & 0xffff) << 16) +#define MIPI_DSI_MAIN_VSA(x) (((x) & 0x3ff) << 22) +#define MIPI_DSI_MAIN_HSA(x) (((x) & 0xffff) << 0) + +#define MIPI_DSI_LANE_EN(x) (((x) & 0x1f) << 0) +#define MIPI_DSI_NUM_OF_DATALANE(x) (((x) & 0x3) << 5) +#define MIPI_DSI_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) +#define MIPI_DSI_MAIN_PIX_FORMAT(x) (((x) & 0x7) << 12) +#define MIPI_DSI_SUB_VC(x) (((x) & 0x3) << 16) +#define MIPI_DSI_MAIN_VC(x) (((x) & 0x3) << 18) +#define MIPI_DSI_HSA_DISABLE_MODE(x) (((x) & 0x1) << 20) +#define MIPI_DSI_HBP_DISABLE_MODE(x) (((x) & 0x1) << 21) +#define MIPI_DSI_HFP_DISABLE_MODE(x) (((x) & 0x1) << 22) +#define MIPI_DSI_HSE_DISABLE_MODE(x) (((x) & 0x1) << 23) +#define MIPI_DSI_AUTO_MODE(x) (((x) & 0x1) << 24) +#define MIPI_DSI_VIDEO_MODE(x) (((x) & 0x1) << 25) +#define MIPI_DSI_BURST_MODE(x) (((x) & 0x1) << 26) +#define MIPI_DSI_SYNC_IN_FORM(x) (((x) & 0x1) << 27) +#define MIPI_DSI_EOT_R03(x) (((x) & 0x1) << 28) +#define MIPI_DSI_MFLUSH_VS(x) (((x) & 0x1) << 29) + +#define MIPI_DSI_DP_DN_SWAP_DATA (0x1 << 24) +#define MIPI_DSI_PLL_EN(x) (((x) & 0x1) << 23) +#define MIPI_DSI_PMS(x) (((x) & 0x7ffff) << 1) + +#define MIPI_DSI_TX_REQUEST_HSCLK(x) (((x) & 0x1) << 31) +#define MIPI_DSI_DPHY_SEL(x) (((x) & 0x1) << 29) +#define MIPI_DSI_ESC_CLK_EN(x) (((x) & 0x1) << 28) +#define MIPI_DSI_PLL_BYPASS(x) (((x) & 0x1) << 27) +#define MIPI_DSI_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) +#define MIPI_DSI_BYTE_CLK_EN(x) (((x) & 0x1) << 24) +#define MIPI_DSI_LANE_ESC_CLK_EN(x) (((x) & 0x1f) << 19) + +#define MIPI_DSI_FORCE_STOP_STATE(x) (((x) & 0x1) << 20) + +#define MIPI_DSI_M_TLPXCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_THSEXITCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_M_TCLKPRPRCTL(x) (((x) & 0xff) << 24) +#define MIPI_DSI_M_TCLKZEROCTL(x) (((x) & 0xff) << 16) +#define MIPI_DSI_M_TCLKPOSTCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_TCLKTRAILCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_M_THSPRPRCTL(x) (((x) & 0xff) << 16) +#define MIPI_DSI_M_THSZEROCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_THSTRAILCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_PLL_STABLE(x) (((x) & 0x1) << 31) +#define MIPI_DSI_TX_READY_HS_CLK(x) (((x) & 0x1) << 10) +#define MIPI_DSI_ULPS_CLK(x) (((x) & 0x1) << 9) +#define MIPI_DSI_STOP_STATE_CLK(x) (((x) & 0x1) << 8) +#define MIPI_DSI_ULPS_DAT(x) (((x) & 0xf) << 4) +#define MIPI_DSI_STOP_STATE_DAT(x) (((x) & 0xf) << 0) + +#define INTSRC_SFR_PL_FIFO_EMPTY (0x1 << 29) +#define INTSRC_SFR_PH_FIFO_EMPTY (0x1 << 28) +#define INTSRC_RX_DATA_DONE (0x1 << 18) +#define INTMSK_SFR_PL_FIFO_EMPTY (0x1 << 29) +#define INTMSK_SFR_PH_FIFO_EMPTY (0x1 << 28) +#define INTMSK_RX_DATA_DONE (0x1 << 18) + +#define MIPI_DSI_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) +#define MIPI_DSI_CMD_LPDT (0x1 << 7) +#define MIPI_DSI_TX_LPDT (0x1 << 6) + +#endif diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 9a43763a68ad..e315691e1ce1 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -255,6 +255,10 @@ struct mmc_supply { struct regulator *vqmmc; /* Optional Vccq supply */ }; +struct mmc_ctx { + struct task_struct *task; +}; + struct mmc_host { struct device *parent; struct device class_dev; @@ -349,6 +353,8 @@ struct mmc_host { #define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ #define MMC_CAP2_CQE (1 << 23) /* Has eMMC command queue engine */ #define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */ +#define MMC_CAP2_CD_POST (1 << 25) /* post card rescan, let client driver to start */ +#define MMC_CAP2_DDR52_3_3V (1 << 26) /* Only supprot eMMC DDR52 at 3.3v */ mmc_pm_flag_t pm_caps; /* supported pm features */ @@ -374,6 +380,7 @@ struct mmc_host { unsigned int doing_retune:1; /* re-tuning in progress */ unsigned int retune_now:1; /* do re-tuning at next req */ unsigned int retune_paused:1; /* re-tuning is temporarily disabled */ + unsigned int use_blk_mq:1; /* use blk-mq */ int rescan_disable; /* disable card detection */ int rescan_entered; /* used with nonremovable devices */ @@ -388,8 +395,9 @@ struct mmc_host { struct mmc_card *card; /* device attached to this host */ wait_queue_head_t wq; - struct task_struct *claimer; /* task that has host claimed */ + struct mmc_ctx *claimer; /* context that has host claimed */ int claim_cnt; /* "claim" nesting count */ + struct mmc_ctx default_ctx; /* default context */ struct delayed_work detect; int detect_change; /* card detect flag */ @@ -469,6 +477,8 @@ void mmc_detect_change(struct mmc_host *, unsigned long delay); void mmc_request_done(struct mmc_host *, struct mmc_request *); void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq); +void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq); + static inline void mmc_signal_sdio_irq(struct mmc_host *host) { host->ops->enable_sdio_irq(host, 0); diff --git a/include/linux/mmc/pm.h b/include/linux/mmc/pm.h index 4a139204c20c..6e2d6a135c7e 100644 --- a/include/linux/mmc/pm.h +++ b/include/linux/mmc/pm.h @@ -26,5 +26,6 @@ typedef unsigned int mmc_pm_flag_t; #define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */ #define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */ +#define MMC_PM_IGNORE_PM_NOTIFY (1 << 2) /* ignore mmc pm notify */ #endif /* LINUX_MMC_PM_H */ diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 17446d3c3602..bbb9c0010cce 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -12,6 +12,8 @@ #ifndef LINUX_MMC_SDIO_H #define LINUX_MMC_SDIO_H +#include <linux/mmc/host.h> + /* SDIO commands type argument response */ #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */ #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */ @@ -190,4 +192,6 @@ #define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */ +void mmc_sdio_force_remove(struct mmc_host *host); + #endif /* LINUX_MMC_SDIO_H */ diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h index 68bbbd9edc08..93fa5513ef5a 100644 --- a/include/linux/mmc/sdio_ids.h +++ b/include/linux/mmc/sdio_ids.h @@ -36,12 +36,14 @@ #define SDIO_DEVICE_ID_BROADCOM_4339 0x4339 #define SDIO_DEVICE_ID_BROADCOM_43362 0xa962 #define SDIO_DEVICE_ID_BROADCOM_43364 0xa9a4 +#define SDIO_DEVICE_ID_BROADCOM_43428 0xa9a4 #define SDIO_DEVICE_ID_BROADCOM_43430 0xa9a6 #define SDIO_DEVICE_ID_BROADCOM_4345 0x4345 #define SDIO_DEVICE_ID_BROADCOM_43455 0xa9bf #define SDIO_DEVICE_ID_BROADCOM_4354 0x4354 #define SDIO_DEVICE_ID_BROADCOM_4356 0x4356 #define SDIO_DEVICE_ID_CYPRESS_4373 0x4373 +#define SDIO_DEVICE_ID_CYPRESS_43012 43012 #define SDIO_VENDOR_ID_INTEL 0x0089 #define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402 diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 9b57a9b1b081..626beeb63d37 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -233,6 +233,11 @@ struct cfi_pri_amdstd { uint8_t VppMin; uint8_t VppMax; uint8_t TopBottom; + /* Below field are added from version 1.5 */ + uint8_t ProgramSuspend; + uint8_t UnlockBypass; + uint8_t SecureSiliconSector; + uint8_t SoftwareFeatures; } __packed; /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */ @@ -377,6 +382,7 @@ struct cfi_fixup { #define CFI_MFR_SHARP 0x00B0 #define CFI_MFR_SST 0x00BF #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ +#define CFI_MFR_MICRON 0x002C #define CFI_MFR_TOSHIBA 0x0098 #define CFI_MFR_WINBOND 0x00DA diff --git a/include/linux/mtd/hyperbus.h b/include/linux/mtd/hyperbus.h new file mode 100644 index 000000000000..28087fcf609d --- /dev/null +++ b/include/linux/mtd/hyperbus.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __LINUX_MTD_HYPERBUS_H__ +#define __LINUX_MTD_HYPERBUS_H__ + +#include <linux/mtd/map.h> + +enum hyperbus_memtype { + HYPERFLASH, + HYPERRAM, +}; + +/** + * struct hyperbus_device - struct representing HyperBus slave device + * @map: map_info struct for accessing MMIO HyperBus flash memory + * @np: pointer to HyperBus slave device node + * @mtd: pointer to MTD struct + * @ctlr: pointer to HyperBus controller struct + * @memtype: type of memory device: HyperFlash or HyperRAM + * @registered: flag to indicate whether device is registered with MTD core + */ + +struct hyperbus_device { + struct map_info map; + struct device_node *np; + struct mtd_info *mtd; + struct hyperbus_ctlr *ctlr; + enum hyperbus_memtype memtype; + bool registered; +}; + +/** + * struct hyperbus_ops - struct representing custom HyperBus operations + * @read16: read 16 bit of data, usually from register/ID-CFI space + * @write16: write 16 bit of data, usually to register/ID-CFI space + * @copy_from: copy data from flash memory + * @copy_to: copy data to flash memory + * @calibrate: calibrate HyperBus controller + * @prepare: preparation for ops + * @unprepare: post work after ops + */ + +struct hyperbus_ops { + u16 (*read16)(struct hyperbus_device *hbdev, unsigned long addr); + void (*write16)(struct hyperbus_device *hbdev, + unsigned long addr, u16 val); + void (*copy_from)(struct hyperbus_device *hbdev, void *to, + unsigned long from, ssize_t len); + void (*copy_to)(struct hyperbus_device *dev, unsigned long to, + const void *from, ssize_t len); + int (*calibrate)(struct hyperbus_device *dev); + int (*prepare)(struct hyperbus_device *dev); + void (*unprepare)(struct hyperbus_device *dev); +}; + +/** + * struct hyperbus_ctlr - struct representing HyperBus controller + * @calibrated: flag to indicate ctlr calibration sequence is complete + * @ops: HyperBus controller ops + */ +struct hyperbus_ctlr { + struct device *dev; + bool calibrated; + + const struct hyperbus_ops *ops; +}; + +/** + * hyperbus_calibrate - default calibration routine for use by HyperBus ctlr. + * @hbdev: hyperbus_device to be used for calibration + * + * Return: 0 for success, others for failure. + */ +int hyperbus_calibrate(struct hyperbus_device *hbdev); + +/** + * hyperbus_register_device - probe and register a HyperBus slave memory device + * @hbdev: hyperbus_device struct with dev, np and ctlr field populated + * + * Return: 0 for success, others for failure. + */ +int hyperbus_register_device(struct hyperbus_device *hbdev); + +/** + * hyperbus_unregister_device - deregister HyperBus slave memory device + * @hbdev: hyperbus_device to be unregistered + * + * Return: 0 for success, others for failure. + */ +int hyperbus_unregister_device(struct hyperbus_device *hbdev); + +#endif /* __LINUX_MTD_HYPERBUS_H__ */ diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index 01b990e4b228..9a397595b68c 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h @@ -446,7 +446,7 @@ static inline void inline_map_copy_from(struct map_info *map, void *to, unsigned if (map->cached) memcpy(to, (char *)map->cached + from, len); else - memcpy_fromio(to, map->virt + from, len); + memcpy(to, map->virt + from, len); } static inline void inline_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 1f0a7fc7772f..9c9401c7e1a5 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,6 +24,7 @@ #define SNOR_MFR_GIGADEVICE 0xc8 #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ +#define SNOR_MFR_MICRONO CFI_MFR_MICRON /* Original Micron */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST @@ -69,6 +70,7 @@ #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ +#define SPINOR_OP_READ_1_4_4_D_4B 0xee /* Read data bytes (DDR Quad SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ @@ -79,11 +81,13 @@ /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ #define SPINOR_OP_READ_1_1_1_DTR 0x0d #define SPINOR_OP_READ_1_2_2_DTR 0xbd +#define SPINOR_OP_READ_1_1_4_DTR 0x6d #define SPINOR_OP_READ_1_4_4_DTR 0xed #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee +#define SPINOR_OP_READ_1_8_8_DTR_4B 0x9d /* Used for SST flashes only. */ #define SPINOR_OP_BP 0x02 /* Byte program */ @@ -110,6 +114,8 @@ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ +#define SPINOR_OP_RD_VCR 0x85 /* Read VCR register */ +#define SPINOR_OP_WR_VCR 0x81 /* Write VCR register */ /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ diff --git a/include/linux/mx8_mu.h b/include/linux/mx8_mu.h new file mode 100644 index 000000000000..b31e52693db8 --- /dev/null +++ b/include/linux/mx8_mu.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MU_ATR0_OFFSET1 0x0 +#define MU_ARR0_OFFSET1 0x10 +#define MU_ASR_OFFSET1 0x20 +#define MU_ACR_OFFSET1 0x24 + +/* Registers offsets of the MU Version 1.0 */ +#define MU_V10_VER_OFFSET1 0x0 +#define MU_V10_ATR0_OFFSET1 0x20 +#define MU_V10_ARR0_OFFSET1 0x40 +#define MU_V10_ASR_OFFSET1 0x60 +#define MU_V10_ACR_OFFSET1 0x64 +#define MU_VER_ID_V10 0x0100 /* Version 1.0 */ + +#define MU_TR_COUNT1 4 +#define MU_RR_COUNT1 4 + +#define MU_CR_GIEn_MASK1 (0xF << 28) +#define MU_CR_RIEn_MASK1 (0xF << 24) +#define MU_CR_TIEn_MASK1 (0xF << 20) +#define MU_CR_GIRn_MASK1 (0xF << 16) +#define MU_CR_NMI_MASK1 (1 << 3) +#define MU_CR_Fn_MASK1 0x7 + +#define MU_SR_TE0_MASK1 (1 << 23) +#define MU_SR_RF0_MASK1 (1 << 27) +#define MU_CR_RIE0_MASK1 (1 << 27) +#define MU_CR_GIE0_MASK1 (1 << 31) + +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + + +void MU_Init(void __iomem *base); +void MU_SendMessage(void __iomem *base, uint32_t regIndex, uint32_t msg); +void MU_SendMessageTimeout(void __iomem *base, uint32_t regIndex, uint32_t msg, uint32_t t); +void MU_ReceiveMsg(void __iomem *base, uint32_t regIndex, uint32_t *msg); +void MU_EnableGeneralInt(void __iomem *base, uint32_t index); +void MU_EnableRxFullInt(void __iomem *base, uint32_t index); +uint32_t MU_ReadStatus(void __iomem *base); +int32_t MU_SetFn(void __iomem *base, uint32_t Fn); + diff --git a/include/linux/mxc_dcic.h b/include/linux/mxc_dcic.h new file mode 100644 index 000000000000..8e330bd466da --- /dev/null +++ b/include/linux/mxc_dcic.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file linux/mxc_dcic.h + * + * @brief Global header file for the MXC DCIC driver + * + * @ingroup MXC DCIC + */ + +#ifndef __LINUX_DCIC_H__ +#define __LINUX_DCIC_H__ + +#include <uapi/linux/mxc_dcic.h> + +#define DCICC_IC_ENABLE 0x1 +#define DCICC_IC_DISABLE 0x0 +#define DCICC_IC_MASK 0x1 +#define DCICC_DE_ACTIVE_HIGH 0 +#define DCICC_DE_ACTIVE_LOW (0x1 << 4) +#define DCICC_DE_ACTIVE_MASK (0x1 << 4) +#define DCICC_HSYNC_POL_ACTIVE_HIGH 0 +#define DCICC_HSYNC_POL_ACTIVE_LOW (0x1 << 5) +#define DCICC_HSYNC_POL_ACTIVE_MASK (0x1 << 5) +#define DCICC_VSYNC_POL_ACTIVE_HIGH 0 +#define DCICC_VSYNC_POL_ACTIVE_LOW (0x1 << 6) +#define DCICC_VSYNC_POL_ACTIVE_MASK (0x1 << 6) +#define DCICC_CLK_POL_NO_INVERTED 0 +#define DCICC_CLK_POL_INVERTED (0x1 << 7) +#define DCICC_CLK_POL_INVERTED_MASK (0x1 << 7) + +#define DCICIC_ERROR_INT_DISABLE 1 +#define DCICIC_ERROR_INT_ENABLE 0 +#define DCICIC_ERROR_INT_MASK_MASK 1 +#define DCICIC_FUN_INT_DISABLE (0x1 << 1) +#define DCICIC_FUN_INT_ENABLE 0 +#define DCICIC_FUN_INT_MASK (0x1 << 1) +#define DCICIC_FREEZE_MASK_CHANGED 0 +#define DCICIC_FREEZE_MASK_FORZEN (0x1 << 3) +#define DCICIC_FREEZE_MASK_MASK (0x1 << 3) +#define DCICIC_EXT_SIG_EX_DISABLE 0 +#define DCICIC_EXT_SIG_EN_ENABLE (0x1 << 16) +#define DCICIC_EXT_SIG_EN_MASK (0x1 << 16) + +#define DCICS_ROI_MATCH_STAT_MASK 0xFFFF +#define DCICS_EI_STAT_PENDING (0x1 << 16) +#define DCICS_EI_STAT_NO_PENDING 0 +#define DCICS_FI_STAT_PENDING (0x1 << 17) +#define DCICS_FI_STAT_NO_PENDING 0 + +#define DCICRC_ROI_START_OFFSET_X_MASK 0x1FFF +#define DCICRC_ROI_START_OFFSET_X_SHIFT 0 +#define DCICRC_ROI_START_OFFSET_Y_MASK (0xFFF << 16) +#define DCICRC_ROI_START_OFFSET_Y_SHIFT 16 +#define DCICRC_ROI_CHANGED 0 +#define DCICRC_ROI_FROZEN (0x1 << 30) +#define DCICRC_ROI_ENABLE (0x1 << 31) +#define DCICRC_ROI_DISABLE 0 + +#define DCICRS_ROI_END_OFFSET_X_MASK 0x1FFF +#define DCICRS_ROI_END_OFFSET_X_SHIFT 0 +#define DCICRS_ROI_END_OFFSET_Y_MASK (0xFFF << 16) +#define DCICRS_ROI_END_OFFSET_Y_SHIFT 16 + +struct roi_regs { + u32 dcicrc; + u32 dcicrs; + u32 dcicrrs; + u32 dcicrcs; +}; + +struct dcic_regs { + u32 dcicc; + u32 dcicic; + u32 dcics; + u32 dcic_reserved; + struct roi_regs ROI[16]; +}; + +struct dcic_mux { + char dcic[16]; + u32 val; +}; + +struct bus_mux { + char name[16]; + int reg; + int shift; + int mask; + int dcic_mux_num; + const struct dcic_mux *dcics; +}; + +struct dcic_info { + int bus_mux_num; + const struct bus_mux *buses; +}; + +struct dcic_data { + struct regmap *regmap; + struct device *dev; + struct dcic_regs *regs; + const struct bus_mux *buses; + u32 bus_n; + u32 mux_n; + struct clk *disp_axi_clk; + struct clk *dcic_clk; + struct mutex lock; + struct completion roi_crc_comp; + struct class *class; + int major; + struct cdev cdev; /* Char device structure */ + dev_t devt; + unsigned int result; +}; +#endif diff --git a/include/linux/mxc_mlb.h b/include/linux/mxc_mlb.h new file mode 100644 index 000000000000..d7c792a2bee4 --- /dev/null +++ b/include/linux/mxc_mlb.h @@ -0,0 +1,55 @@ +/* + * mxc_mlb.h + * + * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_MLB_H +#define _MXC_MLB_H + +/* define IOCTL command */ +#define MLB_DBG_RUNTIME _IO('S', 0x09) +#define MLB_SET_FPS _IOW('S', 0x10, unsigned int) +#define MLB_GET_VER _IOR('S', 0x11, unsigned long) +#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char) + +/*! + * set channel address for each logical channel + * the MSB 16bits is for tx channel, the left LSB is for rx channel + */ +#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int) +#define MLB_CHAN_STARTUP _IO('S', 0x14) +#define MLB_CHAN_SHUTDOWN _IO('S', 0x15) +#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long) + +#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17) +#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18) +#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int) +#define MLB_IRQ_ENABLE _IO('S', 0x20) +#define MLB_IRQ_DISABLE _IO('S', 0x21) + +/*! + * MLB event define + */ +enum { + MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0, + MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1, + MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8, + MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9, + MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16, + MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17, + MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24, + MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25, +}; + + +#endif /* _MXC_MLB_H */ diff --git a/include/linux/mxc_sim_interface.h b/include/linux/mxc_sim_interface.h new file mode 100644 index 000000000000..5eae53a59075 --- /dev/null +++ b/include/linux/mxc_sim_interface.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef MXC_SIM_INTERFACE_H +#define MXC_SIM_INTERFACE_H + +#define SIM_ATR_LENGTH_MAX 32 + +/* Raw ATR SIM_IOCTL_GET_ATR */ +typedef struct { + unsigned int size;/* length of ATR received */ + unsigned char *atr_buffer;/* raw ATR string received */ + int errval;/* The error vale reported to user space after completing ATR*/ +} sim_atr_t; + +/* ISO7816-3 protocols */ +#define SIM_PROTOCOL_T0 1 +#define SIM_PROTOCOL_T1 2 + +/* Transfer types for SIM_IOCTL_XFER */ +#define SIM_XFER_TYPE_TPDU 1 +#define SIM_XFER_TYPE_PTS 2 + +typedef struct { + unsigned int wwt; + unsigned int cwt; + unsigned int bwt; + unsigned int bgt; + unsigned int cgt; +} sim_timing_t; + +/* Transfer data for SIM_IOCTL_XFER */ +typedef struct { + unsigned char *xmt_buffer; /* transmit buffer pointer */ + int xmt_length;/* transmit buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after completing transmitting*/ +} sim_xmt_t; + +typedef struct { + unsigned char *rcv_buffer; /* receive buffer pointer */ + int rcv_length; /* receive buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after receiving*/ +} sim_rcv_t; + +typedef struct { + unsigned char di; + unsigned char fi; +} sim_baud_t; + +/* Interface power states */ +#define SIM_POWER_OFF (0) +#define SIM_POWER_ON (1) + +/* Return values for SIM_IOCTL_GET_PRESENSE */ +#define SIM_PRESENT_REMOVED (0) +#define SIM_PRESENT_DETECTED (1) +#define SIM_PRESENT_OPERATIONAL (2) + +/* The error value */ +#define SIM_OK (0) +#define SIM_ERROR_CWT (1 << 0) +#define SIM_ERROR_BWT (1 << 1) +#define SIM_ERROR_PARITY (1 << 2) +#define SIM_ERROR_INVALID_TS (1 << 3) +#define SIM_ERROR_FRAME (1 << 4) +#define SIM_ERROR_ATR_TIMEROUT (1 << 5) +#define SIM_ERROR_NACK_THRESHOLD (1 << 6) +#define SIM_ERROR_BGT (1 << 7) +#define SIM_ERROR_ATR_DELAY (1 << 8) + +/* Return values for SIM_IOCTL_GET_ERROR */ +#define SIM_E_ACCESS (1) +#define SIM_E_TPDUSHORT (2) +#define SIM_E_PTSEMPTY (3) +#define SIM_E_INVALIDXFERTYPE (4) +#define SIM_E_INVALIDXMTLENGTH (5) +#define SIM_E_INVALIDRCVLENGTH (6) +#define SIM_E_NACK (7) +#define SIM_E_TIMEOUT (8) +#define SIM_E_NOCARD (9) +#define SIM_E_PARAM_FI_INVALID (10) +#define SIM_E_PARAM_DI_INVALID (11) +#define SIM_E_PARAM_FBYD_WITHFRACTION (12) +#define SIM_E_PARAM_FBYD_NOTDIVBY8OR12 (13) +#define SIM_E_PARAM_DIVISOR_RANGE (14) +#define SIM_E_MALLOC (15) +#define SIM_E_IRQ (16) +#define SIM_E_POWERED_ON (17) +#define SIM_E_POWERED_OFF (18) + +/* ioctl encodings */ +#define SIM_IOCTL_BASE (0xc0) +#define SIM_IOCTL_GET_PRESENSE _IOR(SIM_IOCTL_BASE, 1, int) +#define SIM_IOCTL_GET_ATR _IOR(SIM_IOCTL_BASE, 2, sim_atr_t) +#define SIM_IOCTL_XMT _IOR(SIM_IOCTL_BASE, 3, sim_xmt_t) +#define SIM_IOCTL_RCV _IOR(SIM_IOCTL_BASE, 4, sim_rcv_t) +#define SIM_IOCTL_ACTIVATE _IO(SIM_IOCTL_BASE, 5) +#define SIM_IOCTL_DEACTIVATE _IO(SIM_IOCTL_BASE, 6) +#define SIM_IOCTL_WARM_RESET _IO(SIM_IOCTL_BASE, 7) +#define SIM_IOCTL_COLD_RESET _IO(SIM_IOCTL_BASE, 8) +#define SIM_IOCTL_CARD_LOCK _IO(SIM_IOCTL_BASE, 9) +#define SIM_IOCTL_CARD_EJECT _IO(SIM_IOCTL_BASE, 10) +#define SIM_IOCTL_SET_PROTOCOL _IOR(SIM_IOCTL_BASE, 11, unsigned int) +#define SIM_IOCTL_SET_TIMING _IOR(SIM_IOCTL_BASE, 12, sim_timing_t) +#define SIM_IOCTL_SET_BAUD _IOR(SIM_IOCTL_BASE, 13, sim_baud_t) +#define SIM_IOCTL_WAIT _IOR(SIM_IOCTL_BASE, 14, unsigned int) + +#endif diff --git a/include/linux/mxc_v4l2.h b/include/linux/mxc_v4l2.h new file mode 100644 index 000000000000..6d778e83ef53 --- /dev/null +++ b/include/linux/mxc_v4l2.h @@ -0,0 +1,27 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file linux/mxc_v4l2.h + * + * @brief MXC V4L2 private header file + * + * @ingroup MXC V4L2 + */ + +#ifndef __LINUX_MXC_V4L2_H__ +#define __LINUX_MXC_V4L2_H__ + +#include <uapi/linux/mxc_v4l2.h> + +#endif diff --git a/include/linux/mxc_vpu-malone.h b/include/linux/mxc_vpu-malone.h new file mode 100755 index 000000000000..4541c8733124 --- /dev/null +++ b/include/linux/mxc_vpu-malone.h @@ -0,0 +1,49 @@ +/* + * Copyright 2017 NXP + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file linux/mxc_vpu-malone.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __LINUX_MXC_VPU_MALONE_H__ +#define __LINUX_MXC_VPU_MALONE_H__ + +#include <linux/fs.h> + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + void *cpu_addr; /* cpu address to free the dma mem */ + u64 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 5) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 7) + +#endif diff --git a/include/linux/mxc_vpu.h b/include/linux/mxc_vpu.h new file mode 100644 index 000000000000..df024698dee7 --- /dev/null +++ b/include/linux/mxc_vpu.h @@ -0,0 +1,118 @@ +/* + * Copyright 2004-2013, 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file linux/mxc_vpu.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __LINUX_MXC_VPU_H__ +#define __LINUX_MXC_VPU_H__ + +#include <linux/fs.h> + +struct mxc_vpu_platform_data { + bool iram_enable; + int iram_size; + void (*reset) (void); + void (*pg) (int); +}; + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + u32 cpu_addr; /* cpu address to free the dma mem */ + u32 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7) +#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8) +#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12) +#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13) +#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14) +#define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15) +#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 16) + +#define BIT_CODE_RUN 0x000 +#define BIT_CODE_DOWN 0x004 +#define BIT_INT_CLEAR 0x00C +#define BIT_INT_STATUS 0x010 +#define BIT_CUR_PC 0x018 +#define BIT_INT_REASON 0x174 + +#define MJPEG_PIC_STATUS_REG 0x3004 +#define MBC_SET_SUBBLK_EN 0x4A0 + +#define BIT_WORK_CTRL_BUF_BASE 0x100 +#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) +#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0) +#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1) +#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2) +#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3) +#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) +#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) + +#ifndef CONFIG_SOC_IMX6Q +#define BIT_RESET_CTRL 0x11C +#else +#define BIT_RESET_CTRL 0x128 +#endif + +/* i could be 0, 1, 2, 3 */ +#define BIT_RD_PTR_BASE 0x120 +#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8) +#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4) + +/* i could be 0, 1, 2, 3 */ +#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140) +#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4) + +#define BIT_BUSY_FLAG 0x160 +#define BIT_RUN_COMMAND 0x164 +#define BIT_INT_ENABLE 0x170 + +#define BITVAL_PIC_RUN 8 + +#define VPU_SLEEP_REG_VALUE 10 +#define VPU_WAKE_REG_VALUE 11 + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +#endif diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h new file mode 100644 index 000000000000..67db5ee3fd11 --- /dev/null +++ b/include/linux/mxcfb.h @@ -0,0 +1,46 @@ +/* + * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/mxcfb.h + * + * @brief Global header file for the MXC Frame buffer + * + * @ingroup Framebuffer + */ +#ifndef __LINUX_MXCFB_H__ +#define __LINUX_MXCFB_H__ + +#include <uapi/linux/mxcfb.h> + +extern struct fb_videomode mxcfb_modedb[]; +extern int mxcfb_modedb_sz; + +enum { + MXC_DISP_SPEC_DEV = 0, + MXC_DISP_DDC_DEV = 1, +}; + +enum { + MXCFB_REFRESH_OFF, + MXCFB_REFRESH_AUTO, + MXCFB_REFRESH_PARTIAL, +}; + +int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode, + struct mxcfb_rect *update_region); +int mxc_elcdif_frame_addr_setup(dma_addr_t phys); +void mxcfb_elcdif_register_mode(const struct fb_videomode *modedb, + int num_modes, int dev_mode); + +#endif diff --git a/include/linux/mxcfb_epdc.h b/include/linux/mxcfb_epdc.h new file mode 100644 index 000000000000..35a8b83b22d3 --- /dev/null +++ b/include/linux/mxcfb_epdc.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _MXCFB_EPDC_KERNEL +#define _MXCFB_EPDC_KERNEL + +struct imx_epdc_fb_mode { + struct fb_videomode *vmode; + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct imx_epdc_fb_platform_data { + struct imx_epdc_fb_mode *epdc_mode; + int num_modes; + int (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); +}; + +#endif diff --git a/include/linux/of.h b/include/linux/of.h index 3c108f9be5e7..fd9b9d2c005f 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -384,6 +384,7 @@ extern int of_phandle_iterator_args(struct of_phandle_iterator *it, extern void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)); extern int of_alias_get_id(struct device_node *np, const char *stem); extern int of_alias_get_highest_id(const char *stem); +extern int of_alias_max_index(const char *stem); extern int of_machine_is_compatible(const char *compat); @@ -826,6 +827,11 @@ static inline int of_alias_get_highest_id(const char *stem) return -ENOSYS; } +static inline int of_alias_max_index(const char *stem) +{ + return -ENODEV; +} + static inline int of_machine_is_compatible(const char *compat) { return 0; diff --git a/include/linux/of_reserved_mem.h b/include/linux/of_reserved_mem.h index bb4fda7317be..2a37f8490ea0 100644 --- a/include/linux/of_reserved_mem.h +++ b/include/linux/of_reserved_mem.h @@ -35,13 +35,13 @@ int of_reserved_mem_device_init_by_idx(struct device *dev, struct device_node *np, int idx); void of_reserved_mem_device_release(struct device *dev); -int early_init_dt_alloc_reserved_memory_arch(phys_addr_t size, +int early_init_dt_alloc_reserved_memory_arch(unsigned long node, + phys_addr_t size, phys_addr_t align, phys_addr_t start, phys_addr_t end, bool nomap, phys_addr_t *res_base); - void fdt_init_reserved_mem(void); void fdt_reserved_mem_save_node(unsigned long node, const char *uname, phys_addr_t base, phys_addr_t size); diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index 809c2f1873ac..36c9ddbb6d30 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -73,5 +73,6 @@ extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */ /* for DT-based PCI controllers that support ECAM */ int pci_host_common_probe(struct platform_device *pdev, struct pci_ecam_ops *ops); +int pci_host_common_remove(struct platform_device *pdev); #endif #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index 59f4d10568c6..13f667f82e5a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1525,12 +1525,10 @@ void pci_cfg_access_unlock(struct pci_dev *dev); */ #ifdef CONFIG_PCI_DOMAINS extern int pci_domains_supported; -int pci_get_new_domain_nr(void); #else enum { pci_domains_supported = 0 }; static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } -static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } #endif /* CONFIG_PCI_DOMAINS */ /* @@ -1686,7 +1684,6 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } -static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } #define dev_is_pci(d) (false) #define dev_is_pf(d) (false) diff --git a/include/linux/phy.h b/include/linux/phy.h index efc04c2d92c9..16caed3a7f8a 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -867,6 +867,7 @@ void phy_attached_info(struct phy_device *phydev); int genphy_config_init(struct phy_device *phydev); int genphy_setup_forced(struct phy_device *phydev); int genphy_restart_aneg(struct phy_device *phydev); +int genphy_config_aneg_check(struct phy_device *phydev); int genphy_config_aneg(struct phy_device *phydev); int genphy_aneg_done(struct phy_device *phydev); int genphy_update_link(struct phy_device *phydev); diff --git a/include/linux/phy/phy-mixel-lvds-combo.h b/include/linux/phy/phy-mixel-lvds-combo.h new file mode 100644 index 000000000000..9eac98c42829 --- /dev/null +++ b/include/linux/phy/phy-mixel-lvds-combo.h @@ -0,0 +1,38 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_LVDS_COMBO_H_ +#define PHY_MIXEL_LVDS_COMBO_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS_COMBO) +void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy, + unsigned long phy_clk_rate); +void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high); +void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high); +#else +void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy, + unsigned long phy_clk_rate) +{ +} +void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high) +{ +} +void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high) +{ +} +#endif + +#endif /* PHY_MIXEL_LVDS_COMBO_H_ */ diff --git a/include/linux/phy/phy-mixel-lvds.h b/include/linux/phy/phy-mixel-lvds.h new file mode 100644 index 000000000000..3540857b7a65 --- /dev/null +++ b/include/linux/phy/phy-mixel-lvds.h @@ -0,0 +1,36 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_LVDS_H_ +#define PHY_MIXEL_LVDS_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS) +void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate); +void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high); +void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high); +#else +void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate) +{ +} +void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high) +{ +} +void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high) +{ +} +#endif + +#endif /* PHY_MIXEL_LVDS_H_ */ diff --git a/include/linux/phy/phy-mixel-mipi-dsi.h b/include/linux/phy/phy-mixel-mipi-dsi.h new file mode 100644 index 000000000000..a76eea4d2704 --- /dev/null +++ b/include/linux/phy/phy-mixel-mipi-dsi.h @@ -0,0 +1,35 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_MIPI_DSI_H_ +#define PHY_MIXEL_MIPI_DSI_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_MIPI_DSI) +int mixel_phy_mipi_set_phy_speed(struct phy *phy, + unsigned long bit_clk, + unsigned long ref_clk, + bool best_match); +#else +int mixel_phy_mipi_set_phy_speed(struct phy *phy, + unsigned long bit_clk, + unsigned long ref_clk, + bool best_match) +{ + return -ENODEV; +} +#endif + +#endif /* PHY_MIXEL_MIPI_DSI_H_ */ diff --git a/include/linux/platform_data/brcmfmac.h b/include/linux/platform_data/brcmfmac.h index 1d30bf278231..b737c0a8e58d 100644 --- a/include/linux/platform_data/brcmfmac.h +++ b/include/linux/platform_data/brcmfmac.h @@ -178,6 +178,7 @@ struct brcmfmac_platform_data { void (*power_off)(void); char *fw_alternative_path; int device_count; + struct device *dev; struct brcmfmac_pd_device devices[0]; }; diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h index 30e676b36b24..da06645bea80 100644 --- a/include/linux/platform_data/dma-imx-sdma.h +++ b/include/linux/platform_data/dma-imx-sdma.h @@ -52,6 +52,8 @@ struct sdma_script_start_addrs { s32 zcanfd_2_mcu_addr; s32 zqspi_2_mcu_addr; s32 mcu_2_ecspi_addr; + s32 mcu_2_sai_addr; + s32 sai_2_mcu_addr; /* End of v3 array */ s32 mcu_2_zqspi_addr; /* End of v4 array */ diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h index 7d964e787299..59e34a321da4 100644 --- a/include/linux/platform_data/dma-imx.h +++ b/include/linux/platform_data/dma-imx.h @@ -1,5 +1,6 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -42,6 +43,8 @@ enum sdma_peripheral_type { IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */ IMX_DMATYPE_ASRC_SP, /* Shared ASRC */ IMX_DMATYPE_SAI, /* SAI */ + IMX_DMATYPE_HDMI, /* HDMI Audio */ + IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */ }; enum imx_dma_prio { @@ -55,6 +58,10 @@ struct imx_dma_data { int dma_request2; /* secondary DMA request line */ enum sdma_peripheral_type peripheral_type; int priority; + bool src_dualfifo; + bool dst_dualfifo; + int idx; + int done_sel; }; static inline int imx_dma_is_ipu(struct dma_chan *chan) @@ -62,6 +69,11 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan) return !strcmp(dev_name(chan->device->dev), "ipu-core"); } +static inline int imx_dma_is_pxp(struct dma_chan *chan) +{ + return strstr(dev_name(chan->device->dev), "pxp") != NULL; +} + static inline int imx_dma_is_general_purpose(struct dma_chan *chan) { return !strcmp(chan->device->dev->driver->name, "imx-sdma") || diff --git a/include/linux/platform_data/mmc-esdhc-imx.h b/include/linux/platform_data/mmc-esdhc-imx.h index 7daa78a2f342..9888c868423b 100644 --- a/include/linux/platform_data/mmc-esdhc-imx.h +++ b/include/linux/platform_data/mmc-esdhc-imx.h @@ -34,7 +34,6 @@ enum cd_types { * @cd_gpio: gpio for card_detect interrupt * @wp_type: type of write_protect method (see wp_types enum above) * @cd_type: type of card_detect method (see cd_types enum above) - * @support_vsel: indicate it supports 1.8v switching */ struct esdhc_platform_data { @@ -43,9 +42,9 @@ struct esdhc_platform_data { enum wp_types wp_type; enum cd_types cd_type; int max_bus_width; - bool support_vsel; unsigned int delay_line; unsigned int tuning_step; /* The delay cell steps in tuning procedure */ unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ + unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ }; #endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 84f423d5633e..49e92073517c 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -90,6 +90,7 @@ struct generic_pm_domain { }; }; + unsigned int state_idx_saved; /* saved power state for recovery after system suspend/resume */ }; static inline struct generic_pm_domain *pd_to_genpd(struct dev_pm_domain *pd) @@ -233,6 +234,8 @@ extern int of_genpd_parse_idle_states(struct device_node *dn, struct genpd_power_state **states, int *n); int genpd_dev_pm_attach(struct device *dev); +struct generic_pm_domain *genpd_get_from_provider( + struct of_phandle_args *genpdspec); #else /* !CONFIG_PM_GENERIC_DOMAINS_OF */ static inline int of_genpd_add_provider_simple(struct device_node *np, struct generic_pm_domain *genpd) @@ -276,6 +279,13 @@ struct generic_pm_domain *of_genpd_remove_last(struct device_node *np) { return ERR_PTR(-ENOTSUPP); } + +static inline +struct generic_pm_domain *genpd_get_from_provider( + struct of_phandle_args *genpdspec) +{ + return ERR_PTR(-ENOTSUPP); +} #endif /* CONFIG_PM_GENERIC_DOMAINS_OF */ #ifdef CONFIG_PM diff --git a/include/linux/pmic_status.h b/include/linux/pmic_status.h new file mode 100644 index 000000000000..a127c7117e13 --- /dev/null +++ b/include/linux/pmic_status.h @@ -0,0 +1,82 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_STATUS_H__ +#define __ASM_ARCH_MXC_PMIC_STATUS_H__ +#include <asm-generic/errno-base.h> +#ifdef __KERNEL__ +#include <asm/uaccess.h> /* copy_{from,to}_user() */ +#endif +/*! + * @file arch-mxc/pmic_status.h + * @brief PMIC APIs return code definition. + * + * @ingroup PMIC_CORE + */ + +/*! + * @enum PMIC_STATUS + * @brief Define return values for all PMIC APIs. + * + * These return values are used by all of the PMIC APIs. + * + * @ingroup PMIC + */ +typedef enum { + PMIC_SUCCESS = 0, /*!< The requested operation was successfully + completed. */ + PMIC_ERROR = -1, /*!< The requested operation could not be completed + due to an error. */ + PMIC_PARAMETER_ERROR = -2, /*!< The requested operation failed because + one or more of the parameters was + invalid. */ + PMIC_NOT_SUPPORTED = -3, /*!< The requested operation could not be + completed because the PMIC hardware + does not support it. */ + PMIC_SYSTEM_ERROR_EINTR = -EINTR, + + PMIC_MALLOC_ERROR = -5, /*!< Error in malloc function */ + PMIC_UNSUBSCRIBE_ERROR = -6, /*!< Error in un-subscribe event */ + PMIC_EVENT_NOT_SUBSCRIBED = -7, /*!< Event occur and not subscribed */ + PMIC_EVENT_CALL_BACK = -8, /*!< Error - bad call back */ + PMIC_CLIENT_NBOVERFLOW = -9, /*!< The requested operation could not be + completed because there are too many + PMIC client requests */ +} PMIC_STATUS; + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Macros implementing error handling + */ +#define CHECK_ERROR(a) \ +do { \ + int ret = (a); \ + if (ret != PMIC_SUCCESS) \ + return ret; \ +} while (0) + +#define CHECK_ERROR_KFREE(func, freeptrs) \ +do { \ + int ret = (func); \ + if (ret != PMIC_SUCCESS) { \ + freeptrs; \ + return ret; \ + } \ +} while (0); + +#endif /* __ASM_ARCH_MXC_PMIC_STATUS_H__ */ diff --git a/include/linux/power/sabresd_battery.h b/include/linux/power/sabresd_battery.h new file mode 100644 index 000000000000..10bfa4588864 --- /dev/null +++ b/include/linux/power/sabresd_battery.h @@ -0,0 +1,65 @@ +/* + * sabresd_battery.h - Maxim 8903 USB/Adapter Charger Driver + * + * Copyright (C) 2011 Samsung Electronics + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * Based on max8903_charger.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MAX8903_SABRESD_H__ +#define __MAX8903_SABRESD_H__ + +struct max8903_pdata { + /* + * GPIOs + * cen, chg, flt, and usus are optional. + * dok, dcm, and uok are not optional depending on the status of + * dc_valid and usb_valid. + */ + int cen; /* Charger Enable input */ + int dok; /* DC(Adapter) Power OK output */ + int uok; /* USB Power OK output */ + int chg; /* Charger status output */ + int flt; /* Fault output */ + int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */ + int usus; /* USB Suspend Input (1: suspended) */ + int feature_flag;/* battery capacity feature(0:enable, 1:disable) */ + + /* + * DCM wired to Logic High Set this true when DCM pin connect to + * Logic high. + */ + bool dcm_always_high; + + /* + * DC(Adapter/TA) is wired + * When dc_valid is true, + * dok and dcm should be valid. + * + * At least one of dc_valid or usb_valid should be true. + */ + bool dc_valid; + /* + * USB is wired + * When usb_valid is true, + * uok should be valid. + */ + bool usb_valid; +}; + +#endif /* __SABRESD_BATTERY_H__ */ diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h index e8afbd71a140..cac4d427cde4 100644 --- a/include/linux/pwm_backlight.h +++ b/include/linux/pwm_backlight.h @@ -21,6 +21,7 @@ struct platform_pwm_backlight_data { void (*notify_after)(struct device *dev, int brightness); void (*exit)(struct device *dev); int (*check_fb)(struct device *dev, struct fb_info *info); + char fb_id[16]; }; #endif diff --git a/include/linux/pxp_device.h b/include/linux/pxp_device.h new file mode 100644 index 000000000000..df185c49d017 --- /dev/null +++ b/include/linux/pxp_device.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _PXP_DEVICE +#define _PXP_DEVICE + +#include <linux/idr.h> +#include <linux/hash.h> +#include <uapi/linux/pxp_device.h> + +struct pxp_irq_info { + wait_queue_head_t waitq; + atomic_t irq_pending; + int hist_status; +}; + +struct pxp_buffer_hash { + struct hlist_head *hash_table; + u32 order; + spinlock_t hash_lock; +}; + +struct pxp_buf_obj { + uint32_t handle; + + uint32_t size; + uint32_t mem_type; + + unsigned long offset; + void *virtual; + + struct hlist_node item; +}; + +struct pxp_chan_obj { + uint32_t handle; + struct dma_chan *chan; +}; + +/* File private data */ +struct pxp_file { + struct file *filp; + + /* record allocated dma buffer */ + struct idr buffer_idr; + spinlock_t buffer_lock; + + /* record allocated dma channel */ + struct idr channel_idr; + spinlock_t channel_lock; +}; + +#endif diff --git a/include/linux/pxp_dma.h b/include/linux/pxp_dma.h new file mode 100644 index 000000000000..a48871caebfc --- /dev/null +++ b/include/linux/pxp_dma.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _PXP_DMA +#define _PXP_DMA + +#include <uapi/linux/pxp_dma.h> + +struct pxp_tx_desc { + struct dma_async_tx_descriptor txd; + struct list_head tx_list; + struct list_head list; + int len; + union { + struct pxp_layer_param s0_param; + struct pxp_layer_param out_param; + struct pxp_layer_param ol_param; + struct pxp_layer_param processing_param; + } layer_param; + struct pxp_proc_data proc_data; + + u32 hist_status; /* Histogram output status */ + + struct pxp_tx_desc *next; +}; + +struct pxp_channel { + struct dma_chan dma_chan; + dma_cookie_t completed; /* last completed cookie */ + enum pxp_channel_status status; + void *client; /* Only one client per channel */ + unsigned int n_tx_desc; + struct pxp_tx_desc *desc; /* allocated tx-descriptors */ + struct list_head active_list; /* active tx-descriptors */ + struct list_head free_list; /* free tx-descriptors */ + struct list_head queue; /* queued tx-descriptors */ + struct list_head list; /* track queued channel number */ + spinlock_t lock; /* protects sg[0,1], queue */ + struct mutex chan_mutex; /* protects status, cookie, free_list */ + int active_buffer; + unsigned int eof_irq; + char eof_name[16]; /* EOF IRQ name for request_irq() */ +}; + +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) + +void pxp_txd_ack(struct dma_async_tx_descriptor *txd, + struct pxp_channel *pxp_chan); + +#ifdef CONFIG_MXC_PXP_CLIENT_DEVICE +int register_pxp_device(void); +void unregister_pxp_device(void); +#else +static int register_pxp_device(void) { return 0; } +static void unregister_pxp_device(void) {} +#endif +void pxp_fill( + u32 bpp, + u32 value, + u32 width, + u32 height, + u32 output_buffer, + u32 output_pitch); + +void m4_process(void); +#endif diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h index f3f76051e8b0..82875120a9c4 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -121,6 +121,9 @@ struct regmap; #define REGULATOR_EVENT_PRE_DISABLE 0x400 #define REGULATOR_EVENT_ABORT_DISABLE 0x800 #define REGULATOR_EVENT_ENABLE 0x1000 +#define REGULATOR_EVENT_PRE_DO_ENABLE 0x2000 +#define REGULATOR_EVENT_PRE_DO_DISABLE 0x4000 +#define REGULATOR_EVENT_AFT_DO_ENABLE 0x8000 /* * Regulator errors that can be queried using regulator_get_error_flags diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h index 48918be649d4..ba4ac009d832 100644 --- a/include/linux/regulator/fixed.h +++ b/include/linux/regulator/fixed.h @@ -51,6 +51,7 @@ struct fixed_voltage_config { int microvolts; int gpio; unsigned startup_delay; + unsigned off_on_delay; unsigned gpio_is_open_drain:1; unsigned enable_high:1; unsigned enabled_at_boot:1; diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h index 10d6ae8bbb7d..df056ad6bf78 100644 --- a/include/linux/rpmsg.h +++ b/include/linux/rpmsg.h @@ -43,6 +43,8 @@ #include <linux/mutex.h> #include <linux/poll.h> +#define VIRTIO_RPMSG_F_NS 0 + #define RPMSG_ADDR_ANY 0xFFFFFFFF struct rpmsg_device; diff --git a/include/linux/tee_drv.h b/include/linux/tee_drv.h index cb889afe576b..07bd226cd5f9 100644 --- a/include/linux/tee_drv.h +++ b/include/linux/tee_drv.h @@ -25,8 +25,9 @@ * specific TEE driver. */ -#define TEE_SHM_MAPPED 0x1 /* Memory mapped by the kernel */ -#define TEE_SHM_DMA_BUF 0x2 /* Memory with dma-buf handle */ +#define TEE_SHM_MAPPED BIT(0) /* Memory mapped by the kernel */ +#define TEE_SHM_DMA_BUF BIT(1) /* Memory with dma-buf handle */ +#define TEE_SHM_EXT_DMA_BUF BIT(2) /* Memory with dma-buf handle */ struct device; struct tee_device; @@ -211,6 +212,16 @@ void *tee_get_drvdata(struct tee_device *teedev); struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags); /** + * tee_shm_register_fd() - Register shared memory from file descriptor + * + * @ctx: Context that allocates the shared memory + * @fd: shared memory file descriptor reference. + * + * @returns a pointer to 'struct tee_shm' + */ +struct tee_shm *tee_shm_register_fd(struct tee_context *ctx, int fd); + +/** * tee_shm_free() - Free shared memory * @shm: Handle to shared memory to free */ @@ -275,4 +286,36 @@ int tee_shm_get_id(struct tee_shm *shm); */ struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id); +static inline bool tee_param_is_memref(struct tee_param *param) +{ + switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) { + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT: + return true; + default: + return false; + } +} + +struct tee_context *tee_client_open_context(struct tee_context *start, + int (*match)(struct tee_ioctl_version_data *, + const void *), + const void *data, struct tee_ioctl_version_data *vers); + +void tee_client_close_context(struct tee_context *ctx); + +void tee_client_get_version(struct tee_context *ctx, + struct tee_ioctl_version_data *vers); + +int tee_client_open_session(struct tee_context *ctx, + struct tee_ioctl_open_session_arg *arg, + struct tee_param *param); + +int tee_client_close_session(struct tee_context *ctx, u32 session); + +int tee_client_invoke_func(struct tee_context *ctx, + struct tee_ioctl_invoke_arg *arg, + struct tee_param *param); + #endif /*__TEE_DRV_H*/ diff --git a/include/linux/usb.h b/include/linux/usb.h index a22a3e139e96..991b467012ac 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -431,6 +431,7 @@ struct usb_bus { * Does the host controller use PIO * for control transfers? */ + struct otg_fsm *otg_fsm; /* usb otg finite state machine */ u8 otg_port; /* 0, or number of OTG/HNP port */ unsigned is_b_host:1; /* true during some HNP roleswitches */ unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */ diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 523aa088f6ab..db21b11bec6e 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -62,4 +62,29 @@ extern enum usb_device_speed usb_get_maximum_speed(struct device *dev); */ extern const char *usb_state_string(enum usb_device_state state); +/** + * usb_decode_ctrl - Returns human readable representation of control request. + * @str: buffer to return a human-readable representation of control request. + * This buffer should have about 200 bytes. + * @size: size of str buffer. + * @bRequestType: matches the USB bmRequestType field + * @bRequest: matches the USB bRequest field + * @wValue: matches the USB wValue field (CPU byte order) + * @wIndex: matches the USB wIndex field (CPU byte order) + * @wLength: matches the USB wLength field (CPU byte order) + * + * Function returns decoded, formatted and human-readable description of + * control request packet. + * + * The usage scenario for this is for tracepoints, so function as a return + * use the same value as in parameters. This approach allows to use this + * function in TP_printk + * + * Important: wValue, wIndex, wLength parameters before invoking this function + * should be processed by le16_to_cpu macro. + */ +const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType, + __u8 bRequest, __u16 wValue, __u16 wIndex, + __u16 wLength); + #endif /* __LINUX_USB_CH9_H */ diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index 07f99362bc90..fe79de7f264e 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -60,9 +60,22 @@ struct ci_hdrc_platform_data { #define CI_HDRC_OVERRIDE_RX_BURST BIT(11) #define CI_HDRC_OVERRIDE_PHY_CONTROL BIT(12) /* Glue layer manages phy */ #define CI_HDRC_REQUIRES_ALIGNED_DMA BIT(13) +#define CI_HDRC_IMX_EHCI_QUIRK BIT(14) +#define CI_HDRC_IMX_IS_HSIC BIT(15) +/* need request pmqos during low power */ +#define CI_HDRC_PMQOS BIT(16) +/* Using PHY's charger detection */ +#define CI_HDRC_PHY_CHARGER_DETECTION BIT(17) +/* PHY enter low power mode when bus suspend */ +#define CI_HDRC_HOST_SUSP_PHY_LPM BIT(18) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 +#define CI_HDRC_CONTROLLER_VBUS_EVENT 2 +#define CI_HDRC_IMX_HSIC_ACTIVE_EVENT 5 +#define CI_HDRC_IMX_HSIC_SUSPEND_EVENT 6 +#define CI_HDRC_IMX_TERM_SELECT_OVERRIDE_FS 7 +#define CI_HDRC_IMX_TERM_SELECT_OVERRIDE_OFF 8 int (*notify_event) (struct ci_hdrc *ci, unsigned event); struct regulator *reg_vbus; struct usb_otg_caps ci_otg_caps; @@ -89,4 +102,6 @@ struct platform_device *ci_hdrc_add_device(struct device *dev, /* Remove ci hdrc device */ void ci_hdrc_remove_device(struct platform_device *pdev); +/* Get current available role */ +enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev); #endif diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index a1f03ebfde47..ea7fe49daa1d 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -398,7 +398,10 @@ struct hc_driver { int (*find_raw_port_number)(struct usb_hcd *, int); /* Call for power on/off the port if necessary */ int (*port_power)(struct usb_hcd *hcd, int portnum, bool enable); - + /* Call for SINGLE_STEP_SET_FEATURE Test for USB2 EH certification */ +#define EHSET_TEST_SINGLE_STEP_SET_FEATURE 0x06 + int (*submit_single_step_set_feature)(struct usb_hcd *, + struct urb *, int); }; static inline int hcd_giveback_urb_in_bh(struct usb_hcd *hcd) @@ -456,6 +459,14 @@ extern int usb_hcd_find_raw_port_number(struct usb_hcd *hcd, int port1); struct platform_device; extern void usb_hcd_platform_shutdown(struct platform_device *dev); +#ifdef CONFIG_USB_HCD_TEST_MODE +extern int ehset_single_step_set_feature(struct usb_hcd *hcd, int port); +#else +static inline int ehset_single_step_set_feature(struct usb_hcd *hcd, int port) +{ + return 0; +} +#endif /* CONFIG_USB_HCD_TEST_MODE */ #ifdef CONFIG_USB_PCI struct pci_dev; diff --git a/include/linux/usb/otg-fsm.h b/include/linux/usb/otg-fsm.h index a0a8f878503c..afebc95703d0 100644 --- a/include/linux/usb/otg-fsm.h +++ b/include/linux/usb/otg-fsm.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. +/* Copyright (C) 2007-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -53,6 +53,10 @@ enum otg_fsm_timer { A_WAIT_ENUM, B_DATA_PLS, B_SSEND_SRP, + A_DP_END, + A_TST_MAINT, + B_SRP_REQD, + B_TST_SUSP, NUM_OTG_FSM_TIMERS, }; @@ -170,6 +174,13 @@ struct otg_fsm { int b_srp_done; int b_hnp_enable; int a_clr_err; + int hnp_polling; + + /* OTG test device */ + int tst_maint; + int otg_vbus_off; + int otg_srp_reqd; + int otg_hnp_reqd; /* Informative variables. All unused as of now */ int a_bus_drop_inf; diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h index b7a2625947f5..ef89950cb68a 100644 --- a/include/linux/usb/phy.h +++ b/include/linux/usb/phy.h @@ -63,6 +63,13 @@ enum usb_otg_state { OTG_STATE_A_VBUS_ERR, }; +/* The usb role of phy to be working with */ +enum usb_current_mode { + USB_MODE_NONE, + USB_MODE_HOST, + USB_MODE_DEVICE, +}; + struct usb_phy; struct usb_otg; @@ -155,6 +162,15 @@ struct usb_phy { * manually detect the charger type. */ enum usb_charger_type (*charger_detect)(struct usb_phy *x); + + int (*notify_suspend)(struct usb_phy *x, + enum usb_device_speed speed); + int (*notify_resume)(struct usb_phy *x, + enum usb_device_speed speed); + + int (*set_mode)(struct usb_phy *x, + enum usb_current_mode mode); + }; /** @@ -229,6 +245,15 @@ usb_phy_vbus_off(struct usb_phy *x) return x->set_vbus(x, false); } +static inline int +usb_phy_set_mode(struct usb_phy *x, enum usb_current_mode mode) +{ + if (!x || !x->set_mode) + return 0; + + return x->set_mode(x, mode); +} + /* for usb host and peripheral controller drivers */ #if IS_ENABLED(CONFIG_USB_PHY) extern struct usb_phy *usb_get_phy(enum usb_phy_type type); @@ -370,6 +395,24 @@ usb_phy_notify_disconnect(struct usb_phy *x, enum usb_device_speed speed) return 0; } +static inline int usb_phy_notify_suspend + (struct usb_phy *x, enum usb_device_speed speed) +{ + if (x && x->notify_suspend) + return x->notify_suspend(x, speed); + else + return 0; +} + +static inline int usb_phy_notify_resume + (struct usb_phy *x, enum usb_device_speed speed) +{ + if (x && x->notify_resume) + return x->notify_resume(x, speed); + else + return 0; +} + /* notifiers */ static inline int usb_register_notifier(struct usb_phy *x, struct notifier_block *nb) diff --git a/include/linux/usb/typec.h b/include/linux/usb/typec.h index 0d44ce6af08f..41320b14d29c 100644 --- a/include/linux/usb/typec.h +++ b/include/linux/usb/typec.h @@ -25,6 +25,7 @@ enum typec_port_type { TYPEC_PORT_DFP, TYPEC_PORT_UFP, TYPEC_PORT_DRP, + TYPEC_PORT_TYPE_UNKNOWN, }; enum typec_plug_type { @@ -43,6 +44,7 @@ enum typec_data_role { enum typec_role { TYPEC_SINK, TYPEC_SOURCE, + TYPEC_ROLE_UNKNOWN, }; enum typec_pwr_opmode { @@ -244,5 +246,7 @@ void typec_set_data_role(struct typec_port *port, enum typec_data_role role); void typec_set_pwr_role(struct typec_port *port, enum typec_role role); void typec_set_vconn_role(struct typec_port *port, enum typec_role role); void typec_set_pwr_opmode(struct typec_port *port, enum typec_pwr_opmode mode); +enum typec_port_type typec_get_port_type(struct device *dev); +enum typec_role typec_get_power_role(struct device *dev); #endif /* __LINUX_USB_TYPEC_H */ diff --git a/include/linux/wakelock.h b/include/linux/wakelock.h new file mode 100644 index 000000000000..f4a698a22880 --- /dev/null +++ b/include/linux/wakelock.h @@ -0,0 +1,67 @@ +/* include/linux/wakelock.h + * + * Copyright (C) 2007-2012 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_WAKELOCK_H +#define _LINUX_WAKELOCK_H + +#include <linux/ktime.h> +#include <linux/device.h> + +/* A wake_lock prevents the system from entering suspend or other low power + * states when active. If the type is set to WAKE_LOCK_SUSPEND, the wake_lock + * prevents a full system suspend. + */ + +enum { + WAKE_LOCK_SUSPEND, /* Prevent suspend */ + WAKE_LOCK_TYPE_COUNT +}; + +struct wake_lock { + struct wakeup_source ws; +}; + +static inline void wake_lock_init(struct wake_lock *lock, int type, + const char *name) +{ + wakeup_source_init(&lock->ws, name); +} + +static inline void wake_lock_destroy(struct wake_lock *lock) +{ + wakeup_source_trash(&lock->ws); +} + +static inline void wake_lock(struct wake_lock *lock) +{ + __pm_stay_awake(&lock->ws); +} + +static inline void wake_lock_timeout(struct wake_lock *lock, long timeout) +{ + __pm_wakeup_event(&lock->ws, jiffies_to_msecs(timeout)); +} + +static inline void wake_unlock(struct wake_lock *lock) +{ + __pm_relax(&lock->ws); +} + +static inline int wake_lock_active(struct wake_lock *lock) +{ + return lock->ws.active; +} + +#endif diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h new file mode 100644 index 000000000000..b4c8416c3d1f --- /dev/null +++ b/include/media/v4l2-chip-ident.h @@ -0,0 +1,355 @@ +/* + v4l2 chip identifiers header + + This header provides a list of chip identifiers that can be returned + through the VIDIOC_DBG_G_CHIP_IDENT ioctl. + + Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef V4L2_CHIP_IDENT_H_ +#define V4L2_CHIP_IDENT_H_ + +/* VIDIOC_DBG_G_CHIP_IDENT: identifies the actual chip installed on the board */ + +/* KEEP THIS LIST ORDERED BY ID! + Otherwise it will be hard to see which ranges are already in use when + adding support to a new chip family. */ +enum { + /* general idents: reserved range 0-49 */ + V4L2_IDENT_NONE = 0, /* No chip matched */ + V4L2_IDENT_AMBIGUOUS = 1, /* Match too general, multiple chips matched */ + V4L2_IDENT_UNKNOWN = 2, /* Chip found, but cannot identify */ + + /* module tvaudio: reserved range 50-99 */ + V4L2_IDENT_TVAUDIO = 50, /* A tvaudio chip, unknown which it is exactly */ + + /* Sony IMX074 */ + V4L2_IDENT_IMX074 = 74, + + /* module saa7110: just ident 100 */ + V4L2_IDENT_SAA7110 = 100, + + /* module saa7115: reserved range 101-149 */ + V4L2_IDENT_SAA7111 = 101, + V4L2_IDENT_SAA7111A = 102, + V4L2_IDENT_SAA7113 = 103, + V4L2_IDENT_SAA7114 = 104, + V4L2_IDENT_SAA7115 = 105, + V4L2_IDENT_SAA7118 = 108, + + V4L2_IDENT_GM7113C = 140, + + /* module saa7127: reserved range 150-199 */ + V4L2_IDENT_SAA7127 = 157, + V4L2_IDENT_SAA7129 = 159, + + /* module cx25840: reserved range 200-249 */ + V4L2_IDENT_CX25836 = 236, + V4L2_IDENT_CX25837 = 237, + V4L2_IDENT_CX25840 = 240, + V4L2_IDENT_CX25841 = 241, + V4L2_IDENT_CX25842 = 242, + V4L2_IDENT_CX25843 = 243, + + /* OmniVision sensors: reserved range 250-299 */ + V4L2_IDENT_OV7670 = 250, + V4L2_IDENT_OV7720 = 251, + V4L2_IDENT_OV7725 = 252, + V4L2_IDENT_OV7660 = 253, + V4L2_IDENT_OV9650 = 254, + V4L2_IDENT_OV9655 = 255, + V4L2_IDENT_SOI968 = 256, + V4L2_IDENT_OV9640 = 257, + V4L2_IDENT_OV6650 = 258, + V4L2_IDENT_OV2640 = 259, + V4L2_IDENT_OV9740 = 260, + V4L2_IDENT_OV5642 = 261, + + /* module saa7146: reserved range 300-309 */ + V4L2_IDENT_SAA7146 = 300, + + /* Conexant MPEG encoder/decoders: reserved range 400-420 */ + V4L2_IDENT_CX23418_843 = 403, /* Integrated A/V Decoder on the '418 */ + V4L2_IDENT_CX23415 = 415, + V4L2_IDENT_CX23416 = 416, + V4L2_IDENT_CX23417 = 417, + V4L2_IDENT_CX23418 = 418, + + /* module bt819: reserved range 810-819 */ + V4L2_IDENT_BT815A = 815, + V4L2_IDENT_BT817A = 817, + V4L2_IDENT_BT819A = 819, + + /* module au0828 */ + V4L2_IDENT_AU0828 = 828, + + /* module bttv: ident 848 + 849 */ + V4L2_IDENT_BT848 = 848, + V4L2_IDENT_BT849 = 849, + + /* module bt856: just ident 856 */ + V4L2_IDENT_BT856 = 856, + + /* module bt866: just ident 866 */ + V4L2_IDENT_BT866 = 866, + + /* module bttv: ident 878 + 879 */ + V4L2_IDENT_BT878 = 878, + V4L2_IDENT_BT879 = 879, + + /* module ks0127: reserved range 1120-1129 */ + V4L2_IDENT_KS0122S = 1122, + V4L2_IDENT_KS0127 = 1127, + V4L2_IDENT_KS0127B = 1128, + + /* module indycam: just ident 2000 */ + V4L2_IDENT_INDYCAM = 2000, + + /* module vp27smpx: just ident 2700 */ + V4L2_IDENT_VP27SMPX = 2700, + + /* module vpx3220: reserved range: 3210-3229 */ + V4L2_IDENT_VPX3214C = 3214, + V4L2_IDENT_VPX3216B = 3216, + V4L2_IDENT_VPX3220A = 3220, + + /* VX855 just ident 3409 */ + /* Other via devs could use 3314, 3324, 3327, 3336, 3364, 3353 */ + V4L2_IDENT_VIA_VX855 = 3409, + + /* module tvp5150 */ + V4L2_IDENT_TVP5150 = 5150, + + /* module saa5246a: just ident 5246 */ + V4L2_IDENT_SAA5246A = 5246, + + /* module saa5249: just ident 5249 */ + V4L2_IDENT_SAA5249 = 5249, + + /* module cs5345: just ident 5345 */ + V4L2_IDENT_CS5345 = 5345, + + /* module tea6415c: just ident 6415 */ + V4L2_IDENT_TEA6415C = 6415, + + /* module tea6420: just ident 6420 */ + V4L2_IDENT_TEA6420 = 6420, + + /* module saa6588: just ident 6588 */ + V4L2_IDENT_SAA6588 = 6588, + + /* module vs6624: just ident 6624 */ + V4L2_IDENT_VS6624 = 6624, + + /* module saa6752hs: reserved range 6750-6759 */ + V4L2_IDENT_SAA6752HS = 6752, + V4L2_IDENT_SAA6752HS_AC3 = 6753, + + /* modules tef6862: just ident 6862 */ + V4L2_IDENT_TEF6862 = 6862, + + /* module tvp7002: just ident 7002 */ + V4L2_IDENT_TVP7002 = 7002, + + /* module adv7170: just ident 7170 */ + V4L2_IDENT_ADV7170 = 7170, + + /* module adv7175: just ident 7175 */ + V4L2_IDENT_ADV7175 = 7175, + + /* module adv7180: just ident 7180 */ + V4L2_IDENT_ADV7180 = 7180, + + /* module adv7183: just ident 7183 */ + V4L2_IDENT_ADV7183 = 7183, + + /* module saa7185: just ident 7185 */ + V4L2_IDENT_SAA7185 = 7185, + + /* module saa7191: just ident 7191 */ + V4L2_IDENT_SAA7191 = 7191, + + /* module ths7303: just ident 7303 */ + V4L2_IDENT_THS7303 = 7303, + + /* module adv7343: just ident 7343 */ + V4L2_IDENT_ADV7343 = 7343, + + /* module ths7353: just ident 7353 */ + V4L2_IDENT_THS7353 = 7353, + + /* module adv7393: just ident 7393 */ + V4L2_IDENT_ADV7393 = 7393, + + /* module adv7604: just ident 7604 */ + V4L2_IDENT_ADV7604 = 7604, + + /* module saa7706h: just ident 7706 */ + V4L2_IDENT_SAA7706H = 7706, + + /* module mt9v011, just ident 8243 */ + V4L2_IDENT_MT9V011 = 8243, + + /* module wm8739: just ident 8739 */ + V4L2_IDENT_WM8739 = 8739, + + /* module wm8775: just ident 8775 */ + V4L2_IDENT_WM8775 = 8775, + + /* Marvell controllers starting at 8801 */ + V4L2_IDENT_CAFE = 8801, + V4L2_IDENT_ARMADA610 = 8802, + + /* AKM AK8813/AK8814 */ + V4L2_IDENT_AK8813 = 8813, + V4L2_IDENT_AK8814 = 8814, + + /* module cx23885 and cx25840 */ + V4L2_IDENT_CX23885 = 8850, + V4L2_IDENT_CX23885_AV = 8851, /* Integrated A/V decoder */ + V4L2_IDENT_CX23887 = 8870, + V4L2_IDENT_CX23887_AV = 8871, /* Integrated A/V decoder */ + V4L2_IDENT_CX23888 = 8880, + V4L2_IDENT_CX23888_AV = 8881, /* Integrated A/V decoder */ + V4L2_IDENT_CX23888_IR = 8882, /* Integrated infrared controller */ + + /* module ad9389b: just ident 9389 */ + V4L2_IDENT_AD9389B = 9389, + + /* module tda9840: just ident 9840 */ + V4L2_IDENT_TDA9840 = 9840, + + /* module tw9910: just ident 9910 */ + V4L2_IDENT_TW9910 = 9910, + + /* module sn9c20x: just ident 10000 */ + V4L2_IDENT_SN9C20X = 10000, + + /* module cx231xx and cx25840 */ + V4L2_IDENT_CX2310X_AV = 23099, /* Integrated A/V decoder; not in '100 */ + V4L2_IDENT_CX23100 = 23100, + V4L2_IDENT_CX23101 = 23101, + V4L2_IDENT_CX23102 = 23102, + + /* module msp3400: reserved range 34000-34999 for msp34xx */ + V4L2_IDENT_MSPX4XX = 34000, /* generic MSPX4XX identifier, only + use internally (tveeprom.c). */ + + V4L2_IDENT_MSP3400B = 34002, + V4L2_IDENT_MSP3400C = 34003, + V4L2_IDENT_MSP3400D = 34004, + V4L2_IDENT_MSP3400G = 34007, + V4L2_IDENT_MSP3401G = 34017, + V4L2_IDENT_MSP3402G = 34027, + V4L2_IDENT_MSP3405D = 34054, + V4L2_IDENT_MSP3405G = 34057, + V4L2_IDENT_MSP3407D = 34074, + V4L2_IDENT_MSP3407G = 34077, + + V4L2_IDENT_MSP3410B = 34102, + V4L2_IDENT_MSP3410C = 34103, + V4L2_IDENT_MSP3410D = 34104, + V4L2_IDENT_MSP3410G = 34107, + V4L2_IDENT_MSP3411G = 34117, + V4L2_IDENT_MSP3412G = 34127, + V4L2_IDENT_MSP3415D = 34154, + V4L2_IDENT_MSP3415G = 34157, + V4L2_IDENT_MSP3417D = 34174, + V4L2_IDENT_MSP3417G = 34177, + + V4L2_IDENT_MSP3420G = 34207, + V4L2_IDENT_MSP3421G = 34217, + V4L2_IDENT_MSP3422G = 34227, + V4L2_IDENT_MSP3425G = 34257, + V4L2_IDENT_MSP3427G = 34277, + + V4L2_IDENT_MSP3430G = 34307, + V4L2_IDENT_MSP3431G = 34317, + V4L2_IDENT_MSP3435G = 34357, + V4L2_IDENT_MSP3437G = 34377, + + V4L2_IDENT_MSP3440G = 34407, + V4L2_IDENT_MSP3441G = 34417, + V4L2_IDENT_MSP3442G = 34427, + V4L2_IDENT_MSP3445G = 34457, + V4L2_IDENT_MSP3447G = 34477, + + V4L2_IDENT_MSP3450G = 34507, + V4L2_IDENT_MSP3451G = 34517, + V4L2_IDENT_MSP3452G = 34527, + V4L2_IDENT_MSP3455G = 34557, + V4L2_IDENT_MSP3457G = 34577, + + V4L2_IDENT_MSP3460G = 34607, + V4L2_IDENT_MSP3461G = 34617, + V4L2_IDENT_MSP3465G = 34657, + V4L2_IDENT_MSP3467G = 34677, + + /* module msp3400: reserved range 44000-44999 for msp44xx */ + V4L2_IDENT_MSP4400G = 44007, + V4L2_IDENT_MSP4408G = 44087, + V4L2_IDENT_MSP4410G = 44107, + V4L2_IDENT_MSP4418G = 44187, + V4L2_IDENT_MSP4420G = 44207, + V4L2_IDENT_MSP4428G = 44287, + V4L2_IDENT_MSP4440G = 44407, + V4L2_IDENT_MSP4448G = 44487, + V4L2_IDENT_MSP4450G = 44507, + V4L2_IDENT_MSP4458G = 44587, + + /* Micron CMOS sensor chips: 45000-45099 */ + V4L2_IDENT_MT9M001C12ST = 45000, + V4L2_IDENT_MT9M001C12STM = 45005, + V4L2_IDENT_MT9M111 = 45007, + V4L2_IDENT_MT9M112 = 45008, + V4L2_IDENT_MT9V022IX7ATC = 45010, /* No way to detect "normal" I77ATx */ + V4L2_IDENT_MT9V022IX7ATM = 45015, /* and "lead free" IA7ATx chips */ + V4L2_IDENT_MT9T031 = 45020, + V4L2_IDENT_MT9T111 = 45021, + V4L2_IDENT_MT9T112 = 45022, + V4L2_IDENT_MT9V111 = 45031, + V4L2_IDENT_MT9V112 = 45032, + + /* HV7131R CMOS sensor: just ident 46000 */ + V4L2_IDENT_HV7131R = 46000, + + /* Sharp RJ54N1CB0C, 0xCB0C = 51980 */ + V4L2_IDENT_RJ54N1CB0C = 51980, + + /* module m52790: just ident 52790 */ + V4L2_IDENT_M52790 = 52790, + + /* module cs53132a: just ident 53132 */ + V4L2_IDENT_CS53l32A = 53132, + + /* modules upd61151 MPEG2 encoder: just ident 54000 */ + V4L2_IDENT_UPD61161 = 54000, + /* modules upd61152 MPEG2 encoder with AC3: just ident 54001 */ + V4L2_IDENT_UPD61162 = 54001, + + /* module upd64031a: just ident 64031 */ + V4L2_IDENT_UPD64031A = 64031, + + /* module upd64083: just ident 64083 */ + V4L2_IDENT_UPD64083 = 64083, + + /* Don't just add new IDs at the end: KEEP THIS LIST ORDERED BY ID! */ +}; + +#endif diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index 28a686eb7d09..6cd753236213 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -153,6 +153,7 @@ struct v4l2_file_operations { ssize_t (*read) (struct file *, char __user *, size_t, loff_t *); ssize_t (*write) (struct file *, const char __user *, size_t, loff_t *); unsigned int (*poll) (struct file *, struct poll_table_struct *); + long (*ioctl) (struct file *, unsigned int, unsigned long); long (*unlocked_ioctl) (struct file *, unsigned int, unsigned long); #ifdef CONFIG_COMPAT long (*compat_ioctl32) (struct file *, unsigned int, unsigned long); diff --git a/include/media/v4l2-device.h b/include/media/v4l2-device.h index 8ffa94009d1a..bb97f64e91c8 100644 --- a/include/media/v4l2-device.h +++ b/include/media/v4l2-device.h @@ -69,6 +69,8 @@ struct v4l2_device { unsigned int notification, void *arg); struct v4l2_ctrl_handler *ctrl_handler; struct v4l2_prio_state prio; + /* BKL replacement mutex. Temporary solution only. */ + struct mutex ioctl_lock; struct kref ref; void (*release)(struct v4l2_device *v4l2_dev); }; diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h index a7b3f7c75d62..15563d874af1 100644 --- a/include/media/v4l2-ioctl.h +++ b/include/media/v4l2-ioctl.h @@ -555,6 +555,8 @@ struct v4l2_ioctl_ops { int (*vidioc_g_chip_info)(struct file *file, void *fh, struct v4l2_dbg_chip_info *chip); #endif + int (*vidioc_g_chip_ident) (struct file *file, void *fh, + struct v4l2_dbg_chip_ident *chip); int (*vidioc_enum_framesizes)(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize); diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index e83872078376..fb143fd2ea43 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -97,6 +97,7 @@ struct v4l2_decode_vbi_line { /* * Core ops: it is highly recommended to implement at least these ops: * + * g_chip_ident * log_status * g_register * s_register @@ -186,6 +187,7 @@ struct v4l2_subdev_io_pin_config { * @unsubscribe_event: remove event subscription from the control framework. */ struct v4l2_subdev_core_ops { + int (*g_chip_ident)(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip); int (*log_status)(struct v4l2_subdev *sd); int (*s_io_pin_config)(struct v4l2_subdev *sd, size_t n, struct v4l2_subdev_io_pin_config *pincfg); diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index 030eea38f258..843dfacd1710 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -3282,6 +3282,7 @@ enum wiphy_flags { WIPHY_FLAG_SUPPORTS_5_10_MHZ = BIT(22), WIPHY_FLAG_HAS_CHANNEL_SWITCH = BIT(23), WIPHY_FLAG_HAS_STATIC_WEP = BIT(24), + WIPHY_FLAG_DFS_OFFLOAD = BIT(25) }; /** @@ -4529,6 +4530,32 @@ void cfg80211_send_layer2_update(struct net_device *dev, const u8 *addr); int regulatory_hint(struct wiphy *wiphy, const char *alpha2); /** + * regulatory_hint_user - hint to the wireless core a regulatory domain + * which the driver has received from an application + * @alpha2: the ISO/IEC 3166 alpha2 the driver claims its regulatory domain + * should be in. If @rd is set this should be NULL. Note that if you + * set this to NULL you should still set rd->alpha2 to some accepted + * alpha2. + * @user_reg_hint_type: the type of user regulatory hint. + * + * Wireless drivers can use this function to hint to the wireless core + * the current regulatory domain as specified by trusted applications, + * it is the driver's responsibilty to estbalish which applications it + * trusts. + * + * The wiphy should be registered to cfg80211 prior to this call. + * For cfg80211 drivers this means you must first use wiphy_register(), + * for mac80211 drivers you must first use ieee80211_register_hw(). + * + * Drivers should check the return value, its possible you can get + * an -ENOMEM or an -EINVAL. + * + * Return: 0 on success. -ENOMEM, -EINVAL. + */ +int regulatory_hint_user(const char *alpha2, + enum nl80211_user_reg_hint_type user_reg_hint_type); + +/** * regulatory_set_wiphy_regd - set regdom info for self managed drivers * @wiphy: the wireless device we want to process the regulatory domain on * @rd: the regulatory domain informatoin to use for this wiphy @@ -6204,6 +6231,16 @@ void cfg80211_nan_func_terminated(struct wireless_dev *wdev, /* ethtool helper */ void cfg80211_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info); +/** + * cfg80211_is_gratuitous_arp_unsolicited_na - packet is grat. ARP/unsol. NA + * @skb: the input packet, must be an ethernet frame already + * + * Return: %true if the packet is a gratuitous ARP or unsolicited NA packet. + * This is used to drop packets that shouldn't occur because the AP implements + * a proxy service. + */ +bool cfg80211_is_gratuitous_arp_unsolicited_na(struct sk_buff *skb); + /* Logging, debugging and troubleshooting/diagnostic helpers. */ /* wiphy_printk helpers, similar to dev_printk */ diff --git a/include/soc/imx/fsl_hvc.h b/include/soc/imx/fsl_hvc.h new file mode 100644 index 000000000000..63e3cc5a3f2a --- /dev/null +++ b/include/soc/imx/fsl_hvc.h @@ -0,0 +1,15 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SOC_FSL_HVC_H +#define __SOC_FSL_HVC_H + +/* VENDOR HVC 0xC6000000 - 0xC600FFFF */ +#define FSL_HVC_SC 0xC6000000 + +#endif diff --git a/include/soc/imx/fsl_sip.h b/include/soc/imx/fsl_sip.h new file mode 100644 index 000000000000..1fe8f286b13c --- /dev/null +++ b/include/soc/imx/fsl_sip.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SOC_FSL_SIP_H +#define __SOC_FSL_SIP_H + +/* SIP 0xC2000000 - 0xC200FFFF */ +#define FSL_SIP_GPC 0xC2000000 +#define FSL_SIP_CONFIG_GPC_MASK 0x00 +#define FSL_SIP_CONFIG_GPC_UNMASK 0x01 +#define FSL_SIP_CONFIG_GPC_SET_WAKE 0x02 +#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 +#define FSL_SIP_CONFIG_GPC_CORE_WAKE 0x05 + +#define FSL_SIP_CPUFREQ 0xC2000001 +#define FSL_SIP_SET_CPUFREQ 0x00 + +#define FSL_SIP_SRTC 0xC2000002 +#define FSL_SIP_SRTC_SET_TIME 0x00 +#define FSL_SIP_SRTC_START_WDOG 0x01 +#define FSL_SIP_SRTC_STOP_WDOG 0x02 +#define FSL_SIP_SRTC_SET_WDOG_ACT 0x03 +#define FSL_SIP_SRTC_PING_WDOG 0x04 +#define FSL_SIP_SRTC_SET_TIMEOUT_WDOG 0x05 +#define FSL_SIP_SRTC_GET_WDOG_STAT 0x06 +#define FSL_SIP_SRTC_SET_PRETIME_WDOG 0x07 + +#define FSL_SIP_DDR_DVFS 0xc2000004 + +#define IMX8MQ_PD_MIPI 0 +#define IMX8MQ_PD_PCIE1 1 +#define IMX8MQ_PD_OTG1 2 +#define IMX8MQ_PD_OTG2 3 +#define IMX8MQ_PD_GPU 4 +#define IMX8MQ_PD_VPU 5 +#define IMX8MQ_PD_HDMI 6 +#define IMX8MQ_PD_DISP 7 +#define IMX8MQ_PD_MIPI_CSI1 8 +#define IMX8MQ_PD_MIPI_CSI2 9 +#define IMX8MQ_PD_PCIE2 10 + +#define FSL_SIP_DDR_DVFS 0xc2000004 + +#define FSL_SIP_SRC 0xc2000005 +#define FSL_SIP_SRC_M4_START 0x00 +#define FSL_SIP_SRC_M4_STARTED 0x01 + +#define FSL_SIP_GET_SOC_INFO 0xc2000006 + +#define FSL_SIP_NOC 0xc2000008 +#define FSL_SIP_NOC_LCDIF 0x0 +#define FSL_SIP_NOC_PRIORITY 0x1 +#define NOC_GPU_PRIORITY 0x10 +#define NOC_DCSS_PRIORITY 0x11 +#define NOC_VPU_PRIORITY 0x12 +#define NOC_CPU_PRIORITY 0x13 +#define NOC_MIX_PRIORITY 0x14 + +#define FSL_SIP_WAKEUP_SRC 0xc2000009 +#define FSL_SIP_WAKEUP_SRC_SCU 0x1 +#define FSL_SIP_WAKEUP_SRC_IRQSTEER 0x2 + +#endif diff --git a/include/soc/imx/gpc.h b/include/soc/imx/gpc.h new file mode 100644 index 000000000000..6a976e6aa3fe --- /dev/null +++ b/include/soc/imx/gpc.h @@ -0,0 +1,7 @@ +#ifndef __SOC_IMX_GPC_H +#define __SOC_IMX_GPC_H + +void imx_gpc_hold_m4_in_sleep(void); +void imx_gpc_release_m4_in_sleep(void); + +#endif /* __SOC_IMX_GPC_H */ diff --git a/include/soc/imx/src.h b/include/soc/imx/src.h new file mode 100644 index 000000000000..c55c34cd2366 --- /dev/null +++ b/include/soc/imx/src.h @@ -0,0 +1,6 @@ +#ifndef __SOC_IMX_SRC_H +#define __SOC_IMX_SRC_H + +bool imx_src_is_m4_enabled(void); + +#endif /* __SOC_IMX_SRC_H */ diff --git a/include/soc/imx8/fsl_bitaccess.h b/include/soc/imx8/fsl_bitaccess.h new file mode 100644 index 000000000000..11e71eeb411b --- /dev/null +++ b/include/soc/imx8/fsl_bitaccess.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*! + * @file devices/MX8/include/fsl_bitaccess.h + * + * Header file containing register access macros. + * + * \addtogroup Peripheral_access_layer (HAL) Device Peripheral Access Layer + * + * @{ + */ + +#ifndef _FSL_BITACCESS_H +#define _FSL_BITACCESS_H 1 + +/*! + * @addtogroup SCF Register Access Macros + * @{ + */ + +/* + * Macros for single instance registers + */ + +#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) +#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) +#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) + +#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) +#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) +#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) + +#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BF_RD(reg, field) HW_##reg.B.field +#define BF_WR(reg, field, v) BW_##reg##_##field(v) + + +/******************************************************************************* + * Macros to create bitfield mask, shift, and width from CMSIS definitions + ******************************************************************************/ + +/* Bitfield Mask */ +#define SCF_BMSK(bit) (bit ## _MASK) + +/* Bitfield Left Shift */ +#define SCF_BLSH(bit) (bit ## _SHIFT) + +/* Bitfield Width */ +#define SCF_BWID(bit) (bit ## _WIDTH) + +/* Bitfield Value */ +#define SCF_BVAL(bit, val) ((val) << (SCF_BLSH(bit))) + + +/******************************************************************************* + * Macros to set, clear, extact, and insert bitfields into register structures + * or local variables + ******************************************************************************/ + +/* Bitfield Set */ +#define SCF_BSET(var, bit) (var |= (SCF_BMSK(bit))) + +/* Bitfield Clear */ +#define SCF_BCLR(var, bit) (var &= (~(SCF_BMSK(bit)))) + +/* Bitfield Extract */ +#define SCF_BEXR(var, bit) ((var & (SCF_BMSK(bit))) >> (SCF_BLSH(bit))) + +/* Bitfield Insert */ +#define SCF_BINS(var, bit, val) (var = (var & (~(SCF_BMSK(bit)))) | SCF_BVAL(bit, val)) + + +/******************************************************************************* + * Macros to set, clear, extact, and insert bitfields into register structures + * that support SCT + ******************************************************************************/ + +#ifdef EMUL +/* Emulation does not have SCT hardware and must fallback to non-SCT definitions */ + +/* SCT Bitfield Set */ +#define SCF_SCT_BSET(var, bit) (SCF_BSET(var, bit)) + +/* SCT Bitfield Clear */ +#define SCF_SCT_BCLR(var, bit) (SCF_BCLR(var, bit)) + +/* SCT Bitfield Insert */ +#define SCF_SCT_BINS(var, bit, val) (SCF_BINS(var, bit, val)) + +#else +/*! @todo Port macros leverage SCT register access hardware */ + +/* SCT Bitfield Set */ +#define SCF_SCT_BSET(var, bit) (SCF_BSET(var, bit)) + +/* SCT Bitfield Clear */ +#define SCF_SCT_BCLR(var, bit) (SCF_BCLR(var, bit)) + +/* SCT Bitfield Insert */ +#define SCF_SCT_BINS(var, bit, val) (SCF_BINS(var, bit, val)) + +#endif /* EMUL */ + +/*! + * @} + */ /* end of group SCF */ + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + +#endif /* _FSL_BITACCESS_H */ + +/******************************************************************************/ diff --git a/include/soc/imx8/imx-secvio-sc.h b/include/soc/imx8/imx-secvio-sc.h new file mode 100644 index 000000000000..ff419ad512d1 --- /dev/null +++ b/include/soc/imx8/imx-secvio-sc.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright 2019 NXP */ + +#ifndef _MISC_IMX_SECVIO_SC_H_ +#define _MISC_IMX_SECVIO_SC_H_ + +#define HPSVS__LP_SEC_VIO__MASK BIT(31) +#define HPSVS__SW_LPSV__MASK BIT(15) +#define HPSVS__SW_FSV__MASK BIT(14) +#define HPSVS__SW_SV__MASK BIT(13) +#define HPSVS__SV5__MASK BIT(5) +#define HPSVS__SV4__MASK BIT(4) +#define HPSVS__SV3__MASK BIT(3) +#define HPSVS__SV2__MASK BIT(2) +#define HPSVS__SV1__MASK BIT(1) +#define HPSVS__SV0__MASK BIT(0) + +#define HPSVS__ALL_SV__MASK (HPSVS__LP_SEC_VIO__MASK | \ + HPSVS__SW_LPSV__MASK | \ + HPSVS__SW_FSV__MASK | \ + HPSVS__SW_SV__MASK | \ + HPSVS__SV5__MASK | \ + HPSVS__SV4__MASK | \ + HPSVS__SV3__MASK | \ + HPSVS__SV2__MASK | \ + HPSVS__SV1__MASK | \ + HPSVS__SV0__MASK) + +#define LPS__ESVD__MASK BIT(16) +#define LPS__ET2D__MASK BIT(10) +#define LPS__ET1D__MASK BIT(9) +#define LPS__WMT2D__MASK BIT(8) +#define LPS__WMT1D__MASK BIT(7) +#define LPS__VTD__MASK BIT(6) +#define LPS__TTD__MASK BIT(5) +#define LPS__CTD__MASK BIT(4) +#define LPS__PGD__MASK BIT(3) +#define LPS__MCR__MASK BIT(2) +#define LPS__SRTCR__MASK BIT(1) +#define LPS__LPTA__MASK BIT(0) + +#define LPS__ALL_TP__MASK (LPS__ESVD__MASK | \ + LPS__ET2D__MASK | \ + LPS__ET1D__MASK | \ + LPS__WMT2D__MASK | \ + LPS__WMT1D__MASK | \ + LPS__VTD__MASK | \ + LPS__TTD__MASK | \ + LPS__CTD__MASK | \ + LPS__PGD__MASK | \ + LPS__MCR__MASK | \ + LPS__SRTCR__MASK | \ + LPS__LPTA__MASK) + +#define LPTDS__ET10D__MASK BIT(7) +#define LPTDS__ET9D__MASK BIT(6) +#define LPTDS__ET8D__MASK BIT(5) +#define LPTDS__ET7D__MASK BIT(4) +#define LPTDS__ET6D__MASK BIT(3) +#define LPTDS__ET5D__MASK BIT(2) +#define LPTDS__ET4D__MASK BIT(1) +#define LPTDS__ET3D__MASK BIT(0) + +#define LPTDS__ALL_TP__MASK (LPTDS__ET10D__MASK | \ + LPTDS__ET9D__MASK | \ + LPTDS__ET8D__MASK | \ + LPTDS__ET7D__MASK | \ + LPTDS__ET6D__MASK | \ + LPTDS__ET5D__MASK | \ + LPTDS__ET4D__MASK | \ + LPTDS__ET3D__MASK) + +/* Struct for notification */ +struct notifier_info { + u32 sv_status; /* From HPSVS */ + u32 tp_status_1; /* From LPS */ + u32 tp_status_2; /* From LPTDS */ +}; + +int register_imx_secvio_sc_notifier(struct notifier_block *nb); +int unregister_imx_secvio_sc_notifier(struct notifier_block *nb); + +#endif /* _MISC_IMX_SECVIO_SC_H_ */ diff --git a/include/soc/imx8/imx8qm/lpcg.h b/include/soc/imx8/imx8qm/lpcg.h new file mode 100644 index 000000000000..220f23369326 --- /dev/null +++ b/include/soc/imx8/imx8qm/lpcg.h @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_1_LPCG 0x5AC90000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_4_LPCG 0x5AC40000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define EMVSIM_1_LPCG 0x5A4E0000 +#define EMVSIM_0_LPCG 0x5A4D0000 +#define LPUART_4_LPCG 0x5A4A0000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* MIPI DSI SS */ +#define MIPI_DSI_0_LPCG 0x56223000 +#define MIPI_DSI_1_LPCG 0x57223000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SPDIF_1_LPCG 0x59430000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000 +#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_ESAI_1_LPCG 0x59c10000 +#define AUD_SAI_6_LPCG 0x59c20000 +#define AUD_SAI_7_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +/* CM41 SS */ +#define CM41_I2C_LPCG 0x3B630000 + +#endif diff --git a/include/soc/imx8/imx8qxp/lpcg.h b/include/soc/imx8/imx8qxp/lpcg.h new file mode 100644 index 000000000000..79b774d825ba --- /dev/null +++ b/include/soc/imx8/imx8qxp/lpcg.h @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define ROMCP_LPCG 0x5D500000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define PWM_LPCG 0x5A590000 +#define LCD_LPCG 0x5A580000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* PARALLEL CSI SS */ +#define PARALLEL_CSI_LPCG 0x58263000 + +/* Display MIPI SS */ +#define DI_MIPI0_LPCG 0x56223000 +#define DI_MIPI1_LPCG 0x56243000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_SAI_4_LPCG 0x59c20000 +#define AUD_SAI_5_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + + +#endif diff --git a/include/soc/imx8/sc/ipc.h b/include/soc/imx8/sc/ipc.h new file mode 100644 index 000000000000..de55ce73fbeb --- /dev/null +++ b/include/soc/imx8/sc/ipc.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file for the IPC implementation. + */ + +#ifndef SC_IPC_H +#define SC_IPC_H + +/* Includes */ + +#include <linux/thermal.h> +#include <soc/imx8/sc/types.h> + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * This function opens an IPC channel. + * + * @param[out] ipc return pointer for ipc handle + * @param[in] id id of channel to open + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC + * otherwise). + * + * The \a id parameter is implementation specific. Could be an MU + * address, pointer to a driver path, channel index, etc. + */ +sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id); + +/*! + * This function closes an IPC channel. + * + * @param[in] ipc id of channel to close + */ +void sc_ipc_close(sc_ipc_t ipc); + +/*! + * This function reads a message from an IPC channel. + * + * @param[in] ipc id of channel read from + * @param[out] data pointer to message buffer to read + * + * This function will block if no message is available to be read. + */ +void sc_ipc_read(sc_ipc_t ipc, void *data); + +/*! + * This function writes a message to an IPC channel. + * + * @param[in] ipc id of channel to write to + * @param[in] data pointer to message buffer to write + * + * This function will block if the outgoing buffer is full. + */ +void sc_ipc_write(sc_ipc_t ipc, const void *data); + +int register_scu_notifier(struct notifier_block *nb); +int unregister_scu_notifier(struct notifier_block *nb); + +#endif /* SC_IPC_H */ + diff --git a/include/soc/imx8/sc/scfw.h b/include/soc/imx8/sc/scfw.h new file mode 100644 index 000000000000..3c77c69f7f89 --- /dev/null +++ b/include/soc/imx8/sc/scfw.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_SCFW_H +#define _SC_SCFW_H + +#include <linux/types.h> + +/*! + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef uint32_t sc_ipc_t; + +/*! + * This type is used to declare an ID for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef uint32_t sc_ipc_id_t; + +/*! + * This function returns the MU channel ID for this implementation + * + * @param[in] ipc pointer to Mu channel ID + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC + * otherwise). + */ +int sc_ipc_getMuID(uint32_t *mu_id); + +#endif diff --git a/include/soc/imx8/sc/sci.h b/include/soc/imx8/sc/sci.h new file mode 100644 index 000000000000..004ad078091f --- /dev/null +++ b/include/soc/imx8/sc/sci.h @@ -0,0 +1,42 @@ +/*==========================================================================*/ +/*! + * @file sci.h + * + * Header file containing the public System Controller Interface (SCI) + * definitions. + * + * + * @{ + */ +/*==========================================================================*/ + +#ifndef _SC_SCI_H +#define _SC_SCI_H + +/* Defines */ + +#define SC_NUM_IPC 5 + +/* Includes */ + +#include <soc/imx8/sc/ipc.h> +#include <soc/imx8/sc/svc/misc/api.h> +#include <soc/imx8/sc/svc/pad/api.h> +#include <soc/imx8/sc/svc/pm/api.h> +#include <soc/imx8/sc/svc/rm/api.h> +#include <soc/imx8/sc/svc/timer/api.h> + +/* Types */ + +/* Functions */ +/*! + * This function initializes the MU connection to SCU. + * + * @return Returns an error code. + */ +int imx8_mu_init(void); + +#endif /* _SC_SCI_H */ + +/**@}*/ + diff --git a/include/soc/imx8/sc/svc/irq/api.h b/include/soc/imx8/sc/svc/irq/api.h new file mode 100644 index 000000000000..a2c8b043c3f6 --- /dev/null +++ b/include/soc/imx8/sc/svc/irq/api.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Interrupt (IRQ) function. + * + * @addtogroup IRQ_SVC IRQ: Interrupt Service + * + * Module for the Interrupt (IRQ) service. + * + * @{ + */ + +#ifndef SC_IRQ_API_H +#define SC_IRQ_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> + +/* Defines */ + +#define SC_IRQ_NUM_GROUP 7U /* Number of groups */ + +/*! + * @name Defines for sc_irq_group_t + */ +/*@{*/ +#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */ +#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */ +#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */ +#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */ +#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */ +#define SC_IRQ_GROUP_REBOOTED 5U /* Partition reboot complete */ +#define SC_IRQ_GROUP_REBOOT 6U /* Partition reboot starting */ +/*@}*/ + +/*! + * @name Defines for sc_irq_temp_t + */ +/*@{*/ +#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_wdog_t + */ +/*@{*/ +#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_rtc_t + */ +/*@{*/ +#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */ +/*@}*/ + +/*! + * @name Defines for sc_irq_wake_t + */ +/*@{*/ +#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */ +#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */ +#define SC_IRQ_USR1 (1U << 2U) /* User defined 1 */ +#define SC_IRQ_USR2 (1U << 3U) /* User defined 2 */ +#define SC_IRQ_BC_PAD (1U << 4U) /* Pad wakeup (broadcast to all partitions) */ +#define SC_IRQ_SW_WAKE (1U << 5U) /* Software requested wake */ +#define SC_IRQ_SECVIO (1U << 6U) /* Security violation */ +/*@}*/ + +/*! + * @name Defines for sc_irq_sysctr_t + */ +/*@{*/ +#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare an interrupt group. + */ +typedef uint8_t sc_irq_group_t; + +/*! + * This type is used to declare a bit mask of temp interrupts. + */ +typedef uint8_t sc_irq_temp_t; + +/*! + * This type is used to declare a bit mask of watchdog interrupts. + */ +typedef uint8_t sc_irq_wdog_t; + +/*! + * This type is used to declare a bit mask of RTC interrupts. + */ +typedef uint8_t sc_irq_rtc_t; + +/*! + * This type is used to declare a bit mask of wakeup interrupts. + */ +typedef uint8_t sc_irq_wake_t; + +/* Functions */ + +/*! + * This function enables/disables interrupts. If pending interrupts + * are unmasked, an interrupt will be triggered. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group group the interrupts are in + * @param[in] mask mask of interrupts to affect + * @param[in] enable state to change interrupts to + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + */ +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable); + +/*! + * This function returns the current interrupt status (regardless if + * masked). Automatically clears pending interrupts. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group groups the interrupts are in + * @param[in] status status of interrupts + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + * + * The returned \a status may show interrupts pending that are + * currently masked. + */ +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status); + +#endif /* SC_IRQ_API_H */ + +/**@}*/ diff --git a/include/soc/imx8/sc/svc/misc/api.h b/include/soc/imx8/sc/svc/misc/api.h new file mode 100644 index 000000000000..35d876fa99f1 --- /dev/null +++ b/include/soc/imx8/sc/svc/misc/api.h @@ -0,0 +1,463 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Miscellaneous (MISC) function. + * + * @addtogroup MISC_SVC MISC: Miscellaneous Service + * + * Module for the Miscellaneous (MISC) service. + * + * @{ + */ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> +#include <soc/imx8/sc/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */ +/*@}*/ + +/*! Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U + +/*! + * @name Defines for sc_misc_boot_status_t + */ +/*@{*/ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ +/*@}*/ + +/*! + * @name Defines for sc_misc_temp_t + */ +/*@{*/ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ +/*@}*/ + +/*! + * @name Defines for sc_misc_bt_t + */ +/*@{*/ +#define SC_MISC_BT_PRIMARY 0U /* Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /* Serial boot */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to store a DMA channel priority group. + */ +typedef uint8_t sc_misc_dma_group_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_boot_status_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_temp_t; + +/*! + * This type is used report the boot type. + */ +typedef uint8_t sc_misc_bt_t; + +/* Functions */ + +/*! + * @name Control Functions + * @{ + */ + +/*! + * This function sets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to change + * @param[in] val value to apply to the control + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val); + +/*! + * This function gets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to get + * @param[out] val pointer to return the control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val); + +/* @} */ + +/*! + * @name DMA Functions + * @{ + */ + +/*! + * This function configures the max DMA channel priority group for a + * partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a max + * @param[in] max max priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent + * of the affected partition + * + * Valid \a max range is 0-31 with 0 being the lowest and 31 the highest. + * Default is the max priority group for the parent partition of \a pt. + */ +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_misc_dma_group_t max); + +/*! + * This function configures the priority group for a DMA channel. + * + * @param[in] ipc IPC handle + * @param[in] resource DMA channel resource + * @param[in] group priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the DMA channel + * + * Valid \a group range is 0-31 with 0 being the lowest and 31 the highest. + * The max value of \a group is limited by the partition max set using + * sc_misc_set_max_dma_group(). + */ +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_dma_group_t group); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used output a debug character from the SCU UART. + * + * @param[in] ipc IPC handle + * @param[in] ch character to output + */ +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch); + +/*! + * This function starts/stops emulation waveform capture. + * + * @param[in] ipc IPC handle + * @param[in] enable flag to enable/disable capture + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_UNAVAILABLE if not running on emulation + */ +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable); + +/*! + * This function is used to return the SCFW build info. + * + * @param[in] ipc IPC handle + * @param[out] build pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit); + +/*! + * This function is used to return the SCFW API versions. + * + * @param[in] ipc IPC handle + * @param[out] cl_maj pointer to return major part of client version + * @param[out] cl_min pointer to return minor part of client version + * @param[out] sv_maj pointer to return major part of SCFW version + * @param[out] sv_min pointer to return minor part of SCFW version + * + * Client verion is the version of the API ported to and used by the caller. + * SCFW version is the version of the SCFW binary running on the CPU. + * + * Note a major version difference indicates a break in compatibility. + */ +void sc_misc_api_ver(sc_ipc_t ipc, uint16_t *cl_maj, + uint16_t *cl_min, uint16_t *sv_maj, uint16_t *sv_min); + +/*! + * This function is used to return the device's unique ID. + * + * @param[in] ipc IPC handle + * @param[out] id_l pointer to return lower 32-bit of ID [31:0] + * @param[out] id_h pointer to return upper 32-bits of ID [63:32] + */ +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h); + +/* @} */ + +/*! + * @name Other Functions + * @{ + */ + +/*! + * This function configures the ARI match value for PCIe/SATA resources. + * + * @param[in] ipc IPC handle + * @param[in] resource match resource + * @param[in] resource_mst PCIe/SATA master to match + * @param[in] ari ARI to match + * @param[in] enable enable match or not + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the resource and translation + * + * For PCIe, the ARI is the 16-bit value that includes the bus number, + * device number, and function number. For SATA, this value includes the + * FISType and PM_Port. + */ +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, + sc_bool_t enable); + +/*! + * This function reports boot status. + * + * @param[in] ipc IPC handle + * @param[in] status boot status + * + * This is used by SW partitions to report status of boot. This is + * normally used to report a boot failure. + */ +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); + +/*! + * This function tells the SCFW that a CPU is done booting. + * + * @param[in] ipc IPC handle + * @param[in] cpu CPU that is done booting + * + * This is called by early booting CPUs to report they are done with + * initialization. After starting early CPUs, the SCFW halts the + * booting process until they are done. During this time, early + * CPUs can call the SCFW with lower latency as the SCFW is idle. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the CPU owner + */ +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu); + +/*! + * This function reads a given fuse word index. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[out] val fuse read value + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if read operation failed + * - SC_ERR_LOCKED if read operation is locked + */ +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val); + +/*! + * This function writes a given fuse word index. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[in] val fuse write value + * + * The command is passed as is to SECO. SECO uses part of the + * \a word parameter to indicate if the fuse should be locked + * after programming. See the "Write common fuse" section of + * the SECO API Reference Guide for more info. + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * - SC_ERR_NOACCESS if write operation failed + * - SC_ERR_LOCKED if write operation is locked + */ +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val); + +/*! + * This function sets a temp sensor alarm. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp alarm to set + * @param[in] celsius whole part of temp to set + * @param[in] tenths fractional part of temp to set + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * This function will enable the alarm interrupt if the temp requested is + * not the min/max temp. This enable automatically clears when the alarm + * occurs and this function has to be called again to re-enable. + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + * - SC_ERR_NOACCESS if caller does not own the resource + * - SC_ERR_NOPOWER if power domain of resource not powered + */ +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths); + +/*! + * This function gets a temp sensor value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp value to get (sensor or alarm) + * @param[out] celsius whole part of temp to get + * @param[out] tenths fractional part of temp to get + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + * - SC_ERR_BUSY if temp not ready yet (time delay after power on) + * - SC_ERR_NOPOWER if power domain of resource not powered + */ +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, + int8_t *tenths); + +/*! + * This function returns the boot device. + * + * @param[in] ipc IPC handle + * @param[out] dev pointer to return boot device + */ +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev); + +/*! + * This function returns the boot type. + * + * @param[in] ipc IPC handle + * @param[out] type pointer to return boot type + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors code: + * - SC_ERR_UNAVAILABLE if type not passed by ROM + */ +sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type); + +/*! + * This function returns the boot container index. + * + * @param[in] ipc IPC handle + * @param[out] idx pointer to return index + * + * Return \a idx = 1 for first container, 2 for second. + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors code: + * - SC_ERR_UNAVAILABLE if index not passed by ROM + */ +sc_err_t sc_misc_get_boot_container(sc_ipc_t ipc, uint8_t *idx); + +/*! + * This function returns the current status of the ON/OFF button. + * + * @param[in] ipc IPC handle + * @param[out] status pointer to return button status + */ +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); + +/*! + * This function returns the ROM patch checksum. + * + * @param[in] ipc IPC handle + * @param[out] checksum pointer to return checksum + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum); + +/*! + * This function calls the board IOCTL function. + * + * @param[in] ipc IPC handle + * @param[in,out] parm1 pointer to pass parameter 1 + * @param[in,out] parm2 pointer to pass parameter 2 + * @param[in,out] parm3 pointer to pass parameter 3 + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3); + +/* @} */ + +#endif /* SC_MISC_API_H */ + +/**@}*/ diff --git a/include/soc/imx8/sc/svc/pad/api.h b/include/soc/imx8/sc/svc/pad/api.h new file mode 100644 index 000000000000..1baaeea22737 --- /dev/null +++ b/include/soc/imx8/sc/svc/pad/api.h @@ -0,0 +1,576 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Pad Control (PAD) function. + * + * @addtogroup PAD_SVC PAD: Pad Service + * + * Module for the Pad Control (PAD) service. + * + * @details + * + * Pad configuration is managed by SC firmware. The pad configuration + * features supported by the SC firmware include: + * + * - Configuring the mux, input/output connection, and low-power isolation + mode. + * - Configuring the technology-specific pad setting such as drive strength, + * pullup/pulldown, etc. + * - Configuring compensation for pad groups with dual voltage capability. + * + * Pad functions fall into one of three categories. Generic functions are + * common to all SoCs and all process technologies. SoC functions are raw + * low-level functions. Technology-specific functions are specific to the + * process technology. + * + * The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS) + * for valid pad values. Note that all pads exist on a die but may or + * may not be brought out by the specific package. Mapping of pads to + * package pins/balls is documented in the associated Data Sheet. Some pads + * may not be brought out because the part (die+package) is defeatured and + * some pads may connect to the substrate in the package. + * + * Some pads (SC_P_COMP_*) that can be specified are not individual pads + * but are in fact pad groups. These groups have additional configuration + * that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More + * info on these can be found in the associated Reference Manual. + * + * Pads are managed as a resource by the Resource Manager (RM). They have + * assigned owners and only the owners can configure the pads. Some of the + * pads are reserved for use by the SCFW itself and this can be overriden + * with the implementation of board_config_sc(). Additionally, pads may + * be assigned to various other partitions via the implementation of + * board_system_config(). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * @includedoc pad/details.dox + * + * @{ + */ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> +#include <soc/imx8/sc/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_PAD_MUX_W 3U /* Width of mux parameter */ +/*@}*/ + +/*! + * @name Defines for sc_pad_config_t + */ +/*@{*/ +#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ +#define SC_PAD_CONFIG_OD 1U /* Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ +/*@}*/ + +/*! + * @name Defines for sc_pad_iso_t + */ +/*@{*/ +#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_dse_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed drive strength for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength for dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength for dual volt */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_ps_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ +/*@}*/ + +/*! + * @name Defines for sc_pad_28fdsoi_pus_t + */ +/*@{*/ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ +/*@}*/ + +/*! + * @name Defines for sc_pad_wakeup_t + */ +/*@{*/ +#define SC_PAD_WAKEUP_OFF 0U /* Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a pad config. It determines how the + * output data is driven, pull-up is controlled, and input signal is + * connected. Normal and OD are typical and only connect the input + * when the output is not driven. The IN options are less common and + * force an input connection even when driving the output. + */ +typedef uint8_t sc_pad_config_t; + +/*! + * This type is used to declare a pad low-power isolation config. + * ISO_LATE is the most common setting. ISO_EARLY is only used when + * an output pad is directly determined by another input pad. The + * other two are only used when SW wants to directly contol isolation. + */ +typedef uint8_t sc_pad_iso_t; + +/*! + * This type is used to declare a drive strength. Note it is specific + * to 28FDSOI. Also note that valid values depend on the pad type. + */ +typedef uint8_t sc_pad_28fdsoi_dse_t; + +/*! + * This type is used to declare a pull select. Note it is specific + * to 28FDSOI. + */ +typedef uint8_t sc_pad_28fdsoi_ps_t; + +/*! + * This type is used to declare a pull-up select. Note it is specific + * to 28FDSOI HSIC pads. + */ +typedef uint8_t sc_pad_28fdsoi_pus_t; + +/*! + * This type is used to declare a wakeup mode of a pad. + */ +typedef uint8_t sc_pad_wakeup_t; + +/* Functions */ + +/*! + * @name Generic Functions + * @{ + */ + +/*! + * This function configures the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso); + +/*! + * This function gets the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *mux, sc_pad_config_t *config, + sc_pad_iso_t *iso); + +/*! + * This function configures the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] ctrl control value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl); + +/*! + * This function gets the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] ctrl pointer to return control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl); + +/*! + * This function configures the wakeup mode of the pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] wakeup wakeup to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup); + +/*! + * This function gets the wakeup mode of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] wakeup pointer to return wakeup + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup); + +/*! + * This function configures a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * @param[in] ctrl control value + * @param[in] wakeup wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup); + +/*! + * This function gets a pad's config. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * @param[out] ctrl pointer to return control value + * @param[out] wakeup pointer to return wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, + uint32_t *ctrl, sc_pad_wakeup_t *wakeup); + +/* @} */ + +/*! + * @name SoC Specific Functions + * @{ + */ + +/*! + * This function configures the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] val value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val); + +/*! + * This function gets the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] val pointer to return setting + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); + +/* @} */ + +/*! + * @name Technology Specific Functions + * @{ + */ + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] ps pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, + sc_pad_28fdsoi_ps_t ps); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] ps pointer to return pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, + sc_pad_28fdsoi_ps_t *ps); + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] hys hysteresis + * @param[in] pus pull-up select + * @param[in] pke pull keeper enable + * @param[in] pue pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, + sc_pad_28fdsoi_pus_t pus, sc_bool_t pke, + sc_bool_t pue); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] hys pointer to return hysteresis + * @param[out] pus pointer to return pull-up select + * @param[out] pke pointer to return pull keeper enable + * @param[out] pue pointer to return pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, + sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke, + sc_bool_t *pue); + +/*! + * This function configures the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] compen compensation/freeze mode + * @param[in] fastfrz fast freeze + * @param[in] rasrcp compensation code for PMOS + * @param[in] rasrcn compensation code for NMOS + * @param[in] nasrc_sel NASRC read select + * @param[in] psw_ovr 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + * + * Note \a psw_ovr is only applicable to pads supporting 2.5 volt + * operation (e.g. some Ethernet pads). + */ +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, + uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr); + +/*! + * This function gets the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] compen pointer to return compensation/freeze mode + * @param[out] fastfrz pointer to return fast freeze + * @param[out] rasrcp pointer to return compensation code for PMOS + * @param[out] rasrcn pointer to return compensation code for NMOS + * @param[out] nasrc_sel pointer to return NASRC read select + * @param[out] compok pointer to return compensation status + * @param[out] nasrc pointer to return NASRCP/NASRCN + * @param[out] psw_ovr pointer to return the 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_UNAVAILABLE if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, + uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, + uint8_t *nasrc, sc_bool_t *psw_ovr); + +/* @} */ + +#endif /* SC_PAD_API_H */ + +/**@}*/ diff --git a/include/soc/imx8/sc/svc/pm/api.h b/include/soc/imx8/sc/svc/pm/api.h new file mode 100644 index 000000000000..34990fac3ee5 --- /dev/null +++ b/include/soc/imx8/sc/svc/pm/api.h @@ -0,0 +1,875 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Power Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * @addtogroup PM_SVC PM: Power Management Service + * + * Module for the Power Management (PM) service. + * + * @includedoc pm/details.dox + * + * @{ + */ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> +#include <soc/imx8/sc/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ +/*@}*/ + +/*! + * @name Defines for clock indexes (sc_pm_clk_t) + */ +/*@{*/ +/*@}*/ + +/*! + * @name Defines for ALL parameters + */ +/*@{*/ +#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */ +/*@}*/ + +/*! + * @name Defines for sc_pm_power_mode_t + */ +/*@{*/ +#define SC_PM_PW_MODE_OFF 0U /* Power off */ +#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ +#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /* Power on */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_t + */ +/*@{*/ +#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ +#define SC_PM_CLK_PER 2U /* Peripheral clock */ +#define SC_PM_CLK_PHY 3U /* Phy clock */ +#define SC_PM_CLK_MISC 4U /* Misc clock */ +#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /* CPU clock */ +#define SC_PM_CLK_PLL 4U /* PLL */ +#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_mode_t + */ +/*@{*/ +#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM */ +#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_parent_t + */ +/*@{*/ +#define SC_PM_PARENT_XTAL 0U /* Parent is XTAL */ +#define SC_PM_PARENT_PLL0 1U /* Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /* Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /* Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /* Parent is a bypass clock. */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_type_t + */ +/*@{*/ +#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_reason_t + */ +/*@{*/ +#define SC_PM_RESET_REASON_POR 0U /* Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /* Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ +/*@}*/ + +/*! + * @name Defines for sc_pm_sys_if_t + */ +/*@{*/ +#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ +#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /* DDR memory */ +/*@}*/ + +/*! + * @name Defines for sc_pm_wake_src_t + */ +/*@{*/ +#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ +typedef uint8_t sc_pm_power_mode_t; + +/*! + * This type is used to declare a clock. + */ +typedef uint8_t sc_pm_clk_t; + +/*! + * This type is used to declare a clock mode. + */ +typedef uint8_t sc_pm_clk_mode_t; + +/*! + * This type is used to declare the clock parent. + */ +typedef uint8_t sc_pm_clk_parent_t; + +/*! + * This type is used to declare clock rates. + */ +typedef uint32_t sc_pm_clock_rate_t; + +/*! + * This type is used to declare a desired reset type. + */ +typedef uint8_t sc_pm_reset_type_t; + +/*! + * This type is used to declare a reason for a reset. + */ +typedef uint8_t sc_pm_reset_reason_t; + +/*! + * This type is used to specify a system-level interface to be power managed. + */ +typedef uint8_t sc_pm_sys_if_t; + +/*! + * This type is used to specify a wake source for CPU resources. + */ +typedef uint8_t sc_pm_wake_src_t; + +/* Functions */ + +/*! + * @name Power Functions + * @{ + */ + +/*! + * This function sets the system power mode. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid mode, + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * + * @see sc_pm_set_sys_power_mode(). + */ +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode); + +/*! + * This function sets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or mode, + * - SC_ERR_NOACCESS if caller's partition is not the owner or + * parent of \a pt + * + * The power mode of the partitions is a max power any resource will + * be set to. Calling this will result in all resources owned + * by \a pt to have their power changed to the lower of \a mode or the + * individual resource mode set using sc_pm_set_resource_power_mode(). + */ +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode); + +/*! + * This function gets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode); + +/*! + * This function sends a wake interrupt to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to wake + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * An SC_IRQ_SW_WAKE interrupt is sent to all MUs owned by the + * partition that have this interrupt enabled. The CPU using an + * MU will exit a low-power state to service the MU interrupt. + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +sc_err_t sc_pm_partition_wake(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function sets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or mode, + * - SC_ERR_PARM if resource is the MU used to make the call, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner + * + * Resources must be at SC_PM_PW_MODE_LP mode or higher to access them, + * otherwise the master will get a bus error or hang. + * + * This function will record the individual resource power mode + * and change it if the requested mode is lower than or equal to the + * partition power mode set with sc_pm_set_partition_power_mode(). + * In other words, the power mode of the resource will be the minimum + * of the resource power mode and the partition power mode. + * + * Note some resources are still not accessible even when powered up if bus + * transactions go through a fabric not powered up. Examples of this are + * resources in display and capture subsystems which require the display + * controller or the imaging subsytem to be powered up first. + * + * Not that resources are grouped into power domains by the underlying + * hardware. If any resource in the domain is on, the entire power domain + * will be on. Other power domains required to access the resource will + * also be turned on. Clocks required to access the peripheral will be + * turned on. Refer to the SoC RM for more info on power domains and access + * infrastructure (bus fabrics, clock domains, etc.). + */ +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! +* This function sets the power mode for all the resources owned +* by a child partition. +* +* @param[in] ipc IPC handle +* @param[in] pt handle of child partition +* @param[in] mode power mode to apply +* @param[in] exclude resource to exclude +* +* @return Returns an error code (SC_ERR_NONE = success). +* +* Return errors: +* - SC_ERR_PARM if invalid partition or mode, +* - SC_ERR_NOACCESS if caller's partition is not the parent +* (with grant) of \a pt +* +* This functions loops through all the resources owned by \a pt +* and sets the power mode to \a mode. It will skip setting +* \a exclude (SC_R_LAST to skip none). +* +* This function can only be called by the parent. It is used to +* implement some aspects of virtualization. +*/ +sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc, + sc_rm_pt_t pt, + sc_pm_power_mode_t mode, + sc_rsrc_t exclude); + +/*! + * This function gets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value + * returned does not reflect the power mode of the partition.. + */ +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode); + +/*! + * This function specifies the low power mode some of the resources + * can enter based on their state. This API is only valid for the + * following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2, + * SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35, + * SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3. + * For all other resources it will return SC_ERR_PARAM. + * This function will set the low power mode the cores, cluster + * and cluster associated resources will enter when all the cores + * in a given cluster execute WFI + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * This function requests low-power mode entry for CPU/cluster + * resources. This API is only valid for the following resources: + * SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x, + * SC_R_CCI. For all other resources it will return SC_ERR_PARAM. + * For individual core resources, the specified power mode + * and wake source will be applied after the core has entered + * WFI. For cluster resources, the specified power mode is + * applied after all cores in the cluster have entered low-power mode. + * For multicluster resources, the specified power mode is applied + * after all clusters have reached low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * @param[in] wake_src wake source for low-power exit + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode, + sc_pm_wake_src_t wake_src); + +/*! + * This function is used to set the resume address of a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, + sc_faddr_t address); + +/*! + * This function is used to set parameters for CPU resume from + * low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] isPrimary set SC_TRUE if primary wake CPU + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address); + +/*! + * This function requests the power mode configuration for system-level + * interfaces including messaging units, interconnect, and memories. This API + * is only valid for the following resources : SC_R_A53, SC_R_A72, and + * SC_R_M4_x_PID_y. For all other resources, it will return SC_ERR_PARAM. + * The requested power mode will be captured and applied to system-level + * resources as system conditions allow. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] sys_if system-level interface to be configured + * @param[in] hpm high-power mode for the system interface + * @param[in] lpm low-power mode for the system interface + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, + sc_pm_power_mode_t hpm, + sc_pm_power_mode_t lpm); + +/* @} */ + +/*! + * @name Clock/PLL Functions + * @{ + */ + +/*! + * This function sets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[in,out] rate pointer to rate to set, + * return actual rate + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock/PLL, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource, + * - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL) + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function gets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[out] rate pointer to return rate + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock/PLL, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource + * + * This function returns the actual clock rate of the hardware. This rate + * may be different from the original requested clock rate if the resource + * is set to a low power mode. + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function enables/disables a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] enable enable if SC_TRUE; otherwise disabled + * @param[in] autog HW auto clock gating + * + * If \a resource is SC_R_ALL then all resources owned will be affected. + * No error will be returned. + * + * If \a clk is SC_PM_CLK_ALL, then an error will be returned if any + * of the available clocks returns an error. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent (with grant) of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); + +/*! + * This function sets the parent of a resource's clock. + * This function should only be called when the clock is disabled. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] parent New parent of the clock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent (with grant) of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * - SC_ERR_BUSY if clock is currently enabled. + * - SC_ERR_NOPOWER if resource not powered + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent); + +/*! + * This function gets the parent of a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[out] parent pointer to return parent of clock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); + +/* @} */ + +/*! + * @name Reset Functions + * @{ + */ + +/*! + * This function is used to reset the system. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid type, + * - SC_ERR_NOACCESS if caller cannot access SC_R_SYSTEM + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function gets a caller's reset reason. + * + * @param[in] ipc IPC handle + * @param[out] reason pointer to return the reset reason + * + * This function returns the reason a partition was reset. If the reason + * is POR, then the system reset reason will be returned. + * + * Note depending on the connection of the WDOG_OUT signal and the OTP + * programming of the PMIC, some resets may trigger a system POR + * and the original reason will be lost. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); + +/*! + * This function gets the partition that caused a reset. + * + * @param[in] ipc IPC handle + * @param[out] pt pointer to return the resetting partition + * + * If the reset reason obtained via sc_pm_reset_reason() is POR then the + * result from this function will be 0. Some SECO causes of reset will + * also return 0. + * + * Note depending on the connection of the WDOG_OUT signal and the OTP + * programming of the PMIC, some resets may trigger a system POR + * and the partition info will be lost. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! + * This function is used to boot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to boot + * @param[in] resource_cpu ID of the CPU resource to start + * @param[in] boot_addr 64-bit boot address + * @param[in] resource_mu ID of the MU that must be powered + * @param[in] resource_dev ID of the boot device that must be powered + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition, resource, or addr, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * partition to boot + * + * This must be used to boot a partition. Only a partition booted this + * way can be rebooted using the watchdog, sc_pm_boot() or + * sc_pm_reboot_partition(). + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * This function is used to change the boot parameters for a partition. + * + * @param[in] ipc IPC handle + * @param[in] resource_cpu ID of the CPU resource to start + * @param[in] boot_addr 64-bit boot address + * @param[in] resource_mu ID of the MU that must be powered (0=none) + * @param[in] resource_dev ID of the boot device that must be powered (0=none) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource, or addr + * + * This function can be used to change the boot parameters for a partition. + * This can be useful if a partitions reboots differently from the initial + * boot done via sc_pm_boot() or via ROM. + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +sc_err_t sc_pm_set_boot_parm(sc_ipc_t ipc, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * This function is used to reboot the caller's partition. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * returns SC_ERR_PARM as these are not supported. + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function is used to reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to reboot + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * returns SC_ERR_PARM as these are not supported. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or type + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt + * and the caller does not have access to SC_R_SYSTEM + * + * Most peripherals owned by the partition will be reset if + * possible. SC state (partitions, power, clocks, etc.) is reset. The + * boot SW of the booting CPU must be able to handle peripherals that + * that are not reset. + * + * If board_reboot_part() returns a non-0 mask, then the reboot will + * be delayed until all partitions indicated in the mask have called + * sc_pm_reboot_continue() to continue the boot. + */ +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_reset_type_t type); + +/*! + * This function is used to continue the reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to continue + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function is used to start/stop a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] enable start if SC_TRUE; otherwise stop + * @param[in] address 64-bit boot address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + * + * This function is usually used to start a secondar CPU in the + * same partition as the caller. It is not used to start the first + * CPU in a dedicated partition. That would be started by calling + * sc_pm_boot(). + * + * A CPU started with sc_pm_cpu_start() will not restart as a result + * of a watchdog event or calling sc_pm_reboot() or sc_pm_reboot_partition(). + * Those will reboot that partition which will start the CPU started with + * sc_pm_boot(). + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address); + +/*! + * This function is used to reset a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] address 64-bit boot address + * + * This function does not return anything as the calling core may have been + * reset. It can still fail if the resource or address is invalid. It can also + * fail if the caller's partition is not the owner of the CPU, not the parent + * of the CPU resource owner, or has access to SC_R_SYSTEM. Will also fail if + * the resource is not powered on. No indication of failure is returned. + * + * Note this just resets the CPU. None of the peripherals or bus fabric used by + * the CPU is reset. State configured in the SCFW is not reset. The SW running + * on the core has to understand and deal with this. + * + * The address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address); + +/*! + * This function is used to reset a peripheral. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to reset + * + * This function will reset a resource. Most resources cannot be reset unless + * the SoC design specifically allows it. In the case on MUs, the IPC/RPC + * protocol is also reset. Note a caller cannot reset an MU that this API + * call is sent on. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource, + * - SC_ERR_PARM if resource is the MU used to make the call, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * (with grant) of the owner, + * - SC_ERR_BUSY if the resource cannot be reset bdue to power state of buses, + * - SC_ERR_UNAVAILABLE if the resource cannot be reset due to hardware limitations + */ +sc_err_t sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function returns a bool indicating if a partition was started. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to check + * + * @return Returns a bool (SC_TRUE = started). + * + * Note this indicates if a partition was started. It does not indicate if a + * partition is currently running or in a low power state. + */ +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); + +/* @} */ + +#endif /* SC_PM_API_H */ + +/**@}*/ diff --git a/include/soc/imx8/sc/svc/rm/api.h b/include/soc/imx8/sc/svc/rm/api.h new file mode 100644 index 000000000000..b5c3c2223a79 --- /dev/null +++ b/include/soc/imx8/sc/svc/rm/api.h @@ -0,0 +1,862 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Resource Management (RM) function. This includes functions for + * partitioning resources, pads, and memory regions. + * + * @addtogroup RM_SVC RM: Resource Management Service + * + * Module for the Resource Management (RM) service. + * + * @includedoc rm/details.dox + * + * @{ + */ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ +/*@}*/ + +/*! + * @name Defines for ALL parameters + */ +/*@{*/ +#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /* All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /* All memory regions */ +/*@}*/ + +/*! + * @name Defines for sc_rm_spa_t + */ +/*@{*/ +#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ +/*@}*/ + +/*! + * @name Defines for sc_rm_perm_t + */ +/*@{*/ +#define SC_RM_PERM_NONE 0U /* No access */ +#define SC_RM_PERM_SEC_R 1U /* Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /* Full access */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef uint8_t sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef uint8_t sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef uint8_t sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef uint16_t sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef uint8_t sc_rm_spa_t; + +/*! + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ +typedef uint8_t sc_rm_perm_t; + +/* Functions */ + +/*! + * @name Partition Functions + * @{ + */ + +/*! + * This function requests that the SC create a new resource partition. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for partition; used for subsequent function + * calls associated with this partition + * @param[in] secure boolean indicating if this partition should be secure; only + * valid if caller is secure + * @param[in] isolated boolean indicating if this partition should be HW isolated + * via XRDC; set SC_TRUE if new DID is desired + * @param[in] restricted boolean indicating if this partition should be restricted; set + * SC_TRUE if masters in this partition cannot create new partitions + * @param[in] grant boolean indicating if this partition should always grant + * access and control to the parent + * @param[in] coherent boolean indicating if this partition is coherent; + * set SC_TRUE if only this partition will contain both AP clusters + * and they will be coherent via the CCI + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space) + * + * Marking as non-secure prevents subsequent functions from configuring masters in this + * partition to assert the secure signal. Basically, if TrustZone SW is used, the Cortex-A + * cores and peripherals the TZ SW will use should be in a secure partition. Almost all + * other partitions (for a non-secure OS or M4 cores) should be in non-secure partitions. + * + * Isolated should be true for almost all partitions. The exception is the non-secure + * partition for a Cortex-A core used to run a non-secure OS. This isn't isolated by + * domain but is instead isolated by the TZ security hardware. + * + * If restricted then the new partition is limited in what functions it can call, + * especially those associated with managing partitions. + * + * The grant option is usually used to isolate a bus master's traffic to specific + * memory without isolating the peripheral interface of the master or the API + * controls of that master. This is only used when creating a sub-partition with + * no CPU. It's useful to separate out a master and the memory it uses. + */ +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent); + +/*! + * This function makes a partition confidential. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition that is granting + * @param[in] retro retroactive + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's not allowed to change \a pt + * - SC_ERR_LOCKED if partition \a pt is locked + * + * Call to make a partition confidential. Confidential means only this + * partition should be able to grant access permissions to this partition. + * + * If retroactive, then all resources owned by other partitions will have + * access rights for this partition removed, even if locked. + */ +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro); + +/*! + * This function frees a partition and assigns all resources to the caller. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt out of range or invalid, + * - SC_ERR_NOACCESS if \a pt is the SC partition, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt or caller's partition is locked + * + * All resources, memory regions, and pads are assigned to the caller/parent. + * The partition watchdog is disabled (even if locked). DID is freed. + */ +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function returns the DID of a partition. + * + * @param[in] ipc IPC handle + * + * @return Returns the domain ID (DID) of the caller's partition. + * + * The DID is a SoC-specific internal ID used by the HW resource + * protection mechanism. It is only required by clients when using the + * SEMA42 module as the DID is sometimes connected to the master ID. + */ +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc); + +/*! + * This function forces a partition to use a specific static DID. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a did + * @param[in] did static DID to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt or \a did out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt is locked + * + * Assumes no assigned resources or memory regions yet! The number of static + * DID is fixed by the SC at boot. + */ +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did); + +/*! + * This function locks a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to lock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt + * + * If a partition is locked it cannot be freed, have resources/pads assigned + * to/from it, memory regions created/assigned, DID changed, or parent changed. + */ +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function gets the partition handle of the caller. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for caller's partition + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! + * This function sets a new parent for a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition for which parent is to be + * changed + * @param[in] pt_parent handle of partition to set as parent + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if either partition is locked + */ +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); + +/*! + * This function moves all movable resources/pads owned by a source partition + * to a destination partition. It can be used to more quickly set up a new + * partition if a majority of the caller's resources are to be moved to a + * new partition. + * + * @param[in] ipc IPC handle + * @param[in] pt_src handle of partition from which resources should + * be moved from + * @param[in] pt_dst handle of partition to which resources should be + * moved to + * @param[in] move_rsrc boolean to indicate if resources should be moved + * @param[in] move_pads boolean to indicate if pads should be moved + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * By default, all resources are movable. This can be changed using the + * sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU + * bypass. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the + * parent of \a pt_src, + * - SC_ERR_LOCKED if either partition is locked + */ +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, + sc_bool_t move_rsrc, sc_bool_t move_pads); + +/* @} */ + +/*! + * @name Resource Functions + * @{ + */ + +/*! + * This function assigns ownership of a resource to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which resource should be + * assigned + * @param[in] resource resource to assign + * + * This function assigned a resource to a partition. This partition is then + * the owner. All resources always have an owner (one owner). The owner + * has various rights to make API calls affecting the resource. Ownership + * does not imply access to the peripheral itself (that is based on access + * rights). + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This action resets the resource's master and peripheral attributes. + * Privilege attribute will be PASSTHRU, security attribute will be + * ASSERT if the partition si secure and NEGATE if it is not, and + * masters will defaulted to SMMU bypass. Access permissions will reset + * to SEC_RW for the owning partition only for secure partitions, FULL for + * non-secure. Default is no access by other partitions. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); + +/*! + * This function flags resources as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] resource_fst first resource for which flag should be set + * @param[in] resource_lst last resource for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if resources are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of resources that will be + * moved using the sc_rm_move_all() function. All resources are movable + * by default so this function is normally used to prevent a set of + * resources from moving. + */ +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, + sc_rsrc_t resource_lst, sc_bool_t movable); + +/*! + * This function flags all of a subsystem's resources as movable + * or not. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to use to identify subsystem + * @param[in] movable movable flag (SC_TRUE is movable) + * + * A subsystem is a physical grouping within the chip of related resources; + * this is SoC specific. This function is used to optimize moving resource + * for these groupings, for instance, an M4 core and its associated resources. + * The list of subsystems and associated resources can be found in the + * SoC-specific API document [Resources](@ref RESOURCES) chapter. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if a function argument is out of range + * + * Note \a resource is used to find the associated subsystem. Only + * resources owned by the caller are set. + */ +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t movable); + +/*! + * This function sets attributes for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sa security attribute + * @param[in] pa privilege attribute + * @param[in] smmu_bypass SMMU bypass mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * Masters are IP blocks that generate bus transactions. This function configures + * how the isolation HW will define these bus transactions from the specified master. + * Note the security attribute will only be changed if the caller's partition is + * secure. + * + * Note an IP block can be both a master and peripheral (have both a programming model + * and generate bus transactions). + */ +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, + sc_bool_t smmu_bypass); + +/*! + * This function sets the StreamID for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sid StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function configures the SID attribute associated with all bus transactions + * from this master. Note 0 is not a valid SID as it is reserved to indicate + * bypass. + */ +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t sid); + +/*! + * This function sets access permissions for a peripheral resource. + * + * @param[in] ipc IPC handle + * @param[in] resource peripheral resource for which permissions should apply + * @param[in] pt handle of partition \a perm should by applied for + * @param[in] perm permissions to apply to \a resource for \a pt + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * Peripherals are IP blocks that have a programming model that can be + * accessed. + * + * This function configures how the isolation HW will restrict access to a + * peripheral based on the attributes of a transaction from bus master. It + * also allows the access permissions of SC_R_SYSTEM to be set. + * + * Note an IP block can be both a master and peripheral (have both a programming + * model and generate bus transactions). + */ +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function gets ownership status of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the resource). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to get the owner of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * @param[out] pt pointer to return owning partition + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid + * + * If \a resource is out of range then SC_ERR_PARM is returned. + */ +sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt); + +/*! + * This function is used to test if a resource is a bus master. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * Masters are IP blocks that generate bus transactions. Note an IP block + * can be both a master and peripheral (have both a programming model + * and generate bus transactions). + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to test if a resource is a peripheral. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * Peripherals are IP blocks that have a programming model that can be + * accessed. Note an IP block can be both a master and peripheral (have + * both a programming model and generate bus transactions) + * + * @return Returns a boolean (SC_TRUE if the resource is a peripheral). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to obtain info about a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to inquire about + * @param[out] sid pointer to return StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a resource is out of range + */ +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t *sid); + +/* @} */ + +/*! + * @name Memory Region Functions + * @{ + */ + +/*! + * This function requests that the SC create a new memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is misaligned, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * This function will create a new memory region. The area covered by the + * new region must already exist in a memory region owned by the caller. The + * result will be two memory regions, the new one overlapping the existing + * one. The new region has higher priority. See the XRDC2 MRC documentation + * for how it resolves access permissions in this case. By default, the new + * region will have access permission set to allow the caller to access. + */ +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function requests that the SC split an existing memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to split + * @param[out] mr_ret return handle for new region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is not start/end part of mr, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * This function will take an existing region and split it into two, + * non-overlapping regions. Note the new region must start or end on the + * split region. + */ +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, + sc_faddr_t addr_end); + +/*! + * This function requests that the SC fragment a memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr_ret return handle for new region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * This function finds the memory region containing the address range. + * It then splits it as required and returns the extracted region. The + * result is 2-3 non-overlapping regions, depending on how the new region + * aligns with existing regions. + */ +sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function frees a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr, + * - SC_ERR_LOCKED if the owning partition of \a mr is locked + */ +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * Internal SC function to find a memory region. + * + * @see sc_rm_find_memreg(). + */ +/*! + * This function finds a memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; used for + * subsequent function calls + * associated with this region + * @param[in] addr_start start address of region to search for + * @param[in] addr_end end address of region to search for + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOTFOUND if region not found, + * + * Searches only for regions owned by the caller. Finds first + * region containing the range specified. + */ +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function assigns ownership of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which memory region + * should be assigned + * @param[in] mr handle of memory region to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This function assigns a memory region to a partition. This partition is then + * the owner. All regions always have an owner (one owner). The owner + * has various rights to make API calls affecting the region. Ownership + * does not imply access to the memory itself (that is based on access + * rights). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr); + +/*! + * This function sets access permissions for a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region for which permissions + * should apply + * @param[in] pt handle of partition \a perm should by + * applied for + * @param[in] perm permissions to apply to \a mr for \a pt + * + * This operates on the memory region specified. If SC_RM_PT_ALL is specified + * then it operates on all the regions owned by the caller that exist at the + * time of the call. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * This function configures how the HW isolation will restrict access to a + * memory region based on the attributes of a transaction from bus master. + */ +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function gets ownership status of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the + * memory region). + * + * If \a mr is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * This function is used to obtain info about a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to inquire about + * @param[out] addr_start pointer to return start address + * @param[out] addr_end pointer to return end address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr is out of range + */ +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end); + +/* @} */ + +/*! + * @name Pad Functions + * @{ + */ + +/*! + * This function assigns ownership of a pad to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which pad should + * be assigned + * @param[in] pad pad to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); + +/*! + * This function flags pads as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] pad_fst first pad for which flag should be set + * @param[in] pad_lst last pad for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * This function assigned a pad to a partition. This partition is then + * the owner. All pads always have an owner (one owner). The owner + * has various rights to make API calls affecting the pad. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if pads are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of pads that will be + * moved using the sc_rm_move_all() function. All pads are movable + * by default so this function is normally used to prevent a set of + * pads from moving. + */ +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, + sc_pad_t pad_lst, sc_bool_t movable); + +/*! + * This function gets ownership status of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the pad). + * + * If \a pad is out of range then SC_FALSE is returned. + */ +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function dumps the RM state for debug. + * + * @param[in] ipc IPC handle + */ +void sc_rm_dump(sc_ipc_t ipc); + +/* @} */ + +#endif /* SC_RM_API_H */ + +/**@}*/ diff --git a/include/soc/imx8/sc/svc/seco/api.h b/include/soc/imx8/sc/svc/seco/api.h new file mode 100644 index 000000000000..108008c5d105 --- /dev/null +++ b/include/soc/imx8/sc/svc/seco/api.h @@ -0,0 +1,757 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Security (SECO) function. + * + * @addtogroup SECO_SVC SECO: Security Service + * + * Module for the Security (SECO) service. + * + * @anchor seco_err + * + * @includedoc seco/details.dox + * + * @{ + */ + +#ifndef SC_SECO_API_H +#define SC_SECO_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> +#include <soc/imx8/sc/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for sc_seco_auth_cmd_t + */ +/*@{*/ +#define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_SECO_VERIFY_IMAGE 1U /* Verify image */ +#define SC_SECO_REL_CONTAINER 2U /* Release container */ +#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ +#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ +#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ +#define SC_SECO_EVERIFY_IMAGE 6U /* Enhanced verify image */ +/*@}*/ + +/*! + * @name Defines for seco_rng_stat_t + */ +/*@{*/ +#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ +#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ +#define SC_SECO_RNG_STAT_READY 2U /* Initialized */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef uint8_t sc_seco_auth_cmd_t; + +/*! + * This type is used to return the RNG initialization status. + */ +typedef uint32_t sc_seco_rng_stat_t; + +/* Functions */ + +/*! + * @name Image Functions + * @{ + */ + +/*! + * This function loads a SECO image. + * + * @param[in] ipc IPC handle + * @param[in] addr_src address of image source + * @param[in] addr_dst address of image destination + * @param[in] len lenth of image to load + * @param[in] fw SC_TRUE = firmware load + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to load images via the SECO. Examples include SECO + * Firmware and IVT/CSF data used for authentication. These are usually + * loaded into SECO TCM. \a addr_src is in secure memory. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); + +/*! + * This function is used to authenticate a SECO image or command. + * + * @param[in] ipc IPC handle + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_BUSY if SECO is busy with another authentication request, + * - SC_ERR_FAIL if SECO response is bad, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to authenticate a SECO image or issue a security + * command. \a addr often points to an container. It is also + * just data (or even unused) for some commands. + * + * Implementation of this command depends on the underlying security + * architecture of the device. For example, on devices with SECO FW, + * the following options apply: + * + * - cmd=SC_SECO_AUTH_CONTAINER, addr=container address (sends AHAB_AUTH_CONTAINER_REQ to SECO) + * - cmd=SC_SECO_VERIFY_IMAGE, addr=image mask (sends AHAB_VERIFY_IMAGE_REQ to SECO) + * - cmd=SC_SECO_REL_CONTAINER, addr unused (sends AHAB_RELEASE_CONTAINER_REQ to SECO) + * - cmd=SC_SECO_AUTH_HDMI_TX_FW, addr unused (sends AHAB_ENABLE_HDMI_X_REQ with Subsystem=0 to SECO) + * - cmd=SC_SECO_AUTH_HDMI_RX_FW, addr unused (sends AHAB_ENABLE_HDMI_X_REQ with Subsystem=1 to SECO) + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_authenticate(sc_ipc_t ipc, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr); + +/*! + * This function is used to authenticate a SECO image or command. This is an + * enhanced version that has additional mask arguments. + * + * @param[in] ipc IPC handle + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * @param[in] mask1 metadata + * @param[in] mask2 metadata + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_BUSY if SECO is busy with another authentication request, + * - SC_ERR_FAIL if SECO response is bad, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This supports all the commands found in sc_seco_authenticate(). Those + * commands should set both masks to 0 (except SC_SECO_VERIFY_IMAGE). + + * New commands are as follows: + * + * - cmd=SC_SECO_VERIFY_IMAGE, addr unused, mask1=image mask, mask2 unused (sends AHAB_VERIFY_IMAGE_REQ to SECO) + * - cmd=SC_SECO_EVERIFY_IMAGE, addr=container address, mask1=image mask, mask2=move mask (sends AHAB_EVERIFY_IMAGE_REQ to SECO) + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_enh_authenticate(sc_ipc_t ipc, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr, + uint32_t mask1, uint32_t mask2); + +/* @} */ + +/*! + * @name Lifecycle Functions + * @{ + */ + +/*! + * This function updates the lifecycle of the device. + * + * @param[in] ipc IPC handle + * @param[in] change desired lifecycle transistion + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used for going from Open to NXP Closed to OEM Closed. + * Note \a change is NOT the new desired lifecycle. It is a lifecycle + * transition as documented in the <em>SECO API Reference Guide</em>. + * + * If any SECO request fails or only succeeds because the part is in an + * "OEM open" lifecycle, then a request to transition from "NXP closed" + * to "OEM closed" will also fail. For example, booting a signed container + * when the OEM SRK is not fused will succeed, but as it is an abnormal + * situation, a subsequent request to transition the lifecycle will return + * an error. + */ +sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change); + +/*! + * This function updates the lifecycle to one of the return lifecycles. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * To switch back to NXP states (Full Field Return), message must be signed + * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM + * SRK. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to commit into the fuses any new SRK revocation + * and FW version information that have been found in the primary and + * secondary containers. + * + * @param[in] ipc IPC handle + * @param[in,out] info pointer to information type to be committed + * + * The return \a info will contain what was actually committed. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a info is invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + */ +sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info); + +/* @} */ + +/*! + * @name Attestation Functions + * @{ + */ + +/*! + * This function is used to set the attestation mode. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] mode mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a mode is invalid, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to set the SECO attestation mode. This can be prover + * or verfier. See the <em>SECO API Reference Guide</em> for more on the + * suported modes, mode values, and mode behavior. + */ +sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode); + +/*! + * This function is used to request atestation. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] nonce unique value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to ask SECO to perform an attestation. The result depends + * on the attestation mode. After this call, the signature can be + * requested or a verify can be requested. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce); + +/*! + * This function is used to retrieve the attestation public key. + * Mode must be verifier. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 96 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to retrieve attestation signature and parameters. + * Mode must be provider. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 120 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to verify attestation. Mode must be verifier. + * Only the owner of the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address of signature + * + * The \a addr parmater must point to an address SECO can access. It must be + * 64-bit aligned. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_FAIL if signature doesn't match, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr); + +/* @} */ + +/*! + * @name Key Functions + * @{ + */ + +/*! + * This function is used to generate a SECO key blob. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] load_addr load address + * @param[in] export_addr export address + * @param[in] max_size max export size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used to encapsulate sensitive keys in a specific structure + * called a blob, which provides both confidentiality and integrity protection. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id, + sc_faddr_t load_addr, sc_faddr_t export_addr, + uint16_t max_size); + +/*! + * This function is used to load a SECO key. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] addr key address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used to install private cryptographic keys encapsulated + * in a blob previously generated by SECO. The controller can be either the + * IEE or the VPU. The blob header carries the controller type and the key + * size, as provided by the user when generating the key blob. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id, sc_faddr_t addr); + +/* @} */ + +/*! + * @name Manufacturing Protection Functions + * @{ + */ + +/*! + * This function is used to get the manufacturing protection public key. + * + * @param[in] ipc IPC handle + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is supported only in OEM-closed lifecycle. It generates + * the mfg public key and stores it in a specific location in the secure + * memory. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + uint16_t dst_size); + +/*! + * This function is used to update the manufacturing protection message + * register. + * + * @param[in] ipc IPC handle + * @param[in] addr data address + * @param[in] size size + * @param[in] lock lock_reg + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is supported only in OEM-closed lifecycle. It updates the + * content of the MPMR (Manufacturing Protection Message register of 256 + * bits). This register will be appended to the input-data message when + * generating the signature. Please refer to the CAAM block guide for details. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, + uint8_t size, uint8_t lock); + +/*! + * This function is used to get the manufacturing protection signature. + * + * @param[in] ipc IPC handle + * @param[in] msg_addr message address + * @param[in] msg_size message size + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used to generate an ECDSA signature for an input-data + * message and to store it in a specific location in the secure memory. It + * is only supported in OEM-closed lifecycle. In order to get the ECDSA + * signature, the RNG must be initialized. In case it has not been started + * an error will be returned. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, + uint16_t dst_size); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used to return the SECO FW build info. + * + * @param[in] ipc IPC handle + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit); + +/*! + * This function is used to return SECO chip info. + * + * @param[in] ipc IPC handle + * @param[out] lc pointer to return lifecycle + * @param[out] monotonic pointer to return monotonic counter + * @param[out] uid_l pointer to return UID (lower 32 bits) + * @param[out] uid_h pointer to return UID (upper 32 bits) + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + */ +sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, + uint32_t *uid_h); + +/*! + * This function securely enables debug. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to return an event from the SECO error log. + * + * @param[in] ipc IPC handle + * @param[out] idx index of event to return + * @param[out] event pointer to return event + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Read of \a idx 0 captures events from SECO. Loop starting + * with 0 until an error is returned to dump all events. + */ +sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx, uint32_t *event); + +/* @} */ + +/*! + * @name Miscellaneous Functions + * @{ + */ + +/*! + * This function securely writes a group of fuse words. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function applies a patch. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_patch(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function starts the random number generator. + * + * @param[in] ipc IPC handle + * @param[out] status pointer to return state of RNG + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * The RNG is started automatically after all CPUs are booted. This + * function can be used to start earlier and to check the status. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_start_rng(sc_ipc_t ipc, sc_seco_rng_stat_t *status); + +/*! + * This function sends a generic signed message to the + * SECO SHE/HSM components. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the <em>SECO API Reference Guide</em> for more info. + */ +sc_err_t sc_seco_sab_msg(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to enable security violation and tamper interrupts. + * These are then reported using the IRQ service via the SC_IRQ_SECVIO + * interrupt. Note it is automatically enabled at boot. + * + * @param[in] ipc IPC handle + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if caller does not own SC_R_SECVIO, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * The security violation interrupt is self-masking. Once it is cleared in + * the SNVS it must be re-enabled using this function. + */ +sc_err_t sc_seco_secvio_enable(sc_ipc_t ipc); + +/*! + * This function is used to read/write SNVS security violation + * and tamper registers. + * + * @param[in] ipc IPC handle + * @param[in] id register ID + * @param[in] access 0=read, 1=write + * @param[in] data0 pointer to data to read or write + * @param[in] data1 pointer to data to read or write + * @param[in] data2 pointer to data to read or write + * @param[in] data3 pointer to data to read or write + * @param[in] data4 pointer to data to read or write + * @param[in] size number of valid data words + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if caller does not own SC_R_SECVIO, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Unused data words can be passed a NULL pointer. + * + * See AHAB_MANAGE_SNVS_REQ in the <em>SECO API Reference Guide</em> for + * more info. + */ +sc_err_t sc_seco_secvio_config(sc_ipc_t ipc, uint8_t id, uint8_t access, + uint32_t *data0, uint32_t *data1, + uint32_t *data2, uint32_t *data3, + uint32_t *data4, uint8_t size); + +sc_err_t sc_seco_secvio_dgo_config(sc_ipc_t ipc, uint8_t id, uint8_t access, + uint32_t *data); + +/* @} */ + +#endif /* SC_SECO_API_H */ + +/**@}*/ diff --git a/include/soc/imx8/sc/svc/timer/api.h b/include/soc/imx8/sc/svc/timer/api.h new file mode 100644 index 000000000000..09da665ca881 --- /dev/null +++ b/include/soc/imx8/sc/svc/timer/api.h @@ -0,0 +1,374 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Timer function. + * + * @addtogroup TIMER_SVC TIMER: Timer Service + * + * Module for the Timer service. This includes support for the watchdog, RTC, + * and system counter. Note every resource partition has a watchdog it can + * use. + * + * @{ + */ + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> +#include <soc/imx8/sc/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */ +/*@}*/ + +/*! + * @name Defines for sc_timer_wdog_action_t + */ +/*@{*/ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to configure the watchdog action. + */ +typedef uint8_t sc_timer_wdog_action_t; + +/*! + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef uint32_t sc_timer_wdog_time_t; + +/* Functions */ + +/*! + * @name Wathdog Functions + * @{ + */ + +/*! + * This function sets the watchdog timeout in milliseconds. If not + * set then the timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] timeout timeout period for the watchdog + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout); + +/*! + * This function sets the watchdog pre-timeout in milliseconds. If not + * set then the pre-timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] pre_timeout pre-timeout period for the watchdog + * + * When the pre-timout expires an IRQ will be generated. Note this timeout + * clears when the IRQ is triggered. An IRQ is generated for the failing + * partition and all of its child partitions. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t pre_timeout); + +/*! + * This function starts the watchdog. + * + * @param[in] ipc IPC handle + * @param[in] lock boolean indicating the lock status + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is not isolated + * + * If \a lock is set then the watchdog cannot be stopped or the timeout + * period changed. + * + * If the calling partition is not isolated then the wdog cannot be used. + * This is always the case if a non-secure partition is running on the same + * CPU as a secure partition (e.g. Linux under TZ). See sc_rm_partition_alloc(). + */ +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock); + +/*! + * This function stops the watchdog if it is not locked. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc); + +/*! + * This function pings (services, kicks) the watchdog resetting the time + * before expiration back to the timeout. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc); + +/*! + * This function gets the status of the watchdog. All arguments are + * in milliseconds. + * + * @param[in] ipc IPC handle + * @param[out] timeout pointer to return the timeout + * @param[out] max_timeout pointer to return the max timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, + sc_timer_wdog_time_t *timeout, + sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time); + +/*! + * This function gets the status of the watchdog of a partition. All + * arguments are in milliseconds. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to query + * @param[out] enb pointer to return enable status + * @param[out] timeout pointer to return the timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, + sc_timer_wdog_time_t *remaining_time); + +/*! + * This function configures the action to be taken when a watchdog + * expires. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to affect + * @param[in] action action to take + * + * Default action is inherited from the parent. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid parameters, + * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner, + * - SC_ERR_LOCKED if the watchdog is locked + */ +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_timer_wdog_action_t action); + +/* @} */ + +/*! + * @name Real-Time Clock (RTC) Functions + * @{ + */ + +/*! + * This function sets the RTC time. Only the owner of the SC_R_SYSTEM + * resource or a partition with access permissions to SC_R_SYSTEM can + * set the time. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters, + * - SC_ERR_NOACCESS if caller's partition cannot access SC_R_SYSTEM + */ +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, + uint8_t sec); + +/*! + * This function gets the RTC time. + * + * @param[in] ipc IPC handle + * @param[out] year pointer to return year (min 1970) + * @param[out] mon pointer to return month (1-12) + * @param[out] day pointer to return day of the month (1-31) + * @param[out] hour pointer to return hour (0-23) + * @param[out] min pointer to return minute (0-59) + * @param[out] sec pointer to return second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, + uint8_t *day, uint8_t *hour, uint8_t *min, + uint8_t *sec); + +/*! + * This function gets the RTC time in seconds since 1/1/1970. + * + * @param[in] ipc IPC handle + * @param[out] sec pointer to return second + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec); + +/*! + * This function sets the RTC alarm. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * Note this alarm setting clears when the alarm is triggered. This is an + * absolute time. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, + uint8_t sec); + +/*! + * This function sets the RTC alarm (periodic mode). + * + * @param[in] ipc IPC handle + * @param[in] sec period in seconds + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note this is a relative time. + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec); + +/*! + * This function cancels the RTC alarm. + * + * @param[in] ipc IPC handle + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc); + +/*! + * This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM + * resource or a partition with access permissions to SC_R_SYSTEM can set the + * calibration. + * + * @param[in] ipc IPC handle + * @param[in] count calbration count (-16 to 15) + * + * The calibration value is a 5-bit value including the sign bit, which is + * implemented in 2's complement. It is added or subtracted from the RTC on + * a perdiodic basis, once per 32768 cycles of the RTC clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count); + +/* @} */ + +/*! + * @name System Counter (SYSCTR) Functions + * @{ + */ + +/*! + * This function sets the SYSCTR alarm. + * + * @param[in] ipc IPC handle + * @param[in] ticks number of 8MHz cycles + * + * Note the \a ticks parameter is an absolute time. This alarm + * setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks); + +/*! + * This function sets the SYSCTR alarm (periodic mode). + * + * @param[in] ipc IPC handle + * @param[in] ticks number of 8MHz cycles + * + * Note the \a ticks parameter is a relative time. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks); + +/*! + * This function cancels the SYSCTR alarm. + * + * @param[in] ipc IPC handle + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc); + +/* @} */ + +#endif /* SC_TIMER_API_H */ + +/**@}*/ diff --git a/include/soc/imx8/sc/types.h b/include/soc/imx8/sc/types.h new file mode 100644 index 000000000000..a1326148bae0 --- /dev/null +++ b/include/soc/imx8/sc/types.h @@ -0,0 +1,892 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing types used across multiple service APIs. + */ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ + +#include <soc/imx8/sc/scfw.h> + +/* Defines */ + +/*! + * @name Defines for common frequencies + */ +/*@{*/ +#define SC_32KHZ 32768U /* 32KHz */ +#define SC_10MHZ 10000000U /* 10MHz */ +#define SC_16MHZ 16000000U /* 16MHz */ +#define SC_20MHZ 20000000U /* 20MHz */ +#define SC_25MHZ 25000000U /* 25MHz */ +#define SC_27MHZ 27000000U /* 27MHz */ +#define SC_40MHZ 40000000U /* 40MHz */ +#define SC_45MHZ 45000000U /* 45MHz */ +#define SC_50MHZ 50000000U /* 50MHz */ +#define SC_60MHZ 60000000U /* 60MHz */ +#define SC_66MHZ 66666666U /* 66MHz */ +#define SC_74MHZ 74250000U /* 74.25MHz */ +#define SC_80MHZ 80000000U /* 80MHz */ +#define SC_83MHZ 83333333U /* 83MHz */ +#define SC_84MHZ 84375000U /* 84.37MHz */ +#define SC_100MHZ 100000000U /* 100MHz */ +#define SC_114MHZ 114000000U /* 114MHz */ +#define SC_125MHZ 125000000U /* 125MHz */ +#define SC_133MHZ 133333333U /* 133MHz */ +#define SC_135MHZ 135000000U /* 135MHz */ +#define SC_150MHZ 150000000U /* 150MHz */ +#define SC_160MHZ 160000000U /* 160MHz */ +#define SC_166MHZ 166666666U /* 166MHz */ +#define SC_175MHZ 175000000U /* 175MHz */ +#define SC_180MHZ 180000000U /* 180MHz */ +#define SC_200MHZ 200000000U /* 200MHz */ +#define SC_250MHZ 250000000U /* 250MHz */ +#define SC_266MHZ 266666666U /* 266MHz */ +#define SC_300MHZ 300000000U /* 300MHz */ +#define SC_312MHZ 312500000U /* 312.5MHZ */ +#define SC_320MHZ 320000000U /* 320MHz */ +#define SC_325MHZ 325000000U /* 325MHz */ +#define SC_333MHZ 333333333U /* 333MHz */ +#define SC_350MHZ 350000000U /* 350MHz */ +#define SC_372MHZ 372000000U /* 372MHz */ +#define SC_375MHZ 375000000U /* 375MHz */ +#define SC_400MHZ 400000000U /* 400MHz */ +#define SC_465MHZ 465000000U /* 465MHz */ +#define SC_500MHZ 500000000U /* 500MHz */ +#define SC_594MHZ 594000000U /* 594MHz */ +#define SC_625MHZ 625000000U /* 625MHz */ +#define SC_640MHZ 640000000U /* 640MHz */ +#define SC_648MHZ 648000000U /* 648MHz */ +#define SC_650MHZ 650000000U /* 650MHz */ +#define SC_667MHZ 666666667U /* 667MHz */ +#define SC_675MHZ 675000000U /* 675MHz */ +#define SC_700MHZ 700000000U /* 700MHz */ +#define SC_720MHZ 720000000U /* 720MHz */ +#define SC_750MHZ 750000000U /* 750MHz */ +#define SC_753MHZ 753000000U /* 753MHz */ +#define SC_793MHZ 793000000U /* 793MHz */ +#define SC_800MHZ 800000000U /* 800MHz */ +#define SC_850MHZ 850000000U /* 850MHz */ +#define SC_858MHZ 858000000U /* 858MHz */ +#define SC_900MHZ 900000000U /* 900MHz */ +#define SC_953MHZ 953000000U /* 953MHz */ +#define SC_963MHZ 963000000U /* 963MHz */ +#define SC_1000MHZ 1000000000U /* 1GHz */ +#define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1068MHZ 1068000000U /* 1.068GHz */ +#define SC_1121MHZ 1121000000U /* 1.121GHz */ +#define SC_1173MHZ 1173000000U /* 1.173GHz */ +#define SC_1188MHZ 1188000000U /* 1.188GHz */ +#define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1278MHZ 1278000000U /* 1.278GHz */ +#define SC_1280MHZ 1280000000U /* 1.28GHz */ +#define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1313MHZ 1313000000U /* 1.313GHz */ +#define SC_1345MHZ 1345000000U /* 1.345GHz */ +#define SC_1400MHZ 1400000000U /* 1.4GHz */ +#define SC_1500MHZ 1500000000U /* 1.5GHz */ +#define SC_1600MHZ 1600000000U /* 1.6GHz */ +#define SC_1800MHZ 1800000000U /* 1.8GHz */ +#define SC_1860MHZ 1860000000U /* 1.86GHz */ +#define SC_2000MHZ 2000000000U /* 2.0GHz */ +#define SC_2112MHZ 2112000000U /* 2.12GHz */ +/*@}*/ + +/*! + * @name Defines for 24M related frequencies + */ +/*@{*/ +#define SC_8MHZ 8000000U /* 8MHz */ +#define SC_12MHZ 12000000U /* 12MHz */ +#define SC_19MHZ 19800000U /* 19.8MHz */ +#define SC_24MHZ 24000000U /* 24MHz */ +#define SC_48MHZ 48000000U /* 48MHz */ +#define SC_120MHZ 120000000U /* 120MHz */ +#define SC_132MHZ 132000000U /* 132MHz */ +#define SC_144MHZ 144000000U /* 144MHz */ +#define SC_192MHZ 192000000U /* 192MHz */ +#define SC_211MHZ 211200000U /* 211.2MHz */ +#define SC_228MHZ 228000000U /* 233MHz */ +#define SC_240MHZ 240000000U /* 240MHz */ +#define SC_264MHZ 264000000U /* 264MHz */ +#define SC_352MHZ 352000000U /* 352MHz */ +#define SC_360MHZ 360000000U /* 360MHz */ +#define SC_384MHZ 384000000U /* 384MHz */ +#define SC_396MHZ 396000000U /* 396MHz */ +#define SC_432MHZ 432000000U /* 432MHz */ +#define SC_456MHZ 456000000U /* 466MHz */ +#define SC_480MHZ 480000000U /* 480MHz */ +#define SC_600MHZ 600000000U /* 600MHz */ +#define SC_744MHZ 744000000U /* 744MHz */ +#define SC_792MHZ 792000000U /* 792MHz */ +#define SC_864MHZ 864000000U /* 864MHz */ +#define SC_912MHZ 912000000U /* 912MHz */ +#define SC_960MHZ 960000000U /* 960MHz */ +#define SC_1056MHZ 1056000000U /* 1056MHz */ +#define SC_1104MHZ 1104000000U /* 1104MHz */ +#define SC_1200MHZ 1200000000U /* 1.2GHz */ +#define SC_1464MHZ 1464000000U /* 1.464GHz */ +#define SC_2400MHZ 2400000000U /* 2.4GHz */ +/*@}*/ + +/*! + * @name Defines for A/V related frequencies + */ +/*@{*/ +#define SC_62MHZ 62937500U /* 62.9375MHz */ +#define SC_755MHZ 755250000U /* 755.25MHz */ +/*@}*/ + +/*! + * @name Defines for type widths + */ +/*@{*/ +#define SC_BOOL_W 1U /* Width of sc_bool_t */ +#define SC_ERR_W 4U /* Width of sc_err_t */ +#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ +/*@}*/ + +/*! + * @name Defines for sc_bool_t + */ +/*@{*/ +#define SC_FALSE ((sc_bool_t) 0U) /* False */ +#define SC_TRUE ((sc_bool_t) 1U) /* True */ +/*@}*/ + +/*! + * @name Defines for sc_err_t. + */ +/*@{*/ +#define SC_ERR_NONE 0U /* Success */ +#define SC_ERR_VERSION 1U /* Incompatible API version */ +#define SC_ERR_CONFIG 2U /* Configuration error */ +#define SC_ERR_PARM 3U /* Bad parameter */ +#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ +#define SC_ERR_LOCKED 5U /* Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /* Not found */ +#define SC_ERR_NOPOWER 8U /* No power */ +#define SC_ERR_IPC 9U /* Generic IPC error */ +#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /* General I/O failure */ +#define SC_ERR_LAST 12U +/*@}*/ + +/*! + * @name Defines for sc_rsrc_t. + */ +/*@{*/ +#define SC_R_A53 0U +#define SC_R_A53_0 1U +#define SC_R_A53_1 2U +#define SC_R_A53_2 3U +#define SC_R_A53_3 4U +#define SC_R_A72 5U +#define SC_R_A72_0 6U +#define SC_R_A72_1 7U +#define SC_R_A72_2 8U +#define SC_R_A72_3 9U +#define SC_R_CCI 10U +#define SC_R_DB 11U +#define SC_R_DRC_0 12U +#define SC_R_DRC_1 13U +#define SC_R_GIC_SMMU 14U +#define SC_R_IRQSTR_M4_0 15U +#define SC_R_IRQSTR_M4_1 16U +#define SC_R_SMMU 17U +#define SC_R_GIC 18U +#define SC_R_DC_0_BLIT0 19U +#define SC_R_DC_0_BLIT1 20U +#define SC_R_DC_0_BLIT2 21U +#define SC_R_DC_0_BLIT_OUT 22U +#define SC_R_PERF 23U +#define SC_R_USB_1_PHY 24U +#define SC_R_DC_0_WARP 25U +#define SC_R_V2X_MU_0 26U +#define SC_R_V2X_MU_1 27U +#define SC_R_DC_0_VIDEO0 28U +#define SC_R_DC_0_VIDEO1 29U +#define SC_R_DC_0_FRAC0 30U +#define SC_R_V2X_MU_2 31U +#define SC_R_DC_0 32U +#define SC_R_GPU_2_PID0 33U +#define SC_R_DC_0_PLL_0 34U +#define SC_R_DC_0_PLL_1 35U +#define SC_R_DC_1_BLIT0 36U +#define SC_R_DC_1_BLIT1 37U +#define SC_R_DC_1_BLIT2 38U +#define SC_R_DC_1_BLIT_OUT 39U +#define SC_R_V2X_MU_3 40U +#define SC_R_V2X_MU_4 41U +#define SC_R_DC_1_WARP 42U +#define SC_R_TBU_CTL 43U +#define SC_R_SECVIO 44U +#define SC_R_DC_1_VIDEO0 45U +#define SC_R_DC_1_VIDEO1 46U +#define SC_R_DC_1_FRAC0 47U +#define SC_R_UNUSED13 48U +#define SC_R_DC_1 49U +#define SC_R_UNUSED14 50U +#define SC_R_DC_1_PLL_0 51U +#define SC_R_DC_1_PLL_1 52U +#define SC_R_SPI_0 53U +#define SC_R_SPI_1 54U +#define SC_R_SPI_2 55U +#define SC_R_SPI_3 56U +#define SC_R_UART_0 57U +#define SC_R_UART_1 58U +#define SC_R_UART_2 59U +#define SC_R_UART_3 60U +#define SC_R_UART_4 61U +#define SC_R_EMVSIM_0 62U +#define SC_R_EMVSIM_1 63U +#define SC_R_DMA_0_CH0 64U +#define SC_R_DMA_0_CH1 65U +#define SC_R_DMA_0_CH2 66U +#define SC_R_DMA_0_CH3 67U +#define SC_R_DMA_0_CH4 68U +#define SC_R_DMA_0_CH5 69U +#define SC_R_DMA_0_CH6 70U +#define SC_R_DMA_0_CH7 71U +#define SC_R_DMA_0_CH8 72U +#define SC_R_DMA_0_CH9 73U +#define SC_R_DMA_0_CH10 74U +#define SC_R_DMA_0_CH11 75U +#define SC_R_DMA_0_CH12 76U +#define SC_R_DMA_0_CH13 77U +#define SC_R_DMA_0_CH14 78U +#define SC_R_DMA_0_CH15 79U +#define SC_R_DMA_0_CH16 80U +#define SC_R_DMA_0_CH17 81U +#define SC_R_DMA_0_CH18 82U +#define SC_R_DMA_0_CH19 83U +#define SC_R_DMA_0_CH20 84U +#define SC_R_DMA_0_CH21 85U +#define SC_R_DMA_0_CH22 86U +#define SC_R_DMA_0_CH23 87U +#define SC_R_DMA_0_CH24 88U +#define SC_R_DMA_0_CH25 89U +#define SC_R_DMA_0_CH26 90U +#define SC_R_DMA_0_CH27 91U +#define SC_R_DMA_0_CH28 92U +#define SC_R_DMA_0_CH29 93U +#define SC_R_DMA_0_CH30 94U +#define SC_R_DMA_0_CH31 95U +#define SC_R_I2C_0 96U +#define SC_R_I2C_1 97U +#define SC_R_I2C_2 98U +#define SC_R_I2C_3 99U +#define SC_R_I2C_4 100U +#define SC_R_ADC_0 101U +#define SC_R_ADC_1 102U +#define SC_R_FTM_0 103U +#define SC_R_FTM_1 104U +#define SC_R_CAN_0 105U +#define SC_R_CAN_1 106U +#define SC_R_CAN_2 107U +#define SC_R_DMA_1_CH0 108U +#define SC_R_DMA_1_CH1 109U +#define SC_R_DMA_1_CH2 110U +#define SC_R_DMA_1_CH3 111U +#define SC_R_DMA_1_CH4 112U +#define SC_R_DMA_1_CH5 113U +#define SC_R_DMA_1_CH6 114U +#define SC_R_DMA_1_CH7 115U +#define SC_R_DMA_1_CH8 116U +#define SC_R_DMA_1_CH9 117U +#define SC_R_DMA_1_CH10 118U +#define SC_R_DMA_1_CH11 119U +#define SC_R_DMA_1_CH12 120U +#define SC_R_DMA_1_CH13 121U +#define SC_R_DMA_1_CH14 122U +#define SC_R_DMA_1_CH15 123U +#define SC_R_DMA_1_CH16 124U +#define SC_R_DMA_1_CH17 125U +#define SC_R_DMA_1_CH18 126U +#define SC_R_DMA_1_CH19 127U +#define SC_R_DMA_1_CH20 128U +#define SC_R_DMA_1_CH21 129U +#define SC_R_DMA_1_CH22 130U +#define SC_R_DMA_1_CH23 131U +#define SC_R_DMA_1_CH24 132U +#define SC_R_DMA_1_CH25 133U +#define SC_R_DMA_1_CH26 134U +#define SC_R_DMA_1_CH27 135U +#define SC_R_DMA_1_CH28 136U +#define SC_R_DMA_1_CH29 137U +#define SC_R_DMA_1_CH30 138U +#define SC_R_DMA_1_CH31 139U +#define SC_R_V2X_PID0 140U +#define SC_R_V2X_PID1 141U +#define SC_R_V2X_PID2 142U +#define SC_R_V2X_PID3 143U +#define SC_R_GPU_0_PID0 144U +#define SC_R_GPU_0_PID1 145U +#define SC_R_GPU_0_PID2 146U +#define SC_R_GPU_0_PID3 147U +#define SC_R_GPU_1_PID0 148U +#define SC_R_GPU_1_PID1 149U +#define SC_R_GPU_1_PID2 150U +#define SC_R_GPU_1_PID3 151U +#define SC_R_PCIE_A 152U +#define SC_R_SERDES_0 153U +#define SC_R_MATCH_0 154U +#define SC_R_MATCH_1 155U +#define SC_R_MATCH_2 156U +#define SC_R_MATCH_3 157U +#define SC_R_MATCH_4 158U +#define SC_R_MATCH_5 159U +#define SC_R_MATCH_6 160U +#define SC_R_MATCH_7 161U +#define SC_R_MATCH_8 162U +#define SC_R_MATCH_9 163U +#define SC_R_MATCH_10 164U +#define SC_R_MATCH_11 165U +#define SC_R_MATCH_12 166U +#define SC_R_MATCH_13 167U +#define SC_R_MATCH_14 168U +#define SC_R_PCIE_B 169U +#define SC_R_SATA_0 170U +#define SC_R_SERDES_1 171U +#define SC_R_HSIO_GPIO 172U +#define SC_R_MATCH_15 173U +#define SC_R_MATCH_16 174U +#define SC_R_MATCH_17 175U +#define SC_R_MATCH_18 176U +#define SC_R_MATCH_19 177U +#define SC_R_MATCH_20 178U +#define SC_R_MATCH_21 179U +#define SC_R_MATCH_22 180U +#define SC_R_MATCH_23 181U +#define SC_R_MATCH_24 182U +#define SC_R_MATCH_25 183U +#define SC_R_MATCH_26 184U +#define SC_R_MATCH_27 185U +#define SC_R_MATCH_28 186U +#define SC_R_LCD_0 187U +#define SC_R_LCD_0_PWM_0 188U +#define SC_R_LCD_0_I2C_0 189U +#define SC_R_LCD_0_I2C_1 190U +#define SC_R_PWM_0 191U +#define SC_R_PWM_1 192U +#define SC_R_PWM_2 193U +#define SC_R_PWM_3 194U +#define SC_R_PWM_4 195U +#define SC_R_PWM_5 196U +#define SC_R_PWM_6 197U +#define SC_R_PWM_7 198U +#define SC_R_GPIO_0 199U +#define SC_R_GPIO_1 200U +#define SC_R_GPIO_2 201U +#define SC_R_GPIO_3 202U +#define SC_R_GPIO_4 203U +#define SC_R_GPIO_5 204U +#define SC_R_GPIO_6 205U +#define SC_R_GPIO_7 206U +#define SC_R_GPT_0 207U +#define SC_R_GPT_1 208U +#define SC_R_GPT_2 209U +#define SC_R_GPT_3 210U +#define SC_R_GPT_4 211U +#define SC_R_KPP 212U +#define SC_R_MU_0A 213U +#define SC_R_MU_1A 214U +#define SC_R_MU_2A 215U +#define SC_R_MU_3A 216U +#define SC_R_MU_4A 217U +#define SC_R_MU_5A 218U +#define SC_R_MU_6A 219U +#define SC_R_MU_7A 220U +#define SC_R_MU_8A 221U +#define SC_R_MU_9A 222U +#define SC_R_MU_10A 223U +#define SC_R_MU_11A 224U +#define SC_R_MU_12A 225U +#define SC_R_MU_13A 226U +#define SC_R_MU_5B 227U +#define SC_R_MU_6B 228U +#define SC_R_MU_7B 229U +#define SC_R_MU_8B 230U +#define SC_R_MU_9B 231U +#define SC_R_MU_10B 232U +#define SC_R_MU_11B 233U +#define SC_R_MU_12B 234U +#define SC_R_MU_13B 235U +#define SC_R_ROM_0 236U +#define SC_R_FSPI_0 237U +#define SC_R_FSPI_1 238U +#define SC_R_IEE 239U +#define SC_R_IEE_R0 240U +#define SC_R_IEE_R1 241U +#define SC_R_IEE_R2 242U +#define SC_R_IEE_R3 243U +#define SC_R_IEE_R4 244U +#define SC_R_IEE_R5 245U +#define SC_R_IEE_R6 246U +#define SC_R_IEE_R7 247U +#define SC_R_SDHC_0 248U +#define SC_R_SDHC_1 249U +#define SC_R_SDHC_2 250U +#define SC_R_ENET_0 251U +#define SC_R_ENET_1 252U +#define SC_R_MLB_0 253U +#define SC_R_DMA_2_CH0 254U +#define SC_R_DMA_2_CH1 255U +#define SC_R_DMA_2_CH2 256U +#define SC_R_DMA_2_CH3 257U +#define SC_R_DMA_2_CH4 258U +#define SC_R_USB_0 259U +#define SC_R_USB_1 260U +#define SC_R_USB_0_PHY 261U +#define SC_R_USB_2 262U +#define SC_R_USB_2_PHY 263U +#define SC_R_DTCP 264U +#define SC_R_NAND 265U +#define SC_R_LVDS_0 266U +#define SC_R_LVDS_0_PWM_0 267U +#define SC_R_LVDS_0_I2C_0 268U +#define SC_R_LVDS_0_I2C_1 269U +#define SC_R_LVDS_1 270U +#define SC_R_LVDS_1_PWM_0 271U +#define SC_R_LVDS_1_I2C_0 272U +#define SC_R_LVDS_1_I2C_1 273U +#define SC_R_LVDS_2 274U +#define SC_R_LVDS_2_PWM_0 275U +#define SC_R_LVDS_2_I2C_0 276U +#define SC_R_LVDS_2_I2C_1 277U +#define SC_R_M4_0_PID0 278U +#define SC_R_M4_0_PID1 279U +#define SC_R_M4_0_PID2 280U +#define SC_R_M4_0_PID3 281U +#define SC_R_M4_0_PID4 282U +#define SC_R_M4_0_RGPIO 283U +#define SC_R_M4_0_SEMA42 284U +#define SC_R_M4_0_TPM 285U +#define SC_R_M4_0_PIT 286U +#define SC_R_M4_0_UART 287U +#define SC_R_M4_0_I2C 288U +#define SC_R_M4_0_INTMUX 289U +#define SC_R_ENET_0_A0 290U +#define SC_R_ENET_0_A1 291U +#define SC_R_M4_0_MU_0B 292U +#define SC_R_M4_0_MU_0A0 293U +#define SC_R_M4_0_MU_0A1 294U +#define SC_R_M4_0_MU_0A2 295U +#define SC_R_M4_0_MU_0A3 296U +#define SC_R_M4_0_MU_1A 297U +#define SC_R_M4_1_PID0 298U +#define SC_R_M4_1_PID1 299U +#define SC_R_M4_1_PID2 300U +#define SC_R_M4_1_PID3 301U +#define SC_R_M4_1_PID4 302U +#define SC_R_M4_1_RGPIO 303U +#define SC_R_M4_1_SEMA42 304U +#define SC_R_M4_1_TPM 305U +#define SC_R_M4_1_PIT 306U +#define SC_R_M4_1_UART 307U +#define SC_R_M4_1_I2C 308U +#define SC_R_M4_1_INTMUX 309U +#define SC_R_UNUSED17 310U +#define SC_R_UNUSED18 311U +#define SC_R_M4_1_MU_0B 312U +#define SC_R_M4_1_MU_0A0 313U +#define SC_R_M4_1_MU_0A1 314U +#define SC_R_M4_1_MU_0A2 315U +#define SC_R_M4_1_MU_0A3 316U +#define SC_R_M4_1_MU_1A 317U +#define SC_R_SAI_0 318U +#define SC_R_SAI_1 319U +#define SC_R_SAI_2 320U +#define SC_R_IRQSTR_SCU2 321U +#define SC_R_IRQSTR_DSP 322U +#define SC_R_ELCDIF_PLL 323U +#define SC_R_OCRAM 324U +#define SC_R_AUDIO_PLL_0 325U +#define SC_R_PI_0 326U +#define SC_R_PI_0_PWM_0 327U +#define SC_R_PI_0_PWM_1 328U +#define SC_R_PI_0_I2C_0 329U +#define SC_R_PI_0_PLL 330U +#define SC_R_PI_1 331U +#define SC_R_PI_1_PWM_0 332U +#define SC_R_PI_1_PWM_1 333U +#define SC_R_PI_1_I2C_0 334U +#define SC_R_PI_1_PLL 335U +#define SC_R_SC_PID0 336U +#define SC_R_SC_PID1 337U +#define SC_R_SC_PID2 338U +#define SC_R_SC_PID3 339U +#define SC_R_SC_PID4 340U +#define SC_R_SC_SEMA42 341U +#define SC_R_SC_TPM 342U +#define SC_R_SC_PIT 343U +#define SC_R_SC_UART 344U +#define SC_R_SC_I2C 345U +#define SC_R_SC_MU_0B 346U +#define SC_R_SC_MU_0A0 347U +#define SC_R_SC_MU_0A1 348U +#define SC_R_SC_MU_0A2 349U +#define SC_R_SC_MU_0A3 350U +#define SC_R_SC_MU_1A 351U +#define SC_R_SYSCNT_RD 352U +#define SC_R_SYSCNT_CMP 353U +#define SC_R_DEBUG 354U +#define SC_R_SYSTEM 355U +#define SC_R_SNVS 356U +#define SC_R_OTP 357U +#define SC_R_VPU_PID0 358U +#define SC_R_VPU_PID1 359U +#define SC_R_VPU_PID2 360U +#define SC_R_VPU_PID3 361U +#define SC_R_VPU_PID4 362U +#define SC_R_VPU_PID5 363U +#define SC_R_VPU_PID6 364U +#define SC_R_VPU_PID7 365U +#define SC_R_ENET_0_A2 366U +#define SC_R_ENET_1_A0 367U +#define SC_R_ENET_1_A1 368U +#define SC_R_ENET_1_A2 369U +#define SC_R_ENET_1_A3 370U +#define SC_R_ENET_1_A4 371U +#define SC_R_DMA_4_CH0 372U +#define SC_R_DMA_4_CH1 373U +#define SC_R_DMA_4_CH2 374U +#define SC_R_DMA_4_CH3 375U +#define SC_R_DMA_4_CH4 376U +#define SC_R_ISI_CH0 377U +#define SC_R_ISI_CH1 378U +#define SC_R_ISI_CH2 379U +#define SC_R_ISI_CH3 380U +#define SC_R_ISI_CH4 381U +#define SC_R_ISI_CH5 382U +#define SC_R_ISI_CH6 383U +#define SC_R_ISI_CH7 384U +#define SC_R_MJPEG_DEC_S0 385U +#define SC_R_MJPEG_DEC_S1 386U +#define SC_R_MJPEG_DEC_S2 387U +#define SC_R_MJPEG_DEC_S3 388U +#define SC_R_MJPEG_ENC_S0 389U +#define SC_R_MJPEG_ENC_S1 390U +#define SC_R_MJPEG_ENC_S2 391U +#define SC_R_MJPEG_ENC_S3 392U +#define SC_R_MIPI_0 393U +#define SC_R_MIPI_0_PWM_0 394U +#define SC_R_MIPI_0_I2C_0 395U +#define SC_R_MIPI_0_I2C_1 396U +#define SC_R_MIPI_1 397U +#define SC_R_MIPI_1_PWM_0 398U +#define SC_R_MIPI_1_I2C_0 399U +#define SC_R_MIPI_1_I2C_1 400U +#define SC_R_CSI_0 401U +#define SC_R_CSI_0_PWM_0 402U +#define SC_R_CSI_0_I2C_0 403U +#define SC_R_CSI_1 404U +#define SC_R_CSI_1_PWM_0 405U +#define SC_R_CSI_1_I2C_0 406U +#define SC_R_HDMI 407U +#define SC_R_HDMI_I2S 408U +#define SC_R_HDMI_I2C_0 409U +#define SC_R_HDMI_PLL_0 410U +#define SC_R_HDMI_RX 411U +#define SC_R_HDMI_RX_BYPASS 412U +#define SC_R_HDMI_RX_I2C_0 413U +#define SC_R_ASRC_0 414U +#define SC_R_ESAI_0 415U +#define SC_R_SPDIF_0 416U +#define SC_R_SPDIF_1 417U +#define SC_R_SAI_3 418U +#define SC_R_SAI_4 419U +#define SC_R_SAI_5 420U +#define SC_R_GPT_5 421U +#define SC_R_GPT_6 422U +#define SC_R_GPT_7 423U +#define SC_R_GPT_8 424U +#define SC_R_GPT_9 425U +#define SC_R_GPT_10 426U +#define SC_R_DMA_2_CH5 427U +#define SC_R_DMA_2_CH6 428U +#define SC_R_DMA_2_CH7 429U +#define SC_R_DMA_2_CH8 430U +#define SC_R_DMA_2_CH9 431U +#define SC_R_DMA_2_CH10 432U +#define SC_R_DMA_2_CH11 433U +#define SC_R_DMA_2_CH12 434U +#define SC_R_DMA_2_CH13 435U +#define SC_R_DMA_2_CH14 436U +#define SC_R_DMA_2_CH15 437U +#define SC_R_DMA_2_CH16 438U +#define SC_R_DMA_2_CH17 439U +#define SC_R_DMA_2_CH18 440U +#define SC_R_DMA_2_CH19 441U +#define SC_R_DMA_2_CH20 442U +#define SC_R_DMA_2_CH21 443U +#define SC_R_DMA_2_CH22 444U +#define SC_R_DMA_2_CH23 445U +#define SC_R_DMA_2_CH24 446U +#define SC_R_DMA_2_CH25 447U +#define SC_R_DMA_2_CH26 448U +#define SC_R_DMA_2_CH27 449U +#define SC_R_DMA_2_CH28 450U +#define SC_R_DMA_2_CH29 451U +#define SC_R_DMA_2_CH30 452U +#define SC_R_DMA_2_CH31 453U +#define SC_R_ASRC_1 454U +#define SC_R_ESAI_1 455U +#define SC_R_SAI_6 456U +#define SC_R_SAI_7 457U +#define SC_R_AMIX 458U +#define SC_R_MQS_0 459U +#define SC_R_DMA_3_CH0 460U +#define SC_R_DMA_3_CH1 461U +#define SC_R_DMA_3_CH2 462U +#define SC_R_DMA_3_CH3 463U +#define SC_R_DMA_3_CH4 464U +#define SC_R_DMA_3_CH5 465U +#define SC_R_DMA_3_CH6 466U +#define SC_R_DMA_3_CH7 467U +#define SC_R_DMA_3_CH8 468U +#define SC_R_DMA_3_CH9 469U +#define SC_R_DMA_3_CH10 470U +#define SC_R_DMA_3_CH11 471U +#define SC_R_DMA_3_CH12 472U +#define SC_R_DMA_3_CH13 473U +#define SC_R_DMA_3_CH14 474U +#define SC_R_DMA_3_CH15 475U +#define SC_R_DMA_3_CH16 476U +#define SC_R_DMA_3_CH17 477U +#define SC_R_DMA_3_CH18 478U +#define SC_R_DMA_3_CH19 479U +#define SC_R_DMA_3_CH20 480U +#define SC_R_DMA_3_CH21 481U +#define SC_R_DMA_3_CH22 482U +#define SC_R_DMA_3_CH23 483U +#define SC_R_DMA_3_CH24 484U +#define SC_R_DMA_3_CH25 485U +#define SC_R_DMA_3_CH26 486U +#define SC_R_DMA_3_CH27 487U +#define SC_R_DMA_3_CH28 488U +#define SC_R_DMA_3_CH29 489U +#define SC_R_DMA_3_CH30 490U +#define SC_R_DMA_3_CH31 491U +#define SC_R_AUDIO_PLL_1 492U +#define SC_R_AUDIO_CLK_0 493U +#define SC_R_AUDIO_CLK_1 494U +#define SC_R_MCLK_OUT_0 495U +#define SC_R_MCLK_OUT_1 496U +#define SC_R_PMIC_0 497U +#define SC_R_PMIC_1 498U +#define SC_R_SECO 499U +#define SC_R_CAAM_JR1 500U +#define SC_R_CAAM_JR2 501U +#define SC_R_CAAM_JR3 502U +#define SC_R_SECO_MU_2 503U +#define SC_R_SECO_MU_3 504U +#define SC_R_SECO_MU_4 505U +#define SC_R_HDMI_RX_PWM_0 506U +#define SC_R_A35 507U +#define SC_R_A35_0 508U +#define SC_R_A35_1 509U +#define SC_R_A35_2 510U +#define SC_R_A35_3 511U +#define SC_R_DSP 512U +#define SC_R_DSP_RAM 513U +#define SC_R_CAAM_JR1_OUT 514U +#define SC_R_CAAM_JR2_OUT 515U +#define SC_R_CAAM_JR3_OUT 516U +#define SC_R_VPU_DEC_0 517U +#define SC_R_VPU_ENC_0 518U +#define SC_R_CAAM_JR0 519U +#define SC_R_CAAM_JR0_OUT 520U +#define SC_R_PMIC_2 521U +#define SC_R_DBLOGIC 522U +#define SC_R_HDMI_PLL_1 523U +#define SC_R_BOARD_R0 524U +#define SC_R_BOARD_R1 525U +#define SC_R_BOARD_R2 526U +#define SC_R_BOARD_R3 527U +#define SC_R_BOARD_R4 528U +#define SC_R_BOARD_R5 529U +#define SC_R_BOARD_R6 530U +#define SC_R_BOARD_R7 531U +#define SC_R_MJPEG_DEC_MP 532U +#define SC_R_MJPEG_ENC_MP 533U +#define SC_R_VPU_TS_0 534U +#define SC_R_VPU_MU_0 535U +#define SC_R_VPU_MU_1 536U +#define SC_R_VPU_MU_2 537U +#define SC_R_VPU_MU_3 538U +#define SC_R_VPU_ENC_1 539U +#define SC_R_VPU 540U +#define SC_R_DMA_5_CH0 541U +#define SC_R_DMA_5_CH1 542U +#define SC_R_DMA_5_CH2 543U +#define SC_R_DMA_5_CH3 544U +#define SC_R_ATTESTATION 545U +#define SC_R_LAST 546U +#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /* All resources */ +/*@}*/ + +/*! + * Define for ATF/Linux. Not used by SCFW. Not a valid parameter + * for any SCFW API calls! + */ +#define SC_R_NONE 0xFFF0U + +/* NOTE - please add by replacing some of the UNUSED from above! */ + +/*! + * Defines for sc_ctrl_t. + */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_CALIB0 46U +#define SC_C_CALIB1 47U +#define SC_C_CALIB2 48U +#define SC_C_IPG_DEBUG 49U +#define SC_C_IPG_DOZE 50U +#define SC_C_IPG_WAIT 51U +#define SC_C_IPG_STOP 52U +#define SC_C_IPG_STOP_MODE 53U +#define SC_C_IPG_STOP_ACK 54U +#define SC_C_SYNC_CTRL 55U +#define SC_C_OFS_AUDIO_ALT 56U +#define SC_C_DSP_BYP 57U +#define SC_C_LAST 58U + +#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /* All pads */ + +/* Types */ + +/*! + * This type is used to store a boolean + */ +typedef uint8_t sc_bool_t; + +/*! + * This type is used to store a system (full-size) address. + */ +typedef uint64_t sc_faddr_t; + +/*! + * This type is used to indicate error response for most functions. + */ +typedef uint8_t sc_err_t; + +/*! + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +typedef uint32_t sc_rsrc_t; + +/*! + * This type is used to indicate a control. + */ +typedef uint32_t sc_ctrl_t; + +/*! + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef uint16_t sc_pad_t; + +/* Extra documentation of standard types */ + +#ifdef DOXYGEN + /*! + * Type used to declare an 8-bit integer. + */ +typedef __INT8_TYPE__ int8_t; + + /*! + * Type used to declare a 16-bit integer. + */ +typedef __INT16_TYPE__ int16_t; + + /*! + * Type used to declare a 32-bit integer. + */ +typedef __INT32_TYPE__ int32_t; + + /*! + * Type used to declare a 64-bit integer. + */ +typedef __INT64_TYPE__ int64_t; + + /*! + * Type used to declare an 8-bit unsigned integer. + */ +typedef __UINT8_TYPE__ uint8_t; + + /*! + * Type used to declare a 16-bit unsigned integer. + */ +typedef __UINT16_TYPE__ uint16_t; + + /*! + * Type used to declare a 32-bit unsigned integer. + */ +typedef __UINT32_TYPE__ uint32_t; + + /*! + * Type used to declare a 64-bit unsigned integer. + */ +typedef __UINT64_TYPE__ uint64_t; +#endif + +#endif /* SC_TYPES_H */ diff --git a/include/soc/imx8/soc.h b/include/soc/imx8/soc.h new file mode 100644 index 000000000000..376c58d2588a --- /dev/null +++ b/include/soc/imx8/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef __SOC_IMX8_SOC_H__ +#define __SOC_IMX8_SOC_H__ + +#define IMX_SOC_IMX8QM 0x01 +#define IMX_SOC_IMX8QXP 0x02 +#define IMX_SOC_IMX8MQ 0x82 + +bool cpu_is_imx8qm(void); +bool cpu_is_imx8mq(void); +bool cpu_is_imx8qxp(void); + +extern bool TKT340553_SW_WORKAROUND; +unsigned int imx8_get_soc_revision(void); + +int check_m4_enabled(void); +bool check_hdcp_enabled(void); + +#endif diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h index 67be2445941a..267192c22e6a 100644 --- a/include/sound/dmaengine_pcm.h +++ b/include/sound/dmaengine_pcm.h @@ -74,6 +74,8 @@ struct dma_chan *snd_dmaengine_pcm_get_chan(struct snd_pcm_substream *substream) * @chan_name: Custom channel name to use when requesting DMA channel. * @fifo_size: FIFO size of the DAI controller in bytes * @flags: PCM_DAI flags, only SND_DMAENGINE_PCM_DAI_FLAG_PACK for now + * @check_xrun: check if hardware xrun happen in the cpu dai. + * @device_reset: if xrun happened, then do cpu dai reset. */ struct snd_dmaengine_dai_dma_data { dma_addr_t addr; @@ -84,6 +86,17 @@ struct snd_dmaengine_dai_dma_data { const char *chan_name; unsigned int fifo_size; unsigned int flags; + unsigned int fifo_num; + bool (*check_xrun)(struct snd_pcm_substream *substream); + void (*device_reset)(struct snd_pcm_substream *substream, bool stop); +}; + +struct dmaengine_pcm_runtime_data { + struct dma_chan *dma_chan; + dma_cookie_t cookie; + + unsigned int pos; + dma_async_tx_callback callback; }; void snd_dmaengine_pcm_set_config_from_dai_data( diff --git a/include/sound/soc.h b/include/sound/soc.h index d22de9712c45..d90b76e99bbf 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -1077,6 +1077,7 @@ struct snd_soc_dai_link { /* DPCM used FE & BE merged format */ unsigned int dpcm_merged_format:1; + unsigned int dpcm_merged_chan:1; /* pmdown_time is ignored at stop */ unsigned int ignore_pmdown_time:1; diff --git a/include/trace/events/cpufreq_interactive.h b/include/trace/events/cpufreq_interactive.h new file mode 100644 index 000000000000..faecc0bfdeff --- /dev/null +++ b/include/trace/events/cpufreq_interactive.h @@ -0,0 +1,112 @@ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM cpufreq_interactive + +#if !defined(_TRACE_CPUFREQ_INTERACTIVE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_CPUFREQ_INTERACTIVE_H + +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(set, + TP_PROTO(u32 cpu_id, unsigned long targfreq, + unsigned long actualfreq), + TP_ARGS(cpu_id, targfreq, actualfreq), + + TP_STRUCT__entry( + __field(u32, cpu_id) + __field(unsigned long, targfreq) + __field(unsigned long, actualfreq) + ), + + TP_fast_assign( + __entry->cpu_id = (u32)cpu_id; + __entry->targfreq = targfreq; + __entry->actualfreq = actualfreq; + ), + + TP_printk("cpu=%u targ=%lu actual=%lu", + __entry->cpu_id, __entry->targfreq, + __entry->actualfreq) +); + +DEFINE_EVENT(set, cpufreq_interactive_setspeed, + TP_PROTO(u32 cpu_id, unsigned long targfreq, + unsigned long actualfreq), + TP_ARGS(cpu_id, targfreq, actualfreq) +); + +DECLARE_EVENT_CLASS(loadeval, + TP_PROTO(unsigned long cpu_id, unsigned long load, + unsigned long curtarg, unsigned long curactual, + unsigned long newtarg), + TP_ARGS(cpu_id, load, curtarg, curactual, newtarg), + + TP_STRUCT__entry( + __field(unsigned long, cpu_id) + __field(unsigned long, load) + __field(unsigned long, curtarg) + __field(unsigned long, curactual) + __field(unsigned long, newtarg) + ), + + TP_fast_assign( + __entry->cpu_id = cpu_id; + __entry->load = load; + __entry->curtarg = curtarg; + __entry->curactual = curactual; + __entry->newtarg = newtarg; + ), + + TP_printk("cpu=%lu load=%lu cur=%lu actual=%lu targ=%lu", + __entry->cpu_id, __entry->load, __entry->curtarg, + __entry->curactual, __entry->newtarg) +); + +DEFINE_EVENT(loadeval, cpufreq_interactive_target, + TP_PROTO(unsigned long cpu_id, unsigned long load, + unsigned long curtarg, unsigned long curactual, + unsigned long newtarg), + TP_ARGS(cpu_id, load, curtarg, curactual, newtarg) +); + +DEFINE_EVENT(loadeval, cpufreq_interactive_already, + TP_PROTO(unsigned long cpu_id, unsigned long load, + unsigned long curtarg, unsigned long curactual, + unsigned long newtarg), + TP_ARGS(cpu_id, load, curtarg, curactual, newtarg) +); + +DEFINE_EVENT(loadeval, cpufreq_interactive_notyet, + TP_PROTO(unsigned long cpu_id, unsigned long load, + unsigned long curtarg, unsigned long curactual, + unsigned long newtarg), + TP_ARGS(cpu_id, load, curtarg, curactual, newtarg) +); + +TRACE_EVENT(cpufreq_interactive_boost, + TP_PROTO(const char *s), + TP_ARGS(s), + TP_STRUCT__entry( + __string(s, s) + ), + TP_fast_assign( + __assign_str(s, s); + ), + TP_printk("%s", __get_str(s)) +); + +TRACE_EVENT(cpufreq_interactive_unboost, + TP_PROTO(const char *s), + TP_ARGS(s), + TP_STRUCT__entry( + __string(s, s) + ), + TP_fast_assign( + __assign_str(s, s); + ), + TP_printk("%s", __get_str(s)) +); + +#endif /* _TRACE_CPUFREQ_INTERACTIVE_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 97677cd6964d..27eb278bb3f2 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -863,6 +863,11 @@ extern "C" { #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) +#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) +#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) +#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) +#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) + /** * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3ad838d3f93f..10e26af753f2 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -140,6 +140,7 @@ extern "C" { #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane, 10-bit per channel */ /* * 3 plane YCbCr @@ -183,6 +184,8 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 +#define DRM_FORMAT_MOD_VENDOR_AMPHION 0x08 +#define DRM_FORMAT_MOD_VENDOR_VSI 0x09 /* add more to the end as needed */ #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) @@ -338,6 +341,15 @@ extern "C" { */ #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) +/* + * Vivante 64x64 super-tiling with compression layout + * + * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile + * contains 8x4 groups of 2x4 tiles of 4x4 pixels each, all in row-major layout + * with compression. + */ +#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED_FC fourcc_mod_code(VIVANTE, 5) + /* NVIDIA Tegra frame buffer modifiers */ /* @@ -403,6 +415,42 @@ extern "C" { */ #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) +/* Amphion tiled layout */ + +/* + * Amphion 8x128 tiling layout + * + * This is a tiled layout using 8x128 pixel vertical strips, where each strip + * contains 1x16 groups of 8x8 pixels in a row-major layout. + */ +#define DRM_FORMAT_MOD_AMPHION_TILED fourcc_mod_code(AMPHION, 1) + +/* Verisilicon framebuffer modifiers */ + +/* + * Verisilicon 8x4 tiling layout + * + * This is G1 VPU tiled layout using tiles of 8x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VSI_G1_TILED fourcc_mod_code(VSI, 1) + +/* + * Verisilicon 4x4 tiling layout + * + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VSI_G2_TILED fourcc_mod_code(VSI, 2) + +/* + * Verisilicon 4x4 tiling with compression layout + * + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major + * layout with compression. + */ +#define DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED fourcc_mod_code(VSI, 3) + #if defined(__cplusplus) } #endif diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 54fc38c3c3f1..f0de943c7e22 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -90,6 +90,13 @@ extern "C" { #define DRM_MODE_PICTURE_ASPECT_4_3 1 #define DRM_MODE_PICTURE_ASPECT_16_9 2 +/* Content type options */ +#define DRM_MODE_CONTENT_TYPE_NO_DATA 0 +#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1 +#define DRM_MODE_CONTENT_TYPE_PHOTO 2 +#define DRM_MODE_CONTENT_TYPE_CINEMA 3 +#define DRM_MODE_CONTENT_TYPE_GAME 4 + /* Aspect ratio flag bitmask (4 bits 22:19) */ #define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19) #define DRM_MODE_FLAG_PIC_AR_NONE \ @@ -173,6 +180,10 @@ extern "C" { DRM_MODE_REFLECT_X | \ DRM_MODE_REFLECT_Y) +/* Content Protection Flags */ +#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0 +#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1 +#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2 struct drm_mode_modeinfo { __u32 clock; @@ -590,6 +601,27 @@ struct drm_color_lut { __u16 reserved; }; +enum supported_eotf_type { + TRADITIONAL_GAMMA_SDR = 0, + TRADITIONA_GAMMA_HDR, + SMPTE_ST2084, + FUTURE_EOTF +}; + +/* HDR Metadata */ +struct hdr_static_metadata { + uint8_t eotf; + uint8_t type; + uint16_t display_primaries_x[3]; + uint16_t display_primaries_y[3]; + uint16_t white_point_x; + uint16_t white_point_y; + uint16_t max_mastering_display_luminance; + uint16_t min_mastering_display_luminance; + uint16_t max_fall; + uint16_t max_cll; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 @@ -782,6 +814,72 @@ struct drm_mode_destroy_blob { __u32 blob_id; }; +/** + * Lease mode resources, creating another drm_master. + */ +struct drm_mode_create_lease { + /** Pointer to array of object ids (__u32) */ + __u64 object_ids; + /** Number of object ids */ + __u32 object_count; + /** flags for new FD (O_CLOEXEC, etc) */ + __u32 flags; + + /** Return: unique identifier for lessee. */ + __u32 lessee_id; + /** Return: file descriptor to new drm_master file */ + __u32 fd; +}; + +/** + * List lesses from a drm_master + */ +struct drm_mode_list_lessees { + /** Number of lessees. + * On input, provides length of the array. + * On output, provides total number. No + * more than the input number will be written + * back, so two calls can be used to get + * the size and then the data. + */ + __u32 count_lessees; + __u32 pad; + + /** Pointer to lessees. + * pointer to __u64 array of lessee ids + */ + __u64 lessees_ptr; +}; + +/** + * Get leased objects + */ +struct drm_mode_get_lease { + /** Number of leased objects. + * On input, provides length of the array. + * On output, provides total number. No + * more than the input number will be written + * back, so two calls can be used to get + * the size and then the data. + */ + __u32 count_objects; + __u32 pad; + + /** Pointer to objects. + * pointer to __u32 array of object ids + */ + __u64 objects_ptr; +}; + +/** + * Revoke lease + */ +struct drm_mode_revoke_lease { + /** Unique ID of lessee + */ + __u32 lessee_id; +}; + #if defined(__cplusplus) } #endif diff --git a/include/uapi/drm/imx_drm.h b/include/uapi/drm/imx_drm.h new file mode 100644 index 000000000000..e80cad4be8bd --- /dev/null +++ b/include/uapi/drm/imx_drm.h @@ -0,0 +1,89 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _UAPI_IMX_DRM_H_ +#define _UAPI_IMX_DRM_H_ + +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * Dpu frame info. + * + */ +struct drm_imx_dpu_frame_info { + __u32 width; + __u32 height; + __u32 x_offset; + __u32 y_offset; + __u32 stride; + __u32 format; + __u64 modifier; + __u64 baddr; + __u64 uv_addr; +}; + +#define DRM_IMX_DPU_SET_CMDLIST 0x00 +#define DRM_IMX_DPU_WAIT 0x01 +#define DRM_IMX_DPU_GET_PARAM 0x02 + +#define DRM_IOCTL_IMX_DPU_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_IMX_DPU_SET_CMDLIST, struct drm_imx_dpu_set_cmdlist) +#define DRM_IOCTL_IMX_DPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_IMX_DPU_WAIT, struct drm_imx_dpu_wait) +#define DRM_IOCTL_IMX_DPU_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_IMX_DPU_GET_PARAM, enum drm_imx_dpu_param) + +/** + * struct drm_imx_dpu_set_cmdlist - ioctl argument for + * DRM_IMX_DPU_SET_CMDLIST. + */ +struct drm_imx_dpu_set_cmdlist { + __u64 cmd; + __u32 cmd_nr; + + /* reserved */ + __u64 user_data; +}; + +/** + * struct drm_imx_dpu_wait - ioctl argument for + * DRM_IMX_DPU_WAIT. + * + */ +struct drm_imx_dpu_wait { + /* reserved */ + __u64 user_data; +}; + +/** + * enum drm_imx_dpu_param - ioctl argument for + * DRM_IMX_DPU_GET_PARAM. + * + */ +enum drm_imx_dpu_param { + DRM_IMX_MAX_DPUS, +}; + +#if defined(__cplusplus) +} +#endif + +#endif /* _UAPI_IMX_DRM_H_ */ diff --git a/include/uapi/linux/dma-buf.h b/include/uapi/linux/dma-buf.h index d75df5210a4a..f0eef45dd19f 100644 --- a/include/uapi/linux/dma-buf.h +++ b/include/uapi/linux/dma-buf.h @@ -27,6 +27,10 @@ struct dma_buf_sync { __u64 flags; }; +struct dma_buf_phys { + __u64 phys; +}; + #define DMA_BUF_SYNC_READ (1 << 0) #define DMA_BUF_SYNC_WRITE (2 << 0) #define DMA_BUF_SYNC_RW (DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE) @@ -37,5 +41,6 @@ struct dma_buf_sync { #define DMA_BUF_BASE 'b' #define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) +#define DMA_BUF_IOCTL_PHYS _IOW(DMA_BUF_BASE, 1, struct dma_buf_phys) #endif diff --git a/include/uapi/linux/hantrodec.h b/include/uapi/linux/hantrodec.h new file mode 100755 index 000000000000..4add50e85299 --- /dev/null +++ b/include/uapi/linux/hantrodec.h @@ -0,0 +1,93 @@ +/***************************************************************************** +* +* The GPL License (GPL) +* +* Copyright (c) 2015-2017, VeriSilicon Inc. +* Copyright (c) 2011-2014, Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software Foundation, +* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +* +*****************************************************************************/ + +#ifndef _UAPI_HANTRODEC_H_ +#define _UAPI_HANTRODEC_H_ +#include <linux/ioctl.h> +#include <linux/types.h> + +#undef PDEBUG +#ifdef HANTRODEC_DEBUG +# ifdef __KERNEL__ +# define PDEBUG(fmt, args...) pr_info("hantrodec: " fmt, ## args) +# else +# define PDEBUG(fmt, args...) fprintf(stderr, fmt, ## args) +# endif +#else +# define PDEBUG(fmt, args...) +#endif + +struct core_desc { + __u32 id; /* id of the Core */ + __u32 *regs; /* pointer to user registers */ + __u32 size; /* size of register space */ +}; + +/* Use 'k' as magic number */ +#define HANTRODEC_IOC_MAGIC 'k' + +/* + * S means "Set" through a ptr, + * T means "Tell" directly with the argument value + * G means "Get": reply by setting through a pointer + * Q means "Query": response is on the return value + * X means "eXchange": G and S atomically + * H means "sHift": T and Q atomically + */ + +#define HANTRODEC_PP_INSTANCE _IO(HANTRODEC_IOC_MAGIC, 1) +#define HANTRODEC_HW_PERFORMANCE _IO(HANTRODEC_IOC_MAGIC, 2) +#define HANTRODEC_IOCGHWOFFSET _IOR(HANTRODEC_IOC_MAGIC, 3, unsigned long *) +#define HANTRODEC_IOCGHWIOSIZE _IOR(HANTRODEC_IOC_MAGIC, 4, unsigned int *) + +#define HANTRODEC_IOC_CLI _IO(HANTRODEC_IOC_MAGIC, 5) +#define HANTRODEC_IOC_STI _IO(HANTRODEC_IOC_MAGIC, 6) +#define HANTRODEC_IOC_MC_OFFSETS _IOR(HANTRODEC_IOC_MAGIC, 7, unsigned long *) +#define HANTRODEC_IOC_MC_CORES _IOR(HANTRODEC_IOC_MAGIC, 8, unsigned int *) + + +#define HANTRODEC_IOCS_DEC_PUSH_REG _IOW(HANTRODEC_IOC_MAGIC, 9, struct core_desc *) +#define HANTRODEC_IOCS_PP_PUSH_REG _IOW(HANTRODEC_IOC_MAGIC, 10, struct core_desc *) + +#define HANTRODEC_IOCH_DEC_RESERVE _IO(HANTRODEC_IOC_MAGIC, 11) +#define HANTRODEC_IOCT_DEC_RELEASE _IO(HANTRODEC_IOC_MAGIC, 12) +#define HANTRODEC_IOCQ_PP_RESERVE _IO(HANTRODEC_IOC_MAGIC, 13) +#define HANTRODEC_IOCT_PP_RELEASE _IO(HANTRODEC_IOC_MAGIC, 14) + +#define HANTRODEC_IOCX_DEC_WAIT _IOWR(HANTRODEC_IOC_MAGIC, 15, struct core_desc *) +#define HANTRODEC_IOCX_PP_WAIT _IOWR(HANTRODEC_IOC_MAGIC, 16, struct core_desc *) + +#define HANTRODEC_IOCS_DEC_PULL_REG _IOWR(HANTRODEC_IOC_MAGIC, 17, struct core_desc *) +#define HANTRODEC_IOCS_PP_PULL_REG _IOWR(HANTRODEC_IOC_MAGIC, 18, struct core_desc *) + +#define HANTRODEC_IOCG_CORE_WAIT _IOR(HANTRODEC_IOC_MAGIC, 19, int *) + +#define HANTRODEC_IOX_ASIC_ID _IOWR(HANTRODEC_IOC_MAGIC, 20, __u32 *) + +#define HANTRODEC_IOCG_CORE_ID _IO(HANTRODEC_IOC_MAGIC, 21) + +#define HANTRODEC_DEBUG_STATUS _IO(HANTRODEC_IOC_MAGIC, 29) + +#define HANTRODEC_IOC_MAXNR 29 + +#endif /* !_UAPI_HANTRODEC_H_ */ diff --git a/include/uapi/linux/hx280enc.h b/include/uapi/linux/hx280enc.h new file mode 100755 index 000000000000..d465c25f9f66 --- /dev/null +++ b/include/uapi/linux/hx280enc.h @@ -0,0 +1,79 @@ + /***************************************************************************** + * Encoder device driver (kernel module header) + * + * Copyright (C) 2012 Google Finland Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * +-------------------------------------------------------------------------------- +-- +-- Abstract : 6280/7280/8270/8290/H1 Encoder device driver (kernel module) +-- +*****************************************************************************/ +#ifndef _UAPI_HX280ENC_H_ +#define _UAPI_HX280ENC_H_ +#include <linux/ioctl.h> /* needed for the _IOW etc stuff used later */ + +/* + * Macros to help debugging + */ + +#undef PDEBUG /* undef it, just in case */ +#ifdef HX280ENC_DEBUG +# ifdef __KERNEL__ + /* This one if debugging is on, and kernel space */ +# define PDEBUG(fmt, args...) printk(KERN_INFO "hmp4e: " fmt, ## args) +# else + /* This one for user space */ +# define PDEBUG(fmt, args...) printf(__FILE__ ":%d: " fmt, __LINE__, ## args) +# endif +#else +# define PDEBUG(fmt, args...) /* not debugging: nothing */ +#endif + +/* + * Ioctl definitions + */ + +/* Use 'k' as magic number */ +#define HX280ENC_IOC_MAGIC 'k' +/* + * S means "Set" through a ptr, + * T means "Tell" directly with the argument value + * G means "Get": reply by setting through a pointer + * Q means "Query": response is on the return value + * X means "eXchange": G and S atomically + * H means "sHift": T and Q atomically + */ + /* + * #define HX280ENC_IOCGBUFBUSADDRESS _IOR(HX280ENC_IOC_MAGIC, 1, unsigned long *) + * #define HX280ENC_IOCGBUFSIZE _IOR(HX280ENC_IOC_MAGIC, 2, unsigned int *) + */ +#define HX280ENC_IOCGHWOFFSET _IOR(HX280ENC_IOC_MAGIC, 3, unsigned long *) +#define HX280ENC_IOCGHWIOSIZE _IOR(HX280ENC_IOC_MAGIC, 4, unsigned int *) +#define HX280ENC_IOC_CLI _IO(HX280ENC_IOC_MAGIC, 5) +#define HX280ENC_IOC_STI _IO(HX280ENC_IOC_MAGIC, 6) +#define HX280ENC_IOCXVIRT2BUS _IOWR(HX280ENC_IOC_MAGIC, 7, unsigned long *) + +#define HX280ENC_IOCHARDRESET _IO(HX280ENC_IOC_MAGIC, 8) /* debugging tool */ +#define HX280ENC_IOCGSRAMOFFSET _IOR(HX280ENC_IOC_MAGIC, 9, unsigned long *) +#define HX280ENC_IOCGSRAMEIOSIZE _IOR(HX280ENC_IOC_MAGIC, 10, unsigned int *) + +#define HX280ENC_IOCH_ENC_RESERVE _IOR(HX280ENC_IOC_MAGIC, 11, unsigned int *) +#define HX280ENC_IOCH_ENC_RELEASE _IOR(HX280ENC_IOC_MAGIC, 12, unsigned int *) +#define HX280ENC_IOCG_CORE_WAIT _IOR(HX280ENC_IOC_MAGIC, 13, unsigned int *) +#define HX280ENC_IOC_MAXNR 30 + +#endif /* !_UAPI_HX280ENC_H_ */ diff --git a/include/uapi/linux/ipu.h b/include/uapi/linux/ipu.h new file mode 100644 index 000000000000..c92f292bcc9d --- /dev/null +++ b/include/uapi/linux/ipu.h @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup IPU MXC Image Processing Unit (IPU) Driver + */ +/*! + * @file uapi/linux/ipu.h + * + * @brief This file contains the IPU driver API declarations. + * + * @ingroup IPU + */ + +#ifndef __ASM_ARCH_IPU_H__ +#define __ASM_ARCH_IPU_H__ + +#include <linux/types.h> +#include <linux/videodev2.h> + +#ifndef __KERNEL__ +#ifndef __cplusplus +typedef unsigned char bool; +#endif +#define irqreturn_t int +#define dma_addr_t int +#define uint32_t unsigned int +#define uint16_t unsigned short +#define uint8_t unsigned char +#define u32 unsigned int +#define u8 unsigned char +#define __u32 u32 +#endif + +/*! + * Enumeration of IPU rotation modes + */ +typedef enum { + /* Note the enum values correspond to BAM value */ + IPU_ROTATE_NONE = 0, + IPU_ROTATE_VERT_FLIP = 1, + IPU_ROTATE_HORIZ_FLIP = 2, + IPU_ROTATE_180 = 3, + IPU_ROTATE_90_RIGHT = 4, + IPU_ROTATE_90_RIGHT_VFLIP = 5, + IPU_ROTATE_90_RIGHT_HFLIP = 6, + IPU_ROTATE_90_LEFT = 7, +} ipu_rotate_mode_t; + +/*! + * Enumeration of VDI MOTION select + */ +typedef enum { + MED_MOTION = 0, + LOW_MOTION = 1, + HIGH_MOTION = 2, +} ipu_motion_sel; + +/*! + * Enumeration of DI ports for ADC. + */ +typedef enum { + DISP0, + DISP1, + DISP2, + DISP3 +} display_port_t; + +/* IPU Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/*! + * @name IPU Pixel Formats + * + * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are + * the same used by V4L2 API. + */ + +/*! @{ */ +/*! @name GPU Tile Formats */ +/*! @{ */ +#define IPU_PIX_FMT_GPU32_SB_ST fourcc('5', 'P', '4', 'S') /*!< 32bit split buf 4x4 standard */ +#define IPU_PIX_FMT_GPU32_SB_SRT fourcc('5', 'P', '4', 'R') /*!< 32bit split buf 4x4 super */ +#define IPU_PIX_FMT_GPU32_ST fourcc('5', 'I', '4', 'S') /*!< 32bit single buf 4x4 standard */ +#define IPU_PIX_FMT_GPU32_SRT fourcc('5', 'I', '4', 'R') /*!< 32bit single buf 4x4 super */ +#define IPU_PIX_FMT_GPU16_SB_ST fourcc('4', 'P', '8', 'S') /*!< 16bit split buf 8x4 standard */ +#define IPU_PIX_FMT_GPU16_SB_SRT fourcc('4', 'P', '8', 'R') /*!< 16bit split buf 8x4 super */ +#define IPU_PIX_FMT_GPU16_ST fourcc('4', 'I', '8', 'S') /*!< 16bit single buf 8x4 standard */ +#define IPU_PIX_FMT_GPU16_SRT fourcc('4', 'I', '8', 'R') /*!< 16bit single buf 8x4 super */ + +/*! @{ */ +/*! @name Generic or Raw Data Formats */ +/*! @{ */ +#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_GENERIC_16 fourcc('I', 'P', 'U', '2') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') /*!< IPU Generic Data */ +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */ +#define IPU_PIX_FMT_BGRA4444 fourcc('4', '4', '4', '4') /*!< 16 RGBA-4-4-4-4 */ +#define IPU_PIX_FMT_BGRA5551 fourcc('5', '5', '5', '1') /*!< 16 RGBA-5-5-5-1 */ +#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define IPU_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */ +#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */ +#define IPU_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */ +#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */ +#define IPU_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */ +#define IPU_PIX_FMT_AYUV fourcc('A', 'Y', 'U', 'V') /*!< 32 AYUV 4:4:4:4 */ +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define PRE_PIX_FMT_NV21 fourcc('N', 'V', '2', '1') /* 12 Y/CbCr 4:2:0 */ +#define IPU_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ +#define PRE_PIX_FMT_NV61 fourcc('N', 'V', '6', '1') /* 16 Y/CbCr 4:2:2 */ +/* two planes -- 12 tiled Y/CbCr 4:2:0 */ +#define IPU_PIX_FMT_TILED_NV12 fourcc('T', 'N', 'V', 'P') +#define IPU_PIX_FMT_TILED_NV12F fourcc('T', 'N', 'V', 'F') + +/*! @} */ +/*! @name YUV Planar Formats */ +/*! @{ */ +#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */ +#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */ +#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */ +#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */ +#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */ +#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */ +/* non-interleaved 4:4:4 */ +#define IPU_PIX_FMT_YUV444P fourcc('4', '4', '4', 'P') /*!< 24 YUV 4:4:4 */ +/*! @} */ +#define IPU_PIX_FMT_TILED_NV12_MBALIGN (16) +#define TILED_NV12_FRAME_SIZE(w, h) \ + (ALIGN((w) * (h), SZ_4K) + ALIGN((w) * (h) / 2, SZ_4K)) +/* IPU device */ +typedef enum { + RGB_CS, + YUV_CS, + NULL_CS +} cs_t; + +struct ipu_pos { + u32 x; + u32 y; +}; + +struct ipu_crop { + struct ipu_pos pos; + u32 w; + u32 h; +}; + +struct ipu_deinterlace { + bool enable; + u8 motion; /*see ipu_motion_sel*/ +#define IPU_DEINTERLACE_FIELD_TOP 0 +#define IPU_DEINTERLACE_FIELD_BOTTOM 1 +#define IPU_DEINTERLACE_FIELD_MASK \ + (IPU_DEINTERLACE_FIELD_TOP | IPU_DEINTERLACE_FIELD_BOTTOM) + /* deinterlace frame rate double flags */ +#define IPU_DEINTERLACE_RATE_EN 0x80 +#define IPU_DEINTERLACE_RATE_FRAME1 0x40 +#define IPU_DEINTERLACE_RATE_MASK \ + (IPU_DEINTERLACE_RATE_EN | IPU_DEINTERLACE_RATE_FRAME1) +#define IPU_DEINTERLACE_MAX_FRAME 2 + u8 field_fmt; +}; + +struct ipu_input { + u32 width; + u32 height; + u32 format; + struct ipu_crop crop; + dma_addr_t paddr; + + struct ipu_deinterlace deinterlace; + dma_addr_t paddr_n; /*valid when deinterlace enable*/ +}; + +struct ipu_alpha { +#define IPU_ALPHA_MODE_GLOBAL 0 +#define IPU_ALPHA_MODE_LOCAL 1 + u8 mode; + u8 gvalue; /* 0~255 */ + dma_addr_t loc_alp_paddr; +}; + +struct ipu_colorkey { + bool enable; + u32 value; /* RGB 24bit */ +}; + +struct ipu_overlay { + u32 width; + u32 height; + u32 format; + struct ipu_crop crop; + struct ipu_alpha alpha; + struct ipu_colorkey colorkey; + dma_addr_t paddr; +}; + +struct ipu_output { + u32 width; + u32 height; + u32 format; + u8 rotate; + struct ipu_crop crop; + dma_addr_t paddr; +}; + +struct ipu_task { + struct ipu_input input; + struct ipu_output output; + + bool overlay_en; + struct ipu_overlay overlay; + +#define IPU_TASK_PRIORITY_NORMAL 0 +#define IPU_TASK_PRIORITY_HIGH 1 + u8 priority; + +#define IPU_TASK_ID_ANY 0 +#define IPU_TASK_ID_VF 1 +#define IPU_TASK_ID_PP 2 +#define IPU_TASK_ID_MAX 3 + u8 task_id; + + int timeout; +}; + +enum { + IPU_CHECK_OK = 0, + IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN = 0x1, + IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN = 0x2, + IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN = 0x4, + IPU_CHECK_ERR_MIN, + IPU_CHECK_ERR_INPUT_CROP, + IPU_CHECK_ERR_OUTPUT_CROP, + IPU_CHECK_ERR_OVERLAY_CROP, + IPU_CHECK_ERR_INPUT_OVER_LIMIT, + IPU_CHECK_ERR_OV_OUT_NO_FIT, + IPU_CHECK_ERR_OVERLAY_WITH_VDI, + IPU_CHECK_ERR_PROC_NO_NEED, + IPU_CHECK_ERR_SPLIT_INPUTW_OVER, + IPU_CHECK_ERR_SPLIT_INPUTH_OVER, + IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER, + IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER, + IPU_CHECK_ERR_SPLIT_WITH_ROT, + IPU_CHECK_ERR_NOT_SUPPORT, + IPU_CHECK_ERR_NOT16ALIGN, + IPU_CHECK_ERR_W_DOWNSIZE_OVER, + IPU_CHECK_ERR_H_DOWNSIZE_OVER, +}; + +/* IOCTL commands */ +#define IPU_CHECK_TASK _IOWR('I', 0x1, struct ipu_task) +#define IPU_QUEUE_TASK _IOW('I', 0x2, struct ipu_task) +#define IPU_ALLOC _IOWR('I', 0x3, int) +#define IPU_FREE _IOW('I', 0x4, int) + +#endif diff --git a/include/uapi/linux/isl29023.h b/include/uapi/linux/isl29023.h new file mode 100644 index 000000000000..9fddf4282573 --- /dev/null +++ b/include/uapi/linux/isl29023.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __UAPI_LINUX_ISL29023_H__ +#define __UAPI_LINUX_ISL29023_H__ + +#include <linux/types.h> + +#define ISL29023_PD_MODE 0x0 +#define ISL29023_ALS_ONCE_MODE 0x1 +#define ISL29023_IR_ONCE_MODE 0x2 +#define ISL29023_ALS_CONT_MODE 0x5 +#define ISL29023_IR_CONT_MODE 0x6 + +#define ISL29023_INT_PERSISTS_1 0x0 +#define ISL29023_INT_PERSISTS_4 0x1 +#define ISL29023_INT_PERSISTS_8 0x2 +#define ISL29023_INT_PERSISTS_16 0x3 + +#define ISL29023_RES_16 0x0 +#define ISL29023_RES_12 0x1 +#define ISL29023_RES_8 0x2 +#define ISL29023_RES_4 0x3 + +#define ISL29023_RANGE_1K 0x0 +#define ISL29023_RANGE_4K 0x1 +#define ISL29023_RANGE_16K 0x2 +#define ISL29023_RANGE_64K 0x3 + +#endif diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 9e3511742fdc..3083f0734264 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,7 +34,7 @@ #define MEDIA_BUS_FMT_FIXED 0x0001 -/* RGB - next is 0x101b */ +/* RGB - next is 0x101f */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 @@ -61,6 +61,10 @@ #define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a +#define MEDIA_BUS_FMT_RGB888_1X30_PADLO 0x101b +#define MEDIA_BUS_FMT_RGB666_1X30_PADLO 0x101c +#define MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG 0x101d +#define MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA 0x101e /* YUV (including grey) - next is 0x202c */ #define MEDIA_BUS_FMT_Y8_1X8 0x2001 diff --git a/include/uapi/linux/mxc_asrc.h b/include/uapi/linux/mxc_asrc.h new file mode 100644 index 000000000000..79059c3be2c4 --- /dev/null +++ b/include/uapi/linux/mxc_asrc.h @@ -0,0 +1,165 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * @file mxc_asrc.h + * + * @brief i.MX Asynchronous Sample Rate Converter + * + * @ingroup Audio + */ + +#ifndef __MXC_ASRC_UAPI_H__ +#define __MXC_ASRC_UAPI_H__ + +#define ASRC_IOC_MAGIC 'C' + +#define ASRC_REQ_PAIR _IOWR(ASRC_IOC_MAGIC, 0, struct asrc_req) +#define ASRC_CONFIG_PAIR _IOWR(ASRC_IOC_MAGIC, 1, struct asrc_config) +#define ASRC_RELEASE_PAIR _IOW(ASRC_IOC_MAGIC, 2, enum asrc_pair_index) +#define ASRC_CONVERT _IOW(ASRC_IOC_MAGIC, 3, struct asrc_convert_buffer) +#define ASRC_START_CONV _IOW(ASRC_IOC_MAGIC, 4, enum asrc_pair_index) +#define ASRC_STOP_CONV _IOW(ASRC_IOC_MAGIC, 5, enum asrc_pair_index) +#define ASRC_STATUS _IOW(ASRC_IOC_MAGIC, 6, struct asrc_status_flags) +#define ASRC_FLUSH _IOW(ASRC_IOC_MAGIC, 7, enum asrc_pair_index) + +enum asrc_pair_index { + ASRC_INVALID_PAIR = -1, + ASRC_PAIR_A = 0, + ASRC_PAIR_B = 1, + ASRC_PAIR_C = 2, + ASRC_PAIR_D = 3, +}; + +enum asrc_inclk { + INCLK_NONE = 0x03, + INCLK_ESAI_RX = 0x00, + INCLK_SSI1_RX = 0x01, + INCLK_SSI2_RX = 0x02, + INCLK_SSI3_RX = 0x07, + INCLK_SPDIF_RX = 0x04, + INCLK_MLB_CLK = 0x05, + INCLK_PAD = 0x06, + INCLK_ESAI_TX = 0x08, + INCLK_SSI1_TX = 0x09, + INCLK_SSI2_TX = 0x0a, + INCLK_SSI3_TX = 0x0b, + INCLK_SPDIF_TX = 0x0c, + INCLK_ASRCK1_CLK = 0x0f, +/* imx8 */ + INCLK_AUD_PLL_DIV_CLK0 = 0x10, + INCLK_AUD_PLL_DIV_CLK1 = 0x11, + INCLK_AUD_CLK0 = 0x12, + INCLK_AUD_CLK1 = 0x13, + INCLK_ESAI0_RX_CLK = 0x14, + INCLK_ESAI0_TX_CLK = 0x15, + INCLK_SPDIF0_RX = 0x16, + INCLK_SPDIF1_RX = 0x17, + INCLK_SAI0_RX_BCLK = 0x18, + INCLK_SAI0_TX_BCLK = 0x19, + INCLK_SAI1_RX_BCLK = 0x1a, + INCLK_SAI1_TX_BCLK = 0x1b, + INCLK_SAI2_RX_BCLK = 0x1c, + INCLK_SAI3_RX_BCLK = 0x1d, + INCLK_ASRC0_MUX_CLK = 0x1e, + + INCLK_ESAI1_RX_CLK = 0x20, + INCLK_ESAI1_TX_CLK = 0x21, + INCLK_SAI6_TX_BCLK = 0x22, + INCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, + INCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, +}; + +enum asrc_outclk { + OUTCLK_NONE = 0x03, + OUTCLK_ESAI_TX = 0x00, + OUTCLK_SSI1_TX = 0x01, + OUTCLK_SSI2_TX = 0x02, + OUTCLK_SSI3_TX = 0x07, + OUTCLK_SPDIF_TX = 0x04, + OUTCLK_MLB_CLK = 0x05, + OUTCLK_PAD = 0x06, + OUTCLK_ESAI_RX = 0x08, + OUTCLK_SSI1_RX = 0x09, + OUTCLK_SSI2_RX = 0x0a, + OUTCLK_SSI3_RX = 0x0b, + OUTCLK_SPDIF_RX = 0x0c, + OUTCLK_ASRCK1_CLK = 0x0f, + +/* imx8 */ + OUTCLK_AUD_PLL_DIV_CLK0 = 0x10, + OUTCLK_AUD_PLL_DIV_CLK1 = 0x11, + OUTCLK_AUD_CLK0 = 0x12, + OUTCLK_AUD_CLK1 = 0x13, + OUTCLK_ESAI0_RX_CLK = 0x14, + OUTCLK_ESAI0_TX_CLK = 0x15, + OUTCLK_SPDIF0_RX = 0x16, + OUTCLK_SPDIF1_RX = 0x17, + OUTCLK_SAI0_RX_BCLK = 0x18, + OUTCLK_SAI0_TX_BCLK = 0x19, + OUTCLK_SAI1_RX_BCLK = 0x1a, + OUTCLK_SAI1_TX_BCLK = 0x1b, + OUTCLK_SAI2_RX_BCLK = 0x1c, + OUTCLK_SAI3_RX_BCLK = 0x1d, + OUTCLK_ASRCO_MUX_CLK = 0x1e, + + OUTCLK_ESAI1_RX_CLK = 0x20, + OUTCLK_ESAI1_TX_CLK = 0x21, + OUTCLK_SAI6_TX_BCLK = 0x22, + OUTCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, + OUTCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, +}; + +struct asrc_config { + enum asrc_pair_index pair; + unsigned int channel_num; + unsigned int dma_buffer_size; + unsigned int input_sample_rate; + unsigned int output_sample_rate; + snd_pcm_format_t input_format; + snd_pcm_format_t output_format; + enum asrc_inclk inclk; + enum asrc_outclk outclk; +}; + +struct asrc_req { + unsigned int chn_num; + enum asrc_pair_index index; + uint64_t supported_in_format; + uint64_t supported_out_format; +}; + +struct asrc_querybuf { + unsigned int buffer_index; + unsigned int input_length; + unsigned int output_length; + unsigned long input_offset; + unsigned long output_offset; +}; + +struct asrc_convert_buffer { + void *input_buffer_vaddr; + void *output_buffer_vaddr; + unsigned int input_buffer_length; + unsigned int output_buffer_length; +}; + +struct asrc_status_flags { + enum asrc_pair_index index; + unsigned int overload_error; +}; + +enum asrc_error_status { + ASRC_TASK_Q_OVERLOAD = 0x01, + ASRC_OUTPUT_TASK_OVERLOAD = 0x02, + ASRC_INPUT_TASK_OVERLOAD = 0x04, + ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08, + ASRC_INPUT_BUFFER_UNDERRUN = 0x10, +}; +#endif/* __MXC_ASRC_UAPI_H__ */ diff --git a/include/uapi/linux/mxc_dcic.h b/include/uapi/linux/mxc_dcic.h new file mode 100644 index 000000000000..83e3e2c68c02 --- /dev/null +++ b/include/uapi/linux/mxc_dcic.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file uapi/linux/mxc_dcic.h + * + * @brief MXC DCIC private header file + * + * @ingroup MXC DCIC + */ +#ifndef __ASM_ARCH_MXC_DCIC_H__ +#define __ASM_ARCH_MXC_DCIC_H__ + +#define DCIC_IOC_ALLOC_ROI_NUM _IO('D', 10) +#define DCIC_IOC_FREE_ROI_NUM _IO('D', 11) +#define DCIC_IOC_CONFIG_DCIC _IO('D', 12) +#define DCIC_IOC_CONFIG_ROI _IO('D', 13) +#define DCIC_IOC_GET_RESULT _IO('D', 14) + +struct roi_params { + unsigned int roi_n; + unsigned int ref_sig; + unsigned int start_y; + unsigned int start_x; + unsigned int end_y; + unsigned int end_x; + char freeze; +}; + +#endif diff --git a/include/uapi/linux/mxc_dsp.h b/include/uapi/linux/mxc_dsp.h new file mode 100644 index 000000000000..040681cc39c8 --- /dev/null +++ b/include/uapi/linux/mxc_dsp.h @@ -0,0 +1,152 @@ +/* + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MXC_DSP_UAPI_H__ +#define __MXC_DSP_UAPI_H__ + +#define DSP_IOC_MAGIC 'H' +#define DSP_CLIENT_REGISTER _IOW(DSP_IOC_MAGIC, 0, unsigned int) +#define DSP_CLIENT_UNREGISTER _IOW(DSP_IOC_MAGIC, 1, unsigned int) +#define DSP_IPC_MSG_SEND _IOW(DSP_IOC_MAGIC, 2, unsigned int) +#define DSP_IPC_MSG_RECV _IOW(DSP_IOC_MAGIC, 3, unsigned int) +#define DSP_GET_SHMEM_INFO _IOW(DSP_IOC_MAGIC, 4, unsigned int) +#define DSP_LOAD_LIB _IOW(DSP_IOC_MAGIC, 5, unsigned int) +#define DSP_UNLOAD_LIB _IOW(DSP_IOC_MAGIC, 6, unsigned int) + + +#define CODEC_MP3_DEC 1 +#define CODEC_AAC_DEC 2 +#define CODEC_DAB_DEC 3 +#define CODEC_MP2_DEC 4 +#define CODEC_BSAC_DEC 5 +#define CODEC_DRM_DEC 6 +#define CODEC_SBC_DEC 7 +#define CODEC_SBC_ENC 8 +#define CODEC_DEMO_DEC 9 + +#define RENDER_ESAI 0x10 +#define RENDER_SAI 0x11 + +enum DSP_ERROR_TYPE { + XA_SUCCESS = 0, + + XA_ERROR_STREAM, + XA_PARA_ERROR, + XA_INSUFFICIENT_MEM, + XA_ERR_UNKNOWN, + XA_PROFILE_NOT_SUPPORT, + XA_INIT_ERR, + XA_NO_OUTPUT, + + XA_NOT_ENOUGH_DATA = 0x100, + XA_CAPIBILITY_CHANGE = 0x200, + XA_END_OF_STREAM = 0x300, /* no output */ +}; + +/* Parameter type to Set /Get */ +enum DSP_ParaType { +/* Set parmameters */ +/* common */ + XA_SAMPLERATE = 0, + XA_CHANNEL, + XA_FRAMED, /* one whole frame input */ + XA_DEPTH, + XA_CODEC_DATA, + XA_BITRATE, + XA_DOWNMIX_STEREO, + XA_STREAM_TYPE, + XA_CHAN_MAP_TABLE, + //UNIA_CHANNEL_MASK, + XA_TO_STEREO, + +/* dedicate for mp3 dec */ + XA_MP3_DEC_CRC_CHECK = 0x120, + XA_MP3_DEC_MCH_ENABLE, + XA_MP3_DEC_NONSTD_STRM_SUPPORT, + +/* dedicate for bsac dec */ + XA_BSAC_DEC_DECODELAYERS = 0x130, + +/* dedicate for aacplus dec */ + XA_AACPLUS_DEC_BDOWNSAMPLE = 0x140, + XA_AACPLUS_DEC_BBITSTREAMDOWNMIX, + XA_AACPLUS_DEC_CHANROUTING, + +/* dedicate for dabplus dec */ + XA_DABPLUS_DEC_BDOWNSAMPLE = 0x150, + XA_DABPLUS_DEC_BBITSTREAMDOWNMIX, + XA_DABPLUS_DEC_CHANROUTING, + +/* dedicate for sbc enc */ + XA_SBC_ENC_SUBBANDS = 0x160, + XA_SBC_ENC_BLOCKS, + XA_SBC_ENC_SNR, + XA_SBC_ENC_BITPOOL, + XA_SBC_ENC_CHMODE, + +/* Get parmameters */ + XA_CODEC_DESCRIPTION = 0x200, + XA_OUTPUT_PCM_FORMAT, + XA_CONSUMED_LENGTH, + XA_OUTBUF_ALLOC_SIZE, + XA_CONSUMED_CYCLES, + +}; + +#define XA_STREAM_DABPLUS_BASE 0x30 +enum DSP_StreamType { + /* AAC/AACPLUS file format */ + XA_STREAM_UNKNOWN = 0, + XA_STREAM_ADTS, + XA_STREAM_ADIF, + XA_STREAM_RAW, + + XA_STREAM_LATM, + XA_STREAM_LATM_OUTOFBAND_CONFIG, + XA_STREAM_LOAS, + + /* DABPLUS file format */ + XA_STREAM_DABPLUS_RAW_SIDEINFO = XA_STREAM_DABPLUS_BASE, + XA_STREAM_DABPLUS, + + /* BSAC file raw format */ + XA_STREAM_BSAC_RAW, + +}; + +/* sbc_enc-specific channel modes */ +enum DSP_SbcEncChmode { + XA_CHMODE_MONO = 0, + XA_CHMODE_DUAL = 1, + XA_CHMODE_STEREO = 2, + XA_CHMODE_JOINT = 3, +}; + +struct shmem_info { + unsigned int phys_addr; + unsigned int size; +}; + +#endif/* __MXC_DSP_UAPI_H__ */ diff --git a/include/uapi/linux/mxc_mlb.h b/include/uapi/linux/mxc_mlb.h new file mode 100644 index 000000000000..20ba5240ea51 --- /dev/null +++ b/include/uapi/linux/mxc_mlb.h @@ -0,0 +1,55 @@ +/* + * mxc_mlb.h + * + * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_MLB_UAPI_H +#define _MXC_MLB_UAPI_H + +/* define IOCTL command */ +#define MLB_DBG_RUNTIME _IO('S', 0x09) +#define MLB_SET_FPS _IOW('S', 0x10, unsigned int) +#define MLB_GET_VER _IOR('S', 0x11, unsigned long) +#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char) + +/*! + * set channel address for each logical channel + * the MSB 16bits is for tx channel, the left LSB is for rx channel + */ +#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int) +#define MLB_CHAN_STARTUP _IO('S', 0x14) +#define MLB_CHAN_SHUTDOWN _IO('S', 0x15) +#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long) + +#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17) +#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18) +#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int) +#define MLB_IRQ_ENABLE _IO('S', 0x20) +#define MLB_IRQ_DISABLE _IO('S', 0x21) + +/*! + * MLB event define + */ +enum { + MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0, + MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1, + MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8, + MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9, + MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16, + MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17, + MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24, + MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25, +}; + + +#endif /* _MXC_MLB_H */ diff --git a/include/uapi/linux/mxc_sim_interface.h b/include/uapi/linux/mxc_sim_interface.h new file mode 100644 index 000000000000..9ac3c029ab40 --- /dev/null +++ b/include/uapi/linux/mxc_sim_interface.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef UAPI_MXC_SIM_INTERFACE_H +#define UAPI_MXC_SIM_INTERFACE_H + +#define SIM_ATR_LENGTH_MAX 32 + +/* Raw ATR SIM_IOCTL_GET_ATR */ +typedef struct { + unsigned int size;/* length of ATR received */ + unsigned char *atr_buffer;/* raw ATR string received */ + int errval;/* The error vale reported to user space after completing ATR*/ +} sim_atr_t; + +/* ISO7816-3 protocols */ +#define SIM_PROTOCOL_T0 1 +#define SIM_PROTOCOL_T1 2 + +/* Transfer types for SIM_IOCTL_XFER */ +#define SIM_XFER_TYPE_TPDU 1 +#define SIM_XFER_TYPE_PTS 2 + +typedef struct { + unsigned int wwt; + unsigned int cwt; + unsigned int bwt; + unsigned int bgt; + unsigned int cgt; +} sim_timing_t; + +/* Transfer data for SIM_IOCTL_XFER */ +typedef struct { + unsigned char *xmt_buffer; /* transmit buffer pointer */ + int xmt_length;/* transmit buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after completing transmitting*/ +} sim_xmt_t; + +typedef struct { + unsigned char *rcv_buffer; /* receive buffer pointer */ + int rcv_length; /* receive buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after receiving*/ +} sim_rcv_t; + +typedef struct { + unsigned char di; + unsigned char fi; +} sim_baud_t; + +/* Interface power states */ +#define SIM_POWER_OFF (0) +#define SIM_POWER_ON (1) + +/* Return values for SIM_IOCTL_GET_PRESENSE */ +#define SIM_PRESENT_REMOVED (0) +#define SIM_PRESENT_DETECTED (1) +#define SIM_PRESENT_OPERATIONAL (2) + +/* The error value */ +#define SIM_OK (0) +#define SIM_ERROR_CWT (1 << 0) +#define SIM_ERROR_BWT (1 << 1) +#define SIM_ERROR_PARITY (1 << 2) +#define SIM_ERROR_INVALID_TS (1 << 3) +#define SIM_ERROR_FRAME (1 << 4) +#define SIM_ERROR_ATR_TIMEROUT (1 << 5) +#define SIM_ERROR_NACK_THRESHOLD (1 << 6) +#define SIM_ERROR_BGT (1 << 7) +#define SIM_ERROR_ATR_DELAY (1 << 8) + +/* Return values for SIM_IOCTL_GET_ERROR */ +#define SIM_E_ACCESS (1) +#define SIM_E_TPDUSHORT (2) +#define SIM_E_PTSEMPTY (3) +#define SIM_E_INVALIDXFERTYPE (4) +#define SIM_E_INVALIDXMTLENGTH (5) +#define SIM_E_INVALIDRCVLENGTH (6) +#define SIM_E_NACK (7) +#define SIM_E_TIMEOUT (8) +#define SIM_E_NOCARD (9) +#define SIM_E_PARAM_FI_INVALID (10) +#define SIM_E_PARAM_DI_INVALID (11) +#define SIM_E_PARAM_FBYD_WITHFRACTION (12) +#define SIM_E_PARAM_FBYD_NOTDIVBY8OR12 (13) +#define SIM_E_PARAM_DIVISOR_RANGE (14) +#define SIM_E_MALLOC (15) +#define SIM_E_IRQ (16) +#define SIM_E_POWERED_ON (17) +#define SIM_E_POWERED_OFF (18) + +/* ioctl encodings */ +#define SIM_IOCTL_BASE (0xc0) +#define SIM_IOCTL_GET_PRESENSE _IOR(SIM_IOCTL_BASE, 1, int) +#define SIM_IOCTL_GET_ATR _IOR(SIM_IOCTL_BASE, 2, sim_atr_t) +#define SIM_IOCTL_XMT _IOR(SIM_IOCTL_BASE, 3, sim_xmt_t) +#define SIM_IOCTL_RCV _IOR(SIM_IOCTL_BASE, 4, sim_rcv_t) +#define SIM_IOCTL_ACTIVATE _IO(SIM_IOCTL_BASE, 5) +#define SIM_IOCTL_DEACTIVATE _IO(SIM_IOCTL_BASE, 6) +#define SIM_IOCTL_WARM_RESET _IO(SIM_IOCTL_BASE, 7) +#define SIM_IOCTL_COLD_RESET _IO(SIM_IOCTL_BASE, 8) +#define SIM_IOCTL_CARD_LOCK _IO(SIM_IOCTL_BASE, 9) +#define SIM_IOCTL_CARD_EJECT _IO(SIM_IOCTL_BASE, 10) +#define SIM_IOCTL_SET_PROTOCOL _IOR(SIM_IOCTL_BASE, 11, unsigned int) +#define SIM_IOCTL_SET_TIMING _IOR(SIM_IOCTL_BASE, 12, sim_timing_t) +#define SIM_IOCTL_SET_BAUD _IOR(SIM_IOCTL_BASE, 13, sim_baud_t) +#define SIM_IOCTL_WAIT _IOR(SIM_IOCTL_BASE, 14, unsigned int) + +#endif diff --git a/include/uapi/linux/mxc_v4l2.h b/include/uapi/linux/mxc_v4l2.h new file mode 100644 index 000000000000..f261b925a7ed --- /dev/null +++ b/include/uapi/linux/mxc_v4l2.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file uapi/linux/mxc_v4l2.h + * + * @brief MXC V4L2 private header file + * + * @ingroup MXC V4L2 + */ + +#ifndef __ASM_ARCH_MXC_V4L2_H__ +#define __ASM_ARCH_MXC_V4L2_H__ + +/* + * For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID. + * And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3. + */ +#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0) +#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_MXC_SWITCH_CAM (V4L2_CID_PRIVATE_BASE + 6) + +#define V4L2_MXC_ROTATE_NONE 0 +#define V4L2_MXC_ROTATE_VERT_FLIP 1 +#define V4L2_MXC_ROTATE_HORIZ_FLIP 2 +#define V4L2_MXC_ROTATE_180 3 +#define V4L2_MXC_ROTATE_90_RIGHT 4 +#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5 +#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6 +#define V4L2_MXC_ROTATE_90_LEFT 7 + +struct v4l2_mxc_offset { + uint32_t u_offset; + uint32_t v_offset; +}; + +struct v4l2_mxc_dest_crop { + __u32 type; /* enum v4l2_buf_type */ + struct v4l2_mxc_offset offset; +}; + +/* + * Private IOCTLs + * + * VIDIOC_S_INOUT_CROP: Set input stream crop size + * VIDIOC_G_INOUT_CROP: Get input stream crop size + */ +#define VIDIOC_S_INPUT_CROP \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct v4l2_crop) +#define VIDIOC_G_INPUT_CROP \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct v4l2_crop) +#define VIDIOC_S_DEST_CROP \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct v4l2_mxc_dest_crop) +#endif diff --git a/include/uapi/linux/mxcfb.h b/include/uapi/linux/mxcfb.h new file mode 100644 index 000000000000..3a984090769a --- /dev/null +++ b/include/uapi/linux/mxcfb.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * @file uapi/linux/mxcfb.h + * + * @brief Global header file for the MXC frame buffer + * + * @ingroup Framebuffer + */ +#ifndef __ASM_ARCH_MXCFB_H__ +#define __ASM_ARCH_MXCFB_H__ + +#include <linux/fb.h> + +#define FB_SYNC_OE_LOW_ACT 0x80000000 +#define FB_SYNC_CLK_LAT_FALL 0x40000000 +#define FB_SYNC_DATA_INVERT 0x20000000 +#define FB_SYNC_CLK_IDLE_EN 0x10000000 +#define FB_SYNC_SHARP_MODE 0x08000000 +#define FB_SYNC_SWAP_RGB 0x04000000 +#define FB_ACCEL_TRIPLE_FLAG 0x00000000 +#define FB_ACCEL_DOUBLE_FLAG 0x00000001 + +struct mxcfb_gbl_alpha { + int enable; + int alpha; +}; + +struct mxcfb_loc_alpha { + int enable; + int alpha_in_pixel; + unsigned long alpha_phy_addr0; + unsigned long alpha_phy_addr1; +}; + +struct mxcfb_color_key { + int enable; + __u32 color_key; +}; + +struct mxcfb_pos { + __u16 x; + __u16 y; +}; + +struct mxcfb_gamma { + int enable; + int constk[16]; + int slopek[16]; +}; + +struct mxcfb_gpu_split_fmt { + struct fb_var_screeninfo var; + unsigned long offset; +}; + +struct mxcfb_rect { + __u32 top; + __u32 left; + __u32 width; + __u32 height; +}; + +#define GRAYSCALE_8BIT 0x1 +#define GRAYSCALE_8BIT_INVERTED 0x2 +#define GRAYSCALE_4BIT 0x3 +#define GRAYSCALE_4BIT_INVERTED 0x4 + +#define AUTO_UPDATE_MODE_REGION_MODE 0 +#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1 + +#define UPDATE_SCHEME_SNAPSHOT 0 +#define UPDATE_SCHEME_QUEUE 1 +#define UPDATE_SCHEME_QUEUE_AND_MERGE 2 + +#define UPDATE_MODE_PARTIAL 0x0 +#define UPDATE_MODE_FULL 0x1 + +#define WAVEFORM_MODE_GLR16 4 +#define WAVEFORM_MODE_GLD16 5 +#define WAVEFORM_MODE_AUTO 257 + +#define TEMP_USE_AMBIENT 0x1000 + +#define EPDC_FLAG_ENABLE_INVERSION 0x01 +#define EPDC_FLAG_FORCE_MONOCHROME 0x02 +#define EPDC_FLAG_USE_CMAP 0x04 +#define EPDC_FLAG_USE_ALT_BUFFER 0x100 +#define EPDC_FLAG_TEST_COLLISION 0x200 +#define EPDC_FLAG_GROUP_UPDATE 0x400 +#define EPDC_FLAG_USE_DITHERING_Y1 0x2000 +#define EPDC_FLAG_USE_DITHERING_Y4 0x4000 +#define EPDC_FLAG_USE_REGAL 0x8000 + +enum mxcfb_dithering_mode { + EPDC_FLAG_USE_DITHERING_PASSTHROUGH = 0x0, + EPDC_FLAG_USE_DITHERING_FLOYD_STEINBERG, + EPDC_FLAG_USE_DITHERING_ATKINSON, + EPDC_FLAG_USE_DITHERING_ORDERED, + EPDC_FLAG_USE_DITHERING_QUANT_ONLY, + EPDC_FLAG_USE_DITHERING_MAX, +}; + +#define FB_POWERDOWN_DISABLE -1 + +struct mxcfb_alt_buffer_data { + __u32 phys_addr; + __u32 width; /* width of entire buffer */ + __u32 height; /* height of entire buffer */ + struct mxcfb_rect alt_update_region; /* region within buffer to update */ +}; + +struct mxcfb_update_data { + struct mxcfb_rect update_region; + __u32 waveform_mode; + __u32 update_mode; + __u32 update_marker; + int temp; + unsigned int flags; + int dither_mode; + int quant_bit; + struct mxcfb_alt_buffer_data alt_buffer_data; +}; + +struct mxcfb_update_marker_data { + __u32 update_marker; + __u32 collision_test; +}; + +/* + * Structure used to define waveform modes for driver + * Needed for driver to perform auto-waveform selection + */ +struct mxcfb_waveform_modes { + int mode_init; + int mode_du; + int mode_gc4; + int mode_gc8; + int mode_gc16; + int mode_gc32; +}; + +/* + * Structure used to define a 5*3 matrix of parameters for + * setting IPU DP CSC module related to this framebuffer. + */ +struct mxcfb_csc_matrix { + int param[5][3]; +}; + +#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t) +#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha) +#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key) +#define MXCFB_SET_OVERLAY_POS _IOWR('F', 0x24, struct mxcfb_pos) +#define MXCFB_GET_FB_IPU_CHAN _IOR('F', 0x25, u_int32_t) +#define MXCFB_SET_LOC_ALPHA _IOWR('F', 0x26, struct mxcfb_loc_alpha) +#define MXCFB_SET_LOC_ALP_BUF _IOW('F', 0x27, unsigned long) +#define MXCFB_SET_GAMMA _IOW('F', 0x28, struct mxcfb_gamma) +#define MXCFB_GET_FB_IPU_DI _IOR('F', 0x29, u_int32_t) +#define MXCFB_GET_DIFMT _IOR('F', 0x2A, u_int32_t) +#define MXCFB_GET_FB_BLANK _IOR('F', 0x2B, u_int32_t) +#define MXCFB_SET_DIFMT _IOW('F', 0x2C, u_int32_t) +#define MXCFB_CSC_UPDATE _IOW('F', 0x2D, struct mxcfb_csc_matrix) +#define MXCFB_SET_GPU_SPLIT_FMT _IOW('F', 0x2F, struct mxcfb_gpu_split_fmt) +#define MXCFB_SET_PREFETCH _IOW('F', 0x30, int) +#define MXCFB_GET_PREFETCH _IOR('F', 0x31, int) + +/* IOCTLs for E-ink panel updates */ +#define MXCFB_SET_WAVEFORM_MODES _IOW('F', 0x2B, struct mxcfb_waveform_modes) +#define MXCFB_SET_TEMPERATURE _IOW('F', 0x2C, int32_t) +#define MXCFB_SET_AUTO_UPDATE_MODE _IOW('F', 0x2D, __u32) +#define MXCFB_SEND_UPDATE _IOW('F', 0x2E, struct mxcfb_update_data) +#define MXCFB_WAIT_FOR_UPDATE_COMPLETE _IOWR('F', 0x2F, struct mxcfb_update_marker_data) +#define MXCFB_SET_PWRDOWN_DELAY _IOW('F', 0x30, int32_t) +#define MXCFB_GET_PWRDOWN_DELAY _IOR('F', 0x31, int32_t) +#define MXCFB_SET_UPDATE_SCHEME _IOW('F', 0x32, __u32) +#define MXCFB_GET_WORK_BUFFER _IOWR('F', 0x34, unsigned long) +#define MXCFB_DISABLE_EPDC_ACCESS _IO('F', 0x35) +#define MXCFB_ENABLE_EPDC_ACCESS _IO('F', 0x36) +#endif diff --git a/include/uapi/linux/pxp_device.h b/include/uapi/linux/pxp_device.h new file mode 100644 index 000000000000..fce89ce066bb --- /dev/null +++ b/include/uapi/linux/pxp_device.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _UAPI_PXP_DEVICE +#define _UAPI_PXP_DEVICE + +#include <linux/pxp_dma.h> + +struct pxp_chan_handle { + unsigned int handle; + int hist_status; +}; + +struct pxp_mem_desc { + unsigned int handle; + unsigned int size; + dma_addr_t phys_addr; + unsigned int virt_uaddr; /* virtual user space address */ + unsigned int mtype; +}; + +struct pxp_mem_flush { + unsigned int handle; + unsigned int type; +}; + +#define PXP_IOC_MAGIC 'P' + +#define PXP_IOC_GET_CHAN _IOR(PXP_IOC_MAGIC, 0, struct pxp_mem_desc) +#define PXP_IOC_PUT_CHAN _IOW(PXP_IOC_MAGIC, 1, struct pxp_mem_desc) +#define PXP_IOC_CONFIG_CHAN _IOW(PXP_IOC_MAGIC, 2, struct pxp_mem_desc) +#define PXP_IOC_START_CHAN _IOW(PXP_IOC_MAGIC, 3, struct pxp_mem_desc) +#define PXP_IOC_GET_PHYMEM _IOWR(PXP_IOC_MAGIC, 4, struct pxp_mem_desc) +#define PXP_IOC_PUT_PHYMEM _IOW(PXP_IOC_MAGIC, 5, struct pxp_mem_desc) +#define PXP_IOC_WAIT4CMPLT _IOWR(PXP_IOC_MAGIC, 6, struct pxp_mem_desc) +#define PXP_IOC_FLUSH_PHYMEM _IOR(PXP_IOC_MAGIC, 7, struct pxp_mem_flush) + +/* Memory types supported*/ +#define MEMORY_TYPE_UNCACHED 0x0 +#define MEMORY_TYPE_WC 0x1 +#define MEMORY_TYPE_CACHED 0x2 + +/* Cache flush operations */ +#define CACHE_CLEAN 0x1 +#define CACHE_INVALIDATE 0x2 +#define CACHE_FLUSH 0x4 + +#endif diff --git a/include/uapi/linux/pxp_dma.h b/include/uapi/linux/pxp_dma.h new file mode 100644 index 000000000000..76983abb4344 --- /dev/null +++ b/include/uapi/linux/pxp_dma.h @@ -0,0 +1,346 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _UAPI_PXP_DMA +#define _UAPI_PXP_DMA + +#include <linux/posix_types.h> +#include <linux/types.h> + +#ifndef __KERNEL__ +typedef unsigned long dma_addr_t; +typedef unsigned char bool; +#endif + +/* PXP Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/*! + * @name PXP Pixel Formats + * + * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are + * the same used by V4L2 API. + */ + +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define PXP_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define PXP_PIX_FMT_RGB444 fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */ +#define PXP_PIX_FMT_ARGB444 fourcc('A', 'R', '1', '2') /* 16 aaaarrrr ggggbbbb */ +#define PXP_PIX_FMT_RGBA444 fourcc('R', 'A', '1', '2') /* 16 rrrrgggg bbbbaaaa */ +#define PXP_PIX_FMT_XRGB444 fourcc('X', 'R', '1', '2') /* 16 xxxxrrrr ggggbbbb */ +#define PXP_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define PXP_PIX_FMT_ARGB555 fourcc('A', 'R', '1', '5') /*!< 16 ARGB-1-5-5-5 */ +#define PXP_PIX_FMT_RGBA555 fourcc('R', 'A', '1', '5') /*!< 16 RGBA-5-5-5-1 */ +#define PXP_PIX_FMT_XRGB555 fourcc('X', 'R', '1', '5') /*!< 16 XRGB-1-5-5-5 */ +#define PXP_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 16 RGB-5-6-5 */ +#define PXP_PIX_FMT_BGR565 fourcc('B', 'G', 'R', 'P') /*!< 16 BGR-5-6-5 */ +#define PXP_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define PXP_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define PXP_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define PXP_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define PXP_PIX_FMT_XBGR32 fourcc('X', 'B', 'G', 'R') /*!< 32 XBGR-8-8-8-8 */ +#define PXP_PIX_FMT_BGRX32 fourcc('B', 'G', 'R', 'X') /*!< 32 BGRX-8-8-8-8 */ +#define PXP_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGRA-8-8-8-8 */ +#define PXP_PIX_FMT_XRGB32 fourcc('X', 'R', 'G', 'B') /*!< 32 XRGB-8-8-8-8 */ +#define PXP_PIX_FMT_RGBX32 fourcc('R', 'G', 'B', 'X') /*!< 32 RGBX-8-8-8-8 */ +#define PXP_PIX_FMT_ARGB32 fourcc('A', 'R', 'G', 'B') /*!< 32 ARGB-8-8-8-8 */ +#define PXP_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGBA-8-8-8-8 */ +#define PXP_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +#define PXP_PIX_FMT_RGB32 PXP_PIX_FMT_XRGB32 +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define PXP_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define PXP_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define PXP_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 YVU 4:2:2 */ +#define PXP_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVU 4:2:2 */ +#define PXP_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define PXP_PIX_FMT_VUY444 fourcc('V', 'U', 'Y', 'A') /*!< 32 VUYA 8:8:8 */ +#define PXP_PIX_FMT_YUV444 fourcc('A', 'Y', 'U', 'V') /*!< 32 AYUV 8:8:8 */ +#define PXP_PIX_FMT_YVU444 fourcc('A', 'Y', 'V', 'U') /*!< 32 AYUV 8:8:8 */ +/* two planes -- one Y, one Cb + Cr interleaved */ +#define PXP_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define PXP_PIX_FMT_NV21 fourcc('N', 'V', '2', '1') /* 12 Y/CbCr 4:2:0 */ +#define PXP_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 12 Y/CbCr 4:2:2 */ +#define PXP_PIX_FMT_NV61 fourcc('N', 'V', '6', '1') /* 12 Y/CbCr 4:2:2 */ +/*! @} */ +/*! @name YUV Planar Formats */ +/*! @{ */ +#define PXP_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */ +#define PXP_PIX_FMT_GY04 fourcc('G', 'Y', '0', '4') /*!< 4 Greyscale */ +#define PXP_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */ +#define PXP_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */ +#define PXP_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */ +#define PXP_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */ +#define PXP_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */ +#define PXP_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */ +#define PXP_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */ +/*! @} */ + +#define PXP_LUT_NONE 0x0 +#define PXP_LUT_INVERT 0x1 +#define PXP_LUT_BLACK_WHITE 0x2 +#define PXP_LUT_USE_CMAP 0x4 + +/* dithering modes enum */ +#define PXP_DITHER_PASS_THROUGH 0 +#define PXP_DITHER_FLOYD 1 +#define PXP_DITHER_ATKINSON 2 +#define PXP_DITHER_ORDERED 3 +#define PXP_DITHER_QUANT_ONLY 4 + +#define NR_PXP_VIRT_CHANNEL 16 + +#define PXP_IOC_MAGIC 'P' + +#define PXP_IOC_GET_CHAN _IOR(PXP_IOC_MAGIC, 0, struct pxp_mem_desc) +#define PXP_IOC_PUT_CHAN _IOW(PXP_IOC_MAGIC, 1, struct pxp_mem_desc) +#define PXP_IOC_CONFIG_CHAN _IOW(PXP_IOC_MAGIC, 2, struct pxp_mem_desc) +#define PXP_IOC_START_CHAN _IOW(PXP_IOC_MAGIC, 3, struct pxp_mem_desc) +#define PXP_IOC_GET_PHYMEM _IOWR(PXP_IOC_MAGIC, 4, struct pxp_mem_desc) +#define PXP_IOC_PUT_PHYMEM _IOW(PXP_IOC_MAGIC, 5, struct pxp_mem_desc) +#define PXP_IOC_WAIT4CMPLT _IOWR(PXP_IOC_MAGIC, 6, struct pxp_mem_desc) + +#define PXP_IOC_FILL_DATA _IOWR(PXP_IOC_MAGIC, 7, struct pxp_mem_desc) + +#define ALPHA_MODE_ROP 0x1 +#define ALPHA_MODE_LEGACY 0x2 +#define ALPHA_MODE_PORTER_DUFF 0x3 + +#define PXP_DEVICE_LEGACY + +/* Order significant! */ +enum pxp_channel_status { + PXP_CHANNEL_FREE, + PXP_CHANNEL_INITIALIZED, + PXP_CHANNEL_READY, +}; + +enum pxp_working_mode { + PXP_MODE_LEGACY = 0x1, + PXP_MODE_STANDARD = 0x2, + PXP_MODE_ADVANCED = 0x4, +}; + +enum pxp_buffer_flag { + PXP_BUF_FLAG_WFE_A_FETCH0 = 0x0001, + PXP_BUF_FLAG_WFE_A_FETCH1 = 0x0002, + PXP_BUF_FLAG_WFE_A_STORE0 = 0x0004, + PXP_BUF_FLAG_WFE_A_STORE1 = 0x0008, + PXP_BUF_FLAG_WFE_B_FETCH0 = 0x0010, + PXP_BUF_FLAG_WFE_B_FETCH1 = 0x0020, + PXP_BUF_FLAG_WFE_B_STORE0 = 0x0040, + PXP_BUF_FLAG_WFE_B_STORE1 = 0x0080, + PXP_BUF_FLAG_DITHER_FETCH0 = 0x0100, + PXP_BUF_FLAG_DITHER_FETCH1 = 0x0200, + PXP_BUF_FLAG_DITHER_STORE0 = 0x0400, + PXP_BUF_FLAG_DITHER_STORE1 = 0x0800, +}; + +enum pxp_engine_ctrl { + PXP_ENABLE_ROTATE0 = 0x001, + PXP_ENABLE_ROTATE1 = 0x002, + PXP_ENABLE_LUT = 0x004, + PXP_ENABLE_CSC2 = 0x008, + PXP_ENABLE_ALPHA_B = 0x010, + PXP_ENABLE_INPUT_FETCH_SOTRE = 0x020, + PXP_ENABLE_WFE_B = 0x040, + PXP_ENABLE_WFE_A = 0x080, + PXP_ENABLE_DITHER = 0x100, + PXP_ENABLE_PS_AS_OUT = 0x200, + PXP_ENABLE_COLLISION_DETECT = 0x400, + PXP_ENABLE_HANDSHAKE = 0x1000, + PXP_ENABLE_DITHER_BYPASS = 0x2000, +}; + +enum pxp_op_type { + PXP_OP_2D = 0x001, + PXP_OP_DITHER = 0x002, + PXP_OP_WFE_A = 0x004, + PXP_OP_WFE_B = 0x008, +}; + +struct rect { + int top; /* Upper left coordinate of rectangle */ + int left; + int width; + int height; +}; + +#define ALPHA_MODE_STRAIGHT 0x0 +#define ALPHA_MODE_INVERSED 0x1 + +#define GLOBAL_ALPHA_MODE_ON 0x0 +#define GLOBAL_ALPHA_MODE_OFF 0x1 +#define GLOBAL_ALPHA_MODE_SCALE 0x2 + +#define FACTOR_MODE_ONE 0x0 +#define FACTOR_MODE_ZERO 0x1 +#define FACTOR_MODE_STRAIGHT 0x2 +#define FACTOR_MODE_INVERSED 0x3 + +#define COLOR_MODE_STRAIGHT 0x0 +#define COLOR_MODE_MULTIPLY 0x1 + +struct pxp_alpha { + unsigned int alpha_mode; + unsigned int global_alpha_mode; + unsigned int global_alpha_value; + unsigned int factor_mode; + unsigned int color_mode; +}; + +struct pxp_layer_param { + unsigned short left; + unsigned short top; + unsigned short width; + unsigned short height; + unsigned short stride; /* aka pitch */ + unsigned int pixel_fmt; + + unsigned int flag; + /* layers combining parameters + * (these are ignored for S0 and output + * layers, and only apply for OL layer) + */ + bool combine_enable; + unsigned int color_key_enable; + unsigned int color_key; + bool global_alpha_enable; + /* global alpha is either override or multiply */ + bool global_override; + unsigned char global_alpha; + bool alpha_invert; + bool local_alpha_enable; + int comp_mask; + + struct pxp_alpha alpha; + struct rect crop; + + dma_addr_t paddr; +}; + +struct pxp_collision_info { + unsigned int pixel_cnt; + unsigned int rect_min_x; + unsigned int rect_min_y; + unsigned int rect_max_x; + unsigned int rect_max_y; + unsigned int victim_luts[2]; +}; + +struct pxp_proc_data { + /* S0 Transformation Info */ + int scaling; + int hflip; + int vflip; + int rotate; + int rot_pos; + int yuv; + unsigned int alpha_mode; + + /* Source rectangle (srect) defines the sub-rectangle + * within S0 to undergo processing. + */ + struct rect srect; + /* Dest rect (drect) defines how to position the processed + * source rectangle (after resizing) within the output frame, + * whose dimensions are defined in pxp->pxp_conf_state.out_param + */ + struct rect drect; + + /* Current S0 configuration */ + unsigned int bgcolor; + unsigned char fill_en; + + /* Output overlay support */ + int overlay_state; + + /* LUT transformation on Y data */ + int lut_transform; + unsigned char *lut_map; /* 256 entries */ + bool lut_map_updated; /* Map recently changed */ + bool combine_enable; + + enum pxp_op_type op_type; + + /* LUT cleanup */ + __u64 lut_sels; + + /* the mode pxp's working against */ + enum pxp_working_mode working_mode; + enum pxp_engine_ctrl engine_enable; + + /* wfe */ +/* + * partial: + * 0 - full update + * 1 - partial update + * alpha_en: + * 0 - upd is {Y4[3:0],4'b0000} format + * 1 - upd is {Y4[3:0],3'b000,alpha} format + * reagl_en: + * 0 - use normal waveform algorithm + * 1 - enable reagl/-d waveform algorithm + * detection_only: + * 0 - write working buffer + * 1 - do no write working buffer, detection only + * lut: + * valid value 0-63 + * set to the lut used for next update + */ + bool partial_update; + bool alpha_en; + bool lut_update; + bool reagl_en; /* enable reagl/-d */ + bool reagl_d_en; /* enable reagl or reagl-d */ + bool detection_only; + bool pxp_legacy; + int lut; + bool lut_cleanup; + unsigned int lut_status_1; + unsigned int lut_status_2; + + /* Dithering specific data */ + int dither_mode; + unsigned int quant_bit; +}; + +struct pxp_config_data { + struct pxp_layer_param s0_param; + struct pxp_layer_param ol_param[1]; + struct pxp_layer_param out_param; + struct pxp_layer_param wfe_a_fetch_param[2]; + struct pxp_layer_param wfe_a_store_param[2]; + struct pxp_layer_param wfe_b_fetch_param[2]; + struct pxp_layer_param wfe_b_store_param[2]; + struct pxp_layer_param dither_fetch_param[2]; + struct pxp_layer_param dither_store_param[2]; + struct pxp_proc_data proc_data; + int layer_nr; + + /* Users don't touch */ + int handle; +}; + +#endif diff --git a/include/uapi/linux/seco_mu_ioctl.h b/include/uapi/linux/seco_mu_ioctl.h new file mode 100644 index 000000000000..578e38a5732f --- /dev/null +++ b/include/uapi/linux/seco_mu_ioctl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause*/ +/* + * Copyright 2019 NXP + */ + +#ifndef SECO_MU_IOCTL_H +#define SECO_MU_IOCTL_H + +/* IOCTL definitions. */ +struct seco_mu_ioctl_setup_iobuf { + uint8_t *user_buf; + uint32_t length; + uint32_t flags; + uint64_t seco_addr; +}; +struct seco_mu_ioctl_shared_mem_cfg { + uint32_t base_offset; + uint32_t size; +}; + +struct seco_mu_ioctl_get_mu_info { + uint8_t seco_mu_idx; + uint8_t interrupt_idx; + uint8_t tz; + uint8_t did; +}; + +struct seco_mu_ioctl_signed_message { + uint8_t *message; + uint32_t msg_size; + uint32_t error_code; +}; + +#define SECO_MU_IO_FLAGS_IS_INPUT (0x01u) +#define SECO_MU_IO_FLAGS_USE_SEC_MEM (0x02u) +#define SECO_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u) + +#define SECO_MU_IOCTL 0x0A /* like MISC_MAJOR. */ +#define SECO_MU_IOCTL_ENABLE_CMD_RCV _IO(SECO_MU_IOCTL, 0x01) +#define SECO_MU_IOCTL_SHARED_BUF_CFG _IOW(SECO_MU_IOCTL, 0x02, \ + struct seco_mu_ioctl_shared_mem_cfg) +#define SECO_MU_IOCTL_SETUP_IOBUF _IOWR(SECO_MU_IOCTL, 0x03, \ + struct seco_mu_ioctl_setup_iobuf) +#define SECO_MU_IOCTL_GET_MU_INFO _IOR(SECO_MU_IOCTL, 0x04, \ + struct seco_mu_ioctl_get_mu_info) +#define SECO_MU_IOCTL_SIGNED_MESSAGE _IOWR(SECO_MU_IOCTL, 0x05, \ + struct seco_mu_ioctl_signed_message) + +#endif diff --git a/include/uapi/linux/tee.h b/include/uapi/linux/tee.h index 688782e90140..31f71276f413 100644 --- a/include/uapi/linux/tee.h +++ b/include/uapi/linux/tee.h @@ -117,6 +117,35 @@ struct tee_ioctl_shm_alloc_data { struct tee_ioctl_shm_alloc_data) /** + * struct tee_ioctl_shm_register_fd_data - Shared memory registering argument + * @fd: [in] file descriptor identifying the shared memory + * @size: [out] Size of shared memory to allocate + * @flags: [in] Flags to/from allocation. + * @id: [out] Identifier of the shared memory + * + * The flags field should currently be zero as input. Updated by the call + * with actual flags as defined by TEE_IOCTL_SHM_* above. + * This structure is used as argument for TEE_IOC_SHM_ALLOC below. + */ +struct tee_ioctl_shm_register_fd_data { + __s64 fd; + __u64 size; + __u32 flags; + __s32 id; +} __aligned(8); + +/** + * TEE_IOC_SHM_REGISTER_FD - register a shared memory from a file descriptor + * + * Returns a file descriptor on success or < 0 on failure + * + * The returned file descriptor refers to the shared memory object in kernel + * land. The shared memory is freed when the descriptor is closed. + */ +#define TEE_IOC_SHM_REGISTER_FD _IOWR(TEE_IOC_MAGIC, TEE_IOC_BASE + 8, \ + struct tee_ioctl_shm_register_fd_data) + +/** * struct tee_ioctl_buf_data - Variable sized buffer * @buf_ptr: [in] A __user pointer to a buffer * @buf_len: [in] Length of the buffer above @@ -154,6 +183,13 @@ struct tee_ioctl_buf_data { */ #define TEE_IOCTL_PARAM_ATTR_TYPE_MASK 0xff +/* Meta parameter carrying extra information about the message. */ +#define TEE_IOCTL_PARAM_ATTR_META 0x100 + +/* Mask of all known attr bits */ +#define TEE_IOCTL_PARAM_ATTR_MASK \ + (TEE_IOCTL_PARAM_ATTR_TYPE_MASK | TEE_IOCTL_PARAM_ATTR_META) + /* * Matches TEEC_LOGIN_* in GP TEE Client API * Are only defined for GP compliant TEEs diff --git a/include/uapi/linux/usb/ch9.h b/include/uapi/linux/usb/ch9.h index 8512777889b0..2b158a736a6d 100644 --- a/include/uapi/linux/usb/ch9.h +++ b/include/uapi/linux/usb/ch9.h @@ -143,6 +143,8 @@ #define TEST_SE0_NAK 3 #define TEST_PACKET 4 #define TEST_FORCE_EN 5 +#define TEST_OTG_SRP_REQD 6 +#define TEST_OTG_HNP_REQD 7 /* * New Feature Selectors as added by USB 3.0 diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 1c095b5a99c5..4fa7c9be7806 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -511,6 +511,8 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') /* 32 ARGB-8-8-8-8 */ #define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */ +#define V4L2_PIX_FMT_RGBA v4l2_fourcc('R', 'G', 'B', 'A') /* 32 RGBA-8-8-8-8 */ + /* Grey formats */ #define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ #define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ @@ -539,6 +541,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ #define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ #define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ +#define V4L2_PIX_FMT_YUV24 v4l2_fourcc('Y', 'U', 'V', '3') /* 24 YUV-8-8-8 */ #define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ #define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ @@ -2246,13 +2249,11 @@ struct v4l2_event_subscription { /* VIDIOC_DBG_G_REGISTER and VIDIOC_DBG_S_REGISTER */ #define V4L2_CHIP_MATCH_BRIDGE 0 /* Match against chip ID on the bridge (0 for the bridge) */ -#define V4L2_CHIP_MATCH_SUBDEV 4 /* Match against subdev index */ - -/* The following four defines are no longer in use */ #define V4L2_CHIP_MATCH_HOST V4L2_CHIP_MATCH_BRIDGE #define V4L2_CHIP_MATCH_I2C_DRIVER 1 /* Match against I2C driver name */ #define V4L2_CHIP_MATCH_I2C_ADDR 2 /* Match against I2C 7-bit address */ #define V4L2_CHIP_MATCH_AC97 3 /* Match against ancillary AC97 chip */ +#define V4L2_CHIP_MATCH_SUBDEV 4 /* Match against subdev index */ struct v4l2_dbg_match { __u32 type; /* Match type */ @@ -2269,6 +2270,13 @@ struct v4l2_dbg_register { __u64 val; } __attribute__ ((packed)); +/* VIDIOC_DBG_G_CHIP_IDENT */ +struct v4l2_dbg_chip_ident { + struct v4l2_dbg_match match; + __u32 ident; /* chip identifier as specified in <media/v4l2-chip-ident.h> */ + __u32 revision; /* chip revision, chip specific */ +} __attribute__ ((packed)); + #define V4L2_CHIP_FL_READABLE (1 << 0) #define V4L2_CHIP_FL_WRITABLE (1 << 1) @@ -2373,6 +2381,12 @@ struct v4l2_create_buffers { #define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register) #define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register) +/* Experimental, meant for debugging, testing and internal use. + Never use this ioctl in applications! + Note: this ioctl is deprecated in favor of VIDIOC_DBG_G_CHIP_INFO and + will go away in the future. */ +#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident) + #define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) #define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) #define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) diff --git a/include/video/dpu.h b/include/video/dpu.h new file mode 100644 index 000000000000..e765651c44a6 --- /dev/null +++ b/include/video/dpu.h @@ -0,0 +1,893 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __DRM_DPU_H__ +#define __DRM_DPU_H__ + +#include <drm/drm_crtc.h> +#include <drm/drm_modes.h> +#include <video/imx8-prefetch.h> +#include <video/videomode.h> + +struct dpu_soc; + +enum dpu_irq { + IRQ_STORE9_SHDLOAD = 0, + IRQ_STORE9_FRAMECOMPLETE = 1, + IRQ_STORE9_SEQCOMPLETE = 2, + IRQ_EXTDST0_SHDLOAD = 3, + IRQ_EXTDST0_FRAMECOMPLETE = 4, + IRQ_EXTDST0_SEQCOMPLETE = 5, + IRQ_EXTDST4_SHDLOAD = 6, + IRQ_EXTDST4_FRAMECOMPLETE = 7, + IRQ_EXTDST4_SEQCOMPLETE = 8, + IRQ_EXTDST1_SHDLOAD = 9, + IRQ_EXTDST1_FRAMECOMPLETE = 10, + IRQ_EXTDST1_SEQCOMPLETE = 11, + IRQ_EXTDST5_SHDLOAD = 12, + IRQ_EXTDST5_FRAMECOMPLETE = 13, + IRQ_EXTDST5_SEQCOMPLETE = 14, + IRQ_STORE4_SHDLOAD = 15, + IRQ_STORE4_FRAMECOMPLETE = 16, + IRQ_STORE4_SEQCOMPLETE = 17, + IRQ_STORE5_SHDLOAD = 18, + IRQ_STORE5_FRAMECOMPLETE = 19, + IRQ_STORE5_SEQCOMPLETE = 20, + IRQ_RESERVED21 = 21, + IRQ_HISTOGRAM4_VALID = 22, + IRQ_RESERVED23 = 23, + IRQ_HISTOGRAM5_VALID = 24, + IRQ_FRAMEDUMP0_ERROR = 25, + IRQ_FRAMEDUMP1_ERROR = 26, + IRQ_DISENGCFG_SHDLOAD0 = 27, + IRQ_DISENGCFG_FRAMECOMPLETE0 = 28, + IRQ_DISENGCFG_SEQCOMPLETE0 = 29, + IRQ_FRAMEGEN0_INT0 = 30, + IRQ_FRAMEGEN0_INT1 = 31, + IRQ_FRAMEGEN0_INT2 = 32, + IRQ_FRAMEGEN0_INT3 = 33, + IRQ_SIG0_SHDLOAD = 34, + IRQ_SIG0_VALID = 35, + IRQ_SIG0_ERROR = 36, + IRQ_DISENGCFG_SHDLOAD1 = 37, + IRQ_DISENGCFG_FRAMECOMPLETE1 = 38, + IRQ_DISENGCFG_SEQCOMPLETE1 = 39, + IRQ_FRAMEGEN1_INT0 = 40, + IRQ_FRAMEGEN1_INT1 = 41, + IRQ_FRAMEGEN1_INT2 = 42, + IRQ_FRAMEGEN1_INT3 = 43, + IRQ_SIG1_SHDLOAD = 44, + IRQ_SIG1_VALID = 45, + IRQ_SIG1_ERROR = 46, + IRQ_ITUIFC4_ERROR = 47, + IRQ_ITUIFC5_ERROR = 48, + IRQ_RESERVED49 = 49, + IRQ_CMDSEQ_ERROR = 50, + IRQ_COMCTRL_SW0 = 51, + IRQ_COMCTRL_SW1 = 52, + IRQ_COMCTRL_SW2 = 53, + IRQ_COMCTRL_SW3 = 54, + IRQ_FRAMEGEN0_PRIMSYNC_ON = 55, + IRQ_FRAMEGEN0_PRIMSYNC_OFF = 56, + IRQ_FRAMEGEN0_SECSYNC_ON = 57, + IRQ_FRAMEGEN0_SECSYNC_OFF = 58, + IRQ_FRAMEGEN1_PRIMSYNC_ON = 59, + IRQ_FRAMEGEN1_PRIMSYNC_OFF = 60, + IRQ_FRAMEGEN1_SECSYNC_ON = 61, + IRQ_FRAMEGEN1_SECSYNC_OFF = 62, + IRQ_FRAMECAP4_SYNC_ON = 63, + IRQ_FRAMECAP4_SYNC_OFF = 64, + IRQ_CMD = 65, + IRQ_FRAMECAP5_SYNC_OFF = 66, +}; + +typedef enum { + ID_NONE = 0x00, /* 0 */ + /* pixel engines */ + ID_FETCHDECODE9 = 0x01, /* 1 */ + ID_FETCHPERSP9 = 0x02, /* 2 */ + ID_FETCHECO9 = 0x03, /* 3 */ + ID_ROP9 = 0x04, /* 4 */ + ID_CLUT9 = 0x05, /* 5 */ + ID_MATRIX9 = 0x06, /* 6 */ + ID_HSCALER9 = 0x07, /* 7 */ + ID_VSCALER9 = 0x08, /* 8 */ + ID_FILTER9 = 0x09, /* 9 */ + ID_BLITBLEND9 = 0x0A, /* 10 */ + ID_STORE9 = 0x0B, /* 11 */ + ID_CONSTFRAME0 = 0x0C, /* 12 */ + ID_EXTDST0 = 0x0D, /* 13 */ + ID_CONSTFRAME4 = 0x0E, /* 14 */ + ID_EXTDST4 = 0x0F, /* 15 */ + ID_CONSTFRAME1 = 0x10, /* 16 */ + ID_EXTDST1 = 0x11, /* 17 */ + ID_CONSTFRAME5 = 0x12, /* 18 */ + ID_EXTDST5 = 0x13, /* 19 */ + ID_EXTSRC4 = 0x14, /* 20 */ + ID_STORE4 = 0x15, /* 21 */ + ID_EXTSRC5 = 0x16, /* 22 */ + ID_STORE5 = 0x17, /* 23 */ + ID_FETCHDECODE2 = 0x18, /* 24 */ + ID_FETCHDECODE3 = 0x19, /* 25 */ + ID_FETCHWARP2 = 0x1A, /* 26 */ + ID_FETCHECO2 = 0x1B, /* 27 */ + ID_FETCHDECODE0 = 0x1C, /* 28 */ + ID_FETCHECO0 = 0x1D, /* 29 */ + ID_FETCHDECODE1 = 0x1E, /* 30 */ + ID_FETCHECO1 = 0x1F, /* 31 */ + ID_FETCHLAYER0 = 0x20, /* 32 */ + ID_FETCHLAYER1 = 0x21, /* 33 */ + ID_GAMMACOR4 = 0x22, /* 34 */ + ID_MATRIX4 = 0x23, /* 35 */ + ID_HSCALER4 = 0x24, /* 36 */ + ID_VSCALER4 = 0x25, /* 37 */ + ID_HISTOGRAM4 = 0x26, /* 38 */ + ID_GAMMACOR5 = 0x27, /* 39 */ + ID_MATRIX5 = 0x28, /* 40 */ + ID_HSCALER5 = 0x29, /* 41 */ + ID_VSCALER5 = 0x2A, /* 42 */ + ID_HISTOGRAM5 = 0x2B, /* 43 */ + ID_LAYERBLEND0 = 0x2C, /* 44 */ + ID_LAYERBLEND1 = 0x2D, /* 45 */ + ID_LAYERBLEND2 = 0x2E, /* 46 */ + ID_LAYERBLEND3 = 0x2F, /* 47 */ + ID_LAYERBLEND4 = 0x30, /* 48 */ + ID_LAYERBLEND5 = 0x31, /* 49 */ + ID_LAYERBLEND6 = 0x32, /* 50 */ + ID_EXTSRC0 = 0x33, /* 51 */ + ID_EXTSRC1 = 0x34, /* 52 */ + /* display engines */ + ID_DISENGCFG = 0x35, /* 53 */ + ID_FRAMEGEN0 = 0x36, /* 54 */ + ID_MATRIX0 = 0x37, /* 55 */ + ID_GAMMACOR0 = 0x38, /* 56 */ + ID_DITHER0 = 0x39, /* 57 */ + ID_TCON0 = 0x3A, /* 58 */ + ID_SIG0 = 0x3B, /* 59 */ + ID_FRAMEGEN1 = 0x3C, /* 60 */ + ID_MATRIX1 = 0x3D, /* 61 */ + ID_GAMMACOR1 = 0x3E, /* 62 */ + ID_DITHER1 = 0x3F, /* 63 */ + ID_TCON1 = 0x40, /* 64 */ + ID_SIG1 = 0x41, /* 65 */ + ID_FRAMECAP4 = 0x42, /* 66 */ + ID_FRAMECAP5 = 0x43, /* 67 */ +} dpu_block_id_t; + +typedef enum { + DEC_SIG_SEL_FRAMEGEN = 0, + DEC_SIG_SEL_GAMMACOR, + DEC_SIG_SEL_MATRIX, + DEC_SIG_SEL_DITHER, +} dec_sig_sel_t; + +typedef enum { + ED_SRC_DISABLE = ID_NONE, + ED_SRC_BLITBLEND9 = ID_BLITBLEND9, + ED_SRC_CONSTFRAME0 = ID_CONSTFRAME0, + ED_SRC_CONSTFRAME1 = ID_CONSTFRAME1, + ED_SRC_CONSTFRAME4 = ID_CONSTFRAME4, + ED_SRC_CONSTFRAME5 = ID_CONSTFRAME5, + ED_SRC_MATRIX4 = ID_MATRIX4, + ED_SRC_HSCALER4 = ID_HSCALER4, + ED_SRC_VSCALER4 = ID_VSCALER4, + /* content stream(extdst 0/1) only */ + ED_SRC_EXTSRC4 = ID_EXTSRC4, + ED_SRC_MATRIX5 = ID_MATRIX5, + ED_SRC_HSCALER5 = ID_HSCALER5, + ED_SRC_VSCALER5 = ID_VSCALER5, + /* content stream(extdst 0/1) only */ + ED_SRC_EXTSRC5 = ID_EXTSRC5, + ED_SRC_LAYERBLEND6 = ID_LAYERBLEND6, + ED_SRC_LAYERBLEND5 = ID_LAYERBLEND5, + ED_SRC_LAYERBLEND4 = ID_LAYERBLEND4, + ED_SRC_LAYERBLEND3 = ID_LAYERBLEND3, + ED_SRC_LAYERBLEND2 = ID_LAYERBLEND2, + ED_SRC_LAYERBLEND1 = ID_LAYERBLEND1, + ED_SRC_LAYERBLEND0 = ID_LAYERBLEND0, +} extdst_src_sel_t; + +typedef enum { + SINGLE, /* Reconfig pipeline after explicit trigger */ + AUTO, /* Reconfig pipeline after every kick when idle */ +} ed_sync_mode_t; + +typedef enum { + PSTATUS_EMPTY, + PSTATUS_RUNNING, + PSTATUS_RUNNING_RETRIGGERED, + PSTATUS_RESERVED +} ed_pipeline_status_t; + +typedef enum { + SOFTWARE = 0, /* kick generation by KICK field only */ + EXTERNAL = BIT(8), /* kick signal from external allowed */ +} ed_kick_mode_t; + +typedef enum { + SHLDREQID_FETCHDECODE9 = BIT(1), + SHLDREQID_FETCHPERSP9 = BIT(2), + SHLDREQID_FETCHECO9 = BIT(3), + SHLDREQID_CONSTFRAME0 = BIT(4), + SHLDREQID_CONSTFRAME4 = BIT(5), + SHLDREQID_CONSTFRAME1 = BIT(6), + SHLDREQID_CONSTFRAME5 = BIT(7), + SHLDREQID_EXTSRC4 = BIT(8), + SHLDREQID_EXTSRC5 = BIT(9), + SHLDREQID_FETCHDECODE2 = BIT(10), + SHLDREQID_FETCHDECODE3 = BIT(11), + SHLDREQID_FETCHWARP2 = BIT(12), + SHLDREQID_FETCHECO2 = BIT(13), + SHLDREQID_FETCHDECODE0 = BIT(14), + SHLDREQID_FETCHECO0 = BIT(15), + SHLDREQID_FETCHDECODE1 = BIT(16), + SHLDREQID_FETCHECO1 = BIT(17), + SHLDREQID_FETCHLAYER0 = BIT(18), + SHLDREQID_FETCHLAYER1 = BIT(19), + SHLDREQID_EXTSRC0 = BIT(20), + SHLDREQID_EXTSRC1 = BIT(21), +} shadow_load_req_t; + +typedef enum { + PIXENGCFG_STATUS_SEL_DISABLE, + PIXENGCFG_STATUS_SEL_STORE9, + PIXENGCFG_STATUS_SEL_EXTDST0, + PIXENGCFG_STATUS_SEL_EXTDST4, + PIXENGCFG_STATUS_SEL_EXTDST1, + PIXENGCFG_STATUS_SEL_EXTDST5, + PIXENGCFG_STATUS_SEL_STORE4, + PIXENGCFG_STATUS_SEL_STORE5, +} pixengcfg_status_sel_t; + +typedef enum { + FD_SRC_DISABLE = ID_NONE, + FD_SRC_FETCHECO0 = ID_FETCHECO0, + FD_SRC_FETCHECO1 = ID_FETCHECO1, + FD_SRC_FETCHECO2 = ID_FETCHECO2, + FD_SRC_FETCHDECODE0 = ID_FETCHDECODE0, + FD_SRC_FETCHDECODE1 = ID_FETCHDECODE1, + FD_SRC_FETCHDECODE2 = ID_FETCHDECODE2, + FD_SRC_FETCHDECODE3 = ID_FETCHDECODE3, + FD_SRC_FETCHWARP2 = ID_FETCHWARP2, +} fd_dynamic_src_sel_t; + +typedef enum { + /* RL and RLAD decoder */ + FETCHTYPE__DECODE, + /* fractional plane(8 layers) */ + FETCHTYPE__LAYER, + /* arbitrary warping and fractional plane(8 layers) */ + FETCHTYPE__WARP, + /* minimum feature set for alpha, chroma and coordinate planes */ + FETCHTYPE__ECO, + /* affine, perspective and arbitrary warping */ + FETCHTYPE__PERSP, + /* affine and arbitrary warping */ + FETCHTYPE__ROT, + /* RL and RLAD decoder, reduced feature set */ + FETCHTYPE__DECODEL, + /* fractional plane(8 layers), reduced feature set */ + FETCHTYPE__LAYERL, + /* affine and arbitrary warping, reduced feature set */ + FETCHTYPE__ROTL, +} fetchtype_t; + +typedef enum { + /* No side-by-side synchronization. */ + FGSYNCMODE__OFF = 0, + /* Framegen is master. */ + FGSYNCMODE__MASTER = 1 << 1, + /* Runs in cyclic synchronization mode. */ + FGSYNCMODE__SLAVE_CYC = 2 << 1, + /* Runs in one time synchronization mode. */ + FGSYNCMODE__SLAVE_ONCE = 3 << 1, +} fgsyncmode_t; + +typedef enum { + FGDM__BLACK, + /* Constant Color Background is shown. */ + FGDM__CONSTCOL, + FGDM__PRIM, + FGDM__SEC, + FGDM__PRIM_ON_TOP, + FGDM__SEC_ON_TOP, + /* White color background with test pattern is shown. */ + FGDM__TEST, +} fgdm_t; + +typedef enum { + HS_SRC_SEL__DISABLE = ID_NONE, + HS_SRC_SEL__MATRIX9 = ID_MATRIX9, + HS_SRC_SEL__VSCALER9 = ID_VSCALER9, + HS_SRC_SEL__FILTER9 = ID_FILTER9, + HS_SRC_SEL__EXTSRC4 = ID_EXTSRC4, + HS_SRC_SEL__EXTSRC5 = ID_EXTSRC5, + HS_SRC_SEL__FETCHDECODE2 = ID_FETCHDECODE2, + HS_SRC_SEL__FETCHDECODE3 = ID_FETCHDECODE3, + HS_SRC_SEL__FETCHDECODE0 = ID_FETCHDECODE0, + HS_SRC_SEL__FETCHDECODE1 = ID_FETCHDECODE1, + HS_SRC_SEL__MATRIX4 = ID_MATRIX4, + HS_SRC_SEL__VSCALER4 = ID_VSCALER4, + HS_SRC_SEL__MATRIX5 = ID_MATRIX5, + HS_SRC_SEL__VSCALER5 = ID_VSCALER5, +} hs_src_sel_t; + +typedef enum { + /* common options */ + LB_PRIM_SEL__DISABLE = ID_NONE, + LB_PRIM_SEL__BLITBLEND9 = ID_BLITBLEND9, + LB_PRIM_SEL__CONSTFRAME0 = ID_CONSTFRAME0, + LB_PRIM_SEL__CONSTFRAME1 = ID_CONSTFRAME1, + LB_PRIM_SEL__CONSTFRAME4 = ID_CONSTFRAME4, + LB_PRIM_SEL__CONSTFRAME5 = ID_CONSTFRAME5, + LB_PRIM_SEL__MATRIX4 = ID_MATRIX4, + LB_PRIM_SEL__HSCALER4 = ID_HSCALER4, + LB_PRIM_SEL__VSCALER4 = ID_VSCALER4, + LB_PRIM_SEL__EXTSRC4 = ID_EXTSRC4, + LB_PRIM_SEL__MATRIX5 = ID_MATRIX5, + LB_PRIM_SEL__HSCALER5 = ID_HSCALER5, + LB_PRIM_SEL__VSCALER5 = ID_VSCALER5, + LB_PRIM_SEL__EXTSRC5 = ID_EXTSRC5, + /* + * special options: + * layerblend(n) has n special options, + * from layerblend0 to layerblend(n - 1), e.g., + * layerblend4 has 4 special options - + * layerblend0/1/2/3. + */ + LB_PRIM_SEL__LAYERBLEND5 = ID_LAYERBLEND5, + LB_PRIM_SEL__LAYERBLEND4 = ID_LAYERBLEND4, + LB_PRIM_SEL__LAYERBLEND3 = ID_LAYERBLEND3, + LB_PRIM_SEL__LAYERBLEND2 = ID_LAYERBLEND2, + LB_PRIM_SEL__LAYERBLEND1 = ID_LAYERBLEND1, + LB_PRIM_SEL__LAYERBLEND0 = ID_LAYERBLEND0, +} lb_prim_sel_t; + +typedef enum { + LB_SEC_SEL__DISABLE = ID_NONE, + LB_SEC_SEL__FETCHDECODE2 = ID_FETCHDECODE2, + LB_SEC_SEL__FETCHDECODE3 = ID_FETCHDECODE3, + LB_SEC_SEL__FETCHWARP2 = ID_FETCHWARP2, + LB_SEC_SEL__FETCHDECODE0 = ID_FETCHDECODE0, + LB_SEC_SEL__FETCHDECODE1 = ID_FETCHDECODE1, + LB_SEC_SEL__MATRIX4 = ID_MATRIX4, + LB_SEC_SEL__HSCALER4 = ID_HSCALER4, + LB_SEC_SEL__VSCALER4 = ID_VSCALER4, + LB_SEC_SEL__MATRIX5 = ID_MATRIX5, + LB_SEC_SEL__HSCALER5 = ID_HSCALER5, + LB_SEC_SEL__VSCALER5 = ID_VSCALER5, + LB_SEC_SEL__FETCHLAYER0 = ID_FETCHLAYER0, + LB_SEC_SEL__FETCHLAYER1 = ID_FETCHLAYER1, +} lb_sec_sel_t; + +typedef enum { + PRIMARY, /* background plane */ + SECONDARY, /* foreground plane */ + BOTH, +} lb_shadow_sel_t; + +typedef enum { + LB_NEUTRAL, /* Output is same as primary input. */ + LB_BLEND, +} lb_mode_t; + +typedef enum { + /* Constant 0 indicates frame or top field. */ + SCALER_ALWAYS0 = 0x0, + /* Constant 1 indicates bottom field. */ + SCALER_ALWAYS1 = 0x1 << 12, + /* Output field polarity is taken from input field polarity. */ + SCALER_INPUT = 0x2 << 12, + /* Output field polarity toggles, starting with 0 after reset. */ + SCALER_TOGGLE = 0x3 << 12, +} scaler_field_mode_t; + +typedef enum { + /* pointer-sampling */ + SCALER_NEAREST = 0x0, + /* box filter */ + SCALER_LINEAR = 0x100, +} scaler_filter_mode_t; + +typedef enum { + SCALER_DOWNSCALE = 0x0, + SCALER_UPSCALE = 0x10, +} scaler_scale_mode_t; + +typedef enum { + /* Pixel by-pass the scaler, all other settings are ignored. */ + SCALER_NEUTRAL = 0x0, + /* Scaler is active. */ + SCALER_ACTIVE = 0x1, +} scaler_mode_t; + +typedef enum { + VS_SRC_SEL__DISABLE = ID_NONE, + VS_SRC_SEL__MATRIX9 = ID_MATRIX9, + VS_SRC_SEL__HSCALER9 = ID_HSCALER9, + VS_SRC_SEL__EXTSRC4 = ID_EXTSRC4, + VS_SRC_SEL__EXTSRC5 = ID_EXTSRC5, + VS_SRC_SEL__FETCHDECODE2 = ID_FETCHDECODE2, + VS_SRC_SEL__FETCHDECODE3 = ID_FETCHDECODE3, + VS_SRC_SEL__FETCHDECODE0 = ID_FETCHDECODE0, + VS_SRC_SEL__FETCHDECODE1 = ID_FETCHDECODE1, + VS_SRC_SEL__MATRIX4 = ID_MATRIX4, + VS_SRC_SEL__HSCALER4 = ID_HSCALER4, + VS_SRC_SEL__MATRIX5 = ID_MATRIX5, + VS_SRC_SEL__HSCALER5 = ID_HSCALER5, +} vs_src_sel_t; + +#define CLKEN_MASK (0x3 << 24) +#define CLKEN_MASK_SHIFT 24 +typedef enum { + CLKEN__DISABLE = 0x0, + CLKEN__AUTOMATIC = 0x1, + CLKEN__FULL = 0x3, +} pixengcfg_clken_t; + +/* fetch unit types */ +enum { + FU_T_NA, + FU_T_FD, + FU_T_FE, + FU_T_FL, + FU_T_FW, +}; + +enum dpu_crc_source { + DPU_CRC_SRC_NONE, + DPU_CRC_SRC_FRAMEGEN, + DPU_CRC_SRC_FRAMEGEN_ROI, +}; + +struct dpu_fetchunit; + +struct dpu_fetchunit_ops { + void (*set_burstlength)(struct dpu_fetchunit *fu, + unsigned int x_offset, unsigned int mt_w, + int bpp, dma_addr_t baddr, bool use_prefetch); + + void (*set_baseaddress)(struct dpu_fetchunit *fu, unsigned int width, + unsigned int x_offset, unsigned int y_offset, + unsigned int mt_w, unsigned int mt_h, + int bpp, dma_addr_t baddr); + + void (*set_src_bpp)(struct dpu_fetchunit *fu, int bpp); + + void (*set_src_stride)(struct dpu_fetchunit *fu, + unsigned int width, unsigned int x_offset, + unsigned int mt_w, int bpp, unsigned int stride, + dma_addr_t baddr, bool use_prefetch); + + void (*set_src_buf_dimensions)(struct dpu_fetchunit *fu, + unsigned int w, unsigned int h, u32 fmt, + bool deinterlace); + + void (*set_fmt)(struct dpu_fetchunit *fu, u32 fmt, + enum drm_color_encoding color_encoding, + enum drm_color_range color_range, + bool deinterlace); + + void (*set_pixel_blend_mode)(struct dpu_fetchunit *fu, + unsigned int pixel_blend_mode, u16 alpha, + u32 fb_format); + + void (*enable_src_buf)(struct dpu_fetchunit *fu); + void (*disable_src_buf)(struct dpu_fetchunit *fu); + bool (*is_enabled)(struct dpu_fetchunit *fu); + + void (*set_framedimensions)(struct dpu_fetchunit *fu, + unsigned int w, unsigned int h, + bool deinterlace); + + void (*set_controltrigger)(struct dpu_fetchunit *fu); + + unsigned int (*get_stream_id)(struct dpu_fetchunit *fu); + void (*set_stream_id)(struct dpu_fetchunit *fu, unsigned int id); +}; + +struct dpu_fetchunit { + void __iomem *pec_base; + void __iomem *base; + char *name; + struct mutex mutex; + int id; + int sub_id; /* for fractional fetch units */ + int type; + bool inuse; + struct dpu_soc *dpu; + /* see DPU_PLANE_SRC_xxx */ + unsigned int stream_id; + struct dprc *dprc; + const struct dpu_fetchunit_ops *ops; +}; + +int dpu_map_inner_irq(struct dpu_soc *dpu, int irq); + +/* Constant Frame Unit */ +struct dpu_constframe; +void constframe_shden(struct dpu_constframe *cf, bool enable); +void constframe_framedimensions(struct dpu_constframe *cf, unsigned int w, + unsigned int h); +void constframe_constantcolor(struct dpu_constframe *cf, unsigned int r, + unsigned int g, unsigned int b, unsigned int a); +void constframe_controltrigger(struct dpu_constframe *cf, bool trigger); +shadow_load_req_t constframe_to_shdldreq_t(struct dpu_constframe *cf); +struct dpu_constframe *dpu_cf_get(struct dpu_soc *dpu, int id); +void dpu_cf_put(struct dpu_constframe *cf); +struct dpu_constframe *dpu_aux_cf_peek(struct dpu_constframe *cf); + +/* Display Engine Configuration Unit */ +struct dpu_disengcfg; +void disengcfg_polarity_ctrl(struct dpu_disengcfg *dec, unsigned int flags); +void disengcfg_sig_select(struct dpu_disengcfg *dec, dec_sig_sel_t sig_sel); +struct dpu_disengcfg *dpu_dec_get(struct dpu_soc *dpu, int id); +void dpu_dec_put(struct dpu_disengcfg *dec); +struct dpu_disengcfg *dpu_aux_dec_peek(struct dpu_disengcfg *dec); + +/* External Destination Unit */ +struct dpu_extdst; +void extdst_pixengcfg_shden(struct dpu_extdst *ed, bool enable); +void extdst_pixengcfg_powerdown(struct dpu_extdst *ed, bool powerdown); +void extdst_pixengcfg_sync_mode(struct dpu_extdst *ed, ed_sync_mode_t mode); +void extdst_pixengcfg_reset(struct dpu_extdst *ed, bool reset); +void extdst_pixengcfg_div(struct dpu_extdst *ed, u16 div); +void extdst_pixengcfg_syncmode_master(struct dpu_extdst *ed, bool enable); +int extdst_pixengcfg_src_sel(struct dpu_extdst *ed, extdst_src_sel_t src); +void extdst_pixengcfg_sel_shdldreq(struct dpu_extdst *ed); +void extdst_pixengcfg_shdldreq(struct dpu_extdst *ed, u32 req_mask); +void extdst_pixengcfg_sync_trigger(struct dpu_extdst *ed); +void extdst_pixengcfg_trigger_sequence_complete(struct dpu_extdst *ed); +bool extdst_pixengcfg_is_sync_busy(struct dpu_extdst *ed); +ed_pipeline_status_t extdst_pixengcfg_pipeline_status(struct dpu_extdst *ed); +void extdst_shden(struct dpu_extdst *ed, bool enable); +void extdst_kick_mode(struct dpu_extdst *ed, ed_kick_mode_t mode); +void extdst_perfcountmode(struct dpu_extdst *ed, bool enable); +void extdst_gamma_apply_enable(struct dpu_extdst *ed, bool enable); +void extdst_kick(struct dpu_extdst *ed); +void extdst_cnt_err_clear(struct dpu_extdst *ed); +bool extdst_cnt_err_status(struct dpu_extdst *ed); +u32 extdst_last_control_word(struct dpu_extdst *ed); +void extdst_pixel_cnt(struct dpu_extdst *ed, u16 *x, u16 *y); +void extdst_last_pixel_cnt(struct dpu_extdst *ed, u16 *x, u16 *y); +u32 extdst_perfresult(struct dpu_extdst *ed); +bool extdst_is_master(struct dpu_extdst *ed); +struct dpu_extdst *dpu_ed_get(struct dpu_soc *dpu, int id); +void dpu_ed_put(struct dpu_extdst *ed); +struct dpu_extdst *dpu_aux_ed_peek(struct dpu_extdst *ed); + +/* Fetch Decode Unit */ +int fetchdecode_pixengcfg_dynamic_src_sel(struct dpu_fetchunit *fu, + fd_dynamic_src_sel_t src); +void fetchdecode_layeroffset(struct dpu_fetchunit *fd, unsigned int x, + unsigned int y); +void fetchdecode_clipoffset(struct dpu_fetchunit *fd, unsigned int x, + unsigned int y); +void fetchdecode_clipdimensions(struct dpu_fetchunit *fd, unsigned int w, + unsigned int h); +void fetchdecode_rgb_constantcolor(struct dpu_fetchunit *fd, + u8 r, u8 g, u8 b, u8 a); +void fetchdecode_yuv_constantcolor(struct dpu_fetchunit *fd, + u8 y, u8 u, u8 v); +int fetchdecode_fetchtype(struct dpu_fetchunit *fd, fetchtype_t *type); +shadow_load_req_t fetchdecode_to_shdldreq_t(struct dpu_fetchunit *fd); +u32 fetchdecode_get_vproc_mask(struct dpu_fetchunit *fd); +bool fetchdecode_need_fetcheco(struct dpu_fetchunit *fd, u32 fmt); +struct dpu_fetchunit *dpu_fd_get(struct dpu_soc *dpu, int id); +void dpu_fd_put(struct dpu_fetchunit *fu); + +/* Fetch ECO Unit */ +void fetcheco_layeroffset(struct dpu_fetchunit *fu, unsigned int x, + unsigned int y); +void fetcheco_clipoffset(struct dpu_fetchunit *fu, unsigned int x, + unsigned int y); +void fetcheco_clipdimensions(struct dpu_fetchunit *fu, unsigned int w, + unsigned int h); +void fetcheco_frameresampling(struct dpu_fetchunit *fu, unsigned int x, + unsigned int y); +int fetcheco_fetchtype(struct dpu_fetchunit *fu, fetchtype_t *type); +dpu_block_id_t fetcheco_get_block_id(struct dpu_fetchunit *fu); +struct dpu_fetchunit *dpu_fe_get(struct dpu_soc *dpu, int id); +void dpu_fe_put(struct dpu_fetchunit *fu); + +/* Fetch Layer Unit */ +void fetchlayer_rgb_constantcolor(struct dpu_fetchunit *fu, + u8 r, u8 g, u8 b, u8 a); +void fetchlayer_yuv_constantcolor(struct dpu_fetchunit *fu, u8 y, u8 u, u8 v); +int fetchlayer_fetchtype(struct dpu_fetchunit *fu, fetchtype_t *type); +struct dpu_fetchunit *dpu_fl_get(struct dpu_soc *dpu, int id); +void dpu_fl_put(struct dpu_fetchunit *fu); + +/* Fetch Warp Unit */ +void fetchwarp_rgb_constantcolor(struct dpu_fetchunit *fu, + u8 r, u8 g, u8 b, u8 a); +void fetchwarp_yuv_constantcolor(struct dpu_fetchunit *fu, u8 y, u8 u, u8 v); +int fetchwarp_fetchtype(struct dpu_fetchunit *fu, fetchtype_t *type); +struct dpu_fetchunit *dpu_fw_get(struct dpu_soc *dpu, int id); +void dpu_fw_put(struct dpu_fetchunit *fu); + +/* Frame Generator Unit */ +struct dpu_framegen; +void framegen_enable(struct dpu_framegen *fg); +void framegen_disable(struct dpu_framegen *fg); +void framegen_enable_pixel_link(struct dpu_framegen *fg); +void framegen_disable_pixel_link(struct dpu_framegen *fg); +void framegen_shdtokgen(struct dpu_framegen *fg); +void framegen_syncmode(struct dpu_framegen *fg, fgsyncmode_t mode); +void +framegen_cfg_videomode(struct dpu_framegen *fg, + struct drm_display_mode *m, bool side_by_side, + bool encoder_type_has_tmds, bool encoder_type_has_lvds); +void framegen_pkickconfig(struct dpu_framegen *fg, bool enable); +void framegen_syncmode_fixup(struct dpu_framegen *fg, bool enable); +void framegen_displaymode(struct dpu_framegen *fg, fgdm_t mode); +void framegen_panic_displaymode(struct dpu_framegen *fg, fgdm_t mode); +void framegen_wait_done(struct dpu_framegen *fg, struct drm_display_mode *m); +void framegen_read_timestamp(struct dpu_framegen *fg, + u32 *frame_index, u32 *line_index); +void framegen_wait_for_frame_counter_moving(struct dpu_framegen *fg); +bool framegen_secondary_requests_to_read_empty_fifo(struct dpu_framegen *fg); +void framegen_secondary_clear_channel_status(struct dpu_framegen *fg); +bool framegen_secondary_is_syncup(struct dpu_framegen *fg); +void framegen_wait_for_secondary_syncup(struct dpu_framegen *fg); +void framegen_enable_clock(struct dpu_framegen *fg); +void framegen_disable_clock(struct dpu_framegen *fg); +bool framegen_is_master(struct dpu_framegen *fg); +bool framegen_is_slave(struct dpu_framegen *fg); +struct dpu_framegen *dpu_fg_get(struct dpu_soc *dpu, int id); +void dpu_fg_put(struct dpu_framegen *fg); +struct dpu_framegen *dpu_aux_fg_peek(struct dpu_framegen *fg); + +/* Horizontal Scaler Unit */ +struct dpu_hscaler; +int hscaler_pixengcfg_dynamic_src_sel(struct dpu_hscaler *hs, hs_src_sel_t src); +void hscaler_pixengcfg_clken(struct dpu_hscaler *hs, pixengcfg_clken_t clken); +void hscaler_shden(struct dpu_hscaler *hs, bool enable); +void hscaler_setup1(struct dpu_hscaler *hs, unsigned int src, unsigned int dst); +void hscaler_setup2(struct dpu_hscaler *hs, u32 phase_offset); +void hscaler_output_size(struct dpu_hscaler *hs, u32 line_num); +void hscaler_filter_mode(struct dpu_hscaler *hs, scaler_filter_mode_t m); +void hscaler_scale_mode(struct dpu_hscaler *hs, scaler_scale_mode_t m); +void hscaler_mode(struct dpu_hscaler *hs, scaler_mode_t m); +bool hscaler_is_enabled(struct dpu_hscaler *hs); +dpu_block_id_t hscaler_get_block_id(struct dpu_hscaler *hs); +unsigned int hscaler_get_stream_id(struct dpu_hscaler *hs); +void hscaler_set_stream_id(struct dpu_hscaler *hs, unsigned int id); +struct dpu_hscaler *dpu_hs_get(struct dpu_soc *dpu, int id); +void dpu_hs_put(struct dpu_hscaler *hs); + +/* Layer Blend Unit */ +struct dpu_layerblend; +int layerblend_pixengcfg_dynamic_prim_sel(struct dpu_layerblend *lb, + lb_prim_sel_t prim); +void layerblend_pixengcfg_dynamic_sec_sel(struct dpu_layerblend *lb, + lb_sec_sel_t sec); +void layerblend_pixengcfg_clken(struct dpu_layerblend *lb, + pixengcfg_clken_t clken); +void layerblend_shden(struct dpu_layerblend *lb, bool enable); +void layerblend_shdtoksel(struct dpu_layerblend *lb, lb_shadow_sel_t sel); +void layerblend_shdldsel(struct dpu_layerblend *lb, lb_shadow_sel_t sel); +void layerblend_control(struct dpu_layerblend *lb, lb_mode_t mode); +void layerblend_blendcontrol(struct dpu_layerblend *lb, unsigned int zpos, + unsigned int pixel_blend_mode, u16 alpha); +void layerblend_position(struct dpu_layerblend *lb, int x, int y); +struct dpu_layerblend *dpu_lb_get(struct dpu_soc *dpu, int id); +void dpu_lb_put(struct dpu_layerblend *lb); + +/* Signature Unit */ +#define MAX_DPU_SIGNATURE_WIN_NUM 8 +struct dpu_signature; +void signature_shden(struct dpu_signature *sig, bool enable); +void signature_shdldsel_local(struct dpu_signature *sig); +void signature_shdldsel_global(struct dpu_signature *sig); +void +signature_global_panic(struct dpu_signature *sig, unsigned int win, bool enable); +void +signature_local_panic(struct dpu_signature *sig, unsigned int win, bool enable); +void +signature_alpha_mask(struct dpu_signature *sig, unsigned int win, bool enable); +void signature_crc(struct dpu_signature *sig, unsigned int win, bool enable); +void +signature_eval_win(struct dpu_signature *sig, unsigned int win, bool enable); +void signature_win(struct dpu_signature *sig, unsigned int win, + int xul, int yul, int xlr, int ylr); +void signature_crc_value(struct dpu_signature *sig, unsigned int win, + u32 *red, u32 *green, u32 *blue); +void signature_shdldreq(struct dpu_signature *sig, u8 win_mask); +void signature_continuous_mode(struct dpu_signature *sig, bool enable); +void signature_kick(struct dpu_signature *sig); +bool signature_is_idle(struct dpu_signature *sig); +void signature_wait_for_idle(struct dpu_signature *sig); +bool signature_is_valid(struct dpu_signature *sig); +bool signature_is_error(struct dpu_signature *sig, u8 *err_win_mask); +struct dpu_signature *dpu_sig_get(struct dpu_soc *dpu, int id); +void dpu_sig_put(struct dpu_signature *sig); +struct dpu_signature *dpu_aux_sig_peek(struct dpu_signature *sig); + +/* Store Unit */ +struct dpu_store; +void store_pixengcfg_syncmode_fixup(struct dpu_store *st, bool enable); +struct dpu_store *dpu_st_get(struct dpu_soc *dpu, int id); +void dpu_st_put(struct dpu_store *st); + +/* Timing Controller Unit */ +struct dpu_tcon; +int tcon_set_fmt(struct dpu_tcon *tcon, u32 bus_format); +void tcon_set_operation_mode(struct dpu_tcon *tcon); +void tcon_cfg_videomode(struct dpu_tcon *tcon, + struct drm_display_mode *m, bool side_by_side); +bool tcon_is_master(struct dpu_tcon *tcon); +bool tcon_is_slave(struct dpu_tcon *tcon); +void tcon_configure_pc(struct dpu_tcon *tcon, unsigned int di, + unsigned int frame_width, u32 mode, u32 format); +void tcon_enable_pc(struct dpu_tcon *tcon); +void tcon_disable_pc(struct dpu_tcon *tcon); +struct dpu_tcon *dpu_tcon_get(struct dpu_soc *dpu, int id); +void dpu_tcon_put(struct dpu_tcon *tcon); +struct dpu_tcon *dpu_aux_tcon_peek(struct dpu_tcon *tcon); + +/* Vertical Scaler Unit */ +struct dpu_vscaler; +int vscaler_pixengcfg_dynamic_src_sel(struct dpu_vscaler *vs, vs_src_sel_t src); +void vscaler_pixengcfg_clken(struct dpu_vscaler *vs, pixengcfg_clken_t clken); +void vscaler_shden(struct dpu_vscaler *vs, bool enable); +void vscaler_setup1(struct dpu_vscaler *vs, u32 src, u32 dst, bool deinterlace); +void vscaler_setup2(struct dpu_vscaler *vs, bool deinterlace); +void vscaler_setup3(struct dpu_vscaler *vs, bool deinterlace); +void vscaler_setup4(struct dpu_vscaler *vs, u32 phase_offset); +void vscaler_setup5(struct dpu_vscaler *vs, u32 phase_offset); +void vscaler_output_size(struct dpu_vscaler *vs, u32 line_num); +void vscaler_field_mode(struct dpu_vscaler *vs, scaler_field_mode_t m); +void vscaler_filter_mode(struct dpu_vscaler *vs, scaler_filter_mode_t m); +void vscaler_scale_mode(struct dpu_vscaler *vs, scaler_scale_mode_t m); +void vscaler_mode(struct dpu_vscaler *vs, scaler_mode_t m); +bool vscaler_is_enabled(struct dpu_vscaler *vs); +dpu_block_id_t vscaler_get_block_id(struct dpu_vscaler *vs); +unsigned int vscaler_get_stream_id(struct dpu_vscaler *vs); +void vscaler_set_stream_id(struct dpu_vscaler *vs, unsigned int id); +struct dpu_vscaler *dpu_vs_get(struct dpu_soc *dpu, int id); +void dpu_vs_put(struct dpu_vscaler *vs); + +struct dpu_fetchunit *fetchdecode_get_fetcheco(struct dpu_fetchunit *fu); +struct dpu_hscaler *fetchdecode_get_hscaler(struct dpu_fetchunit *fu); +struct dpu_vscaler *fetchdecode_get_vscaler(struct dpu_fetchunit *fu); + +bool dpu_has_pc(struct dpu_soc *dpu); +unsigned int dpu_get_syncmode_min_prate(struct dpu_soc *dpu); +unsigned int dpu_get_singlemode_max_width(struct dpu_soc *dpu); +unsigned int dpu_get_master_stream_id(struct dpu_soc *dpu); + +bool dpu_vproc_has_fetcheco_cap(u32 cap_mask); +bool dpu_vproc_has_hscale_cap(u32 cap_mask); +bool dpu_vproc_has_vscale_cap(u32 cap_mask); + +u32 dpu_vproc_get_fetcheco_cap(u32 cap_mask); +u32 dpu_vproc_get_hscale_cap(u32 cap_mask); +u32 dpu_vproc_get_vscale_cap(u32 cap_mask); + +void fetchunit_get_dprc(struct dpu_fetchunit *fu, void *data); +void fetchunit_shden(struct dpu_fetchunit *fu, bool enable); +void fetchunit_baddr_autoupdate(struct dpu_fetchunit *fu, u8 layer_mask); +void fetchunit_shdldreq_sticky(struct dpu_fetchunit *fu, u8 layer_mask); +void fetchunit_set_burstlength(struct dpu_fetchunit *fu, + unsigned int x_offset, unsigned int mt_w, + int bpp, dma_addr_t baddr, bool use_prefetch); +void fetchunit_set_baseaddress(struct dpu_fetchunit *fu, unsigned int width, + unsigned int x_offset, unsigned int y_offset, + unsigned int mt_w, unsigned int mt_h, + int bpp, dma_addr_t baddr); +void fetchunit_set_src_bpp(struct dpu_fetchunit *fu, int bpp); +void fetchunit_set_src_stride(struct dpu_fetchunit *fu, + unsigned int width, unsigned int x_offset, + unsigned int mt_w, int bpp, unsigned int stride, + dma_addr_t baddr, bool use_prefetch); +void fetchunit_set_pixel_blend_mode(struct dpu_fetchunit *fu, + unsigned int pixel_blend_mode, u16 alpha, + u32 fb_format); +void fetchunit_enable_src_buf(struct dpu_fetchunit *fu); +void fetchunit_disable_src_buf(struct dpu_fetchunit *fu); +bool fetchunit_is_enabled(struct dpu_fetchunit *fu); +unsigned int fetchunit_get_stream_id(struct dpu_fetchunit *fu); +void fetchunit_set_stream_id(struct dpu_fetchunit *fu, unsigned int id); +bool fetchunit_is_fetchdecode(struct dpu_fetchunit *fu); +bool fetchunit_is_fetcheco(struct dpu_fetchunit *fu); +bool fetchunit_is_fetchlayer(struct dpu_fetchunit *fu); +bool fetchunit_is_fetchwarp(struct dpu_fetchunit *fu); + +/* dpu blit engine */ +struct dpu_bliteng; +int dpu_bliteng_init(struct dpu_bliteng *dpu_bliteng); +void dpu_bliteng_fini(struct dpu_bliteng *dpu_bliteng); +int dpu_be_get(struct dpu_bliteng *dpu_be); +void dpu_be_put(struct dpu_bliteng *dpu_be); +void dpu_be_wait(struct dpu_bliteng *dpu_be); +int dpu_be_blit(struct dpu_bliteng *dpu_be, u32 *cmdlist, + u32 cmdnum); +int dpu_bliteng_get_empty_instance(struct dpu_bliteng **dpu_be, + struct device *dev); +u32 *dpu_bliteng_get_cmd_list(struct dpu_bliteng *dpu_be); +s32 dpu_bliteng_get_id(struct dpu_bliteng *dpu_be); +void dpu_bliteng_set_id(struct dpu_bliteng *dpu_be, int id); +void dpu_bliteng_set_dev(struct dpu_bliteng *dpu_be, struct device *dev); + +void dpu_be_configure_prefetch(struct dpu_bliteng *dpu_be, + u32 width, u32 height, + u32 x_offset, u32 y_offset, + u32 stride, u32 format, u64 modifier, + u64 baddr, u64 uv_addr); + +/* + * to avoid on-the-fly/hot plane resource migration + * between two display interfaces + */ +#define DPU_PLANE_SRC_TO_DISP_STREAM0 BIT(0) +#define DPU_PLANE_SRC_TO_DISP_STREAM1 BIT(1) +#define DPU_PLANE_SRC_DISABLED 0 + +#define MAX_FD_NUM 4 +#define MAX_FL_NUM 2 +#define MAX_FW_NUM 1 +#define MAX_LB_NUM 7 +struct dpu_plane_res { + struct dpu_extdst *ed[2]; + struct dpu_fetchunit *fd[MAX_FD_NUM]; + struct dpu_fetchunit *fe[2]; + struct dpu_fetchunit *fl[MAX_FL_NUM]; + struct dpu_fetchunit *fw[MAX_FW_NUM]; + struct dpu_framegen *fg[2]; + struct dpu_hscaler *hs[2]; + struct dpu_layerblend *lb[MAX_LB_NUM]; + struct dpu_vscaler *vs[2]; +}; + +/* + * Each DPU plane can be a primary plane or an overlay plane + * of one of the DPU's two CRTCs. + */ +struct dpu_plane_grp { + struct dpu_plane_res res; + unsigned int hw_plane_num; + unsigned int hw_plane_fetcheco_num; + unsigned int hw_plane_hscaler_num; + unsigned int hw_plane_vscaler_num; + unsigned int id; + bool has_vproc; + /* + * used when assigning plane source + * index: 0 1 2 3 4 5 6 + * source: fl0(sub0) fl1(sub0) fw2(sub0) fd0 fd1 fd2 fd3 + */ + struct mutex mutex; + u32 src_a_mask; + u32 src_na_mask; + u32 src_use_vproc_mask; +}; + +static inline struct dpu_plane_grp *plane_res_to_grp(struct dpu_plane_res *res) +{ + return container_of(res, struct dpu_plane_grp, res); +} + +struct dpu_client_platformdata { + const unsigned int stream_id; + unsigned int di_grp_id; + struct dpu_plane_grp *plane_grp; + + /* Store9 could be shared bewteen display engine and blit engine */ + struct dpu_store *st9; + + struct device_node *of_node; +}; +#endif /* __DRM_DPU_H__ */ diff --git a/include/video/imx-dcss.h b/include/video/imx-dcss.h new file mode 100644 index 000000000000..20b6daedd044 --- /dev/null +++ b/include/video/imx-dcss.h @@ -0,0 +1,190 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __IMX_DCSS_H__ +#define __IMX_DCSS_H__ + +#include <linux/types.h> +#include <video/videomode.h> +#include <drm/drm_rect.h> + +struct dcss_soc; + +struct dcss_client_platformdata { + struct device_node *of_node; +}; + +/* COMMON */ +int dcss_vblank_irq_get(struct dcss_soc *dcss); +void dcss_vblank_irq_enable(struct dcss_soc *dcss, bool en); +void dcss_vblank_irq_clear(struct dcss_soc *dcss); +enum dcss_color_space dcss_drm_fourcc_to_colorspace(u32 drm_fourcc); +void dcss_trace_write(u64 tag); + + +#define TAG(x) ((x) << 56) + +#define TRACE_COMMON TAG(0LL) +#define TRACE_DTG TAG(1LL) +#define TRACE_SS TAG(2LL) +#define TRACE_DPR TAG(3LL) +#define TRACE_SCALER TAG(4LL) +#define TRACE_CTXLD TAG(5LL) +#define TRACE_DEC400D TAG(6LL) +#define TRACE_DTRC TAG(7LL) +#define TRACE_HDR10 TAG(8LL) +#define TRACE_RDSRC TAG(9LL) +#define TRACE_WRSCL TAG(10LL) + +#define TRACE_DRM_CRTC TAG(11LL) +#define TRACE_DRM_PLANE TAG(12LL) +#define TRACE_DRM_KMS TAG(13LL) + +#define dcss_trace_module(mod_tag, val) dcss_trace_write((mod_tag) | (val)); + +/* BLKCTL */ +void dcss_blkctl_hdmi_secure_src_en(struct dcss_soc *dcss); + +/* DPR */ +enum dcss_tile_type { + TILE_LINEAR = 0, + TILE_GPU_STANDARD, + TILE_GPU_SUPER, + TILE_VPU_YUV420, + TILE_VPU_VP9, +}; + +enum dcss_pix_size { + PIX_SIZE_8, + PIX_SIZE_16, + PIX_SIZE_32, +}; + +void dcss_dpr_set_res(struct dcss_soc *dcss, int ch_num, u32 xres, u32 yres, + u32 adj_w, u32 adj_h); +void dcss_dpr_addr_set(struct dcss_soc *dcss, int ch_num, u32 luma_base_addr, + u32 chroma_base_addr, u16 pitch); +void dcss_dpr_enable(struct dcss_soc *dcss, int ch_num, bool en); +void dcss_dpr_format_set(struct dcss_soc *dcss, int ch_num, u32 pix_format, + bool modifiers_present); +void dcss_dpr_tile_derive(struct dcss_soc *dcss, + int ch_num, + uint64_t modifier); +void dcss_dpr_set_rotation(struct dcss_soc *dcss, int ch_num, u32 rotation); + +/* DTG */ +int dcss_dtg_mode_valid(struct dcss_soc *dcss, int clock, int crtc_clock); +int dcss_dtg_mode_fixup(struct dcss_soc *dcss, int clock); +void dcss_dtg_sync_set(struct dcss_soc *dcss, struct videomode *vm); +void dcss_dtg_plane_pos_set(struct dcss_soc *dcss, int ch_num, + int px, int py, int pw, int ph); +void dcss_dtg_enable(struct dcss_soc *dcss, bool en, + struct completion *dis_completion); +bool dcss_dtg_is_enabled(struct dcss_soc *dcss); +void dcss_dtg_ch_enable(struct dcss_soc *dcss, int ch_num, bool en); +void dcss_dtg_plane_alpha_set(struct dcss_soc *dcss, int ch_num, + u32 pix_format, int alpha, bool use_global_alpha); +bool dcss_dtg_global_alpha_changed(struct dcss_soc *dcss, int ch_num, + u32 pix_format, int alpha, + int use_global_alpha); +void dcss_dtg_css_set(struct dcss_soc *dcss, u32 pix_format); +void dcss_dtg_ctxld_kick_irq_enable(struct dcss_soc *dcss, bool en); +bool dcss_dtg_vblank_irq_valid(struct dcss_soc *dcss); + +/* SUBSAM */ +void dcss_ss_sync_set(struct dcss_soc *dcss, struct videomode *vm, + bool phsync, bool pvsync); +void dcss_ss_subsam_set(struct dcss_soc *dcss, u32 pix_format); +void dcss_ss_enable(struct dcss_soc *dcss, bool en); + +/* SCALER */ +void dcss_scaler_enable(struct dcss_soc *dcss, int ch_num, bool en); +void dcss_scaler_setup(struct dcss_soc *dcss, int ch_num, u32 pix_format, + int src_xres, int src_yres, int dst_xres, int dst_yres, + u32 vrefresh_hz); +bool dcss_scaler_can_scale(struct dcss_soc *dcss, int ch_num, + int src_xres, int src_yres, + int dst_xres, int dst_yres); + +/* CTXLD */ +int dcss_ctxld_enable(struct dcss_soc *dcss); +bool dcss_ctxld_is_flushed(struct dcss_soc *dcss); + +/* HDR10 */ +enum dcss_hdr10_nonlinearity { + NL_REC2084, + NL_REC709, + NL_BT1886, + NL_2100HLG, + NL_SRGB, +}; + +enum dcss_hdr10_pixel_range { + PR_LIMITED, + PR_FULL, +}; + +enum dcss_hdr10_gamut { + G_REC2020, + G_REC709, + G_REC601_NTSC, + G_REC601_PAL, + G_ADOBE_ARGB, +}; + +struct dcss_hdr10_pipe_cfg { + u32 pixel_format; + enum dcss_hdr10_nonlinearity nl; + enum dcss_hdr10_pixel_range pr; + enum dcss_hdr10_gamut g; +}; + +void dcss_hdr10_setup(struct dcss_soc *dcss, int ch_num, + struct dcss_hdr10_pipe_cfg *ipipe_cfg, + struct dcss_hdr10_pipe_cfg *opipe_cfg); + +/* DTRC */ +void dcss_dtrc_bypass(struct dcss_soc *dcss, int ch_num); +void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src, + struct drm_rect *old_src, u32 pixel_format); +void dcss_dtrc_addr_set(struct dcss_soc *dcss, int ch_num, u32 p1_ba, u32 p2_ba, + uint64_t dec_table_ofs); +void dcss_dtrc_enable(struct dcss_soc *dcss, int ch_num, bool enable); +void dcss_dtrc_set_format_mod(struct dcss_soc *dcss, int ch_num, u64 modifier); + +enum dcss_color_space { + DCSS_COLORSPACE_RGB, + DCSS_COLORSPACE_YUV, + DCSS_COLORSPACE_UNKNOWN, +}; + +/* DEC400D */ +void dcss_dec400d_set_format_mod(struct dcss_soc *dcss, + uint32_t fourcc, + uint32_t mod_idx, + uint64_t modifier); +void dcss_dec400d_bypass(struct dcss_soc *dcss); +void dcss_dec400d_shadow_trig(struct dcss_soc *dcss); +void dcss_dec400d_addr_set(struct dcss_soc *dcss, + uint32_t baddr, + uint32_t caddr); +void dcss_dec400d_read_config(struct dcss_soc *dcss, + uint32_t read_id, + bool compress_en, + uint32_t compress_format); +void dcss_dec400d_fast_clear_config(struct dcss_soc *dcss, + uint32_t fc_value, + bool enable); +void dcss_dec400d_enable(struct dcss_soc *dcss); +#endif /* __IMX_DCSS_H__ */ diff --git a/include/video/imx-lcdif.h b/include/video/imx-lcdif.h new file mode 100644 index 000000000000..96b124852dd1 --- /dev/null +++ b/include/video/imx-lcdif.h @@ -0,0 +1,42 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __IMX_LCDIF_H__ +#define __IMX_LCDIF_H__ + +struct lcdif_soc; +struct videomode; + +struct lcdif_client_platformdata { + struct device_node *of_node; +}; + +int lcdif_vblank_irq_get(struct lcdif_soc *lcdif); +void lcdif_vblank_irq_enable(struct lcdif_soc *lcdif); +void lcdif_vblank_irq_disable(struct lcdif_soc *lcdif); +void lcdif_vblank_irq_clear(struct lcdif_soc *lcdif); + +int lcdif_get_bus_fmt_from_pix_fmt(struct lcdif_soc *lcdif, + uint32_t format); +int lcdif_set_pix_fmt(struct lcdif_soc *lcdif, u32 format); +void lcdif_set_bus_fmt(struct lcdif_soc *lcdif, u32 bus_format); +void lcdif_set_fb_addr(struct lcdif_soc *lcdif, int id, u32 addr); +void lcdif_set_mode(struct lcdif_soc *lcdif, struct videomode *vmode); +void lcdif_set_fb_hcrop(struct lcdif_soc *lcdif, u32 src_w, + u32 fb_w, bool crop); +void lcdif_enable_controller(struct lcdif_soc *lcdif); +void lcdif_disable_controller(struct lcdif_soc *lcdif); +void lcdif_dump_registers(struct lcdif_soc *lcdif); + +#endif diff --git a/include/video/imx8-pc.h b/include/video/imx8-pc.h new file mode 100644 index 000000000000..ab81d56a5f5f --- /dev/null +++ b/include/video/imx8-pc.h @@ -0,0 +1,33 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef _IMX8_PIXEL_COMBINER_H_ +#define _IMX8_PIXEL_COMBINER_H_ + +enum { + PC_BYPASS, + PC_COMBINE, + PC_CONVERSION, + PC_SPLIT_RGB, +}; + +struct pc; + +void pc_enable(struct pc *pc); +void pc_disable(struct pc *pc); +void pc_configure(struct pc *pc, unsigned int di, unsigned int frame_width, + u32 mode, u32 format); +struct pc *pc_lookup_by_phandle(struct device *dev, const char *name); + +#endif diff --git a/include/video/imx8-prefetch.h b/include/video/imx8-prefetch.h new file mode 100644 index 000000000000..0ca6f85c700f --- /dev/null +++ b/include/video/imx8-prefetch.h @@ -0,0 +1,79 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef _IMX8_PREFETCH_H_ +#define _IMX8_PREFETCH_H_ + +#define PRG_HANDSHAKE_8LINES 8 +#define PRG_HANDSHAKE_4LINES 4 +#define AMPHION_STRIPE_WIDTH 8 +#define AMPHION_STRIPE_HEIGHT 128 +#define AMPHION_UV_STRIPE_HEIGHT AMPHION_STRIPE_HEIGHT +#define AMPHION_Y_STRIPE_HEIGHT (2 * AMPHION_STRIPE_HEIGHT) +#define VIVANTE_TILE_WIDTH 4 +#define VIVANTE_TILE_HEIGHT 4 +#define VIVANTE_SUPER_TILE_WIDTH 64 +#define VIVANTE_SUPER_TILE_HEIGHT 64 + +struct prg; +struct prg * +prg_lookup_by_phandle(struct device *dev, const char *name, int index); +void prg_enable(struct prg *prg); +void prg_disable(struct prg *prg, bool hard); +void prg_configure(struct prg *prg, unsigned int width, unsigned int height, + unsigned int x_offset, unsigned int y_offset, + unsigned int stride, unsigned int bits_per_pixel, + unsigned long baddr, u32 format, u64 modifier, + bool start); +void prg_reg_update(struct prg *prg); +void prg_shadow_enable(struct prg *prg); +void prg_shadow_disable(struct prg *prg); +bool prg_stride_supported(struct prg *prg, unsigned int stride); +bool prg_stride_double_check(struct prg *prg, + unsigned int width, unsigned int x_offset, + unsigned int bits_per_pixel, u64 modifier, + unsigned int stride, dma_addr_t baddr); +void prg_set_auxiliary(struct prg *prg); +void prg_set_primary(struct prg *prg); +void prg_set_blit(struct prg *prg); + +struct dprc; +struct dprc * +dprc_lookup_by_phandle(struct device *dev, const char *name, int index); +void dprc_enable(struct dprc *dprc); +void dprc_disable(struct dprc *dprc, bool hard); +void dprc_configure(struct dprc *dprc, unsigned int stream_id, + unsigned int width, unsigned int height, + unsigned int x_offset, unsigned int y_offset, + unsigned int stride, u32 format, u64 modifier, + unsigned long baddr, unsigned long uv_baddr, + bool start, bool aux_start, bool interlace_frame); +void dprc_disable_repeat_en(struct dprc *dprc); +bool dprc_is_repeat_en(struct dprc *dprc); +void dprc_gasket_shadow_enable(struct dprc *dprc); +void dprc_gasket_shadow_disable(struct dprc *dprc); +void dprc_reg_update(struct dprc *dprc); +void dprc_first_frame_handle(struct dprc *dprc); +void dprc_irq_handle(struct dprc *dprc); +void dprc_enable_ctrl_done_irq(struct dprc *dprc); +bool dprc_format_supported(struct dprc *dprc, u32 format, u64 modifier); +bool dprc_stride_supported(struct dprc *dprc, + unsigned int stride, unsigned int uv_stride, + unsigned int width, u32 format); +bool dprc_stride_double_check(struct dprc *dprc, + unsigned int width, unsigned int x_offset, + u32 format, u64 modifier, + dma_addr_t baddr, dma_addr_t uv_baddr); + +#endif diff --git a/include/video/mxc_edid.h b/include/video/mxc_edid.h new file mode 100644 index 000000000000..ff7ddd92a3bc --- /dev/null +++ b/include/video/mxc_edid.h @@ -0,0 +1,107 @@ +/* + * Copyright 2009-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxc_edid.h + * + * @brief MXC EDID tools + * + * @ingroup Framebuffer + */ + +#ifndef MXC_EDID_H +#define MXC_EDID_H + +#include <linux/fb.h> + +#define FB_VMODE_ASPECT_4_3 0x10 +#define FB_VMODE_ASPECT_16_9 0x20 +#define FB_VMODE_ASPECT_MASK (FB_VMODE_ASPECT_4_3 | FB_VMODE_ASPECT_16_9) + +enum cea_audio_coding_types { + AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0, + AUDIO_CODING_TYPE_LPCM = 1, + AUDIO_CODING_TYPE_AC3 = 2, + AUDIO_CODING_TYPE_MPEG1 = 3, + AUDIO_CODING_TYPE_MP3 = 4, + AUDIO_CODING_TYPE_MPEG2 = 5, + AUDIO_CODING_TYPE_AACLC = 6, + AUDIO_CODING_TYPE_DTS = 7, + AUDIO_CODING_TYPE_ATRAC = 8, + AUDIO_CODING_TYPE_SACD = 9, + AUDIO_CODING_TYPE_EAC3 = 10, + AUDIO_CODING_TYPE_DTS_HD = 11, + AUDIO_CODING_TYPE_MLP = 12, + AUDIO_CODING_TYPE_DST = 13, + AUDIO_CODING_TYPE_WMAPRO = 14, + AUDIO_CODING_TYPE_RESERVED = 15, +}; + +struct mxc_hdmi_3d_format { + unsigned char vic_order_2d; + unsigned char struct_3d; + unsigned char detail_3d; + unsigned char reserved; +}; + +struct mxc_edid_cfg { + bool cea_underscan; + bool cea_basicaudio; + bool cea_ycbcr444; + bool cea_ycbcr422; + bool hdmi_cap; + + /*VSD*/ + bool vsd_support_ai; + bool vsd_dc_48bit; + bool vsd_dc_36bit; + bool vsd_dc_30bit; + bool vsd_dc_y444; + bool vsd_dvi_dual; + + bool vsd_cnc0; + bool vsd_cnc1; + bool vsd_cnc2; + bool vsd_cnc3; + + u8 vsd_video_latency; + u8 vsd_audio_latency; + u8 vsd_I_video_latency; + u8 vsd_I_audio_latency; + + u8 physical_address[4]; + u8 hdmi_vic[64]; + struct mxc_hdmi_3d_format hdmi_3d_format[64]; + u16 hdmi_3d_mask_all; + u16 hdmi_3d_struct_all; + u32 vsd_max_tmdsclk_rate; + + u8 max_channels; + u8 sample_sizes; + u8 sample_rates; + u8 speaker_alloc; +}; + +extern const struct fb_videomode mxc_cea_mode[64]; + +int mxc_edid_var_to_vic(struct fb_var_screeninfo *var); +int mxc_edid_mode_to_vic(const struct fb_videomode *mode); +int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr, + unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi); +int mxc_edid_parse_ext_blk(unsigned char *edid, struct mxc_edid_cfg *cfg, + struct fb_monspecs *specs); +#endif diff --git a/include/video/mxc_hdmi.h b/include/video/mxc_hdmi.h new file mode 100644 index 000000000000..79eb3024f65c --- /dev/null +++ b/include/video/mxc_hdmi.h @@ -0,0 +1,1015 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_HDMI_H__ +#define __MXC_HDMI_H__ + +/* + * Hdmi controller registers + */ + +/* Identification Registers */ +#define HDMI_DESIGN_ID 0x0000 +#define HDMI_REVISION_ID 0x0001 +#define HDMI_PRODUCT_ID0 0x0002 +#define HDMI_PRODUCT_ID1 0x0003 +#define HDMI_CONFIG0_ID 0x0004 +#define HDMI_CONFIG1_ID 0x0005 +#define HDMI_CONFIG2_ID 0x0006 +#define HDMI_CONFIG3_ID 0x0007 + +/* Interrupt Registers */ +#define HDMI_IH_FC_STAT0 0x0100 +#define HDMI_IH_FC_STAT1 0x0101 +#define HDMI_IH_FC_STAT2 0x0102 +#define HDMI_IH_AS_STAT0 0x0103 +#define HDMI_IH_PHY_STAT0 0x0104 +#define HDMI_IH_I2CM_STAT0 0x0105 +#define HDMI_IH_CEC_STAT0 0x0106 +#define HDMI_IH_VP_STAT0 0x0107 +#define HDMI_IH_I2CMPHY_STAT0 0x0108 +#define HDMI_IH_AHBDMAAUD_STAT0 0x0109 + +#define HDMI_IH_MUTE_FC_STAT0 0x0180 +#define HDMI_IH_MUTE_FC_STAT1 0x0181 +#define HDMI_IH_MUTE_FC_STAT2 0x0182 +#define HDMI_IH_MUTE_AS_STAT0 0x0183 +#define HDMI_IH_MUTE_PHY_STAT0 0x0184 +#define HDMI_IH_MUTE_I2CM_STAT0 0x0185 +#define HDMI_IH_MUTE_CEC_STAT0 0x0186 +#define HDMI_IH_MUTE_VP_STAT0 0x0187 +#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 +#define HDMI_IH_MUTE 0x01FF + +/* Video Sample Registers */ +#define HDMI_TX_INVID0 0x0200 +#define HDMI_TX_INSTUFFING 0x0201 +#define HDMI_TX_GYDATA0 0x0202 +#define HDMI_TX_GYDATA1 0x0203 +#define HDMI_TX_RCRDATA0 0x0204 +#define HDMI_TX_RCRDATA1 0x0205 +#define HDMI_TX_BCBDATA0 0x0206 +#define HDMI_TX_BCBDATA1 0x0207 + +/* Video Packetizer Registers */ +#define HDMI_VP_STATUS 0x0800 +#define HDMI_VP_PR_CD 0x0801 +#define HDMI_VP_STUFF 0x0802 +#define HDMI_VP_REMAP 0x0803 +#define HDMI_VP_CONF 0x0804 +#define HDMI_VP_STAT 0x0805 +#define HDMI_VP_INT 0x0806 +#define HDMI_VP_MASK 0x0807 +#define HDMI_VP_POL 0x0808 + +/* Frame Composer Registers */ +#define HDMI_FC_INVIDCONF 0x1000 +#define HDMI_FC_INHACTV0 0x1001 +#define HDMI_FC_INHACTV1 0x1002 +#define HDMI_FC_INHBLANK0 0x1003 +#define HDMI_FC_INHBLANK1 0x1004 +#define HDMI_FC_INVACTV0 0x1005 +#define HDMI_FC_INVACTV1 0x1006 +#define HDMI_FC_INVBLANK 0x1007 +#define HDMI_FC_HSYNCINDELAY0 0x1008 +#define HDMI_FC_HSYNCINDELAY1 0x1009 +#define HDMI_FC_HSYNCINWIDTH0 0x100A +#define HDMI_FC_HSYNCINWIDTH1 0x100B +#define HDMI_FC_VSYNCINDELAY 0x100C +#define HDMI_FC_VSYNCINWIDTH 0x100D +#define HDMI_FC_INFREQ0 0x100E +#define HDMI_FC_INFREQ1 0x100F +#define HDMI_FC_INFREQ2 0x1010 +#define HDMI_FC_CTRLDUR 0x1011 +#define HDMI_FC_EXCTRLDUR 0x1012 +#define HDMI_FC_EXCTRLSPAC 0x1013 +#define HDMI_FC_CH0PREAM 0x1014 +#define HDMI_FC_CH1PREAM 0x1015 +#define HDMI_FC_CH2PREAM 0x1016 +#define HDMI_FC_AVICONF3 0x1017 +#define HDMI_FC_GCP 0x1018 +#define HDMI_FC_AVICONF0 0x1019 +#define HDMI_FC_AVICONF1 0x101A +#define HDMI_FC_AVICONF2 0x101B +#define HDMI_FC_AVIVID 0x101C +#define HDMI_FC_AVIETB0 0x101D +#define HDMI_FC_AVIETB1 0x101E +#define HDMI_FC_AVISBB0 0x101F +#define HDMI_FC_AVISBB1 0x1020 +#define HDMI_FC_AVIELB0 0x1021 +#define HDMI_FC_AVIELB1 0x1022 +#define HDMI_FC_AVISRB0 0x1023 +#define HDMI_FC_AVISRB1 0x1024 +#define HDMI_FC_AUDICONF0 0x1025 +#define HDMI_FC_AUDICONF1 0x1026 +#define HDMI_FC_AUDICONF2 0x1027 +#define HDMI_FC_AUDICONF3 0x1028 +#define HDMI_FC_VSDIEEEID0 0x1029 +#define HDMI_FC_VSDSIZE 0x102A +#define HDMI_FC_VSDIEEEID1 0x1030 +#define HDMI_FC_VSDIEEEID2 0x1031 +#define HDMI_FC_VSDPAYLOAD0 0x1032 +#define HDMI_FC_VSDPAYLOAD1 0x1033 +#define HDMI_FC_VSDPAYLOAD2 0x1034 +#define HDMI_FC_VSDPAYLOAD3 0x1035 +#define HDMI_FC_VSDPAYLOAD4 0x1036 +#define HDMI_FC_VSDPAYLOAD5 0x1037 +#define HDMI_FC_VSDPAYLOAD6 0x1038 +#define HDMI_FC_VSDPAYLOAD7 0x1039 +#define HDMI_FC_VSDPAYLOAD8 0x103A +#define HDMI_FC_VSDPAYLOAD9 0x103B +#define HDMI_FC_VSDPAYLOAD10 0x103C +#define HDMI_FC_VSDPAYLOAD11 0x103D +#define HDMI_FC_VSDPAYLOAD12 0x103E +#define HDMI_FC_VSDPAYLOAD13 0x103F +#define HDMI_FC_VSDPAYLOAD14 0x1040 +#define HDMI_FC_VSDPAYLOAD15 0x1041 +#define HDMI_FC_VSDPAYLOAD16 0x1042 +#define HDMI_FC_VSDPAYLOAD17 0x1043 +#define HDMI_FC_VSDPAYLOAD18 0x1044 +#define HDMI_FC_VSDPAYLOAD19 0x1045 +#define HDMI_FC_VSDPAYLOAD20 0x1046 +#define HDMI_FC_VSDPAYLOAD21 0x1047 +#define HDMI_FC_VSDPAYLOAD22 0x1048 +#define HDMI_FC_VSDPAYLOAD23 0x1049 +#define HDMI_FC_SPDVENDORNAME0 0x104A +#define HDMI_FC_SPDVENDORNAME1 0x104B +#define HDMI_FC_SPDVENDORNAME2 0x104C +#define HDMI_FC_SPDVENDORNAME3 0x104D +#define HDMI_FC_SPDVENDORNAME4 0x104E +#define HDMI_FC_SPDVENDORNAME5 0x104F +#define HDMI_FC_SPDVENDORNAME6 0x1050 +#define HDMI_FC_SPDVENDORNAME7 0x1051 +#define HDMI_FC_SDPPRODUCTNAME0 0x1052 +#define HDMI_FC_SDPPRODUCTNAME1 0x1053 +#define HDMI_FC_SDPPRODUCTNAME2 0x1054 +#define HDMI_FC_SDPPRODUCTNAME3 0x1055 +#define HDMI_FC_SDPPRODUCTNAME4 0x1056 +#define HDMI_FC_SDPPRODUCTNAME5 0x1057 +#define HDMI_FC_SDPPRODUCTNAME6 0x1058 +#define HDMI_FC_SDPPRODUCTNAME7 0x1059 +#define HDMI_FC_SDPPRODUCTNAME8 0x105A +#define HDMI_FC_SDPPRODUCTNAME9 0x105B +#define HDMI_FC_SDPPRODUCTNAME10 0x105C +#define HDMI_FC_SDPPRODUCTNAME11 0x105D +#define HDMI_FC_SDPPRODUCTNAME12 0x105E +#define HDMI_FC_SDPPRODUCTNAME13 0x105F +#define HDMI_FC_SDPPRODUCTNAME14 0x1060 +#define HDMI_FC_SPDPRODUCTNAME15 0x1061 +#define HDMI_FC_SPDDEVICEINF 0x1062 +#define HDMI_FC_AUDSCONF 0x1063 +#define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_DATACH0FILL 0x1070 +#define HDMI_FC_DATACH1FILL 0x1071 +#define HDMI_FC_DATACH2FILL 0x1072 +#define HDMI_FC_CTRLQHIGH 0x1073 +#define HDMI_FC_CTRLQLOW 0x1074 +#define HDMI_FC_ACP0 0x1075 +#define HDMI_FC_ACP28 0x1076 +#define HDMI_FC_ACP27 0x1077 +#define HDMI_FC_ACP26 0x1078 +#define HDMI_FC_ACP25 0x1079 +#define HDMI_FC_ACP24 0x107A +#define HDMI_FC_ACP23 0x107B +#define HDMI_FC_ACP22 0x107C +#define HDMI_FC_ACP21 0x107D +#define HDMI_FC_ACP20 0x107E +#define HDMI_FC_ACP19 0x107F +#define HDMI_FC_ACP18 0x1080 +#define HDMI_FC_ACP17 0x1081 +#define HDMI_FC_ACP16 0x1082 +#define HDMI_FC_ACP15 0x1083 +#define HDMI_FC_ACP14 0x1084 +#define HDMI_FC_ACP13 0x1085 +#define HDMI_FC_ACP12 0x1086 +#define HDMI_FC_ACP11 0x1087 +#define HDMI_FC_ACP10 0x1088 +#define HDMI_FC_ACP9 0x1089 +#define HDMI_FC_ACP8 0x108A +#define HDMI_FC_ACP7 0x108B +#define HDMI_FC_ACP6 0x108C +#define HDMI_FC_ACP5 0x108D +#define HDMI_FC_ACP4 0x108E +#define HDMI_FC_ACP3 0x108F +#define HDMI_FC_ACP2 0x1090 +#define HDMI_FC_ACP1 0x1091 +#define HDMI_FC_ISCR1_0 0x1092 +#define HDMI_FC_ISCR1_16 0x1093 +#define HDMI_FC_ISCR1_15 0x1094 +#define HDMI_FC_ISCR1_14 0x1095 +#define HDMI_FC_ISCR1_13 0x1096 +#define HDMI_FC_ISCR1_12 0x1097 +#define HDMI_FC_ISCR1_11 0x1098 +#define HDMI_FC_ISCR1_10 0x1099 +#define HDMI_FC_ISCR1_9 0x109A +#define HDMI_FC_ISCR1_8 0x109B +#define HDMI_FC_ISCR1_7 0x109C +#define HDMI_FC_ISCR1_6 0x109D +#define HDMI_FC_ISCR1_5 0x109E +#define HDMI_FC_ISCR1_4 0x109F +#define HDMI_FC_ISCR1_3 0x10A0 +#define HDMI_FC_ISCR1_2 0x10A1 +#define HDMI_FC_ISCR1_1 0x10A2 +#define HDMI_FC_ISCR2_15 0x10A3 +#define HDMI_FC_ISCR2_14 0x10A4 +#define HDMI_FC_ISCR2_13 0x10A5 +#define HDMI_FC_ISCR2_12 0x10A6 +#define HDMI_FC_ISCR2_11 0x10A7 +#define HDMI_FC_ISCR2_10 0x10A8 +#define HDMI_FC_ISCR2_9 0x10A9 +#define HDMI_FC_ISCR2_8 0x10AA +#define HDMI_FC_ISCR2_7 0x10AB +#define HDMI_FC_ISCR2_6 0x10AC +#define HDMI_FC_ISCR2_5 0x10AD +#define HDMI_FC_ISCR2_4 0x10AE +#define HDMI_FC_ISCR2_3 0x10AF +#define HDMI_FC_ISCR2_2 0x10B0 +#define HDMI_FC_ISCR2_1 0x10B1 +#define HDMI_FC_ISCR2_0 0x10B2 +#define HDMI_FC_DATAUTO0 0x10B3 +#define HDMI_FC_DATAUTO1 0x10B4 +#define HDMI_FC_DATAUTO2 0x10B5 +#define HDMI_FC_DATMAN 0x10B6 +#define HDMI_FC_DATAUTO3 0x10B7 +#define HDMI_FC_RDRB0 0x10B8 +#define HDMI_FC_RDRB1 0x10B9 +#define HDMI_FC_RDRB2 0x10BA +#define HDMI_FC_RDRB3 0x10BB +#define HDMI_FC_RDRB4 0x10BC +#define HDMI_FC_RDRB5 0x10BD +#define HDMI_FC_RDRB6 0x10BE +#define HDMI_FC_RDRB7 0x10BF +#define HDMI_FC_STAT0 0x10D0 +#define HDMI_FC_INT0 0x10D1 +#define HDMI_FC_MASK0 0x10D2 +#define HDMI_FC_POL0 0x10D3 +#define HDMI_FC_STAT1 0x10D4 +#define HDMI_FC_INT1 0x10D5 +#define HDMI_FC_MASK1 0x10D6 +#define HDMI_FC_POL1 0x10D7 +#define HDMI_FC_STAT2 0x10D8 +#define HDMI_FC_INT2 0x10D9 +#define HDMI_FC_MASK2 0x10DA +#define HDMI_FC_POL2 0x10DB +#define HDMI_FC_PRCONF 0x10E0 + +#define HDMI_FC_GMD_STAT 0x1100 +#define HDMI_FC_GMD_EN 0x1101 +#define HDMI_FC_GMD_UP 0x1102 +#define HDMI_FC_GMD_CONF 0x1103 +#define HDMI_FC_GMD_HB 0x1104 +#define HDMI_FC_GMD_PB0 0x1105 +#define HDMI_FC_GMD_PB1 0x1106 +#define HDMI_FC_GMD_PB2 0x1107 +#define HDMI_FC_GMD_PB3 0x1108 +#define HDMI_FC_GMD_PB4 0x1109 +#define HDMI_FC_GMD_PB5 0x110A +#define HDMI_FC_GMD_PB6 0x110B +#define HDMI_FC_GMD_PB7 0x110C +#define HDMI_FC_GMD_PB8 0x110D +#define HDMI_FC_GMD_PB9 0x110E +#define HDMI_FC_GMD_PB10 0x110F +#define HDMI_FC_GMD_PB11 0x1110 +#define HDMI_FC_GMD_PB12 0x1111 +#define HDMI_FC_GMD_PB13 0x1112 +#define HDMI_FC_GMD_PB14 0x1113 +#define HDMI_FC_GMD_PB15 0x1114 +#define HDMI_FC_GMD_PB16 0x1115 +#define HDMI_FC_GMD_PB17 0x1116 +#define HDMI_FC_GMD_PB18 0x1117 +#define HDMI_FC_GMD_PB19 0x1118 +#define HDMI_FC_GMD_PB20 0x1119 +#define HDMI_FC_GMD_PB21 0x111A +#define HDMI_FC_GMD_PB22 0x111B +#define HDMI_FC_GMD_PB23 0x111C +#define HDMI_FC_GMD_PB24 0x111D +#define HDMI_FC_GMD_PB25 0x111E +#define HDMI_FC_GMD_PB26 0x111F +#define HDMI_FC_GMD_PB27 0x1120 + +#define HDMI_FC_DBGFORCE 0x1200 +#define HDMI_FC_DBGAUD0CH0 0x1201 +#define HDMI_FC_DBGAUD1CH0 0x1202 +#define HDMI_FC_DBGAUD2CH0 0x1203 +#define HDMI_FC_DBGAUD0CH1 0x1204 +#define HDMI_FC_DBGAUD1CH1 0x1205 +#define HDMI_FC_DBGAUD2CH1 0x1206 +#define HDMI_FC_DBGAUD0CH2 0x1207 +#define HDMI_FC_DBGAUD1CH2 0x1208 +#define HDMI_FC_DBGAUD2CH2 0x1209 +#define HDMI_FC_DBGAUD0CH3 0x120A +#define HDMI_FC_DBGAUD1CH3 0x120B +#define HDMI_FC_DBGAUD2CH3 0x120C +#define HDMI_FC_DBGAUD0CH4 0x120D +#define HDMI_FC_DBGAUD1CH4 0x120E +#define HDMI_FC_DBGAUD2CH4 0x120F +#define HDMI_FC_DBGAUD0CH5 0x1210 +#define HDMI_FC_DBGAUD1CH5 0x1211 +#define HDMI_FC_DBGAUD2CH5 0x1212 +#define HDMI_FC_DBGAUD0CH6 0x1213 +#define HDMI_FC_DBGAUD1CH6 0x1214 +#define HDMI_FC_DBGAUD2CH6 0x1215 +#define HDMI_FC_DBGAUD0CH7 0x1216 +#define HDMI_FC_DBGAUD1CH7 0x1217 +#define HDMI_FC_DBGAUD2CH7 0x1218 +#define HDMI_FC_DBGTMDS0 0x1219 +#define HDMI_FC_DBGTMDS1 0x121A +#define HDMI_FC_DBGTMDS2 0x121B + +/* HDMI Source PHY Registers */ +#define HDMI_PHY_CONF0 0x3000 +#define HDMI_PHY_TST0 0x3001 +#define HDMI_PHY_TST1 0x3002 +#define HDMI_PHY_TST2 0x3003 +#define HDMI_PHY_STAT0 0x3004 +#define HDMI_PHY_INT0 0x3005 +#define HDMI_PHY_MASK0 0x3006 +#define HDMI_PHY_POL0 0x3007 + +/* HDMI Master PHY Registers */ +#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 +#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 +#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 +#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 +#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 +#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 +#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 +#define HDMI_PHY_I2CM_INT_ADDR 0x3027 +#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 +#define HDMI_PHY_I2CM_DIV_ADDR 0x3029 +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 + +/* Audio Sampler Registers */ +#define HDMI_AUD_CONF0 0x3100 +#define HDMI_AUD_CONF1 0x3101 +#define HDMI_AUD_INT 0x3102 +#define HDMI_AUD_CONF2 0x3103 +#define HDMI_AUD_N1 0x3200 +#define HDMI_AUD_N2 0x3201 +#define HDMI_AUD_N3 0x3202 +#define HDMI_AUD_CTS1 0x3203 +#define HDMI_AUD_CTS2 0x3204 +#define HDMI_AUD_CTS3 0x3205 +#define HDMI_AUD_INPUTCLKFS 0x3206 +#define HDMI_AUD_SPDIFINT 0x3302 +#define HDMI_AUD_CONF0_HBR 0x3400 +#define HDMI_AUD_HBR_STATUS 0x3401 +#define HDMI_AUD_HBR_INT 0x3402 +#define HDMI_AUD_HBR_POL 0x3403 +#define HDMI_AUD_HBR_MASK 0x3404 + +/* Generic Parallel Audio Interface Registers */ +/* Not used as GPAUD interface is not enabled in hw */ +#define HDMI_GP_CONF0 0x3500 +#define HDMI_GP_CONF1 0x3501 +#define HDMI_GP_CONF2 0x3502 +#define HDMI_GP_STAT 0x3503 +#define HDMI_GP_INT 0x3504 +#define HDMI_GP_MASK 0x3505 +#define HDMI_GP_POL 0x3506 + +/* Audio DMA Registers */ +#define HDMI_AHB_DMA_CONF0 0x3600 +#define HDMI_AHB_DMA_START 0x3601 +#define HDMI_AHB_DMA_STOP 0x3602 +#define HDMI_AHB_DMA_THRSLD 0x3603 +#define HDMI_AHB_DMA_STRADDR0 0x3604 +#define HDMI_AHB_DMA_STRADDR1 0x3605 +#define HDMI_AHB_DMA_STRADDR2 0x3606 +#define HDMI_AHB_DMA_STRADDR3 0x3607 +#define HDMI_AHB_DMA_STPADDR0 0x3608 +#define HDMI_AHB_DMA_STPADDR1 0x3609 +#define HDMI_AHB_DMA_STPADDR2 0x360a +#define HDMI_AHB_DMA_STPADDR3 0x360b +#define HDMI_AHB_DMA_BSTADDR0 0x360c +#define HDMI_AHB_DMA_BSTADDR1 0x360d +#define HDMI_AHB_DMA_BSTADDR2 0x360e +#define HDMI_AHB_DMA_BSTADDR3 0x360f +#define HDMI_AHB_DMA_MBLENGTH0 0x3610 +#define HDMI_AHB_DMA_MBLENGTH1 0x3611 +#define HDMI_AHB_DMA_STAT 0x3612 +#define HDMI_AHB_DMA_INT 0x3613 +#define HDMI_AHB_DMA_MASK 0x3614 +#define HDMI_AHB_DMA_POL 0x3615 +#define HDMI_AHB_DMA_CONF1 0x3616 +#define HDMI_AHB_DMA_BUFFSTAT 0x3617 +#define HDMI_AHB_DMA_BUFFINT 0x3618 +#define HDMI_AHB_DMA_BUFFMASK 0x3619 +#define HDMI_AHB_DMA_BUFFPOL 0x361a + +/* Main Controller Registers */ +#define HDMI_MC_SFRDIV 0x4000 +#define HDMI_MC_CLKDIS 0x4001 +#define HDMI_MC_SWRSTZ 0x4002 +#define HDMI_MC_OPCTRL 0x4003 +#define HDMI_MC_FLOWCTRL 0x4004 +#define HDMI_MC_PHYRSTZ 0x4005 +#define HDMI_MC_LOCKONCLOCK 0x4006 +#define HDMI_MC_HEACPHY_RST 0x4007 + +/* Color Space Converter Registers */ +#define HDMI_CSC_CFG 0x4100 +#define HDMI_CSC_SCALE 0x4101 +#define HDMI_CSC_COEF_A1_MSB 0x4102 +#define HDMI_CSC_COEF_A1_LSB 0x4103 +#define HDMI_CSC_COEF_A2_MSB 0x4104 +#define HDMI_CSC_COEF_A2_LSB 0x4105 +#define HDMI_CSC_COEF_A3_MSB 0x4106 +#define HDMI_CSC_COEF_A3_LSB 0x4107 +#define HDMI_CSC_COEF_A4_MSB 0x4108 +#define HDMI_CSC_COEF_A4_LSB 0x4109 +#define HDMI_CSC_COEF_B1_MSB 0x410A +#define HDMI_CSC_COEF_B1_LSB 0x410B +#define HDMI_CSC_COEF_B2_MSB 0x410C +#define HDMI_CSC_COEF_B2_LSB 0x410D +#define HDMI_CSC_COEF_B3_MSB 0x410E +#define HDMI_CSC_COEF_B3_LSB 0x410F +#define HDMI_CSC_COEF_B4_MSB 0x4110 +#define HDMI_CSC_COEF_B4_LSB 0x4111 +#define HDMI_CSC_COEF_C1_MSB 0x4112 +#define HDMI_CSC_COEF_C1_LSB 0x4113 +#define HDMI_CSC_COEF_C2_MSB 0x4114 +#define HDMI_CSC_COEF_C2_LSB 0x4115 +#define HDMI_CSC_COEF_C3_MSB 0x4116 +#define HDMI_CSC_COEF_C3_LSB 0x4117 +#define HDMI_CSC_COEF_C4_MSB 0x4118 +#define HDMI_CSC_COEF_C4_LSB 0x4119 + +/* HDCP Interrupt Registers */ +#define HDMI_A_APIINTCLR 0x5006 +#define HDMI_A_APIINTSTAT 0x5007 +#define HDMI_A_APIINTMSK 0x5008 + +/* CEC Engine Registers */ +#define HDMI_CEC_CTRL 0x7D00 +#define HDMI_CEC_STAT 0x7D01 +#define HDMI_CEC_MASK 0x7D02 +#define HDMI_CEC_POLARITY 0x7D03 +#define HDMI_CEC_INT 0x7D04 +#define HDMI_CEC_ADDR_L 0x7D05 +#define HDMI_CEC_ADDR_H 0x7D06 +#define HDMI_CEC_TX_CNT 0x7D07 +#define HDMI_CEC_RX_CNT 0x7D08 +#define HDMI_CEC_TX_DATA0 0x7D10 +#define HDMI_CEC_TX_DATA1 0x7D11 +#define HDMI_CEC_TX_DATA2 0x7D12 +#define HDMI_CEC_TX_DATA3 0x7D13 +#define HDMI_CEC_TX_DATA4 0x7D14 +#define HDMI_CEC_TX_DATA5 0x7D15 +#define HDMI_CEC_TX_DATA6 0x7D16 +#define HDMI_CEC_TX_DATA7 0x7D17 +#define HDMI_CEC_TX_DATA8 0x7D18 +#define HDMI_CEC_TX_DATA9 0x7D19 +#define HDMI_CEC_TX_DATA10 0x7D1a +#define HDMI_CEC_TX_DATA11 0x7D1b +#define HDMI_CEC_TX_DATA12 0x7D1c +#define HDMI_CEC_TX_DATA13 0x7D1d +#define HDMI_CEC_TX_DATA14 0x7D1e +#define HDMI_CEC_TX_DATA15 0x7D1f +#define HDMI_CEC_RX_DATA0 0x7D20 +#define HDMI_CEC_RX_DATA1 0x7D21 +#define HDMI_CEC_RX_DATA2 0x7D22 +#define HDMI_CEC_RX_DATA3 0x7D23 +#define HDMI_CEC_RX_DATA4 0x7D24 +#define HDMI_CEC_RX_DATA5 0x7D25 +#define HDMI_CEC_RX_DATA6 0x7D26 +#define HDMI_CEC_RX_DATA7 0x7D27 +#define HDMI_CEC_RX_DATA8 0x7D28 +#define HDMI_CEC_RX_DATA9 0x7D29 +#define HDMI_CEC_RX_DATA10 0x7D2a +#define HDMI_CEC_RX_DATA11 0x7D2b +#define HDMI_CEC_RX_DATA12 0x7D2c +#define HDMI_CEC_RX_DATA13 0x7D2d +#define HDMI_CEC_RX_DATA14 0x7D2e +#define HDMI_CEC_RX_DATA15 0x7D2f +#define HDMI_CEC_LOCK 0x7D30 +#define HDMI_CEC_WKUPCTRL 0x7D31 + +/* I2C Master Registers (E-DDC) */ +#define HDMI_I2CM_SLAVE 0x7E00 +#define HDMI_I2CM_ADDRESS 0x7E01 +#define HDMI_I2CM_DATAO 0x7E02 +#define HDMI_I2CM_DATAI 0x7E03 +#define HDMI_I2CM_OPERATION 0x7E04 +#define HDMI_I2CM_INT 0x7E05 +#define HDMI_I2CM_CTLINT 0x7E06 +#define HDMI_I2CM_DIV 0x7E07 +#define HDMI_I2CM_SEGADDR 0x7E08 +#define HDMI_I2CM_SOFTRSTZ 0x7E09 +#define HDMI_I2CM_SEGPTR 0x7E0A +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 + +/* Random Number Generator Registers (RNG) */ +#define HDMI_RNG_BASE 0x8000 + + +/* + * Register field definitions + */ +enum { +/* IH_FC_INT2 field values */ + HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_FC_STAT2 field values */ + HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_PHY_STAT0 field values */ + HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, + HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, + HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, + HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, + HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, + HDMI_IH_PHY_STAT0_HPD = 0x1, + +/* IH_CEC_STAT0 field values */ + HDMI_IH_CEC_STAT0_WAKEUP = 0x40, + HDMI_IH_CEC_STAT0_ERROR_FOLL = 0x20, + HDMI_IH_CEC_STAT0_ERROR_INIT = 0x10, + HDMI_IH_CEC_STAT0_ARB_LOST = 0x8, + HDMI_IH_CEC_STAT0_NACK = 0x4, + HDMI_IH_CEC_STAT0_EOM = 0x2, + HDMI_IH_CEC_STAT0_DONE = 0x1, + + +/* IH_MUTE_I2CMPHY_STAT0 field values */ + HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, + HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, + +/* IH_PHY_STAT0 field values */ + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE3 = 0x20, + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE2 = 0x10, + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE1 = 0x8, + HDMI_IH_MUTE_PHY_STAT0_RX_SENSE0 = 0x4, + HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2, + HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1, + +/* IH_AHBDMAAUD_STAT0 field values */ + HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, + HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, + HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, + HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, + HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, + HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, + +/* IH_MUTE_FC_STAT2 field values */ + HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* IH_MUTE_AHBDMAAUD_STAT0 field values */ + HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, + +/* IH_MUTE field values */ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, + +/* TX_INVID0 field values */ + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, + +/* TX_INSTUFFING field values */ + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, + +/* VP_PR_CD field values */ + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, + +/* VP_STUFF field values */ + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, + HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, + HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, + HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, + HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, + HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, + HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, + +/* VP_CONF field values */ + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, + HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, + HDMI_VP_CONF_PP_EN_ENMASK = 0x20, + HDMI_VP_CONF_PP_EN_ENABLE = 0x20, + HDMI_VP_CONF_PP_EN_DISABLE = 0x00, + HDMI_VP_CONF_PR_EN_MASK = 0x10, + HDMI_VP_CONF_PR_EN_ENABLE = 0x10, + HDMI_VP_CONF_PR_EN_DISABLE = 0x00, + HDMI_VP_CONF_YCC422_EN_MASK = 0x8, + HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, + HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, + +/* VP_REMAP field values */ + HDMI_VP_REMAP_MASK = 0x3, + HDMI_VP_REMAP_YCC422_24bit = 0x2, + HDMI_VP_REMAP_YCC422_20bit = 0x1, + HDMI_VP_REMAP_YCC422_16bit = 0x0, + +/* FC_INVIDCONF field values */ + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, + +/* FC_AUDICONF0 field values */ + HDMI_FC_AUDICONF0_CC_OFFSET = 4, + HDMI_FC_AUDICONF0_CC_MASK = 0x70, + HDMI_FC_AUDICONF0_CT_OFFSET = 0, + HDMI_FC_AUDICONF0_CT_MASK = 0xF, + +/* FC_AUDICONF1 field values */ + HDMI_FC_AUDICONF1_SS_OFFSET = 3, + HDMI_FC_AUDICONF1_SS_MASK = 0x18, + HDMI_FC_AUDICONF1_SF_OFFSET = 0, + HDMI_FC_AUDICONF1_SF_MASK = 0x7, + +/* FC_AUDICONF3 field values */ + HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, + HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, + HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, + HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, + HDMI_FC_AUDICONF3_LSV_OFFSET = 0, + HDMI_FC_AUDICONF3_LSV_MASK = 0xF, + +/* FC_AUDSCHNLS0 field values */ + HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, + HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, + HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, + HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, + +/* FC_AUDSCHNLS3-6 field values */ + HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, + HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, + HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, + HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, + HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, + HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, + HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, + HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, + + HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, + HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, + HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, + HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, + HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, + HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, + HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, + HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, + +/* HDMI_FC_AUDSCHNLS7 field values */ + HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, + HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, + +/* HDMI_FC_AUDSCHNLS8 field values */ + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, + +/* FC_AUDSCONF field values */ + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, + HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, + +/* FC_STAT2 field values */ + HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, + HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_INT2 field values */ + HDMI_FC_INT2_OVERFLOW_MASK = 0x03, + HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_MASK2 field values */ + HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, + HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, + HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, + +/* FC_PRCONF field values */ + HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, + HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, + HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, + HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, + +/* FC_AVICONF0-FC_AVICONF3 field values */ + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, + + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, + + HDMI_FC_AVICONF2_SCALING_MASK = 0x03, + HDMI_FC_AVICONF2_SCALING_NONE = 0x00, + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, + HDMI_FC_AVICONF2_SCALING_VERT = 0x02, + HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, + + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + +/* FC_DBGFORCE field values */ + HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, + HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, + +/* PHY_CONF0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, + HDMI_PHY_CONF0_SPARECTRL = 0x20, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, + HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, + +/* PHY_TST0 field values */ + HDMI_PHY_TST0_TSTCLR_MASK = 0x20, + HDMI_PHY_TST0_TSTCLR_OFFSET = 5, + HDMI_PHY_TST0_TSTEN_MASK = 0x10, + HDMI_PHY_TST0_TSTEN_OFFSET = 4, + HDMI_PHY_TST0_TSTCLK_MASK = 0x1, + HDMI_PHY_TST0_TSTCLK_OFFSET = 0, + +/* PHY_STAT0 field values */ + HDMI_PHY_RX_SENSE3 = 0x80, + HDMI_PHY_RX_SENSE2 = 0x40, + HDMI_PHY_RX_SENSE1 = 0x20, + HDMI_PHY_RX_SENSE0 = 0x10, + HDMI_PHY_HPD = 0x02, + HDMI_PHY_TX_PHY_LOCK = 0x01, + +/* PHY_I2CM_SLAVE_ADDR field values */ + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, + HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, + +/* PHY_I2CM_OPERATION_ADDR field values */ + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, + HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, + +/* HDMI_PHY_I2CM_INT_ADDR */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, + +/* HDMI_PHY_I2CM_CTLINT_ADDR */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, + +/* AUD_CTS3 field values */ + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, + HDMI_AUD_CTS3_N_SHIFT_1 = 0, + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, + /* note that the CTS3 MANUAL bit has been removed + from our part. Can't set it, will read as 0. */ + HDMI_AUD_CTS3_CTS_MANUAL = 0x10, + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, + +/* AHB_DMA_CONF0 field values */ + HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, + HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, + HDMI_AHB_DMA_CONF0_HBR = 0x10, + HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, + HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, + HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, + HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, + HDMI_AHB_DMA_CONF0_INCR4 = 0x0, + HDMI_AHB_DMA_CONF0_INCR8 = 0x2, + HDMI_AHB_DMA_CONF0_INCR16 = 0x4, + HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, + +/* HDMI_AHB_DMA_START field values */ + HDMI_AHB_DMA_START_START_OFFSET = 0, + HDMI_AHB_DMA_START_START_MASK = 0x01, + +/* HDMI_AHB_DMA_STOP field values */ + HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, + HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, + +/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ + HDMI_AHB_DMA_DONE = 0x80, + HDMI_AHB_DMA_RETRY_SPLIT = 0x40, + HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, + HDMI_AHB_DMA_ERROR = 0x10, + HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, + HDMI_AHB_DMA_FIFO_FULL = 0x02, + HDMI_AHB_DMA_FIFO_EMPTY = 0x01, + +/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */ + HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, + HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, + +/* MC_CLKDIS field values */ + HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, + HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, + HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + +/* MC_SWRSTZ field values */ + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + +/* MC_FLOWCTRL field values */ + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + +/* MC_PHYRSTZ field values */ + HDMI_MC_PHYRSTZ_ASSERT = 0x0, + HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + +/* MC_HEACPHY_RST field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, + HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, + +/* CSC_CFG field values */ + HDMI_CSC_CFG_INTMODE_MASK = 0x30, + HDMI_CSC_CFG_INTMODE_OFFSET = 4, + HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, + HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, + HDMI_CSC_CFG_DECMODE_MASK = 0x3, + HDMI_CSC_CFG_DECMODE_OFFSET = 0, + HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, + HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, + +/* CSC_SCALE field values */ + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, + HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, + +/* I2CM_OPERATION field values */ + HDMI_I2CM_OPERATION_WRITE = 0x10, + HDMI_I2CM_OPERATION_READ_EXT = 0x2, + HDMI_I2CM_OPERATION_READ = 0x1, + +/* HDMI_I2CM_INT */ + HDMI_I2CM_INT_DONE_POL = 0x08, + HDMI_I2CM_INT_DONE_MASK = 0x04, + +/* HDMI_I2CM_CTLINT */ + HDMI_I2CM_CTLINT_NAC_POL = 0x80, + HDMI_I2CM_CTLINT_NAC_MASK = 0x40, + HDMI_I2CM_CTLINT_ARBITRATION_POL = 0x08, + HDMI_I2CM_CTLINT_ARBITRATION_MASK = 0x04, + +}; + +enum imx_hdmi_type { + IMX6DL_HDMI, + IMX6Q_HDMI, +}; + +/* IOCTL commands */ +#define HDMI_IOC_MAGIC 'H' + +#define HDMI_IOC_GET_RESOURCE _IO(HDMI_IOC_MAGIC, 0) +#define HDMI_IOC_GET_CPU_TYPE _IO(HDMI_IOC_MAGIC, 1) + + +#endif /* __MXC_HDMI_H__ */ diff --git a/include/video/viv-metadata.h b/include/video/viv-metadata.h new file mode 100644 index 000000000000..d08680a4308e --- /dev/null +++ b/include/video/viv-metadata.h @@ -0,0 +1,116 @@ +/**************************************************************************** +* +* The MIT License (MIT) +* +* Copyright (c) 2014 - 2018 Vivante Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +***************************************************************************** +* +* The GPL License (GPL) +* +* Copyright (C) 2014 - 2018 Vivante Corporation +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software Foundation, +* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +* +***************************************************************************** +* +* Note: This software is released under dual MIT and GPL licenses. A +* recipient may use this file under the terms of either the MIT license or +* GPL License. If you wish to use only one license not the other, you can +* indicate your decision by deleting one of the above license notices in your +* version of this file. +* +*****************************************************************************/ + +#ifndef __VIV_METADATA_H__ +#define __VIV_METADATA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macro to combine four characters into a Character Code. */ +#define __FOURCC(a, b, c, d) \ + ((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) + +#define VIV_VIDMEM_METADATA_MAGIC __FOURCC('v', 'i', 'v', 'm') + +/* Compressed format now was defined same as dec400d, should be general. */ +typedef enum _VIV_COMPRESS_FMT +{ + _VIV_CFMT_ARGB8 = 0, + _VIV_CFMT_XRGB8, + _VIV_CFMT_AYUV, + _VIV_CFMT_UYVY, + _VIV_CFMT_YUY2, + _VIV_CFMT_YUV_ONLY, + _VIV_CFMT_UV_MIX, + _VIV_CFMT_ARGB4, + _VIV_CFMT_XRGB4, + _VIV_CFMT_A1R5G5B5, + _VIV_CFMT_X1R5G5B5, + _VIV_CFMT_R5G6B5, + _VIV_CFMT_Z24S8, + _VIV_CFMT_Z24, + _VIV_CFMT_Z16, + _VIV_CFMT_A2R10G10B10, + _VIV_CFMT_BAYER, + _VIV_CFMT_SIGNED_BAYER, + _VIV_CFMT_VAA16, + _VIV_CFMT_S8, + + _VIV_CFMT_MAX, +} _VIV_COMPRESS_FMT; + +/* Metadata for cross-device fd share with additional (ts) info. */ +typedef struct _VIV_VIDMEM_METADATA +{ + uint32_t magic; + + int32_t ts_fd; + void * ts_dma_buf; + + uint32_t fc_enabled; + uint32_t fc_value; + uint32_t fc_value_upper; + + uint32_t compressed; + uint32_t compress_format; +} _VIV_VIDMEM_METADATA; + +#ifdef __cplusplus +} +#endif + +#endif /* __VIV_METADATA_H__ */ + diff --git a/include/xen/interface/io/i2cif.h b/include/xen/interface/io/i2cif.h new file mode 100644 index 000000000000..36e9024a1b04 --- /dev/null +++ b/include/xen/interface/io/i2cif.h @@ -0,0 +1,95 @@ +/****************************************************************************** + * i2cif.h + * + * I2C device I/O interface for Xen guest OSes. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Copyright 2018 NXP + * + * Authors: Peng Fan <peng.fan@nxp.com> + */ + +#ifndef __XEN_PUBLIC_IO_I2CIF_H__ +#define __XEN_PUBLIC_IO_I2CIF_H__ + +#include <xen/interface/io/ring.h> +#include <xen/interface/grant_table.h> + +#define I2CIF_BUF_LEN I2C_SMBUS_BLOCK_MAX + 2 +#define I2CIF_MAX_MSG 2 + +#define I2CIF_M_RD 0x0001 /* read data, from slave to master */ + /* I2C_M_RD is guaranteed to be 0x0001! */ +#define I2CIF_M_TEN 0x0010 /* this is a ten bit chip address */ +#define I2CIF_M_RECV_LEN 0x0400 /* length will be first received byte */ +#define I2CIF_M_NO_RD_ACK 0x0800 /* if I2CIF_FUNC_PROTOCOL_MANGLING */ +#define I2CIF_M_IGNORE_NAK 0x1000 /* if I2CIF_FUNC_PROTOCOL_MANGLING */ +#define I2CIF_M_REV_DIR_ADDR 0x2000 /* if I2CIF_FUNC_PROTOCOL_MANGLING */ +#define I2CIF_M_NOSTART 0x4000 /* if I2CIF_FUNC_NOSTART */ +#define I2CIF_M_STOP 0x8000 /* if I2CIF_FUNC_PROTOCOL_MANGLING */ + +#define I2CIF_FUNC_I2C 0x00000001 +#define I2CIF_FUNC_10BIT_ADDR 0x00000002 +#define I2CIF_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_IGNORE_NAK etc. */ +#define I2CIF_FUNC_SMBUS_PEC 0x00000008 +#define I2CIF_FUNC_NOSTART 0x00000010 /* I2C_M_NOSTART */ +#define I2CIF_FUNC_SLAVE 0x00000020 +#define I2CIF_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */ +#define I2CIF_FUNC_SMBUS_QUICK 0x00010000 +#define I2CIF_FUNC_SMBUS_READ_BYTE 0x00020000 +#define I2CIF_FUNC_SMBUS_WRITE_BYTE 0x00040000 +#define I2CIF_FUNC_SMBUS_READ_BYTE_DATA 0x00080000 +#define I2CIF_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000 +#define I2CIF_FUNC_SMBUS_READ_WORD_DATA 0x00200000 +#define I2CIF_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000 +#define I2CIF_FUNC_SMBUS_PROC_CALL 0x00800000 +#define I2CIF_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000 +#define I2CIF_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000 +#define I2CIF_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */ +#define I2CIF_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */ +#define I2CIF_FUNC_SMBUS_HOST_NOTIFY 0x10000000 + +#define I2CIF_ADAPTER_NAME_LEN 32 + +struct i2cif_request { + struct { + __u16 addr; /* slave address */ + __u16 flags; /* msg flags */ + __u16 len; /* msg length */ + } msg[I2CIF_MAX_MSG]; + int num_msg; + __u8 write_buf[I2CIF_BUF_LEN]; + + bool is_smbus; + __u16 addr; + __u16 flags; + __u8 read_write; + __u8 command; + int protocol; +}; + +struct i2cif_response { + int result; + __u8 read_buf[I2CIF_BUF_LEN]; +}; + +DEFINE_RING_TYPES(i2cif, struct i2cif_request, struct i2cif_response); + +#endif |