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-rw-r--r--sound/soc/tegra/tegra30_i2s.c30
-rw-r--r--sound/soc/tegra/tegra_aic326x.c11
-rw-r--r--sound/soc/tegra/tegra_cs42l73.c44
-rw-r--r--sound/soc/tegra/tegra_max98088.c17
4 files changed, 84 insertions, 18 deletions
diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
index 469e9e116bc4..09c56dc37101 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -987,6 +987,9 @@ static int configure_baseband_i2s(struct tegra30_i2s *i2s, int is_i2smaster,
{
u32 val;
int i2sclock, bitcnt, ret, is_formatdsp;
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ u32 i;
+#endif
is_formatdsp = (i2s_mode == TEGRA_DAIFMT_DSP_A) ||
(i2s_mode == TEGRA_DAIFMT_DSP_B);
@@ -995,7 +998,6 @@ static int configure_baseband_i2s(struct tegra30_i2s *i2s, int is_i2smaster,
i2sclock = bit_clk;
} else {
i2sclock = rate * channels * bitsize * 2;
-
/* additional 8 for baseband */
if (is_formatdsp)
i2sclock *= 8;
@@ -1046,10 +1048,18 @@ static int configure_baseband_i2s(struct tegra30_i2s *i2s, int is_i2smaster,
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
if (i2s_mode == TEGRA_DAIFMT_DSP_A) {
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ i2s->reg_ch_ctrl |= (1 <<
+ TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT);
+#endif
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
} else if (i2s_mode == TEGRA_DAIFMT_DSP_B) {
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ i2s->reg_ch_ctrl |= (1 <<
+ TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT);
+#endif
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
@@ -1061,12 +1071,30 @@ static int configure_baseband_i2s(struct tegra30_i2s *i2s, int is_i2smaster,
tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ val = 0;
+ for (i = 0; i < channels; i++)
+ val |= (1 << i);
+
+ val |= val <<
+ TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_SHIFT;
+ val |= val <<
+ TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_SHIFT;
+ tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL2, val);
+
+ val = 0;
+ if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
+ val = channels - 1;
+
+ tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
+#else
val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
val &= ~(TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK |
TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK);
val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT |
1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
+#endif
val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
(1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
diff --git a/sound/soc/tegra/tegra_aic326x.c b/sound/soc/tegra/tegra_aic326x.c
index eb1caf400aa4..9b7d0e6f8c08 100644
--- a/sound/soc/tegra/tegra_aic326x.c
+++ b/sound/soc/tegra/tegra_aic326x.c
@@ -246,16 +246,27 @@ static int tegra_aic326x_set_dam_cif(int dam_ifc, int srate,
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
channels, bit_size, channels,
bit_size);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
+ channels, bit_size, channels,
+ 32);
+#else
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
channels, bit_size, channels,
bit_size);
+#endif
if (src_on) {
tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
src_srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+ src_channels, src_bit_size, 1, 32);
+#else
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
src_channels, src_bit_size, 1, 16);
+#endif
}
return 0;
diff --git a/sound/soc/tegra/tegra_cs42l73.c b/sound/soc/tegra/tegra_cs42l73.c
index 4c19cde98532..e8d9a62a966a 100644
--- a/sound/soc/tegra/tegra_cs42l73.c
+++ b/sound/soc/tegra/tegra_cs42l73.c
@@ -127,14 +127,18 @@ static int tegra_call_mode_put(struct snd_kcontrol *kcontrol,
int is_call_mode_new = ucontrol->value.integer.value[0];
int codec_index;
unsigned int i;
+ int uses_voice_codec;
if (machine->is_call_mode == is_call_mode_new)
return 0;
- if (machine->is_device_bt)
+ if (machine->is_device_bt) {
codec_index = BT_SCO;
- else
+ uses_voice_codec = 0;
+ } else {
codec_index = VOICE_CODEC;
+ uses_voice_codec = 1;
+ }
if (is_call_mode_new) {
if (machine->codec_info[codec_index].rate == 0 ||
@@ -146,11 +150,11 @@ static int tegra_call_mode_put(struct snd_kcontrol *kcontrol,
tegra30_make_voice_call_connections(
&machine->codec_info[codec_index],
- &machine->codec_info[BASEBAND], 1);
+ &machine->codec_info[BASEBAND], uses_voice_codec);
} else {
tegra30_break_voice_call_connections(
&machine->codec_info[codec_index],
- &machine->codec_info[BASEBAND], 1);
+ &machine->codec_info[BASEBAND], uses_voice_codec);
for (i = 0; i < machine->pcard->num_links; i++)
machine->pcard->dai_link[i].ignore_suspend = 0;
@@ -185,16 +189,27 @@ static int tegra_cs42l73_set_dam_cif(int dam_ifc, int srate,
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
channels, bit_size, channels,
bit_size);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
+ channels, bit_size, channels,
+ 32);
+#else
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
channels, bit_size, channels,
bit_size);
+#endif
tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
if (src_on) {
tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
src_srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
src_channels, src_bit_size, 1, 32);
+#else
+ tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+ src_channels, src_bit_size, 1, 16);
+#endif
}
return 0;
@@ -308,11 +323,10 @@ static int tegra_cs42l73_hw_params(struct snd_pcm_substream *substream,
}
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- if (i2s->dam_ifc)
- tegra_cs42l73_set_dam_cif(i2s->dam_ifc, srate,
- params_channels(params), sample_size, 0, 0, 0, 0);
- }
+ if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) &&
+ i2s->is_dam_used)
+ tegra_cs42l73_set_dam_cif(i2s->dam_ifc, srate,
+ params_channels(params), sample_size, 0, 0, 0, 0);
#endif
return 0;
@@ -452,9 +466,9 @@ static int tegra_bt_hw_params(struct snd_pcm_substream *substream,
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) &&
- i2s->dam_ifc)
+ i2s->is_dam_used)
tegra_cs42l73_set_dam_cif(i2s->dam_ifc, params_rate(params),
- params_channels(params), sample_size, 0, 0, 0, 0);
+ params_channels(params), sample_size, 0, 0, 0, 0);
#endif
return 0;
@@ -1038,10 +1052,10 @@ static int tegra_cs42l73_init(struct snd_soc_pcm_runtime *rtd)
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- if (machine->codec_info[BASEBAND].i2s_id != -1)
- i2s->is_dam_used = true;
-
- i2s->is_dam_used = false;
+ if (machine->codec_info[BASEBAND].i2s_id != -1) {
+ if (i2s->id == machine->codec_info[BT_SCO].i2s_id)
+ i2s->is_dam_used = true;
+ }
#endif
if (machine->init_done)
diff --git a/sound/soc/tegra/tegra_max98088.c b/sound/soc/tegra/tegra_max98088.c
index 6c45ed149d45..819075871fde 100644
--- a/sound/soc/tegra/tegra_max98088.c
+++ b/sound/soc/tegra/tegra_max98088.c
@@ -184,16 +184,27 @@ static int tegra_max98088_set_dam_cif(int dam_ifc, int srate,
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
channels, bit_size, channels,
bit_size);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
+ channels, bit_size, channels,
+ 32);
+#else
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
channels, bit_size, channels,
bit_size);
+#endif
if (src_on) {
tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
src_srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+ tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+ src_channels, src_bit_size, 1, 32);
+#else
tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
src_channels, src_bit_size, 1, 16);
+#endif
}
return 0;
@@ -317,7 +328,8 @@ static int tegra_max98088_hw_params(struct snd_pcm_substream *substream,
}
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ && (i2s->is_dam_used))
tegra_max98088_set_dam_cif(i2s->dam_ifc, srate,
params_channels(params), sample_size, 0, 0, 0, 0);
#endif
@@ -456,7 +468,8 @@ static int tegra_bt_hw_params(struct snd_pcm_substream *substream,
}
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ && (i2s->is_dam_used))
tegra_max98088_set_dam_cif(i2s->dam_ifc, params_rate(params),
params_channels(params), sample_size, 0, 0, 0, 0);
#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-24 19:12:47 +0000