summaryrefslogtreecommitdiff
path: root/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json
diff options
context:
space:
mode:
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json')
-rw-r--r--tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json18
1 files changed, 18 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json
new file mode 100644
index 000000000000..f3f57a3d48b4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/imx8qxp-ddr-uncore.json
@@ -0,0 +1,18 @@
+[
+ {
+ "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
+ "BriefDescription": "imx8qxp: bytes of all masters read from ddr0",
+ "MetricName": "imx8qxp-ddr0-all-r",
+ "MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4",
+ "MetricGroup": "i.MX8QXP_DDR_MON",
+ "SocName": "i.MX8QXP"
+ },
+ {
+ "PublicDescription": "Calculate bytes all masters wirte to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
+ "BriefDescription": "imx8qxp: bytes of all masters write to ddr0",
+ "MetricName": "imx8qxp-ddr0-all-w",
+ "MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4",
+ "MetricGroup": "i.MX8QXP_DDR_MON",
+ "SocName": "i.MX8QXP"
+ }
+]