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This prevents jumbled characters on serial ports with Sysvinit.
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Cleaned up incorrect iomux defines.
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disabled in UART config. The receive interrupt was attempting to schedule a work
queue only defined if EDMA is enabled.
kernel BUG at kernel/workqueue.c:1037!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
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registrations in Linux.
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interrupt instead of level triggered (low) to fix the following issue seen on
MVF platform.
Level Triggered interrupts are not One Shot in nature, resulting in interrupt
handler being called continusouly until a GPIO state change.
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This is the same defconfig that Timesys Factory uses.
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This patch was submitted by Roshni Shah <roshni.shah@timesys.com>
for ticket #52067
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This patch was submitted by Yoshihisa Ozawa <ozawa@lineo.co.jp> in
ticket #52306.
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when using USB1.
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the kernel.
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is not present.
Author: Roshni Shah <roshni.shah@timesys.com>
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Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value. However the memset itself became broken
by that patch for misaligned pointers.
This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.
Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.
While at it, the entry instructions are slightly reworked to help dual
issue pipelines.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 418df63adac56841ef6b0f1fcf435bc64d4ed177)
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optimizations
Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.
For instance in the following function:
void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
waiter->magic = waiter;
INIT_LIST_HEAD(&waiter->list);
}
compiled as:
800554d0 <debug_mutex_lock_common>:
800554d0: e92d4008 push {r3, lr}
800554d4: e1a00001 mov r0, r1
800554d8: e3a02010 mov r2, #16 ; 0x10
800554dc: e3a01011 mov r1, #17 ; 0x11
800554e0: eb04426e bl 80165ea0 <memset>
800554e4: e1a03000 mov r3, r0
800554e8: e583000c str r0, [r3, #12]
800554ec: e5830000 str r0, [r3]
800554f0: e5830004 str r0, [r3, #4]
800554f4: e8bd8008 pop {r3, pc}
GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.
This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:
Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).
Step 2
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Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:
save r8:
- str lr, [sp, #-4]!
+ stmfd sp!, {r8, lr}
and restore r8 on both exit paths:
- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
(...)
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
- ldr lr, [sp], #4
+ ldmfd sp!, {r8, lr}
Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:
save r8:
- stmfd sp!, {r4-r7, lr}
+ stmfd sp!, {r4-r8, lr}
and restore r8 on both exit paths:
bgt 3b
- ldmeqfd sp!, {r4-r7, pc}
+ ldmeqfd sp!, {r4-r8, pc}
(...)
tst r2, #16
stmneia ip!, {r4-r7}
- ldmfd sp!, {r4-r7, lr}
+ ldmfd sp!, {r4-r8, lr}
Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 455bd4c430b0c0a361f38e8658a0d6cb469942b5)
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This change fixes a linking problem, which happens if oprofile is selected to
be compiled as built-in:
`oprofile_arch_exit' referenced in section `.init.text' of
arch/arm/oprofile/built-in.o: defined in discarded section
`.exit.text' of arch/arm/oprofile/built-in.o
The problem is appeared after commit 87121ca504, which introduced
oprofile_arch_exit() calls from __init function. Note that the aforementioned
commit has been backported to stable branches, and the problem is known to be
reproduced at least with 3.0.13 and 3.1.5 kernels.
Cc: stable@kernel.org # 3.0+
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@nokia.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>
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The issue was caused due to sched_clock() inplementation in pit.c which reported values which were incosistent with what it should
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default console (i.e. printf) for MQX as of the beta-3 release.
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between cpu and dcu. This showed up when painting a large bootlogo. holes would appear and then fill in as the boot progressed.
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routing interrupt routing bits unchanged
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When serial-transmit a file from host to target, an error "BUG: scheduling
while atomic: cat/998/0x00010002" occurs.
BUG: scheduling while atomic: cat/998/0x00010002 Modules linked in:
Pid: 998, comm: cat
CPU: 0 Not tainted (3.0.15 #1)
PC is at n_tty_write+0x260/0x43c
LR is at tty_write_room+0x20/0x2c
pc : <80204700> lr : <80206194> psr: 60000013
sp : 863b9e78 ip : 8038e378 fp : 863b9ec4
r10: 00000fff r9 : 863b6400 r8 : 86165d80
r7 : 863b8000 r6 : 86368b6c r5 : 86368800 r4 : 00000002
r3 : 00000010 r2 : 00000000 r1 : 00000040 r0 : 00000002
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 863f8059 DAC: 00000015 <80031f5c>
(show_regs+0x0/0x54) from <803761f0>
(__schedule_bug+0x4c/0x60)
r4:863b9e30 r3:60000193
<803761a4> (__schedule_bug+0x0/0x60) from <8037941c>
(__schedule+0x35c/0x3c4)
Thanks to Tadayoshi Arai <ara@lineo.co.jp> for reporting this and submitting
this patch
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Signed-off-by: Ed Nash <ed@kidlearn.com>
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Allows the NAND to properly probe if cmdline partitioning
is not specified. Otherwise, it will fail silently.
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