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In android, IPU fills the I420 buffer. And GPU shows the buffer to display.
mx6's GPU has 32 Y-stride alignment for I420. The stride alignment will
be passed through by bytesperline. This update is only for
csi->smfc->mem channel.
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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USB does not work when plug in a usb device during system suspend. Under this
case, USB driver will be in low power mode, but WIE bit not be set if usb wake
up is not enabled.So there are only ID change interrupt no USB wakeup interrupt
after system resume.In current bsp, after system resume ID change status not be
clear,and ID change interrupt will continue happen, which cause the system busy.
No checking WIR bit if ID change interrupt happen when USB in low power mode to
fix this issue.
Signed-off-by: make shi <b15407@freescale.com>
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- It is better to disable otgsc and wake up interrupt to avoid an
abnormal interrupt happen during USB driver being removed.
- If the USB host is already at low power mode, only need turn on
the clock, no need turn off the clock.
- Need discharge dp and dm during USB driver being removed ,in order
to avoid a wakeup interrupt happen. And if the USB otg is in host
mode, we should clear discharge dp and dm in fsl_otg_set_host()
during system boot up.
Signed-off-by: make shi <b15407@freescale.com>
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One issue is bring in by merge.
The other is bring in by BSP's cpufreq commit.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Update config file and copyright comments.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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imx_3.0.35_android
Conflicts:
arch/arm/mach-mx6/board-mx6q_sabrelite.c
arch/arm/mach-mx6/board-mx6q_sabresd.c
arch/arm/plat-mxc/cpufreq.c
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Another patch changed caam_ipg_clk's CG to CG4 and this commit will
revert this change.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix chip select for SPI-NOR and
remove flags for no writeable partition for weim nor and
SPI-NOR
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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On Uart driver, CTS signal were never disabled
on the imx_set_mctrl function since the register was
written inside of the conditional.
if (mctrl & TIOCM_RTS) {
temp |= UCR2_CTS;
writel(temp, sport->port.membase + UCR2);
}
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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when detect hp inserted, disable speaker; when hp is plugout,
enable speaker.
Signed-off-by: Gary Zhang <b13634@freescale.com>
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Update config file and copyright comments.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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The UART2 pin mux settings are aligned to the mux settings
from i.MX53 ICS where GPS was operational.
Signed-off-by: Jeff Kudrick <jeff.kudrick@freescale.com>
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Warning: no return statement in function returning non-void.
fec_ptp_ioctl return zero when 1588 is not enable.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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When do Ethernet UDP stress overnight test with abundance of
data transmission, RX path may hang-on.
Dump the RX BD, found all BD "Empty" bit is cleared, which means
CPU read BD status is not right and waiting here.
Change BD memroy attribute from Normal to strongly ordered:
changes the memory attribute of C=0, B=0 instead of C=0, B=1.
Apply the change, the issue cannot be reproduced.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Issue:
By default, cd_gpio is 0 for always presented host controller, which is a
valid gpio. Then it will result to free_irq for 0 in esdhc_pltfm_exit for
these always_present host controllers.
Fix:
Invalid cd_gpio if the controller is indicated to be always present.
Acked-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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This patch add device drvier for novatek touch screen driver.
This touch screen chip will be support because it have
more populary screen size.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Per hardware design, we can't set LDO bypass mode on Sabreauto board,otherwise,
system will can't reset,if cpu freq run in 400Mhz.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Currently, if we used LDO bypass, will set pfuze register by I2C bus to modify
voltage according to different cpu frequency, if I2C transfer error, we should
restore to old cpu frequency, not only in cpufreq driver but also cpufreq core.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Our SDMA code did not support SDMA M2M copy function before, we add
SDMA M2M copy function in this patch, you can use 'sg' to use this
function, you can refer to 'linux-test/module_test/mxc_sdma_memcopy_test.c'
for how to use this function.
Signed-off-by: Ge Lei <b42127@freescale.com>
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Add V4L2_MEMORY_USERPTR support for csi v4l2 capture
Support V4L2_MEMORY_USERPTR and V4L2_MEMORY_MMAP now
Signed-off-by: Robby Cai <R63905@freescale.com>
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Bypass eMMC version checking, so that eMMC v4.5 can work on current kernel as
eMMC v4.4 cards, no specific v4.5 feature supported. Only basic read/write
operations are supported, also ddr mode is supported.
Acked-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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ov5642 add some delay to wait for sensor stable after S_PARM.
And ov5640_mipi should keep the same behavior.
So the upper layer can trust the first frame comes out of ov5640_mipi.
- delay added according to the recommended time from ov company
Signed-off-by: Sheng Nan <b38800@freescale.com>
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- must add a new config item to enable USB
CONFIG_USB_FSL_ARC_OTG=y
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
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The job ring driver exhibited a hang condition in the top of
caam_jr_dequeue() where a BUG_ON statement looks for a condition
where the output ring is said to have valid entries by the ring logic,
but the ring entries apparently have NULL descriptor pointers.
In the initial ARM port of this driver, the cache flush call
of the output ring content occured before the output ring read index
register read occurred, exposing a condition where the driver sensed valid
output entries, yet the entries written by the ring hardware were not
invalidated, and therefore were not visible to the processor, appearing
as false NULL entries.
This patch relocates the invalidate call to immediately follow the
check of the output read index, where it is required.
Signed-off-by: Vicki Milhoan <vicki.milhoan@freescale.com>
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Didn't care about pu_regulator is enabled or not when regulator restore if some
regulator set failed.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Didn't take more care about non-pfuze board, and there is two place in BSP will
call "mx6_cpu_regulator_init". It means regulator_get will be called twice on
every vddcore/vddsoc regulator. Then one value need set twice ,because from
regulator core view, there is two regulators share the same regulator. The non-
validate one will return error and print "COULD NOT SET GP VOLTAGE!!!!." on
Sabreauto board. The same as Sabrelite and ARM2 board.
Meanwhile, Sabreauto need be configured LDO bypass default.
Signed-off-by: Robin Gong <b38343@freescale.com>
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This bug was introduced by ENGR00229290 which fixed
the problem of greater than 16 LUTs used when 5-bit
waveform loaded. The bug is that now the driver is also
restricted to using 16 LUTs in 4-bit mode.
The fix is to correct the test of the EPDC_FORMAT
register used to determine if a 5-bit waveform
is loaded.
Also removed the while loop in favor of a bitwise OR
used to determine if a chosen LUT has yet to be
acknowledged by the interrupt handler.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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* Aline weim-nor partition layout with u-boot expected
offtsets
"bootloader" /dev/mtd0
"bootenv" /dev/mtd1
"kernel" /dev/mtd2
"rootfs" /dev/mtd3
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Aline spi-nor partition layout
* set correct chip-select value
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Commit 88f5acf88ae6 ("mm: page allocator: adjust the per-cpu counter
threshold when memory is low") changed the form how free_pages is
calculated but it forgot that we used to do free_pages - ((1 << order) -
1) so we ended up with off-by-two when calculating free_pages.
Reported-by: Wang Sheng-Hui <shhuiw@gmail.com>
Signed-off-by: Michal Hocko <mhocko@suse.cz>
Acked-by: Mel Gorman <mgorman@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- add CONFIG_MACH_MX6SL_EVK to imx6s_android_defconfig
Signed-off-by: Jack Lee <jacklee@freescale.com>
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SDP boards layout have board's width aligne with LVDS's height
Update the mma8451 and mag3110's config to algin with SDP board
Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
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Currently, we use pm_notifier to enter suspend/resume flow. But in the notifier
we only set cpufreq, didn't tell CPUFREQ core what the current cpufreq setting
now. So in the next time if CPUFREQ core find the current cpu frequncy is not
the value that CPUFREQ core want to set before. CPUFREQ core will force to set
the freqs.old with its own rule, which means the freqs.old will be MODIFYED
unexpectedly, and this will cause wrong loops_per_jiffy. We need add cpufreq_
notify_transition in the suspend/resume interface of cpufreq.
Signed-off-by: Robin Gong <b38343@freescale.com>
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When pause the capture test program, the "working queue empty" message
shows up repeatedly. However this message is expected to show up because
there's no QBUF called. Change pr_err to pr_debug to keep it as debug level.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Without this dependency, we have to manually disable
CONFIG_VIDEO_MXC_PXP_V4L2 when disable CONFIG_FB_MXC_ELCDIF_FB.
Otherwise, a build error shows up. This patch fixed it.
Signed-off-by: Robby Cai <R63905@freescale.com>
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added ioctls are:
VIDIOC_ENUM_FRAMEINTERVALS
VIDIOC_ENUM_FRAMESIZES
VIDIOC_ENUM_FMT
VIDIOC_DBG_G_CHIP_IDENT
Signed-off-by: Robby Cai <R63905@freescale.com>
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Forget submit some local change...
Signed-off-by: Robin Gong <b38343@freescale.com>
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On Sabresd board design, the WDOG_B output to reset external pmic source from
GPIO_2 pad which can be configured as WDOG2_WDOG_B, so if in ldo bypass mode,
we should use WDOG2 reset signal to reset pmic, not WDOG1. Also, configure the
related pins.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Restore back cpu freq and regulator if set fail.
Signed-off-by: Robin Gong <b38343@freescale.com>
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U-boot will not care about ldo bypass, move these code from u-boot to kernel.
Move the workaround for PFUZE1.0 to kernel too.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Currently, use CONFIG_MX6_INTER_LDO_BYPASS to enable/disable LDO bypass, and
use the same macro in u-boot too. It's not very friendly ,it will be more
flexible if use dynamic configure by command line input by u-boot.
Two ways to enable LDO bypass:
1. use command line:
You can set "ldo_active=on" or "ldo_active=off" in command line to enable/
disable LDO bypass.
2. set enable_ldo_mode value in board file:
If you didn't set the param in command line, every board
will use its default value, for example, you can find below code in arch/arm/
mach-mx6/mx6q_sabresd_pmic_pfuze100.c:
static int pfuze100_init(struct mc_pfuze *pfuze)
{
....
/*use default mode(ldo bypass) if no param from cmdline*/
if (enable_ldo_mode == LDO_MODE_DEFAULT)
enable_ldo_mode = LDO_MODE_BYPASSED;
....
}
Note:
1.You should know clearly ldo bypass can be only enabled in the board
that mounted with external pmic to supply VDDARM_IN/VDDSOC_IN power rail, and
you should implement related external regulator firstly, such as:
in arch/arm/mach-mx6/board-mx6q_sabresd.c
static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
....
}
otherwise, you have to use internal ldo which is the default configuration.
2.one special case, if the chip is 1.2Ghz, it can't be set LDO bypass.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Before, we use "arm_freq" in command line to set 1.2G. Now we will read the
fuse bit and "arm_freq", get the mini value to be used as "arm_max_freq".And:
1. you can easily set CPU max freq on what frequency you want by cmdline.
2. if you didn't set arm_freq in cmdline, kernel will read the fuse bit
(0x021bc440) to set the right arm_max_freq.
At the same time, add 1Ghz setpoint if chip max freq is 1.2Ghz.
Signed-off-by: Robin Gong <b38343@freescale.com>
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This patch add the fuse check for VPU_DISABLE feature. If the fuse
bit for VPU_DISABLE is 1, which means VPU is disabled, then we will
not register VPU device to the kernel.
Signed-off-by: Jason Liu <r64343@freescale.com>
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Setting certain IOMUX settings on SD1 prevents the system from
entering suspend. These pins are already configured as GPIO, so
it does not help to reconfigure them during suspend.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In MX6Q/DL, originally GPIO_0 is used as CKO pin function. when SNVS
module is enabled, CKO output stops suddenly.
Both CKO clock config register CCOSR and GPIO_0 IOMUX register value are
not changed. But because ALT7 of GPIO_0 pad is SNVS_VIO_5 function. I
doubt that when SNVS module is enabled, GPIO_0 pad is automatically
changed to SNVS instance by SoC.
Thus we add option for snvs enable/disable.
Signed-off-by: Terry Lv <r65388@freescale.com>
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The reason is that when switching from SHA1 to SHA256, cryptodev will
create a new session.
But in this new session, the __ctx in allocated req is not fully initialized.
Thus dma_buf in __ctx will be a random value.
If the value is 0 or some address in DMA memory, that will be ok,
otherwise, it will crashed in dma_unmap_single().
The calling sequence is:
ahash_final_ctx=>try_buf_map_to_sec_sg()=>dma_unmap_single()
When calling dma_unmap_single(), the parameter buf_dma is invalid in
crash case.
The error msg is:
kernel BUG at arch/arm/mm/dma-mapping.c:478!
requested hash CRYPTO_SHA2_256, Unable to handle kernel NULL pointer
dereference at virtual address 00000000
got sha256 with driver sha256-caapgd = e4ea0000
m
Encrypting in chunks of 256 b[00000000] *pgd=74edb831ytes: ,
*pte=00000000, *ppte=00000000
Internal error: Oops: 817 [#1] PREEMPT SMP
Modules linked in: cryptodev
CPU: 0 Not tainted (3.0.35-02200-ge392070-dirty #68)
PC is at __bug+0x1c/0x28
LR is at __bug+0x18/0x28
pc : [<80044260>] lr : [<8004425c>] psr: 60000013
sp : e4ec7c40 ip : ea9a2000 fp : 00000010
r10: 883f8038 r9 : 883f8038 r8 : e4803060
r7 : 00000000 r6 : 00000001 r5 : 00000000 r4 : 6f66c10a
r3 : 00000000 r2 : 80aafd5c r1 : 60000093 r0 : 00000033
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 74ea004a DAC: 00000015
Process sha_speed (pid: 2747, stack limit = 0xe4ec62f0)
Stack: (0xe4ec7c40 to 0xe4ec8000)
7c40: 74803184 8004a424 e4803000 e4730c08 e4262840 803c50dc
e4786f20 883f8000
7c60: 00000020 00000000 00000028 883f8018 e43ffcc0 e4803000
00000000 803c3d04
7c80: 00000004 80041104 e4ec6000 00000000 7efc4b64 803c3d10
e4774a3c 802079f8
7ca0: e43ffd1c e43ffcc0 00000000 7f0031a0 e4ec7e0c e43ffcc0
e4ec7e0c 7f00240c
7cc0: 00000100 e4786f20 e481bd40 e4ec7cd8 e4ec7cdc 7f0016b4
e4803200 00000000
7ce0: e4094480 00000000 7efc4b2c 00000004 80041104 7f001b64
8c81200c 00000000
7d00: 3fe1c2a2 2aba7e2c 00000000 00000000 00000000 00000000
00000000 2abc8870
7d20: 2abc8870 2abc8870 7efc4e10 00000000 2aba3000 00000000
2abc7f48 00000000
7d40: 00000000 00000000 00000000 00000000 00000000 00000000
2abc7f88 2abc7f80
7d60: 2abc7f50 2abc7f60 2abc7f68 00000000 00000000 00000000
2abc7f70 2abc7f78
7d80: 00000000 32616873 2a003635 00000000 00000000 2abc7fa0
2abc7fa8 2abc7fb0
7da0: 2abc7f90 00000000 00000000 2abc7f98 00000000 00000000
00000000 00000000
7dc0: 00000000 32616873 632d3635 006d6161 00000000 00000000
00000000 00000000
7de0: 2abc7fc0 2abc7fb8 00000000 2abc7fd0 00000000 00000000
00000000 00000000
7e00: 00000000 00000000 00000001 3fe1c2a2 00000000 00000100
00012008 00000000
7e20: 7efc4ab8 00000000 00000000 8006a120 e4044740 8c80ef40
00000001 00000000
7e40: 00000002 e4044740 e4ec7e7c 8006f5f4 e4ec6000 8007ffd4
e4348880 60000093
7e60: 00000000 80ae6de8 e4253200 8004e0fc 00000261 8028c0f4
e4877000 80ae6de8
7e80: e4786f20 e481bd40 00000261 8028c0f4 000059ac 00000000
36390b02 00000000
7ea0: e4cd7b6c e43488d0 8c80e4c4 00000038 e43488d0 802342dc
0000003f e43488d0
7ec0: 8c80e4b8 8c80e4b8 00000038 80090714 0000003f 8aafab02
00000000 80091134
7ee0: 8aafab02 0000003f e4ec6000 80a99cc0 e4eed510 7efc4b2c
e4ef96e0 00000004
7f00: 80041104 800febd0 60a9b3cd e4786f20 e4348880 00000000
e4ec7f88 e43488d0
7f20: e4ec6000 00000000 00000000 80091408 00000000 00000001
00000001 e4ec7f78
7f40: 000059b1 00000000 fffffff7 80aedc50 80a8a0c0 00000000
00000000 e4ec7f90
7f60: 7efc4b20 e4ef96e0 7efc4b2c c01c6368 00000004 80041104
e4ec6000 00000000
7f80: 7efc4b64 800ff0d4 00000000 00000000 00000109 00000000
00000000 00008628
7fa0: 00000036 80040f80 00000000 00000000 00000004 c01c6368
7efc4b2c 7efc4b2c
7fc0: 00000000 00000000 00008628 00000036 00000000 00000000
2abc8000 7efc4b64
7fe0: 00000000 7efc4a90 00008b5c 2ac857bc 80000010 00000004
e28bd000 e8bd0800
[<80044260>] (__bug+0x1c/0x28) from [<8004a424>]
(___dma_single_dev_to_cpu+0x84/0x94)
[<8004a424>] (___dma_single_dev_to_cpu+0x84/0x94) from [<803c50dc>]
(ahash_final_ctx+0x1a0/0x41c)
[<803c50dc>] (ahash_final_ctx+0x1a0/0x41c) from [<803c3d10>]
(ahash_final+0xc/0x10)
[<803c3d10>] (ahash_final+0xc/0x10) from [<802079f8>]
(crypto_ahash_op+0x28/0xc0)
[<802079f8>] (crypto_ahash_op+0x28/0xc0) from [<7f0031a0>]
(cryptodev_hash_final+0x30/0xc0 [cryptodev])
[<7f0031a0>] (cryptodev_hash_final+0x30/0xc0 [cryptodev]) from
[<7f00240c>] (crypto_run+0x10c/0x398 [cryptodev])
[<7f00240c>] (crypto_run+0x10c/0x398 [cryptodev]) from [<7f001b64>]
(cryptodev_ioctl+0x360/0x768 [cryptodev])
[<7f001b64>] (cryptodev_ioctl+0x360/0x768 [cryptodev]) from
[<800febd0>] (do_vfs_ioctl+0x80/0x54c)
[<800febd0>] (do_vfs_ioctl+0x80/0x54c) from [<800ff0d4>]
(sys_ioctl+0x38/0x5c)
[<800ff0d4>] (sys_ioctl+0x38/0x5c) from [<80040f80>]
(ret_fast_syscall+0x0/0x30)
Code: e59f0010 e1a01003 eb12fddb e3a03000 (e5833000)
---[ end trace 0057f6be00952f77 ]---
Signed-off-by: Terry Lv <r65388@freescale.com>
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Read "Disabled MLB" bit in OTP CFG2 to check if to enable mlb.
Signed-off-by: Terry Lv <r65388@freescale.com>
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For ASRC memory to memory transfer, user would send driver input buffer
and driver would copy converted output buffer into user's buffer.
However, ASRC can't promise the ratio of output buffer size/input buffer
size being equal to output sample rate/input sample rate.e.g, for
convert from 8k to 48k and 1000 bytes input buffer size, ASRC may pop
out 5999 bytes or 6001 bytes. If driver copy all 6001 bytes into user's
buffer, kernel dump may happens cause of accessing unexisted buffer.
In this patch, if ASRC output buffer size is larger than user's buffer
size, discard exact part.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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warning:
Compiling warning on mainline imx_3.0.35 (potential bug):
drivers/mxc/asrc/mxc_asrc.c: In function 'asrc_output_task_worker':
drivers/mxc/asrc/mxc_asrc.c:961:68: warning: 't_size' may be used
uninitialized in this function [-Wuninitialized]
drivers/mxc/asrc/mxc_asrc.c:943:23: note: 't_size' was declared here
In this patch, init t_size.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
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In ASoC ESAI machine driver, use ASRC ops instead of directly use ASRC
function calling, so that it can support ASRC loadable.
Signed-off-by: Ge Lei <b42127@freescale.com>
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