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2012-05-24asoc: tegra: utils: fix for multiple instances of extern1 clock.Ankit Gupta
The extern1 codec clock was not getting switched off whenever codec goes below BIAS_OFF level. Moreover, there were two instances of extern1 clock whenever codec was on. Reason behind this was that, those codecs for which probe function was called and were not present on board, turned on their extern1 clock, but clean up routine (for switch device register failure) was not able to turn off the clock. With this change, a conditional check is put to turn off the clock. (Bug 984678) Signed-off-by: Ankit Gupta <ankitgupta@nvidia.com> Change-Id: I585ecf73c0cabca856592dcd84e67588dfe13beb Reviewed-on: http://git-master/r/104073 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Ankit Gupta (Engrg-SW) <ankitgupta@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-24mfd: tps80031: turn on backup battery charger circuitTom Cherry
The backup battery for the RTC circuit needs to be manually turned on. This change turns it on when the driver is first probed, off during LP0 to prevent excess power draw, and back on again upon resume. Bug 986402 Change-Id: Id4768929d6a73546662806f04d98d714997174b0 Signed-off-by: Tom Cherry <tcherry@nvidia.com> Reviewed-on: http://git-master/r/103425 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-24arm: tegra: Enable arm errata 764369Krishna Reddy
Enable arm errata 764369 for TEGRA_2x and 3x. Bug 981223 Bug 885467 Change-Id: Ie013dc1ed4f1417a72dda72ea2d079a6534c3933 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/104181 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-24nvmap: Use linux conventions.Krishna Reddy
Avoid multiple CONFIG_TEGRA_NVMAP ifdefs. Change-Id: Ic186a8203d8b2291d3d39ce8b612b33bee16f531 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/103937 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-24net: wireless: bcm4329: Fix GCC 4.6 warningDan Willemsen
This module has -Werror turned on, so this was causing the build to break on GCC 4.6: drivers/net/wireless/bcm4329/wl_iw.c: In function 'wl_iw_set_pmksa': drivers/net/wireless/bcm4329/wl_iw.c:5149:5: error: array subscript is above array bounds [-Werror=array-bounds] drivers/net/wireless/bcm4329/wl_iw.c:5152:5: error: array subscript is above array bounds [-Werror=array-bounds] It's a partial 'backport' of a change made to the bcmdhd driver: commit 09a8dc7361d0e603d9935ec7f736fabaa2e6dc7a net: wireless: bcmdhd: Combined P2P fix Change-Id: Ie62ad82f884c213553772ac91eaf85e17a807503 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-on: http://git-master/r/88694 GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-05-23video: tegra: detect fbmem alignment on probeJon Mayo
Detect the stride size used by the bootloader. If DC is not enabled, fallback to a default stride size. Bug 973111 Change-Id: If04647ddf04a44987cd841062ff30e03fa4d6a02 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/104031 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-23asoc: tegra: P1852 machine: Add TDM mode settingsNitin Pai
Pass TDM mode variables for CPU dai. Codec Id is not passed properly, hence use dual instances of the dai_link operations. Bug 948478 Change-Id: I13188d5001b8f9c2f2f67ee7a9d3bec89311037d Signed-off-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-on: http://git-master/r/103793 Reviewed-by: Nitin Pai <npai@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-05-23spi: tegra: synchronize PPSB late writeLaxman Dewangan
When any write is made to PPSB register, it take time to actual happen in the register due to ARM-PPSB design. Delay or readback is required to make sure that write is completed. There is no worst case guaranteed delay and hence doing the register read to make write completes actually. Change-Id: Iefd25115e1a9f02c64e83f11a4e249ad9d086d16 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/102207 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-23spi: tegra: cleanup in runtime_pm implementation.Laxman Dewangan
Cleaning up runtime pm implementation for the driver. There is lots of duplicate code which is not require as it is handled in the runtime framework. Change-Id: I4494cdd3518cbcb90f24fb3387f38c9859b4f957 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/102206 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-23arm: tegra: cardhu: add TEGRA_CARDHU_DUAL_DSI_PANEL config optionPreetham Chandru
add TEGRA_CARDHU_DUAL_DSI_PANEL config option to enable or disable dual dsi panel in cardhu Bug 935764 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I9a93386c046f5845a3dcf55c575de6b8e67f188d Reviewed-on: http://git-master/r/96706 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-23video: tegra: dsi: enable dsi panel BPreetham Chandru
Enable dsi panel B by setting the first bit in APB_MISC_GP_MIPI_PAD_CTRL_0 register. Bug 935764 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I9e958e0c9d9e934edf77688fd6a987b5e863392b Reviewed-on: http://git-master/r/96672 Reviewed-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Kiran Adduri <kadduri@nvidia.com> Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-23video: tegra: remove free memory checkKirill Artamonov
Used free memory check in allocation policy is not working, because it doesn't calculate available physical memory size in same way as android oom killer. It also breaks kernel build if swapping is enabled. Remove free memory check from allocation policy. Change-Id: I214d1829451f313dbace967e87ed4111e688865d Reviewed-on: http://git-master/r/85227 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-23arm: tegra: kai: change thermal sensor to nct72Chandler Zhang
Kai board uses OnSemi NCT72 thermal sensor. NCT72 is pin and register compatible to NCT1008. Change the i2c device id from "nct1008" to "nct72" to avoid confusion. Bug 961970 Reviewed-on: http://git-master/r/100466 Signed-off-by: Chandler Zhang <chazhang@nvidia.com> (cherry picked from commit 07ed4a320ff7e18e615270e0e15bd4212e6a7c9f) Change-Id: I6ef858d27b1b1f35ddd071542bb22caed2e776ab Reviewed-on: http://git-master/r/103582 Tested-by: Daniel Fu <danifu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-23misc: nct1008: add id for nct72Chandler Zhang
Add id for nct1008 compatible thermal sensor: NCT72 Bug 961970 Change-Id: I792af664f73b6d1c8317a35c66330cf571cf3aba Reviewed-on: http://git-master/r/100465 Signed-off-by: Chandler Zhang <chazhang@nvidia.com> [danifu@nvidia.com: resolved conflicits in nct1008.c] Signed-off-by: Daniel Fu <danifu@nvidia.com> Reviewed-on: http://git-master/r/103581 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-23video: tegra: dc: Open-up HDMI mode filterShashank Sharma
We support dynamic pixel-clock setting now, so open HDMI mode filter by not rejecting a mode due to pixel clock mismatch. If the mode's requested pixclock is within the suppoted range, check few constraints of hardware and allow it. Add aspect ratio check to reject modes with awkward aspect ratio. Bug 967458 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Change-Id: Ife474dbfe4137a000a4a43b0e1ff72847f2a8b0a Reviewed-on: http://git-master/r/96163 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-23asoc: tegra: Add TDM mode supportNitin Pai
Added TDM mode support in I2S driver. Added support functions in AHUB to pass audio/client bits. Added support functions in AHUB to pass audio/client channels. Fixed the stopping of I2S/TDM by clearing the fifo. Bug 948478 Signed-off-by: Nitin Pai <npai@nvidia.com> Change-Id: I560f4ab5b71e4833931934275272a094241241fe Reviewed-on: http://git-master/r/103840 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-05-23media: video: tegra: Do not use nvmap private headerTerje Bergstrom
Do not include nvmap private header. The needed function is available in the public header. Bug 965206 Change-Id: I2ff752c66e66f64e8c518711aecf6f54dc152d41 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/103676 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-23video: tegra: host: move function pointers to nvhost_driverMayuresh Kulkarni
- currently, function pointers are inside nvhost_device - these functions abstract the device specific implementation of a functionality per SoC - move them to nvhost_driver so that nvhost_device can be instantiated from arch code using board files/device trees - add support to use single driver for multiple devices using concept of id_table. this will be useful in supporting multiple SoC devices binding single driver - also add some notes about how device name is expected Bug 871237 Change-Id: I4c75d7121d26c3bdc50f058e0d144d89ca0edbd9 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/100985 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-22video: tegra: nvmap: Export nvmap_duplicate_handle_idTerje Bergstrom
Export nvmap_duplicate_handle_id() for usage by other drivers. It is already being used in nvavp and tegradc, and nvhost needs it to be able to move the relocation code to inside nvhost. Bug 965206 Change-Id: I3f818d1faa967886e834aa457a99dfdb61bc6b85 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/103587 Reviewed-by: Automatic_Commit_Validation_User
2012-05-22mmc: returning correct mmc test case numberVishal Singh
mmc_test currently shows test case number as 0 for all test cases. Correcting this to depict the correct test case number. Bug 976137. Change-Id: Ifa7bdd08d537ef20a3303594938a771e823d4e3b Signed-off-by: Vishal Singh <vissingh@nvidia.com> Reviewed-on: http://git-master/r/103368 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Tested-by: Shridhar Rasal <srasal@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-05-22media: video: tegra: fix nvc power managementAnton Kondratenko
NVC focuser code was not up to date with the latest changes related to power management in upper layers. This change is to fix it. Bug 968003 Change-Id: I362fa062039eaa06c4f67644eac7ee2db0bf7d6b Signed-off-by: Anton Kondratenko <akondratenko@nvidia.com> Reviewed-on: http://git-master/r/103188 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-05-22rtc: tps6591x: Limiting years in the 0 - 99 rangeVenu Byravarasu
As RTC can store year in the 0 - 99 range only, handling it accordingly bug 985890 Change-Id: Idcfb29028f482283ae2658579a3283c7d4f230f1 Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-on: http://git-master/r/102798 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-22video: tegra: dc: remove bandwidth efficiencyVenkata (Muni) Anda
Remove the efficiency factor in the bandwidth calculation. Clock API will take care off setting the right clock based factoring the efficiency. Change-Id: I2b549197778b5afaf1aab3cc87a84debb08172e8 Reviewed-on: http://git-master/r/91659 Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/103682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21arm: tegra: Added support for TDM mode paramsNitin Pai
Added TDM mode params to be passed from platform to the machine driver Bug 948478 Change-Id: I909db0ceebde002fcebcf7635cebe98c6a74142d Signed-off-by: Nitin Pai <npai@nvidia.com> Reviewed-on: http://git-master/r/103594 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-05-21ARM: tegra: clock: Account for memory BW efficiencyAlex Frid
Account for memory efficiency when processing requests from Tegra3 EMC shared bandwidth users. Do not round requests from these users until they are aggregated. The respective debugfs node: /d/tegra_emc/efficiency (in %). Bug 952739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 86929087f68c4366d6179101eb9a6a6473a4f084) Change-Id: I4acdd89f44de1401ce5dad8fc4936932df014458 Reviewed-on: http://git-master/r/103499 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21ARM: tegra: clock: Share Tegra3 camera EMC bandwidthAlex Frid
Change Tegra3 camera EMC shared user mode from SHARED_FLOOR to SHARED_BW and combine requests from ISO clients (camera and display, which is already in SHARED_BW mode). Bug 652739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit f1107ea4fe229d9807c1fba79a003753d0a8be7f) Change-Id: If5b7f578060a646df1794dde8c9be2944d88e942 Reviewed-on: http://git-master/r/103498 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21video: tegra: dc: Enable GCOV for dc/ext codeChao Xu
Change-Id: Ie6d425f06911008d77c2ed87dc7b40611755ee6a Signed-off-by: Chao Xu <cxu@nvidia.com> Reviewed-on: http://git-master/r/103396 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mark Stadler <mastadler@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-21arm: tegra: apbdmaio: Add dma_sync* callsPradeep Kumar
Add dma_sync* calls to make memory coherent between CPU and Device. Bug 983988 Change-Id: I40c514e01130762a12833c3ab7e0613f984870c6 Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/103336 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21ARM: tegra: define/enable ARCH_HAS_SUSPEND_PAGETABLEChris Johnson
For Tegra, the CPU suspend code path installs its own 1:1 pagetable setup once at init time. This pagetable is used by all CPUs doing suspend/resume. We want to use the common ARM code for CPU suspend/resume, but don't want the MMU reenable code to patch the current pagetable as it's shared (and could cause problems if the pagetable loads/stores were were interleaved). The installed pagetable already covers the cpu_resume_turn_mmu_on VA, so we're able to just use the existing pagetable. This sets up the CONFIG option to skip this part of the MMU reenable. Bug 929856 Change-Id: Ibbac258122df6def7f7a2d511778a6f11d474938 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/92350 Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Ahung Cheng <ahcheng@nvidia.com> Tested-by: Ahung Cheng <ahcheng@nvidia.com> Reviewed-on: http://git-master/r/103205 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21ARM: vfp: ensure preemption is disabled when enabling VFP accessWill Deacon
The vfp_enable function enables access to the VFP co-processor register space (cp10 and cp11) on the current CPU and must be called with preemption disabled. Unfortunately, the vfp_init late initcall does not disable preemption and can lead to an oops during boot if thread migration occurs at the wrong time and we end up attempting to access the FPSID on a CPU with VFP access disabled. This patch fixes the initcall to call vfp_enable from a non-preemptible context on each CPU and adds a BUG_ON(preemptible) to ensure that any similar problems are easily spotted in the future. originally from http://git.kernel.org/?p=linux/kernel/git/will/linux.git;a=commit;h=468c963e0210bf8108b17cf75066f25f39cabb56 Change-Id: I26fff8abe4c18bd3291613f70d0228aa2313811a Reported-by: Hyungwoo Yang <hwoo.yang@gmail.com> Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Reviewed-on: http://git-master/r/102315 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-21Revert "ARM: vfp: Prevent process migration"Hyungwoo Yang
This reverts commit 68667feb8eae225f1293a7044c989ab0bba8dbd1. Change-Id: I59023f2d83392465f7a989693b67cef96d565ed9 Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com> Reviewed-on: http://git-master/r/102314 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-21arm: tegra: governor: change governor using cpufreq interfacePuneet Saxena
Older code sets "conservative" governor in early-suspend using sysfs entries.This implementation changes governor in early-suspend using cpufreq interfaces. bug 871958 Change-Id: I721afb6184982a063dc5f330da31f8fb88481cfd Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/100849 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21ARM: tegra: decouple mode from flagsBo Yan
When doing LP2 on last standing CPU, we currently pass "mode | flag" to a few functions as argument, with the assumption that "mode" will be confined to lower 22 bits in PMC_CTRL register and "flags" will occupy higher 10 bits. If "flags" grows downward or "mode" grows upward, without this explicit knowledge, LP2 will break on the last standing CPU. Therefore we need to decouple them. Currently only "flags" part is being used when passed to other subroutines, so use "flags" only. Change-Id: I299c998145d81c17760bda8a0b56311fed553958 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/100358 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21ARM: Tegra: P1852: changed nor timing regs and freqMohit Kataria
Nor frequency and timing registers changed as per values provided by syseng Bug 978870 Change-Id: I18313c7df6265ddd4140d264ac2751ed8f1982df Reviewed-on: http://git-master/r/103355 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-21ARM: tegra: cardhu: add A07 memory tableRay Poudrier
Bug 970890 Change-Id: If0ebb1ad76dfe3267bc0acd3feae70a701c1dfdb Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/103237 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-21power: smb349: support for self-powered devicesChandler Zhang
Some self-powered devices doesn't strictly follow USB spec that has 5V Vbus to upstream cannot work with mux on the data lines. The MAX4983 mux routes the data lines to SMB349 rather than the Tegra chip when PGOOD polarity is low-active and DCIN is 5V. Change PGOOD not to invert polarity for the devices that has 5V to upstream. Bug 981761 Change-Id: Ic67ec66ce8936d9a9d5d2df7bca2ff7f9c65b147 Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/103526 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-21video: tegra: dc: Change the definitions in display feature table.Kevin Huang
Change-Id: I13f0f7502aea7f43b2ddff12e9664c22a1d9bd21 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/103210 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-05-21arm: thermal: Removed nonTEGRA_THERMAL_SYSFS logicJoshua Primero
All throttling must go through the Linux thermal sysfs framework now. Change-Id: Ia871e0b06e548d5d82211a65979bea52a6c28fb0 Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/103183 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21arm: tegra: thermal: removed TEGRA_THERMAL_SYSFSJoshua Primero
Removed the CONFIG_TEGRA_THERMAL_SYSFS option. Any throttling activities must go through the Linux thermal sysfs framework now via CONFIG_THERMAL. Change-Id: Ibe680d82d3225994e6bebcfe75a0f058e567e35c Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/103182 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21arm: tegra: xmm: pm qos for modem enumerationVinayak Pane
XMM modem first enumeration has timing requirement, so khubd should perform enum within 1 second. An issue is seen sometimes when the hub events are not sent on time (on fully loaded system) and then khubd timesout. This patch adds PM QOS request to bump up the cpu frequency for 2 seconds. Bug 946027 Change-Id: I1a43c043d42cfa442517a2a7ad8d69a934d4ab47 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/102697 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-21arm: tegra: xmm: simultaneous L3 to L0 wakeupVinayak Pane
In AP initiated L3->L0 wakeup xmm power state is set BBXMM_PS_L3TOL0 but if CP is also trying to wakeup then ipc_ap_wake_irq with falling edge treats it incorrectly as CP wakeup pending - new race condition. Adding a check to fix this scenario for both L3 and L3TOL0 states. Bug 966077 Change-Id: I3af3538b48745588f17e4c13a3e23e4033f21821 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/102698 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Steve Lin <stlin@nvidia.com>
2012-05-21video: tegra: dc: Init hdmi's platform data and fbShashank Sharma
1. Change hdmi platform data structure's xres and yres values. These values were made same as LVDS panel (1366x768). LVDS runs fix display mode,but HDMI can switch to different modes. The new values (640x480) are corresponding to HDMI's fallback mode resolution. 2. Map bootloader's framebuffer content to fb1 also, to initialize fb1's content, and to avoid black & white strips when hdmi gets enabled but has no content in fb. It sometimes causes inconsistency on fb_console mapped on HDMI. Bug: 930136 Change-Id: Iecf0d8c1cdd6a1baec2aec9c5dded3d73d1347e1 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/103381 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-05-18ARM: tegra: pcie: Fix for second pcie port detection.Manoj Chourasia
PCIE card on second port doesn't get detected if the first port is empty. If the link for first port is reset and the second port is queried for card, it doesn't get detected. Fix for the issue is do not reset the link if the port is not detected in third attempt. bug 970206 Change-Id: I4e4d32c22697b817381834ac746417437016d7f3 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/101986 (cherry picked from commit c085f6b1b3a77b7aae3b04e22c7a9bfed8517c1e) Reviewed-on: http://git-master/r/103077 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-18ARM: tegra: cardhu: add initial A07 supportRay Poudrier
Bug 970890 Change-Id: I24c3b1e2c621afbb90ced552194403f147e20a6c Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/102984 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-18arm: tegra: nvmap: remove nvmap.h from mach-tegra/include.Krishna Reddy
It is moved to kernel/include. Bug 854182 Change-Id: I3fb729c88e29a9f213656fbf20810c10dfd9d7a6 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/102727 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2012-05-18spi: tegra: correct directions when syncing buffer for device/dma.Laxman Dewangan
The Tx buffer to be synced with the direction of DMA_TO_DEVICE and Rx buffer should be synced with direction of DMA_FROM_DEVICE. bug 959947 Change-Id: I490a93e05723e3114c8ae3c640bb7eff23bcc75d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/103095 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-18i2c: tegra: Fix i2c unknown interrupt issueKen Chang
writes to modules on APB bus may complete out-of-order. need to guarantee that the write is completed by reading it back. read I2C_INT_STATUS back right after writing the current int status in the isr to make sure the clear operation of I2C_INT_STATUS is done before the interrupt is re-enabled. the same also done for DVC_STATUS. bug 980763 Change-Id: I34f18804d530ccadf561fe1736552b6a4dd6e4ce Signed-off-by: Ken Chang <kenc@nvidia.com> Reviewed-on: http://git-master/r/101925 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-18spi: tegra: register interrupt as ONESHOTLaxman Dewangan
The Tegra spi's engine is design as it generates interrupt when any error occurs and it keep transferring data. It does not stop the engine once error occurred and interrupt generated. This may cause reentry of ISR as on error case, isr get called where it clears interrupt and because it is still in progress, it again interrupts and schedule the thread. The second time scheduling of the isr/thread can cause the issue in queue management and sw state. So Making the interrupt as ONESHOT so that the interrupt will not get schedule until the engine is reset in error case. Change-Id: I96daaf50102aede93164c82b7f6da235d0a7fbfc Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/101547 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com> Tested-by: Jui Chang Kuo <jckuo@nvidia.com>
2012-05-18ARM: tegra: cardhu: add pm267 to kbc int keysRay Poudrier
Bug 896071 Change-Id: I1bcd8069bfccdd80a1506e71bb9cc0353b9ea9a6 Conflicts: arch/arm/mach-tegra/board-cardhu-kbc.c Change-Id: I29af7c5289ae06757eb9cffce3065db08b3e8d06 Reviewed-on: http://git-master/r/97734 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-18tegra: usb: host: dma buffer sync while mappingVinayak Pane
Implementing dma_sync_* functions for usb transfer buffers when DMA is being used by ehci-hcd. Bug 953885 Change-Id: Ia772138752e3fe03bb45ee983dffa1b5d8d620f5 Signed-off-by: Vinayak Pane <vpane@nvidia.com> Reviewed-on: http://git-master/r/102687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-20 19:00:16 +0000