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2013-01-28ENGR00241582 MX6 USB host: USB host certification patchmake shi
The patch include: - USB test mode on hub port and Root-hub port - support 3 types of message: too much hub ties for hub attachment too much power consumption for device attachment unsupported device class warning - support menuconfig select the FSL_USB_TEST_MODE, located in: -> Device Drivers -> USB support (USB_SUPPORT [=y]) -> FSL High-speed Electrical Test Mode support Signed-off-by: make shi <b15407@freescale.com>
2013-01-28ENGR00241003-2 pfuze: using _sel interface to add delay supportAnson Huang
use regulator _sel interface set to support auto delay, as when regulator's voltage go up, it will take some time to ramp up to the required voltage, so the delay is necessary. _sel interface set support such function, now we switch to this interface set. Signed-off-by: Anson Huang <b20788@freescale.com>
2013-01-28ENGR00241003-1 mx6: need to add delay in LDO voltage settingAnson Huang
1.LDO ramp up time may be modified by ROM code according to fuse setting, cpu freq driver use fixed delay time which assume the LDO ramp up time is the reset value of ANATOP register, need to set it to reset value in regulator init. 2.The regulator set voltage should take care of the ramp up time, calculate the ramp up time based of register setting and to the delay, make sure that when the set voltage function return, the voltage is stable enough. 3.CPUFreq no need to use delay, it is already taken care by regulator voltage setting. Signed-off-by: Anson Huang <b20788@freescale.com>
2013-01-25ENGR00240988-12 Enable GPU hardware reset for 3.5 kernelLoren HUANG
Cherry-pick from imx_3.5.7 branch. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Lily Zhang
2013-01-25ENGR00240988-10 Add runtime pm function call in gpu driverLoren HUANG
Cherry-pick from imx_3.5.7 branch. -Add runtime pm function. -Set bus frequency to high when gpu power is on. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Lily Zhang
2013-01-25ENGR00240988-5 Update gpu code to support 3.5 kernelLoren HUANG
Cherry-pick from imx_3.5.7 branch. -Comment regulator setting code temperarily for 3.5 kernel. -Adjust clock setting code based on new clock framework. -Disable dynamic frequency change feature as it depends on thermal driver. -Use DTS to get reserved memory information. -Comment cpu check code for 3.5 kernel. -Comment GPU reset code for 3.5 kernel. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Lily Zhang
2013-01-23ENGR00240972-3 V4L2: VDI double frame rate for interlace streamWayne Zou
Each VPU decoded frame is de-interlaced twice inside v4l2 output driver, and show twice also to achieve IPU/VDI double frame rate output. This feature is disable by default. Signed-off-by: Wayne Zou <b36644@freescale.com>
2013-01-23ENGR00240972-2 IPU: Add vdic double frame rate featureWayne Zou
Add vdic double frame rate feature It depends on the which frame(0 or 1), and interlace field format(top or bottom) to do VDI process Signed-off-by: Wayne Zou <b36644@freescale.com>
2013-01-23ENGR00240972-1 IPU: Add deinterlace frame rate double flagsWayne Zou
Add deinterlace frame rate double flags for ipu header file Signed-off-by: Wayne Zou <b36644@freescale.com>
2013-01-21ENGR00240990 MX6 HDMI dongle:Configure HDMI PHY registersLiu Ying
This patch sets HDMI PHY register values in MXC HDMI driver platform data so that MXC HDMI driver can configure the 0x09 CKSYMTXCTRL register(Clock Symbol and Transmitter Control Register) and 0x0E VLEVCTRL register(Voltage Level Control Register), then we may pass HDMI compliance test for MX6 HDMI dongle board. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 788bcf52a2e4c37dc42e9605d31995f8dd80d674)
2013-01-21ENGR00240740-3 IPUv3 fb:Workaround bootup ipu errorLiu Ying
Enabling IPU hsp clock in mxcfb_probe() context by calling ipu_init_channel() can avoid the IPU display channel(setup in bootloader) from being damaged by some IPU common driver APIS which enable/disable IPU hsp clock when doing driver probe. However, somehow, after LDO bypass patch set is pushed to kernel, this clock enablement can trigger IPU errors (IPU_INT_STAT_5 - 0x00800000/IPU_INT_STAT_10 - 0x00100000) and a display flash. A workaround is to enable IPU hsp clock when we are at ipu_probe() context, which is earlier than mxcfb_probe() context, and then to disable(cleanup) the clock once more when fb_set_par() is triggered by the user for the first time. This patch updates the comment for ipu_init_channel() and ipu_enable_channel() in mxcfb_probe() context, and disables ipu hsp clock when fb_set_par() is triggered by the user for the first time. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 5528e415659a60f3c6d67db96692befb3302a58a)
2013-01-21ENGR00240740-2 ARM:IPUv3:Add an interface to disable IPU hsp clkLiu Ying
This patch adds an interface to disable IPU hsp clock so that it can be called out of ipu common driver. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 78f0495e79f3b18d3f56ac8bf6ca76a5cea91cf5)
2013-01-21ENGR00240740-1 IPUv3:Workaround bootup ipu errorLiu Ying
Enabling IPU hsp clock in mxcfb_probe() context by calling ipu_init_channel() can avoid the IPU display channel(setup in bootloader) from being damaged by some IPU common driver APIS which enable/disable IPU hsp clock when doing driver probe. However, somehow, after LDO bypass patch set is pushed to kernel, this clock enablement can trigger IPU errors (IPU_INT_STAT_5 - 0x00800000/IPU_INT_STAT_10 - 0x00100000) and a display flash. A workaround is to enable IPU hsp clock when we are at ipu_probe() context, which is earlier than mxcfb_probe() context, and then to disable(cleanup) the clock once more when fb_set_par() is triggered by the user for the first time. This patch exports an interface to disable ipu hsp clock so that fb_set_par() may call it, and enables ipu hsp clock in ipu_probe() context. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 06e5772151c3b8e060110fbb2b1ce83ef6be70dd)
2013-01-18ENGR00240228: IPUv3: CSI: Correct enum definition of IPU_CSI_DATA_WIDTHSheng Nan
The current definition for with 10 and 16 is not correct. IPU_CSI_DATA_WIDTH_10 = 2; IPU_CSI_DATA_WIDTH_16 = 3; According to the latest i.MX6DQ RM, the correct value should be: IPU_CSI_DATA_WIDTH_10 = 3; IPU_CSI_DATA_WIDTH_16 = 9; Signed-off-by: Sheng Nan <b38800@freescale.com>
2013-01-18ENGR00240650 pcie: imx: fix ep device no int when pcie switch is usedRichard Zhu
The pcie ep device inserted into the downstream port of the pcie switch doesn't get the legacy INT when pcie switch is used. Signed-off-by: Richard Zhu <r65037@freescale.com>
2013-01-18ENGR00239734 Mx6 HDMI PHY: Add 2 variable to pass board specific configSandor Yu
The PHY register 0x9 and 0xe should setting to different value in different board to pass HCT. Add variable phy_reg_vlev and phy_reg_cksymtx to pass phy config data. Signed-off-by: Sandor Yu <R01008@freescale.com>
2013-01-17ENGR00240571 mtd: gpmi: fix the compiler warningHuang Shijie
The current code may print out the following warning: .................................................................... drivers/mtd/nand/gpmi-nand/gpmi-lib.c: In function gpmi_begin: drivers/mtd/nand/gpmi-nand/gpmi-lib.c:1163: warning: hw.use_half_periods may be used uninitialized in this function drivers/mtd/nand/gpmi-nand/gpmi-lib.c:1163: warning: hw.sample_delay_factor may be used uninitialized in this function .................................................................... this patch fixes it. Signed-off-by: Huang Shijie <b32955@freescale.com>
2013-01-17ENGR00240298 IMX IPU: Optimize IPU resize performanceWayne Zou
When disabling IPU channels, it needs less than 200us to wait for stop Using msleep, it often sleep longer(above 10ms). So the extra delay decrease the performance. For 720p video playback on 1080p display(60Hz), the performance is about 40fps With this patch, it can achieve around 60fps. Signed-off-by: Wayne Zou <b36644@freescale.com>
2013-01-17ENGR00240506 fix a bug in abnormal abort handlingHongzhang Yang
Bug: If app quits before FW is loaded to VPU, VPU driver will hang in vpu_release(). Root cause: In that case, if BIT_BUSY_FLAG=1, vpu_release may reset VPU and run FW init code, but FW has not been loaded. Solution: - Don't run FW init code after reset since VPU lib can load it next time. - If PC=0, which means VPU never runs, don't check BIT_BUSY_FLAG Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
2013-01-14ENGR00239905 PCIe Enable PCIe switch supportRichard Zhu
PCIe switch access mechanism: - CfgRd0/CfgWr0 is used to access the CFG space of the EP device or the upstream port of PCIe switch that is connected to RC directly. - CfgRd1/CfgWr1 is used to access the CFG space of the downstream port of PCIe switch and so on cases. UR and kernel crash problem: i.MX6 PCIe maps UR(Unsupported Request)err to AXI SLVERR err, which would cause the arm data abort exception. There is one "Received Master Abort" in iMX6 Root complex Secondary status register when a requester receives a Completion with Unsupported Request Completion Status. In this case, the Linux kernel would be crashed. Workaround: correct this imprecise external abort. Signed-off-by: Richard Zhu <r65037@freescale.com>
2013-01-11ENGR00239569 Mx6x HDMI Add RGB/YCbCr output select via system fileSandor Yu
Add RGB/YCbCr output select via system file, the default output is RGB. Signed-off-by: Sandor Yu <R01008@freescale.com>
2013-01-11ENGR00239207 MX6x HDMI add some support modesSandor Yu
Remove video mode 2880x480p60 that not supported by IPU. Add video mode 1080p25, 1080p30, 720p100, 720p120, 1440x480p60, 1440x288p50, 1440x576p50. Signed-off-by: Sandor Yu <R01008@freescale.com>
2013-01-11ENGR00232755 USB: disable clock and abnormal wakeup when remove gadget drivermake shi
- In current bsp, the usb clock mismatch when rmmod gadget class driver. The clock should be turn off when gadget class driver unregister. - There is an abnormal usb wakeup interrupt happen if phy is no power without VBUS. If we unplug the usb cable after unregister usb gadget driver, it is difficult to handle the unexpected usb wakeup interrupt. SO we must call dr_discharge_line() to make sure no abnormal usb wakeup interrupt happen in usb unregister gadget class driver. Signed-off-by: make shi <b15407@freescale.com>
2013-01-09ENGR00237682-3: mxc_v4l2_capture: ov5640: support scaling modesSheng Nan
The method for change between scaling and subsampling mode is different from ov5640_mipi. (image bigger than 1280*960 is scaling mode, smaller is subsampling). According to OV5640 Auto Focus Camera Module Application Notes (with DVP Interface) R2.14.pdf, change back from QSXGA to VGA, don't need to do exposure calculation. According to the test result, if we do exposure calculation when change back from scaling to subsampling mode, the image would be dark. So the method is: Change to scaling mode, go through exposure calcuation. Change to or back to subsampling mode, change mode directly. Supported mode: - QSXGA@7.5fps - 1080P@7.5fps Can't make 1080P works at 15fps. Here is a reply from ov fae: because of scaling down, max frame for 1080P is the same as 5M, both are 15fps. so if 5M can runs up to 7.5fps on your demo, then 1080P is the same 7.5fps max. Signed-off-by: Sheng Nan <b38800@freescale.com>
2013-01-09ENGR00237682-2: mxc_v4l2_capture: ov5640: support all subsampling modesSheng Nan
Supported the following modes, verified image quality and frame rate - VGA 30/15fps - QVGA 30/15fps - NTSC 30/15fps - PAL 30/15fps - 720P 30/15fps Note: use the same setting as app note of ov5640 dvp - QCIF 30/15fps - XGA 22.5/15fps Note: cannot make XGA work on 30fps. Just a reference of ov5640 datasheet: 1280*960 YUV422 maximum at 22.5fps. 1280*720 YUV422 maximum at 30fps. Need to confirm later. Signed-off-by: Sheng Nan <b38800@freescale.com>
2013-01-09ENGR00237706: mxc_v4l2_capture: ov5640: correct the behavior of ENUM_FMTSheng Nan
ov5640 ioctl_enum_fmt_cap only returns value of index = 0; before support other formats, correct the behavior of this ioctl. - ENUM_FMT returns all the supported format. Signed-off-by: Sheng Nan <b38800@freescale.com>
2013-01-09ENGR00237682-1: mxc_v4l2_capture: ov5640: use global initializationSheng Nan
The current code struct of parallel ov5640 set mode directly. The newest settings need to go through global initialization. New settings are provided by ov company So this patch does: - Make parallel ov5640 mode settings go through global initialization. - Only VGA (640 * 480) are provided as a validation of the new setting. - Other modes will be provided in the later patches. Signed-off-by: Sheng Nan <b38800@freescale.com>
2013-01-08ENGR00237364: board-mx6q_sabreauto fix adv7180 tvin powerdownAdrian Alonso
* Fix adv7180 tvin powerdown function gpio power pin already exported in io-mux setup function no need to request/free gpio * Update copyrigth year 2013. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2013-01-08fix echo 1 > compact_memory return error issueJason Liu
when run the folloing command under shell, it will return error sh/$ echo 1 > /proc/sys/vm/compact_memory sh/$ sh: write error: Bad address After strace, I found the following log: ... write(1, "1\n", 2) = 3 write(1, "", 4294967295) = -1 EFAULT (Bad address) write(2, "echo: write error: Bad address\n", 31echo: write error: Bad address ) = 31 This tells system return 3(COMPACT_COMPLETE) after write data to compact_memory. The fix is to make the system just return 0 instead 3(COMPACT_COMPLETE) from sysctl_compaction_handler after compaction_nodes finished. Signed-off-by: Jason Liu <r64343@freescale.com> Suggested-by: David Rientjes <rientjes@google.com> Cc: Mel Gorman <mgorman@suse.de> Cc: Rik van Riel <riel@redhat.com> Cc: Minchan Kim <minchan@kernel.org> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2013-01-08ENGR00232879 mx6sl: EPDC VDDH and VPOS power on/off sequence is wrongPeter Chan
VDDH should only be ON after VPOS when power up and should be off before VPOS when power down. Set the appropriate MAX17135 timing parameters for the correct power up/down sequence Signed-off-by: Peter Chan <B18700@freescale.com>
2013-01-08ENGR00239062 MX6X HDMI add 1440x240p60 mode supportSandor Yu
Adjust 1440x240p60 timing to pass HDMI compliance test. Signed-off-by: Sandor Yu <R01008@freescale.com>
2013-01-08ENGR00239187 input: novatek_ts: fix some point not release issue.Zhang Jiejing
This issue is caused by Touch Screen F/W, and it will report a full package with 0xFF * 6 to notice the point was release. Add this workaround to fix this issue, fixup the wrong finger id. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2013-01-08ENGR00238813 ASRC: add check before release ASRC pairChen Liangjun
Add check before relase ASRC pair to prevent ASRC register operation while clock is not enabled. The ASRC clock is disable while index is not applied. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2013-01-06ENGR00238237-2 mx6sl: csi/v4l: Initialize the variable cam_fmtRobby Cai
This patch fixed the cam_fmt uninitialization issue. Signed-off-by: LiGang <b41990@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit 48a48ea30c6e55e44c9eacaad316b5caa04a3dda)
2013-01-06ENGR00238237-1 mx6sl: csi/v4l: fix camera picture flickering issueRobby Cai
Flickering issue happens when there's no buffer to be processed(e.g., the pace of QBUF is much slower than DQBUF). The cause is the hardware is using double buffering, while the driver has no good protection at above case and thus the CSI will fill the buffer not in the right order. The way to fix is refining the output of the working_q buffer list, that is, if there's no buffer to be processed then output to a dummy buffer. Another important change is to only do DMA reflash operation when SOF is detected in streamon. Remove this operation is CSI interrupt handler because it violates to the SPEC (only do DMA reflash before DMA is enabled but NOT at the time or after DMA's enabled). Signed-off-by: LiGang <b41990@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit 0c4584763fa44b01a2f48198fa27c9206a116164)
2013-01-05ENGR00238947 [GPU]Integrate Vivante 4.6.9p10 gpu driver kernel part codeLoren Huang
Integrate both 4.6.9p9.1 and 4.6.9p10. Signed-off-by: Loren Huang <b02279@freescale.com> Acked-by: Lily Zhang
2013-01-05ENGR00238943 wm8962: add judgement for no det_pin caseGary Zhang
add judgement to avoid no detect pin case Signed-off-by: Gary Zhang <b13634@freescale.com>
2013-01-05ENGR00238307 MX6SL_EVK bluetooth: Add support to Silex SXSDMAN moduleLionel Xu
mx6sl_evk board uses Silex SXSDMAN board for bluetooth, add uart4 driver to support it. Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
2013-01-05ENGR00238281 MX6SL_EVK: Add rfkill interface to bluetoothLionel Xu
MX6SL EVK board uses Silex SX-SDMAN board for bluetooth. Add rfkill interface to control SX-SDMAN reset. The reset signal is required before using bluetooth. Signed-off-by: Lionel Xu <R63889@freescale.com>
2013-01-05ENGR00238809-2 mx6sl: ssi: add IRAM supportGary Zhang
locate SSI playback buffer into IRAM in mx6sl. because left IRAM room is not enough to contain record buffer, if IRAM allocation for record fails, record buffer will use external ram Signed-off-by: Gary Zhang <b13634@freescale.com>
2013-01-04ENGR00238809-1 mx6sl: clock: add dependency of IRAM clkGary Zhang
when IRAM is used by SSI, add IRAM clock dependency to SSI clock Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-12-28ENGR00238439 ASRC: add delay before reading ASRC FIFO statusChen Liangjun
ASRC driver would read the sample number of ASRC output FIFO to fetch the data from ASRC output FIFO. However, SDMA's fetching operation may not finished before ASRC's reading. In this case, ASRC driver may read a error data from the register. In this patch, add delay before reading ASRC FIFO status to prevent noise. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-12-27ENGR00238391 MX6x HDMI: Add default EDID config function when read EDID failedSandor Yu
Add default EDID config function when read EDID failed. Fix HDMI no audio issue when failed read EDID. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-12-27ENGR00238384 MX6x HDMI: Update HDMI setting when HDMI cable pluginSandor Yu
Update HDMI setting when HDMI cable plugin, HDMI will catch capbility update with EDID data updated. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-12-27ENGR00238382 MX6 HDMI: Change VGA mode flag, adjust default modelist sequencySandor Yu
- Change VGA mode the flag from unknow to VESA. - Adjust default modelist order, put the VESA to the end of modelist. - Fix a build warning. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-12-27ENGR00238357 MX6x Change HDMI default output RGBSandor Yu
Change HDMI default output RGB Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-12-26ENGR00238201-2 V4L2:ADV7180:driver kconfig changeguoyin.chen
Move ADV7180 out of choice to make it be enabled with other camera config simultaneously Signed-off-by: guoyin.chen <guoyin.chen@freescale.com> (cherry picked from commit a6becd9a87da4fe0bdcc0e96d690377078c856b9)
2012-12-26ENGR00238201-1 V4L2:ADV7180:Support ioctrl_enum_framesizesguoyin.chen
Add ioctl_enum_framesizes function to align the requirement of Camera HAL in Android Signed-off-by: guoyin.chen <guoyin.chen@freescale.com> (cherry picked from commit fd0a1be3e55c3ca5b16f5bf89a24c62b1f3f3abe)
2012-12-26ENGR00236141 csi:Add stride alignment setting from userspaceguoyin.chen
In android, IPU fills the I420 buffer. And GPU shows the buffer to display. mx6's GPU has 32 Y-stride alignment for I420. The stride alignment will be passed through by bytesperline. This update is only for csi->smfc->mem channel. Signed-off-by: guoyin.chen <guoyin.chen@freescale.com> (cherry picked from commit 4708dc1999ed4857799100434e4f46f68f4e7c13)
2012-12-21ENGR00237742 busfreq:fix IPG_PERCLK will be decreased to 6M once exit low busRobin Gong
on Sabresd board, IPG_PERCLK will be fixed on 6Mhz once system enter low bus, and never restore to 22Mhz which be set in boot. It means some device clock which sourcing from IPG_PERCLK such as I2C will be slow down. The root cause is that there is workaround for GPT timer of Arik TO1.0 in mx6_ddr_freq.S. GPT clock source from IPG_PERCLK on TO1.0 and should be fixed on 6Mhz. But for TO1.1 and TO1.2 ,the workaround should be removed. Signed-off-by: Robin Gong <B38343@freescale.com>
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