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Porting some changes from pxp-v2 driver to fix some bugs
which have already been fixed in v2 driver.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
(cherry picked from commit 22ae3b63eca3913ce0fb524e383cd2ca1d36a23e)
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sii902x HDMI display is the prime display for imx7d SDB.
so move all sii902x property to imx7d-sdb.dts and
remove imx7d-sdb-hdmi.dts file.
Please make sure imx7D sdb board have added 2.2k pull-up
resistor on the HDMI_I2CSDA and HDMI_I2CSCL signals.
Otherwise kernel will hang at bootup.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit e3f86f31a04f36c750fd939d907540f2e4f849bf)
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Enable wdog1 as default watchdog device since on all boards we use wdog1.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit d254198e5101b3e9e74dd6b147d77b9546b2f52c)
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currently we set burst length from 8 to 16 in our usdhc driver, but
we find if the burst length is 16, the SD3.0 performance on
i.MX6Q-sabreauto and i.MX6QP-sabreauto board will drop a lot.
for TOSHIBA 16GB SDR104 card,
if burst length is 16, the peformance on these two boards is:
read: 19.4MB/s, write: 13.2MB/s
when burst length is 8, the performance on these two boards is:
read: 63MB/s, write: 25.4MB/s
other boards like i.MX6sl-evk, i.MX6sx-sdb and i.MX7D-12x12-arm2
has no this issue.
The root cause still not find on these two boards. So this patch
just change the burst length to 16 for i.MX7d, all i.MX6 series
will remain 8.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
(cherry picked from commit bcb043082c14a65098a167624448715bbffa4a70)
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Rather than using the streaming API, use the coherent allocator to
provide this memory, thereby eliminating cache flushing of it each
time we map and unmap it. This results in a 7.5% increase in
transfer speed with a UHS-1 card operating in 3.3v mode at a clock
of 49.5MHz.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Markus Pargmann <mpa@pengutronix.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit d1e49f77d7c7b75fdc022e1d46c1549bbc91c5b7)
(cherry picked from commit 71b9094aa4598818f4d866c823e2815052e4a9e0)
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At the end of playback and before power down, write i2c will failed.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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According to the RM of wm8958, BCLK DIV 348 doesn't exist, correct it
to 384.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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wm8958 codec support list below:
playback 16 bit: 8k, 11.025k, 16k, 22.050k, 32k, 44k, 48k, 88.2k, 96k.
playback 24 bit: 8k, 11.025k, 16k, 22.050k, 32k, 44k, 48k.
capture 16 bit: 8k, 11.025k, 16k, 22.050k, 32k, 44k, 48k.
capture 24 bit: 8k, 11.025k, 16k, 22.050k, 32k.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Revert "MLK-10539-2: ARM: clk_imx7d: add audio_post_div clock to init list"
As the clock tree has been refined, then imx7d_pll_audio_post_div needn't be
added to init_on structure.
This reverts commit 0ac3187a47594a87c784003371db4c0ea8ab2eaa.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Introduced new imx clk APIs like imx_clk_divider2 which has flag
CLK_SET_PARENT_ON for imx7d.
PLL/PFDs does not need this flag.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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parent on
On Freescale i.MX7D platform, all clocks operations, including enable/disable,
rate change and re-parent, requires its parent clock on.
Current clock core can not support it well.
This patch introduce a new flag CLK_SET_PARENT_ON to handle this special case
in clock core that enable its parent clock firstly for each operation and disable
it later after operation complete.
The most special case is for set_parent() operation which requires both parent,
old one and new one, to be enabled at the same time during the operation.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Fix the warning by dynamically allocating the buffer for 'pxp_conf'.
drivers/dma/pxp/pxp_device.c: In function 'pxp_ioc_config_chan':
drivers/dma/pxp/pxp_device.c:487:1: warning: the frame size of 1264 bytes is larger than 1024 bytes [-Wframe-larger-than=]
Signed-off-by: Robby Cai <r63905@freescale.com>
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- a7 linux would be hang at adc/flexcan probe when
m4 is kicked off.
- setup standalone dts to handle this situation.
- move the mcc support to m4 dts
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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Random hang may occur if module clock gating is enabled for TX module,
The software workaround is to disable clock gating for the TX module
Date: Apr 01, 2015
Signed-off-by: Xianzhong <b07117@freescale.com>
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Add a new entry for MX25L51245G QSPI NOR chip.
Signed-off-by: Han Xu <b45815@freescale.com>
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Add a new dts file for QSPI on i.MX7D SDB, also changed dtb file order
to alphabetical order.
Signed-off-by: Han Xu <b45815@freescale.com>
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rate for 24 bit word length
change AIF1CLK to 384fs to get accurate sample rate for 24 bit word length.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Add sii902x hdmi sound card.
Set clk IMX7D_PLL_AUDIO_POST_DIV to 884736000HZ.
Set clk IMX7D_SAI1_ROOT_SRC parent to IMX7D_PLL_AUDIO_POST_DIV.
Set clk IMX7D_SAI1_ROOT_CLK to 18432000HZ.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Add machine driver for sii902x hdmi audio. Restricting by SAI master clock,
the hdmi audio just support 16bit 24bit sample width and 32k 48k sample rate.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Set tdm slot in hw_params() for sai master mode.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Add tdm slot operation for SAI master mode. When using SAI as master
mode, we should use set_tdm_slot() helper function to set tdm slots in
machine driver.
SAI will generate BCLK depends on sample rate, slots and slot width.
And there may be unused BCLK cycles before each LRCLK transition.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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wm8958 can't support dac sample rate 64kHZ, so add a constraint
list for it.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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change coding style for wm8960 machine driver.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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When uart port (non-console port) in dma mode and use uart as remote wakeup
source, after resume back, the AWAKE bit is not cleared most of interrupts
are disabled. And then let system suspend state, system resume back immediately
without any wake up action. So we need to clear the AWAKE bit after resume
back in DMA mode.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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The previous commit e8e43b960723f0cae129327f392761a57269bcc9 has
disabled PRG2 by accident. This patch restored it.
Signed-off-by: Robby Cai <r63905@freescale.com>
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it's useful to enable/disable it by just using the label.
Signed-off-by: Robby Cai <r63905@freescale.com>
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This pinmux group is also used by EPDC. Thus need to move from hoggroup,
and only set in probe function of its driver. sii902x is already disabled
by default to avoid the conflict, and only enabled in *-hdmi.dts file.
Signed-off-by: Robby Cai <r63905@freescale.com>
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This pinmux group is also used by ENET. Thus need to move from hoggroup,
and only set in probe function of its driver. MAX17135 is disabled by default
to avoid the conflict, and only enabled in *-epdc.dts file.
Signed-off-by: Robby Cai <r63905@freescale.com>
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DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.
There is a test_div placed before DRAM PLL's gate, so
add this test div clk.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The audio/video PLL's rate caculation is as below in RM:
Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's
code, below code is used:
(parent_rate * div) + ((parent_rate / mfd) * mfn
as it does NOT consider the float data using div, so below
formula should be used as a decent method:
(parent_rate * div) + ((parent_rate * mfn) / mfd)
and we also need to consider parent_rate * mfd may overflow
a 32 bit value, 64 bit value should be used.
After updating this formula, the dram PLL's rate is
1066MHz, which is correct, while the old formula gets
1056MHz.
Signed-off-by: Anson Huang <b20788@freescale.com>
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imx7d IMX7D_LCDIF_PIXEL_ROOT_SRC clk parent can not changed,
The issue is caused by register IMX7D_LCDIF_PIXEL_ROOT_SRC clk with
anatop base address, that address is different with CCM address.
Move IMX7D_LCDIF_PIXEL_ROOT_SRC clk register function to CCM
base address section to fix the issue.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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The mipi dsi dphy reference clock initialization is not
correct. So correct it.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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There is only one channel input in hardware connection. Route it to right
channel, then all 2 channel has sound.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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- refine the print info format, to make alignment with
m4 side.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- enable sema4 on imx7d, and verified on imx7d mcc
pingpong tests.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- use dsb() to make sure the consistence of the share
memory , because that share memory is located in ddr memory,
it maybe buffer-able although it is remapped as nocache
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- enable imx7d mu root clock ehen mu is enabled
- remove the mu trigger bit double check, when trigger
the cpu2cpu int. Because that mcc stack can handle
multi-int in one isr process.
- waiting for the ep bit clear after cpu2cpu int is triggered.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- add mu sema4 device nodes on imx7d dts
- add mcc pingpong/tty tests nodes on imx7d dts
- enable mcc test on imx7d
- specify the top 1MB of the 1GB DDR as mcc share memory
- add 7d sema/mu root clocks
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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- add imx7d sema4 and mu root clocks
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
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When playback Mono stream using "aplay -Dhw:0", there will be some noise
on the right channal. We found that the SAI TX DATA pin will auto pull
up or down on the right channel, and have hysteresis phenomenon. When
disable the pull function, no noise appear.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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wm8958 doesn't support ADC sample rate 88.2k and 96k, so add a
constraint list for capture.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Clear R1568 ADC_OSR128 bit to support slower SYSCLK. And it will support
ADC sample rate 8K, 11.025K and 12K.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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It is too early to put clk get rate in probe, because the rate for
the clock may not be ready.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Add imx7d-12x12-arm2-mqs device tree for mqs
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Add audio_post_div clock to init list
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Add SAI_IPG clock for sai2, sai3
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Add clk divider for i.MX7D AUDIO/VIDEO PLL, there are two
diviers for audio pll, one is test_div and the other
is post div, per design team's saying, test_div is
placed before PLL gate and post div is placed after
PLL gate.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add power lost check implementation for i.MX7D.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <jun.li@freescale.com>
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Update mf-mix-wakeup-irq to include irq of USB OTG1 and OTG2.
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Li Jun <jun.li@freescale.com>
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