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2012-05-15video: tegra: dc: correct dc initialisation sequencePritesh Raithatha
-Move _tegra_dc_enable to before irq_request and remove disable_dc_irq. -It will remove warning of "IRQ when DC not powered!". Bug 955184 Change-Id: If9b039f3f1635d92f10bfc54af08101972fc3d57 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/101498 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-15asoc:codecs: tiaic326x: remove mini dsp supportNikesh Oswal
disable the compilation of minidsp specific code, we are disabling the minidsp in codec because the driver is not stable and different customers are using different process flows for mini dsp Change-Id: I08f8f485f1a379773f2f1f7ae2fd1b3a89c45d07 Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/101232 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-15regulator: TPS6238X0: Add tps6238X0 regulator driverLaxman Dewangan
The regulator module consists of 1 DCDC. The output voltage is configurable and is meant for supply power to the core voltage of Soc. Change-Id: Ic62d100a588f7b6f1b30c11fd44a925c97393069 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100653 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-15video: tegra: dsi: WAR to stop on going host writeAnimesh Kishore
WAR comprises of soft reset dsi controller followed by explicitly clearing host trigger. Bug 982919 Change-Id: Ia8c497dd496435e429cd5b5ee8aaf1b7d78dc797 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/102204 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-15misc: bt rfkill: toggle power GPIO based on current power stateNagarjuna Kristam
check if requested state and current BT power state is same, if yes, do not toggle BT power GPIO's. if not, set requested power state. Bug 982600 Bug 928604 Change-Id: I82c65fd6d43940c86cc3de440295ba179a4ade33 Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-on: http://git-master/r/102190 Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-15ARM: config: tegra: Enable SECTION_MISMATCH warningLaxman Dewangan
Some of our driver generate the section mismatch warning but details of the error is not displayed. Enable config variable to display all such warning during compilation. Change-Id: Ie0a6dc10cc20304b74a7712717adb44a86474247 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/102183 Reviewed-by: Automatic_Commit_Validation_User
2012-05-15rtc: tps6591x: Enable alarm interrupt for RTC_WKALM_SET ioctlPreetham Chandru
RTC_WKALM_SET ioctl should do two things: 1. Set alarm value 2. Enable alarm irq In the current implementation for RTC_WKALM_SET ioctl we are only setting the alarm value but not enabling the alarm irq and hence the system is not waking from lp0 state once the set alarm value expiries. For RTC_WKALM_SET ioctl, alarm->enabled will be set to one from userspace. So based on this condition we can differentiate between RTC_WKALM_SET & RTC_ALM_SET and accordingly enable alarm irq. Bug 978205 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: Ia35192e691ca116b13093f52873020f67c5c2f8d Reviewed-on: http://git-master/r/101447 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-05-15mmc: enable background ops in driverVishal Singh
Adding a new config option and enabling background ops in driver. Correcting the EXT_CSD byte that needs to be written in order to trigger background ops in the MMC firmware. Bug 847037. Change-Id: Ibc517540cab43fa5070b142a416f6b67f2f7e7be Signed-off-by: Vishal Singh <vissingh@nvidia.com> Reviewed-on: http://git-master/r/99117 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-15usb: ehci: tegra: Split resume & suspend call appropriatelyPreetham Chandru
tegra_ehci_suspend_noirq/tegra_ehci_resume_noirq breaks the modem suspend call as it does a regulator_disable()/regulator_enable call which in turn requires the irqs to be enabled. Hence maintain a normal suspend call i.e with irqs enabled but split the resume to normal resume and noirq resume. Spliting the resume in this way takes care of the below erros in lp0/lp1 "tegra-ehci tegra-ehci.2:fatal error" "tegra-ehci tegra-ehci.2: HC died; cleaning up" Originally resume_noirq & suspend_noirq were added to avoid the above errors but since it breaks the modem suspend call splitting the suspend and resume in this way Bug 954564 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I630b3dbe2ca66d194857dc71ababa3e5955785b1 Reviewed-on: http://git-master/r/99100 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-14asoc: tegra: MAX98088 machine: Add support for setting bias levelAnkit Gupta
Allow setting bias level to turn off clock extern1 when codec is idle for enterprise board. (Maxim 98088 codec) Bug 984678 Change-Id: Ib01be71362ab0c5525f570693b41db73777875e6 Signed-off-by: Ankit Gupta <ankitgupta@nvidia.com> Reviewed-on: http://git-master/r/102240 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-05-14asoc:tegra: Enable I2S tx in voice callNikesh Oswal
Associated with I2S there is a playback ref count, when we open the I2S for plyabck it is incremented and during voice call we check if its not zero then enable the tX. This logic fails if the start-trigger is not called for the prior playback stream. Hence we unconditionally enable the tx, which is harmless Bug: 981806 Change-Id: I66aafda596e2b2b03745e93f3e851dedc3b8ef5d Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/101996 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-05-14ARM: tegra: cardhu: wakeup system from GPIO_PV0 without key detectionLaxman Dewangan
To meet the LP0 exit power on sequence, it is require to wake system for tegra gpio in place of PMIC for E1291-A04. Also it is observed that if GPIO key is used to wakeup then there is possibility of loosing the key event and hence adding the gpio GPIO_PV0 as the key with code of RESERVED so that it can only wakeup system but will not able to send the key event through gpio keys. bug 981320 Change-Id: I8610adca4b5ed8ae79f8fcca9a1d4b5548158c60 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/101784 Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-05-14ARM: tegra: pm: suspend trace eventSivaram Nair
A new trace event is added for tracing cpu suspend start and end Change-Id: I2506e3aed0692c44fb4325e9d381cea53228b0c3 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/101748 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-14asoc: codecs: spdif: Add support for setting bias levelAnkit Gupta
Allow setting bias level to turn off clock extern1 on enterprise when codec is idle. Added a dummy widget to make the target_bias_level to BIAS_OFF as per required by the new ALSA kernel. Bug 984678 Signed-off-by: Ankit Gupta <ankitgupta@nvidia.com> Change-Id: I29de405c26286eee0a49e655f1d4236f6093ce8a Reviewed-on: http://git-master/r/100287 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Tested-by: Ankit Gupta (Engrg-SW) <ankitgupta@nvidia.com>
2012-05-14asoc: tegra: pcm: Add support for setting bias levelAnkit Gupta
Allow setting bias level to turn off clock extern1 when codec is idle for Enterprise (Maxim 98088 codec). Bug 984678 Signed-off-by: Ankit Gupta <ankitgupta@nvidia.com> Change-Id: I09538dafe6c6f01547ff989de3c23933c9745db0 Reviewed-on: http://git-master/r/100286 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com> Tested-by: Ankit Gupta (Engrg-SW) <ankitgupta@nvidia.com>
2012-05-14arm: tegra: p1852: Add Tegra camera driverSonghee Baek
Add Tegra camera driver to support video capture through H/W interfaces VIP, CSI. Bug 978086 Change-Id: I0dc51e47928388ed2073a99f8ca80b5a5a77d166 Signed-off-by: Songhee Baek <sbaek@nvidia.com> Reviewed-on: http://git-master/r/101590 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14ARM: tegra: clock: Export clock minimumAntti P Miettinen
Add clock minimum to debugfs. Bug 917644 Change-Id: Ie088809829af2bdc81a969a034bf00847459f0ce Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/101555 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14arm: tegra: sdhci: Limit eMMC,SDIO,SD DDR clockPavan Kunapuli
Limit eMMC, SD and SDIO DDR mode clock to 41MHz. Bug 967719 Change-Id: Iaccc5b771b81b15226f87684b547ad1fb7dd38d3 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101173 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14arm: tegra: clock: Add tegra3 sdmmc4 EMC shared userPavan Kunapuli
Adding tegra3 sdmmc4 EMC shared user in the tegra3 clock table. Bug 967719 Change-Id: I934dcaebf664f8b1db9ea07eef07eb6f266822aa Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100582 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14mmc: tegra: Set eMMC DDR clock based on emc clockPavan Kunapuli
Set the eMMC ddr mode clock dynamically based on emc clock rate. If ddr clock limit is specified and the emc clock is less than max emc freq, then limit emmc ddr clk. If not, set the max eMMC ddr clock. Bug 967719 Change-Id: I9f70077c4ac4bb1f3e6d894fcb8420b1aba284dd Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100579 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14arm: tegra: sdhci: Define ddr50 clock limitPavan Kunapuli
Added a new variable in sdhci platform data which will limit the ddr50 mode clock. Bug 967719 Change-Id: I3f55b55651362447845c2e1d5000939e3e028df6 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100569 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14drivers: video: tegra: Implement HOST1X syncpt initTerje Bergstrom
Move initialization for HOST1X sync point irq to nvhost driver. Bug 871237 Change-Id: I0d31e03b43999c609194665cdcbd2f0e498d848f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/100250 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-14ARM: tegra: Correction of safe optionAshwini Ghuge
Corrected safe option for LPW0 and LPW2 Bug 920686 Change-Id: I14e1a22de3338ba569d3b381508e123d12aad059 Reviewed-on: http://git-master/r/101973 Tested-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-14arm: tegra: cardhu: add ov5640 supportCharlie Huang
bug 921322 Change-Id: If7f05c632816abac54852293ebd3834b5b3984d8 Signed-off-by: Charlie Huang <chahuang@nvidia.com> Reviewed-on: http://git-master/r/99508 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-14media: video: tegra: ov5640: add supportCharlie Huang
add ov5640 yuv sensor support - initial. bug 921322 Change-Id: I813afa8963e39afe475f9fdd43152cfaf1a16ae1 Signed-off-by: Charlie Huang <chahuang@nvidia.com> Reviewed-on: http://git-master/r/99506 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Frank Chen <frankc@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-05-14asoc: codecs: resolve compilation time warningsSanjay Singh Rawat
Bug 949219 Change-Id: I9c2a0aa22432c586a7e72273ad935d42332e873f Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/95087 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-14ARM: config: tegra3: enable CONFIG_REGULATOR_USERSPACE_CONSUMERLaxman Dewangan
By enabling the user space regulator consumer, it is possible to control the rail from userspace through sysfs. bug 966960 Change-Id: I0f4a7a0afdc998d58e6448e4f621ee4e430a7ef6 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/100320 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-11ARM: tegra: Pinmux conflict correctionAshwini Ghuge
Corrected Mux option for LPW2 Bug 920686 Change-Id: I1e93a28c070ca7689c305d84ed8664c3f170bfcb Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/101959 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-05-11ARM: tegra: Enable TXFILLTUNING for all USB interfacesVenu Byravarasu
As per recommendation from ASIC team, Setting TXFILLTUNNING to 0x10 for all USB interfaces. bug 974507 Change-Id: Id2ee26927e56bf500a0fed2a414b74ffab157403 Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-on: http://git-master/r/99629 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-11arm: enterprise: power: Fix sdmmc3 regulator entryPavan Kunapuli
Register vdio_sdmmc3 supply with a valid device id instead of NULL. Bug 982788 Change-Id: Ie19d8a48b381190e8f966928a785af0f51794cb1 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101971 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-11arm: tegra: configs: Add GPIO regulator supportPavan Kunapuli
Enable CONFIG_GPIO_REGULATOR for Tegra3 platforms. Bug 982788 Change-Id: I17587447013fdde6dc58b4fbf23f0ca37faa3dc5 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101968 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-11Revert "serial: tegra: Use tegra_dma_cancel() to abort request"Pradeep Kumar
BT Filetransfer have some issue. This reverts commit e8c243d5d09d1a552b66df7a8a0a0313047ebbac. Bug 982630 Change-Id: I6e76d44e076874569518fa881e427918d3e546f2 Signed-off-by: Pradeep Kumar <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/101914 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-11video: tegra: host: move chip_support out of nvhost_masterMayuresh Kulkarni
- currently, nvhost_master holds the reference to struct chip_support - the struct chip_support hides the chip specific implementation for channel submit, cdma, push buffer operations etc. so it exposed all the internal structures through nvhost_master - move chip_support to be a part of nvhost_bus since it only has function pointers to chip specific api implementations - nvhost_master is host1x device specific private data so ideally it should not hold reference to chip specifics Bug 871237 Change-Id: I4f3f48ee5fc47a90288d110ea8eef905150275a0 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/94421 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-11mmc: tegra: Fix SDR50 mode clock rate settingPavan Kunapuli
In SDR50 mode, set the controller clock to double the requested clock to ensure that the core voltage is maintained at a min of 1.2V. Bug 965298 Change-Id: I557a07de97efd6b44f812a11da657e03d3ddefd0 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/101522 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-11video: tegra: dc: Add display feature table support.Kevin Huang
Add display feature table so that user and kernel could set and update window attributes properly. Bug 962353 Change-Id: I08490a225892660126f3eefe4d5b7a4bb61d9bf7 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/101078 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-11mmc: core: Abort failed transfer before retriesPavan Kunapuli
Retries should be done only after abort command is issued for the current failed transfer. The block layer already has an implementation for retrying. No need for the extra retries. Bug 961761 Bug 922239 Change-Id: I07f60e85e093b725007727833739013f8fd66d43 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100563 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-11Revert "asoc: tegra: Add TDM mode support"Nikesh Oswal
This reverts commit dfa00e184b5fe0d4d48fa62a15fc956de9b6b65c. This is causing a regresssion. Bug: 977319 Change-Id: I4fe6daf88b2988978f089194f2931691eeb0eb09 Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/101687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijaya Bhaskar <vbhaskar@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-05-11arm: tegra: enterprise: New EMC table for A04 enterpriseKarthik Ramakrishnan
New EMC memory table for A04 Enterprise board Bug 969716 Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> Change-Id: I6936859ddf8d01b71025bfd21b690394dc3207bc Reviewed-on: http://git-master/r/101626 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2012-05-10video: tegra: host: Add syncpt trace eventsTerje Bergstrom
Add trace events for updating the syncpt value from hardware, and wait check. Change-Id: If17de153ae36c0665fe0af2f405dfe42f7fcd656 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/101524 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com>
2012-05-10video: tegra: host: Add context switch to trace dumpTerje Bergstrom
Add context switch to the ftrace dump. Change-Id: I5df032273982b919fb94263cff38d8b8b6b6be45 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/101523 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-10ARM: tegra: kai: change NCT72 conversion rateDaniel Fu
Bug 961829 NCT72 thermal sensor consumes ~3mW at 16Hz conversion rate. At 32Hz, the power consumption ~1.5mW. Change conversion rate to 32Hz to reduce power consumption. LP0 power consumption will not reduce, because the sensor will enter standby mode. Signed-off-by: Daniel Fu <danifu@nvidia.com> Change-Id: If584c57b4d6e0b3068d9a1210a977ef5cd347984 Reviewed-on: http://git-master/r/101217 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-10Arm: Tegra: Nor: use timing1 proper valueMohit Kataria
timing1_read was initialized with timing0 from nor platform data changed the same to use timing1 from platform data instead of timing0 Bug 934187 Change-Id: I04c41323de25fb2bb53dac91301cee9c0820707a Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/95293 Reviewed-on: http://git-master/r/100904 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amlan Kundu <akundu@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-05-10Arm: tegra: p1852: Changed sclk to run at max.Mohit Kataria
Sclk frequecy changes depending on the clocks derived from sclk. Changed it to run at max POR frequecy. Bug 971061 Change-Id: I357e1acd8d049bf233ff79b942c911db123865f6 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/100859 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-05-09arm: tegra: Correct tap delay for all T30 sdhci controllersnaveenk
Tap delay value of 0x0F is recommended by HW team Bug 911075 Change-Id: I9b73e7203c0dcb1971073b1d7251d11d71eddff3 Reviewed-on: http://git-master/r/98796 (cherry picked from commit 637b073d6ff7d7d71c2e0e632b222ecc6850be23) Reviewed-on: http://git-master/r/98763 Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-09power: bq27x00: start/stop delayed work upon suspend/resumePritesh Raithatha
Cancel delayed work upon suspend and schedule it on resume Bug 917914 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/95833 (cherry picked from commit a191d13e9dcdae715c9e03e1980857d00c082dc5) Change-Id: Ib8292daed3b4115657b1a66e1382ed7c1c448071 Reviewed-on: http://git-master/r/97080 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> GVS: Gerrit_Virtual_Submit <kchilds@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-09usb: gadget: udc-core: fix kernel crash on soft_connect and srp interfacesPreetham Chandru
We should not call dev_get_drvdata() as the driver data is never set. We should use container_of() as it is been used for other sysfs attributes. Without this change writing to the soft_connect or srp interfaces crashes the kernel because of null pointer dereference. Bug 975473 Signed-off-by: Preeham Chandru R <pchandru@nvidia.com> Change-Id: I45f6dab32f5435d518bd5b4fcdfafa54b9b89acd Reviewed-on: http://git-master/r/100238 Tested-by: Preetham Chandru <pchandru@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Kiran Adduri <kadduri@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2012-05-09Revert "ARM: tegra: clock: Don't fail clk_enable when max_rate has been lowered"Alex Frid
This reverts commit 8d351aa5478de533114e614f2607bc85ed23df91. The above commit introduced recursive call of clk enable/set rate APIs that may hang the system. Change-Id: I04eff9e1c3ddee82f6d2e17690122cc41fad203f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/100710 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-09ARM: tegra: power: Apply down delay to balancing CPUsAlex Frid
On Tegra3 secondary G-CPU may be turned off by auto-hotplug governor in two cases: when overall CPU load is low enough to justify transition to LP CPU, or when CPU cores usage by the scheduler is unbalanced (skewed). In the former case down delay (currently 2sec) was inserted before the core is turned Off. In the latter case the up delay (100ms) was used, i.e., the same delay applied to balancing cores regardless of the On/Off direction. This commit would apply down delay when turning core Off in both cases above, and keep using up delay only for turning core On. Change-Id: Id545f8d48cbf380e24824a5adfe045ff68c1f39c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/99708 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-08Revert "asoc:codecs: tiaic326x: remove minidsp support"Simone Willett
This reverts commit 774fa71fc9834fbdcb297048d9e9a4bc7b944b48 Change-Id: Ib187dff51d3b2fd2b2ac0c98a53abe07c99148aa Reviewed-on: http://git-master/r/101359 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-08cpufreq: interface for setting governor for a cpuPuneet Saxena
This implementation sets governor for a cpu using existing cpufreq interfaces. bug 871958 Change-Id: Ic4e7e2a2b0babaf1829b559b5db211666d449b86 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/97939 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-12 23:04:22 +0000