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2011-09-23ARM: errata: 752520: Faulty arbitration between PLD and Cacheable TLB ↵vdumpa
requests may create a system deadlock. Under rare circumstances, PLDs may interfere with a Cacheable page table walk, creating a processor deadlock. The erratum can only happen when the Data Cache and MMU are enabled, with the TLB descriptors marked as L1 cacheable, so that Page Table Walks are performed as cache linefills. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing PLD operations treated as NOP. (cherry-picked from b501cafea7328bc578f67e3e846ab9d25b7ec1b0) Change-Id: Ic4039b83de43530bae7ce705162441bea74e1e98 Reviewed-on: http://git-master/r/54095 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-06-16ARM: Cortex-A9: Enable dynamic clock gatingTodd Poynor
Enable dynamic high level clock gating for Cortex-A9 CPUs, as described in 2.3.3 "Dynamic high level clock gating" of the Cortex-A9 TRM. This may cut the clock of the integer core, system control block, and Data Engine in certain conditions. Add ARM errata 720791 to avoid corrupting the Jazelle instruction stream on earlier Cortex-A9 revisions. Original-Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86 Signed-off-by: Todd Poynor <toddpoynor@google.com>
2011-05-23[ARM] tegra: add FIQ supportIliyan Malchev
Signed-off-by: Iliyan Malchev <malchev@google.com>
2011-05-23[ARM] tegra: Add arch-specific udelay using TMRUSColin Cross
Change-Id: If075117642a725ee2ee24a622068274e588a5bc1 Signed-off-by: Colin Cross <ccross@android.com>
2011-05-23[ARM] Add ARCH_PROVIDES_UDELAY config optionColin Cross
Change-Id: Ife690c9d055fc0f17a52d2b29048af5062a664a6 Signed-off-by: Colin Cross <ccross@android.com>
2011-04-13Merge branch 'fix' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into fixes
2011-04-10ARM: 6866/1: Do not restrict HIGHPTE to !OUTER_CACHECatalin Marinas
The HIGHPTE config option depends on !OUTER_CACHE. However, there is no set_pte_ext() function that does outer cache maintenance by physical address, hence no need for such restriction. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-04-02ARM: Only allow PM_SLEEP with CPUs which support suspendRussell King
Offering CONFIG_PM_SLEEP for CPUs which do not support suspend leads to build errors, so only set CONFIG_ARCH_SUSPEND_POSSIBLE if we have a CPU selected which supports suspend. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-31Fix common misspellingsLucas De Marchi
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
2011-03-30Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (65 commits) ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC support ARM: 6838/1: etm: fix section mismatch warning ARM: 6837/1: remove unused pci_fixup_prpmc1100 ARM: 6836/1: kprobes/fix emulation of LDR/STR instruction when Rn == PC Fix the broken build for Marvell Dove platform. ARM: 6835/1: perf: ensure overflows aren't missed due to IRQ latency ARM: 6834/1: perf: reset counters on all CPUs during initialisation ARM: 6833/1: perf: add required isbs() to ARMv7 backend ARM: 6825/1: kernel/sleep.S: fix Thumb2 compilation issues ARM: 6807/1: realview: Fix secondary GIC initialisation for EB with MPCore tile arm: mach-mx3: pcm043: add write-protect and card-detect for SD1 eukrea_mbimxsd51: add SD Card detect eukrea_mbimxsd25-baseboard: add SD card detect mx3/eukrea_mbimxsd-baseboard: add SD card detect support mx3/eukrea_mbimxsd-baseboard: fix gpio request ARM: mxs/mx28evk: add mmc device ARM: mxs/mx23evk: add mmc device ARM: mxs: dynamically allocate mmc device ARM: mx51_efika: update platform data for new mfd changes mx2/iomux: Set direction for CSPI2 pins ...
2011-03-29arm: Use generic show_interrupts()Thomas Gleixner
Use the generic version and just keep the arch specific output. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-28Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into ↵Russell King
devel-stable
2011-03-28ARM: Suspend: Fix dependency of ARCH_SUSPEND_POSSIBLEKukjin Kim
The current mainline codes of ARCH_S5P64X0 and ARCH_S5P6442 can not support suspend to ram. So needs this for preventing build error on them. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Len Brown <len.brown@intel.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-03-23Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (35 commits) ARM: Update (and cut down) mach-types ARM: 6771/1: vexpress: add support for multiple core tiles ARM: 6797/1: hw_breakpoint: Fix newlines in WARNings ARM: 6751/1: vexpress: select applicable errata workarounds in Kconfig ARM: 6753/1: omap4: Enable ARM local timers with OMAP4430 es1.0 exception ARM: 6759/1: smp: Select local timers vs broadcast timer support runtime ARM: pgtable: add pud-level code ARM: 6673/1: LPAE: use phys_addr_t instead of unsigned long for start of membanks ARM: Use long long format when printing meminfo physical addresses ARM: integrator: add Integrator/CP sched_clock support ARM: realview/vexpress: consolidate SMP bringup code ARM: realview/vexpress: consolidate localtimer support ARM: integrator/versatile: consolidate FPGA IRQ handling code ARM: rationalize versatile family Kconfig/Makefile ARM: realview: remove old AMBA device DMA definitions ARM: versatile: remove old AMBA device DMA definitions ARM: vexpress: use new init_early for clock tree and sched_clock init ARM: realview: use new init_early for clock tree and sched_clock init ARM: versatile: use new init_early for clock tree and sched_clock init ARM: integrator: use new init_early for clock tree init ...
2011-03-23ARM: mxc: Add sched_clock to mxc platformJan Weitzel
Add sched_clock using cyc_to_sched_clock and update_sched_clock with HAVE_SCHED_CLOCK tested on iMX27 and iMX35 Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-03-20Merge branches 'fixes', 'pgt-next' and 'versatile' into develRussell King
2011-03-17Merge branch 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msmLinus Torvalds
* 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msm: (46 commits) msm: scm: Check for interruption immediately msm: scm: Fix improper register assignment msm: scm: Mark inline asm as volatile msm: iommu: Enable HTW L2 redirection on MSM8960 msm: iommu: Don't read from write-only registers msm: iommu: Remove dependency on IDR msm: iommu: Use ASID tagging instead of VMID tagging msm: iommu: Rework clock logic and add IOMMU bus clock control msm: iommu: Clock control for the IOMMU driver msm: mdp: Set the correct pack pattern for XRGB/ARGB msm_fb: Fix framebuffer console msm: mdp: Add support for RGBX 8888 image format. video: msmfb: Put the partial update magic value into the fix_screen struct. msm: clock: Migrate to clkdev msm: clock: Remove references to clk_ops_pcom msm: headsmp.S: Fix section mismatch msm: Use explicit GPLv2 licenses msm: iommu: Enable IOMMU support for MSM8960 msm: iommu: Generalize platform data for multiple targets msm: iommu: Create a Kconfig item for the IOMMU driver ...
2011-03-17Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (289 commits) davinci: DM644x EVM: register MUSB device earlier davinci: add spi devices on tnetv107x evm davinci: add ssp config for tnetv107x evm board davinci: add tnetv107x ssp platform device spi: add ti-ssp spi master driver mfd: add driver for sequencer serial port ARM: EXYNOS4: Implement Clock gating for System MMU ARM: EXYNOS4: Enhancement of System MMU driver ARM: EXYNOS4: Add support for gpio interrupts ARM: S5P: Add function to register gpio interrupt bank data ARM: S5P: Cleanup S5P gpio interrupt code ARM: EXYNOS4: Add missing GPYx banks ARM: S3C64XX: Fix section mismatch from cpufreq init ARM: EXYNOS4: Add keypad device to the SMDKV310 ARM: EXYNOS4: Update clocks for keypad ARM: EXYNOS4: Update keypad base address ARM: EXYNOS4: Add keypad device helpers ARM: EXYNOS4: Add support for SATA on ARMLEX4210 plat-nomadik: make GPIO interrupts work with cpuidle ApSleep mach-u300: define a dummy filter function for coh901318 ... Fix up various conflicts in - arch/arm/mach-exynos4/cpufreq.c - arch/arm/mach-mxs/gpio.c - drivers/net/Kconfig - drivers/tty/serial/Kconfig - drivers/tty/serial/Makefile - drivers/usb/gadget/fsl_mxc_udc.c - drivers/video/Kconfig
2011-03-16Merge remote branch 'rmk/for-linus' into for-linusDavid Brown
* rmk/for-linus: (1557 commits) ARM: 6806/1: irq: introduce entry and exit functions for chained handlers ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas ARM: 6747/1: P2V: Thumb2 support ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9 ARM: 6772/1: errata: possible fault MMU translations following an ASID switch ARM: 6776/1: mach-ux500: activate fix for errata 753970 ARM: 6794/1: SPEAr: Append UL to device address macros. ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files ARM: 6792/1: SPEAr: Replace SIZE macro's with SZ_4K macros ARM: 6791/1: SPEAr3xx: Declare device structures after shirq code ARM: 6790/1: SPEAr: Clock Framework: Rename usbd clock and align apb_clk entry ARM: 6789/1: SPEAr3xx: Rename sdio to sdhci ARM: 6788/1: SPEAr: Include mach/hardware.h instead of mach/spear.h ARM: 6787/1: SPEAr: Reorder #includes in .h & .c files. ARM: 6681/1: SPEAr: add debugfs support to clk API ARM: 6703/1: SPEAr: update clk API support ARM: 6679/1: SPEAr: make clk API functions more generic ARM: 6737/1: SPEAr: formalized timer support ... Conflicts: arch/arm/mach-msm/board-msm7x27.c arch/arm/mach-msm/board-msm7x30.c arch/arm/mach-msm/board-qsd8x50.c arch/arm/mach-msm/board-sapphire.c arch/arm/mach-msm/include/mach/memory.h
2011-03-16Merge branch 'remove' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'remove' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6629/2: aaec2000: remove support for mach-aaec2000 ARM: lh7a40x: remove unmaintained platform support Fix up trivial conflicts in - arch/arm/mach-{aaec2000,lh7a40x}/include/mach/memory.h (removed) - drivers/usb/gadget/Kconfig (USB_[GADGET_]LH7A40X removed, others added)
2011-03-16Merge branch 'p2v' into develRussell King
Conflicts: arch/arm/kernel/module.c arch/arm/mach-s5pv210/sleep.S
2011-03-16Merge branch 'v6v7' into develRussell King
Conflicts: arch/arm/include/asm/cacheflush.h arch/arm/include/asm/proc-fns.h arch/arm/mm/Kconfig
2011-03-16Merge branch 'misc' into develRussell King
Conflicts: arch/arm/Kconfig
2011-03-16Merge branches 'at91', 'ep93xx', 'errata', 'footbridge', 'fncpy', 'gemini', ↵Russell King
'irqdata', 'pm', 'sh', 'smp', 'spear', 'ux500' and 'via' into devel
2011-03-12ARM: S5P: Update defconfig for HRT supportSangbeom Kim
This patch updates s5pv210_defconfig and s5p64x0_defconfig for HRT support and CONFIG_S5P_HRT is used for its configuration. Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-03-11ARM: EXYNOS4: Implement kernel timers using MCTChanghwan Youn
The Multi-Core Timer(MCT) of EXYNOS4 is designed for implementing clock source timer and clock event timers. This patch implements 1 clock source timer with 64 bit free running counter of MCT and 2 clock event timers with two of 31-bit tick counters. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-03-10ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gasDave Martin
Various binutils versions can resolve Thumb-2 branches to locally-defined, preemptible global symbols as short-range "b.n" branch instructions. This is a problem, because there's no guarantee the final destination of the symbol, or any candidate locations for a trampoline, are within range of the branch. For this reason, the kernel does not support fixing up the R_ARM_THM_JUMP11 (102) relocation in modules at all, and it makes little sense to add support. The symptom is that the kernel fails with an "unsupported relocation" error when loading some modules. Until fixed tools are available, passing -fno-optimize-sibling-calls to gcc should prevent gcc generating code which hits this problem, at the cost of a bit of extra runtime stack usage in some cases. The problem is described in more detail at: https://bugs.launchpad.net/binutils-linaro/+bug/725126 Only Thumb-2 kernels are affected. This patch adds a new CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 config option which adds -fno-optimize-sibling-calls to CFLAGS_MODULE when building a Thumb-2 kernel. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-10ARM: 6747/1: P2V: Thumb2 supportNicolas Pitre
Adding Thumb2 support to the runtime patching of the virt_to_phys and phys_to_virt opcodes. Tested both the 8-bit and the 16-bit fixups, using different placements in memory to exercize all code paths. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-09ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9Will Deacon
On revisions of the Cortex-A9 prior to r2p0, the Store Buffer does not have any automatic draining mechanism and therefore a livelock may occur if an external agent continuously polls a memory location waiting to observe an update. This workaround defines cpu_relax() as smp_mb(), preventing correctly written polling loops from denying visibility of updates to memory. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-09ARM: 6772/1: errata: possible fault MMU translations following an ASID switchWill Deacon
On the r2p* and r3p* versions of the Cortex-A9, a speculative memory access may cause a page table walk which starts prior to an ASID switch but completes afterwards. This can populate the micro-TLB with a stale entry which may be hit with the new ASID. This workaround places two dsb instructions in the mm switching code so that no page table walks can cross the ASID switch. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-09ARM: 6786/1: enable CONFIG_KTIME_SCALARRob Herring
Use straight 64-bit values as 64-bit operations are fairly efficient on ARM. Comparing the asm output with and without KTIME_SCALAR, using 64-bit math generates clearly better code. Comparing kernel/hrtimer.c .text size, it goes from 0x1414 to 0x119c with this change. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-09ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corruptiSantosh Shilimkar
PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. Workaround: Disable Write-Back and Cache Linefill (Debug Control Register) Clean & Invalidate by Way (0x7FC) Re-enable Write-Back and Cache Linefill (Debug Control Register) This patch also removes any OMAP dependency on PL310 Errata's Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-28msm: clock: Migrate to clkdevStephen Boyd
Migrating to clkdev has several advantages: * Less code in mach-msm/clock.c * A more robust clk_get() implementation * clk_add_alias() support * clk_get_sys() support In general, this will help board authors setup clock aliases and break the dependency on device pointers in the clock tables. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2011-02-23ARM: move L1_CACHE_SHIFT_6 to mm/KconfigRussell King
Move L1_CACHE_SHIFT related options together, rather than spreading them across two separate Kconfig files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-22ARM: EXYNOS4: Update Kconfig and Makefile for the new ARCH_EXYNOS4Kukjin Kim
This patch changes the Kconfig and Makefile for the new ARCH_EXYNOS4. It also updates arch/arm/Kconfig, Makeifile and arch/arm/mm/Kconfig to include support for the new ARCH_EXYNOS4. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-02-19ARM: 6743/1: errata: interrupted ICALLUIS may prevent completion of ↵Will Deacon
broadcasted operation On versions of the Cortex-A9 prior to r3p0, an interrupted ICIALLUIS operation may prevent the completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing CP15 maintenance operations to be uninterruptible. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: 6741/1: errata: pl310 cache sync operation may be faultySrinidhi Kasagar
The effect of cache sync operation is to drain the store buffer and wait for all internal buffers to be empty. In normal conditions, store buffer is able to merge the normal memory writes within its 32-byte data buffers. Due to this erratum present in r3p0, the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. This can severely affect performance on the write traffic esp. on Normal memory NC one. The proposed workaround is to replace the normal offset of cache sync operation(0x730) by another offset targeting an unmapped PL310 register 0x740. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: integrator/versatile: consolidate FPGA IRQ handling codeRussell King
Consolidate the FPGA IRQ handling code. Integrator/AP and Versatile have one FPGA-based IRQ handler each. Integrator/CP has three. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: rationalize versatile family Kconfig/MakefileRussell King
Move leds and sched_clock build conditionals out of the Makefile into the Kconfig file. Move selection of HAVE_SCHED_CLOCK into the platform Kconfig rather than duplicating it three times in the main architecture Kconfig. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: vexpress: switch Versatile Express to use consolidated CLCDRussell King
This switches Versatile Express to use the conslidated CLCD panel support, including the display capabilities. As Versatile Express uses a PL111, it can support the full range of pixel formats - 444, 5551, 565 in both RGB and BGR mode. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: realview: switch Realview to use consolidated CLCDRussell King
This switches Realview platforms to use the consolidated CLCD panel support, including the display capabilities. As Realview uses a PL111, it can support the full range of pixel formats - 444, 5551, 565 in both RGB and BGR mode. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: versatile: switch Versatile to use consolidated CLCDRussell King
This switches Versatile platforms to use the consolidated CLCD panel support, including the display capabilities. Versatile can support RGB5551, BGR5551, RGB565 and BGR565 modes. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-19ARM: add versatile family consolidated CLCD supportRussell King
This consolidates the CLCD panel definitions and memory allocation into one location. Rename the Sanyo 2.5in and Epson 2.2in displays after their respective part numbers. Rather than using a general "Sanyo 2.5in" and "Epson 2.2in" description of the display panel, use the manufacturers part number to be more specific. This helps people identify what the timings actually refer to, which are panel specific. While here, add CLCD capability information to each panel definition, which has no effect until we add the board-level capabilities. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-17ARM: P2V: extend to 16-bit translation offsetsRussell King
MSM's memory is aligned to 2MB, which is more than we can do with our existing method as we're limited to the upper 8 bits. Extend this by using two instructions to 16 bits, automatically selected when MSM is enabled. Acked-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-17ARM: P2V: introduce phys_to_virt/virt_to_phys runtime patchingRussell King
This idea came from Nicolas, Eric Miao produced an initial version, which was then rewritten into this. Patch the physical to virtual translations at runtime. As we modify the code, this makes it incompatible with XIP kernels, but allows us to achieve this with minimal loss of performance. As many translations are of the form: physical = virtual + (PHYS_OFFSET - PAGE_OFFSET) virtual = physical - (PHYS_OFFSET - PAGE_OFFSET) we generate an 'add' instruction for __virt_to_phys(), and a 'sub' instruction for __phys_to_virt(). We calculate at run time (PHYS_OFFSET - PAGE_OFFSET) by comparing the address prior to MMU initialization with where it should be once the MMU has been initialized, and place this constant into the above add/sub instructions. Once we have (PHYS_OFFSET - PAGE_OFFSET), we can calculate the real PHYS_OFFSET as PAGE_OFFSET is a build-time constant, and save this for the C-mode PHYS_OFFSET variable definition to use. At present, we are unable to support Realview with Sparsemem enabled as this uses a complex mapping function, and MSM as this requires a constant which will not fit in our math instruction. Add a module version magic string for this feature to prevent incompatible modules being loaded. Tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-11ARM: 6659/1: Thumb-2: Make CONFIG_OABI_COMPAT depend on !CONFIG_THUMB2_KERNELDave Martin
rmk says: "You might as well make OABI_COMPAT depend on !THUMB2_KERNEL. OABI userland is useless without FPA support." nwfpe doesn't work with Thumb-2 anyway and will probably never get ported, so I can't argue with that. This patch implements the dependency change. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-11ARM: 6629/2: aaec2000: remove support for mach-aaec2000Jamie Iles
mach-aaec2000 is no longer actively maintained and is only receiving fixups to remain building with other kernel updates. Cc: Bellido Nicolas <ml@acolin.be> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-02ARM: v6k: only allow SMP if we have v6k or v7 CPURussell King
SMP extensions are only supported on ARMv6k or ARMv7 architectures, so only offer the option if we're building for such an architecture. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-02ARM: v6k: select generic atomic64 code according to V6 variantsRussell King
If CONFIG_CPU_V6 is enabled, avoid using the double-word exclusive instructions in the kernel's atomic implementations as these are not supported. Fall back to the generic spinlock code instead. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-02ARM: v6k: Dove platforms use V6K architecture CPUsRussell King
Make Dove platforms select the new V6K CPU option. Tested-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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