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- Add usbphy_nop, hsic uses nop phy driver
- Add anatop phandle, hsic needs to access anatop register to
change osc clock for different boards
- Add phy_type, hsic needs to config PHY parameters at portsc
- For imx6q-arm2 board, hsic has pin conflict with ethernet, we create a
dedicated dts(imx6q-arm2-hsic.dts) for it with ethernet disabled, besides
please make sure keep the line of data and strobe unchanged between board
boots up and enable hsic controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
(cherry picked from commit 2f8a266d271874cd398d14556752ab4ab0be27ba)
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NAND scans the bad blocks during kernel boots up, which invokes the
gpmi_ecc_read_oob function to check the badblock mark for each block. In
this function the oob data was raw read from NAND chip without ECC, so
it hardly to guarantee the consistency of the data considering the
possible bitflips. It found that in some MLC NAND the oob data changed
and consequently the BBT changed in different power cycles. This issue
may cause the UBIFS mount failed.
To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT
in NAND flash. On the first time kernel boot up, all bad blocks and
probably some fake bad block would be recognized and be recorded in
on-nand bad block table. From the second time boot, kernel will read BBT
from NAND Flash rather than calling gpmi_ecc_read_oob function to check
bad block.
No bad block would be missed when create BBT since the probability that
16bit bad block mark filps from 0x00 to 0xFF is extremely low.
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked and merge from commit d957353768a1b6d39b340b9d10b22fc42b0aa8e2)
(cherry picked from commit 7b7d3d683a24b23f33d6c08874f31fe50ef2fc76)
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Disable all otg features for otg1 port of imx6q-arm2 board, then
the otg port can only do role swtich by ID pin state.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit 70c4fe93ac7064f5128ae2275b766fb00c4cd6ef)
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Several dts files set a bit in the SPEED field for pads
RGMII_{R,T}{XC,D0,D1,D2,D3,X_CTL}, but that doesn't exist. Writing there
doesn't have an effect and the bit reads as zero.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add the DT property to all boards that have the hardware workaround
for erratum ERR006687 present. This allows the CPUidle driver to use
the deep idle states, even if the FEC is active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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As of commit 1006ed7e1b258dac ("serial: imx: Use generic uart-has-rtscts
DT property"), the Freescale IMX UART driver recognizes the generic
"uart-has-rtscts" DT property, deprecating the vendor-specific
"fsl,uart-has-rtscts" DT property. Hence replace the latter by the
former in all DTS files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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cd-gpios polarity should be changed to GPIO_ACTIVE_LOW and wp-gpios
should be changed to GPIO_ACTIVE_HIGH.
Otherwise, the SD may not work properly due to wrong polarity inversion
specified in DT after switch to common parsing function mmc_of_parse().
Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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This works around a hardware bug.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The device tree specification recommends that generic name should be
used for nodes. So instead of naming those fixed regulator nodes
arbitrarily, let's use the generic name 'regulator@num' for those nodes.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.
The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Enable USB OTG controller at imx6q-arm2 board
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add the dma property for all the uart.
Note: Add the dma property does not mean we enable the dma for this
uart.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board
design can work with either chip plugged into the socket, e.g. sabresd
and sabreauto boards.
We currently define pin groups in imx6q.dtsi and imx6dl.dtsi
respectively because the pad macro names are different between two
chips. This brings a maintenance burden on having the same label point
to the same pin group defined in two places.
The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs
pad macro names. Then the pin groups becomes completely common between
imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the
long term maintenance of imx6q/dt pin settings becomes easier.
Unfortunately, the change brings some dramatic diff stat, but it's all
about DTS file, and the ultimate net diff stat is good.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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enable the uart2 for imx6q-arm2 board.
The uart2 works in the DTE mode, with the RTS/CTS and DMA enabled.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function. Every time a new imx SoC support is
added, we need to add such a big mount of data. With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.
With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.
The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.
As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Replace /include/ (dtc) with #include (C pre-processor) for all imx DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.
This allows future use of #defines and header files in order to define
names for various constants, such as pinctrl settings. Use of those
features will increase the readability of the device tree files.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add dtsi for imx6q and imx6dl with non-common blocks moved into there.
Major differences between imx6dl and imx6q:
* Dual vs. Quad cores
* single vs. dual IPU
* 128 vs. 256 KB OCRAM
* imx6q: ECSPI5, OpenVG (GC355), SATA
* imx6dl: I2C4, PXP, EPDC, LCDIF
* iomuxc/pads definition
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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i.MX6 Quad and i.MX6 DualLite is similar enough to share one dtsi
file, so rename imx6q.dtsi to imx6qdl.dtsi preparing for the addition
of imx6dl support.
Another member of i.MX6 series i.MX6 SoloLite is different enough
from the other two, so it will stand as a separate dtsi. That's why
we rename to imx6qdl.dtsi not imx6.dtsi.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Following omap3-evm.dts way, it changes all imx dts files to use label
in board dts to refer to nodes defined by soc dtsi. Thus, the board
dts files become easier to read and edit with the least indentation
levels.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Commit 9e3c0066 (ARM: dts: imx6q-arm2: add pinctrl for uart and enet)
defines NANDF_CS pins as gpio in 'hog', assuming these two pins are
always used by usdhc3 in gpio mode as card-detection and
write-protection on ARM2 board. But it's not true. These pins are
shared by usdhc3 and gpmi-nand. We should have the pins functional
for gpmi-nand when usdhc3 is disabled.
Move the pins out of 'hog', so that pins only work in gpio mode as CD
and WP when usdhc3 is enabled, and otherwise they are available for
gpmi-nand.
Reported-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add missing pinctrl of uart and enet for imx6q-arm2 board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add the DT node for gpmi nand.
Add the pinmux support for gpmi nand.
The gpmi nand may conflicts with other modules, such as MMC.
So we do not enable the gpmi nand for mx6q-arm2 board, just add the
node for the board.
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Changes in the dt2 branch move stuff around that gets changed
in the drivers/mmc branch. I chose a non-obvious resolution by
adding the new bus-width property into all the tegra sdhci device
nodes.
Conflicts:
arch/arm/boot/dts/tegra-cardhu.dts
arch/arm/boot/dts/tegra-harmony.dts
arch/arm/boot/dts/tegra-ventana.dts
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This patch unifies the current DT MMC bindings documentation and code,
adds generic MMC DT bindings documentation, and updates .dts files for
consistency.
[cjb: typo fixes, addition of max-frequency property]
Signed-off-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Do not hardcode the local mac address.
Let bootloader retrieve it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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It has been pointed out by device tree maintainer for several times
that the generic names 'serial' and 'ethernet' should be used for
those devices per ePAPR. Renames imx uart and fec device tree nodes
to stop them being bad examples.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
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Remove bootargs field as this information is retrieved from the bootloader.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The Sabreauto board was renamed to Armadillo2 recently. To avoid
confusion, rename Sabreauto to Armadillo2/arm2.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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