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2019-02-12MLK-13922: ARM: dts: imx6qp-sabreauto: add lvd-channel info to ldbOctavian Purdila
Also, enable the mxcfb* entries. Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
2019-02-12MLK-12029 ARM: dts: imx6qp-sabreauto.dts: add vmmc supply for usdhc3Haibo Chen
For imx6qp-ard board, it is okay to use external regulator for card slot, so this patch add vmmc-supply for usdhc3. Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
2019-02-12MLK-11431-3: ARM: DTS: imx6 Add IPU and display supportSandor Yu
Add IPU, HDMI and LDB support. Signed-off-by: Sandor Yu <R01008@freescale.com>
2019-02-12MLK-11376-01 ARM: dts: add dts file for imx6qpBai Ping
Add dtsi and dts file for i.MX6QP Signed-off-by: Bai Ping <b51503@freescale.com> In 4.14 upstream has different definitions for pre/prg. Picked our definitions instead because our driver is unrelated. Adjusted pcie overrides to match upstream rename from commit 3e1b857786f0 ("ARM: dts: imx: fix PCI bus dtc warnings") Drop adding duplicate imx6qp-sabreauto.dtb to Makefile Upstream removed definitions for ipu1/ipu2, added our definitions as per latest 4.9.y. Originally part of: MLK-14282: 4.9 rebase: LVDS display not working on iMX6QP SabreSD Fix IPU2 DI(Display Interface) clocks for iMX6QP SABRESD. The upstream version uses ldb_di0_podf and ldb_di1_podf as clock parents for ipu_di, which fails to work on iMX6QP SABRESD. This patch fixes clock tree by: - setting ipu_di selectors to ldb_di_div_sel in imx6q clock driver - matching "ldb_di0", "ldb_di1" clock names with IMX6QDL_CLK_LDB_DI0_DIV_SEL, IMX6QDL_CLK_LDB_DI1_DIV_SEL; otherwise, ldb_di0_div_sel and ldb_di1_div_sel will not be recognized as LDB clk parents and will not drive the Display Interface. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-02-12MLK-11853 ARM: dts: imx6qp-sabreauto: remove the enet pin reconfigFugang Duan
Tuning MMDC ZQ_PU_OFFSET impact DDR IO timing like the value is greater than 0x9 causing enet lost packets due to the worse timing. Reinforce ENET DDR IO drive strength can fix the issue. Use the default pin setting can match the RGMII timing for AI board. Worse timing cause performance drop, the performance has no drop after enhancing the DDR IO pins drive strength. Pass over night test. Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit: 5ceb746c0358c0851187a3f4f6f61d02e951eae0) Conflicts: arch/arm/boot/dts/imx6qp-sabreauto.dts (cherry picked from commit 0ea975d4bd6fb8ee479333441e7693a1a1f0d76a)
2016-02-29ARM: dts: imx: Add basic dts support for imx6qp-sabreautoBai Ping
This patch adds basic dts file for i.MX6QP-Sbreauto board. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>