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The sw2iso count should cover ARM LDO ramp-up time,
the MAX ARM LDO ramp-up time may be up to more than
100us, this patch sets sw2iso to 0xf (~384us) which
is the default value.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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For the slot support SD3.0 card, during system suspend, if plug out
the sd card, and insert another SD3.0 card, after system resume back,
SD3.0 card can't be recognised as SD3.0 card, just SD2.0 card.
This is bause the time delay between vmmc regulator off and on is
too small, this patch add the oo-on-delay in vmmc-supply regulator,
to assign proper delay value.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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SW3B fused to high voltage 0.8v~3.3v and the low voltage setting in
dts cause pfuze200 driver probe failed as below even if the pfuze
driver have already updated the voltage to the right 0.8v~3.3v.But the
issue not caught on v4.1 since it's common regualtor framework behavior.
Correct the SW3B into the right voltage in v4.9
fuze100-regulator 0-0008: pfuze200 found.
SW3B: Bringing 3300000uV into 1975000-1975000uV
SW3B: failed to apply 1975000-1975000uV constraint(-22)
pfuze100-regulator 0-0008: register regulatorSW3B failed
pfuze100-regulator: probe of 0-0008 failed with error -22
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 19, base_baud = 5000000) is a IMX
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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On imx_4.9.y we no longer override the cpu arm/soc/pu-supply properties
to link to pmic directly but rather rely on the regulator core
propagating a set_voltage on a bypassed regulator upwards.
This change was already performance for imx6qdl, now do it for all the
boards using ldo-bypass.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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The Linux kernel regulator core implementation does not accept negative
voltage values; all negative values are treated as errors.
The problem with the EPDC is that the panel uses a negative voltage
regulator which fails to be enabled by the regulator core. This issue has
slipped up until the 4.9 rebase because the voltage range [min, max] was
checked against only when min = max. This has been fixed in 4.9, resulting
in errors in the VCOM regulator driver.
The fix is to use the negative values when communicating with the hardware,
but send only positive values to the regulator core.
This patch sends the absolute value to the regulator core and transforms
the received value (from the regulator core) to negative one before sending
it to hardware.
Fix device tree to deal with negative voltage regulator values by setting
min_value = -real_max_value and vice versa. Boards affected:
- imx6dl-sabresd
- imx6ull-14x14-ddr3-arm2
- imx7d-12x12-lpddr3-arm2
- imx7d-sdb
- imx6sll-evk
- imx6sl-evk
- imx6sll-lpddr3-arm2
Signed-off-by: Cristina Ciocan <cristina-mihaela.ciocan@nxp.com>
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According to the latest datasheet(Rev. 0,09/2016), update the
setpoints of i.MX6ULL. we add 25mV margin to cover IR drop
and board tolerance.
LDO enable:
Freq VDD_SOC VDD_ARM
528MHz 1.175V 1.175V
396MHz 1.175V 1.025V
198MHz 1.175V 0.95V
LDO bypass
Freq VDD_SOC VDD_ARM
528MHz 1.175V 1.175V
396Mhz 1.175V 1.175V
198MHz 1.175V 1.175V
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Using pull-up or pull down will cause that codec can get
big data in right channel. using keeper to fix this issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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enable WDOG_B reset pin on i.mx6ull-14x14-ddr3-arm2 board
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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On i.MX6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins have been move to the IOMUXC_SNVS. Add additional pinfunc define
and correct the pinctrl binding.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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of hog
Move usdhc1 wp/cd/reset/vselect pin setting and usdhc2 reset pin
setting out of hog. Due to many pin conflict with usdhc1 and usdhc2,
this patch can let other modules do not touch the iomuxc.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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Improve enet data/txc clock timing suggested by HW team.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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The optional QSPI pin should be only enabled on reworked board, fix the
issue which conflict with SD2.
Signed-off-by: Han Xu <han.xu@nxp.com>
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Add usdhc2 support, due to cd/wp pin conflict with usdhc1, this
patch drop these two pins, and make usdhc2 as no removeable.
Moreover, due to VSELECT pin is not connected by default, we also
add no-1-8-v property.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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According to Hardware team's suggestion, for usdhc2, this patch change
the drive strength for clock pin and data pin, which can make the signal
meet the requirement for DDR50 mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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support QSPI on i.MX6ULL. By default, only QSPI1 was enabled, while
reworked board could support all 4 QSPI chips.
Signed-off-by: Han Xu <han.xu@nxp.com>
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lcd touch
Since pwm3 and lcd touch are conflict for one pin, change
backlight to use pwm1 instead. But pwm1 also conflicts with
enet1, so enable backlight in a new dts file.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Use a dedicatd dts file to enable both OTG1 and OTG2 ports in OTG mode,
- otg2 ID pin is muxed with SD1 vselect, so move it out of hog and don't
use it in usdhc1 in usb dts.
- otg2 vbus control use GPIO1_IO09 since the original gpio is shared
with i2c1(with pmic chip connected).
Signed-off-by: Li Jun <jun.li@nxp.com>
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Enable otg mode for OTG1 port for imx6ull arm2 board.
Signed-off-by: Li Jun <jun.li@nxp.com>
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Enable fec1 port in ddr3 ARM2 board.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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The pwm3 and otg1 share the same pin 'GPIO1_IO04'. And default,
the pin is used for otg1. So create a new dts file to solve
this conflict.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Add dts file for i.MX6ULL DDR3 ARM2 board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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