| Age | Commit message (Collapse) | Author |
|---|
|
- Update iomux header for i.MX7ULP B0 silicon.
- Align the pin func name with header file for all dts files.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Acked-by: Shenwei Wang <shenwei.wang@nxp.com>
During the 4.14 rebase all intermediate commits were adjusted for
upstream prefix so this has many fewer dts changes.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
|
|
i.MX7ULP B0 has different CPU opp table, update it accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
|
|
i.MX7ULP QSPI dtb was used to update the M4 images, it should not able
to boot the kernel even without the M4 image in QSPI.
Also fixed the typo in dtsi to correct the QSPI register address
mapping range.
Signed-off-by: Han Xu <han.xu@nxp.com>
|
|
The iomux PAD setting for QSPI on i.MX7ULP should belong to
iomuxc0(refers to iomuxc in dtsi file) rather than iomuxc1.
Signed-off-by: Han Xu <han.xu@nxp.com>
|
|
Add one more dts for QSPI on i.MX7ULP1 for mfgtool purpose.
Signed-off-by: Han Xu <han.xu@nxp.com>
|
