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Add dma configurations in dts files, for imx7ulp and imx8qm.
There is no "edma0" node in fsl-imx8qm-mek(or lpddr4-arm2)-domu.dts.
lpspi0 node has been deleted in these dts files, so delete lpspi3 node.
Add edma0a and edma0d for lpspi0 and lpspi3, and enable lpspi0/3 for xen.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Acked-by: Fugang Duan <Fugang.duan@nxp.com>
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i.MX7ULP LPSPI also use both ipg/per clock for the module, which ipg
clock was not exposed. Add one dummy clock as ipg clock to make the
lpspi code neat and clear.
Reviewed-by: Pan Gao <pandy.gao@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
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add board compatible string for imx7ulp and m845s
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
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Set gpu physical base address and size into dts for 7ulp.
Date: Dec 21, 2016
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
(cherry picked from commit b5ae6ee5c84b8eb197af34d78f572be667ed0574)
(cherry picked from commit 64ba25ed48ec760a5b783ecf3c0defb5d71916be)
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The resources retrieved by CAAM driver was wrong as the size
was not correct hence future uses might have issues.
before:
[ 3.010744] caam 30900000.caam:
sm res: [start: 0000000000100000,
end: 0000000000107ffe,
name: /caam-sm@00100000,
flags:0x200 desc:0x0] -> size: 0x7fff
modif to actual size:
[ 3.012495] caam 30900000.caam:
sm res: [start: 0000000000100000,
end: 0000000000107fff,
name: /caam-sm@00100000,
flags:0x200 desc:0x0] -> size: 0x8000
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
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Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
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Added the PMU node in the imx7ulp.dtsi, and enable
it by default.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
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7ULP uses the same mmdc profiling block as i.mx6q. Added the
"fsl,imx6q-mmdc" compatible string to enable the mmdc profiling
feature.
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
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Confirm with IC, HS400 MAX clock Freq for Instance 0 is 198Mhz
and for Instance 1 is 192MHz, so set the usdhc parent clock at
396MHz, due to current APLL is config to 529.2MHz, use the formula
APLL_PFD clock = APLL * 18 / i, the nearest clock is 381.024MHz when
the i is 25, so the usdhc root clock is 190.512MHz.
But eMMC HS400 can't pass stress test at 190.512MHz, will meet CRC
error sometimes, only when down to 176.4MHz can pass the stress test.
This patch make the usdhc0 and usdhc1 root clock both source from
IMX7ULP_CLK_APLL_PFD1, and set this APLL_PFD1 clcok rate at 352.8MHz,
and set the USDHC0 root clock at 352.8MHz, and set the USDHC1 root
clock at 176.4MHz.
Also remove the clk_prepare_enable() and clk_disable_unprepare() for
APLL_PFD2, bacause U-Boot already gate off APLL_PFD1, not need to do
this again.
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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Fixing a terrible coding format issue.
Cc: Song Bing <bing.song@nxp.com>
Fixes: 5cb40d13c879 ("MLK-13563 ion: Enable ion driver on imx7ulp")
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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According to the clk digram in section 24.6 Core, Platform and System Bus
clocks in reference manual, the correct available periph_bus_sels should be
{ "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus",
"nic1_div", "spll_bus_clk", }.
And the real tpm/pwm/lpuart parent clock should be IMX7ULP_CLK_SOSC_BUS_CLK
while some others should be IMX7ULP_CLK_FIRC_BUS_CLK, So update dts as well.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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On MX7ULP, GPIO controller needs two necessary clocks:
Port module clock and GPIO module clock.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Currently people have no idea on which pad is correspding to which gpio
controller as there's no hints in dts. Let's add a proper prefix for gpio
nodes as follows in dts to make it much easier to use.
gpio0 = &gpio_ptc;
gpio1 = &gpio_ptd;
gpio2 = &gpio_pte;
gpio3 = &gpio_ptf;
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Remove unnecessary fsl,mux_mask property which is also not documented in
binding doc. As we already have imx_pinctrl_soc_info structure which
represents the SoC specific properties, encode in it instead.
The patch also simplies the code a bit by removing the mux_shift
calculation code which is not necessary as well.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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On i.MX7ULP B0 chip, NMI irq number is changed,
update it to make VLLS/VLPS work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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According to datasheet Rev-D, on B0 part, below CPU
freq needs to be supported:
500MHz for RUN mode;
720MHz for HSRUN mode.
Update opp table accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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Add rpmsg rtc node for i.MX7ULP.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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Add 'phy-ref-clkfreq' property for 'mipi_dsi' node on
imx7ulp board.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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i.MX7ULP QSPI dtb was used to update the M4 images, it should not able
to boot the kernel even without the M4 image in QSPI.
Also fixed the typo in dtsi to correct the QSPI register address
mapping range.
Signed-off-by: Han Xu <han.xu@nxp.com>
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The lpi2c needs two clks, per clk and ipg clk. This patch adds ipg
clk for lpi2c device node.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
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Update the setpoint voltage on i.MX7ULP.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add the 'data-lanes-num' and 'max-data-rate' properties which
are used to describe this mipi dsi capabilites.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit bfe7d0e1c6931467f00a382e48aa592bf50c9339)
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Add pwm device node in dtsi file.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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lpi2c4 is not used on imx7ulp platform, disable it;
lpi2c7 is used for touch, enable it;
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
(cherry-pick from 9137ed6de38513c585206febe7ce6c8279674f1b)
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gc7000nu has only clk2x core input, no external shader clock input,
currently gpu_3d_shader clock is set to the 2d bus clock mistakenly,
should set gpu_3d_shader config with dummy clock in gpu device,
also removed the unused gpu2d_shader_clock setting from dts.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit 021b397e2594a37987d852a382f90bf0559fcf30)
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add heartbeat device node to add suspend/resume in
arch/arm/mach-imx/pm-rpmsg.c
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Add CPU setpoints property on i.MX7ULP A0 part, the setpoints table is a preliminary
one, will update it according to the datasheet when the final one is available.
The setpoints we can currently used is as below:
416072 KHz/0.925V,
531648 KHz/1.025V;
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Correct this spelling mistake error for lpi2c5 node.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
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Add ocotp node.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The untrimmed chip firc clock is 50Mhz after manually tuning.
Now the trimmed chip firc clock is stable to 48Mhz, so change
the lpuart module clock rate to 48Mhz.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add dts support for mipi dsi module on imx7ulp-evk board.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 51584bcf07c6e97631bd22ed7eeb8bd14cbfc61a)
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On imx7ulp-evk board, the SD slot on base board is conflict with BT/WiFi.
This patch seperate the usdhc1 from imx7ulp-evk.dts, and create new dts.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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Add SD3.0 support for usdhc0 on imx7ulp-evk board. Currently the
usdhc0 root clock is 158.4MHz.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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Add one more dts for QSPI on i.MX7ULP1 for mfgtool purpose.
Signed-off-by: Han Xu <han.xu@nxp.com>
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According to test, 0x8 is better than 0x10.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Add USBOTG1 support, we use GPIO as ID function for dual-role switch.
Besides, #define <dt-bindings/gpio/gpio.h> to imx7ulp.dtsi since
lots of boards may need it.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Enable ion driver on imx7ulp
Signed-off-by: Song Bing <bing.song@nxp.com>
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Adjust suspend ocram location for i.MX7ULP, since previous
location is used by M4.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Enable rpmsg/mu support on i.mx7ulp, since some mu register and
rmpsg buffer different as before
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Disable i.MX7ULP's IOMUXC now since there is no module
using it and after kernel boot up, below failed message
will come out:
imx7ulp-pinctrl 4103d000.iomuxc: fail to probe dt properties
imx7ulp-pinctrl: probe of 4103d000.iomuxc failed with error -22
Any module who needs it can enable it anytime.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add Murata 1DX wifi/bt for evk board.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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There are 2 usdhc instances on i.MX7ULP, previous
usdhc1 should be usdhc0, now add the correct usdhc1 node.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add GPIO (PCTLC,D,E,F) support
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Add 'timeout-sec' property for wdog node of i.MX7ULP.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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As FIRC may be NOT accurate enough and it also can
be disabled when M4 goes into VLPR mode, so using
OSC as TMP clock parent is better.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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On i.MX7ULP B0 chip, SNVS is located in M4 domain,
remove it from dtsi.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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According to reference mannual, there should be also an ipg clock,
so add it.
Cc: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
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Add i.MX7ULP dtsi support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Gan Yuchou <yuchou.gan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
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