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path: root/arch/arm/boot/dts/r8a7792.dtsi
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2016-09-05ARM: dts: r8a7792: add QSPI supportSergei Shtylyov
Define the generic R8A7792 part of the QSPI device node. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-09-05ARM: dts: r8a7792: add QSPI clockSergei Shtylyov
Describe the QSPI clock in the R8A7792 device tree. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-23ARM: dts: r8a7792: add VSP1V supportSergei Shtylyov
Describe 3 instances (VSPS, VSPD0, and VSPD1) of the VSP1V in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-23ARM: dts: r8a7792: add VSP1V clocksSergei Shtylyov
Describe the VSP1V clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add DU supportSergei Shtylyov
Define the generic R8A7792 part of the DU device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add DU clocksSergei Shtylyov
Describe the DU0/1 clocks and their parent, ZX clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: fix misindented lineSergei Shtylyov
Commit 2a0900655d5e (ARM: dts: r8a7792: add I2C support) had a wrongly indented line at the end of the "aliases" subnode -- fix it. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add VIN supportSergei Shtylyov
Define the generic R8A7792 parts of the VIN[0-5] device nodes. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add VIN clocksSergei Shtylyov
Describe the VIN[0-5] clocks and their parent, ZG clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add I2C supportSergei Shtylyov
Define the generic R8A7792 parts of the I2C[0-5] device nodes. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add I2C clocksSergei Shtylyov
Describe the I2C[0-5] clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add SDHI supportSergei Shtylyov
Define the generic R8A7792 part of the SDHI0 device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add SD clocksSergei Shtylyov
Describe the SDHI0 clock and its parent, SD clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08ARM: dts: r8a7792: add CAN supportSergei Shtylyov
Define the generic R8A7792 parts of the CAN0/1 device nodes. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08ARM: dts: r8a7792: add CAN clocksSergei Shtylyov
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and the external clock fed on the CAN_CLK pin. Describe those clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08ARM: dts: r8a7792: add EtherAVB supportSergei Shtylyov
Define the generic R8A7792 part of the EtherAVB device node. Based on the commit 89aac8af1a60 ("ARM: dts: r8a7794: add EtherAVB support"). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08ARM: dts: r8a7792: add EtherAVB clocksSergei Shtylyov
Add the EtherAVB clock and its parent, HP clock to the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08ARM: dts: r8a7792: add GPIO supportSergei Shtylyov
Describe all 12 GPIO controllers in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08ARM: dts: r8a7792: add GPIO clocksSergei Shtylyov
Describe the GPIO clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-08ARM: dts: r8a7792: add PFC supportSergei Shtylyov
Define the generic R8A7792 part of the PFC device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-07-15ARM: dts: r8a7792: remove ADSP clockSergei Shtylyov
Simon Horman told me that R8A7792 has ADSP clock based on an incorrect table in the most recent R-Car gen2 manual. But when I received that manual I discovered that this is false: R8A7792 is the only Gen 2 SoC that doesn't have ADSP at all. Accordingly remove the ADSP clock from DT for the r8a7792. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-07-15ARM: dts: r8a7792: add PLL1 divided by 2 clockSergei Shtylyov
Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the latter hasn't been added to the R8A7792 device tree. This patch corrects that oversight. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-30ARM: dts: r8a7792: add SMP supportSergei Shtylyov
Add the device tree nodes for the Advanced Power Management Unit (APMU) and the second Cortex-A15 CPU core. Use the "enable-method" prop to point out that the APMU should be used for the SMP support. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-24ARM: dts: r8a7792: add JPU supportSergei Shtylyov
Describe JPEG Processing Unit (JPU) in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-24ARM: dts: r8a7792: add JPU clocksSergei Shtylyov
Add JPU clock and its parent, M2 clock to the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-16ARM: dts: r8a7792: add IRQC supportSergei Shtylyov
Describe the IRQC interrupt controller in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-16ARM: dts: r8a7792: add [H]SCIF supportSergei Shtylyov
Describe [H]SCIFs in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-16ARM: dts: r8a7792: add SYS-DMAC supportSergei Shtylyov
Describe SYS-DMAC0/1 in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-16ARM: dts: r8a7792: initial SoC device treeSergei Shtylyov
The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC, and the required clock descriptions. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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