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2011-12-21ARM: gic: Use affinity hint to set multiple CPUs for IRQAlex Frid
GIC IRQ affinity is currently set to one CPU only - the 1st cpu in the requested mask. This commit adds option to set IRQ affinity to all cpus present in affinity_hint and requested masks. The option is enabled by default on Tegra architecture starting with Tegra3. (cherry picked from commit 09f7ef4f28a6e18188649c40848252bc18a6646c) Change-Id: I0d655f1d39170382f3372294172ed6d02dc0ad49 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/69328 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-11-30ARM: gic: Allow gic arch extensions to provide irqchip flagsColin Cross
Tegra can benefit from the IRQCHIP_MASK_ON_SUSPEND flag, allow it to be passed to the gic irq chip. Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: gic: Use cpu pm notifiers to save gic stateColin Cross
Signed-off-by: Colin Cross <ccross@android.com>
2011-07-26Merge branch 'next/devel' of ↵Linus Torvalds
ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits) ARM: S5P64X0: External Interrupt Support ARM: EXYNOS4: Enable MFC on Samsung NURI ARM: EXYNOS4: Enable MFC on universal_c210 ARM: S5PV210: Enable MFC on Goni ARM: S5P: Add support for MFC device ARM: EXYNOS4: Add support FIMD on SMDKC210 ARM: EXYNOS4: Add platform device and helper functions for FIMD ARM: EXYNOS4: Add resource definition for FIMD ARM: EXYNOS4: Change devname for FIMD clkdev ARM: SAMSUNG: Add IRQ_I2S0 definition ARM: SAMSUNG: Add platform device for idma ARM: EXYNOS4: Add more registers to be saved and restored for PM ARM: EXYNOS4: Add more register addresses of CMU ARM: EXYNOS4: Add platform device for dwmci driver ARM: EXYNOS4: configure rtc-s3c on NURI ARM: EXYNOS4: configure MAX8903 secondary charger on NURI ARM: EXYNOS4: configure ADC on NURI ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs ... Fix up tons of silly conflicts: - arch/arm/mach-davinci/include/mach/psc.h - arch/arm/mach-exynos4/Kconfig - arch/arm/mach-exynos4/mach-smdkc210.c - arch/arm/mach-exynos4/pm.c - arch/arm/mach-imx/mm-imx1.c - arch/arm/mach-imx/mm-imx21.c - arch/arm/mach-imx/mm-imx25.c - arch/arm/mach-imx/mm-imx27.c - arch/arm/mach-imx/mm-imx31.c - arch/arm/mach-imx/mm-imx35.c - arch/arm/mach-mx5/mm.c - arch/arm/mach-s5pv210/mach-goni.c - arch/arm/mm/Kconfig
2011-07-21ARM: GIC: avoid routing interrupts to offline CPUsRussell King
The irq_set_affinity() method can be called with masks which include offline CPUs. This allows offline CPUs to have interrupts routed to them by writing to /proc/irq/*/smp_affinity after hotplug has taken a CPU offline. Fix this by ensuring that we select a target CPU present in both the required affinity and the online CPU mask. Ensure that we return IRQ_SET_MASK_OK (which happens to be 0) on success to ensure generic code copies the new mask into the irq_data structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-21ARM: CPU hotplug: fix abuse of irqdesc->nodeRussell King
irqdesc's node member is supposed to mark the numa node number for the interrupt. Our use of it is non-standard. Remove this, replacing the functionality with a test of the affinity mask. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-20ARM: GIC: move gic_chip_data structure declaration to headerChanghwan Youn
Since Samsung EXYNOS4210 cannot support register banking in GIC, so needs to update CPU interface base address. The 'gic_chip_data' is used for it, this patch moves gic_chip_data structure declaraton to arch/arm/include/asm/hardware/gic.h to use it. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-05-11ARM: GIC: Convert GIC library to use the IO relaxed operationsSantosh Shilimkar
The GIC register accesses today make use of readl()/writel() which prove to be very expensive when used along with mandatory barriers. This mandatory barriers also introduces an un-necessary and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC IO accesses from CPU are direct and doesn't go through L2X0 write buffer. A DSB before writel_relaxed() in gic_raise_softirq() is added to be compliant with the Barrier Litmus document - the mailbox scenario. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com>
2011-05-11ARM: gic: use handle_fasteoi_irq for SPIsWill Deacon
Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling. On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux. This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip. Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary. Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs). Tested-and-reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Tested-and-acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-03-29arm: Fold irq_set_chip/irq_set_handlerThomas Gleixner
Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-29arm: Reorder irq_set_ function callsThomas Gleixner
Reorder irq_set_chip() irq_set_chip_data() irq_set_handler() to irq_set_chip() irq_set_handler() irq_set_chip_data() so the next patch can combine irq_set_chip() and irq_set_handler() to irq_set_chip_and_handler(). Automated conversion with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-29arm: Cleanup the irq namespaceThomas Gleixner
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-29arm: gic: Use proper accessor functionsThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-09ARM: 6777/1: gic: Add hooks for architecture specific extensionsSantosh Shilimkar
Few architectures combine the GIC with an external interrupt controller. On such systems it may be necessary to update both the GIC registers and the external controller's registers to control IRQ behavior. This can be addressed in couple of possible methods. 1. Export common GIC routines along with 'struct irq_chip gic_chip' and allow architectures to have custom function by override. 2. Provide architecture specific function pointer hooks within GIC library and leave platforms to add the necessary code as part of these hooks. First one might be non-intrusive but have few shortcomings like arch needs to have there own custom gic library. Locks used should be common since it caters to same IRQs etc. Maintenance point of view also it leads to multiple file fixes. The second probably is cleaner and portable. It ensures that all the common GIC infrastructure is not touched and also provides archs to address their specific issue. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Colin Cross <ccross@android.com> Tested-by: Colin Cross <ccross@android.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-23ARM: irq migration: update GIC migration codeRussell King
This cleans up after the conversion to irq_data. Rename the function to match the method, and remove the now useless lookup of the irq descriptor which is never used. Move the bitmask calculation out of the irq_controller_lock region. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-13ARM: gic: irq_data conversion.Lennert Buytenhek
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Acked-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
2010-12-14ARM: GIC: move enablement of PPI interrupts to gic.cRussell King
Avoid adding nasty genirq-specific code to local timers to enable PPI interrupts. Instead, provide a gic function to do this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14ARM: GIC: move gic_data[] initialization into gic_init()Russell King
This avoids writing unnecessarily to gic_data[] from other CPUs, making this a mostly read-only variable. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14ARM: GIC: consolidate gic_cpu_base_addr to common GIC codeRussell King
Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_initRussell King
We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14ARM: GIC: provide a single initialization function for boot CPURussell King
Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-06ARM: 6524/1: GIC irq desciptor bug fixChao Xie
gic_set_cpu will directly use irq_desc[]. If CONFIG_SPARSE_IRQ is enabled, there is no irq_desc[]. So we need use irq_to_desc(irq) to get the descriptor for irq. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-11-30ARM: 6496/1: GIC: Do not try to register more then NR_IRQS interruptsPawel Moll
This change limits number of GIC-originating interrupts to the platform maximum (defined by NR_IRQS) while still initialising all distributor registers. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-11-12ARM: GIC: don't disable software generated interruptsRussell King
Software generated interrupts (SGI) are used for IPIs by the kernel. While previous revisions of the GIC hardware were specified not to implement enable bits for SGIs, more recent hardware is now permitted to implement these bits in a per-CPU banked register. The priority registers for the PPI and SGIs are also per-CPU banked registers, so ensure that these are also appropriately initialized. Reported-by: Scott Valentine <svalentine@concentris-systems.com> Acked-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-06GIC: Dont disable INT in ack callbackAbhijeet Dharmapurikar
Masking in the ack callback fails to work with handle_percpu_irq and handle_edge_irq. The interrupt stays disabled after the first invocation since percpu and edge irq do not unmask an interrupt after handling it. For handle_level_irq masking in the ack is redundant because ack is always called after mask in the mask_ack function. Masking in the ack function is required only when __do_IRQ was used instead of flow handlers, but using __do_IRQ has been deprecated. Remove the masking of interrupt from the ack callback. Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-06-16ARM: 6150/1: gic: implement set_typeRabin Vincent
Implement set_type() to allow configuration of the trigger type. Cc: Abhijeet Dharmapurikar <adharmap@quicinc.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-06-19[ARM] 5556/1: Fix the irq_desc.cpu referencesCatalin Marinas
The cpu member of struct irq_desc was recently renamed to node. The patch renames the ARM references to the old member. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-06-01Merge branch 'linus' into irq/numaIngo Molnar
Conflicts: arch/mips/sibyte/bcm1480/irq.c arch/mips/sibyte/sb1250/irq.c Merge reason: we gathered a few conflicts plus update to latest upstream fixes. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-05-17[ARM] smp: fix cpumask usage in ARM SMP codeRussell King
The ARM SMP code wasn't properly updated for the cpumask changes, which results in smp_timer_broadcast() broadcasting ticks to non-online CPUs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-04-28irq: change ->set_affinity() to return statusYinghai Lu
according to Ingo, change set_affinity() in irq_chip should return int, because that way we can handle failure cases in a much cleaner way, in the genirq layer. v2: fix two typos [ Impact: extend API ] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: linux-arch@vger.kernel.org LKML-Reference: <49F654E9.4070809@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-12-13cpumask: make irq_set_affinity() take a const struct cpumaskRusty Russell
Impact: change existing irq_chip API Not much point with gentle transition here: the struct irq_chip's setaffinity method signature needs to change. Fortunately, not widely used code, but hits a few architectures. Note: In irq_select_affinity() I save a temporary in by mangling irq_desc[irq].affinity directly. Ingo, does this break anything? (Folded in fix from KOSAKI Motohiro) Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Acked-by: Ingo Molnar <mingo@redhat.com> Cc: ralf@linux-mips.org Cc: grundler@parisc-linux.org Cc: jeremy@xensource.com Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
2008-09-06[ARM] Convert asm/io.h to linux/io.hRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-20[ARM] spelling fixesSimon Arlott
Spelling fixes in arch/arm/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-17[ARM] gic: Fix gic cascade irq handlingRussell King
No need for the cascade irq function to have a "fastcall" annotation. Fix the range checking for valid IRQ numbers - comparing the value returned by the GIC with NR_IRQS is meaningless since we translate the GIC irq number to a Linux IRQ number afterwards. Check the GIC returned IRQ number is within limits first, then add the IRQ offset, and only then compare with NR_IRQS. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-15[ARM] 4108/2: Allow multiple GIC interrupt controllers in a systemCatalin Marinas
The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-30[ARM] Remove compatibility layer for ARM irqsRussell King
set_irq_chipdata -> set_irq_chip_data get_irq_chipdata -> get_irq_chip_data do_level_IRQ -> handle_level_irq do_edge_IRQ -> handle_edge_irq do_simple_IRQ -> handle_simple_irq irqdesc -> irq_desc irqchip -> irq_chip Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-08-01[ARM] 3739/1: genirq updates: irq_chip, add and use irq_chip.nameDavid Brownell
Patch from David Brownell ARM genirq cleanups/updates: - Start switching platforms to newer APIs * use "irq_chip" name, not "irqchip" * providing irq_chip.name - Show irq_chip.name in /proc/interrupts, like on x86. This update a bit more than half of the ARM code. The irq_chip.name values were chosen to match docs (if I have them) or be otherwise obvious ("FPGA", "CPLD", or matching the code). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01[ARM] 3686/1: ARM: arm/common: convert irq handlingThomas Gleixner
Patch from Thomas Gleixner From: Thomas Gleixner <tglx@linutronix.de> Convert the files in arch/arm/common to use the generic irq handling functions. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-30[ARM] 2942/1: Fix the warning in arch/arm/common/gic.cCatalin Marinas
Patch from Catalin Marinas The warning is caused by the gic_set_cpu() function being defined but not used if CONFIG_SMP is not defined. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-31[ARM] 2868/1: Include linux/cpumask.h in arch/arm/common/gic.cCatalin Marinas
Patch from Catalin Marinas Minor compilation error fix. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-18[ARM] Add support for ARM GICRussell King
Add support for the ARM Generic Interrupt Controller. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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