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path: root/arch/arm/include/asm/outercache.h
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2012-07-19ARM: mm: cache-l2x0: Implement outer_clean_all()Kirill Artamonov
There is already implemented full outer clean routine in arch/arm/mm/cache-l2x0.c. Make it possible to use it through outer_cache interface, like other outer maintenance functions. bug 983964 Change-Id: I47f1fad536c151c255e6a42d6517114c334ddfef Reviewed-on: http://git-master/r/116074 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com> Tested-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Justin Paver <jpaver@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-03-20Merge branches 'fixes', 'pgt-next' and 'versatile' into develRussell King
2011-03-09ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corruptiSantosh Shilimkar
PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. Workaround: Disable Write-Back and Cache Linefill (Debug Control Register) Clean & Invalidate by Way (0x7FC) Re-enable Write-Back and Cache Linefill (Debug Control Register) This patch also removes any OMAP dependency on PL310 Errata's Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-15ARM: 6671/1: LPAE: use phys_addr_t instead of unsigned long in outercache ↵Will Deacon
functions The unsigned long datatype is not sufficient for mapping physical addresses >= 4GB. This patch ensures that the phys_addr_t datatype is used to represent physical addresses when passed to the outer cache functions. Note that the definitions in struct outer_cache_fns remain as unsigned long because there are currently no outer cache implementations supporting physical addresses wider than 32-bits. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-26arm: Disable outer (L2) cache in kexecThomas Gleixner
kexec does not disable the outer cache before disabling the inner caches in cpu_proc_fin(). So L2 is enabled across the kexec jump. When the new kernel enables chaches again, it randomly crashes. Disabling L2 before calling cpu_proc_fin() cures the problem. Disabling L2 requires the following new functions: flush_all(), inv_all() and disable(). Add them to outer_cache_fns and call them from the kexec code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
2010-03-25ARM: 5994/1: ARM: Add outer_cache_fns.sync function pointer (2/4)Catalin Marinas
This patch introduces the outer_cache_fns.sync function pointer together with the OUTER_CACHE_SYNC config option that can be used to drain the write buffer of the outer cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-03-25ARM: 5993/1: ARM: Move the outer_cache definitions into a separate file (1/4)Catalin Marinas
To avoid #include collisions with subsequent patches in the series, this patch moves the outer_cache definitions to a separate asm/outercache.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>