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2012-11-26ARM: 7115/4: move __exception and friends to asm/exception.hJamie Iles
The definition of __exception_irq_entry for CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a circular dependency with it's current home in asm/system.h. Create asm/exception.h and update all current users. v4: - rebase to rmk/for-next v3: - remove redundant includes of linux/ftrace.h v2: - document the usage restricitions of __exception* Cc: Zoltan Devai <zdevai@gmail.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-09-10ARM: mutex: use generic atomic_dec-based implementation for ARMv6+Will Deacon
Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+") removed the barrier-less, ARM-specific mutex implementation in favour of the generic xchg-based code. Since then, a bug was uncovered in the xchg code when running on SMP platforms, due to interactions between the locking paths and the MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place lock in contended state after fastpath_lock failure"), however, the atomic_dec-based mutex algorithm is now marginally more efficient for ARM (~0.5% improvement in hackbench scores on dual A15). This patch moves ARMv6+ platforms to the atomic_dec-based mutex code. Change-Id: I8f64e98ccb61cc1cb9cb68ee15e55d8a792792f5 Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-on: http://git-master/r/130941 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-10ARM: 7467/1: mutex: use generic xchg-based implementation for ARMv6+Will Deacon
The open-coded mutex implementation for ARMv6+ cores suffers from a severe lack of barriers, so in the uncontended case we don't actually protect any accesses performed during the critical section. Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec code but optimised to remove a branch instruction, as the mutex fastpath was previously inlined. Now that this is executed out-of-line, we can reuse the atomic access code for the locking (in fact, we use the xchg code as this produces shorter critical sections). This patch uses the generic xchg based implementation for mutexes on ARMv6+, which introduces barriers to the lock/unlock operations and also has the benefit of removing a fair amount of inline assembly code. Change-Id: I58e3ca4d2740a834d30b54fc35742fa2df7792ad Cc: <stable@vger.kernel.org> : 0bce9c46: mutex: Place lock in contended... Cc: <stable@vger.kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nicolas Pitre <nico@linaro.org> Reported-by: Shan Kang <kangshan0910@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-on: http://git-master/r/130940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-08-28ARM: cache-l2x0: fix L2 maintenance for R3P1_50Kirill Artamonov
Do flush and clear by set/way instead of by-way by enabling errata 727915 for pl310 revision R3P1_50. By-way maintenance doesn't work with enabled lp2_in_idle on Tegra3 platform using R3P1_50 revision of pl310. Debug register access causes hang when CONFIG_TRUSTED_FOUNDATIONS is defined. Don't access those regeisters if CONFIG_TRUSTED_FOUNDATIONS is defined. bug 983964 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: I76a3a9ef9dbcf86140ee26752202bf25542144e6 Reviewed-on: http://git-master/r/125153 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Tested-by: Antti Miettinen <amiettinen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2012-08-01ARM: 7017/1: Use generic BUG() handlerVishal Singh
ARM uses its own BUG() handler which makes its output slightly different from other archtectures. One of the problems is that the ARM implementation doesn't report the function with the BUG() in it, but always reports the PC being in __bug(). The generic implementation doesn't have this problem. Currently we get something like: kernel BUG at fs/proc/breakme.c:35! Unable to handle kernel NULL pointer dereference at virtual address 00000000 ... PC is at __bug+0x20/0x2c With this patch it displays: kernel BUG at fs/proc/breakme.c:35! Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP ... PC is at write_breakme+0xd0/0x1b4 This implementation uses an undefined instruction to implement BUG, and sets up a bug table containing the relevant information. Many versions of gcc do not support %c properly for ARM (inserting a # when they shouldn't) so we work around this using distasteful macro magic. v1: Initial version to replace existing ARM BUG() implementation with something more similar to other architectures. v2: Add Thumb support, remove backtrace whitespace output changes. Change to use macros instead of requiring the asm %d flag to work (thanks to Dave Martin <dave.martin@linaro.org>) v3: Remove old BUG() implementation in favor of this one. Remove the Backtrace: message (will submit this separately). Rebase to linux-2.6.git master. v4: Allow BUGS in modules (these were not reported correctly in v3) (thanks to Stephen Boyd <sboyd@codeaurora.org> for suggesting that.) Remove __bug() as this is no longer needed. v5: Add %progbits as the section flags. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 87e040b6456fd3416a1f6831c1eedaef5c0a94ff) Change-Id: Ic7692288dff6e4a15c732eb030295bd196a87fb4 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/117356 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Vishal Singh <vissingh@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com> (cherry picked from commit 6708ffd0b44f4d09d8fe745471641545655091fb) Reviewed-on: http://git-master/r/119328 Reviewed-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-07-19ARM: mm: cache-l2x0: Implement outer_clean_all()Kirill Artamonov
There is already implemented full outer clean routine in arch/arm/mm/cache-l2x0.c. Make it possible to use it through outer_cache interface, like other outer maintenance functions. bug 983964 Change-Id: I47f1fad536c151c255e6a42d6517114c334ddfef Reviewed-on: http://git-master/r/116074 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com> Tested-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Justin Paver <jpaver@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-06-13Avoid aliasing mappings in DMA coherent allocatorManoj Chourasia
Avoid multiple mappings with DMA coherent/writecombine allocator by pre- allocating the mappings, and removing that memory from the system memory mapping. (See previous discussions on linux-arm-kernel as to why this is bad.) NB1: By default, we preallocate 2MB for DMA coherent, and 2MB for write combine memory, rather than 1MB for each in case 1MB is not sufficient for existing platform usage. Platforms have the option of shrinking this down to 1MB DMA / 1MB WC (or even 2MB DMA / 0MB WC) if they so wish. The DMA memory must be a multiple of 1MB, the write combine memory must also be a multiple of 1MB, and the two together must be a multiple of 2MB. NB2: On ARMv6/7 where we use 'normal uncacheable' memory for both DMA and WC, the two pools are combined into one, as was the case with the previous implementation. The down side to this change is that the memory is permanently set aside for DMA purposes, but I believe that to be unavoidable if we are to avoid the possibility of the cache getting in the way on VIPT CPUs. This removes the last known offender (at this time) from the kernel. Given that DMA memory is fully coherent by this patch, cache invalidation/clean is not required and so, we skip cache related activities for the memory managed by the DMA layer. The bus address -> virtual address conversion normally used in the calling path and the fact that we remove kernel static mapping corresponding to the DMA buffers leads to exceptions otherwise. bug 876019 bug 965047 bug 987589 Change-Id: I72beb386605aafe1a301494a95a67d094ea6b2e4 Signed-off-by: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/106212 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-04-19Revert "ARM: pm: preallocate a page table for suspend/resume"Sang-Hun Lee
This reverts commit 55f0f45a45263ba26bd473f50f867d29dd836e46. Bug 967887 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Change-Id: I036e0bd4e391a17dec8fa0fe86da7eb6b98d503a Reviewed-on: http://git-master/r/96795 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-19Revert "ARM: pm: convert some assembly to C"Sang-Hun Lee
This reverts commit 11a2e1bb69affe9e8273bc6d1452cd9282ddd27a. Bug 967887 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Change-Id: Ibace368a190a14d24e1cc963e8e2a7ed6fdbba6a Reviewed-on: http://git-master/r/96791 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-05ARM: pm: convert some assembly to CRussell King
Convert some of the sleep.S guts to C code, which makes it easier to use our macros and to add L2 cache handling. We provide a helper function, __cpu_suspend_save(), which deals with saving the common state, setting up for resume, and flushing caches. The remainder left as assembly code is the saving of the CPU general purpose registers, and allocating space on the stack to save the CPU specific registers and resume state. Change-Id: I0e8bc196fa7302cfe52c17d39675dadf25ea1004 Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/85728 Reviewed-by: Automatic_Commit_Validation_User
2012-04-05ARM: pm: preallocate a page table for suspend/resumeRussell King
Preallocate a page table and setup an identity mapping for the MMU enable code. This means we don't have to "borrow" a page table to do this, avoiding complexities with L2 cache coherency. Change-Id: I625d3622359e961e4f358171e9a82b51bcecf9c2 Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/85671 Reviewed-by: Automatic_Commit_Validation_User
2012-04-03dmaengine: move last completed cookie into generic dma_chan structureRussell King - ARM Linux
Every DMA engine implementation declares a last completed dma cookie in their private dma channel structures. This is pointless, and forces driver specific code. Move this out into the common dma_chan structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com> cherry-picked from mainline 4d4e58de32a192fea65ab84509d17d199bd291c8 Change-Id: Ib653bcfa5f492986946fd34006a8de3090db0441 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/93778
2012-03-30arm: include: make module space configurableMursalin Akon
Make the module space a configurable option. The default value remains 16. The main goal of this CL is to enable large module, such as resman module of nvidia. Change-Id: I8a775a6a23c1a75562917d8ab8e4bbe29f08d7e5 Signed-off-by: Mursalin Akon <makon@nvidia.com> (cherry picked from commit 40aaad75bd32822137033fc7972d41ee30ff7bc9) Reviewed-on: http://git-master/r/91322 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Eric Brower <ebrower@nvidia.com> Reviewed-by: Allen Martin <amartin@nvidia.com>
2012-03-02arm: cache: fix v7 boot with lockdep enabledPrashant Gaikwad
Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Change-Id: I1110a7e07fa3f96022b2e198488fa698c91e2642 Reviewed-by: Nicolas Pitre <(address hidden)> Acked-by: Stephen Boyd <(address hidden)> Cc: Catalin Marinas <(address hidden)> Cc: stable@vger.kernel.org Signed-off-by: Rabin Vincent <(address hidden)> Reviewed-on: http://git-master/r/86779 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2012-02-18ARM: 7240/1: Make ARCH_NR_GPIO a Kconfig variablePeter De Schrijver (NVIDIA)
Change ARCH_NR_GPIO into a Kconfig variable as suggested by Russel King. This makes ARCH_NR_GPIO single zImage friendly. The default value for tegra is defined as well. Upstream v3.3 commit 44986ab056076e9dc9fb9f8b4729afef7fa72616 Change-Id: Ia1ae996fc5209b22eb7ea942d90e86cfae56318e Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-on: http://git-master/r/83219 Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-30arm: tegra: whistler: Increase Carveout Memory to 160MVaibhav Gorde
Limited carveout memory gives Out of Memory errors for 1080p camera preview. Even when camera app runs 640x480 preview carveout memory almost all of carveout memory (127/128) gets used. bug 907782 bug 911767 Reviewed-on: http://git-master/r/69492 Change-Id: I993d656910a1853f22719411553dbec3edb9f53f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77311 Reviewed-by: Automatic_Commit_Validation_User
2011-12-22arm: include: asm: add 160M to sizes.hVarun Wadekar
Change-Id: I6657a60476af2d6c63ecb69ab91fd8132f2603bb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-22arm: tegra: whistler: Increase Carveout Memory to 160MVaibhav Gorde
Limited carveout memory gives Out of Memory errors for 1080p camera preview. Even when camera app runs 640x480 preview carveout memory almost all of carveout memory (127/128) gets used. bug 907782 bug 911767 Change-Id: Ibb8226c1fb928b7e4344f8959072973da93ecae5 Reviewed-on: http://git-master/r/69492 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-11-30Merge branch 'korg-android-tegra-3.1' into after-upstream-androidDan Willemsen
Conflicts: arch/arm/mach-tegra/Kconfig arch/arm/mach-tegra/board-ventana.c drivers/misc/Kconfig drivers/video/tegra/dc/hdmi.c Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2011-11-30gcov-kernel: Add ARM eABI supportJuha Tukkinen
Based on work by George G. Davis <gdavis@mvista.com>. See http://lwn.net/Articles/390419/ Change-Id: I8df700d20a154e179f8cf6cdfe4015efc5d384f2 Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/62998 Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R2607a46c8bd1e521abe44a57a5ccf7317333d6c9
2011-11-30arm: mm: change_page_attr supportVinod Rex
bug 865816 Adapted from x86 change_page_attr() implementation Change-Id: I398c9d460b841484de4fcfcac10ffffdf49a4a5a Reviewed-on: http://git-master/r/56769 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: Rddeccf358c948ba84af52316f084814ae53dca5e
2011-11-30ARM: remove unnecessary dcache_clean_areaHeechul Yun
Cortex-A9 has PIPT D-cache which do not require clean the cache on creating page table. Original-Change-Id: I42d528be83ea8def96045c7e575c7b3ed95f5980 Reviewed-on: http://git-master/r/40505 Reviewed-by: Heechul Yun <hyun@nvidia.com> Tested-by: Heechul Yun <hyun@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R214ce4b138abb18e1cfe79465087c39ead248d72
2011-11-30ARM: Add 'card_present' state to mmc_platfrom_dataDmitry Shmidt
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com> Rebase-Id: R326381df3f4188cc1f700eb210c12b483afe9e77
2011-11-30Recreate asm/mach/mmc.h include fileColin Cross
Change-Id: I9f10244b0603f7842b8504a16124d40dc4a71ed2 Signed-off-by: Colin Cross <ccross@android.com> Rebase-Id: Rdc49da8123b4e700f2987a4a5ea19ad2b29ff1d6
2011-11-30Merge branch 'korg-android-3.1' into korg-android+linux-tegra-3.1Dan Willemsen
Conflicts: arch/arm/mm/cache-l2x0.c drivers/misc/Kconfig drivers/misc/Makefile Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2011-11-30ARM: common: fiq_debugger: add suspend/resume handlersDima Zavin
Change-Id: If6eb75059fdf4867eb9a974d60b9d50e5e3350d4 Signed-off-by: Dima Zavin <dima@android.com>
2011-11-30ARM: common: fiq_debugger: add uart_enable/disable platform callbacksDima Zavin
This allows the platform specific drivers to properly enable and disable the uart at the appropriate times. On some platforms, just managing the clock is not enough. Change-Id: I5feaab04cfe313a4a9470ca274838676b9684201 Signed-off-by: Dima Zavin <dima@android.com>
2011-11-30ARM: smp: implement arch_trigger_all_cpus_backtrace using IPIDima Zavin
Based on a rough patch by frank.rowand@am.sony.com Since ARM doesn't have an NMI (fiq's are not always available), send an IPI to all other CPUs (current cpu prints the stack directly) to capture a backtrace. Change-Id: I8b163c8cec05d521b433ae133795865e8a33d4e2 Signed-off-by: Dima Zavin <dima@android.com>
2011-11-30ARM: cache-l2x0: update workaround for PL310 errata 727915Colin Cross
ARM errata 727915 for PL310 has been updated to include a new workaround required for PL310 r2p0 for l2x0_flush_all, which also affects l2x0_clean_all in my testing. For r2p0, clean or flush each set/way individually. For r3p0 or greater, use the debug register for cleaning and flushing. Requires exporting the cache_id, sets and ways detected in the init function for later use. Change-Id: I215055cbe5dc7e4e8184fb2befc4aff672ef0a12 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: etm: Support multiple ETMs/PTMs.Arve Hjønnevåg
If more than one ETM or PTM are present, configure all of them and enable the formatter in the ETB. This allows tracing on dual core systems (e.g. omap4). Change-Id: I028657d5cf2bee1b23f193d4387b607953b35888 Signed-off-by: Arve Hjønnevåg <arve@android.com>
2011-11-30ARM: etm: Configure data tracingArve Hjønnevåg
The old code enabled data tracing, but did not configure the range. We now configure it to trace all data addresses by default, and add a trace_data_range attribute to change the range or disable data tracing. Change-Id: I9d04e3e1ea0d0b4d4d5bcb93b1b042938ad738b2 Signed-off-by: Arve Hjønnevåg <arve@android.com>
2011-11-30ARM: Add 'card_present' state to mmc_platfrom_dataDmitry Shmidt
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
2011-11-30Recreate asm/mach/mmc.h include fileColin Cross
Change-Id: I9f10244b0603f7842b8504a16124d40dc4a71ed2 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: Add generic fiq serial debuggerIliyan Malchev
Change-Id: Ibb536c88f0dbaf4766d0599296907e35e42cbfd6 Signed-off-by: Iliyan Malchev <malchev@google.com> Signed-off-by: Arve Hjønnevåg <arve@android.com>
2011-11-30ARM: Add fiq_glueArve Hjønnevåg
Change-Id: I27d2554e07d9de204e0a06696d38db51608d9f6b Signed-off-by: Arve Hjønnevåg <arve@android.com> Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30[ARM] Do not call flush_cache_user_range with mmap_sem heldDima Zavin
We can't be holding the mmap_sem while calling flush_cache_user_range because the flush can fault. If we fault on a user address, the page fault handler will try to take mmap_sem again. Since both places acquire the read lock, most of the time it succeeds. However, if another thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in between the call to flush_cache_user_range and the fault, the down_read in do_page_fault will deadlock. Also, since we really can't be holding the mmap_sem while calling flush_cache_user_range AND vma is actually unused by the flush itself, get rid of vma as an argument. Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106 Signed-off-by: Dima Zavin <dima@android.com>
2011-11-30[ARM] mm: add memory type for inner-writebackColin Cross
For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906 Signed-off-by: Gary King <gking@nvidia.com> Conflicts: arch/arm/include/asm/pgtable.h arch/arm/mm/proc-v7.S
2011-11-30Revert "[ARM] mm: add page allocator for modifying cache attributes"Gary King
This reverts commit 54d414570432ce07fa1a14b657f53bed752e3d7e. Change-Id: I8e5cf6ef3555129da9741ef52a1e6a3a772ad588 Signed-off-by: Gary King <gking@nvidia.com>
2011-11-30[ARM] mm: add page allocator for modifying cache attributesGary King
ARM CPUs with speculative prefetching have undefined behaviors when the same physical page is mapped to two different virtual addresses with conflicting cache attributes. since many recent systems include IOMMU functionality (i.e., remapping of discontiguous physical pages into a virtually-contiguous address range for I/O devices), it is desirable to support allocating any available OS memory for use by the I/O devices. however, since many systems do not support cache coherency between the CPU and DMA devices, these devices are left with using DMA-coherent allocations from the OS (which severely limits the benefit of an IOMMU) or performing cache maintenance (which can be a severe performance loss, particularly on systems with outer caches, compared to using DMA-coherent memory). this change adds an API for allocating pages from the OS with specific cache maintenance properties and ensures that the kernel's mapping of the page reflects the desired cache attributes, in line with the ARMv7 architectural requirements Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0 Signed-off-by: Gary King <gking@nvidia.com>
2011-11-30[ARM] Add ARCH_PROVIDES_UDELAY config optionColin Cross
Change-Id: Ife690c9d055fc0f17a52d2b29048af5062a664a6 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: mm: cache-l2x0: Add support for re-enabling l2x0Colin Cross
Remove __init annotation from l2x0_init so it can be used to reinitialize the l2x0 after it has been reset during suspend. Only print the init messages the first time l2x0_init is called. Add l2x0_enable to re-enable the l2x0 after l2x0_disable if the l2x0 was not reset. l2x0_disable cannot use writel, as writel calls wmb(), and wmb() may call outer_cache_sync, which takes the same spinlock as l2x0_disable. Change-Id: Iaddedb4f582c7eeaef3cbe2a1e463787f0f809a4 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: gic: Use cpu pm notifiers to save gic stateColin Cross
Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: Add cpu power management notifiersColin Cross
During some CPU power modes entered during idle, hotplug and suspend, peripherals located in the CPU power domain, such as the GIC, localtimers, and VFP, may be powered down. Add a notifier chain that allows drivers for those peripherals to be notified before and after they may be reset. Signed-off-by: Colin Cross <ccross@android.com>
2011-10-15ARM: 7122/1: localtimer: add header linux/errno.h explicitlyShawn Guo
Per the text in Documentation/SubmitChecklist as below, we should explicitly have header linux/errno.h in localtimer.h for ENXIO reference. 1: If you use a facility then #include the file that defines/declares that facility. Don't depend on other header files pulling in ones that you use. Otherwise, we may run into some compiling error like the following one, if any file includes localtimer.h without CONFIG_LOCAL_TIMERS defined. arch/arm/include/asm/localtimer.h: In function ‘local_timer_setup’: arch/arm/include/asm/localtimer.h:53:10: error: ‘ENXIO’ undeclared (first use in this function) Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-26ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_opWill Deacon
The SMP implementation of __futex_atomic_op clobbers oldval with the status flag from the exclusive store. This causes it to always read as zero when performing the FUTEX_OP_CMP_* operation. This patch updates the ARM __futex_atomic_op implementations to take a tmp argument, allowing us to store the strex status flag without overwriting the register containing oldval. Cc: stable@kernel.org Reported-by: Minho Ban <mhban@samsung.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-17ARM: nommu: fix warning with checksyscalls.shRussell King
CALL scripts/checksyscalls.sh <stdin>:46:1: warning: "__IGNORE_migrate_pages" redefined In file included from <stdin>:2: arch/arm/include/asm/unistd.h:482:1: warning: this is the location of the previous definition This is caused because we define __IGNORE_migrate_pages to be 1, but in the case of nommu, it's defined to be empty. Fix this by just defining the __IGNORE_ symbols to be empty. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-07ARM: 7080/1: l2x0: make sure I&D are not locked down on initLinus Walleij
Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state. Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Cc: Rob Herring <robherring2@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Jan Rinze <janrinze@gmail.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-15ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.Srinivas Kandagatla
This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits. The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations. It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small) and also prints incorrect cachesize. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: stable@kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-08-12ARM: perf: make name of arm_pmu_type consistentMark Rutland
Commit f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed {release,reserve}_pmu to take an enum arm_pmu_type as a parameter, but inconsistently named the parameter `type' or `device'. It would be nice if these were consistent. This patch makes use of enum arm_pmu_type consistent, always using `type'. Related printks are updated, explicitly mentioning `type' also. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-08-12ARM: perf: fix prototype of release_pmuMark Rutland
Commit f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed the prototype of release_pmu, but missed the stub for when CONFIG_CPU_HAS_PMU is not selected by the platform. This patch changes the prototype of the stub, preventing possible build failures when CONFIG_CPU_HAS_PMU is not selected. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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