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This reverts commit 55f0f45a45263ba26bd473f50f867d29dd836e46.
Bug 967887
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Change-Id: I036e0bd4e391a17dec8fa0fe86da7eb6b98d503a
Reviewed-on: http://git-master/r/96795
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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This reverts commit 11a2e1bb69affe9e8273bc6d1452cd9282ddd27a.
Bug 967887
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Change-Id: Ibace368a190a14d24e1cc963e8e2a7ed6fdbba6a
Reviewed-on: http://git-master/r/96791
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Convert some of the sleep.S guts to C code, which makes it easier to
use our macros and to add L2 cache handling. We provide a helper
function, __cpu_suspend_save(), which deals with saving the common
state, setting up for resume, and flushing caches.
The remainder left as assembly code is the saving of the CPU general
purpose registers, and allocating space on the stack to save the CPU
specific registers and resume state.
Change-Id: I0e8bc196fa7302cfe52c17d39675dadf25ea1004
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85728
Reviewed-by: Automatic_Commit_Validation_User
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Preallocate a page table and setup an identity mapping for the MMU
enable code. This means we don't have to "borrow" a page table to
do this, avoiding complexities with L2 cache coherency.
Change-Id: I625d3622359e961e4f358171e9a82b51bcecf9c2
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85671
Reviewed-by: Automatic_Commit_Validation_User
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Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures. This is pointless, and
forces driver specific code. Move this out into the common dma_chan
structure.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
cherry-picked from mainline
4d4e58de32a192fea65ab84509d17d199bd291c8
Change-Id: Ib653bcfa5f492986946fd34006a8de3090db0441
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93778
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Make the module space a configurable option.
The default value remains 16. The main goal
of this CL is to enable large module, such as
resman module of nvidia.
Change-Id: I8a775a6a23c1a75562917d8ab8e4bbe29f08d7e5
Signed-off-by: Mursalin Akon <makon@nvidia.com>
(cherry picked from commit 40aaad75bd32822137033fc7972d41ee30ff7bc9)
Reviewed-on: http://git-master/r/91322
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
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Bootup with lockdep enabled has been broken on v7 since b46c0f74657d
("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").
This is because v7_setup (which is called very early during boot) calls
v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
ends up attempting to call into lockdep C code (trace_hardirqs_off())
when we are in no position to execute it (no stack, MMU off).
Fix this by using a notrace variant of save_and_disable_irqs. The code
already uses the notrace variant of restore_irqs.
Change-Id: I1110a7e07fa3f96022b2e198488fa698c91e2642
Reviewed-by: Nicolas Pitre <(address hidden)>
Acked-by: Stephen Boyd <(address hidden)>
Cc: Catalin Marinas <(address hidden)>
Cc: stable@vger.kernel.org
Signed-off-by: Rabin Vincent <(address hidden)>
Reviewed-on: http://git-master/r/86779
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
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Change ARCH_NR_GPIO into a Kconfig variable as suggested by Russel King.
This makes ARCH_NR_GPIO single zImage friendly. The default value for
tegra is defined as well.
Upstream v3.3 commit 44986ab056076e9dc9fb9f8b4729afef7fa72616
Change-Id: Ia1ae996fc5209b22eb7ea942d90e86cfae56318e
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/83219
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Limited carveout memory gives Out of Memory errors for
1080p camera preview. Even when camera app runs 640x480
preview carveout memory almost all of carveout memory
(127/128) gets used.
bug 907782
bug 911767
Reviewed-on: http://git-master/r/69492
Change-Id: I993d656910a1853f22719411553dbec3edb9f53f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77311
Reviewed-by: Automatic_Commit_Validation_User
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Change-Id: I6657a60476af2d6c63ecb69ab91fd8132f2603bb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Limited carveout memory gives Out of Memory errors for
1080p camera preview. Even when camera app runs 640x480
preview carveout memory almost all of carveout memory
(127/128) gets used.
bug 907782
bug 911767
Change-Id: Ibb8226c1fb928b7e4344f8959072973da93ecae5
Reviewed-on: http://git-master/r/69492
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Conflicts:
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/board-ventana.c
drivers/misc/Kconfig
drivers/video/tegra/dc/hdmi.c
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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Based on work by George G. Davis <gdavis@mvista.com>.
See http://lwn.net/Articles/390419/
Change-Id: I8df700d20a154e179f8cf6cdfe4015efc5d384f2
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/62998
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R2607a46c8bd1e521abe44a57a5ccf7317333d6c9
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bug 865816
Adapted from x86 change_page_attr() implementation
Change-Id: I398c9d460b841484de4fcfcac10ffffdf49a4a5a
Reviewed-on: http://git-master/r/56769
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: Rddeccf358c948ba84af52316f084814ae53dca5e
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Cortex-A9 has PIPT D-cache which do not require clean the cache
on creating page table.
Original-Change-Id: I42d528be83ea8def96045c7e575c7b3ed95f5980
Reviewed-on: http://git-master/r/40505
Reviewed-by: Heechul Yun <hyun@nvidia.com>
Tested-by: Heechul Yun <hyun@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R214ce4b138abb18e1cfe79465087c39ead248d72
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Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Rebase-Id: R326381df3f4188cc1f700eb210c12b483afe9e77
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Change-Id: I9f10244b0603f7842b8504a16124d40dc4a71ed2
Signed-off-by: Colin Cross <ccross@android.com>
Rebase-Id: Rdc49da8123b4e700f2987a4a5ea19ad2b29ff1d6
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Conflicts:
arch/arm/mm/cache-l2x0.c
drivers/misc/Kconfig
drivers/misc/Makefile
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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Change-Id: If6eb75059fdf4867eb9a974d60b9d50e5e3350d4
Signed-off-by: Dima Zavin <dima@android.com>
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This allows the platform specific drivers to properly enable
and disable the uart at the appropriate times. On some platforms, just
managing the clock is not enough.
Change-Id: I5feaab04cfe313a4a9470ca274838676b9684201
Signed-off-by: Dima Zavin <dima@android.com>
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Based on a rough patch by frank.rowand@am.sony.com
Since ARM doesn't have an NMI (fiq's are not always available),
send an IPI to all other CPUs (current cpu prints the stack directly)
to capture a backtrace.
Change-Id: I8b163c8cec05d521b433ae133795865e8a33d4e2
Signed-off-by: Dima Zavin <dima@android.com>
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ARM errata 727915 for PL310 has been updated to include a new
workaround required for PL310 r2p0 for l2x0_flush_all, which also
affects l2x0_clean_all in my testing. For r2p0, clean or flush
each set/way individually. For r3p0 or greater, use the debug
register for cleaning and flushing.
Requires exporting the cache_id, sets and ways detected in the
init function for later use.
Change-Id: I215055cbe5dc7e4e8184fb2befc4aff672ef0a12
Signed-off-by: Colin Cross <ccross@android.com>
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If more than one ETM or PTM are present, configure all of them
and enable the formatter in the ETB. This allows tracing on dual
core systems (e.g. omap4).
Change-Id: I028657d5cf2bee1b23f193d4387b607953b35888
Signed-off-by: Arve Hjønnevåg <arve@android.com>
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The old code enabled data tracing, but did not configure the
range. We now configure it to trace all data addresses by default,
and add a trace_data_range attribute to change the range or disable
data tracing.
Change-Id: I9d04e3e1ea0d0b4d4d5bcb93b1b042938ad738b2
Signed-off-by: Arve Hjønnevåg <arve@android.com>
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Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
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Change-Id: I9f10244b0603f7842b8504a16124d40dc4a71ed2
Signed-off-by: Colin Cross <ccross@android.com>
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Change-Id: Ibb536c88f0dbaf4766d0599296907e35e42cbfd6
Signed-off-by: Iliyan Malchev <malchev@google.com>
Signed-off-by: Arve Hjønnevåg <arve@android.com>
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Change-Id: I27d2554e07d9de204e0a06696d38db51608d9f6b
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Signed-off-by: Colin Cross <ccross@android.com>
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We can't be holding the mmap_sem while calling flush_cache_user_range
because the flush can fault. If we fault on a user address, the
page fault handler will try to take mmap_sem again. Since both places
acquire the read lock, most of the time it succeeds. However, if another
thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in
between the call to flush_cache_user_range and the fault, the down_read
in do_page_fault will deadlock.
Also, since we really can't be holding the mmap_sem while calling
flush_cache_user_range AND vma is actually unused by the flush itself,
get rid of vma as an argument.
Change-Id: If55409bde41ad1060fa4fe7cbd4ac530d4d9a106
Signed-off-by: Dima Zavin <dima@android.com>
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For streaming-style operations (e.g., software rendering of graphics
surfaces shared with non-coherent DMA devices), the cost of performing
L2 cache maintenance can exceed the benefit of having the larger cache
(this is particularly true for OUTER_CACHE configurations like the ARM
PL2x0).
This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
in the tex remapping tables as an inner-writeback-write-allocate, outer
non-cacheable memory type, so that this mapping will be available to
clients which will benefit from the reduced L2 maintenance.
Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906
Signed-off-by: Gary King <gking@nvidia.com>
Conflicts:
arch/arm/include/asm/pgtable.h
arch/arm/mm/proc-v7.S
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This reverts commit 54d414570432ce07fa1a14b657f53bed752e3d7e.
Change-Id: I8e5cf6ef3555129da9741ef52a1e6a3a772ad588
Signed-off-by: Gary King <gking@nvidia.com>
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ARM CPUs with speculative prefetching have undefined behaviors when the
same physical page is mapped to two different virtual addresses with
conflicting cache attributes.
since many recent systems include IOMMU functionality (i.e., remapping
of discontiguous physical pages into a virtually-contiguous address
range for I/O devices), it is desirable to support allocating any
available OS memory for use by the I/O devices. however, since many
systems do not support cache coherency between the CPU and DMA devices,
these devices are left with using DMA-coherent allocations from the OS
(which severely limits the benefit of an IOMMU) or performing cache
maintenance (which can be a severe performance loss, particularly on
systems with outer caches, compared to using DMA-coherent memory).
this change adds an API for allocating pages from the OS with specific
cache maintenance properties and ensures that the kernel's mapping
of the page reflects the desired cache attributes, in line with the
ARMv7 architectural requirements
Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0
Signed-off-by: Gary King <gking@nvidia.com>
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Change-Id: Ife690c9d055fc0f17a52d2b29048af5062a664a6
Signed-off-by: Colin Cross <ccross@android.com>
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Remove __init annotation from l2x0_init so it can be used to
reinitialize the l2x0 after it has been reset during suspend.
Only print the init messages the first time l2x0_init is called.
Add l2x0_enable to re-enable the l2x0 after l2x0_disable if
the l2x0 was not reset.
l2x0_disable cannot use writel, as writel calls wmb(), and wmb()
may call outer_cache_sync, which takes the same spinlock as
l2x0_disable.
Change-Id: Iaddedb4f582c7eeaef3cbe2a1e463787f0f809a4
Signed-off-by: Colin Cross <ccross@android.com>
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Signed-off-by: Colin Cross <ccross@android.com>
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During some CPU power modes entered during idle, hotplug and
suspend, peripherals located in the CPU power domain, such as
the GIC, localtimers, and VFP, may be powered down. Add a
notifier chain that allows drivers for those peripherals to
be notified before and after they may be reset.
Signed-off-by: Colin Cross <ccross@android.com>
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Per the text in Documentation/SubmitChecklist as below, we should
explicitly have header linux/errno.h in localtimer.h for ENXIO
reference.
1: If you use a facility then #include the file that defines/declares
that facility. Don't depend on other header files pulling in ones
that you use.
Otherwise, we may run into some compiling error like the following one,
if any file includes localtimer.h without CONFIG_LOCAL_TIMERS defined.
arch/arm/include/asm/localtimer.h: In function ‘local_timer_setup’:
arch/arm/include/asm/localtimer.h:53:10: error: ‘ENXIO’ undeclared (first use in this function)
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The SMP implementation of __futex_atomic_op clobbers oldval with the
status flag from the exclusive store. This causes it to always read as
zero when performing the FUTEX_OP_CMP_* operation.
This patch updates the ARM __futex_atomic_op implementations to take a
tmp argument, allowing us to store the strex status flag without
overwriting the register containing oldval.
Cc: stable@kernel.org
Reported-by: Minho Ban <mhban@samsung.com>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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CALL scripts/checksyscalls.sh
<stdin>:46:1: warning: "__IGNORE_migrate_pages" redefined
In file included from <stdin>:2:
arch/arm/include/asm/unistd.h:482:1: warning: this is the location of the previous definition
This is caused because we define __IGNORE_migrate_pages to be 1, but
in the case of nommu, it's defined to be empty. Fix this by just
defining the __IGNORE_ symbols to be empty.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Fighting unfixed U-Boots and other beasts that may the cache in
a locked-down state when starting the kernel, we make sure to
disable all cache lock-down when initializing the l2x0 so we
are in a known state.
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Adrian Bunk <adrian.bunk@movial.com>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Jan Rinze <janrinze@gmail.com>
Tested-by: Robert Marklund <robert.marklund@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.
The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.
It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small) and also prints incorrect cachesize.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: stable@kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Commit f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed
{release,reserve}_pmu to take an enum arm_pmu_type as a parameter, but
inconsistently named the parameter `type' or `device'. It would be nice
if these were consistent.
This patch makes use of enum arm_pmu_type consistent, always using
`type'. Related printks are updated, explicitly mentioning `type' also.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Commit f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed the
prototype of release_pmu, but missed the stub for when
CONFIG_CPU_HAS_PMU is not selected by the platform.
This patch changes the prototype of the stub, preventing possible build
failures when CONFIG_CPU_HAS_PMU is not selected.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
PCI: remove printks about disabled bridge windows
PCI: fold pci_calc_resource_flags() into decode_bar()
PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR
PCI: correct pcie_set_readrq write size
PCI: pciehp: change wait time for valid configuration access
x86/PCI: Preserve existing pci=bfsort whitelist for Dell systems
PCI: ARI is a PCIe v2 feature
x86/PCI: quirks: Use pci_dev->revision
PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.
PCI hotplug: cpqphp: use pci_dev->vendor
PCI hotplug: cpqphp: use pci_dev->subsystem_{vendor|device}
x86/PCI: config space accessor functions should not ignore the segment argument
PCI: Assign values to 'pci_obff_signal_type' enumeration constants
x86/PCI: reduce severity of host bridge window conflict warnings
PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI
PCI: PCIe AER: add aer_recover_queue
x86/PCI: select direct access mode for mmconfig option
PCI hotplug: Rename is_ejectable which also exists in dock.c
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This patch adds irq_domain infrastructure for translating from
hardware irq numbers to linux irqs. This is particularly important
for architectures adding device tree support because the current
implementation (excluding PowerPC and SPARC) cannot handle
translation for more than a single interrupt controller. irq_domain
supports device tree translation for any number of interrupt
controllers.
This patch converts x86, Microblaze, ARM and MIPS to use irq_domain
for device tree irq translation. x86 is untested beyond compiling it,
irq_domain is enabled for MIPS and Microblaze, but the old behaviour is
preserved until the core code is modified to actually register an
irq_domain yet. On ARM it works and is required for much of the new
ARM device tree board support.
PowerPC has /not/ been converted to use this new infrastructure. It
is still missing some features before it can replace the virq
infrastructure already in powerpc (see documentation on
irq_domain_map/unmap for details). Followup patches will add the
missing pieces and migrate PowerPC to use irq_domain.
SPARC has its own method of managing interrupts from the device tree
and is unaffected by this change.
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits)
ARM: S5P64X0: External Interrupt Support
ARM: EXYNOS4: Enable MFC on Samsung NURI
ARM: EXYNOS4: Enable MFC on universal_c210
ARM: S5PV210: Enable MFC on Goni
ARM: S5P: Add support for MFC device
ARM: EXYNOS4: Add support FIMD on SMDKC210
ARM: EXYNOS4: Add platform device and helper functions for FIMD
ARM: EXYNOS4: Add resource definition for FIMD
ARM: EXYNOS4: Change devname for FIMD clkdev
ARM: SAMSUNG: Add IRQ_I2S0 definition
ARM: SAMSUNG: Add platform device for idma
ARM: EXYNOS4: Add more registers to be saved and restored for PM
ARM: EXYNOS4: Add more register addresses of CMU
ARM: EXYNOS4: Add platform device for dwmci driver
ARM: EXYNOS4: configure rtc-s3c on NURI
ARM: EXYNOS4: configure MAX8903 secondary charger on NURI
ARM: EXYNOS4: configure ADC on NURI
ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI
ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI
ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs
...
Fix up tons of silly conflicts:
- arch/arm/mach-davinci/include/mach/psc.h
- arch/arm/mach-exynos4/Kconfig
- arch/arm/mach-exynos4/mach-smdkc210.c
- arch/arm/mach-exynos4/pm.c
- arch/arm/mach-imx/mm-imx1.c
- arch/arm/mach-imx/mm-imx21.c
- arch/arm/mach-imx/mm-imx25.c
- arch/arm/mach-imx/mm-imx27.c
- arch/arm/mach-imx/mm-imx31.c
- arch/arm/mach-imx/mm-imx35.c
- arch/arm/mach-mx5/mm.c
- arch/arm/mach-s5pv210/mach-goni.c
- arch/arm/mm/Kconfig
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
ARM: Consolidate the clkdev header files
ARM: set vga memory base at run-time
ARM: convert PCI defines to variables
ARM: pci: make pcibios_assign_all_busses use pci_has_flag
ARM: remove unnecessary mach/hardware.h includes
pci: move microblaze and powerpc pci flag functions into asm-generic
powerpc: rename ppc_pci_*_flags to pci_*_flags
Fix up conflicts in arch/microblaze/include/asm/pci-bridge.h
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After changing all consumers of atomics to include <linux/atomic.h>, we
ran into some compile time errors due to this dependency chain:
linux/atomic.h
-> asm/atomic.h
-> asm-generic/atomic-long.h
where atomic-long.h could use funcs defined later in linux/atomic.h
without a prototype. This patches moves the code that includes
asm-generic/atomic*.h to linux/atomic.h.
Archs that need <asm-generic/atomic64.h> need to select
CONFIG_GENERIC_ATOMIC64 from now on (some of them used to include it
unconditionally).
Compile tested on i386 and x86_64 with allnoconfig.
Signed-off-by: Arun Sharma <asharma@fb.com>
Cc: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: David Miller <davem@davemloft.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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This is in preparation for more generic atomic primitives based on
__atomic_add_unless.
Signed-off-by: Arun Sharma <asharma@fb.com>
Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Reviewed-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: David Miller <davem@davemloft.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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