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path: root/arch/arm/mach-imx/anatop.c
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2019-02-12MLK-19589-01 ARM: imx: add imx6ulz basic supportBai Ping
The i.MX6ULZ is new SOC of the i.MX6 series. it is SW compatile with i.MX6ULL, so most of the code can be reuse from i.MX6ULL. To maximum the SW reuse, i.MX6ULZ don't have an independent SOC id in anamix. so a dummy ID is used to identify it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-16266-02 ARM: imx: Enhance the code to support new TO for imx6qpBai Ping
Previous code don't take care about the i.MX6QP revision update of new TO. So improve the code to include future TO support for i.MX6QP. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-16266-01 ARM: imx: improve the soc revision calculation flowBai Ping
On our i.MX6 SOC, the DIGPROG register is used for represent the SOC ID and silicon revision. The revision has two part: MAJOR and MINOR. each is represented in 8 bits in the register. bits [15:8]: reflect the MAJOR part of the revision; bits [7:0]: reflect the MINOR part of the revision; In our linux kernel, the soc revision is represented in 8 bits. MAJOR part and MINOR each occupy 4 bits. previous method does NOT take care about the MAJOR part in DIGPROG register. So reformat the revision read from the HW to compatible the revision format used in kernel. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MXSCM-217 imx: keep weak 2p5 power up when ENET WOL wakeup is enabledJuan Gutierrez
When ENET wake up is enabled by wake-on-lan (WOL), the weak 2P5 ldo needs to keep power up even for LPDDR2 due to the ENET_PLL is feed by the weak 2p5 ldo during DSM. If the weak 2P5 ldo is power down the ENET module is power off hence it is not able to sense the WOL interrupt and trigger the system resume. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2019-02-12MLK-13306-1 ARM: imx: correct ddr type for i.mx6sllAnson Huang
For MMDC, LPDDR3 type's value is 2b'11, which is different from DDRC, so correct it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-13303-10 ARM: imx: add DSM mode support for i.mx6sllAnson Huang
Add DSM mode support for i.MX6SLL, Mega/Fast mix can be off now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12MLK-12627-06 ARM: imx: enable DSM for i.mx6ullAnson Huang
Enable DSM for i.MX6ULL, UART_UBRC is a read-only register, writting it will cause external abort, so skip save/restore for this register. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2019-02-12MLK-10983 : ARM: imx: gpc: wait PU LDO ramp before GPU power up on i.mx6qpRobin Gong
Wait PU LDO ramp before GPU power on once system resume back on i.mx6qp, otherwise, GPU resume may hang. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 361af86190c160e0ea66e007c61b18a793149b74)
2019-02-12MLK-12350: ARM: anatop: disable PU regulator on i.mx6qp before suspendRobin Gong
To eliminate the power number, need turn off PU regulator before suspend since it's turned on always on i.mx6qp. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2019-02-12MLK-11492 ARM: imx: keep weak 2p5 on for USB vbus wakeupAnson Huang
Since i.MX6SX, if USB vbus wake up is enabled, weak 2P5 needs to be on even if the DRAM is LPDDR2, previously, we need to set stop_mode_config to keep 2P5 on, so enter DSM, if USB vbus wakeup is enabled, we need to keep weak 2P5 on. Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit 1ca4dffee79055ea95c59e27bab50bc5080310f5) Signed-off-by: Peter Chen <peter.chen@freescale.com>
2019-02-12MLK-11268-2 ARM: imx: disconnect vddhigh and vddsnvs in dsm for imx6ulAnson Huang
Same as i.MX6SX, need to disconnect vddhigh and vddsnvs in DSM on i.MX6UL, they have same design. Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit f0c63b894a60512318481cb8a7b0777cdb7c46ab)
2019-02-12MLK-11268-1 ARM: imx: disconnect vddhigh and vddsnvs in dsm for imx6sxAnson Huang
per design team's recommendation, in DSM mode, need to disconnect vddhigh and vddsnvs, add it for i.MX6SX. i.MX6SX has different bit definition than i.MX6SL about this bit in PMU_MISC0 register. Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit ec42012c66961c357a1ed4c31d27f83a1db86611)
2019-02-12MLK-11698 ARM: imx: correct stop_mode_config bit offsetAnson Huang
STOP_MODE_CONFIG field of PMU_MISC0 register are different on different i.MX6 SoC, weak2P5 can only be enabled when STOP_MODE_CONFIG is clear, need to read STOP_MODE_CONFIG setting before enabling weak2P5, so the register field must be correct, the definition are as below: i.MX6Q/DL: bit[12]; i.MX6SL: bit[12:11], but only bit[11] is valid, so use bit[11]; i.MX6SX/UL: bit[11:10]. Signed-off-by: Anson Huang <b20788@freescale.com>
2019-02-12MLK-10461: arm: imx7: set the PFD override bit before system entering low ↵Bai Ping
power mode the PFD override bit must be set before system entering any low power mode. Signed-off-by: Bai Ping <b51503@freescale.com>
2019-02-12MLK-11265-8 ARM: imx: add pm support for imx7dOctavian Purdila
Add i.MX7D suspend/resume support, including standby and mem mode support, mega/fast mix off and DDR retention support. Signed-off-by: Anson Huang <b20788@freescale.com>
2016-02-14ARM: imx: Add msl code support for imx6qpBai Ping
The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q Rev_2.0 to maximum the code reusability. The chip silicon number we read from the ANADIG_DIGPROG is 0x630100. This patch add code to identify it as i.MX6QP Rev_1.0 when print out the silicon version. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-01-28ARM: imx7d: correct chip version informationFrank Li
The commond 'cat /sys/devices/soc0/revision' can show correct soc version information. "unknow revision" message in imx_print_silicon_rev() will never work for digprog. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-06-03ARM: imx: add msl support for imx7dAnson Huang
Add i.MX7D MSL support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: add anatop settings for LPDDR2 when enter DSM modeAnson Huang
For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16ARM: i.MX6: add more chip revision supportJason Liu
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-10-21ARM: imx: use imx_init_revision_from_anatop() on imx6slShawn Guo
Add imx6sl support into imx_init_revision_from_anatop(), so that it can be used to initialize cpu type and revision on imx6sl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-10-21ARM: imx: add a common function to initialize revision from anatopShawn Guo
The patch creates a common function imx_init_revision_from_anatop() by merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any SoC that encodes revision info in anatop can use it to initialize revision. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: imx: Move anatop related from board file to anatop driverPeter Chen
Move anatop related (For USB) from board file to anatop driver Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: do not use regmap_read for ANADIG_DIGPROGShawn Guo
Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is called to identify silicon version. Users might query silicon version earlier than regmap subsystem is ready. For example, imx6q clock driver query revision in mx6q_clocks_init(), where regmap is not initialized yet. Change imx_anatop_get_digprog() to map anatop block and read ANADIG_DIGPROG in the native way, so that the function can work at very early stage. While at it, let's move imx_print_silicon_rev() back to imx6q_timer_init() to have the message show up a little earlier. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: mach-imx: anatop: Include "common.h"Fabio Estevam
Fix the following sparse warnings: arch/arm/mach-imx/anatop.c:56:6: warning: symbol 'imx_anatop_pre_suspend' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:62:6: warning: symbol 'imx_anatop_post_resume' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:68:6: warning: symbol 'imx_anatop_usb_chrg_detect_disable' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:78:5: warning: symbol 'imx_anatop_get_digprog' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:86:13: warning: symbol 'imx_anatop_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: enable RBC to support anatop LPM modeAnson Huang
RBC is to control whether some ANATOP sub modules can enter lpm mode when SOC is into STOP mode, if RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP will have below behaviors: 1. Digital LDOs(CORE, SOC and PU) are bypassed; 2. Analog LDOs(1P1, 2P5, 3P0) are disabled; As the 2P5 is necessary for DRAM IO pre-drive in STOP mode, so we need to enable weak 2P5 in STOP mode when 2P5 LDO is disabled. For RBC settings, there are some rules as below due to hardware design: 1. All interrupts must be masked during operating RBC registers; 2. At least 2 CKIL(32K) cycles is needed after the RBC setting is changed. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12ARM: imx: enable anatop suspend/resumeAnson Huang
Anatop module have sereval configurations for user to reduce the power consumption in suspend, provide suspend/resume interface for further use and enable fet_odrive to reduce CORE LDO leakage during suspend. As we have a common anatop file, remove all the operations of anatop module in other files, use anatop interfaces to do that. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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