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The struct arm_reg and soc_reg are declared in by a extern statement
in include/linux/busfreq-imx.h. However they are only declared when
imx6-cpufreq.c is compiled and linked.
Qualify the use of arm_reg and soc_reg with the relevant config option
and change KConfig to switch that option on for the SoCs which use
it.
This fixes the following build issue when building for i.MX 7 with
option ARM_IMX6Q_CPUFREQ not set:
arch/arm/mach-imx/built-in.o: In function `imx6ull_lower_cpu_rate':
platform-imx-dma.c:(.text+0x5514): undefined reference to `arm_reg'
platform-imx-dma.c:(.text+0x551c): undefined reference to `arm_reg'
platform-imx-dma.c:(.text+0x553c): undefined reference to `soc_reg'
platform-imx-dma.c:(.text+0x5544): undefined reference to `soc_reg'
platform-imx-dma.c:(.text+0x5598): undefined reference to `arm_reg'
platform-imx-dma.c:(.text+0x55a0): undefined reference to `arm_reg'
platform-imx-dma.c:(.text+0x55ac): undefined reference to `soc_reg'
platform-imx-dma.c:(.text+0x55b4): undefined reference to `soc_reg'
platform-imx-dma.c:(.text+0x55c8): undefined reference to `soc_reg'
platform-imx-dma.c:(.text+0x55d0): undefined reference to `soc_reg'
platform-imx-dma.c:(.text+0x55f0): undefined reference to `arm_reg'
platform-imx-dma.c:(.text+0x55f8): undefined reference to `arm_reg'
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
(cherry picked from commit 3f68dc7c600c0354f5df7f06b931661319addafb)
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This patch fixes coverity issue of "divide by 0".
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
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- When OPTEE OS is present and if it support the busfreq
for the running the i.MX, the busfreq is executed in
the OPTEE OS by calling a specific SMC function
- Only a WFE function is copied into the OCRAM to
synchronize all Cores in multi-core devices
- OPTEE OS add a DT property 'busfreq=1' in the 'firmware/optee'
node to indicate the busfreq support
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
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Per design requirement, AHB clock parent switch and divider
change needs to keep previous/current parent enabled but
when we switch the clock parent, previous AHB clock parent
may be disabled by common clock framework if the use count
is 0, so here we have to make sure AHB's previous parent
pfd2_270m is enabled during AHB set rate.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 41cb188e5f4732c7fdb83894399c4dc1303fd774)
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The low_bus_freq_handler can be scheduled again between when it starts
executing and when it takes the bus_freq_mutex. This can result in
calling reduce_bus_freq twice as shown in the following trace:
[ 762.101949] set_low_bus_freq(743): begin
[ 762.101971] set_low_bus_freq(768): schedule low_bus_freq
[ 762.114111] set_low_bus_freq(771): scheduled low_bus_freq
[ 765.125161] reduce_bus_freq_handler(722): lock...
[ 765.125174] bus_freq_daemon_handler(1043): lock...
[ 765.125191] bus_freq_daemon_handler(1048): call set_low_bus_freq
[ 765.125200] set_low_bus_freq(743): begin
[ 765.125210] set_low_bus_freq(768): schedule low_bus_freq
[ 765.125228] set_low_bus_freq(771): scheduled low_bus_freq
[ 765.125239] bus_freq_daemon_handler(1052): unlock...
[ 765.160624] reduce_bus_freq_handler(726): call reduce
[ 765.166952] reduce_bus_freq(685): begin
[ 765.170865] busfreq_notify(159): notify low enter
[ 765.176095] Bus freq set to 24000000 start...
[ 765.182731] Bus freq set to 24000000 done! cpu=0
[ 765.192646] imx_busfreq soc:busfreq: Bus freq set to low mode. Count: high 0, med 0, audio 0
[ 765.203912] reduce_bus_freq(717): end
[ 765.208903] reduce_bus_freq_handler(733): unlock...
[ 768.166631] reduce_bus_freq_handler(722): lock...
[ 768.172386] reduce_bus_freq_handler(726): call reduce
[ 768.186330] reduce_bus_freq(685): begin
[ 768.191310] busfreq_notify(159): notify low enter
Prevent this scenario by explicitly calling cancel_low_bus_freq_handler
from inside reduce_bus_freq_handler.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
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The only user of busfreq notifiers is imx_thermal and if it receives a
double LOW_BUSFREQ_ENTER it will incorrectly decrease the reference
count on its clk. Since tempmon uses pll3 directly this can cause
problems like uart hangs.
Guard against this scenario with an explicit check and warn inside
busfreq_notify. This is not a high-performance path so it's better to be
safe.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
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i.MX7D TO1.1 only supports DDR3 running at max frequency of 400MHz,
update busfreq driver accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Drop the VDD_SOC and VDD_ARM voltage to 0.9V when system runs at low
power run mode.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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As periph_pre_clk's parent is not changed when going to high audio frequency,
the clk framework will not update its children's frequency. This cause
the the mmdc_ch0_axi clk_rate does not reflect the right frequency when
reading it from userspace like:
cat /sys/kernel/debug/clk/mmdc_ch0_axi/clk_rate
Since the mmdc_ch0_axi_podf is changed in the asm busfreq routine, then the
mmdc rate needs to be updated to make sure clk tree is right, although it
will not do any change to hardware.
To do this the clk_get_rate api is used to update the mmdc_clk which
needs to be dereferenced from the device tree. Since for other cases like
ddr3, the update of the rate of the mmdc clk is not needed, the absense of
this parameter (on the device tree) don't make throw an error, instead, NULL
checks are used to check if the mmdc clk needs to be updated or not.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
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The deadlock scenario is the following:
1. We schedule low_bus_freq_handle() but it does not run yet.
2. We run set_high_bus_freq() or some other function, that does the
following two things: (a) takes the busfreq mutex and (b)
synchronously cancel the low_bus_freq_handle work
If between (a) and (b) the low_bus_freq_handle work starts running, it
will take the bus freq mutex and block which will cause (b) to
deadlock since the work will never finish now.
To fix this issue avoid synchronously canceling the work and instead
use a new global variable (protected by the busfreq mutex) to mark the
cancellation and abort the work when it is scheduled. In order to
avoid unnecessary schedules we also try to cancel the work with
cancel_delayed_work().
======================================================
[ INFO: possible circular locking dependency detected ]
4.9.0-rc4-00776-gd4f2779 #348 Tainted: G W
-------------------------------------------------------
kworker/3:1/68 is trying to acquire lock:
(
bus_freq_mutex
){+.+...}
, at:
[<c0128a20>] reduce_bus_freq_handler+0x1c/0x30
but task is already holding lock:
(
(&(&low_bus_freq_handler)->work)
){+.+...}
, at:
[<c014f4ec>] process_one_work+0x128/0x418
which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:
-> #1
(
(&(&low_bus_freq_handler)->work)
){+.+...}
:
[<c014dafc>] flush_work+0x44/0x234
[<c0150348>] __cancel_work_timer+0x98/0x1c8
[<c01504a4>] cancel_delayed_work_sync+0x14/0x18
[<c0129d9c>] request_bus_freq+0x9c/0x150
[<c06b2b28>] imx6q_cpufreq_init+0x8c/0xb8
[<c06afc9c>] cpufreq_online+0xc0/0x67c
[<c06b0308>] cpufreq_add_dev+0xb0/0xd4
[<c05251b0>] subsys_interface_register+0x9c/0xd8
[<c06af124>] cpufreq_register_driver+0x130/0x1dc
[<c06b3224>] imx6q_cpufreq_probe+0x5c8/0x8a0
[<c0528768>] platform_drv_probe+0x54/0xb8
[<c0526bf8>] driver_probe_device+0x20c/0x2c4
[<c0526e4c>] __device_attach_driver+0x9c/0xb4
[<c0524e3c>] bus_for_each_drv+0x6c/0xa0
[<c05268c8>] __device_attach+0xb8/0x11c
[<c0526fc4>] device_initial_probe+0x14/0x18
[<c0525ee8>] bus_probe_device+0x90/0x98
[<c052401c>] device_add+0x3c8/0x578
[<c052846c>] platform_device_add+0xa8/0x208
[<c0529030>] platform_device_register+0x28/0x2c
[<c0d0f63c>] imx6q_init_late+0x180/0x1c8
[<c0d03880>] init_machine_late+0x24/0x98
[<c01019ec>] do_one_initcall+0x44/0x180
[<c0d00e28>] kernel_init_freeable+0x12c/0x1f4
[<c0978ba8>] kernel_init+0x10/0x120
[<c0107ff0>] ret_from_fork+0x14/0x24
-> #0
(
bus_freq_mutex
){+.+...}
:
[<c01811e4>] lock_acquire+0x78/0x98
[<c097cedc>] mutex_lock_nested+0x54/0x3e4
[<c0128a20>] reduce_bus_freq_handler+0x1c/0x30
[<c014f558>] process_one_work+0x194/0x418
[<c014f810>] worker_thread+0x34/0x4fc
[<c0155e44>] kthread+0xdc/0xf8
[<c0107ff0>] ret_from_fork+0x14/0x24
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0 CPU1
---- ----
lock( (&(&low_bus_freq_handler)->work) );
lock( bus_freq_mutex );
lock( (&(&low_bus_freq_handler)->work) );
lock( bus_freq_mutex );
*** DEADLOCK ***
2 locks held by kworker/3:1/68:
#0:
(
"events"
){.+.+.+}
, at:
[<c014f4ec>] process_one_work+0x128/0x418
#1:
(
(&(&low_bus_freq_handler)->work)
){+.+...}
, at:
[<c014f4ec>] process_one_work+0x128/0x418
stack backtrace:
CPU: 3 PID: 68 Comm: kworker/3:1 Tainted: G W 4.9.0-rc4-00776-gd4f2779 #348
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
Workqueue: events reduce_bus_freq_handler
Backtrace:
[<c010c538>] (dump_backtrace) from [<c010c730>] (show_stack+0x18/0x1c)
[<c010c718>] (show_stack) from [<c0403a58>] (dump_stack+0xb4/0xe8)
[<c04039a4>] (dump_stack) from [<c017d4f0>] (print_circular_bug+0x1d4/0x318)
[<c017d31c>] (print_circular_bug) from [<c0180bb4>] (__lock_acquire+0x1864/0x1ad4)
[<c017f350>] (__lock_acquire) from [<c01811e4>] (lock_acquire+0x78/0x98)
[<c018116c>] (lock_acquire) from [<c097cedc>] (mutex_lock_nested+0x54/0x3e4)
[<c097ce88>] (mutex_lock_nested) from [<c0128a20>] (reduce_bus_freq_handler+0x1c/0x30)
[<c0128a04>] (reduce_bus_freq_handler) from [<c014f558>] (process_one_work+0x194/0x418)
[<c014f3c4>] (process_one_work) from [<c014f810>] (worker_thread+0x34/0x4fc)
[<c014f7dc>] (worker_thread) from [<c0155e44>] (kthread+0xdc/0xf8)
[<c0155d68>] (kthread) from [<c0107ff0>] (ret_from_fork+0x14/0x24)
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
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On i.MX6SLL, if all PLLs is bypassed in low power run mode, we can decrease
the VDD_ARM_IN and VDD_SOC_IN voltage to 0.925V to save power. a 25mV margin
is added to cover IR drop and board tolerance.
Add low power run voltage change support for i.MX6SLL.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add bufreq driver support on i.MX6SLL. For i.MX6SLL,
it only support LPDDR2 and LPDDR3. the DDR clock change
flow is same on these two type of DDR.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Fix system clock topology used by lpddr2 for audio mode
Keep pll2_pfd2 as clock root for periph_pre_clk to match
lpddr2_freq_imx6q.S switching mechanism.
(Rework from commit id 427b1b6d628827ca83887b92c8331a261a254151)
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
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Add busfreq support on i.MX6ULL. per to the design
team, there is a 24MHz low power run mode on i.MX6ULL.
the define for this mode is as below:
----------------------------
|cpu DRAM AXI AHB |
24MHz 24MHz 24MHz 24MHz
The mode can be implemented as 'low_bus_mode' in busfreq,
compared to i.MX6UL, the additional code we need to add is
clk change for cpu core. so in low_bus_mode, the cpu will run
at 24MHz.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add 100Mhz (HIGH_AUDIO_CLK) bus frequency support for imx6q lpddr2 targets
On HIGH_AUDIO_CLK busfreq request source dram mmdc clock root from
pll2_pfd2_div_2 to generate 100Mhz operation frequency.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry-picked from commit 5bc118112b36b72ed6b1e75a3760c371b486abec)
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Before changing the ARM_PODF, the pll1_bypass clock should be enabled and
bypassed to make sure the ARM_PODF can be changed.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add busfreq support for imx6q lpddr2 pop target platform
DDR scaling support for low bus frequency and high bus
frequency mode (24Mhz/400Mhz)
Update Copyrigth year info
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 91cff834d4f5d065fe8e7e60c1c1799f00990654)
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Change when A7 signal M4 to make sure busfreq is
always up when the M4 send high bus release.
This prevents race condition for Low Power Demo
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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offset high_bus_count+1 when m4 is enabled
Signed-off-by: Teo Hall <teo.hall@freescale.com>
(cherry picked from commit 58983b6522c324affdbbeaa5b7b192a673c615a7)
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Add busfreq support for i.MX6SL SOC. we support three
busfreq mode (high_bus_freq_mode/low_bus_freq_mode and
audio_bus_freq_mode).
Signed-off-by: Bai Ping <b51503@freescale.com>
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Enable the busfreq support on i.MX6UL EVK board. The
busfreq support below 3 busfreq mode:
* high_bus_mode: MMDC<--> 400MHz
* audio_bus_mode: MMDC<--> 50MHz
* low_bus_mode: MMDC<--> 24MHz
Signed-off-by: Bai Ping <b51503@freescale.com>
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Add busfreq support for i.MX6Q/DL, 3 setpoints supported:
HIGH: MMDC = 528MHz on i.MX6Q, = 396MHz on i.MX6DL; AHB = AXI = 24MHz;
AUDIO: MMDC = 50MHz, AXI = 50MHz, AHB = 25MHz;
LOW: MMDC = AXI = AHB = 24MHz.
Signed-off-by: Anson Huang <b20788@freescale.com>
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this patch adds A9-M4 power management, including
below features:
1. busfreq: M4 is registered as a high speed device
of A9, when M4 is running at high speed, busfreq
will NOT enter low bus mode, when M4 is entering
its low power idle, A9 will be able to enter low
bus mode according to its state machine;
2. low power idle: only when M4 is in its low power
idle, busfreq is staying at low bus mode, low
power idle is available for kernel;
3. suspend: when M4 is NOT in its low power idle,
when linux is about to suspend, it will only
force SOC enter WAIT mode, only when M4 is in
its low power idle in TCM, linux suspend can
enter DSM mode. M4 can request/release wakeup
source via MU to A9.
as M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:
M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.
A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;
Signed-off-by: Anson Huang <b20788@freescale.com>
Conflicts:
arch/arm/mach-imx/busfreq-imx6.c
arch/arm/mach-imx/pm-imx6.c
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Add busfreq support for i.MX6SX DDR3 board, tested on
i.MX6SX SDB board, busfreq support below 3 setpoints:
high -> 400MHz
audio -> 50MHz
low -> 24MHz
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch adds busfreq support for i.MX7D SDB
board with DDR3 memory, 3 setpoints supported:
HIGH: DRAM CLK = 533MHz, AXI = 332MHz, AHB = 135MHz;
AUDIO: DRAM CLK = 100MHz; AXI = 24MHz, AHB = 24MHz;
LOW: DRAM CLK = 24MHz; AXI = 24MHz, AHB = 24MHz;
Signed-off-by: Anson Huang <b20788@freescale.com>
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