| Age | Commit message (Collapse) | Author |
|---|
|
toradex_4.1-2.0.x-imx-next
Conflicts:
arch/arm/boot/dts/imx7d.dtsi
arch/arm/mach-imx/busfreq-imx.c
arch/arm/mach-imx/imx_rpmsg.c
drivers/mmc/host/sdhci-esdhc-imx.c
Parts moved to:
arch/arm/boot/dts/imx7s.dtsi
Note: This also includes NXP's latest rel_imx_4.1.15_2.1.0_ga.
|
|
If the M4 core is running and in a low frequency mode, the A7 core
should make sure that the AXI bus is left in a low frequency mode
when entering suspend.
So far the code unconditionally increased the high frequency variable
which essentially forced the AXI bus to run in high frequency mode
when entering suspend. With this change we leave the system in the
state it was last in and also make sure that the last state change
is actually applied before going to sleep. Typically high_bus_count
ends up to be 0 because all devices requiring a high bus frequency
release the bus during suspend, allowing the AXI bus to switch to
24MHz only.
If the M4 is not running we don't want to artificially slow down the
suspend process, hence let the bus run at full speed (it will get
disabled anyway by hardware mechanism). Similar, when the M4 is
running at high speed we likely need the bus capacity.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
Set low frequency state in case M4 start with 24MHz. This makes sure
that Linux is aware of the M4 state and makes sure the bus frequency
is not accidentally increased during suspend (bus_freq_pm_notify).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
To configure the suspend settings for lpddr2 systems is necessary
to know if mmdc is operating on 1ch-mode or 2ch-mode.
Here, the imx_get_lpddr2_2ch_mode api is introduced to get this info
when needed and decide accordingly.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
|
|
Depending on configuration the imx_gpcv2_add_m4_wake_up_irq() stub
might not be used anywhere. (e.g. when configuring for i.MX6Q only).
Set unused attribute to the function so that this does not trigger
a compile time warning.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
|
When ENET wake up is enabled by wake-on-lan (WOL), the weak 2P5
ldo needs to keep power up even for LPDDR2 due to the ENET_PLL is
feed by the weak 2p5 ldo during DSM. If the weak 2P5 ldo is power
down the ENET module is power off hence it is not able to sense the
WOL interrupt and trigger the system resume.
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
|
|
Add low power idle support on i.MX6SLL.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 26de2bb5e8ddef4f1562cc5e6001bfc0027106f0)
|
|
When A7 platform is in low power mode while M4 is NOT,
M4 should be able to send message to wake up A7, so
MU must be always as wake up source.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
Add low power idle for i.MX6ULL.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Need to make sure build pass with single SOC
config, in current build for single SOC config,
if both SOC_IMX7D and SOC_IMX6SX are NOT selected,
below build error will occur, add MU module
config to fix this build issue.
LD init/built-in.o
arch/arm/mach-imx/built-in.o: In function `busfreq_probe':
:(.text+0x5370): undefined reference to `imx_mu_lpm_ready'
arch/arm/mach-imx/built-in.o: In function `bus_freq_pm_notify':
:(.text+0x5d50): undefined reference to `imx_mu_lpm_ready'
:(.text+0x5d68): undefined reference to `imx_mu_lpm_ready'
make: *** [vmlinux] Error 1
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
Add suspend/resume support for i.MX6ULL.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
On i.MX6UL, PGC_CPU_PUPSCR_SW's counter uses IPG/2048 as clock
source, as IPG is at 1.5MHz during low power idle, so the power
up time can be up to 1.3mS which is too long for idle.
Since TO1.1, design team re-define the bit[5], if this bit is
set to 1, the clock will be IPG/32, ~22us, enable this function
for TO1.1, the latency value for low power idle needs to be
adjusted accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
|
|
For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts
and GIC must be disabled at the moment;
The hardware design team recommends ~240us is required during ARM
core power down, so we update the RBC counter value to 8(~240us);
Update GPC SCU and CPU power up/down timing according to design
team's recommendation.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
1. Per design requirement, EXSC for PCIe will need clock to recover RDC
setting on resume when M/F mix is off, so we need to enable PCIe
LPCG before entering DSM.
2. As M4 clock is disabled in low power mode, after exit from DSM, A7
needs to restore TCM for M4, but without M4 clock, this operation
never success, so we enable A7 wakeup sources for M4 as well during
DSM, after exit DSM, M4's original wakeup sources will be restored.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
(cherry picked from commit 847db79957d25545c762670eb1bc003f34cb2592)
Signed-off-by: Teo Hall <teo.hall@nxp.com>
|
|
On i.MX7D, only when M4 enters STOP mode, system is able to enter DSM
mode where M4 power will be gated off. This is done by checking
a variable which records M4's power mode. However, when system
resume from DSM, M4 is re-enabled to RUN mode by A7, but the variable
is NOT updated accordingly, so next time system suspend, even
M4 is NOT in STOP mode, system can enter DSM mode, which is
unexpected and would cause bus-freq use count mismatch.
Fix this issue by reset M4 power mode to RUN mode when resume
from DSM.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
(cherry picked from commit d22127a8f395edaf719a5bf4874cf22c5bdc8661)
Signed-off-by: Teo Hall <teo.hall@nxp.com>
|
|
add LPM messages for:
-M4 reporting state
-M4 Request/Release High Bus Freq
-A7 tell M4 it is ready
Signed-off-by: Teo Hall <teo.hall@freescale.com>
(cherry picked from commit 52234ae38e6e4f2b3452d807dd1c1e199be6350c)
Conflicts:
arch/arm/mach-imx/common.h
arch/arm/mach-imx/mu.c
|
|
Since i.MX6SX, if USB vbus wake up is enabled, weak 2P5
needs to be on even if the DRAM is LPDDR2, previously, we need
to set stop_mode_config to keep 2P5 on, so enter DSM,
if USB vbus wakeup is enabled, we need to keep weak 2P5 on.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 1ca4dffee79055ea95c59e27bab50bc5080310f5)
Signed-off-by: Peter Chen <peter.chen@freescale.com>
|
|
The config option for getting DDR type should
be 'HAVE_IMX_MMDC' and 'HAVE_IMX_DDRC'. Otherwise,
get_ddr type will always return 0(DDR3).
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 6e8048311f854184ae5f16c822e6f6f0fd122e54)
|
|
Currently, all i.MX6 config (CONFIG_SOC_IMX6XXX) are enabled, so
build and function are OK for every i.MX6 SOC, however, when only
one SOC config is selected in menu config, for example, users only
needs i.MX6SL, they might deselect all reset SOC configs, then the
build will fail, this is unacceptable.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Bai Ping <b51503@freescale.com>
|
|
Add low power idle support for i.MX6SL.
Signed-off-by: Bai Ping <b51503@freescale.com>
|
|
Add the low power idle support on i.MX6UL. The ANATOP can enter low
power when all PLLs are powered down. If need entering low power idle
with LDO_2P5 and LDO_1P1 power down and other anatop module in low
power mode, add "uart_from_osc' on command line to make sure the UART
clk is from osc to let the PLL3 power down when entering low power idle.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 5215cba66938fd09f44e61b2c7b7ae0ef0629c2f)
|
|
this patch adds A9-M4 power management, including
below features:
1. busfreq: M4 is registered as a high speed device
of A9, when M4 is running at high speed, busfreq
will NOT enter low bus mode, when M4 is entering
its low power idle, A9 will be able to enter low
bus mode according to its state machine;
2. low power idle: only when M4 is in its low power
idle, busfreq is staying at low bus mode, low
power idle is available for kernel;
3. suspend: when M4 is NOT in its low power idle,
when linux is about to suspend, it will only
force SOC enter WAIT mode, only when M4 is in
its low power idle in TCM, linux suspend can
enter DSM mode. M4 can request/release wakeup
source via MU to A9.
as M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:
M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.
A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;
Signed-off-by: Anson Huang <b20788@freescale.com>
Conflicts:
arch/arm/mach-imx/busfreq-imx6.c
arch/arm/mach-imx/pm-imx6.c
|
|
As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:
clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;
Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.
For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.
Signed-off-by: Anson Huang <b20788@freescale.com>
|
|
Enable low power idle for i.MX6SX:
WFI -> first level idle;
WAIT mode -> second level idle;
Low power idle -> third level idle, only when system is in low bus mode.
In low powe idle mode, below operations will be done:
ARM power off;
AHB freq lower to 3MHz;
PERCLK freq lower to 6MHz;
MMDC freq lower to 1MHz;
Anatop will be put into low power mode, and regular band-gap will
be off and low power band-gap will be enabled instead.
Also, in low power idle mode, 24MHz XTAL power will be off and 24MHz clk
source will be switched to RC-OSC to save power, this feature is only
enabled on i.MX6SX TO1.2.
This patch is cherry-picked from L3.14.y, it is the latest version, below
conflicts are fixed.
Signed-off-by: Anson Huang <b20788@freescale.com>
Conflicts:
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/common.h
arch/arm/mach-imx/cpuidle-imx6sx.c
arch/arm/mach-imx/cpuidle.h
arch/arm/mach-imx/mach-imx6sx.c
arch/arm/mach-imx/pm-imx6.c
|
|
Add an interface for GPC used by drivers to keep mega fast mix domain
power.
Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit f40b0d57803b26a889d12cb70f128801ef75055a)
|
|
Enable the M/F funtion support on i.MX6SX. The M4 M/F off
support is not added at present, will be enabled after the M4
funtion is ready.
Signed-off-by: Bai Ping <b51503@freescale.com>
|
|
Enable cpuidle for i.MX7D, total 3 level idle supported:
1. ARM WFI;
2. WAIT mode;
3. Low power idle with ARM/SCU platform power off.
Only when system in low bus freq mode, system is able to
enter low power idle, and only when both of 2 cores are
in low power idle, ARM/SCU platform will be powered off.
DDR will be put into low power mode when low power idle
is entered.
Signed-off-by: Anson Huang <b20788@freescale.com>
|
|
This patch adds busfreq support for i.MX7D SDB
board with DDR3 memory, 3 setpoints supported:
HIGH: DRAM CLK = 533MHz, AXI = 332MHz, AHB = 135MHz;
AUDIO: DRAM CLK = 100MHz; AXI = 24MHz, AHB = 24MHz;
LOW: DRAM CLK = 24MHz; AXI = 24MHz, AHB = 24MHz;
Signed-off-by: Anson Huang <b20788@freescale.com>
|
|
Add basic pm suspend/resume support for i.MX6UL.
Signed-off-by: Bai Ping <b51503@freescale.com>
|
|
Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.
When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAC address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.
Cherry-pick & Merge patches from:
149ac988a25b8d8eb86d05679cbb7b42819ff7a1 &
3269e5c06bdb2f7ab9bd5afa9bbfe46d872197d3
Signed-off-by: Fugang Duan <B38611@freescale.com>
|
|
Add MSL support for new SoC i.MX7D.
Signed-off-by: Anson Huang <b20788@freescale.com>
|
|
Now that the GPC has been converted to be a full blown irqchip
(and not a mole on the side of the GIC), booting a new kernel
with an old DT is likely to result in a rough ride for the user.
This patch makes sure such a situation is promptly detected and
the user made aware that a DT update is in order.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
We use dynamic memory mapping when using dt, so remove all the static mappings.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
mx25_clocks_init() is only used to register the clocks for non-dt platforms.
As mx25 has been converted to a dt-only platform, we can safely remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
This patch introduces an independent cpuidle driver for
i.MX6SX, and supports arm power off in idle, totally
3 levels of cpuidle are supported as below:
1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.
ARM power off can save at least 5mW power.
This patch also replaces imx6q_enable_rbc with imx6_enable_rbc.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann:
"The remaining cleanups for 3.19 are to a large part result of
devicetree conversion nearing completion on two other platforms
besides AT91:
- Like AT91, Renesas shmobile is in the process to migrate to DT and
multiplatform, but using a different approach of doing it one SoC
at a time. For 3.19, the r8a7791 platform and associated "Koelsch"
board are considered complete and we remove the non-DT
non-multiplatform support for this.
- The ARM Versatile Express has supported DT and multiplatform for a
long time, but we have still kept the legacy board files around,
because not all drivers were fully working before. We have finally
taken the last step to remove the board files.
Other changes in this branch are preparation for the later branches or
just unrelated to the more interesting changes:
- The dts files for arm64 get moved into per-vendor directories for a
clearer structure.
- Some dead code removal (zynq, exynos, davinci, imx)
- Using pr_*() macros more consistently instead of printk(KERN_*) in
some platform code"
* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (71 commits)
ARM: zynq: Remove secondary_startup() declaration from header
ARM: vexpress: Enable regulator framework when MMCI is in use
ARM: vexpress: Remove non-DT code
ARM: imx: Remove unneeded .map_io initialization
ARM: dts: imx6qdl-sabresd: Fix the microphone route
ARM: imx: refactor mxc_iomux_mode()
ARM: imx: simplify clk_pllv3_prepare()
ARM: imx6q: drop unnecessary semicolon
ARM: imx: clean up machine mxc_arch_reset_init_dt reset init
ARM: dts: imx6qdl-rex: Remove unneeded 'fsl,mode' property
ARM: dts: imx6qdl-gw5x: Remove unneeded 'fsl,mode' property
ARM: dts: imx6qdl-sabresd: Use IMX6QDL_CLK_CKO define
ARM: at91: remove useless init_time for DT-only SoCs
ARM: davinci: Remove redundant casts
ARM: davinci: Use standard logging styles
ARM: shmobile: r8a7779: Spelling/grammar s/entity/identity/, s/map/mapping/
ARM: shmobile: sh7372: Spelling/grammar s/entity map/identity mapping/
ARM: shmobile: sh73a0: Spelling/grammar s/entity map/identity mapping/
ARM: EXYNOS: Remove unused static iomapping
ARM: at91: fix build breakage due to legacy board removals
...
|
|
The imx6 PM code seems to be quite creative in its use of irq_data,
using something that is very much a hardware interrupt number where
we expect a virtual one. Yes, it worked so far, but that's only
luck, and it will definitely explode in 3.19.
Fix it by using a pair of helper functions that deal with the
actual hardware.
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
|
Freescale LS1021A SoCs deploy two cortex-A7 processors,
this adds bring-up support for the secondary core.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3,
we used cpu type to decide how to do these settings in suspend
before which is NOT flexible, take i.MX6SL for example, although
it has LPDDR2 on EVK board, but users can also use DDR3 on other
boards, so it is better to read the DDR type from MMDC then decide
how to do related settings.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
System restart mechanism has been changed with the introduction
of "kernel restart handler call chain support". The imx2 watchdog
based restart handler has been moved to the driver, and these
restart can be removed from the machine layer.
This patch cleans up the device tree version machine reset init with
mxc_arch_reset_init_dt and removes corresponding .restart handler,
for the .init_machine that can be handled by system default after
removing the mxc_arch_reset_init_dt, the .init_machine is also removed.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
With commit c716483c3db1 ("ARM: 8122/1: smp_scu: enable SCU standby
support"), the STANDBY bit of SCU is handled by core function
scu_enable(). So imx_scu_standby_enable() can be removed now.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
This patch uses clocksource_of_init() call for DT targets.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
The i.MX SoCs allow to setup fine grained access rights to peripherals on the
AIPS bus.
This is done via the Peripheral Access Register (PAR) in e.g. the i.MX21
or in later SoC versions the Off-Platform Peripheral Access Control Register
(OPACR), e.g. i.MX53.
Under certain circumstances this leads to problems in which bus masters are
not granted their access rights to peripherals.
To be able to disable these restrictions on DT platforms, add a helper function
that looks for AIPS nodes in the DT and disables them for every compatible node
it finds.
The compatible has to be declared in the mach-specific entry file, where this
helper function should then be called.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
Replace .init_time() hook with of_clk_init() for DT targets.
Based on:
d4347ee ARM: i.MX27 clk: Use of_clk_init() for DT case
Signed-off-by: Denis Carikli <denis@eukrea.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
Add standby mode support for suspend, to enter standby mode:
echo standby > /sys/power/state;
Use UART or RTC alarm to wake up system, when system enters
standby mode, SOC will enter STOP mode with ARM core kept
power on and 24M XTAL on.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
According to hardware design, mem bit must be clear before
entering DSM mode, as ARM core will be power gated in DSM mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
Add suspend support for i.MX6SX.
To enter suspend, echo mem > /sys/power/state.
To exit suspend, using RTC alarm or enable debug UART wakeup.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
Replace .init_time() hook with of_clk_init() for DT targets.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
