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Add low power idle for i.MX6ULL.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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On i.MX6UL, PGC_CPU_PUPSCR_SW's counter uses IPG/2048 as clock
source, as IPG is at 1.5MHz during low power idle, so the power
up time can be up to 1.3mS which is too long for idle.
Since TO1.1, design team re-define the bit[5], if this bit is
set to 1, the clock will be IPG/32, ~22us, enable this function
for TO1.1, the latency value for low power idle needs to be
adjusted accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts.
However, the previous setting of RBC counter is 1, which is ~30us,
but the hardware design recommend a ~90us is required during ARM
core power down, so we update the RBC counter value to 4(~120us) here.
Previous delay loop to make sure RBC is actually enabled, 3us is
needed, but the loop value assume ARM is running @1GHz, but actually
ARM is running @24MHz now, so we need to update the loop value
according to ARM speed.
The ARM power up timing is based on IPG / 2048, IPG is 1.5MHz during
low power idle, so the total latency of cpuidle exit should be
updated accordingly.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 4e1fd49da5e87c5cc23f053692e8d7648a4d4b21)
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If in low power idle, we use the RC-OSC to reduce the power consumption,
the RC-OSC freq need to be adjusted, otherwise, the RC-OSC freq is not
very accurate. It may lead to system instability issue.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 8a93ab44e98bcc6611170734b829cd8d140dd722)
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This bit is used to keep the ARM Platform memory clocks enabled if
an interrupt is pending when entering low power mode. This bit should
always bet set when the CCM_CLPCR_LPM bits are set to 01(WAIT Mode) or
10 (STOP mode) without power gating.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 0272868641041c5a9eb1b3476660711bb5cd69e4)
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Add the low power idle support on i.MX6UL. The ANATOP can enter low
power when all PLLs are powered down. If need entering low power idle
with LDO_2P5 and LDO_1P1 power down and other anatop module in low
power mode, add "uart_from_osc' on command line to make sure the UART
clk is from osc to let the PLL3 power down when entering low power idle.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 5215cba66938fd09f44e61b2c7b7ae0ef0629c2f)
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