| Age | Commit message (Collapse) | Author |
|---|
|
Add low power idle support on i.MX6SLL.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Add cpufreq support for i.MX6SLL, uses i.MX6SL's
opp table for now.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
Since we share the same machine code for both imx6sll and imx6sl we
need to check the CPU in order to select the right device tree
binding for the PM CCM.
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
|
|
Add i.MX6SLL MSL support, machine code reuses
i.MX6SL.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Add busfreq support for i.MX6SL SOC. we support three
busfreq mode (high_bus_freq_mode/low_bus_freq_mode and
audio_bus_freq_mode).
Signed-off-by: Bai Ping <b51503@freescale.com>
|
|
Add basic pm suspend/resume support for i.MX6UL.
Signed-off-by: Bai Ping <b51503@freescale.com>
Also squashed the following to fix boot
MLK-11322-02 ARM: imx: add io map for pm code
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
|
|
Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.
When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAarch/arm/mach-imx
/mach-imx6q.cC address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.
Cherry-pick & Merge patches from:
149ac988a25b8d8eb86d05679cbb7b42819ff7a1 &
3269e5c06bdb2f7ab9bd5afa9bbfe46d872197d3
Signed-off-by: Fugang Duan <B38611@freescale.com>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"The cleanup branch keeps going down in size as we've completed a lot
of the major legacy platform removals and conversions.
A handful of changes this time around, some of the themes or larger
sets are:
- A bunch of i.MX cleanups around platform detection, init call cleanups
- Misc fixes of missing/implicit includes
- Removal of ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB"
* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (40 commits)
ARM: mps2: fix typo
ARM: s3c64xx: avoid warning about 'struct device_node'
bus: mvebu-mbus: make mvebu_mbus_syscore_ops static
bus: mvebu-mbus: fix __iomem on register pointers
ARM: tegra: Remove board_init_funcs array
ARM: iop: Fix indentation
ARM: imx: remove cpu_is_mx*()
ARM: imx: remove last call to cpu_is_mx5*
ARM: imx: rework mx27_pm_init() call
ARM: imx: deconstruct mx3_idle
ARM: imx: deconstruct mxc_rnga initialization
ARM: imx: remove cpu_is_mx1 check
ARM: i.MX: Do not explicitly call l2x0_of_init()
ARM: i.MX: system.c: Tweak prefetch settings for performance
ARM: i.MX: system.c: Replace magic numbers
ARM: i.MX: system.c: Remove redundant errata 752271 code
ARM: i.MX: system.c: Convert goto to if statement
ARM: Kirkwood: fix kirkwood_pm_init() declaration/type
ARM: Kirkwood: make kirkwood_disable_mbus_error_propagation() static
ARM: orion5x: make orion5x_legacy_handle_irq static
...
|
|
Use helper of_platform_default_populate() in linux/of_platform
when possible, instead of calling of_platform_populate() with
the default match table.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Krzysztof Halasa <khalasa@piap.pl>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Roland Stigge <stigge@antcom.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Viresh Kumar <vireshk@kernel.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Rob Herring <robh@kernel.org>
|
|
There's no need to explicitly call l2x0_of_init() since it will be
called as a part of init_IRQ() (see arch/arm/kernel/irq.c for
details). This way we can simplify imx_init_l2cache() and ditch the call
to it on i.MX35 (which does not claim compatibility with
"arm,pl310-cache") alltogether.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function")
moves imx6_set_lpm() from clock init function into
imx6_pm_common_init(). This causes a hang when cpuidle support is
enabled. The reason for that is ARM core clock is shut down
unexpectedly by WAIT mode. It happens with the following call stack:
cpuidle_register_governor()
cpuidle_switch_governor()
cpuidle_uninstall_idle_handler()
synchronize_sched()
wait_rcu_gp()
wait_for_completion()
When wait_for_completion() is called as above, all cores are idle/WFI.
Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a
hardware shutdown of the ARM core clock.
To fix the regression, we need to ensure that CCM_CLPCR_LPM is
initialized into RUN mode earlier than cpuidle governor registration,
which is a postcore_initcall. This patch creates function
imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into
RUN mode, and have the function called from machine .init_irq hook,
which should be early enough.
Reported-by: Kevin Hilman <khilman@kernel.org>
Fixes: 8fb76a07e2cb ("ARM: imx6: set initial power mode in pm function")
Tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
Now that the GPC has been converted to be a full blown irqchip
(and not a mole on the side of the GIC), booting a new kernel
with an old DT is likely to result in a rough ride for the user.
This patch makes sure such a situation is promptly detected and
the user made aware that a DT update is in order.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
If machine_desc.map_io is not set, devicemaps_init() in the common ARM
code will call debug_ll_io_init().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
System restart mechanism has been changed with the introduction
of "kernel restart handler call chain support". The imx2 watchdog
based restart handler has been moved to the driver, and these
restart can be removed from the machine layer.
This patch cleans up the device tree version machine reset init with
mxc_arch_reset_init_dt and removes corresponding .restart handler,
for the .init_machine that can be handled by system default after
removing the mxc_arch_reset_init_dt, the .init_machine is also removed.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
Otherwise GCC will mark the .init.rodata section R/W, which causes
a compile error once we add other real R/O data.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
When system enter suspend, we can set the DDR IO to
high-Z state to save DDR IOs' power consumption, this
operation can save many power(from ~26mA@1.5V to ~15mA@1.5V,
measured on i.MX6Q SabreSD board, R25) of DDR IOs. To
achieve that, we need to copy the suspend code to ocram
and run the low level hardware related code(set DDR IOs
to high-Z state) in ocram.
If there is no ocram space available, then system will
still do suspend in external DDR, hence no DDR IOs will
be set to high-Z.
The OCRAM usage layout is as below,
ocram suspend region(4K currently):
======================== high address ======================
.
.
.
^
^
^
imx6_suspend code
PM_INFO structure(imx6_cpu_pm_info)
======================== low address =======================
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
Add cpuidle support for i.MX6SL, currently only support
two cpuidle levels(ARM wfi and WAIT mode), and add software
workaround for WAIT mode errata as below:
ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
during WAIT mode entry process could cause cache memory
corruption.
Software workaround:
To prevent this issue from occurring, software should ensure that
the ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
entering WAIT mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
Re-using iMX6Q driver for cpu frequency scaling.
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
0-DAY kernel build testing backend reports the following.
scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
# many are suggestions rather than must-fix
ERROR: Use of const init definition must use __initconst
#80: arch/arm/mach-imx/mach-imx50.c:26:
+static const char *imx50_dt_board_compat[] __initdata = {
While at it, fix the error globally for IMX platform.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
The imx6sl low power mode implementation inherits imx6q/dl one,
and pm-imx6q.c can just work for imx6sl with some minor updates.
Let's enable imx6sl suspend support by reusing pm-imx6q.c and use
cpu_is_imxXX() to handle the those minor differences between imx6sl
and imx6q/dl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
The patch enables soc bus infrastructure and adds a function
imx_soc_device_init() to report soc info via soc device interface for
imx6qdl and imx6sl. With the support, user space can get soc related
info by looking at sysfs like below.
$ cat /sys/devices/soc0/machine
Freescale i.MX6 Quad SABRE Smart Device Board
$ cat /sys/devices/soc0/family
Freescale i.MX
$ cat /sys/devices/soc0/soc_id
i.MX6Q
$ cat /sys/devices/soc0/revision
1.2
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
Add imx6sl support into imx_init_revision_from_anatop(), so that it can
be used to initialize cpu type and revision on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
Config iomux-gpr1 to select clock source for fec system clock.
Clear gpr1[14], gpr1[18-17] bit to select the fec clock source
from internal anatop PLL.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
With arch/arm calling of_clk_init(NULL) from time_init(), we can now
remove custom .init_time hooks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
|
|
The optimized L2 prefect and power setting done in imx_init_l2cache()
can also benefit imx6sl, so let's call the function on imx6sl as well.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
|
|
Instead of explicitly calling clock initialization functions, we can
declare the functions with CLK_OF_DECLARE() and then call common
of_clk_init() to have them invoked properly.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
Add initial support for i.MX6 SoloLite.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
