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i.MX7ULP SoC revision is available from B0, the SIM_JTAG_ID
register bit[31:28] indicates SoC revision as below:
4b'0001 B0
4b'0010 B1
This register is NOT available on A0, tested on B1 chip
as below:
root@imx7ulpevk:~# cat /sys/devices/soc0/revision
2.1
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Ye Li <ye.li@nxp.com>
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The AIPSx address space of i.MX7ULP need to be mapped as SZ_1M block
in iRAM tlb for suspend code use. If we use ioremap to map these
address region into kernel space, we can't make sure that the returned
virtual address is 1M alignment. So we can map this address regions
as static, then if we use the ioremap to map these memory regions, it will
always return the virtual address of static mapping. So we can make sure
the virtual address is 1M aligned.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add cpufreq device on i.MX7ULP.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add i.MX7ULP cpuidle support, 3 levels idle as below:
1. patial stop mode 3;
2. patial stop mode 2;
3. patial stop mode 1.
PSTOP1 - Partial Stop with system and bus clock disabled
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
PSTOP3 - Partial Stop with system clock enabled and bus clock enabled
All drivers has DMA function need to add pm_qos
API to prevent cpuidle from entering PSTOP 1/2.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add suspend/resume support for i.MX7ULP,
standby mode will enter VLPS mode, can be waked
up by any interrupt which is enabled in GIC,
and mem will enter VLLS mode, can only be waked up
by NMI currently.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add i.MX7ULP MSL support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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