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2020-05-21Merge remote-tracking branch 'remotes/fslc/4.9-2.3.x-imx' into ↵Marcel Ziswiler
toradex_4.9-2.3.x-imx-next Conflicts: sound/soc/codecs/sgtl5000.c sound/soc/fsl/imx-sgtl5000.c
2020-05-19Merge tag 'v4.9.220' into 4.9-2.3.x-imxMarcel Ziswiler
This is the 4.9.220 stable release Conflicts: arch/arm/Kconfig.debug arch/arm/boot/dts/imx7s.dtsi arch/arm/mach-imx/common.h arch/arm/mach-imx/cpuidle-imx6q.c arch/arm/mach-imx/cpuidle-imx6sx.c arch/arm/mach-imx/suspend-imx6.S block/blk-core.c drivers/crypto/caam/caamalg.c drivers/crypto/mxs-dcp.c drivers/dma/imx-sdma.c drivers/gpu/drm/bridge/adv7511/adv7511_drv.c drivers/input/keyboard/imx_keypad.c drivers/input/keyboard/snvs_pwrkey.c drivers/mmc/host/sdhci.c drivers/net/can/flexcan.c drivers/net/ethernet/freescale/fec_main.c drivers/net/phy/phy_device.c drivers/net/wireless/ath/ath10k/pci.c drivers/tty/serial/imx.c drivers/usb/dwc3/gadget.c drivers/usb/host/xhci.c include/linux/blkdev.h include/linux/cpu.h include/linux/platform_data/dma-imx-sdma.h kernel/cpu.c net/wireless/util.c sound/soc/fsl/Kconfig sound/soc/fsl/fsl_esai.c sound/soc/fsl/fsl_sai.c sound/soc/fsl/imx-sgtl5000.c
2019-11-25ARM: imx6: register pm_power_off handler if "fsl,pmic-stby-poweroff" is setOleksij Rempel
[ Upstream commit 8148d2136002da2e2887caf6a07bbd9c033f14f3 ] One of the Freescale recommended sequences for power off with external PMIC is the following: ... 3. SoC is programming PMIC for power off when standby is asserted. 4. In CCM STOP mode, Standby is asserted, PMIC gates SoC supplies. See: http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdf page 5083 This patch implements step 4. of this sequence. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2018-12-24arm: imx: fix handling power stuff without psciMarcel Ziswiler
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-12-24apalis-imx6: use stopmode for poweroffMax Krummenacher
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 051ee1a1c24058db62f10a177b1271daebbd2ebe)
2018-12-24pm-imx6.c: fix power off by stop modeMax Krummenacher
With the 3.14.28 release of the kernel imx6_stop_mode_poweroff() does not enter stop mode. Thus the function does not switch of power but returns. This seems to be caused by the second processor which has been stopped. Set the WFI event mask for the stopped processor works around the issue. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry-picked from commit 2acff0eaece38533e85e08431e7ae9f3027c677a) (cherry picked from commit 894914718e9e563eb601e0090e1ae2ddadf426a9)
2018-12-24colibri-imx6: use stopmode for poweroffMax Krummenacher
After the system has been shutdown with PMIC_ON_REQ and VCC_BATT is supplied from a battery it will never restart either by RESET or power cycle. So use the PMIC_STBY_REQ after shutdown to switch off power rails. Conflicts: arch/arm/mach-imx/pm-imx6.c drivers/regulator/pfuze100-regulator.c (cherry-picked from commit c8b186404065c4502b485820ad4a51515924795c) (cherry-picked from commit ee4c5c4da3b32f65528a2d523ca4bce574dee3c5) Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit 29ff2389ecf7cb4e30924c80b8d42165cf306936)
2018-08-24MLK-16750-5: arm: imx: support using psci to handle power stuffPeng Fan
Support using PSCI to handle Power stuff. Use PSCI to differentiate secure/non-secure kernel. i.MX7 LPSR mode not implemented now. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MXSCM-243-2 arm: imx6q: mmdc handshake for lpddr2 2ch-mode on low-powerJuan Gutierrez
For i.mx6q systems the mmdc handshake on channel 0 is kept enabled (while channel 1 is bypassed). This is ok for lpddr2 systems operating on 1ch-mode, but not true for 2ch-mode. On this case the handshake needs to be set for both channels, otherwise a kernel panic or Oops error might be observed after resuming from suspend. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
2018-08-24MLK-13333-3 ARM: imx: enable bus clock auto gating for i.mx6sllAnson Huang
i.MX6SLL has new hardware function of bus auto clock gating, whenerve bus is idle, its clock will be auto gated to save power, enable this function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-13333-1 ARM: imx: correct i.mx6sll dram io low power modeAnson Huang
i.MX6SLL has different DRAM IO offset, and it has no CAS/RAS/ODT/RESET pin now, correct the DRAM IO offset. To better support all different i.MX6 SoCs and different DRAM types, introduce a new column to store the low power settings for DRAM IO, then suspend asm code no need to check SoC or DRAM type, just get the DRAM IO's low power settings from OCRAM pm_info and set to each DRAM IO. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-13306-2 ARM: imx: update MMDC restore settings for i.mx6sllAnson Huang
i.MX6SLL LPDDR3 script v1.2 is released, update MMDC restore settings accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-13306-1 ARM: imx: correct ddr type for i.mx6sllAnson Huang
For MMDC, LPDDR3 type's value is 2b'11, which is different from DDRC, so correct it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-13303-10 ARM: imx: add DSM mode support for i.mx6sllAnson Huang
Add DSM mode support for i.MX6SLL, Mega/Fast mix can be off now. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-24MLK-12740 cpuidle: imx6q: configure CCM to RUN mode when CPU is activePeng Fan
There are two states in i.MX6Q cpuidle driver. state[1]: ARM WFI mode state[2]: i.MX6Q WAIT mode Take i.MX6DL as example, think out such a case: 1. CPU0/1 both run at normal mode 2. On CPU0, `sleep 1` is executed. And there are no workload on CPU1. 3. CPU0 first runs into state[2] and 'wfi' instruction. Switched to use GPT broadcast. 4. CPU1 runs into state[2] and configure CCM to WAIT MODE, then 'wfi' instruction. Now arm_clk and local timer clock are shutdown. Switched to use GPT broadcast 5. GPT broadcast timer interrupt comes to GPC/GIC, then CPU0 wakes up. CPU0 switched to use arm local timer. CPU1 is still sleeping. 6. No workload on CPU0, CPU0 runs into state[1]. But CCM register is still not restored to Normal RUN mode. 'wfi' + CCM WAIT will cause arm_clk and arm core clk. Now CPU0 stops, which is not correct. So, need to make sure CCM configured to RUN mode when any cpu exit state[2]. In this patch, When CPU exits state[2], it configures CCM to RUN mode. When all CPUs enters state[2], the last CPU needs to check whether it's ok to configure CCM to WAIT mode or not. In imx6q_set_lpm, we only need to unmask GINT when not WAIT_CLOCKED, so add a check condition. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-24MLK-12627-06 ARM: imx: enable DSM for i.mx6ullAnson Huang
Enable DSM for i.MX6ULL, UART_UBRC is a read-only register, writting it will cause external abort, so skip save/restore for this register. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-12627-05 ARM: imx: add suspend support for i.mx6ulAnson Huang
Add suspend/resume support for i.MX6ULL. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-24MLK-12306: ARM: imx: imx6 lpddr2 two channel suspend supportAdrian Alonso
Add lpddr2 two channel suspend support - save/restore mmdc io pads for channel 2 - Set mmdc channe 2 on self refresh and auto power saving mode only if mmdc channel 2 is enabled - Perform a reset fifo on resume_io when restoring mmdc io pads Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 2e5982e82edc8fc7de0aebc8894a9f0a41e01965)
2018-08-24MLK-11889: arm: imx6: low power mode support for imx6q lpddr2Adrian Alonso
Add low power suspend mode support for imx6q lpddr2 Save/restore mmdc iomux pads relevant to dual channel lpddr2 memory when enter/exit low power suspend mode. Remove unused macros in suspend-imx6. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit 5ebac6d425b859c51d570489d03684e0c976ef60)
2018-08-24MLK-11620 ARM: imx: single SOC config/compile supportBai Ping
Currently, all i.MX6 config (CONFIG_SOC_IMX6XXX) are enabled, so build and function are OK for every i.MX6 SOC, however, when only one SOC config is selected in menu config, for example, users only needs i.MX6SL, they might deselect all reset SOC configs, then the build will fail, this is unacceptable. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com>
2018-08-24MLK-11366-2 ARM: imx: add suspend/resume support for imx6ul lpddr2Anson Huang
This patch adds suspend/resume with Mega/Fast mix off support for i.MX6UL-9x9-LPDDR2-EVK board, LPDDR2 has different MMDC restore flow compared to DDR3. Conflicts: arch/arm/mach-imx/pm-imx6.c Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit d5d3915aac04c2a80827d215d703e0f46309ed14)
2018-08-24MLK-11488-10 arm: imx: add A9-M4 power managementAnson Huang
this patch adds A9-M4 power management, including below features: 1. busfreq: M4 is registered as a high speed device of A9, when M4 is running at high speed, busfreq will NOT enter low bus mode, when M4 is entering its low power idle, A9 will be able to enter low bus mode according to its state machine; 2. low power idle: only when M4 is in its low power idle, busfreq is staying at low bus mode, low power idle is available for kernel; 3. suspend: when M4 is NOT in its low power idle, when linux is about to suspend, it will only force SOC enter WAIT mode, only when M4 is in its low power idle in TCM, linux suspend can enter DSM mode. M4 can request/release wakeup source via MU to A9. as M4 can NOT switch its clk parent due to glitch MUX, to handle this case, A9 will help switch M4's clk parent, the flow is as below: M4: 1. enter low power idle, send bus use count-- to A9; 2. enter wfi and only wait for MU interrupt; 3. receive A9's clk switch ready message, go into low power idle; 4. receive interrupt to exit low power idle, send request to A9 for increase busfreq and M4 freq, enter wfi and only wait for MU interrupt; 5. receive A9 ready message, go out of low power idle. A9: 1. when receive M4's message of entering low power idle, wait M4 into wfi, hold M4 in wfi by hardware, gate M4 clk, then switch M4's clk to OSC, ungate M4 clk, send ready command to wake up M4 into low power idle; 2. when receive M4's message of exiting low power idle, wait M4 into wfi, hold M4 in wfi by hardware, gate M4 clk, then switch M4's clk to origin high clk, ungate M4 clk, send ready command to wake up M4 to exit low power idle; Signed-off-by: Anson Huang <b20788@freescale.com> Conflicts: arch/arm/mach-imx/busfreq-imx6.c arch/arm/mach-imx/pm-imx6.c
2018-08-24MLK-11488-8 arm: imx: adjust qspi device index according to dtb settingAnson Huang
When resume from DSM with Mega/Fast off, we need to restore the right QSPI module for M4, so get the qspi index from dtb file. Signed-off-by: Anson Huang <b20788@freescale.com>
2018-08-24MLK-11488-7 arm: imx: add QSPI save/restore when M4 is enabledAllen Xu
As M4 is executing on QSPI2 flash, and QSPI is inside Mega/Fast domain which may lost power in DSM, so we need to do save/restore of QSPI2 controller to make sure QSPI flash can be accessed before waking up M4 after exiting from DSM. Signed-off-by: Allen Xu <b45815@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
2018-08-23MLK-11396-2 ARM: imx: add suspend/resume for imx6sx lpddr2Anson Huang
This patch adds suspend/resume with Mega/Fast mix off support for i.MX6SX LPDDR2, tested on i.MX6SX-14x14-LPDDR2-ARM2 board. Signed-off-by: Anson Huang <b20788@freescale.com>
2018-08-23MLK-11389-03 ARM: imx: enable M/F mix support on imx6sxBai Ping
Enable the M/F funtion support on i.MX6SX. The M4 M/F off support is not added at present, will be enabled after the M4 funtion is ready. Signed-off-by: Bai Ping <b51503@freescale.com>
2018-08-23MLK-11375-1 ARM: imx: bypass pmic ready for imx6sxAnson Huang
i.MX6SX has same design as i.MX6SL which has bypass pmic ready signal, as we do NOT enable this function, so need to bypass it during suspend/resume. Signed-off-by: Anson Huang <b20788@freescale.com>
2018-08-23MLK-11365-02 ARM: imx: add M/F mix support on imx6ulBai Ping
Add M/F mix support on i.MX6UL. Signed-off-by: Bai Ping <b51503@freescale.com>
2018-08-23MLK-11338-2 ARM: imx: add busfreq support for imx7d sdb boardAnson Huang
This patch adds busfreq support for i.MX7D SDB board with DDR3 memory, 3 setpoints supported: HIGH: DRAM CLK = 533MHz, AXI = 332MHz, AHB = 135MHz; AUDIO: DRAM CLK = 100MHz; AXI = 24MHz, AHB = 24MHz; LOW: DRAM CLK = 24MHz; AXI = 24MHz, AHB = 24MHz; Signed-off-by: Anson Huang <b20788@freescale.com>
2018-08-23MLK-11322-02 ARM: imx: add io map for pm codeBai Ping
add necessary io memory mapping used by power management. Signed-off-by: Bai Ping <b51503@freescale.com>
2018-08-23MLK-11300-05 ARM: imx: add pm support for imx6ulBai Ping
Add basic pm suspend/resume support for i.MX6UL. Signed-off-by: Bai Ping <b51503@freescale.com>
2016-10-07Merge tag 'armsoc-soc' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files. Noteworthy changes include: - We get support for running in big-endian mode on two platforms: sunxi (Allwinner) and s3c24xx (old Samsung). - The recently added Uniphier platform now uses standard PSCI methods for SMP booting and we remove support for old bootloader versions that did not support it yet. - In sunxi, we gain support for the "Nextthing GR8" SoC, which is a close relative of the Allwinner A13 and R8 chips. - PXA completes its move over to the generic dmaengine framework and removes its old private API - mach-bcm gains support for BCM47189/BCM53573, their first ARM SoC with integrated 802.11ac wireless networking" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) ARM: imx legacy: pca100: move peripheral initialization to .init_late ARM: imx legacy: mx27ads: move peripheral initialization to .init_late ARM: imx legacy: mx21ads: move peripheral initialization to .init_late ARM: imx legacy: pcm043: move peripheral initialization to .init_late ARM: imx legacy: mx35-3ds: move peripheral initialization to .init_late ARM: imx legacy: mx27-3ds: move peripheral initialization to .init_late ARM: imx legacy: imx27-visstrim-m10: move peripheral initialization to .init_late ARM: imx legacy: vpr200: move peripheral initialization to .init_late ARM: imx legacy: mx31moboard: move peripheral initialization to .init_late ARM: imx legacy: armadillo5x0: move peripheral initialization to .init_late ARM: imx legacy: qong: move peripheral initialization to .init_late ARM: imx legacy: mx31-3ds: move peripheral initialization to .init_late ARM: imx legacy: pcm037: move peripheral initialization to .init_late ARM: imx legacy: mx31lilly: move peripheral initialization to .init_late ARM: imx legacy: mx31ads: move peripheral initialization to .init_late ARM: imx legacy: mx31lite: move peripheral initialization to .init_late ARM: imx legacy: kzm: move peripheral initialization to .init_late MAINTAINERS: update list of Oxnas maintainers ARM: orion5x: remove extraneous NO_IRQ ARM: orion: simplify orion_ge00_switch_init ...
2016-08-30ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sxAnson Huang
i.MX6SX has bypass PMIC ready function, as this function is normally NOT enabled on the board design, so we need to bypass the PMIC ready pin check during DSM mode resume flow, otherwise, the internal DSM resume logic will be waiting for this signal to be ready forever and cause resume fail. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Fixes: ff843d621bfc ("ARM: imx: add suspend support for i.mx6sx") Cc: <stable@vger.kernel.org> Tested-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-29ARM: imx: rename imx6q_set_int_mem_clk_lpm() functionAnson Huang
Let's rename the function imx6q_set_int_mem_clk_lpm() to imx6_set_int_mem_clk_lpm() since it's actually common for all i.MX6 SoCs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-15ARM: imx6: add missing BM_CLPCR_BYP_MMDC_CH0_LPM_HS setting for imx6ulPeter Chen
There is a missing BM_CLPCR_BYP_MMDC_CH0_LPM_HS setting for imx6ul, without it, the "standby" mode can't work well, the system can't be resumed. With this commit, the "standby" mode works well. Signed-off-by: Peter Chen <peter.chen@nxp.com> Cc: Anson Huang <anson.huang@nxp.com> Cc: <stable@vger.kernel.org> Fixes: ee4a5f838c84 ("ARM: imx: add suspend/resume support for i.mx6ul") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-01-28ARM: imx6: fix cleanup path in imx6q_suspend_init()Jean-Christophe Dubois
The wrong pointer is passed to the ioumap function in the cleanup path Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-09-17ARM: imx: add suspend/resume support for i.mx6ulAnson Huang
This patch adds suspend function for i.MX6UL, it supports "standby" and "mem" mode, for "standby" mode, SoC will enter STOP mode only, while for "mem" mode, SoC will enter STOP mode and DDR IO will be set to low power mode. As i.MX6UL contains a "Cortex-A7" ARM core which has no PL310, so we need to avoid any PL310 operations during suspend/resume, also, we need to flush Cortex-A7's inernal L2 cache before suspend. Signed-off-by: Anson Huang <b20788@freescale.com>
2015-09-04genalloc: add name arg to gen_pool_get() and devm_gen_pool_create()Vladimir Zapolskiy
This change modifies gen_pool_get() and devm_gen_pool_create() client interfaces adding one more argument "name" of a gen_pool object. Due to implementation gen_pool_get() is capable to retrieve only one gen_pool associated with a device even if multiple gen_pools are created, fortunately right at the moment it is sufficient for the clients, hence provide NULL as a valid argument on both producer devm_gen_pool_create() and consumer gen_pool_get() sides. Because only one created gen_pool per device is addressable, explicitly add a restriction to devm_gen_pool_create() to create only one gen_pool per device, this implies two possible error codes returned by the function, account it on client side (only misc/sram). This completes client side changes related to genalloc updates. [akpm@linux-foundation.org: gen_pool_get() cleanup] Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-06-30genalloc: rename dev_get_gen_pool() to gen_pool_get()Vladimir Zapolskiy
To be consistent with other genalloc interface namings, rename dev_get_gen_pool() to gen_pool_get(). The original omitted "dev_" prefix is removed, since it points to argument type of the function, and so it does not bring any useful information. [akpm@linux-foundation.org: update arch/arm/mach-socfpga/pm.c] Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Takashi Iwai <tiwai@suse.de> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Mark Brown <broonie@kernel.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Alan Tull <atull@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Kevin Hilman <khilman@linaro.org> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-06-03ARM: imx6: initialize CCM_CLPCR_LPM into RUN mode earlierShawn Guo
Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function") moves imx6_set_lpm() from clock init function into imx6_pm_common_init(). This causes a hang when cpuidle support is enabled. The reason for that is ARM core clock is shut down unexpectedly by WAIT mode. It happens with the following call stack: cpuidle_register_governor() cpuidle_switch_governor() cpuidle_uninstall_idle_handler() synchronize_sched() wait_rcu_gp() wait_for_completion() When wait_for_completion() is called as above, all cores are idle/WFI. Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a hardware shutdown of the ARM core clock. To fix the regression, we need to ensure that CCM_CLPCR_LPM is initialized into RUN mode earlier than cpuidle governor registration, which is a postcore_initcall. This patch creates function imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into RUN mode, and have the function called from machine .init_irq hook, which should be early enough. Reported-by: Kevin Hilman <khilman@kernel.org> Fixes: 8fb76a07e2cb ("ARM: imx6: set initial power mode in pm function") Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Tyler Baker <tyler.baker@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-06-03ARM: imx6: let pm code map CCM block on its ownShawn Guo
We are about to move imx6 clock driver into drivers/clk, so let's get imx6 pm code map CCM block on its own rather than relying on clock driver to do the mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-06-03ARM: imx6: set initial power mode in pm functionShawn Guo
Rather than setting initial low-power mode in every single i.MX6 clock initialization function, we should really do that in pm code. Let's move imx6q_set_lpm(WAIT_CLOCKED) call into imx6_pm_common_init(). While at it, let's rename the function to imx6_set_lpm() since it's actually common for all i.MX6 SoCs. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-30ARM: imx6: convert GPC to stacked domainsMarc Zyngier
IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-05ARM: imx: support arm power off in cpuidle for i.mx6sxAnson Huang
This patch introduces an independent cpuidle driver for i.MX6SX, and supports arm power off in idle, totally 3 levels of cpuidle are supported as below: 1. ARM WFI; 2. SOC in WAIT mode; 3. SOC in WAIT mode + ARM power off. ARM power off can save at least 5mW power. This patch also replaces imx6q_enable_rbc with imx6_enable_rbc. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-05ARM: imx: remove unnecessary setting for DSMAnson Huang
Now we support DSM in OCRAM for all i.MX6 SoCs, the resume entry point is set in asm code of suspend-imx6.S, so no need to set the resume entry point for SRC in pre-suspend flow. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-12-09Merge tag 'soc-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Arnd Bergmann: "New and updated SoC support, notable changes include: - bcm: brcmstb SMP support initial iproc/cygnus support - exynos: Exynos4415 SoC support PMU and suspend support for Exynos5420 PMU support for Exynos3250 pm related maintenance - imx: new LS1021A SoC support vybrid 610 global timer support - integrator: convert to using multiplatform configuration - mediatek: earlyprintk support for mt8127/mt8135 - meson: meson8 soc and l2 cache controller support - mvebu: Armada 38x CPU hotplug support drop support for prerelease Armada 375 Z1 stepping extended suspend support, now works on Armada 370/XP - omap: hwmod related maintenance prcm cleanup - pxa: initial pxa27x DT handling - rockchip: SMP support for rk3288 add cpu frequency scaling support - shmobile: r8a7740 power domain support various small restart, timer, pci apmu changes - sunxi: Allwinner A80 (sun9i) earlyprintk support - ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits) ARM: mvebu: use the cpufreq-dt platform_data for independent clocks soc: integrator: Add terminating entry for integrator_cm_match ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support ARM: add lolevel debug support for asm9260 ARM: add mach-asm9260 ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ...
2014-12-04ARM: imx6: fix bogus use of irq_get_irq_dataMarc Zyngier
The imx6 PM code seems to be quite creative in its use of irq_data, using something that is very much a hardware interrupt number where we expect a virtual one. Yes, it worked so far, but that's only luck, and it will definitely explode in 3.19. Fix it by using a pair of helper functions that deal with the actual hardware. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-11-23ARM: imx: replace cpu type check with ddr type checkAnson Huang
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18ARM: imx: add standby mode support for suspendAnson Huang
Add standby mode support for suspend, to enter standby mode: echo standby > /sys/power/state; Use UART or RTC alarm to wake up system, when system enters standby mode, SOC will enter STOP mode with ARM core kept power on and 24M XTAL on. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18ARM: imx: mem bit must be cleared before entering DSM modeAnson Huang
According to hardware design, mem bit must be clear before entering DSM mode, as ARM core will be power gated in DSM mode. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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