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Using new wake up mode in gpcv2 bring in system issue, USB and AUDIO
meet stress test issue, design team is still checking the root
cause, let's use previous work around of GPC wake up to make sure
system is stable currently.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add support for i.MX7D DDR3 retention, the retention flow
needs to be optimized to support both LPDDR3 and DDR3.
Signed-off-by: Anson Huang <b20788@freescale.com>
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On i.MX7D, LPDDR3 and DDR3 have different retention flow, need to add DDR
type check during initialization.
Some DDR configurations may be updated lated, so it is better to
just read it from register instead of hard coding.
Signed-off-by: Anson Huang <b20788@freescale.com>
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On i.MX7D, the new GPC design has added a function of waking
up GPC from low power mode using internal GIC signal, which
means IRQ number < 32 can also wake up GPC from low power mode
as long as we set the wake up source correctly in A7_BSC, so
we can remove the workaround.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When ARM is waked up from WFI by irq number which < 32, GPC state
machine may keep ARM WFI signal available for next time entering
low power mode, so the issue is when we just set the low power mode
in GPC, ARM is still executing instructions, whenever GPC's low power
mode is enabled, the whole system is forced into low power mode, this
is unexpected, low power mode should only be entered when ARM is in WFI.
To fix this issue, we should make sure the last wakeup irq is from our
SOC platform, the irq number should be >= 32, so here we force the IOMUX
irq to be always pending by setting bit 12 of IOMUX_GPR1, then whenever
we set the low power mode in GPC, we should unmask it in GPC first then
mask it back, it will clean all previous internal logics in GPC low power
mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When Mega/Fast mix is off in DSM, we need to do DDR retention,
by default, Mega/Fast mix will be off in DSM, unless there
is any device inside Mega/Fast mix domain enabled as wakeup source.
Signed-off-by: Anson Huang <b20788@freescale.com>
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DSM of imx7d
With M/F mix off in DSM, during the window of SOC resume and UART driver
resume, the UART1 hardware is NOT working. So, add uart1 registers
save/restore during suspend/resume when no_console_suspend is enabled.
Signed-off-by: Anson Huang <b20788@freescale.com>
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As OCRAM will lost power in DSM mode, need to do save/restore
during enter/exit DSM mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add suspend/resume support for i.MX7D.
Signed-off-by: Anson Huang <b20788@freescale.com>
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