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suspend/resume
This patch ensures that the SCU and certain A9 CP15 registers state are maintained across
a suspend/resume cycle:
1. Need to ensure that SCU standby bit is set again after suspend/resume cycle, else
the system will never WAIT mode after a suspend/resume cycle. This bit should be enabled
on all SMP systems immaterial of whether CPUIDLE is enabled or not.
2. Several A9 errata workarounds involve setting bits in the ARM diagnostic register.
Save/restore this register across a suspend/resume cycle.
3. Save and restore the A9 power control register also.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
(cherry picked from commit 7b5b4ef5b3cdc65c0576f87cfa52bcca1bda8b33)
(cherry picked from commit 2a69800d94f182e975e4ed3ae2e64d30d35a3603)
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The dispmix feature works without problem since TO1.2.
This patch adds the back-compatibility for older chip.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit a187b916d55052fed10de1797009250095b598fb)
(cherry picked from commit dd27604b9d2a1bd294b3d8800e547bc526f87df7)
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GPIO number 0 *is* legal and must be accepted.
Set .ena_gpio to -ENODEV on regulators having no GPIO in preparation
of a code change to accept GPIO 0 in the config.
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This allow gplay to work.
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Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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These are Category B, hence workaround is essential.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch ensures that the low power idle code checks the status of the
dummy ldo2p5 regulator before disabling LDO2p5.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Add hwrng support for i.MX6SL.
1. Add RNG driver. This driver originated as fsl-rngc.c. It
has been modified to support device tree. The name has been
changed since it supports both b and c variants of RNG.
2. Added clock and compatible info to the device tree data.
3. Added the entry in the options in the Kconfig for hwrng.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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This patch mainly adds the clock route from external 24.576MHz OSC to internal
ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an
entirely synchronous clock source against CS42888.
[ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC,
we would get noise during the audio playback via ESAI->CS42888 even though
this generated clock's rate is equal to the external one statistically. It
might be resulted from the tiny difference between two clock source, which
might be crucial to the sensitive CODEC we use -- CS42888. So we here apply
the old 3.0.35 way to feed ESAI the same clock source as CS42888.
2, Ideally, we should use bypass mode for pll4 since we only need to get
the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't
entirely supported: The clock rate would be fixed to 24.0MHz if setting to
bypass, which would cause child clock get an incorrect rate and the driver
who uses the child clock fail to derive a needed clock rate, and it might
be dangerous to involve the clk-pllv3.c driver to this fix. Thus we here
apply 3.0.35 way provisionally. ]
Expected result:
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 786432000
pll4_post_div 0 1 786432000
pll4_audio_div 0 1 786432000
esai_sel 0 1 786432000
esai_pred 0 1 98304000
esai_podf 0 1 24576000
esai 0 1 24576000
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 49584be724d4d9c7a753d2b981b3932d8d871eb4)
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We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 5b74b6b26e4b44d265090fc6ad15b15ccb7b5cff)
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This patch removes the function imx6q_lvds_cabc_init() from the
machine layer since we have a dedicated Hannstar CABC driver to
control the CABC feature.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit b0d2154a9c63b2beba774e46b90ec3d55609c672)
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Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.
The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.
This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1
Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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There's a typo in cko1_sels[], thus fix it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Ensure that PLL is powered down when bypass rate is requested and
power it up when some other rate is requested.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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We are missing spba clock in imx6sl's clock tree, thus add it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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During DDR frequency change code or in low power IDLE code (in iMX6SL),
we need to ensure that all register addresses accessed in the IRAM
code are in the TLB. There should be no TLB walks when DDR is in self-refresh.
To ensure this flush the TLB before DDR frequency change and before
low power IDLE (only iMX6SL) procedures.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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When ARM executes WFI in audio playback mode, its possible to
lower the power consumed on the VDDHIGH_IN and VDDSOC_IN rails
by:
1. Putting DDR into self-refresh
2. Lower DDR frequency to 25MHz
3. Float DDR IO pads.
Also drop AHB to 8MHz in audio playback mode (aligning with 3.0.35)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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L2 can exit by 'reset' or Inband beacon (from remote EP)
toggling phy_powerdown has same effect as 'inband beacon'
So, toggle bit18 of GPR1, used as a workaround of errata
"PCIe PCIe does not support L2 Power Down"
WARNING: This is not official workaround for ERR005723. But we
have not found issue yet. User should take own risk to use it.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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eanble pcie msi support on imx6 platforms
* add check_device api in the msi chip.
* add the quirks into pcie_port struct for the deviation
from standard routines.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Based on community patch-set, re-setup pcie driver on
imx6 platforms.
* re-fine the pcie clks.
* add the pcie support in dts files.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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switch to community upstreamed pcie driver.
Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms"
This reverts commit d33370c77e57aed5a9b6733c9898418541fed54a.
Conflicts:
Documentation/devicetree/bindings/clock/imx6q-clock.txt
arch/arm/mach-imx/clk-imx6q.c
Signed-off-by: Richard Zhu <r65037@freescale.com>
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is enabled"
switch to community upstreamed pcie driver.
Revert "ENGR00277654 imx: pcie: enable pcie lm errata when pcie is enabled"
This reverts commit 72524b16f5cb4e13c1a194dda4cc0c4f206e4e46.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add support for low power audio playback:
1. SSI2 is sourced from PLL4
2. Extern_audio_clk is sourced from pll4
3. PLL4 is in bypass mode during audio playback (based
on freq requested by extern_audio_clk and ssi2 clk)
4. DDR is at 100MHz, AHB is at 24MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The display MIX can be power gated when EPDC, PXP and LCDIF are all inactive.
For safety, this feature is only supported when system enters suspend/standby
mode, in other words, this patch does not support run-time gating.
Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
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ARM clock is sourcing from pll1_sw, and pll1_sw can be either
from pll1_sys or step, so we should enable arm clock during
clock initialization instead of pll1_sys, otherwise, arm clock's
usecount would be incorrect and PLL1 will never be disabled even
it is not used.
Signed-off-by: Anson Huang <b20788@freescale.com>
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For ldo-bypass mode on i.MX6Q/DL sabresd board, we will use another WDOG2 to
reset external pmic to trigger POR event, rather than WDOG1 to trigger WDOG
event in ldo-enable mode. We need to consider it in common mxc_restart().
On i.MX6SL sabresd board we use WDOG1 to trigger WDOG event both ldo-bypass and
ldo-enable mode.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Using common mxc_restart interface to do restart instead of platform specific
interface of imx6sl_restart.
Signed-off-by: Robin Gong <b38343@freescale.com>
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There is ~10% possibility that the following emergency restart command
fails to reboot imx6q.
$ echo b > /proc/sysrq-trigger
The IMX restart routine mxc_restart() assumes that it will always run on
primary core, and will call imx_src_prepare_restart() to disable
secondary cores in order to get them come to online in the following
boot. However, the assumption is only true for normal kernel_restart()
case where migrate_to_reboot_cpu() will be called to migrate to primary
core, but not necessarily true for emergency_restart() case. So when
emergency_restart() calls into mxc_restart() on any secondary core,
system will hang immediately once imx_src_prepare_restart() is called
to disabled secondary cores. Since emergency_restart() is defined as a
function that is safe to call in interrupt context, we cannot just call
migrate_to_reboot_cpu() to fix the issue.
Fortunately, we just found that the issue can be fixed at imx6q platform
level. We used to call imx_src_prepare_restart() to disable all
secondary cores before resetting hardware. Otherwise, the secondary
will fail come to online in the reboot. However, we recently found that
after commit 6050d18 (ARM: imx: reset core along with enable/disable
operation) comes to play, we do not need to reset the secondary cores
any more. That said, mxc_restart() now can run on any core to reboot
the system, as long as we remove the imx_src_prepare_restart() call from
mxc_restart().
So let's simply remove imx_src_prepare_restart() call to fix the above
emergency restart failure.
Reported-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
(cherry picked from commit e2eb7f22c90ab47cce77c6836183fa5e684489d1)
Conflicts:
arch/arm/mach-imx/common.h
Signed-off-by: Robin Gong <b38343@freescale.com>
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The imx6q_restart() works fine with normal reboot but will run into
problem with emergency reboot like sysrq-b. In that case, of_iomap()
gets called from interrupt context and hence triggers the BUG_ON in
__get_vm_area_node().
Actually, since commit c1e31d1 (ARM: imx: create
mxc_arch_reset_init_dt() for DT boot), imx6q/dl should try to use
mxc_restart() by calling mxc_arch_reset_init_dt() beforehand, where
things like of_iomap() can be done.
The patch updates mxc_restart() a little bit to get it work for imx6q/dl
and kill imx6q_restart() completely.
Reported-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
(cherry picked from commit 87a84b69824d7fd63b20f3bc98d75c0238b8e7d0)
Conflicts:
arch/arm/mach-imx/mach-imx6q.c
Signed-off-by: Robin Gong <b38343@freescale.com>
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For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM:
2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Some clocks gates need to be set to 2b'01 to allow CCM
auto disabling them when system enters WAIT mode, this
setting can save many runtime power. These clock gates
are normally always enabled, so no need to add another
status for clk gate enable function, just set them to
right status when system boot up is good enough.
Signed-off-by: Anson Huang <b20788@freescale.com>
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i.MX6DL's axi clock is sourcing from pfd540 by default,
need to switch axi clock from pfd540 to periph when system
enters low bus mode, this is to allow pfd540 to be disabled,
and it also keeps clk tree correct.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Common clk framework will disable unused clks only if
they are enabled by default, so we need to add is_enabled
callback for clk framework to get clks' status.
pfd clocks are enabled by default, so we need to add this
interface for common clk framework to disable unused pfds.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Need to enable MMDC clocks to maintain the correct usecount, else
PLL2 can get disabled incorrectly thus hanging the system.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Incorrect clock disable of PLL2 caused random hangs during
DDR freq change in iMX6DL.
Remove PERCLK freq change code as this is not required for TO1.1
and later.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This is used to avoid a warning:
WARNING: at /home/b29397/work/projects/linux-2.6-imx/drivers/gpio/gpiolib.c:126
gpio_to_desc+0x30/0x44()
invalid GPIO -517
Modules linked in:
....
gpiod_request: invalid GPIO
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Before we have a common can tranceiver binding to handle gpios
operations, we use auxdata to pass flexcan_switch function first.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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From the clock tree defined in i.MX6Q Reference Mannual, the parent of can_root
clock should be pll3_60m.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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With the new tap-out of i.MX6DQ(TO1.5) and i.MX6DL/SOLO(TO1.2), we need add
more chip revision support in order to report the chip revision correctly.
Signed-off-by: Jason Liu <r64343@freescale.com>
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i.MX6DL did NOT have 1.2GHz setpoint, no need to check speed
grading fuse for 1.2GHz opp, otherwise, there will be always
warning message of "failed to disable 1.2 GHz OPP" when system
boot up on i.MX6DL.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Use for_each_online_cpu instead of for_each_present_cpu to take this case,
otherwise system will crash as below when go into low bus with 'maxcpus=1'
setting in command line.
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = 80004000
[00000000] *pgd=00000000
Internal error: Oops: 817 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 68 Comm: kworker/0:2 Not tainted 3.10.17-16647-g0868f35 #27
Workqueue: events reduce_bus_freq_handler
task: ac156d80 ti: ac2a2000 task.ti: ac2a2000
PC is at update_ddr_freq+0x98/0x2d0
LR is at 0x0
pc : [<80021928>] lr : [<00000000>] psr: 400f0013
sp : ac2a3e98 ip : 00000000 fp : 814db740
r10: 016e3600 r9 : 00000000 r8 : 00000000
r7 : 814de900 r6 : 80c60cc0 r5 : 0000000f r4 : 80c60dc0
r3 : 00000000 r2 : 80c60dc0 r1 : 80c60d34 r0 : 00000000
Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 3c49404a DAC: 00000015
Process kworker/0:2 (pid: 68, stack limit = 0xac2a2238)
Stack: (0xac2a3e98 to 0xac2a4000)
3e80: 00000000 00000000
3ea0: 00000000 00000000 00000001 80c60cc0 80c603a4 80c60cc0 814de900 00000000
3ec0: 00000000 ac2a2038 814db740 80020154 00000064 ac02f6c0 00000004 80c2103c
3ee0: 80c60d38 814db740 814de900 80020628 ac135780 8003d7ac 00000001 ac083eb8
3f00: 00000000 00000000 00000003 ac135780 814db754 ac135798 ac2a2000 ac2a2030
3f20: 00000001 ac2a2000 814db740 8003e4b8 8003e380 00000000 00000000 80c5fcc1
3f40: ac2a3f64 ac083ea0 00000000 ac135780 8003e380 00000000 00000000 00000000
3f60: 00000000 800437e0 fd7efff9 00000000 7faf7bfd ac135780 00000000 00000000
3f80: ac2a3f80 ac2a3f80 00000000 00000000 ac2a3f90 ac2a3f90 ac2a3fac ac083ea0
3fa0: 8004372c 00000000 00000000 8000e018 00000000 00000000 00000000 00000000
3fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3fe0: 00000000 00000000 00000000 00000000 00000013 00000000 fffc7fae d4cadbdb
[<80021928>] (update_ddr_freq+0x98/0x2d0) from [<80020154>] (reduce_bus_freq+
0x58/0x518)
[<80020154>] (reduce_bus_freq+0x58/0x518) from [<80020628>] (reduce_bus_freq_
handler+0x14/0x24)
[<80020628>] (reduce_bus_freq_handler+0x14/0x24) from [<8003d7ac>] (process_one
_work+0x10c/0x374)
[<8003d7ac>] (process_one_work+0x10c/0x374) from [<8003e4b8>] (worker_thread+
0x138/0x3fc)
[<8003e4b8>] (worker_thread+0x138/0x3fc) from [<800437e0>] (kthread+0xb4/0xb8)
[<800437e0>] (kthread+0xb4/0xb8) from [<8000e018>] (ret_from_fork+0x14/0x3c)
Code: e5940014 e3002dc0 e594e018 e34820c6 (e5835000)
---[ end trace 206df98575045d04 ]---
Unable to handle kernel paging request at virtual address ffffffec
pgd = 80004000
[ffffffec] *pgd=3ff7e821, *pte=00000000, *ppte=00000000
Signed-off-by: Robin Gong <b38343@freescale.com>
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Bug log during kernel boot:
...
failed to find fsl,imx6q-iomux-gpr regmap
...
The issue is imx6q_1588_init() is called before of_platform_populate().
of_platform_populate() walks the device tree and creates devices from
nodes. imx6q_1588_init() call syscon_regmap_lookup_by_compatible() to
get the device base on the given device node, since the device cannot
created for the node, so it is failed.
So, move the 1588 init function to behind of of_platform_populate().
Signed-off-by: Fugang Duan <B38611@freescale.com>
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1. add epit1, epit2 and tzasc2 clock gate to clk tree so that
clk framework can manage these clock gates;
2. adjust ipu2_di1 clock gate registry code to follow hardware
register CG index sequence.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add caam clock gate nodes into clock tree, so that caam
driver can manage its clock gate to save power.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add optimizations so that the low power IDLE mode numbers match
between the 3.10.9 and 3.0.35 kernel.
Optimizations include:
1. Disable unused PLLs and PFDs in clock init
2. Some of the drivers call clk_prepare in probe and enable much
later. clk_pllv3_prepare locks the PLL disallowing some of the low
power optimizations. For iMX6SL ensure that clk_pllv3_prepare does
not lock the PLL.
3. Ensure that MMDC_CH0_LPM_HS is set when WAIT mode is entered.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add CLK_SET_RATE_PARENT flag for epdc pixel clock to allow the rate change
operation to propagate up to the clock's parent in order to get desired rate.
Signed-off-by: Robby Cai <R63905@freescale.com>
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In order to optmize low power IDLE numbers all PLLs should be in bypass.
On imx6sl, UART can be sourced directly from the 24MHz XTAL. Its frequency
is limited to 4MHz due to an internal divide by 6 divider.
For customer who don't require higher uart speeds add "uart_at_4M"
to the kernel command line.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Added a new bus freq mode - ultra_low_bus_freq_mode.
In this mode the ARM is the only bus master that is active and
the system is already in low power idle mode.
And when ARM executes WFI in this mode, we do some aggressive
power savings techinques like:
1. Drop DDR freq to 1MHz
2. Drop AHB freq to 3MHz
3. Float the DDR IO pads
4. If all PLLs are in bypass (which should be the case), do
some analog power saving options like reducing the OSC-bias current,
turning off the regular bandgap, disabling the regular 2P5, enabling
the weak 2p5 etc.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.
When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAC address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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