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qnap_tsx1x_register_flash is only called by qnap_ts219_init and
qnap_ts41x_init which both live in .init.text, too. So the move is OK.
This fixes the following warning in kirkwood_defconfig:
WARNING: vmlinux.o(.text+0x9334): Section mismatch in reference from the function qnap_tsx1x_register_flash() to the variable .init.data:qnap_tsx1x_spi_slave_info
The function qnap_tsx1x_register_flash() references
the variable __initdata qnap_tsx1x_spi_slave_info.
This is often because qnap_tsx1x_register_flash lacks a __initdata
annotation or the annotation of qnap_tsx1x_spi_slave_info is wrong.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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* git://git.infradead.org/mtd-2.6: (154 commits)
mtd: cfi_cmdset_0002: use AMD standard command-set with Winbond flash chips
mtd: cfi_cmdset_0002: Fix MODULE_ALIAS and linkage for new 0701 commandset ID
mtd: mxc_nand: Remove duplicate NAND_CMD_RESET case value
mtd: update gfp/slab.h includes
jffs2: Stop triggering block erases from jffs2_write_super()
jffs2: Rename jffs2_erase_pending_trigger() to jffs2_dirty_trigger()
jffs2: Use jffs2_garbage_collect_trigger() to trigger pending erases
jffs2: Require jffs2_garbage_collect_trigger() to be called with lock held
jffs2: Wake GC thread when there are blocks to be erased
jffs2: Erase pending blocks in GC pass, avoid invalid -EIO return
jffs2: Add 'work_done' return value from jffs2_erase_pending_blocks()
mtd: mtdchar: Do not corrupt backing device of device node inode
mtd/maps/pcmciamtd: Fix printk format for ssize_t in debug messages
drivers/mtd: Use kmemdup
mtd: cfi_cmdset_0002: Fix argument order in bootloc warning
mtd: nand: add Toshiba TC58NVG0 device ID
pcmciamtd: add another ID
pcmciamtd: coding style cleanups
pcmciamtd: fixing obvious errors
mtd: chips: add SST39WF160x NOR-flashes
...
Trivial conflicts due to dev_node removal in drivers/mtd/maps/pcmciamtd.c
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Add a kirkwood_nand_init_rnb() call to allow boards which
have RnB line detection to register this instead of a
static delay.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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GuruPlug Standard: 1 Gb Ethernet, 2 USB 2.0
GuruPlug Plus: 2 Gb Ethernet, 2 USB 2.0, 1 eSATA, 1 uSD slot
References:
http://www.globalscaletechnologies.com/t-guruplugdetails.aspx
http://plugcomputer.org
This patch is for GuruPlug Plus, but it supports Standard version
as well.
Signed-off-by: Siddarth Gore <gores@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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Commit "Input: add KEY_WPS_BUTTON definition"
added a generic keycode for WPS button.
Let's use it, instead of "F1" mapping.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Conflicts:
arch/arm/mach-mx2/devices.c
arch/arm/mach-mx2/devices.h
sound/soc/pxa/pxa-ssp.c
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* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits)
ARM: Eliminate decompressor -Dstatic= PIC hack
ARM: 5958/1: ARM: U300: fix inverted clk round rate
ARM: 5956/1: misplaced parentheses
ARM: 5955/1: ep93xx: move timer defines into core.c and document
ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c
ARM: 5953/1: ep93xx: fix broken build of clock.c
ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig
ARM: 5949/1: NUC900 add gpio virtual memory map
ARM: 5948/1: Enable timer0 to time4 clock support for nuc910
ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk
ARM: make_coherent(): fix problems with highpte, part 2
MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
ARM: 5945/1: ep93xx: include correct irq.h in core.c
ARM: 5933/1: amba-pl011: support hardware flow control
ARM: 5930/1: Add PKMAP area description to memory.txt.
ARM: 5929/1: Add checks to detect overlap of memory regions.
ARM: 5928/1: Change type of VMALLOC_END to unsigned long.
ARM: 5927/1: Make delimiters of DMA area globally visibly.
ARM: 5926/1: Add "Virtual kernel memory..." printout.
ARM: 5920/1: OMAP4: Enable L2 Cache
...
Fix up trivial conflict in arch/arm/mach-mx25/clock.c
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Accept SD CD and SD WP in accordance to
http://plugcomputer.org/data/docs/Sheeva-PowerPlug-V1.3-GTI-090906.pdf
on MPP 47 and 44 respectively on the eSATA SheevaPlug
Signed-off-by: John Holland <john.holland@cellent-fs.de>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Enable the kirkwood SATA SoC interface on the eSATA SheevaPlug.
Signed-off-by: John Holland <john.holland@cellent-fs.de>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
--
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Allow basic eSATA SheevaPlug board configuration and build.
Signed-off-by: John Holland <john.holland@cellent-fs.de>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
--
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Makes it consistent with VMALLOC_START
Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Otherwise more complicated uart configuration won't be possible.
We can use r1 for tmp register for both head.S and debug.S.
NOTE: This patch depends on another patch to add the the tmp register
into all debug-macro.S files. That can be done with:
$ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/"
arch/arm/*/include/*/debug-macro.S
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch add a GPIO LED named "ns_v2:blue:sata" which can be used to
enable or disable SATA activity LED blinking.
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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The Internet and Network Space v2 boards are very close. The only
difference is that there is no USB type B plug wired on the Internet
Space v2.
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Inspired by the mach-ep93xx flattening work, there is really not
much difference between the OpenRD base and client board support
so they should be merged together.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Acked-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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The (void *) cast is not needed when setting dev.platform_data to the
address of the data. Remove the casts.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Remove the code duplication found in the setup files of TS-219 and
TS-41x.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Add two new models from QNAP to the help text. They are compatible
with the TS-119/TS-219 and therefore supported by the current code.
The only difference is that they have less RAM (256 MB instead of
512 MB), a slower CPU (800 MHz vs 1.2 GHz) and a plastic case.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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MPP36 is used on the QNAP TS-11x/TS-21x devices to indicate how
much RAM there is: it's high for 512 MB RAM (TS-x19) and low for
256 MB (TS-x10). While this may not be very useful, let's add
it for completeness.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Add support for the QNAP TS-410, TS-410U, TS-419P and TS-419U
Turbo NAS.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Disable propagation of mbus errors to the CPU local bus, as this causes
mbus errors (which can occur for example for PCI aborts) to throw CPU
aborts, which we're not set up to deal with.
Reported-by: Dieter Kiermaier <dk-arm-linux@gmx.de>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Instead of allocating PCI devices I/O port bus addresses from the
000xxxxx I/O port range as intended, due to a bus versus physical
address mixup, the Kirkwood PCIe handling code inadvertently
allocated I/O port bus addresses from the f20xxxxx address range
(which is the physical address range of the PCIe I/O mapping window),
but then direct all I/O port accesses to bus addresses 000xxxxx,
which would then not be decoded at all.
Fix this by setting the base address of the PCIe I/O space struct
resource to KIRKWOOD_PCIE_IO_BUS_BASE instead of the incorrect
KIRKWOOD_PCIE_IO_PHYS_BASE, and fix up __io() to expect addresses
offsetted by the former instead of the latter.
(The suggested fix of directing I/O port accesses from the host to
bus addresses f20xxxxx instead has the problem that assigning full
32bit I/O port bus addresses (f20xxxxx) doesn't work on all PCI
devices, as not all PCI devices implement full 32 bit BAR registers
for I/O ports. We should really try to allocate I/O port bus
addresses that fit in 16 bits.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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kirkwood_timer_init() and kirkwood_pcie_setup() lack of __init which
causes following warnings:
WARNING: vmlinux.o(.text+0x9568): Section mismatch in reference from
the function kirkwood_timer_init() to the function
.init.text:kirkwood_find_tclk()
The function kirkwood_timer_init() references
the function __init kirkwood_find_tclk().
This is often because kirkwood_timer_init lacks a __init
annotation or the annotation of kirkwood_find_tclk is wrong.
WARNING: vmlinux.o(.text+0x979c): Section mismatch in reference from
the function kirkwood_pcie_setup() to the function
.init.text:orion_pcie_setup()
The function kirkwood_pcie_setup() references
the function __init orion_pcie_setup().
This is often because kirkwood_pcie_setup lacks a __init
annotation or the annotation of orion_pcie_setup is wrong.
Signed-off-by: lijie <eltshanli@gmail.com>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Acked-by: Dieter Kiermaier <dk-arm-linux@gmx.de>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Initialize PCI/PCIe on the QNAP TS-119, TS-219 and TS-219P hardware
allowing the use of the discrete eSATA controller connected to the PCIe
bus in the TS-219P.
Signed-off-by: John Holland <john.holland@cellent-fs.de>
Tested-by: Thomas Reitmayr <treitmayr@devbase.at>
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Ron Lee <ron@debian.org>
Signed-off-by: Dhaval Vasa <dhaval.vasa@einfochips.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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reference:
http://open-rd.org
http://code.google.com/p/openrd
This patch is tested for:
1. Boot from DRAM/NAND flash
2. NAND read/write/erase
3. GbE0
4. USB read/write
FIXME:
1. SD/UART1 selection
2. MPP configuration (currently, default)
3. PEX
Signed-off-by: Dhaval Vasa <dhaval.vasa@einfochips.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Siddarth Gore <gores@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Correct define typo (. -> ,)
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Always creating the physical mapping should do no harm, so let's remove
the interface that was provided for its optional creation and make the
mapping static.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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We don't have to define resources to the minimal physical window size
as setup_cpu_win() will cope with smaller sizes already.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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The Orion watchdog driver is also used on Kirkwood.
Convention is to use orion5x for stuff specific to 88F5xxx Orion chips
and simply "orion" for shared stuff across SoCs including Kirkwood.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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The Kirkwood architecture uses the same watchdog device as the Orion
architecture. This patch adds orion5x_wdt as a platform device for
Kirkwood.
Signed-off-by: Thomas Reitmayr <treitmayr@devbase.at>
Tested-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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To save power:
1. Enabling clock gating of unused peripherals
2. PLL and PHY of the units are also disabled (when possible.
Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Common resource and platform device structures are moved to common.c
and only the partition table and chip delay remains a per board
parameter.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Erik Benada <erikbenada@yahoo.ca>
[ nico: fix locking, additional cleanups ]
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Just like commit 1419468ab548, let's save some TLB entries by making
ioremap() return pointers into the boot-time Kirkwood peripheral
iotable mapping whenever someone tries to ioremap any part of the Kirkwood
peripheral register space.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Siddarth Gore <gores@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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