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path: root/arch/arm/mach-mx6/clock.c
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2012-07-20ENGR00211670- CPUFREQ-Set CPU to maximum frequency before entering STOP modeRanjani Vaidyanathan
Ensure that the CPUFREQ driver sets the CPU to its maximum frequency when it is suspended. Also change the WAIT macro in clock.c to use GPT counter for the delay instead of getnsdayoftime(). As the kernel timekeeping driver is suspended before CPUFREQ and this causes a dump during suspend. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00209617 MX6x - Add WAIT mode workaroundRanjani Vaidyanathan
To avoid the ARM from accepting an interrupt in the dangerous window, reduce the ARM core freq just before the sytem is about to enter WAIT state. Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG ratio. Use the ARM_PODF to drop the frequency. In a multicore case the frequency is dropped only when all the 4 cores are going to be in WFI. In case of single core environment, its easy to drop the ARM core freq just before WFI since there is no need to identify the state of the other cores. Some other points to note: 1. If "mem_clk_on" is added to the command line, the memory clocks will not be gated in WAIT mode. This will increase the system IDLE power. This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1. 2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz, we cannot match the 12:5 ratio using ARM_PODF only. In this case, donot clock gate the memories in WAIT mode (available on MX6SL, MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable system wide WAIT entry in this case. In STOP mode, always ensure that the memory clocks are gated, else power impact will be significant. WAIT mode is enabled by default with this commit. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00209520-02 - MX6SL MSL : Adjust FEC clock name.Fugang Duan
- Ethernet clock source name is differentiated by IP name. FEC IP clock name is "FEC"; ENET IP clock name is "enet". Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-07-20ENGR00181068: MX6 Source IPU_HSP and AXI clocks from 540M PFD.Ranjani Vaidyanathan
IPU_HSP clocks should NOT be sourced from MMDC clock since the MMDC clock can be scaled. Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead. Also don't source AXI_CLK from periph_clk as this domain is scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK clock to be sourced from PLL3_PFD_540M too. When the system needs to enter low power mode, AXI_CLK is switched from PLL3_PFD_540M to periph_clk. And then switched back when low power mode is exited. The code will print a warning message if PLL3_PFD_540M is relocked to a different frequency when IPU_HSP or axi_clk is sourced from it. Currently remove the support for 400Mhz DDR working point for MX6Q since we can get IPU underruns during the DDR frequency transitions. The DDR freq change code needs to ensure that all bus clocks donot exceed max frequency during the frequency transition. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400MWayne Zou
On mx6dl, set ipu2_clk's parent from pll2_pfd_400M. On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-20ENGR00180185: MX6-Add support for low power audio playbackRanjani Vaidyanathan
The DDR frequency needs to be at 50MHz for low power audio playback. So added a new low power mode for audio. Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00179722: MLB: set correct mlb sys clock in mx6dlTerry Lv
In Rigel validatioin, the MLB sys_clock isn't using the right frequency after boot. In arik, the register CBCMR controls gpu2d clock, not mlb clock, mlb is sourced from axi_clock. But In rigel, the axi clock is lower than in mx6q, so mlb need to find a new clock root. The gpu2d clock is then root of mlb clock in rigel. Thus we need to add setting to support this change. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-07-20ENGR00180096 change NAND clock source to pll2_pfd_400MAllen Xu
change clock source explicitly by calling set_parent() function Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-07-20ENGR00180075 MX6: change CLKO source to pll4_audio_main_clkGary Zhang
change CLKO source to pll4_audio_main_clk for low power mode consideration Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-07-20ENGR00179782: i.mx6: consolidate mx6q/dl_revision() supportJason Liu
The idea is to get the soc silicon revision from DIGPROG register Of ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent with bootloader which need pass the system_rev by ATAG. This patch also will print the chip name and revision when kernel boot up since this information is important for customer to know. on i.mx6q TO1.1, it will print as the following: CPU identified as i.MX6Q, silicon rev 1.1 Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-20ENGR00179804 change NAND clock source from pll2_pfd_352M to pll2_pfd_400MAllen Xu
Due to pll2_pfd_352M would be used for LVDS, change NAND clock source to pll2_pfd_400M. Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-07-20ENGR00179685 MX6 clock:Cleanup LDB DI parent clockLiu Ying
According to ticket TKT071080, 0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1. However, MX6DL uses mmdc_ch1 as LDB DI parent clock. This patch corrects the LDB DI parent clock setting. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-20ENGR00179747: MX6DL-Fix boot failureRanjani Vaidyanathan
Fix the boot failure caused by: 8f0c21e06d4f7d0c7c078d6261ccd75f2a45c3ab MX6- Add bus frequency scaling support There is no SATA on MX6DL. Accessing SATA PHYs early in the boot process causes the system to crash. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1Liu Ying
This patch corrects LDB DI clock's parent clock to be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0 according to ticket TKT071080(0b011 for ldb_dix_clk_sel field in CCM_CS2CDR is changed from pll3_pfd_540M to mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1). Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-07-20ENGR00179574: MX6- Add bus frequency scaling supportRanjani Vaidyanathan
Add support for scaling the bus frequency (both DDR and ahb_clk). The DDR and AHB_CLK are dropped to 24MHz when all devices that need high AHB frequency are disabled and the CORE frequency is at the lowest setpoint. The DDR is dropped to 400MHz for the video playback usecase. In this mode the GPU, FEC, SATA etc are disabled. To scale the bus frequency, its necessary that all cores except the core that is executing the DDR frequency change are in WFE. This is achieved by generating interrupts on un-used interrupts (Int no 139, 144, 145 and 146). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00178597 [MX6DL/S] Multi-instance test in GC880 cause system hangLarry Li
In our code 3d sharder clock uses 3d core clock CCGR field as its enable bit. That works for MX6Q. But MX6DL uses 3d sharder clock as 2d core clock, while disable 2d core clock, it will disable 3d core by mistake. To fix it, remove the enable bit setting of 3d shader clock in clock.c file. Signed-off-by: Larry Li <b20787@freescale.com>
2012-07-20ENGR00177241-1 mx6 close APBH DMA clock when no I/O operationAllen Xu
When there is no NAND I/O operation, close all the reference clock, include GPMI,BCH and APBH clock. Signed-off-by: Allen Xu <allen.xu@freescale.com>
2012-07-20ENGR00178875-1 VDOA: Add vdoa support on i.MX6 SOC platformWayne Zou
Add vdoa support on i.MX6 SOC platform Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-20ENGR00178915: imx6 clock fix build warningsAdrian Alonso
* Fix build warnings * clock.c: In function '_clk_pll1_enable': warning: no return statement in function returning non-void * clock.c: In function 'mx6_clocks_init': warning: unused variable 'reg' Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-07-20ENGR00178763: MX6-Fix TO1.0 boot-fail issueRanjani Vaidyanathan
TO1.0 parts donot boot properly after the following commit: 88d3af87222b37e454acd6a8de3b0cf18180da32 MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq is below 400MHz. Correct gpt_clk was not getting enabled. Fix by adding the appropriate gpt_clk. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00176366: MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq is below 400MHz.Ranjani Vaidyanathan
PLL1 can be disabled whenever ARM_CLK is below 400MHz since ARM_CLK can be sourced from PLL2_PFD_400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-07-20ENGR00178128 mx6 pcie: pass PCIEX1 CT network card verificationsRichard Zhu
what're done: * PCIE topology, RC should be on bus 0, EP should be on bus 1. Root Cause: The CLASS_REV of RC CFG header, specified by SPEC to be RO, should be set to PCI_CLASS_BRIDGE_PCIclass * Added PCIE PWR EN and RESET * iATU wrong configurations. Root Cause: The outbounds excepted the CFG region0 should be removed. Otherwise, the memory ATU wouldn't work correctly. * CT DHCP hang Root Cause: PLL8 is set to bypass mode when linux close fec, and the PCIe ref clk would be broken by PLL8 bypass mode. The parent clk of pcie ref clk is disabled by FEC, since linux would try to disable the none-addressed NIC after DHCP. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-07-20ENGR00177310-2 mx6 clock: change _clk_clko_round_rateLily Zhang
Change _clk_clko_round_rate and ensure the clock should be less than the input rate. Signed-off-by: Lily Zhang <r58066@freescale.com>
2012-07-20ENGR00176469-4: Remove build warnings in clock.cTerry Lv
Remove build warnings in clock.c. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-07-20ENGR00176469-3: Remove build warnings in mlbTerry Lv
Remove build warnings in mlb. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-07-20ENGR00176469-1: Improve the performance of MLBTerry Lv
Pll clock change to make pll clocked more stable. Signed-off-by: Terry Lv <r65388@freescale.com>
2012-07-20ENGR00176655:mx6:remove openvg_axi_clk from gpu2d_axi_clk's secondaryWu Guoxing
if set vg clock as 2d axi clk's secondary will make 2d axi clk use count error Signed-off-by: Wu Guoxing <b39297@freescale.com>
2012-07-20ENGR00176160 [MX6]Correct PLL1 freq change flowAnson Huang
Previous PLL1 freq change is done by switching CPU clock to 400M pfd or 24M OSC, then modifying PLL1 div directly, and switch back CPU clock immediately, it will result in CPU clock stop during PLL1 hardware lock period, thus, DRAM FIFO may blocked by the data CPU requested before PLL1 clock changed, and it will block other devices accessing DRAM, such as IPU, VPU etc. It will cause underrun or hang issue. We should wait PLL1 lock, then switch back. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-20ENGR00176068-1 mx6q: add smp_twd clock for localtimerXinyu Chen
Add a smp_twd system clock which is simple clock from parent of cpu_clk, and it's rate is half of the cpu_clk. This is used for reprograming the twd clock event after cpu freq is changed. Also disable local timer setup when wait mode enabled. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-07-20ENGR00175219-5 MX6: remove cko1_clk in clock.cGary Zhang
there are clko_clk and cko1_clk in clock.c which operate the same CKO1 clock source. remove cko1_clk codes to avoid operation confusion. Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-07-20ENGR00174886-1 - EPDC fb: Don't register EPDC unless "epdc" kernel option setDanny Nold
- Add E Ink support as a default for MX6 platforms - Conditionalize registration of EPDC-related modules based on "epdc" kernel command line option Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-07-20ENGR00171079-7 mx6q clock anaclk input source clockAdrian Alonso
* Add mx6q anaclk_1/2 clock input source clock support * anaclk can be bypassed to pll4_audio. * _clk_audio_video_set_parent allows to bypass anaclk input clock source, for sabreauto platform anaclk_2 is the clock source for cs42888 and this clock needs to be bypassed to esai to supply the same master clk signal. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-07-20ENGR00174897 i.mx6: clock: fix axi clock mux settingJason Liu
Fix the error in the axi clock mux setting, - reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET); + reg |= ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET); Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-20ENGR00174896 i.mx6: i.mx6l: clock: gpu/vpu clock adjustmentJason Liu
GPU clock on i.mx6dl: gpu2d_core_clk source from gpu3d_shader_clk, gpu3d_axi_clk source from mmdc0 directly, 400Mhz by default, gpu2d_axi_clk source from mmdc0 directly, 400Mhz by default, AXI_CLK on i.mx6dl: set axi_clk parent to pll3_pfd_540M and divid by 2, which will get 270Mhz by default, VPU clock on i.mx6dl: VPU will parent from axi_clk, then by default, it will be 270Mhz, which will be suitable for VPU 1080p support. pll3_pfd_540M on i.mx6dl will be dedicated to VPU/IPU/AXI_CLK use, other users should not change this assignment Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-20ENGR00174630 [MX6]Disable GPT serial clockAnson Huang
Currently we use 24MHz clock as GPT's clock source, serial clock can be disabled, it sourced from high freq clock, gating it can save ~8mA @VDDSOC. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-20ENGR00174649 i.mx6dl: clock: set ipu1 clock to 270M, change ldb_di_clk parentWayne Zou
Set ipu1 clock to 270M, source from pll3_pfd_540M for best performance. And set ldb_di_clk parent to pll2_pfd_352M. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-07-20ENGR00174532 [mx6Q]Change 2D clock to 480MLarry Li
Change GPU2D core clock to 480M and use PLL3 as parent Signed-off-by: Larry Li <b20787@freescale.com>
2012-07-20ENGR00174106-1 - EPDC fb: Support EPDC on MX 6DL/SDanny Nold
- Added EPDC and EPD PMIC (Maxim 17135) to MX6Q ARM2 board file - Added EPDC-related IOMUX and GPIO settings - Added EPDC clock configuration settings to clock file - Updated config files with EPDC and Maxim 17135 config entries Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-07-20ENGR00174425: i.mx6: i.mx6dl: clock: set gpu2d_axi clock parent to mmdc0Jason Liu
on i.mx6dl, gpu2d_axi clock is directly connected to mmdc0 Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-20ENGR00174423-2: i.mx6: clock: code clean up in pfd_set_rateJason Liu
code clean up by removing the dead code in function pfd_set_rate Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-20ENGR00174299-2: MSL part: add ePxP V2 driverRobby Cai
MSL part for ePxP v2 driver Signed-off-by: Robby Cai <R63905@freescale.com>
2012-07-20ENGR00174309:mx6/dl: gpu:enable 2d and 3dWu Guoxing
mx6dl do not have 3d shader core, and 2d core clk is using 3d shader clock. Signed-off-by: Wu Guoxing <b39297@freescale.com>
2012-07-20ENGR00174302 [MX6]Clean build warningAnson Huang
arch/arm/mach-mx6/clock.c:1749: warning: unused variable 'reg'; Signed-off-by: Anson Huang <b20788@freescale.com>
2012-07-20ENGR00174033-1 MX6 PCIE: add pcie RC driverRichard Zhu
Add PCIE RC driver on MX6 platforms. Based on iwl4965agn pcie wifi device, verified the following features. * Link up is stable * map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-07-20ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400MJason Liu
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need set DDR/periph_clk parent to pll2_mfd_400M during clock init, which will setup the clock usecount of pll2_mfd_400M correctly, otherwise, when all the child device with clock source from pll2_mfd_400M turn off, the pll2_mfd_400M will turns off automaticly, which will cause system hang due to DDR clock is off when code is runing on it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-20ENGR00172274-01 - [MX6]: rework IEEE-1588 ts_clk in MX6Q ARIK CPU board.Fugang Duan
- Fix GPIO_16 IOMUX config. - Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: Enet work fine at 100/1000Mbps in TO1.1. IEEE 1588 timestamp is convergent. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-07-20ENGR00173869-5: i.mx6: don't turn off MMDC clock on i.mx6dlJason Liu
MMDC clock is from pll2_pfd_400M, thus we can't turn it off Signed-off-by: Jason Liu <r64343@freescale.com>
2012-07-20ENGR00173731-5 MX6Q/ARCH :rename gpmi-nfc to gpmi-nandHuang Shijie
rename the gpmi-nfc to gpmi-nand. Signed-off-by: Huang Shijie <b32955@freescale.com>
2012-07-20ENGR00173639 mx6q: clock: PLL3's power can be off at runtime at TO1.1Peter Chen
It is the fix for Design PDM TKT064178, IC has already verified it, and no more power consumption for setting/clear this bit. With this bit, the power of pll3 can be off even the power bit for pll3 is on. In order to support USB wakeup, the power bit for pll3 should be always on, and the power of pll3 is controller by USB hardware and this new added bit at runtime. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-07-20ENGR00173586-2 [MX6] Add support to source GPT from 24MHzRanjani Vaidyanathan
On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced from a constant source (better for frequency scaling). Currently we set the GPT clock to 3MHz (24MHz div by 8). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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