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path: root/arch/arm/mach-mx6/mm.c
AgeCommit message (Expand)Author
2014-06-06ENGR00316180: [iMX6x] Support IRAM page table when DDR is in self-refresh.Ranjani Vaidyanathan
2014-06-03ENGR00279566: ARM: i.MX6: Enable L2 cache I/D prefetch functionJason Liu
2014-06-03ENGR00275391 i.mx6d/q: disable the double linefill feature of PL310Jason Liu
2014-06-03ENGR00182324-4 - MX6SL MSL: Enable L2 cache as OCRAM functionalityJason Liu
2014-06-03ENGR00182324-2 - MX6SL MSL: Add Support for i.MX6SoloLite SoC revisionJason Liu
2014-06-03ENGR00179782: i.mx6: consolidate mx6q/dl_revision() supportJason Liu
2014-06-03ENGR00174652 i.mx6: explicitly set the LPM mode to run mode during early bootupJason Liu
2014-06-03ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() supportJason Liu
2014-06-03ENGR00170434: MX6 - Add support to read Silicon versionRanjani Vaidyanathan
2014-06-03ENGR00154931 [MX6]L2 cache init wrong after resumeAnson Huang
2014-06-03ENGR00153601 [MX6]Adjust L2 cache parameterAnson Huang
2014-06-03ENGR00152668 [MX6]Enable arch_resetAnson Huang
2014-06-03ENGR00152845-3 MSL imx6: msl files changes.Jason Chen
2014-06-03ENGR00139229-1 MX6: Bring up i.MX6 sabreauto with Single coreZeng Zhaoming
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