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path: root/arch/arm/mach-mx6/mm.c
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2012-02-16ENGR00174652 i.mx6: explicitly set the LPM mode to run mode during early bootupJason Liu
the reset value of LPM[1:0] in CCM_CLPCR register is b'01, which means system will enter into wait mode on next assertion of dsm_request signal. In order to avoid the system unexpectly enter the wait mode during bootup we need set the LPM mode to run mode explicity during early boot up phase, Anytime, we want system to enter the wait mode, the sw procedure is: mxc_cpu_lp_set(LP_MODE) -> set CCM_CLPCR register -> system enter wait mode This patch also fix linux kernel reboot stress test on i.mx6dl, without this patch linux kernel reboot test will fail random with error like this: [ 12.091220] Bad mode in interrupt handler detected [ 12.096056] Bad mode in interrupt handler detected [ 12.100851] Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-07ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() supportJason Liu
In order to support one image for i.mx6q and i.mx6dl, we introduce the below functions by diff the value reading from ANATOP ID register. cpu_is_mx6q() and cpu_is_mx6dl() The layout for the register defines: Major Minor i.MX6Q1.1: 6300 01 i.MX6Q1.0: 6300 00 i.MX6DL1.0: 6100 00 For the common bits shared across all i.mx6 ports, we can use: cpu_is_mx6() for it. Signed-off-by: Jason Liu <r64343@freescale.com>
2012-01-09ENGR00170434: MX6 - Add support to read Silicon versionRanjani Vaidyanathan
Read the silicon version stored in ROM at address ox48. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-01-09ENGR00154931 [MX6]L2 cache init wrong after resumeAnson Huang
1.Need to add condition check after resum, or if we didn't config L2 cache, build will fail. 2.Need to call the mxc_init_l2x0 instead of l2x0_init. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-01-09ENGR00153601 [MX6]Adjust L2 cache parameterAnson Huang
Adjust L2 cache parameter to improve both performance and power consumption. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-01-09ENGR00152668 [MX6]Enable arch_resetAnson Huang
--OCRAM size is 256KB, confirmed by IC owner, the OCRAM_Aliasd 0.75MB is mapped to the same 256KB OCRAM.That means there is only 256KB physical OCRAM. --Enable arch_reset function on MX6Q, For SMP, we need to clear the SRC_GPRx after the secondary cores brought up, or the wdog reset will fail; Signed-off-by: Anson Huang <b20788@freescale.com>
2012-01-09ENGR00152845-3 MSL imx6: msl files changes.Jason Chen
imx6 MSL files change, include clock change for ipu. Signed-off-by: Jason Chen <jason.chen@freescale.com>
2012-01-09ENGR00139229-1 MX6: Bring up i.MX6 sabreauto with Single coreZeng Zhaoming
MSL code for bring up MX6 sabreauto board with Single core. Merged from testbuild:imx6_bringup branch. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com> Singed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Sammy He <r62914@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com> Merged-by: Zeng Zhaoming <b32542@freescale.com> Reviewed-by: Jason Liu <r64343@freescale.com> Reviewed-by: Frank Li <Frank.Li@freescale.com>