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path: root/arch/arm/mach-mx6/mx6_suspend.S
AgeCommit message (Expand)Author
2014-10-07MLK-9663 imx6x:Fix the DDR self-refresh entry procedure in suspend code.Ranjani Vaidyanathan
2014-10-06ENGR00334447 [imx6qdl] Fix random failures caused by ddr frequency change pro...Ranjani Vaidyanathan
2014-10-06ENGR00327364 [imx6x] Ensure that the bandgap self-bias circuit is disabled af...Ranjani Vaidyanathan
2014-06-13ENGR00318393 [iMX6x] Ensure certain CP15 registers are maintained across susp...Ranjani Vaidyanathan
2014-06-06ENGR00316180: [iMX6x] Support IRAM page table when DDR is in self-refresh.Ranjani Vaidyanathan
2014-06-03ENGR00267929: [MX6SL] Add DDR3 support for MX6SLGrace Si
2014-06-03ENGR00233366-1 Anatop PFUZE: LDO bypass can be configed by cmdlineRobin Gong
2014-06-03ENGR00229695 MX6x-Set RBC counters correctly in STOP mode.Ranjani Vaidyanathan
2014-06-03ENGR00227477 mx6qdl: system resume fail due to DDR not accessableAnson Huang
2014-06-03ENGR00225700: ARM: mx6sl: Fix suspend/resume lockupRobert Lee
2014-06-03ENGR00227425 mx6sl: Need to save all registers before calling C functionAnson Huang
2014-06-03ENGR00227249 MX6SL-Add support for low latency STANDBY mode.Ranjani Vaidyanathan
2014-06-03ENGR00222834 MX6x-A9 prefetcher should not access DDR before IO is restoredRanjani Vaidyanathan
2014-06-03ENGR00222257 MX6x-Prime TLB entries before DDR enters self-refresh.Ranjani Vaidyanathan
2014-06-03ENGR00221970 MX6SL:Fix suspend/resume issue on MX6SLEVKRanjani Vaidyanathan
2014-06-03ENGR00215188-2 LDO bypass: disable LDO bypass before suspend and back in resumeRobin Gong
2014-06-03ENGR00214765 [MX6]Fix resume fail when there is pending wakeup irqAnson Huang
2014-06-03ENGR00210547 [MX6]Enable I cache and branch prediction earlyAnson Huang
2014-06-03ENGR00209501 [MX6]Support different platforms DDR IO setting in DSMAnson Huang