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path: root/arch/arm/mach-mx6
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2012-03-08ENGR00176160 [MX6]Correct PLL1 freq change flowAnson Huang
Previous PLL1 freq change is done by switching CPU clock to 400M pfd or 24M OSC, then modifying PLL1 div directly, and switch back CPU clock immediately, it will result in CPU clock stop during PLL1 hardware lock period, thus, DRAM FIFO may blocked by the data CPU requested before PLL1 clock changed, and it will block other devices accessing DRAM, such as IPU, VPU etc. It will cause underrun or hang issue. We should wait PLL1 lock, then switch back. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-03-07ENGR00176147-2: usb: pass the wakeup event to pdataPeter Chen
The host driver needs to differentiate wakeup event. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-03-07ENGR00176068-1 mx6q: add smp_twd clock for localtimerXinyu Chen
Add a smp_twd system clock which is simple clock from parent of cpu_clk, and it's rate is half of the cpu_clk. This is used for reprograming the twd clock event after cpu freq is changed. Also disable local timer setup when wait mode enabled. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-03-06ENGR00176136- MX6: Added support for 1.2GHz ARM FrequencyRanjani Vaidyanathan
Added the new 1.2GHz working point. Currently 'arm_freq=1200" should be added to commandline for the core to run at 1.2GHz. Also ensure that the appropriate HW board mods have been done to set VDDARM_IN at 1.425V. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-03-06ENGR00176175 MX6Q: fix typo in cpu op voltage setting.Zhang Jiejing
Fix a typo when adding 600M WP, the voltage value is wrong, it will lead a warnning when change to this WP: COULD NOT SET GP VOLTAGE!!!! Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-03-06ENGR00170526-1 MX6Q_Sabreauto: remove audio platform data rst_gpio.Lionel Xu
Remove audio platform data rst_gpio which is not longer required now. Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
2012-03-02ENGR00175551:Update sabreauto board file for handling spi and paralle norFrancisco Munoz
*Files affected: board-mx6q_sabreauto.c *Added IOMUX settings for parallel nor *Utilized physmap driver in order to probe the chip *Implemented conditional compilation enabling either spi or parallel nor. Signed-off-by: Francisco Munoz <b37752@freescale.com>
2012-03-02ENGR00175947 camera: sensor mclk change name to clko_clkYuxi Sun
Change mclk sensor name to clko_clk Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-03-02ENGR00175219-6 MX6Q_SABRESD: add clko_clk supportGary Zhang
audio codec wm8958 and camera use the same clock clko_clk with around 22MHz. Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-03-02ENGR00175219-5 MX6: remove cko1_clk in clock.cGary Zhang
there are clko_clk and cko1_clk in clock.c which operate the same CKO1 clock source. remove cko1_clk codes to avoid operation confusion. Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-02-28ENGR00175219-2 MX6Q_SABRESD: add wm8958 supportGary Zhang
add wm8958 codec support Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-02-23ENGR00174905 [MX6] gc355 can't work after specific suspend/resume caseLarry Li
GC355 can't work at below steps: - suspend resume - load gpu driver and run gc355 application In order to make GPU work properly, GPU clock needs to be on while power on GPU. Not only direct GPU clk ccgr needs to be on, but also relative clock in GPU clock tree has to be enabled. Signed-off-by: Larry Li <b20787@freescale.com>
2012-02-22ENGR00174886-1 - EPDC fb: Don't register EPDC unless "epdc" kernel option setDanny Nold
- Add E Ink support as a default for MX6 platforms - Conditionalize registration of EPDC-related modules based on "epdc" kernel command line option Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-02-22ENGR00174569: MX6 - Disable WAIT mode by defaultRanjani Vaidyanathan
None of the workarounds implemented in SW provide a stable solution for the WAIT mode issue. For this release, WAIT mode is disabled by default. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-02-22ENGR00174734-1 usb: need to discharge both dp and dmPeter Chen
Change to discharge both dp and dm Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-02-22ENGR00174615:Enable AH-1613 GPS moduleB38613
set GPIO config and disable UART3 DMA. Signed-off-by: Zhou Jianzheng <B38613@freescale.com>
2012-02-21ENGR00171079-10: mx6q-arm2 cs42888 board sample rate settingsAdrian Alonso
* Board mx6q-arm2 cs42888 supportted sample rate settings, pass them trough mxc_audio_codec_platform_data Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-21ENGR00171079-8 imx6q sabreauto cs42888 audio supportAdrian Alonso
* Add imx6q sabreauto cs42888 audio support * Set clock parent relations anaclk_2 -> pll4_audio_clk -> esai_root_clk * Match corresponding sysclk frequency to keep lrclk_ratio relation on imx-cs4288 esai configuration Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-21ENGR00171079-7 mx6q clock anaclk input source clockAdrian Alonso
* Add mx6q anaclk_1/2 clock input source clock support * anaclk can be bypassed to pll4_audio. * _clk_audio_video_set_parent allows to bypass anaclk input clock source, for sabreauto platform anaclk_2 is the clock source for cs42888 and this clock needs to be bypassed to esai to supply the same master clk signal. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-21ENGR00171079-5 imx6q-sabreauto set supportted sample ratesAdrian Alonso
* cs42888 set imx6q-sabreauto supportted play/record sample rates master clk signal is a fixed source clock @24576000Mhz, thus limit the play/record sample rates lrclk. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-21ENGR00171079-2 mx6 add anaclk_2 io buffers enable macrosAdrian Alonso
* Add ANACLK_2 input/output buffers enable macros. In orther to bypass anaclk_2 to pll4_audio need to set anaclk_2 input buffer enable bits. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-21ENGR00171079-1 mx6q-ard: esai remove record early paramAdrian Alonso
* Remove record early param, pad GPIO9 shared with ESAI_FSR and WDOG1 doesn't conflict as WDOG1 connection is open, NANDF_CS3 is shared with ESAI_TX1 and connection is also open with nand socket, no other pad conflicts. * Add esai interrupt gpio pin. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-21ENGR00175049 - Remove section mismatch warning for Max17135Danny Nold
- Entire max17135_regulator_init function declared as __init, which should be safe, since it is only executed at driver init time. Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-02-21ENGR00174897 i.mx6: clock: fix axi clock mux settingJason Liu
Fix the error in the axi clock mux setting, - reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET); + reg |= ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET); Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-21ENGR00174896 i.mx6: i.mx6l: clock: gpu/vpu clock adjustmentJason Liu
GPU clock on i.mx6dl: gpu2d_core_clk source from gpu3d_shader_clk, gpu3d_axi_clk source from mmdc0 directly, 400Mhz by default, gpu2d_axi_clk source from mmdc0 directly, 400Mhz by default, AXI_CLK on i.mx6dl: set axi_clk parent to pll3_pfd_540M and divid by 2, which will get 270Mhz by default, VPU clock on i.mx6dl: VPU will parent from axi_clk, then by default, it will be 270Mhz, which will be suitable for VPU 1080p support. pll3_pfd_540M on i.mx6dl will be dedicated to VPU/IPU/AXI_CLK use, other users should not change this assignment Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-20ENGR00174829-1 MX6Q_SABRESD: fix warnning messageZhang Jiejing
Fix below warnning message: arch/arm/mach-mx6/board-mx6q_sabresd.c:753: warning: 'mx6q_sabresd_flexcan_gpios' defined but not used Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-02-20ENGR00174824 [MX6]Add workaround for i.MX6DL suspend/resumeAnson Huang
To keep i.MX6DL resume work stably, need to open LDO on based on the current codes.Will continue to optimize power in suspend state in future codes. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-17ENGR00174630 [MX6]Disable GPT serial clockAnson Huang
Currently we use 24MHz clock as GPT's clock source, serial clock can be disabled, it sourced from high freq clock, gating it can save ~8mA @VDDSOC. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-16ENGR00174652 i.mx6: explicitly set the LPM mode to run mode during early bootupJason Liu
the reset value of LPM[1:0] in CCM_CLPCR register is b'01, which means system will enter into wait mode on next assertion of dsm_request signal. In order to avoid the system unexpectly enter the wait mode during bootup we need set the LPM mode to run mode explicity during early boot up phase, Anytime, we want system to enter the wait mode, the sw procedure is: mxc_cpu_lp_set(LP_MODE) -> set CCM_CLPCR register -> system enter wait mode This patch also fix linux kernel reboot stress test on i.mx6dl, without this patch linux kernel reboot test will fail random with error like this: [ 12.091220] Bad mode in interrupt handler detected [ 12.096056] Bad mode in interrupt handler detected [ 12.100851] Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-16ENGR00174394 MX6Q_arm2/MX6Q_sabreauto: change ipu_id/disp_id for LDB config.Wayne Zou
MX6Q_arm2/MX6Q_sabreauto: change ipu_id/disp_id for LDB configuration. For, LDB_SEP0 mode, the disp_id should be 0, and sec_disp_id should be 1 on MX6Q, since the LDB channel 0 should be connected to IPU DI0. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-02-16ENGR00174649 i.mx6dl: clock: set ipu1 clock to 270M, change ldb_di_clk parentWayne Zou
Set ipu1 clock to 270M, source from pll3_pfd_540M for best performance. And set ldb_di_clk parent to pll2_pfd_352M. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-02-16ENGR00174540: i.mx6: anatop_regulator: LDO voltage print not correctlyJason Liu
The LDO voltage constraint not printed correctly: print_constraints: vddpu: 725 <--> 1300 mV at 700 mV fast normal print_constraints: vddsoc: 725 <--> 1300 mV at 700 mV fast normal print_constraints: vdd2p5: 2000 <--> 2775 mV at 2000 mV fast normal print_constraints: vdd1p1: 800 <--> 1400 mV at 700 mV fast normal print_constraints: vdd3p0: 2800 <--> 3150 mV at 2625 mV fast normal There due to one typo: << in the code, thus will make the LDO constraint print not correctly, the patch will make the print correctly as the followings: print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-16ENGR00174532 [mx6Q]Change 2D clock to 480MLarry Li
Change GPU2D core clock to 480M and use PLL3 as parent Signed-off-by: Larry Li <b20787@freescale.com>
2012-02-15ENGR00174106-1 - EPDC fb: Support EPDC on MX 6DL/SDanny Nold
- Added EPDC and EPD PMIC (Maxim 17135) to MX6Q ARM2 board file - Added EPDC-related IOMUX and GPIO settings - Added EPDC clock configuration settings to clock file - Updated config files with EPDC and Maxim 17135 config entries Signed-off-by: Danny Nold <dannynold@freescale.com>
2012-02-15ENGR00172274-02 - [MX6]: rework IEEE-1588 in MX6Q Sabre-lite/sd board.Fugang Duan
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT. - IEEE-1588 ts_clk and i2c3 are mutually exclusive, because all of them use GPIO_16, so it only for one function work at a moment. - Test result: TO1.1 IEEE 1588 is convergent in Sabrelite board. Signed-off-by: Fugang Duan <B38611@freescale.com>
2012-02-15ENGR00174425: i.mx6: i.mx6dl: clock: set gpu2d_axi clock parent to mmdc0Jason Liu
on i.mx6dl, gpu2d_axi clock is directly connected to mmdc0 Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-15ENGR00174423-2: i.mx6: clock: code clean up in pfd_set_rateJason Liu
code clean up by removing the dead code in function pfd_set_rate Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-15ENGR00174423-1 i.mx6: cpu_op: code clean upJason Liu
code clean up by removing the un-expected mfd/mfn/mfi setting Signed-off-by: Jason Liu <r64343@freescale.com>
2012-02-14ENGR00174381 imx6q-sabreauto: spdif remove tx clock settingsAdrian Alonso
* Sabreauto platform only supports spdif in (Rx) Remove unused Tx clock settings Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2012-02-14ENGR00174299-2: MSL part: add ePxP V2 driverRobby Cai
MSL part for ePxP v2 driver Signed-off-by: Robby Cai <R63905@freescale.com>
2012-02-14ENGR00174121-2 MX6Q_SABRESD: add battery chip support.Zhang Jiejing
add battery support. support Charger plug in and detect, DC and USB. support charging status query. not support voltage reading due to HW design, to support this will have more efforts so add this later if needed. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-02-13ENGR00174309:mx6/dl: gpu:enable 2d and 3dWu Guoxing
mx6dl do not have 3d shader core, and 2d core clk is using 3d shader clock. Signed-off-by: Wu Guoxing <b39297@freescale.com>
2012-02-13ENGR00174316 MX6Q ARM2: Fix ov5640_mipi IOMUX incorrect configureEven Xu
One type error on ov5640_mipi IOMUX configure, fix it. Signed-off-by: Even Xu <b21019@freescale.com>
2012-02-13ENGR00174315 MX6Q max7310 set the default value of PCIE PWR ctrl2 to lowRichard Zhu
System would be halt, when the default value CTRL_2 is set to high, change the default value to low. root cause: System 3V3 would be dragged down to 1.5V for about 4ms. Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-13ENGR00174302 [MX6]Clean build warningAnson Huang
arch/arm/mach-mx6/clock.c:1749: warning: unused variable 'reg'; Signed-off-by: Anson Huang <b20788@freescale.com>
2012-02-10ENGR00170126 mx6q sabresd: add GPIO key deviceXinyu Chen
Add volume up/down and power GPIO key button Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-02-10ENGR00174229-1 mx6q sabresd: add sensors devicesXinyu Chen
Add 3-axis accelerometer (mma8451) device. Add Digital Magnetometer (mag3110) device. Add Ambient Light sensor (isl29023) device. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2012-02-10ENGR00173857 MX6Q: add 600M work pointZhang Jiejing
Add a 600M work point for better suit for cpufreq driver. For current MX6Q clock tree, the most near 600M working point is 624M, so we use 624M as 600M working point. We found we have 200/400/800/1G working point is not very good for cpufreq adjustment, since we don't have a uniform working point distribution, since the interactive governor is using cpu usage to adjust frequency, eg, 60% CPU, going to 600M working point, if above a threshold (%85 default) will going to max frequency directly. From the [sheet] , you can see in game case, it will have much chance in 400M working point, between 400M and 800M working point, there is a gap, so the 400M will be most used frequency. we add 600 WP to fill this gap, and make game case have better experience. [sheet] http://wiki.freescale.net/download/attachments/ 40052424/Compare.xlsx?version=1&modificationDate=1326086907000 Wiki About this: http://wiki.freescale.net/display/MADAndroid /i.MX6Q+Performance+and+Power+Optimization Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
2012-02-10ENGR00174033-1 MX6 PCIE: add pcie RC driverRichard Zhu
Add PCIE RC driver on MX6 platforms. Based on iwl4965agn pcie wifi device, verified the following features. * Link up is stable * map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed Signed-off-by: Richard Zhu <r65037@freescale.com>
2012-02-10ENGR00174128-2 Revert "Remove the discharge for VBUS and DP-2"Peter Chen
This reverts commit 4f025d73de4a55077691096eacf60f90c3b9e7af. Signed-off-by: Peter Chen <peter.chen@freescale.com>
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