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path: root/arch/arm/mach-tegra/Makefile
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2011-11-30tegra: p852: Enable p852 support in kernelManoj Chourasia
This patch enable support of p852 in kernel bug 872849 Reviewed-on: http://git-master/r/46387 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Manoj Chourasia <mchourasia@nvidia.com> (cherry picked from commit 10f747a674951ef977f4cc66767ade1b6caa6565) Change-Id: Ideb3c9d09225a6266bfcfa4455613ada72acd789 Reviewed-on: http://git-master/r/56898 Tested-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R90b51f3cbda86d52e6b460e21121d85412d4d626
2011-11-30tegra: harmony: KBC support for chicony keyboardRamalingam C
This change includes the keymapping details for chicony keyboard and registers the platform_device called "tegra-kbc" with all board resources corresponding to KBC. Change-Id: I4222914f09520b60882a447fc149fd1c352be037 Signed-off-by: Ramalingam C <ramalingamc@nvidia.com> Reviewed-on: http://git-master/r/57233 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: Rb233d2e2065fa590a6e776eb81ba205efc45442b
2011-11-30Ventana: KBC: Removing the KBC usage on ventanaRamalingam C
On Ventana, Keys are handled through the GPIO driver. So CONFIG_KEYBOARD_TEGRA should not be defined On LDK, kernel defconfig of Harmony is shared with Ventana(to move towards SingleBinary for multiple tegra boards). Since on Harmony we have to support the matrix keyboard through KBC, we have enabled the KBC driver by defining CONFIG_KEYBOARD_TEGRA which reflects in Ventana also. This situation leads to an spurious interrupt from KBC as soon as system enters into the LP0 state. To avoid the early exit from LP0, we are removing the KBC device registration on board_ventana.c Bug 869778 Reviewed-on: http://git-master/r/52049 (cherry picked from commit 68f4c9bbf9b533fd44215d26b3d0acf11865a819) Change-Id: I8fe42bbe5d5bd41dd1737bca9af9e35611443f40 Reviewed-on: http://git-master/r/54422 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Ra71aa54f1b8d7f8d30ca45c36e2b8d130969b62e
2011-11-30arm: tegra: whistler: Add KBC support for whistlerPuneet Saxena
Add support for matrix Keypad in whistler Change-Id: I5132f8e3ec7b4353f0cf525b7fceecc721ac014b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: http://git-master/r/51259 Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R34806f304acb565419c4e3301fadd324f7210c81
2011-11-30ARM: tegra: enterprise: Enable KBCDan Willemsen
Change-Id: I3d68c141cb515a024432ff5c2b40481494d178f7 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-on: http://git-master/r/50909 Rebase-Id: Rc7e5a79c13087c8f58dc50fa6304206f39dd287e
2011-11-30ARM: tegra: Only enable fuse programming on silicon platformsScott Williams
Fuse programming is possible only on silicon platforms. Do not enable it for simulation or FPGA platforms. Change-Id: If1bec072eeaae1ee95720a37e37fcb7c8e8ee464 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/49724 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R71d2073c18353d32a2b5373819f2e27e1e8bb680
2011-11-30ARM: tegra: Clean up makefile conditionalsScott Williams
Change-Id: I7789a192aad504957770b7632d4f5f9cd01b8c5d Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/50358 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R94f5bab7f502627ce9bda7e07ea5afe4518bb1e2
2011-11-30arm : tegra: sysfs interface for xmm power module on/offSeshendra Gadagottu
Now xmm power module made static part of the kernel. xmm modem can be on/off using the sysfs interface. BUG 828389 Original-Change-Id: Icfbe83beeac43f88418eee29f71ccd58d9b840c2 Reviewed-on: http://git-master/r/47773 Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R3adb92f2a3f3523c1006969a42499263dd0fa6fb
2011-11-30ARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster controlScott Williams
Change-Id: I07c389092132e52e2bdd3deab22c10f8e1e6035c Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48798 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1e0c9acc87c81f9d0dc394c09d6a7b8b94c48d3f
2011-11-30ARM: tegra: power: Separate throttling codeAlex Frid
Moved tegra CPU throttling algorithm implementation into a separate file. For now, the same algorithm is used for both Tegra2 and Tegra3 architecture. Original-Change-Id: I478c32b5adee4c946472129b89615580c10b41e1 Reviewed-on: http://git-master/r/46748 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R2340f78e1d22942022e171044d6b20f260e2d312
2011-11-30arm: tegra: comms: Intel XMM6260 flashless boot.Michael Hsu
Add baseband power drivers to manage gpio for turning on modem, and re-enumerating modem after modem's boot rom has transferred control to downloaded modem software. BUG 828389 Original-Change-Id: Ide96a28b8f0183d8328751d3b3dec92b8068a3c8 Reviewed-on: http://git-master/r/39435 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb3d170a5460bff29550d664c3f783134d2a3a41f
2011-11-30arm: tegra: cardhu: Added I2C arbitration lost recovery mechanismAlok Chauhan
Added the code for arbitration lost recovery mechanism for i2c driver and Initialize gpio number for i2c clock and data as part of platform data. bug 854305 Original-Change-Id: Icdc243a5025c766d65816542a6d5aabd61e6eee1 Reviewed-on: http://git-master/r/43200 Reviewed-by: Bandi Krishna Chaitanya <bandik@nvidia.com> Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com> Reviewed-by: Alok Chauhan <alokc@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R11e00587725418e6e6ef5d0fa2f718424cc0635e
2011-11-30arm: tegra: Implement HSIC power management for baseband devices.Seshendra Gadagottu
Add power management for HSIC baseband power module. Currently the power module implemented state handling for L0->L3 and L3->L0 state transitions. BUG 828389 Original-Change-Id: I46b7da66bfa85fac57261ec68668435855739981 Reviewed-on: http://git-master/r/33065 Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R2d04847c5dc12db17b49ec62a4e12f061bca29fe
2011-11-30ARM: tegra: power: Control IO pad configuration dynamicallyAlex Frid
Tegra IO pads are automatically re-configured when IO power level is changed. Current code keeps auto-detection cells in default, active state all the time. This change will allow turning off cells when IO power is stable, and activate them only during power transitions. In addition IO pads will be set into "no-io-power" state after the respective regulator is disabled, and re-configured back for regular operations before regulator is re-enabled. Dynamic IO pad control introduced in this commit is still disabled by default on all tegra platforms. Bug 853132 Original-Change-Id: Ifc7bbe2ac34929c14f8f8e9feaa4290b78fe6cf6 Reviewed-on: http://git-master/r/42263 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R8b7c7863c1580816a2f3b28bdb3c228a97a18736
2011-11-30ARM: tegra: power: Added global EDP Capping tablePeter Boonstoppel
- Added table with EDP Capping values for different SKUs/regulator currents in new file edp.c - New entry point tegra_init_cpu_edp_limits() - Added DebugFS entry under debug/edp to list the currently selected EDP table - Populated EDP table in edp.c with data from Bug 844268 - edp.c keeps main EDP table; cpu-tegra.c and board-cardhu-power.c both read from there Bug 840255 Original-Change-Id: I55c2ee16278be8cd3005218bedebe76846d137d8 Reviewed-on: http://git-master/r/40938 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R9a5f2bcfc1e6e0b5aee37cd700d75f9ef5cea30b
2011-11-30ARM: tegra: add support for hardware statistic counterPrashant Gaikwad
Tegra2 chip has a hardware statistic counter for CPU/AVP/VDE/SYS modules. This commit adds the support for AVP statistics gathering and controlling avp clock during video playback. Bug 831892 Reviewed-on: http://git-master/r/35647 (cherry picked from commit 145885b03cd9fc625f2ff3460c59ebbb3d93c98e) Original-Change-Id: I441acbaf2cb8dd776529bafd4e13f50e31849afa Reviewed-on: http://git-master/r/39657 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7271973f142f14fc8a11bdbc33ae6f76f6fd38b0
2011-11-30arm: tegra: renaming tegra3_mc_stats to tegra3_mcDonghan Ryu
tegra3_mc_stats is memory controller profiler for tegra3. it is originated from tegra2_mc and having different file name convention is pretty confusing. This change change the name of the files for tegra3. Original-Change-Id: Icd8c1f834e4af0daa8d8de6412b953274750883f Reviewed-on: http://git-master/r/38252 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R191a5bd02e389ad2594a012bcfd82712ac5f3c76
2011-11-30arm: tegra: fuse: support to burn fuses on the fieldVarun Wadekar
- follow the new sequence shared by the hardware team - merge Tegra2 and Tegra3.0 odm fuse burning into a single file Bug 796825 Original-Change-Id: Ia06d589eba95254a410016dce244375f27e22be0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/38404 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R740d7bd47eaa6231954ae98686272a755a4bce14
2011-11-30ARM: tegra: la: Add support for latency allowance.vdumpa
Original-Change-Id: Ia6593fd6720e38f9bb0635fabe236675764cee91 Reviewed-on: http://git-master/r/36570 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R338465e38b998b4c6a8bfa4efc89003eac90d8b9
2011-11-30arm: tegra: tsensor: driver instantiationBitan Biswas
Tegra internal tsensor driver supported for fuse revision 0.8 and above. Bug 661228 Original-Change-Id: I820f6b5f20c20bb2d1ba04266148f5969ab84444 Reviewed-on: http://git-master/r/36054 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4725524b5e3f83b4cd3dd7d0020ef2d6e09a87d0
2011-11-30arm: tegra: Use new platform typesYudong Tan
This change is needed to support three different platforms, silicon, fpga and simulation. Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce Reviewed-on: http://git-master/r/36351 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19
2011-11-30ARM: tegra: clock: Add Tegra3 EMC activity monitor supportAlex Frid
Added EMC clock control using Tegra3 activity monitoring device. The target EMC frequency floor is set based on average activity and short term boost. Average EMC activity is obtained directly from monitoring h/w featuring 1st order IIR activity filter. The boost frequency is calculated by s/w - exponentially increasing/ decreasing when sampled EMC activity has crossed upper/lower boost watermarks. The implementation is interrupt driven - periodic sampling is hidden by h/w. The tune-able debugfs parameters are: /sys/kernel/debug/tegra_actmon/emc/boost_step - boost rate increase step (% of max EMC frequency) /sys/kernel/debug/tegra_actmon/emc/boost_rate_inc - boost rate increase factor (%) /sys/kernel/debug/tegra_actmon/emc/boost_rate_dec - boost rate decrease factor (%) /sys/kernel/debug/tegra_actmon/emc/boost_threshold_up - upper activity watermark for boost increase (% of current EMC frequency) /sys/kernel/debug/tegra_actmon/emc/boost_threshold_dn - lower activity watermark for boost decrease (% of current EMC frequency) Original-Change-Id: I385c6e0a75da42dada792db6b4018b68fea8f23b Reviewed-on: http://git-master/r/36790 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R0ac50b162b8e86237986885e115996f755b1e00a
2011-11-30ARM: tegra: Limit ahb.c to Tegra2Dan Willemsen
Change-Id: Ia9a67a2ce2c437b115efe7d1f5d69da481208d35 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R866af3fffbba37a2efac84ecfcbd8979d3c3b745
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: Add Tegra 3 CPU hotplug supportScott Williams
Change-Id: Ie43f4efdf884a916c6bc9737157091c35dc44501 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1f023651504a7d336f7e98921f6372bee0aa1341
2011-11-30ARM: tegra: Move common timer code into timer.cScott Williams
The system timer initialization code for Tegra2 and Tegra3 is essentially the same except for the actual physical timer used and the range of possible reference clock frequencies. This change removes the needless duplication of code and restructures the system timer code into common and SOC-specific parts. Change-Id: Icb6e4c0e2b218c67667be9450e10326e1e42945b Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbd3fc10b2a6935dd1ca9272695fd0133e0ca4f15
2011-11-30ARM: tegra: Add Tegra GIC extensionsScott Williams
Implement extensions to the standard ARM GIC API for Tegra3 power management. Change-Id: If8b2ce2b366e48bb5ca82d3de2acab1fd0a81bb9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7527cd57edf054c871f5d04d7e9185643f79843
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra: Always compile sleep.SScott Williams
Decouple LP3 (WFI) mode and CPU hotplug shutdown from CONFIG_PM_SLEEP. Change-Id: Ie959fa5e044ab4a7f84772d3b743ce2680465acc Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R8f01e646e7bf65350db44557de87c4c2a33d8059
2011-11-30ARM: tegra: Enable headsmp.S without CONFIG_SMPScott Williams
In the current implementation for Tegra2, tegra_resume is required for low power states, and it's coupled with CONFIG_SMP in headsmp.S. In the implementation for Tegra3, we'll want to use tegra_resume even without SMP. Change-Id: I868eaf1de4f2898d2b1ad220638c0588901384c3 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R25c78e24b79d8bdd244c9cf5df85742047f71291
2011-11-30ARM: tegra: Split sleep.S for Tegra2Scott Williams
Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e
2011-11-30ARM: tegra: Build pm.c even without PM_SLEEPScott Williams
Change-Id: I13799aa03f86c7d83faf8ffa49954fef15aa0bdc Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra6e14b10f89a40a1f09169d864dbaa9e62c7280a
2011-11-30ARM: tegra: Make LP2 require CONFIG_PM_SLEEPScott Williams
Change-Id: Iaaf96375eaf7408f5bedc4196d33a04fb94129ef Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R98567e0d894acbdac770b191f7e46f16592d5d0b
2011-11-30ARM: tegra: Move Tegra2 idlestats to cpuidle-t2.cScott Williams
Change-Id: I2c0814cfefd820626beeba468edd9c462c6be8bb Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbbb70f49af4e731c953315ae81a96480ac25ff4d
2011-11-30ARM: tegra: Makefile reformatScott Williams
Change-Id: If6003c2f30487b808303c9bfd1fba94bbee8026f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R280a168f09d7b7ee521ec167fd6411ae6d2f8ddd
2011-11-30HACK: disable enterprise KBCDan Willemsen
Rebase-Id: Rd59a699ec939d2098ab3ad60010bc4112e4eda0e
2011-11-30get tegra3 compilingDan Willemsen
Rebase-Id: R03f1fc69f4859a0dc66fbd145eb0df31650de3ac
2011-11-30HACK: disable headsmp-t3.SDan Willemsen
Rebase-Id: R6001fd0dada0a331fdfe083d4396ba472d470b3d
2011-11-30ARM: tegra: Disable tegra3_save.SDan Willemsen
Rebase-Id: R97ea582dcab2af31a9ea19b5531d5829baacf0c6
2011-11-30remove placeholdersDan Willemsen
Rebase-Id: R1dbf37d34132ebe69f0c250a9457a7c5096e3d31
2011-11-30Merge branch 'boardfiles/whistler' into after-boardfilesDan Willemsen
2011-11-30Merge branch 'boardfiles/ventana' into after-boardfilesDan Willemsen
2011-11-30Merge branch 'boardfiles/enterprise' into after-boardfilesDan Willemsen
2011-11-30Merge branch 'boardfiles/harmony' into after-boardfilesDan Willemsen
2011-11-30Merge branch 'boardfiles/cardhu' into after-boardfilesDan Willemsen
2011-11-30ARM: tegra: Whistler K39 updatesDan Willemsen
Rebase-Id: Ra87c1d4245a0ce31e3fe7529f06ca18fbe703706
2011-11-30[ARM] tegra: Enable EMC scalingPrashant Gaikwad
Frequency tables added for memory. Enabled memory tables used for EMC scaling. Bug 786376 Original-Change-Id: I8f9713dac7950db4a42dac4f32d8908434c18be1 Reviewed-on: http://git-master/r/22578 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R74db053a9fd2a79023117e9f26c2dc2543c814ea
2011-11-30[ARM] tegra: add baseband modem supportSteve Lin
Add baseband modem init/reset functions for whistler. Bug 776276 Original-Change-Id: I014e8e24831079428c008d166ffa4b156cc66572 Reviewed-on: http://git-master/r/15602 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R5d0b886b465e018d73b1fcc03d6b3c355a844f7b
2011-11-30[ARM] tegra: whistler: Camera sensor ov5650Sachin Nikam
Regestering and intializing tegra_camera and ov5650. Configuring pinmix for VI. Original-Change-Id: I7672f5a1e4ef87cc115183395b144a82bb52f9e8 Reviewed-on: http://git-master/r/14773 Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd2e3a9a82f64070c2e10fbf26a56b78ff705ccdf
2011-11-30[ARM] tegra: whistler: registering kbc driverSachin Nikam
Adding functional keymap for whistler. Original-Change-Id: I43208d8f901933b368c1c034f56cf0680613312a Reviewed-on: http://git-master/r/13777 Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R08ed261467ceee3bb8a841a154123406c21ff29d
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-25 16:28:44 +0000