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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
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Fix PCIe clock and reset not conforming to specification by moving PCIe
reset handling including the PLX PEX 8605 errata 5 workaround from the
board platform data into the right places timing wise in the PCIe driver
itself.
Also add a kernel command line argument to allow using the Apalis GPIO7
as a regular GPIO rather than for above mentioned PLX PEX 8605
workaround:
pex_perst=0
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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The Ixora carrier board has a few MXM3 pins repurposed as follows:
Functionality MXM3 Pin
LED4_RED 146
LED4_GREEN 162
LED5_RED 156
LED5_GREEN 152
PCIE1_WDISABLE_N 144
SW3 160
UART2_3_RS232_FOFF_N 164
This patch allows uncommenting an IXORA define in the board header file
in order to make use of those repurposed pins.
Please note that those pins are usually used for the 8-bit MMC/SD slot
aka Apalis MMC1 and the SDHCI controller/driver unfortunately changes
the output driver behaviour in a way preventing any regular GPIO use.
This patch therefore explicitly does not register the SDHCI driver on
this controller instance in the Ixora case to avoid this.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Both the Apalis EvalBoard as well as Ixora allow their LTC2954
pushbutton on/off controller to optionally initiate orderly shutdown
via GPIO interrupt on GPIO5 upon short power button press (short here
meaning really short unless C137 resp. C35 is assembled). For this to
work the following wiring is required:
Apalis EvalBoard V1.1a X61-4 to X2-6
Ixora V1.0a X5-4 to X27-17
For systemd/logind to actually use this as a power-switch a custom udev
rule /etc/udev/rules.d/70-power-switch-apalis_t30.rules as follows is
required:
# Specific rule for apalis_t30:
#
# Apalis T30's power button is not part of the kernel acpi subsystem.
# Let's manually add the power-switch tag to control its behaviour with
# systemd/logind
ACTION=="remove", GOTO="power_apalis_t30_end"
SUBSYSTEM=="input", KERNEL=="event1", TAG+="power-switch"
LABEL="power_apalis_t30_end"
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Both the Apalis EvalBoard as well as Ixora allow their LTC2954
pushbutton on/off controller to optionally be forced off by using a
GPIO. This patch implements this upon poweroff/shutdown using Apalis
GPIO6 which happens to be internally pulled-up upon power-on reset
(otherwise we would immediately get powered off again). For this to
work the following wiring is required:
Apalis EvalBoard V1.1a X2-A5 to X61-5
Ixora V1.0a X27-18 to X5-5
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Remove TEGRA_FB_VGA defines and use VGA as default. Since initial
mode is now configureable through kernel cmd line parameter, we
don't need those compile time helpers.
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Up to now only the LVDS transceiver controlling GPIOs were exported.
This patch adds the generic Apalis GPIOs to the list of via sysfs to
userspace exported ones as well.
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If the local critical temperature is reached the power is
unconditionally switched off. At 70°C ambient the default of 85°C
can be reached. So increase the limit in the hwmon chip to 95°C.
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By default configure for LG LP156WF1 15.6 inch full HD dual channel
LVDS panel.
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Re-arrange defines in header file.
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Get rid of spurious AC_PRESENT_GPIO/INT defines.
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Add defines for the generic Apalis GPIOs 1 to 8 and the special use
thereof on the Apalis Evaluation Board:
FAN_EN on GPIO8: enable FAN supply on X35
PEX_PERST_N on GPIO7: reset PCIe switch for X43, X44 and X45
TOUCH_WIPER on GPIO6: optional touch wiper GPIO
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Tested on early prototype Apalis T30 V1.0a module.
Known issues:
- ADC not integrated yet.
- HDA not integrated yet.
- CEC not integrated yet.
- IrDA not integrated yet.
- Keys not integrated yet therefore no way to wake from suspend.
- 8-bit MMC1 slot card detection interrupt not working despite
detection GPIO successfully being tested with GPIOConfig.
Note: even 8-bit cards work fine if already plugged-in during boot.
- PCIe limited to internal Gigabit Ethernet chip for now due to our
proprietary way of resetting other ports which requires further
integration into NVIDIA's driver.
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