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Add support for PM315
Bug 1171138
Change-Id: I2e5461c656c41d4172aca60525655cb780eaa17e
Original-author: Mike Thompson <mikthompson@nvidia.com>
Signed-off-by: Mike Thompson <mikthompson@nvidia.com>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/143506
(cherry picked from commit 4e66142b6990ca586e085aa88ae0bd6b819da0c4)
Reviewed-on: http://git-master/r/166814
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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The EmcTclkStable is set to 0x00000004 and McEmemArbOutStandingReq
is set to 0xc0000030
Bug 1030392
Bug 1039060
Reviewed-on: http://git-master/r/122302
(cherry picked from commit a3a1d1797e310d61204256af8be995f9396c22e7)
Change-Id: Ic65334a6573582ae99d05a8f6f8290096755827e
Signed-off-by: Wen Yi <wyi@nvidia.com>
Reviewed-on: http://git-master/r/127458
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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The memory frequencies 266.5mhz and 437mhz have incorrect
EMEM_ARB_CFG set in emc table of Samsung part. That resulted
in emc scaling completely disabled and emc runs at 533mhz all
time. The settings have been corrected to 0x00000008
and 0x0000000D.
Bug 1030392
Bug 1039060
Reviewed-on: http://git-master/r/122163
(cherry picked from commit f691268c138b9ed31b3867b049e64c121ecb188e)
Change-Id: I13f89c19af5391743aeba348f4a3ca4a73307bdf
Signed-off-by: Wen Yi <wyi@nvidia.com>
Reviewed-on: http://git-master/r/127429
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Sanjay Singh Rawat <srawat@nvidia.com>
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Extend tick length to 60ns
Also add missed Cardhu SKU 1000 table
Bug 1001229
Bug 970610
Change-Id: I224158a88d02595d5b911f59b6920b9ed99481ab
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/113315
(cherry picked from commit 492193079047d9c5a4fff617a14191438f356e42)
Reviewed-on: http://git-master/r/116221
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 1005576
Signed-off-by: Peter Zu <pzu@nvidia.com>
Reviewed-on: http://git-master/r/112036
(cherry picked from commit 1f1e6d22e771336fb9e0b91bbabf12fa89f0c57c)
Change-Id: If65aba6aaa0a400c960a2d2b1315a07fa44dcefe
Reviewed-on: http://git-master/r/115054
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Add 12.75mhz emc frequency for Samsung K4P8G304EB-FGC2
LPDDR2 1GB memory chip.
Bug 1011100
Change-Id: Ibbbb3f002c36c31cd2806051803ddd3ba9daa63b
Signed-off-by: Wen Yi <wyi@nvidia.com>
(cherry picked from commit a37cb14dc441005ddd977b6a83f41df817179d79)
Reviewed-on: http://git-master/r/113383
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Bug 970890
Change-Id: If0ebb1ad76dfe3267bc0acd3feae70a701c1dfdb
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/103237
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Bug 918704
Change-Id: I83bdce136df07d744c69a75a38bb5ae1d541055e
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/91935
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Bug 896060
Reviewed-on: http://git-master/r/84679
(cherry picked from commit e1eb8a0802ff7c2aaf8e278e0f8cfd1fa06758be)
Change-Id: Ic233905eaa22775daa894c0132187b1192824b01
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Conflicts:
arch/arm/mach-tegra/board-cardhu-memory.c
Change-Id: Ic233905eaa22775daa894c0132187b1192824b01
Reviewed-on: http://git-master/r/88867
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Since Tegra3 allows bit swapping when routing SoC-to-DDR data bus,
added the respective decoding mechanism for reading LPDDR2 mode
registers. Populated mapping table for PM269 board.
Bug 939626
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5f5329596167681b528c87fd088d60030eee6fdc)
Change-Id: I6670110a828df4264b8f7a8c8e6e67611a830033
Reviewed-on: http://git-master/r/89350
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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The number of outstanding memory transactions is limited by a setting
in MC. This leads to dc underflows which cause flickers on lcd panel.
Increase the limits to optimal values which don't show dc underflows.
Currently, the cap on outstanding requests for a frequency is calculated
by linearly scaling up values for frequencies keeping minimum value at
0x08. An exception has to be made to resolve dc underflows and
lcd flickers.
For cardhu, the lower ram frequencies are 25.5MHz, 51MHz and 102MHz.
So increase minimum value to 0x10 and set 0x18 for 102MHz as an optimal
value with which there are no dc underflows.
Memory tables of Hynix-1GB, Hynix-2GB and Samsung-2GB memory types are
updated with this change.
Bug 932113
Bug 946316
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on:http://git-master/r/87230
(cherry picked from commit 39642475dc4401e666d4ade338c5b9e0741ce017)
Change-Id: I19e8c04f4acc93f07121ee7da98588d2441147e8
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/87236
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Edward Ahn <eahn@nvidia.com>
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Added 900MHz, 850MHz, 450MHz and 425MHz for T33 parts.
Change-Id: I6577b7c1e2242b5c9da2378b074eb40da11fb562
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/83308
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Bug 852560
Change-Id: I335bed2bb4a35e8c740ee54829c1c2e3203d97aa
Reviewed-on: http://git-master/r/73838
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76457
Reviewed-by: Automatic_Commit_Validation_User
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Add DVFS tables for cardhu A05 memory
Also, update memory SKU to handle new format
Bug 911821
Change-Id: I458669d9d42df542e3305fa0c31363d94390599d
Signed-off-by: Ahmed Farra <afarra@nvidia.com>
Reviewed-on: http://git-master/r/68585
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Bug 871975
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/59997
(cherry picked from commit 228f9b4eb5533a0a1cc5ca43c8aa3770dbaeb4c3)
Reviewed-on: http://git-master/r/64272
(cherry picked from commit 0cf62a0879cf0df49d09abea9f6da6a700f85f3a)
Change-Id: I9083a812b31719e069e24dd9283270df4d0680b7
Reviewed-on: http://git-master/r/68067
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Added dynamic self-refresh field and updated arbitration settings.
Bug 896654
(cherry picked from commit 9af03dda41ee154ce7d3818f70456e833a22c893)
(cherry picked from commit f05bd447cb8bc53ff2f98dca3db55c05f53ce29d)
Change-Id: I9f60a60bd0768a86735ccf4e8d0db772d9caeeb9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/67023
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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- Added 800MHz, 400MHz (for T33 parts), and replaced 408MHz with 375MHz
entry (for T30 parts).
- Added dynamic self-refresh field, and updated arbitration settings.
Bug 867684
Bug 896654
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5e31d110a4da1fa37790ace0297f6141f872c183)
(cherry picked from commit 94eafeb884a63fe7fcc57a4636904853d8b3ab72)
Change-Id: I04db7784803b203ecdc1e828bb70cdd7eae017bc
Reviewed-on: http://git-master/r/67022
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Added dynamic self-refresh field and updated arbitration settings.
Bug 896654
Reviewed-on: http://git-master/r/61728
(cherry picked from commit 6b8d5582fb205c6cb277ce0ecbe328fcf724d664)
Reviewed-on: http://git-master/r/62297
(cherry picked from commit 9c60a6c5f5bc07253454a057e9b3e0046c574b45)
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/62535
(cherry picked from commit af73bb50258071d264645f655cae17ea70b9bd10)
Change-Id: Idf7382b1df0d4c06dbe763d5ab20918b48d50515
Reviewed-on: http://git-master/r/64983
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R99ee0ac14f211cd87174642acb3506028bcb3a74
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- Added dynamic self-refresh field, and updated arbitration settings
Bug 896654
Reviewed-on: http://git-master/r/61725
(cherry picked from commit 2d5a9c1fbe5cdf4f4233ec3eca230d625d0439de)
Reviewed-on: http://git-master/r/62296
(cherry picked from commit 31f9198bcc05c35cc4aa797e4f224aed62fdfc64)
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/62534
(cherry picked from commit a0977e407c3937aae077304ca1ec1f937419c07b)
Change-Id: I16b46da22d1a7c40bafcc1e55fd22f2979f3798b
Reviewed-on: http://git-master/r/64982
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R15d84c206780f90108f44ebe7cc4812d75d3e57f
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Adding support for E1257 platform.
bug 864294
Reviewed-on: http://git-master/r/50662
(cherry picked from commit 8217615021a6ffeb992327f6b010ea9deebc34e7)
Change-Id: I3429da1bca38e1ddc5b3c2156a0db6b23aeb5555
Reviewed-on: http://git-master/r/57806
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R7fadbdc30bdca30e41e0b7fdb88628dbc8c32e82
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Adding support for PM311 based system.
bug 870139
Reviewed-on: http://git-master/r/50012
(cherry picked from commit d319d9980b6b225735ac97160fdee18fbabba2f0)
Change-Id: Iaa28921761e035e8fa29956b776f9379ae326b42
Reviewed-on: http://git-master/r/57251
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R50fc9a079bd46a050084afed2b0f460e2916ebc9
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Adding support for PM305.
bug 846246
Original-Change-Id: Ib036c67c12984668e0b7153f76a1a1d44c5be14f
Reviewed-on: http://git-master/r/49820
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R9e9eb93ddcea487159854533eead3fe8eb74e42b
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Bug 861419
Original-Change-Id: Icff68a821f5088af62962ccadaabbd01e4b5af7b
Reviewed-on: http://git-master/r/45966
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4cb37cd9644ed36c7ee8e2b0462ef9bf8536674d
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Bug 852560
Original-Change-Id: I96eefc1851675ea3321abf7197383de13c18cdb1
Reviewed-on: http://git-master/r/44394
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Re4e99d3595c6437e0ef761b89f6a74f422f5f31a
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Changed table format to revision 3.1; added 750MHz entry.
Bug 836260
Bug 829932
Original-Change-Id: I1e9d8db21012fc0dcb62367c3f00dc32a4d969bb
Reviewed-on: http://git-master/r/42525
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rf27767784fa3c62f2e9e2049cf9d9cdbd67ead40
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Bug 852560
Original-Change-Id: I68c9877c43507bf154ab38462866f2e45375f71c
Reviewed-on: http://git-master/r/42017
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R82c2041d99f8696b37c3c0aa7b932c7dddb757d7
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Bug 822468
Original-Change-Id: I5655e76308001fb26553885f2e84da7122148dcc
Reviewed-on: http://git-master/r/41289
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R48dfe21d4cec9c74978a9800c078bd408f8d41fe
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Bug 836260
Original-Change-Id: I4fb8e8eb3610676f89cb29ee0d10487c01200f95
Reviewed-on: http://git-master/r/39244
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R1edb58986433fd6cc95ddecf0ef38e8c41f81fed
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Add EMC table for LP-DDR2 Samsung memory
Original-Change-Id: I931bbb0d2283ad94d130803cef7c08b6da5923a1
Reviewed-on: http://git-master/r/37757
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Racdadadfeb4438faab94ca2bea4d9665da381d18
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Updated Tegra3 EMC DFS table to match new PLLP base frequency
(408MHz) and enable power saving features.
Bug 836260
Change-Id: Ie85cda67804ea29a0df475464020b1e76176ea3b
Reviewed-on: http://git-master/r/36049
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Rebase-Id: Rdbb0343817c2aee5506f5ca78ead4807d4c76182
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Updated Tegra3 EMC clock change procedure with periodic qrst support,
and EMC DFS tables.
Bug 836260
Change-Id: Ia3d7f58bf61ee6e695ab62f934388d4c1b4d2079
Reviewed-on: http://git-master/r/35321
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Rebase-Id: Rf17a6b73285ddf723c8629b56e6d8e56efb28798
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Original-Change-Id: I29db9923c269c1c957342ca32ba0763daca05931
Reviewed-on: http://git-master/r/32685
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R3eee4a16493f149b6090fd96d64c17216e64a2e7
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Made sure default DDR3 EMC DFS table is not applied to cardhu
processor board with LPDDR2.
Original-Change-Id: I78bb2a4f80a5db00e04cb82c530924219e6baa78
Reviewed-on: http://git-master/r/30311
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Rebase-Id: Rc526c375fd15719b434694d7db8b91099a220c2a
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Original-Change-Id: I838b589dbf6e551d1b47e4482df78f828c8b9f20
Reviewed-on: http://git-master/r/27136
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I7c1ae5bf2bc1be29ec5f558f512b784661e78418
Rebase-Id: Re31d21677edd806b52e2fdda48962c90589862fb
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Original-Change-Id: I1ba94ad99da247958001bb15452a6453e8b6fd31
Reviewed-on: http://git-master/r/26741
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I5c8106e773ef74a8bc34bb96b50c2764a38ebd18
Rebase-Id: R3c346d4b4ff806b25210a90d19ad1353185c8719
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Original-Change-Id: I8f80bbad3600e502d6ff71c51e6acaa41a5d4e1e
Reviewed-on: http://git-master/r/22659
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I223167759a875c912fb0af399c81757cd603e20d
Rebase-Id: R95c638f44042065e60c3a9c06b430b21cbb556ee
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Add preliminary EMC DFS table for cardhu at nominal 667MHz.
EMC scaling is still disabled by default.
Original-Change-Id: I3722d6c851332df8781aa42dd20be09be09c2859
Reviewed-on: http://git-master/r/21941
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I306c8733f16678bb6734dace7f06cab0ad6ea363
Rebase-Id: Rd27feaf77da59d15abbe981f4d4cc2ed9f413757
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