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path: root/arch/arm/mach-tegra/board-cardhu-power.c
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2011-08-22arm: tegra: cardhu: secureos LP2 suspend modeJ. Aaron Gamble
FOR 12r7 ONLY Temporary change from LP0 to LP2 for secureos customers Change-Id: I076fd59e92ab64e9d9c958bc991e2fc3e13de108 Reviewed-on: http://git-master/r/48583 Reviewed-by: Ryan Wong <ryanw@nvidia.com> Tested-by: Ryan Wong <ryanw@nvidia.com>
2011-08-17arm: tegra: cardhu: Set LDO2 to 1200mV for E1208-A03Laxman Dewangan
The ldo2 power rail should be set to 1200mV on E1208-A03 based pmu. bug 863728 Change-Id: I7730443bc052348a082d52a73e4f521ec34202f7 Reviewed-on: http://git-master/r/47491 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Vivek Aseeja <vaseeja@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-08-05ARM: tegra: cardhu: switch off PMU at high temperaturevenu byravarasu
Add board support needed for PMU switch off when tsensor detects temperature > TH3 threshold set. bug 850047 Change-Id: I7a283cedc735264dd8ea52801f7f1a103e9293cb Reviewed-on: http://git-master/r/41531 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-29arm: tegra: cardhu: enable wake on wirelessNarayan Reddy
Wake 3 is used by WiFi for waking up from the suspend mode.GPIO associated with wake3 is TEGRA_WAKE_GPIO_PB6.This is applicable for the power configuration LP0. bug 856515 Change-Id: I014997b9f688475f0f3441136661c03ec3c1b4ba Reviewed-on: http://git-master/r/43457 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-22ARM: tegra: cardhu: Add IO power detection consumersAlex Frid
Bug 853132 Change-Id: I59cc6b2025926695ebee12d808fb49f556ffaa6d Reviewed-on: http://git-master/r/42264 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-20ARM: tegra: power: Added global EDP Capping tablePeter Boonstoppel
- Added table with EDP Capping values for different SKUs/regulator currents in new file edp.c - New entry point tegra_init_cpu_edp_limits() - Added DebugFS entry under debug/edp to list the currently selected EDP table - Populated EDP table in edp.c with data from Bug 844268 - edp.c keeps main EDP table; cpu-tegra.c and board-cardhu-power.c both read from there Bug 840255 Change-Id: I55c2ee16278be8cd3005218bedebe76846d137d8 Reviewed-on: http://git-master/r/40938 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-18arm: tegra: cardhu: Set AVDD_PLL and AVDD_PLL_SATA to proper voltageLaxman Dewangan
Setting the rail voltage of the AVDD_PLLs to 1.2V and rail voltage of PLL_SATA to 1.05V. Change-Id: Ibf5bb1d11b7b15cabb68f90da7e24dd999915c55 Reviewed-on: http://git-master/r/41179 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-18arm: tegra: Console suspend for all boardsLaxman Dewangan
Added the board level suspend/resume and call the console suspend from board level suspend/resume. bug 820536 Change-Id: I246265241246dc0682870571c927bd23023e5aca Reviewed-on: http://git-master/r/41448 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-07-15arm: tegra: cardhu: Add board level suspend/resumeLaxman Dewangan
Adding board level suspend/resume for cardhu. Disabling the clock for console uart port if console_suspend is enabled. bug 820536 Change-Id: Iecb78708ff7784dd131ffa83692b2419dba44e88 Reviewed-on: http://git-master/r/41147 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-15mfd: tps6591x: Reorganise GPIO definitionLaxman Dewangan
Adding the TPS6591x gpio definition in tps6591x core header files. bug 849976 Change-Id: I1f7a7cc38e220c091ccf44db5af6e43c34daa1cd Reviewed-on: http://git-master/r/41040 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-13arm: tegra: cardhu: board SKU and fab cleanupLaxman Dewangan
Remove the hardcoding of the numerical value for different sku bit and fab definition and using macro for better readability. Change-Id: Idf70c7a063b5416e170b3b7e61e896250c9ad70c Reviewed-on: http://git-master/r/37644 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-13arm: cardhu: Remove always_on from backlight rails.Laxman Dewangan
Removing the always on in constraints of the power rail of backlights. bug 850674 Change-Id: I15b835012db75fdf74dc1d7a742da0573c5af06d Reviewed-on: http://git-master/r/40798 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-12arm: tegra: cardhu: Add support for the E1256Laxman Dewangan
Adding support for the E1256. The configuration is same as the E1186 board. bug 849990 Change-Id: Idd89e282627b2f0924fc313a5ba28f9e9a6032be Reviewed-on: http://git-master/r/40367 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-11arm: tegra: pm269: remove power on/off delaysRay Poudrier
The problem with slow PMU was fixed with a hardware change to reduce capacitance on the power rail, so delays are no longer needed Change-Id: Ib66378ca6bf18c112e90d44d3213dd5f6c870c92 Reviewed-on: http://git-master/r/37127 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-11arm: tegra: cardhu: rename vpp_fuse_pg to vdd_fuseVarun Wadekar
Bug 796825 Change-Id: I91be0bca739a2daf32807306a611671f387a8988 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/36096 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-11arm: tegra: cardhu: Add full constraints of regulatorLaxman Dewangan
Adding complete constraints of the regulators. bug 843566 Change-Id: Ifd07d15d257ff8c89c4a3cc31c9e72d886e6b431 Reviewed-on: http://git-master/r/39633 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-07-08arm: tegra: cardhu: Add KBC wake eventRay Poudrier
Enables LP0 to stay asleep on PM269 Bug 848662 Change-Id: Ie29c9f89ee1d3a3b8f3272cdbc2714b05d5b0bbc Reviewed-on: http://git-master/r/39450 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-07ARM: tegra: cardhu: Update vid_oc pin for pm269Ray Poudrier
Correct pingroup is DAP3_DOUT Bug 825778 Change-Id: I252398c4f1d653c73c5fd26a7b5c12410a962ade Reviewed-on: http://git-master/r/39822 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-07arm: tegra: pm269: Low power mode to unused vddio-gmi pinsLaxman Dewangan
Putting the unused vddio_gmi pins into the low power mode. bug 833087 Change-Id: I7595d011a61d5993fee167e89ed7eb204d5cb6b6 Reviewed-on: http://git-master/r/37877 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-06-29arm: tegra: cardhu: enable lp0 by defaultLuke Huang
Set the default sleep mode to be lp0. Note: This change only affects Tegra3-A02. For A01, the default sleep mode is still lp1. Bug 802410 Change-Id: Idef6ab46c13a9aca24982c6b39ebe481bad46b9a Reviewed-on: http://git-master/r/38408 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-06-24arm: tegra: cardhu: enable PMU features for lp0Luke Huang
Enable PMU only features for LP0. System-wise LP0 is not enable by default yet. 1. Allow pmu SLEEP state 2. Keep 32KHz clk out from PMU enabled on LP0 3. Set core_power_req to be high enable 4. Turn off VDD1 (power for Vcore) on LP0 Change-Id: Id6babdfc36de1a597f8df5d2943ef048699013d4 Reviewed-on: http://git-master/r/32853 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-06-22arm: tegra: pm269: Correct the input supply for HDMIAlok Chauhan
change the input supply to master 5v to enable VDDIO_HDMI signal for HDMI. Bug 825778 Bug 823160 Change-Id: I2d6360ab3769ff876bdb7d0e0b34d9298aa780d0 Reviewed-on: http://git-master/r/35904 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-06-20arm: tegra: cardhu: support for PMUA03/A04Laxman Dewangan
The core_pwr_req signal need to be make high for the PMU A03 and A04. bug 829846 Change-Id: Ie568a29e76823e86743893ea59953b0429cc027a Reviewed-on: http://git-master/r/36544 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-06-14arm: tegra: cardhu: Changes for E1291-A04 power railsLaxman Dewangan
The E1291-A04 power rails are different then the A02/A03 version of E1291. Supporting the A04 power rails properly. Change-Id: I4c7dc0afa5b6bb1a7350418ef07f4ee7192cff30 Reviewed-on: http://git-master/r/35722 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-05-27arm: tegra: cardhu: Configuring DEV_SLP and gpio2 for A04Laxman Dewangan
Configuring the tps6591x into DEV_SLP mode and gpio2 of tps6591x into sleep mode for E1291-A04 board. This is required in order to have the gpio2 follow the 'CORE_PWR_REQ' pin in E1291-A04. GPIO2 of tps6591x is connected to the EN of the DC-DC converter which supply core voltage. bug 821295 Change-Id: I01a8fa6c056872cff84dd0f2ae7601cee298ebcf Reviewed-on: http://git-master/r/32614 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-23Revert "arm: tegra: cardhu: core related fixes for lp0"Niket Sirsi
This reverts commit 0885c8037152e4b11d669c845ddf09ba49e5c8b6. Change-Id: I254ca2966cdf28d548368340efb64617ce274a74 Reviewed-on: http://git-master/r/32698 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-05-23ARM: Tegra: Cardhu: Enable CPU EDP limits tableDiwakar Tundlam
Change-Id: I57f033f44cfdf19d61bc5bab41cec23e51b40c11 Reviewed-on: http://git-master/r/32089 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-05-23arm: tegra: cardhu: core related fixes for lp0Luke Huang
1. Set core_power_req to be high enable 2. Turn off VDD1 (power for Vcore) on LP0 Change-Id: I81aedb4332c9e7ccd97def546a9a0611253f744a Reviewed-on: http://git-master/r/32277 Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-18arm: tegra: cardhu: set CPU EDP limitstegra-T30.ER5Varun Wadekar
Change-Id: I6282bbb63c34b8cc0d503cdd6eafe575fb78ef5f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/31342 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18arm: tegra: cardhu: Adding board entry for tps6236xLaxman Dewangan
Adding platform data entry for the tps6236x device and registering this device if board info has sku with bit0 as 1. bug 821295 Change-Id: I18618ef75eca66a1f699c003c787dcb1f06e7659 Reviewed-on: http://git-master/r/31388 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-05-13ARM: tegra: power: PM269: Add GPIO_REGPradeep Goudagunta
Adding GPIO_REG for power rails of PM269 board. Bug 823160 Change-Id: Idbb889420e033780900b1b1b700637017640414e Reviewed-on: http://git-master/r/30366 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-13ARM: tegra : power: Set power rails SATA & PCIE off by defaultKaran Jhavar
Setting SATA & PCIE power rails (ldo1 & ldo2) off by default since they are not enabled on Cardhu. Bug 793780, 790141 Change-Id: If905f156b99314271874536d61fe384715f2412a Reviewed-on: http://git-master/r/31292 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-11arm: tegra: cardhu: Adding cam-AF power railsLaxman Dewangan
Adding the camera autofocus power rail infomration. Removing non-existant peripheral entry from i2c4 bus. Adding deselect mux option after each i2c transfer through mux i2c. bug 802264 Change-Id: Id87178666e4d8c4c5db3f8be708fc5fc85b3e2e4 Reviewed-on: http://git-master/r/29998 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-05ARM: tegra: power: Set cpu_pwr_off timer to 200us for PMICDiwakar Tundlam
Change-Id: Ic30a091dd634b1857cdbfc5a0c47d34bc496b04f Reviewed-on: http://git-master/r/29884 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-05arm: tegra: cardhu: Setting CORE_PWR_REQ to output highLaxman Dewangan
Setting CORE_PWR_REQ to high. This is require to enable tracking regulator to supply more than 2A current for cardhu A03 board. bug 805454 Change-Id: I4ff9d4d2bf106dc0d3d708fe9e1a7f7158dce27e Reviewed-on: http://git-master/r/29623 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-03arm: tegra: Enabling RTC data based on defconfigvenu byravarasu
Internal and PMU RTC data are enabled only when respective macros are defined in the Cardhu defconfig file. bug 793949 Change-Id: Iefc074877b263f3620c5ad08026435b3232ae3aa Reviewed-on: http://git-master/r/29637 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-04-29ARM:tegra:cardhu: Adding Vibrator power rail infovenu byravarasu
Adding power rail details for Vibrator on E118x board. bug 810072 Change-Id: Ibf50c986b843fb36515f36493b5a07323ac940ab Reviewed-on: http://git-master/r/29631 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-04-26ARM: tegra: power: Set minimum LP2 target residencyAlex Frid
Added board level tuning parameter to specify minimum LP2 residency time (previous policy allows down to zero residency targets limited only by LP2 exit latency). Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22 Reviewed-on: http://git-master/r/28162 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6
2011-04-26arm: tegra: cardhu: setting default date on RTCvenu byravarasu
With this change, Jan 1, 2000 is being set as default date on PMU RTC Original-Change-Id: Ib1930970c6b58d5fa820a77eedd7b61dab731ee7 Reviewed-on: http://git-master/r/28029 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Change-Id: Iddfaea12cf2329238c48939d7686c98694703e64
2011-04-26ARM: tegra: cardhu: Adjust cpu-suspend timers on some boards.Diwakar Tundlam
Fix for bug 816031: We need to have appropriate delays to make DVS work on all boards we support. Original-Change-Id: I60db0832f2591dcbf2a3904474440996f032bc28 Reviewed-on: http://git-master/r/27966 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Change-Id: I2421b73909edb469f1caaaf74a7213902d02c080
2011-04-26ARM: tegra: Fix file permissionsScott Williams
Remove executable permission bit from source files. Generated with: find \( -name "*.c" -or -name "*.h" -or -name "*akefile" -or \ -name "*\.mk" \) -type f -perm /+x | xargs chmod -x Original-Change-Id: If459d180238b8dd4cc40f92f74a56d01c81a2768 Reviewed-on: http://git-master/r/27916 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: If96e5e61c9f3b60ceaf9dcf88c0c7d7d1d8f343a
2011-04-26rtc: tps6591x: wake up from suspend on alarmvenu byravarasu
Changes required for waking up system, when RTC alarm is triggered. bug 793949 Original-Change-Id: Idcc536a819e977fe35bafeebdffddf57d5388f21 Reviewed-on: http://git-master/r/27359 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I68bb747cb965d14af9918ad6086ac2e9888f7136
2011-04-26arm: tegra: cardhu: Changing power control lines for cardhu-A03Laxman Dewangan
The E1291-A03 uses the following pins for the different power rail controls: EN_VDD_BL1 --->PEX_L0_CLKREQ_N EN_VDD_BL2 --->PEX_L0_PRSNT_N EN_USB1_VBUS_EN_OC --->PEX_L1_CLKREQ_N ENUSB3_VBUS_EN_OC --->PEX_L1_PRSNT_N bug 807504 bug 797021 Original-Change-Id: Id3703bc799373e714501b60588298a2f1e052852 Reviewed-on: http://git-master/r/24269 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Change-Id: I9d7aafa7794e6d9e05f01db6bde7ed4c91e9050e
2011-04-26arm: tegra: cardhu: Supporting power offLaxman Dewangan
Supporting the power off of device through the adb shell "reboot -p" or from GUI with power off. bug 787957 Original-Change-Id: I8bc65707a8c19b0d7cc8c506dfd5327f23c01511 Reviewed-on: http://git-master/r/24112 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Change-Id: I9e30bd5d143bad276f7bc2ee57e7887dcfd48233
2011-04-26arm: tegra: cardhu: Cleanup to support multiboards configurationLaxman Dewangan
Cleanup in the configuration related to board is done so that it will be easier to add another board configuration on same build configuration. Original-Change-Id: Id030d70e4893b886ee73aaf944450526e7722e7e Reviewed-on: http://git-master/r/22392 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Mohit Singh <mpsingh@nvidia.com> Tested-by: Mohit Singh <mpsingh@nvidia.com> Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Rakesh Bodla <rbodla@nvidia.com> Tested-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Change-Id: Id737a2668ce13470be80086e3d3764c4f9ac6096
2011-04-26tegra:cardhu: enable suspend power state(LP1)Narendra Damahe
Enabling suspend power state(LP1) by default for Cardhu Original-Change-Id: I6d39702307a7629ad7cf8b569e7fc9c520f6653e Reviewed-on: http://git-master/r/22092 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Change-Id: Ic22bda19616a61c5e4781b9e32b0dd4dfdd3a110
2011-04-26regulator: tps6591x: Masking all interruptsLaxman Dewangan
Masking all interrupts from tps6591x by default and configuring the PMU interrupt to active low. Original-Change-Id: I2a40bb5f50d7f749debe1a8a478680acf69767a4 Reviewed-on: http://git-master/r/22066 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Change-Id: I676785668026e4ef02a076f70bdb9d292263b346
2011-04-26rtc: adding TPS6591x RTC entries to cardhu boardvenu byravarasu
Cardhu board file is updated with TPS6591x RTC entry. Original-Change-Id: I5207f5d943c6e94a871961a959a019fbcad391b2 Reviewed-on: http://git-master/r/21497 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: Ic11ed608b13366657da4ef32fe3fbb782d6fadb2
2011-04-26arm: tegra: cardhu: Defining base irq number for tps6591xLaxman Dewangan
Defining the irq base address for the tps6591x through cardhu header file. Original-Change-Id: Iebd6ef863a994e4552f358b31b104c6e40a6446e Reviewed-on: http://git-master/r/20755 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I6c758f61913644ea804f1cd8a4e6c84ebdb45f64
2011-04-26ARM: tegra: cardhu: Enable VDD_CPU external controlAlex Frid
Original-Change-Id: Ie2b9c7bb441c72c105ca3205bdd42a8dcd76d9ef Reviewed-on: http://git-master/r/20230 Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Change-Id: I9896c0568ee5103a2608cf4abcab36f592a83f21
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-24 11:35:22 +0000