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Adjust max rates for CPU and several SKU-dependent core clocks
(system bus, AVP, VDE, 3D) to match chip SKU ID. Added max_rate
node to debugfs.
Change-Id: Ifd72d45a303b3d8b5ae5f327693bb97c8510031d
Reviewed-on: http://git-master/r/16077
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Conflicts:
drivers/net/wireless/bcm4329/Makefile
Change-Id: I31ce81e09c6f18d6966a5cffebc533453bce02d8
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Implemented debugfs clock write mechanism (disabled by default).
Expanded and fixed debugfs clock nodes to properly read clock
parent and rate.
Change-Id: I9f20994d0829634e09f4bccd6fce6c7c8b5bf844
Reviewed-on: http://git-master/r/15315
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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When picking clock divider values, the clock framework picks
the closest frequency that is lower than the requested
frequency. If the value from a clock divider rounds down,
and then the new rounded down frequency is requested, it
will get rounded down again, resulting in a frequency two
steps lower than the original requested frequency.
Fix the problem by rounding up when calculating the frequency
coming out of a clock divider, so if that frequency is
requested again, the same divider value will be picked.
Change-Id: Ieaf74448f67d91aeb7ba08226e48c092d8afaa2b
Signed-off-by: Colin Cross <ccross@android.com>
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The SDMMC controllers have extra bits in the clock source
register that adjust the delay between the clock and data
to compenstate for delays on the PCB. The values need to
be set from the clock code so the clock can be locked
during the read-modify-write on the clock source register.
Change-Id: Id25b7cc01fa4ec48478b60aefdf5e59bb040fbf2
Signed-off-by: Colin Cross <ccross@android.com>
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Call the clock's round_rate op, if it exists, before setting
dvfs rate. Ensures dvfs is set to the rate the clock will
be at after the later call to set_rate.
Change-Id: I4c8e85991238492adc3c37aed57c7269f3b41a2c
Signed-off-by: Colin Cross <ccross@android.com>
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The previous version of dvfs handled requirements between two
different voltage rails by using two sets of dvfs tables, one
for each rail. That method fails for vdd_aon, which must be
within 170 mV of vdd_core.
Instead, have each dvfs clock only set the voltage rail that
it directly depends on, and add a relationship system to the
voltage rails. When the voltage changes on one rail, it calls
update on all the rails that depend on it. The dependent rails
compare the new voltage of the original rail to their own
voltage, and update their own voltage as necessary.
Change-Id: I17b30a61c7c0c01e44702ab486238789abd47330
Signed-off-by: Colin Cross <ccross@android.com>
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This reverts commit f58886c359db3c5056fea2d1a41d297f19e9f585.
Change-Id: Ie88d8f79db9bf958fc3b9f261d74d031785161d0
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Change-Id: I9e3a3cc8c6c4424d7f7ded22d886d51f715ec5d5
Signed-off-by: Colin Cross <ccross@android.com>
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Get rid of dvfs_lock, replacing it with the cansleep flag on clocks.
Clocks with the cansleep flag set will lock a mutex before calling
into dvfs.
Also does the regulator api calls during late init, after the
regulators have been probed.
Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: I5b8bd249bd4f3ae495f2076f1e6d2bfb38737f29
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Give each clock its own lock, and remove all lock traversals from
parent to child clocks to prevent AB-BA deadlocks.
Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: I0afb7d1bca956439b1a4f17bbc6748aaec706b49
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Change-Id: I732f9428096d057e08092120c6f8c2890230a242
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New and improved dvfs:
Registered dynamically during init
Exports dvfs functions to control clocks that are not visible to
the clock subsystem
Supports multiple regulators per clock
Fix dvfs on disabled clocks
Adds /d/clock/dvfs to show current voltage requirements
Change-Id: I93794a7761dccc702566e8850bb79f344ff787a2
Signed-off-by: Colin Cross <ccross@android.com>
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Change-Id: Iaa5377dd1d8bf32e90deb668053c10588642fa03
Signed-off-by: Colin Cross <ccross@android.com>
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Change-Id: I136713c2a2ff9fec9fc629ae8f91709e49016618
Signed-off-by: Colin Cross <ccross@android.com>
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Change-Id: I6651ab59b738787ec94f358d5789d950c3d1a563
Signed-off-by: Colin Cross <ccross@android.com>
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Change-Id: Ic707eb111856eb9bdb165776d011c35d04502a9a
Signed-off-by: Colin Cross <ccross@android.com>
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- Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
PLLU is slightly different from the rest of the PLLs. The
lock enable bit is at bit 22 instead of 18 in the MISC
register, and the post divider field is a single bit with
reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: Colin Cross <ccross@android.com>
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v2: fixes from Russell King:
- include linux/io.h instead of asm/io.h
- fix whitespace in Kconfig
- Use spin_lock_init to initialize lock
- Return -ENOSYS instead of BUG for unimplemented clock ops
- Use proper return values in tegra2 clock ops
additional changes:
- Rename some clocks to match dev_ids
- add rate propagation
- add debugfs entries
- add support for clock listed in clk_lookup under multiple dev_ids
v3:
- Replace per-clock locking with global clock lock
- Autodetect clock state on init
- Let clock dividers pick next lower possible frequency
- Add support for clock init tables
- Minor bug fixes
- Fix checkpatch issues
Signed-off-by: Colin Cross <ccross@android.com>
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