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path: root/arch/arm/mach-tegra/clock.c
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2011-07-11ARM: tegra: clock: Use bus lock to protect shared bus updateAlex Frid
Protected shared bus update with bus lock - common for all shared bus users (update procedure was already covered by individual shared users locks, but it did not prevent concurrent access to shared rates list). Change-Id: Ia0e6886265aff1f624802e0415fe8cecb887b507 Reviewed-on: http://git-master/r/39918 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-08tegra: clocks: Fix in clock settingsmchourasia
clk_disable_locked should not be called when clk_enable_locked is failed. Change-Id: I2524ec0198f62de2487723676ca7657d15757eda Reviewed-on: http://git-master/r/38273 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-07ARM: tegra: sysfs write permission for user onlyManoj Gangwal
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. -clock: syncevents Bug 828100 Change-Id: I14affc209e954a58de055e291093e31dc1dbfe16 Reviewed-on: http://git-master/r/39364 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-07-07ARM: tegra: power: Refactored kernel powergate codeKaran Jhavar
This change provides a centralized location for powergating modules. It would take care of switching on/off clocks while un-powergating/ powergating modules respectively. Bug: 814267 Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710 Reviewed-on: http://git-master/r/31776 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-07-01ARM: tegra: clock: Add shared bus users rate printoutAlex Frid
Change-Id: Icb1a5028d575155427f1fd7fa5b3ee2a145934f4 Reviewed-on: http://git-master/r/38421 Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Gerrit_Virtual_Submit Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-06-24ARM: tegra: generate status events for all clocksPeter De Schrijver
Change-Id: I55f52ab038764079811c68b3bb3738a9de17d7bf Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/31530 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-06-24ARM: tegra: sysfs write permission for user onlySachin Nikam
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. - tegra_mc_stats: enable and quantum - susend: mode - clock: rate, parent, state File System Permission CTS expects this to pass. Bug 840409 Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/36867 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-06-24ARM: tegra: clock: Add clock rate change notificationAlex Frid
Change-Id: I97434334a4214180a365d9709a331405da135669 Reviewed-on: http://git-master/r/36202 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-06-20ARM: tegra: clock: Synchronize Tegra3 clocks scalingAlex Frid
On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are sourced from PLLC through integer dividers. Low resolution of these dividers does not allow to set scaling frequency levels matching intermediate voltage steps within core voltage range. Only changing the source frequency can achieve it. However, re-locking common PLL while engines are running requires synchronization of engines clock control, and complex operations including switching to backup sources during PLL stabilization time. This commit introduces a new virtual clock "cbus" to support clocks synchronization and PLLC re-locking procedures. The dvfs table for cbus clock is constructed from frequency steps close to maximum rates for each characterized core voltage level. Engine clocks exposed to the drivers are no longer physical module clocks, but shared cbus users. Setting the rate for such clock specifies the clock floor. The final cbus rate is determined as maximum floor setting for all enabled engines, and rounded up along the cbus dvfs ladder. Actual engine clock rate is set equal to the cbus clock rate. Hence, engines will be running close to maximum frequency for minimum voltage that satisfies all floor requests. Special case: Host1x. This clock will be always configured at 1/2 of cbus clock rate, and its shared user floor request is ignored by cbus target frequency calculations. Added cbus dvfs tables and updated VDE engine dvfs data. Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6 Reviewed-on: http://git-master/r/36199 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-06-13ARM: tegra: remove calls to smp_processor_id()Peter De Schrijver
smp_processor_id() only makes sense if the code can not move to a different CPU. The tegra clock code runs with IRQs enabled and preemption on, so it can move to a different CPU. Bug 827687 Change-Id: I8b3077c71966e535cc6ca2a2ec63eca0d7119777 Reviewed-on: http://git-master/r/35239 Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2011-05-17ARM: tegra: clock: Enable clock while setting rate/parentAlex Frid
When clock configuration (source mux, divider value) changes, the new control register setting does not take effect if clock is disabled. Later, when the clock is enabled it would run for several cycles on the old configuration before switching to the new one. This h/w behavior creates two problems: - since dvfs takes into account only new (enabled) rate, the module can be over-clocked during initial phase of the clock switch - since parent clock refcount is updated when the mux register was written, the parent clock maybe disabled by the time of actual switch and h/w would not be able to complete switch at all To avoid described problems clock is now always enabled while setting the new rate/parent (and disabled afterwards to keep refcount intact). Change-Id: I9bda56a2a98c9f3678715da1e1b8fe78874fb71e Reviewed-on: http://git-master/r/31640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-05-13ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltageAlex Frid
For different Tegra3 process corners/skus/revisions/boards set nominal voltages for CPU and core rails as well as adjust maximum clock rates as follows. - VDD_CORE rail nominal voltage: default value is indexed by speedo_id of the chip (speedo_id is determined by chip sku and revision). Minimum of the default and board specific electrical design voltage is rounded down against core dvfs voltage ladder. The result is set as nominal core voltage (edp voltage API is not implemented, yet). - VDD_CPU rail nominal voltage: default value is indexed by speedo_id of the chip. If too high, it is lowered to core nominal voltage so that core_on_cpu dependency is resolved at nominal core level. The result is compared with voltage required to reach CPU maximum rate as specified in the dvfs table for the particular process corner. Again, the minimal level is selected, and finally set as CPU nominal voltage. After nominal voltages are determined, maximum rate for each dvfs clock is adjusted accordingly, so that it does not exceed the rate specified in the respective DVFS table at nominal level. Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3 Reviewed-on: http://git-master/r/30928 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-05-11ARM: tegra: implement events for clock tracingPeter De Schrijver
Change-Id: If6ae23251aa615a678c8edb76d3c1e6463d86f2e Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Change-Id: I50ffa54eacaf5b3973fcd6cb94eee56e46ec81bf Reviewed-on: http://git-master/r/30384 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-04-29ARM: tegra: clock: Remove "sole parent" requirementAlex Frid
During dvfs initialization, change propagation of sleeping attribute from "current_parent-to-child" to "possible_parent-to-child". This would guarantee that any non-sleeping clock has only non-sleeping parents, and it is no longer required for sleeping clock to be a sole parent of all its children. Change-Id: I11110f6cb9c538c1e71bf00195c3f49dd09ea1f7 Reviewed-on: http://git-master/r/29706 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-04-29ARM: tegra: clock: Show cansleep attribute in clock treeAlex Frid
Change-Id: Iff900aa5b69329696bcd250c824e0a191f6f6299 Reviewed-on: http://git-master/r/29705 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-04-29ARM: tegra: clock: Clip Tegra3 CPU mode rate limitsAlex Frid
Made sure Tegra3 LP CPU mode maximum rate, and G CPU mode minimum rate are clipped to the entries in cpufreq scaling table. Change-Id: I4c82b65be3a8680edbb501041a7158d1a7fbbd07 Reviewed-on: http://git-master/r/29703 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-04-26ARM: tegra: power: Split Tegra3 CPU-G and CPU-LP dvfsAlex Frid
On Tegra3 CPU power is supplied by different rails in G-mode (VDD_CPU) and LP mode (VDD_CORE) - updated dvfs dependencies respectively. Original-Change-Id: Ifae8ae501b227a44e46ce1577bcd532e2e778322 Reviewed-on: http://git-master/r/25200 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I96e6cb7e3dcdf8514714d2900d8f947b6438c95f
2011-04-26ARM: tegra: clock: Add clock time on statisticAlex Frid
Original-Change-Id: I361e00ef84ce4ca9a9c6d7340de2d095fc67a208 Reviewed-on: http://git-master/r/25180 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: If382fc3b5d2ca678df8a9319a06bae967fc3c658
2011-04-26ARM: tegra: clock: Re-factor Tegra3 cpu clocksAlex Frid
Added second level virtualization (on top of virtual cpu rate control) to support different Tegra3 CPU power modes: low power (LP) mode and geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is defined as a child with two parents: virtual cpu_lp and virtual cpu_g clocks for the respective modes. Mode switch sequence was integrated into cpu_cmplx set parent implementation. (Before this commit mode switch was triggered outside the clock framework, which created cpu clock/mode synchronization problems). Each mode clock is derived from its own super clock mux (cclk_lp and cclk_g) to statically match Tegra3 h/w layout. (Before this commit the code had to dynamically synchronize CPU mode and active mux selection). This change also allowed to support PLLX output divider for low power mode as fixed 1:2 divider with bypass control embedded into cclk_lp parent section. Updated auto and sysfs CPU mode switch calls to use new clock framework, and removed clock manipulation from the low level mode switch implementation. Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b Reviewed-on: http://git-master/r/24734 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be
2011-04-26Update copyrightsScott Williams
Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a
2011-04-26arm tegra:Using pll_p clk source for sdmmc instances.Pavan Kunapuli
Using pll_p clk source for all sdmmc instances. Disabling clocks left over by the bootloader. Original-Change-Id: I245347b016618c39a4ceb2323f659b09261eaf7d Reviewed-on: http://git-master/r/17847 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I0790f6f67c944a9ca42be9d6b9398d8093b4beef
2011-04-26arm: tegra: sdhci: Do not disable sdmmc4 clockPavan Kunapuli
Do not switch off sdmmc4 clock. Also, removed ddr mode temporarily from linux mmc driver. Programming tap_delays and internal clock. Original-Change-Id: I830bf5e94ccd47e154c5ef9909e8bff1ff7754c0 Reviewed-on: http://git-master/r/17070 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Ic1cff8dd85229fe903206f1dc9a967d600ba88c1
2011-04-26ARM: tegra: clock: Prevent parent over-clockingAlex Frid
Pre-set clock rate when changing parent to avoid parent over-clocking during clock initialization from common/board specific tables. Drivers however, may still hit over-clocking error. Original-Change-Id: Ib101d85e90ab4c1194ac98680c930eebd8c56b76 Reviewed-on: http://git-master/r/16877 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I307e7eb507d885c381087812d262d56338aab861
2011-04-26ARM: tegra: clock: Add check for parent over-clockingAlex Frid
Fail clk_set_parent() interface if switching the clock parent will set the rate above maximum limit. Original-Change-Id: I47c0798dafe5f8f497dcacfcd23f6957244cdb0a Reviewed-on: http://git-master/r/16876 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Ie5fef027411096a465ae5aa84fe84a08a769a613
2011-04-26ARM: tegra: clock: Propagate errors in debugfsAlex Frid
Original-Change-Id: I7d7f4f49cc1e41707032467197d53967d3ecaf06 Reviewed-on: http://git-master/r/16659 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I9e04b2833ef12466664cf6f6c2666d440600db08
2011-04-26ARM: tegra: clock: Add clock state debugfs controlAlex Frid
Original-Change-Id: I2a16c36c8ee414a1f046eda2f3bdb9c1d71caf8b Reviewed-on: http://git-master/r/16657 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Icc4b526f44697bd788d83434f6e9a62de005b09c
2011-04-26ARM: tegra: clock: Re-factor extended clock operationsAlex Frid
Re-factored extended clock operations to enumerate configuration parameters. Original-Change-Id: I6c1e5f07803a8e6da0ebd6690892f50bb59efcd5 Reviewed-on: http://git-master/r/15144 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I25147998969b385905bad5eb3ceb2dbb89c0d93a
2011-04-26ARM: tegra: clock: Add extended clock configurationAlex Frid
Some peripheral clock source registers have extra bits with setting specific for the respective controller. Added mechanism to manipulate these bits from the clock code with proper locking. Implemented NAND, VI and DTV extended configurations. Original-Change-Id: Ic8a1887923f0b98f9b1fac06dcf4f90084b017c0 Reviewed-on: http://git-master/r/15059 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Change-Id: Ic3416be8683c90043376d6675269fc23e440f61d
2011-04-26Merge remote branch 'remotes/git-master/android-tegra-2.6.36' into 0104-mergeJin Qian
Conflicts: arch/arm/configs/tegra_defconfig arch/arm/configs/tegra_whistler_android_defconfig arch/arm/mach-tegra/Kconfig arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/board-ventana.c arch/arm/mach-tegra/board-ventana.h arch/arm/mach-tegra/board-whistler-power.c arch/arm/mach-tegra/board-whistler.c arch/arm/mach-tegra/clock.c arch/arm/mach-tegra/clock.h arch/arm/mach-tegra/common.c arch/arm/mach-tegra/cpu-tegra.c arch/arm/mach-tegra/dma.c arch/arm/mach-tegra/fuse.c arch/arm/mach-tegra/headsmp.S arch/arm/mach-tegra/include/mach/iomap.h arch/arm/mach-tegra/irq.c arch/arm/mach-tegra/spi_tegra_slave.c arch/arm/mach-tegra/tegra2_clocks.c arch/arm/mach-tegra/tegra2_dvfs.c arch/arm/tools/mach-types drivers/crypto/tegra-aes.c drivers/rtc/rtc-tegra.c drivers/video/tegra/host/dev.c drivers/video/tegra/host/nvhost_acm.c drivers/video/tegra/host/nvhost_channel.c drivers/video/tegra/host/nvhost_intr.c sound/soc/tegra/tegra_i2s.c sound/soc/tegra/tegra_pcm.c Original-Change-Id: If13d61cce097ee90892132e775c5ac805a1f91e0 Reviewed-on: http://git-master/r/14922 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Id331a2ef77522766e5b7f86131c6c981b37ba4c8
2011-04-26ARM: tegra: clock: Update LP-cluster related interfacesAlex Frid
Original-Change-Id: Ifde476a05bd01cdce8c3f4802b268a193a832a1b Reviewed-on: http://git-master/r/14584 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I41204d17c5d8092b1a24b3138efe12cfbd16d7e7
2011-04-26[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
2011-01-19ARM: tegra: clock: Adjust max rates to match SKU IDAlex Frid
Adjust max rates for CPU and several SKU-dependent core clocks (system bus, AVP, VDE, 3D) to match chip SKU ID. Added max_rate node to debugfs. Change-Id: Ifd72d45a303b3d8b5ae5f327693bb97c8510031d Reviewed-on: http://git-master/r/16077 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-01-18merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36Nitin Kumbhar
Conflicts: drivers/net/wireless/bcm4329/Makefile Change-Id: I31ce81e09c6f18d6966a5cffebc533453bce02d8
2011-01-17ARM: tegra: clock: Add debugfs clock set methodsAlex Frid
Implemented debugfs clock write mechanism (disabled by default). Expanded and fixed debugfs clock nodes to properly read clock parent and rate. Change-Id: I9f20994d0829634e09f4bccd6fce6c7c8b5bf844 Reviewed-on: http://git-master/r/15315 Tested-by: Amit Kamath <akamath@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-01-11ARM: tegra: clock: Round frequency up in clock dividersColin Cross
When picking clock divider values, the clock framework picks the closest frequency that is lower than the requested frequency. If the value from a clock divider rounds down, and then the new rounded down frequency is requested, it will get rounded down again, resulting in a frequency two steps lower than the original requested frequency. Fix the problem by rounding up when calculating the frequency coming out of a clock divider, so if that frequency is requested again, the same divider value will be picked. Change-Id: Ieaf74448f67d91aeb7ba08226e48c092d8afaa2b Signed-off-by: Colin Cross <ccross@android.com>
2010-12-29ARM: tegra: clock: Add function to set SDMMC tap delayColin Cross
The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Change-Id: Id25b7cc01fa4ec48478b60aefdf5e59bb040fbf2 Signed-off-by: Colin Cross <ccross@android.com>
2010-12-08ARM: tegra: clock: Round rate before dvfsColin Cross
Call the clock's round_rate op, if it exists, before setting dvfs rate. Ensures dvfs is set to the rate the clock will be at after the later call to set_rate. Change-Id: I4c8e85991238492adc3c37aed57c7269f3b41a2c Signed-off-by: Colin Cross <ccross@android.com>
2010-12-01ARM: tegra: Add dvfs railsColin Cross
The previous version of dvfs handled requirements between two different voltage rails by using two sets of dvfs tables, one for each rail. That method fails for vdd_aon, which must be within 170 mV of vdd_core. Instead, have each dvfs clock only set the voltage rail that it directly depends on, and add a relationship system to the voltage rails. When the voltage changes on one rail, it calls update on all the rails that depend on it. The dependent rails compare the new voltage of the original rail to their own voltage, and update their own voltage as necessary. Change-Id: I17b30a61c7c0c01e44702ab486238789abd47330 Signed-off-by: Colin Cross <ccross@android.com>
2010-12-01Revert "ARM: tegra: dvfs: Fix locking on external dvfs calls"Colin Cross
This reverts commit f58886c359db3c5056fea2d1a41d297f19e9f585. Change-Id: Ie88d8f79db9bf958fc3b9f261d74d031785161d0
2010-11-09ARM: tegra: dvfs: Fix locking on external dvfs callsColin Cross
Change-Id: I9e3a3cc8c6c4424d7f7ded22d886d51f715ec5d5 Signed-off-by: Colin Cross <ccross@android.com>
2010-11-03ARM: tegra: dvfs: Get rid of dvfs_lock and move init laterColin Cross
Get rid of dvfs_lock, replacing it with the cansleep flag on clocks. Clocks with the cansleep flag set will lock a mutex before calling into dvfs. Also does the regulator api calls during late init, after the regulators have been probed. Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I5b8bd249bd4f3ae495f2076f1e6d2bfb38737f29
2010-11-03ARM: tegra: clock: Redo clock lockingColin Cross
Give each clock its own lock, and remove all lock traversals from parent to child clocks to prevent AB-BA deadlocks. Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I0afb7d1bca956439b1a4f17bbc6748aaec706b49
2010-10-25ARM: tegra: clock: Remove dependency between "set" and debugfsColin Cross
Change-Id: I732f9428096d057e08092120c6f8c2890230a242
2010-10-25[ARM] tegra: clock: Add new dvfsColin Cross
New and improved dvfs: Registered dynamically during init Exports dvfs functions to control clocks that are not visible to the clock subsystem Supports multiple regulators per clock Fix dvfs on disabled clocks Adds /d/clock/dvfs to show current voltage requirements Change-Id: I93794a7761dccc702566e8850bb79f344ff787a2 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-25[ARM] tegra: clock: Drop old CPU dvfsColin Cross
Change-Id: Iaa5377dd1d8bf32e90deb668053c10588642fa03 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-25[ARM] tegra: clock: Initialize clocks that have no enableColin Cross
Change-Id: I136713c2a2ff9fec9fc629ae8f91709e49016618 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-25[ARM] tegra: Disable clocks left on by bootloaderColin Cross
Change-Id: I6651ab59b738787ec94f358d5789d950c3d1a563 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-21[ARM] tegra: clock: Drop debuggingColin Cross
Change-Id: Ic707eb111856eb9bdb165776d011c35d04502a9a Signed-off-by: Colin Cross <ccross@android.com>
2010-09-29[ARM] tegra: clock: Add dvfs support, bug fixes, and cleanupsColin Cross
- Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: Colin Cross <ccross@android.com>
2010-08-05[ARM] tegra: Add clock supportColin Cross
v2: fixes from Russell King: - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops additional changes: - Rename some clocks to match dev_ids - add rate propagation - add debugfs entries - add support for clock listed in clk_lookup under multiple dev_ids v3: - Replace per-clock locking with global clock lock - Autodetect clock state on init - Let clock dividers pick next lower possible frequency - Add support for clock init tables - Minor bug fixes - Fix checkpatch issues Signed-off-by: Colin Cross <ccross@android.com>
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